848 lines
23 KiB
C
848 lines
23 KiB
C
/*
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* mcp2515.c
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*
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* Created on: Dec 13, 2020
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* Author: matt
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*/
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#include "mcp2515.h"
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#include "mcp2515_consts.h"
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#include <stm32f4xx_hal.h>
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#include <string.h> //Todo: this is yucky just for the memset function
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/* Modify below items for your SPI configurations */
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extern SPI_HandleTypeDef hspi4;
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#define SPI_CAN &hspi4
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#define SPI_TIMEOUT 10
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//#define MCP2515_CS_HIGH() HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET)
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//#define MCP2515_CS_LOW() HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_RESET)
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void startSPI() {
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HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_RESET);
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}
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void endSPI() {
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HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET);
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}
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uint8_t SPI_transfer(uint8_t txByte){
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uint8_t rxByte;
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HAL_SPI_TransmitReceive(SPI_CAN, &txByte, &rxByte, 1, SPI_TIMEOUT);
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return rxByte;
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}
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void setRegister(uint8_t reg, uint8_t value)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_WRITE);
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SPI_transfer(reg);
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SPI_transfer(value);
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endSPI();
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}
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void setRegisters(uint8_t reg, uint8_t values[], uint8_t n)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_WRITE);
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SPI_transfer(reg);
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for (uint8_t i=0; i<n; i++) {
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SPI_transfer(values[i]);
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}
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// HAL_SPI_Transmit(SPI_CAN, values, n, SPI_TIMEOUT);
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endSPI();
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}
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void loadTx(uint8_t reg, uint8_t values[], uint8_t n){
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startSPI();
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//SPI_transfer(INSTRUCTION_WRITE);
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SPI_transfer(reg);
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for (uint8_t i=0; i<n; i++) {
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SPI_transfer(values[i]);
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}
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// HAL_SPI_Transmit(SPI_CAN, values, n, SPI_TIMEOUT);
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endSPI();
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}
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void modifyRegister(uint8_t reg, uint8_t mask, uint8_t data)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_BITMOD);
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SPI_transfer(reg);
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SPI_transfer(mask);
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SPI_transfer(data);
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endSPI();
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}
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uint8_t readRegister(REGISTER reg)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_READ);
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SPI_transfer(reg);
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uint8_t ret = SPI_transfer(0x00);
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endSPI();
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return ret;
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}
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void readRegisters(REGISTER reg, uint8_t values[], uint8_t n)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_READ);
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SPI_transfer(reg);
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// mcp2515 has auto-increment of address-pointer
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for (uint8_t i=0; i<n; i++) {
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values[i] = SPI_transfer(0x00);
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//HAL_SPI_Receive(&hspi4, values, n, SPI_TIMEOUT); //Todo, check if the 0x00 from above is needed
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}
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endSPI();
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}
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void readRx(REGISTER reg, uint8_t values[], uint8_t n){
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startSPI();
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SPI_transfer(reg);
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// mcp2515 has auto-increment of address-pointer
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for (uint8_t i=0; i<n; i++) {
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values[i] = SPI_transfer(0x00);
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//HAL_SPI_Receive(&hspi4, values, n, SPI_TIMEOUT); //Todo, check if the 0x00 from above is needed
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}
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endSPI();
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}
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CAN_Error setMode(CANCTRL_REQOP_MODE mode)
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{
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unsigned long endTime = HAL_GetTick() + 10;
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uint8_t modeMatch = 0;
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while (HAL_GetTick() < endTime) {
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modifyRegister(MCP_CANCTRL, CANCTRL_REQOP, mode);
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uint8_t newmode = readRegister(MCP_CANSTAT);
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newmode &= CANSTAT_OPMOD;
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modeMatch = newmode == mode;
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if (modeMatch) {
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break;
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}
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}
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return modeMatch ? ERROR_OK : ERROR_FAIL;
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}
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CAN_Error setConfigMode()
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{
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return setMode(CANCTRL_REQOP_CONFIG);
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}
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void prepareId(uint8_t *buffer, uint8_t ext, uint32_t id)
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{
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uint16_t canid = (uint16_t)(id & 0x0FFFF);
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if(ext) {
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buffer[MCP_EID0] = (uint8_t) (canid & 0xFF);
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buffer[MCP_EID8] = (uint8_t) (canid >> 8);
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canid = (uint16_t)(id >> 16);
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buffer[MCP_SIDL] = (uint8_t) (canid & 0x03);
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buffer[MCP_SIDL] += (uint8_t) ((canid & 0x1C) << 3);
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buffer[MCP_SIDL] |= TXB_EXIDE_MASK;
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buffer[MCP_SIDH] = (uint8_t) (canid >> 5);
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} else {
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buffer[MCP_SIDH] = (uint8_t) (canid >> 3);
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buffer[MCP_SIDL] = (uint8_t) ((canid & 0x07 ) << 5);
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buffer[MCP_EID0] = 0;
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buffer[MCP_EID8] = 0;
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}
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}
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uint8_t getStatus(void)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_READ_STATUS);
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uint8_t i = SPI_transfer(0x00);
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endSPI();
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return i;
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}
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CAN_Error MCP_setFilterMask(MASK mask, uint8_t ext, uint32_t ulData)
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{
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CAN_Error res = setConfigMode();
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if (res != ERROR_OK) {
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return res;
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}
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uint8_t tbufdata[4];
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prepareId(tbufdata, ext, ulData);
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REGISTER reg;
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switch (mask) {
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case MASK0: reg = MCP_RXM0SIDH; break;
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case MASK1: reg = MCP_RXM1SIDH; break;
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default:
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return ERROR_FAIL;
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}
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setRegisters(reg, tbufdata, 4);
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return ERROR_OK;
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}
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CAN_Error MCP_setFilter(RXF num, uint8_t ext, uint32_t ulData)
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{
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CAN_Error res = setConfigMode();
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if (res != ERROR_OK) {
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return res;
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}
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REGISTER reg;
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switch (num) {
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case RXF0: reg = MCP_RXF0SIDH; break;
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case RXF1: reg = MCP_RXF1SIDH; break;
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case RXF2: reg = MCP_RXF2SIDH; break;
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case RXF3: reg = MCP_RXF3SIDH; break;
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case RXF4: reg = MCP_RXF4SIDH; break;
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case RXF5: reg = MCP_RXF5SIDH; break;
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default:
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return ERROR_FAIL;
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}
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uint8_t tbufdata[4];
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prepareId(tbufdata, ext, ulData);
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setRegisters(reg, tbufdata, 4);
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return ERROR_OK;
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}
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CAN_Error MCP2515_reset(void)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_RESET);
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endSPI();
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HAL_Delay(10);
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uint8_t zeros[14];
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memset(zeros, 0, sizeof(zeros));
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setRegisters(MCP_TXB0CTRL, zeros, 14);
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setRegisters(MCP_TXB1CTRL, zeros, 14);
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setRegisters(MCP_TXB2CTRL, zeros, 14);
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setRegister(MCP_RXB0CTRL, 0);
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setRegister(MCP_RXB1CTRL, 0);
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setRegister(MCP_CANINTE, CANINTF_RX0IF | CANINTF_RX1IF | CANINTF_ERRIF | CANINTF_MERRF);
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// receives all valid messages using either Standard or Extended Identifiers that
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// meet filter criteria. RXF0 is applied for RXB0, RXF1 is applied for RXB1
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modifyRegister(MCP_RXB0CTRL,
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RXBnCTRL_RXM_MASK | RXB0CTRL_BUKT | RXB0CTRL_FILHIT_MASK,
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RXBnCTRL_RXM_STDEXT | RXB0CTRL_BUKT | RXB0CTRL_FILHIT);
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modifyRegister(MCP_RXB1CTRL,
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RXBnCTRL_RXM_MASK | RXB1CTRL_FILHIT_MASK,
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RXBnCTRL_RXM_STDEXT | RXB1CTRL_FILHIT);
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// clear filters and masks
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// do not filter any standard frames for RXF0 used by RXB0
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// do not filter any extended frames for RXF1 used by RXB1
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RXF filters[] = {RXF0, RXF1, RXF2, RXF3, RXF4, RXF5};
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for (uint8_t i=0; i<6; i++) {
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uint8_t ext = (i == 1);
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CAN_Error result = MCP_setFilter(filters[i], ext, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}
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MASK masks[] = {MASK0, MASK1};
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for (int i=0; i<2; i++) {
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CAN_Error result = MCP_setFilterMask(masks[i], 1, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}
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return ERROR_OK;
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}
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CAN_Error MCP_reset(void)
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{
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startSPI();
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SPI_transfer(INSTRUCTION_RESET);
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endSPI();
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HAL_Delay(10);
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uint8_t zeros[14];
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memset(zeros, 0, sizeof(zeros));
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setRegisters(MCP_TXB0CTRL, zeros, 14);
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setRegisters(MCP_TXB1CTRL, zeros, 14);
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setRegisters(MCP_TXB2CTRL, zeros, 14);
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setRegister(MCP_RXB0CTRL, 0);
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setRegister(MCP_RXB1CTRL, 0);
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setRegister(MCP_CANINTE, CANINTF_RX0IF | CANINTF_RX1IF | CANINTF_ERRIF | CANINTF_MERRF);
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// receives all valid messages using either Standard or Extended Identifiers that
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// meet filter criteria. RXF0 is applied for RXB0, RXF1 is applied for RXB1
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modifyRegister(MCP_RXB0CTRL,
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RXBnCTRL_RXM_MASK | RXB0CTRL_BUKT | RXB0CTRL_FILHIT_MASK,
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RXBnCTRL_RXM_STDEXT | RXB0CTRL_BUKT | RXB0CTRL_FILHIT);
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modifyRegister(MCP_RXB1CTRL,
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RXBnCTRL_RXM_MASK | RXB1CTRL_FILHIT_MASK,
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RXBnCTRL_RXM_STDEXT | RXB1CTRL_FILHIT);
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// clear filters and masks
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// do not filter any standard frames for RXF0 used by RXB0
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// do not filter any extended frames for RXF1 used by RXB1
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RXF filters[] = {RXF0, RXF1, RXF2, RXF3, RXF4, RXF5};
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for (int i=0; i<6; i++) {
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uint8_t ext = (i == 1);
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CAN_Error result = MCP_setFilter(filters[i], ext, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}
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MASK masks[] = {MASK0, MASK1};
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for (int i=0; i<2; i++) {
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CAN_Error result = MCP_setFilterMask(masks[i], 1, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}
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return ERROR_OK;
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}
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CAN_Error MCP_setListenOnlyMode()
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{
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return setMode(CANCTRL_REQOP_LISTENONLY);
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}
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CAN_Error MCP_setSleepMode()
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{
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return setMode(CANCTRL_REQOP_SLEEP);
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}
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CAN_Error MCP_setLoopbackMode()
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{
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return setMode(CANCTRL_REQOP_LOOPBACK);
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}
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CAN_Error MCP_setNormalMode()
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{
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return setMode(CANCTRL_REQOP_NORMAL);
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}
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CAN_Error MCP_setBitrateClock(CAN_SPEED canSpeed, CAN_CLOCK canClock)
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{
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CAN_Error error = setConfigMode();
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if (error != ERROR_OK) {
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return error;
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}
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uint8_t set, cfg1, cfg2, cfg3;
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set = 1;
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switch (canClock)
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{
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case (MCP_8MHZ):
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switch (canSpeed)
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{
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case (CAN_5KBPS): // 5KBPS
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cfg1 = MCP_8MHz_5kBPS_CFG1;
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cfg2 = MCP_8MHz_5kBPS_CFG2;
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cfg3 = MCP_8MHz_5kBPS_CFG3;
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break;
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case (CAN_10KBPS): // 10KBPS
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cfg1 = MCP_8MHz_10kBPS_CFG1;
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cfg2 = MCP_8MHz_10kBPS_CFG2;
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cfg3 = MCP_8MHz_10kBPS_CFG3;
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break;
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case (CAN_20KBPS): // 20KBPS
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cfg1 = MCP_8MHz_20kBPS_CFG1;
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cfg2 = MCP_8MHz_20kBPS_CFG2;
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cfg3 = MCP_8MHz_20kBPS_CFG3;
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break;
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case (CAN_31K25BPS): // 31.25KBPS
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cfg1 = MCP_8MHz_31k25BPS_CFG1;
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cfg2 = MCP_8MHz_31k25BPS_CFG2;
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cfg3 = MCP_8MHz_31k25BPS_CFG3;
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break;
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case (CAN_33KBPS): // 33.333KBPS
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cfg1 = MCP_8MHz_33k3BPS_CFG1;
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cfg2 = MCP_8MHz_33k3BPS_CFG2;
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cfg3 = MCP_8MHz_33k3BPS_CFG3;
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break;
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case (CAN_40KBPS): // 40Kbps
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cfg1 = MCP_8MHz_40kBPS_CFG1;
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cfg2 = MCP_8MHz_40kBPS_CFG2;
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cfg3 = MCP_8MHz_40kBPS_CFG3;
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break;
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case (CAN_50KBPS): // 50Kbps
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cfg1 = MCP_8MHz_50kBPS_CFG1;
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cfg2 = MCP_8MHz_50kBPS_CFG2;
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cfg3 = MCP_8MHz_50kBPS_CFG3;
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break;
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case (CAN_80KBPS): // 80Kbps
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cfg1 = MCP_8MHz_80kBPS_CFG1;
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cfg2 = MCP_8MHz_80kBPS_CFG2;
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cfg3 = MCP_8MHz_80kBPS_CFG3;
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break;
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case (CAN_100KBPS): // 100Kbps
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cfg1 = MCP_8MHz_100kBPS_CFG1;
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cfg2 = MCP_8MHz_100kBPS_CFG2;
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cfg3 = MCP_8MHz_100kBPS_CFG3;
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break;
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case (CAN_125KBPS): // 125Kbps
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cfg1 = MCP_8MHz_125kBPS_CFG1;
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cfg2 = MCP_8MHz_125kBPS_CFG2;
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cfg3 = MCP_8MHz_125kBPS_CFG3;
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break;
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case (CAN_200KBPS): // 200Kbps
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cfg1 = MCP_8MHz_200kBPS_CFG1;
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cfg2 = MCP_8MHz_200kBPS_CFG2;
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cfg3 = MCP_8MHz_200kBPS_CFG3;
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break;
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case (CAN_250KBPS): // 250Kbps
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cfg1 = MCP_8MHz_250kBPS_CFG1;
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cfg2 = MCP_8MHz_250kBPS_CFG2;
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cfg3 = MCP_8MHz_250kBPS_CFG3;
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break;
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case (CAN_500KBPS): // 500Kbps
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cfg1 = MCP_8MHz_500kBPS_CFG1;
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cfg2 = MCP_8MHz_500kBPS_CFG2;
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cfg3 = MCP_8MHz_500kBPS_CFG3;
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break;
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case (CAN_1000KBPS): // 1Mbps
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cfg1 = MCP_8MHz_1000kBPS_CFG1;
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cfg2 = MCP_8MHz_1000kBPS_CFG2;
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cfg3 = MCP_8MHz_1000kBPS_CFG3;
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break;
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default:
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set = 0;
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break;
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}
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break;
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case (MCP_16MHZ):
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switch (canSpeed)
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{
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case (CAN_5KBPS): // 5Kbps
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cfg1 = MCP_16MHz_5kBPS_CFG1;
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cfg2 = MCP_16MHz_5kBPS_CFG2;
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cfg3 = MCP_16MHz_5kBPS_CFG3;
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break;
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case (CAN_10KBPS): // 10Kbps
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cfg1 = MCP_16MHz_10kBPS_CFG1;
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cfg2 = MCP_16MHz_10kBPS_CFG2;
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cfg3 = MCP_16MHz_10kBPS_CFG3;
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break;
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case (CAN_20KBPS): // 20Kbps
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cfg1 = MCP_16MHz_20kBPS_CFG1;
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cfg2 = MCP_16MHz_20kBPS_CFG2;
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cfg3 = MCP_16MHz_20kBPS_CFG3;
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break;
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case (CAN_33KBPS): // 33.333Kbps
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cfg1 = MCP_16MHz_33k3BPS_CFG1;
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cfg2 = MCP_16MHz_33k3BPS_CFG2;
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cfg3 = MCP_16MHz_33k3BPS_CFG3;
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break;
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case (CAN_40KBPS): // 40Kbps
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cfg1 = MCP_16MHz_40kBPS_CFG1;
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cfg2 = MCP_16MHz_40kBPS_CFG2;
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cfg3 = MCP_16MHz_40kBPS_CFG3;
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break;
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case (CAN_50KBPS): // 50Kbps
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cfg1 = MCP_16MHz_50kBPS_CFG1;
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cfg2 = MCP_16MHz_50kBPS_CFG2;
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cfg3 = MCP_16MHz_50kBPS_CFG3;
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break;
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case (CAN_80KBPS): // 80Kbps
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cfg1 = MCP_16MHz_80kBPS_CFG1;
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cfg2 = MCP_16MHz_80kBPS_CFG2;
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cfg3 = MCP_16MHz_80kBPS_CFG3;
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break;
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case (CAN_83K3BPS): // 83.333Kbps
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cfg1 = MCP_16MHz_83k3BPS_CFG1;
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cfg2 = MCP_16MHz_83k3BPS_CFG2;
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cfg3 = MCP_16MHz_83k3BPS_CFG3;
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break;
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case (CAN_100KBPS): // 100Kbps
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cfg1 = MCP_16MHz_100kBPS_CFG1;
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cfg2 = MCP_16MHz_100kBPS_CFG2;
|
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cfg3 = MCP_16MHz_100kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_125KBPS): // 125Kbps
|
|
cfg1 = MCP_16MHz_125kBPS_CFG1;
|
|
cfg2 = MCP_16MHz_125kBPS_CFG2;
|
|
cfg3 = MCP_16MHz_125kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_200KBPS): // 200Kbps
|
|
cfg1 = MCP_16MHz_200kBPS_CFG1;
|
|
cfg2 = MCP_16MHz_200kBPS_CFG2;
|
|
cfg3 = MCP_16MHz_200kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_250KBPS): // 250Kbps
|
|
cfg1 = MCP_16MHz_250kBPS_CFG1;
|
|
cfg2 = MCP_16MHz_250kBPS_CFG2;
|
|
cfg3 = MCP_16MHz_250kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_500KBPS): // 500Kbps
|
|
cfg1 = MCP_16MHz_500kBPS_CFG1;
|
|
cfg2 = MCP_16MHz_500kBPS_CFG2;
|
|
cfg3 = MCP_16MHz_500kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_1000KBPS): // 1Mbps
|
|
cfg1 = MCP_16MHz_1000kBPS_CFG1;
|
|
cfg2 = MCP_16MHz_1000kBPS_CFG2;
|
|
cfg3 = MCP_16MHz_1000kBPS_CFG3;
|
|
break;
|
|
|
|
default:
|
|
set = 0;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case (MCP_20MHZ):
|
|
switch (canSpeed)
|
|
{
|
|
case (CAN_33KBPS): // 33.333Kbps
|
|
cfg1 = MCP_20MHz_33k3BPS_CFG1;
|
|
cfg2 = MCP_20MHz_33k3BPS_CFG2;
|
|
cfg3 = MCP_20MHz_33k3BPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_40KBPS): // 40Kbps
|
|
cfg1 = MCP_20MHz_40kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_40kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_40kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_50KBPS): // 50Kbps
|
|
cfg1 = MCP_20MHz_50kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_50kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_50kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_80KBPS): // 80Kbps
|
|
cfg1 = MCP_20MHz_80kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_80kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_80kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_83K3BPS): // 83.333Kbps
|
|
cfg1 = MCP_20MHz_83k3BPS_CFG1;
|
|
cfg2 = MCP_20MHz_83k3BPS_CFG2;
|
|
cfg3 = MCP_20MHz_83k3BPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_100KBPS): // 100Kbps
|
|
cfg1 = MCP_20MHz_100kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_100kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_100kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_125KBPS): // 125Kbps
|
|
cfg1 = MCP_20MHz_125kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_125kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_125kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_200KBPS): // 200Kbps
|
|
cfg1 = MCP_20MHz_200kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_200kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_200kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_250KBPS): // 250Kbps
|
|
cfg1 = MCP_20MHz_250kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_250kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_250kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_500KBPS): // 500Kbps
|
|
cfg1 = MCP_20MHz_500kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_500kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_500kBPS_CFG3;
|
|
break;
|
|
|
|
case (CAN_1000KBPS): // 1Mbps
|
|
cfg1 = MCP_20MHz_1000kBPS_CFG1;
|
|
cfg2 = MCP_20MHz_1000kBPS_CFG2;
|
|
cfg3 = MCP_20MHz_1000kBPS_CFG3;
|
|
break;
|
|
|
|
default:
|
|
set = 0;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
set = 0;
|
|
break;
|
|
}
|
|
|
|
if (set) {
|
|
setRegister(MCP_CNF1, cfg1);
|
|
setRegister(MCP_CNF2, cfg2);
|
|
setRegister(MCP_CNF3, cfg3);
|
|
return ERROR_OK;
|
|
}
|
|
else {
|
|
return ERROR_FAIL;
|
|
}
|
|
}
|
|
|
|
CAN_Error MCP_setBitrate( CAN_SPEED canSpeed)
|
|
{
|
|
return MCP_setBitrateClock(canSpeed, MCP_16MHZ);
|
|
}
|
|
|
|
|
|
void MCP_RequestToSend(uint8_t instruction)
|
|
{
|
|
startSPI();
|
|
SPI_transfer(instruction);
|
|
endSPI();
|
|
}
|
|
|
|
CAN_Error MCP_sendMessageTo(TXBn txbn, can_frame *frame)
|
|
//TXBm is just 0,1,2 for txbox number
|
|
{
|
|
if (frame->can_dlc > CAN_MAX_DLEN) {
|
|
return ERROR_FAILTX;
|
|
}
|
|
|
|
//Todo, fix these magic numbers, but not with something as awful as the og arduino library
|
|
uint8_t load_addr = (2 * txbn) | 0x40;
|
|
|
|
uint8_t rts_addr = (1 << txbn) | 0x80;
|
|
|
|
uint8_t data[13];
|
|
|
|
uint8_t ext = !!(frame->can_id & CAN_EFF_FLAG);
|
|
uint8_t rtr = !!(frame->can_id & CAN_RTR_FLAG);
|
|
uint32_t id = (frame->can_id & (ext ? CAN_EFF_MASK : CAN_SFF_MASK));
|
|
|
|
prepareId(data, ext, id);
|
|
|
|
data[MCP_DLC] = rtr ? (frame->can_dlc | RTR_MASK) : frame->can_dlc;
|
|
|
|
for(int i = 0; i < frame->can_dlc; i++){
|
|
data[MCP_DATA+i]=frame->data[i];
|
|
}
|
|
|
|
// memcpy(&data[MCP_DATA], frame->data, frame->can_dlc);
|
|
|
|
loadTx(load_addr, data, 5 + frame->can_dlc);
|
|
//setRegisters(load_addr, data, 5 + frame->can_dlc);
|
|
|
|
//modifyRegister(txbuf->CTRL, TXB_TXREQ, TXB_TXREQ);
|
|
//modifyRegister(rts_addr, TXB_TXREQ, TXB_TXREQ);
|
|
MCP_RequestToSend(rts_addr);
|
|
//setRegister(rts_addr, TXB_TXREQ);
|
|
|
|
uint8_t ctrl = readRegister(rts_addr);
|
|
if ((ctrl & (TXB_ABTF | TXB_MLOA | TXB_TXERR)) != 0) {
|
|
return ERROR_FAILTX;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
CAN_Error MCP_sendMessage(can_frame *frame)
|
|
{
|
|
if (frame->can_dlc > CAN_MAX_DLEN) {
|
|
return ERROR_FAILTX;
|
|
}
|
|
|
|
|
|
for (uint8_t i=0; i<N_TXBUFFERS; i++) {
|
|
uint8_t ctrlval = readRegister((i+3)<<4);
|
|
if ( (ctrlval & TXB_TXREQ) == 0 ) {
|
|
return MCP_sendMessageTo(i, frame);
|
|
}
|
|
}
|
|
|
|
return ERROR_ALLTXBUSY;
|
|
}
|
|
|
|
CAN_Error MCP_readMessageFrom(RXBn rxbn, can_frame *frame)
|
|
{
|
|
|
|
|
|
uint8_t readCommand = (rxbn << 2) | 0x90;
|
|
|
|
rx_reg_t rxReg;
|
|
|
|
readRx(readCommand, rxReg.rx_reg_array, sizeof(rxReg.rx_reg_array));
|
|
|
|
uint32_t id = (rxReg.rx_reg_array[MCP_SIDH]<<3) + (rxReg.rx_reg_array[MCP_SIDL]>>5);
|
|
|
|
if ( (rxReg.rx_reg_array[MCP_SIDL] & TXB_EXIDE_MASK) == TXB_EXIDE_MASK ) {
|
|
id = (id<<2) + (rxReg.rx_reg_array[MCP_SIDL] & 0x03);
|
|
id = (id<<8) + rxReg.rx_reg_array[MCP_EID8];
|
|
id = (id<<8) + rxReg.rx_reg_array[MCP_EID0];
|
|
id |= CAN_EFF_FLAG;
|
|
}
|
|
|
|
uint8_t dlc = (rxReg.rx_reg_array[MCP_DLC] & DLC_MASK);
|
|
if (dlc > CAN_MAX_DLEN) {
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
|
|
//0x60 or 0x70
|
|
uint8_t ctrl = readRegister((rxbn + 6) << 4);
|
|
if (ctrl & RXBnCTRL_RTR) {
|
|
id |= CAN_RTR_FLAG;
|
|
}
|
|
|
|
frame->can_id = id;
|
|
frame->can_dlc = dlc;
|
|
|
|
frame->data[0] = rxReg.RXBnD0;
|
|
frame->data[1] = rxReg.RXBnD1;
|
|
frame->data[2] = rxReg.RXBnD2;
|
|
frame->data[3] = rxReg.RXBnD3;
|
|
frame->data[4] = rxReg.RXBnD4;
|
|
frame->data[5] = rxReg.RXBnD5;
|
|
frame->data[6] = rxReg.RXBnD6;
|
|
frame->data[7] = rxReg.RXBnD7;
|
|
|
|
|
|
//Clear the inbox interrupt, 0x1 or 0x2
|
|
modifyRegister(MCP_CANINTF, rxbn + 1, 0);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
CAN_Error MCP_readMessage(can_frame *frame)
|
|
{
|
|
CAN_Error rc;
|
|
uint8_t stat = getStatus();
|
|
|
|
if ( stat & STAT_RX0IF ) {
|
|
rc = MCP_readMessageFrom(RXB0, frame);
|
|
} else if ( stat & STAT_RX1IF ) {
|
|
rc = MCP_readMessageFrom(RXB1, frame);
|
|
} else {
|
|
rc = ERROR_NOMSG;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
uint8_t MCP_checkReceive(void)
|
|
{
|
|
uint8_t res = getStatus();
|
|
if ( res & STAT_RXIF_MASK ) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
uint8_t MCP_getErrorFlags(void)
|
|
{
|
|
return readRegister(MCP_EFLG);
|
|
}
|
|
|
|
uint8_t MCP_checkError(void)
|
|
{
|
|
uint8_t eflg = MCP_getErrorFlags();
|
|
|
|
if ( eflg & EFLG_ERRORMASK ) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
void MCP_clearRXnOVRFlags(void)
|
|
{
|
|
modifyRegister(MCP_EFLG, EFLG_RX0OVR | EFLG_RX1OVR, 0);
|
|
}
|
|
|
|
uint8_t MCP_getInterrupts(void)
|
|
{
|
|
return readRegister(MCP_CANINTF);
|
|
}
|
|
|
|
void MCP_clearInterrupts(void)
|
|
{
|
|
setRegister(MCP_CANINTF, 0);
|
|
}
|
|
|
|
uint8_t MCP_getInterruptMask(void)
|
|
{
|
|
return readRegister(MCP_CANINTE);
|
|
}
|
|
|
|
void MCP_clearTXInterrupts(void)
|
|
{
|
|
modifyRegister(MCP_CANINTF, (CANINTF_TX0IF | CANINTF_TX1IF | CANINTF_TX2IF), 0);
|
|
}
|
|
|
|
void MCP_clearRXnOVR(void)
|
|
{
|
|
uint8_t eflg = MCP_getErrorFlags();
|
|
if (eflg != 0) {
|
|
MCP_clearRXnOVRFlags();
|
|
MCP_clearInterrupts();
|
|
//modifyRegister(MCP_CANINTF, CANINTF_ERRIF, 0);
|
|
}
|
|
|
|
}
|
|
|
|
void MCP_clearMERR()
|
|
{
|
|
//modifyRegister(MCP_EFLG, EFLG_RX0OVR | EFLG_RX1OVR, 0);
|
|
//clearInterrupts();
|
|
modifyRegister(MCP_CANINTF, CANINTF_MERRF, 0);
|
|
}
|
|
|
|
void MCP_clearERRIF()
|
|
{
|
|
//modifyRegister(MCP_EFLG, EFLG_RX0OVR | EFLG_RX1OVR, 0);
|
|
//clearInterrupts();
|
|
modifyRegister(MCP_CANINTF, CANINTF_ERRIF, 0);
|
|
}
|
|
|