diff --git a/NTP/.cproject b/project/.cproject similarity index 100% rename from NTP/.cproject rename to project/.cproject diff --git a/NTP/.mxproject b/project/.mxproject similarity index 100% rename from NTP/.mxproject rename to project/.mxproject diff --git a/NTP/.project b/project/.project similarity index 100% rename from NTP/.project rename to project/.project diff --git a/project/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/project/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..98a69fc --- /dev/null +++ b/project/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/project/.settings/language.settings.xml b/project/.settings/language.settings.xml new file mode 100644 index 0000000..0a72a86 --- /dev/null +++ b/project/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/project/.settings/stm32cubeide.project.prefs b/project/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..ae0181b --- /dev/null +++ b/project/.settings/stm32cubeide.project.prefs @@ -0,0 +1,5 @@ +635E684B79701B039C64EA45C3F84D30=D73B2544A5411CFDF9F73E2F2C7DF7FD +66BE74F758C12D739921AEA421D593D3=0 +8DF89ED150041C4CBC7CB9A9CAA90856=0F24C5AAAF95F07C820716AE3D966203 +DC22A860405A8BF2F2C095E5B6529F12=0F24C5AAAF95F07C820716AE3D966203 +eclipse.preferences.version=1 diff --git a/project/.vscode/settings.json b/project/.vscode/settings.json new file mode 100644 index 0000000..4de70c1 --- /dev/null +++ b/project/.vscode/settings.json @@ -0,0 +1,11 @@ +{ + "files.associations": { + "ntp.h": "c", + "stdint.h": "c", + "math.h": "c", + "stdbool.h": "c", + "stdint-gcc.h": "c", + "main.h": "c", + "ds3231.h": "c" + } +} \ No newline at end of file diff --git a/NTP/Core/Inc/FreeRTOSConfig.h b/project/Core/Inc/FreeRTOSConfig.h similarity index 100% rename from NTP/Core/Inc/FreeRTOSConfig.h rename to project/Core/Inc/FreeRTOSConfig.h diff --git a/NTP/Core/Inc/NTP.h b/project/Core/Inc/NTP.h similarity index 100% rename from NTP/Core/Inc/NTP.h rename to project/Core/Inc/NTP.h diff --git a/NTP/Core/Inc/RTC.h b/project/Core/Inc/RTC.h similarity index 100% rename from NTP/Core/Inc/RTC.h rename to project/Core/Inc/RTC.h diff --git a/NTP/Core/Inc/Time.h b/project/Core/Inc/Time.h similarity index 100% rename from NTP/Core/Inc/Time.h rename to project/Core/Inc/Time.h diff --git a/NTP/Core/Inc/clock.h b/project/Core/Inc/clock.h similarity index 100% rename from NTP/Core/Inc/clock.h rename to project/Core/Inc/clock.h diff --git a/NTP/Core/Inc/debug.h b/project/Core/Inc/debug.h similarity index 100% rename from NTP/Core/Inc/debug.h rename to project/Core/Inc/debug.h diff --git a/NTP/Core/Inc/ds3231_for_stm32_hal.h b/project/Core/Inc/ds3231_for_stm32_hal.h similarity index 100% rename from NTP/Core/Inc/ds3231_for_stm32_hal.h rename to project/Core/Inc/ds3231_for_stm32_hal.h diff --git a/NTP/Core/Inc/main.h b/project/Core/Inc/main.h similarity index 100% rename from NTP/Core/Inc/main.h rename to project/Core/Inc/main.h diff --git a/NTP/Core/Inc/stm32f7xx_hal_conf.h b/project/Core/Inc/stm32f7xx_hal_conf.h similarity index 100% rename from NTP/Core/Inc/stm32f7xx_hal_conf.h rename to project/Core/Inc/stm32f7xx_hal_conf.h diff --git a/NTP/Core/Inc/stm32f7xx_it.h b/project/Core/Inc/stm32f7xx_it.h similarity index 100% rename from NTP/Core/Inc/stm32f7xx_it.h rename to project/Core/Inc/stm32f7xx_it.h diff --git a/NTP/Core/Src/NTP.c b/project/Core/Src/NTP.c similarity index 100% rename from NTP/Core/Src/NTP.c rename to project/Core/Src/NTP.c diff --git a/NTP/Core/Src/RTC.c b/project/Core/Src/RTC.c similarity index 100% rename from NTP/Core/Src/RTC.c rename to project/Core/Src/RTC.c diff --git a/NTP/Core/Src/Time.c b/project/Core/Src/Time.c similarity index 100% rename from NTP/Core/Src/Time.c rename to project/Core/Src/Time.c diff --git a/NTP/Core/Src/app_main.c b/project/Core/Src/app_main.c similarity index 100% rename from NTP/Core/Src/app_main.c rename to project/Core/Src/app_main.c diff --git a/NTP/Core/Src/clock.c b/project/Core/Src/clock.c similarity index 100% rename from NTP/Core/Src/clock.c rename to project/Core/Src/clock.c diff --git a/NTP/Core/Src/debug.c b/project/Core/Src/debug.c similarity index 100% rename from NTP/Core/Src/debug.c rename to project/Core/Src/debug.c diff --git a/NTP/Core/Src/ds3231_for_stm32_hal.c b/project/Core/Src/ds3231_for_stm32_hal.c similarity index 100% rename from NTP/Core/Src/ds3231_for_stm32_hal.c rename to project/Core/Src/ds3231_for_stm32_hal.c diff --git a/NTP/Core/Src/freertos.c b/project/Core/Src/freertos.c similarity index 100% rename from NTP/Core/Src/freertos.c rename to project/Core/Src/freertos.c diff --git a/NTP/Core/Src/main.c b/project/Core/Src/main.c similarity index 100% rename from NTP/Core/Src/main.c rename to project/Core/Src/main.c diff --git a/NTP/Core/Src/stm32f7xx_hal_msp.c b/project/Core/Src/stm32f7xx_hal_msp.c similarity index 100% rename from NTP/Core/Src/stm32f7xx_hal_msp.c rename to project/Core/Src/stm32f7xx_hal_msp.c diff --git a/NTP/Core/Src/stm32f7xx_hal_timebase_tim.c b/project/Core/Src/stm32f7xx_hal_timebase_tim.c similarity index 100% rename from NTP/Core/Src/stm32f7xx_hal_timebase_tim.c rename to project/Core/Src/stm32f7xx_hal_timebase_tim.c diff --git a/NTP/Core/Src/stm32f7xx_it.c b/project/Core/Src/stm32f7xx_it.c similarity index 100% rename from NTP/Core/Src/stm32f7xx_it.c rename to project/Core/Src/stm32f7xx_it.c diff --git a/NTP/Core/Src/syscalls.c b/project/Core/Src/syscalls.c similarity index 100% rename from NTP/Core/Src/syscalls.c rename to project/Core/Src/syscalls.c diff --git a/NTP/Core/Src/sysmem.c b/project/Core/Src/sysmem.c similarity index 100% rename from NTP/Core/Src/sysmem.c rename to project/Core/Src/sysmem.c diff --git a/NTP/Core/Src/system_stm32f7xx.c b/project/Core/Src/system_stm32f7xx.c similarity index 100% rename from NTP/Core/Src/system_stm32f7xx.c rename to project/Core/Src/system_stm32f7xx.c diff --git a/NTP/Core/Startup/startup_stm32f746nghx.s b/project/Core/Startup/startup_stm32f746nghx.s similarity index 100% rename from NTP/Core/Startup/startup_stm32f746nghx.s rename to project/Core/Startup/startup_stm32f746nghx.s diff --git a/project/Debug/Core/Src/NTP.cyclo b/project/Debug/Core/Src/NTP.cyclo new file mode 100644 index 0000000..2034514 --- /dev/null +++ b/project/Debug/Core/Src/NTP.cyclo @@ -0,0 +1,3 @@ +NTP.c:11:10:NTPToEpochUnix 9 +NTP.c:92:6:NTP_DNS_Callback 3 +NTP.c:111:6:NTP_RECV_CALLBACK 4 diff --git a/project/Debug/Core/Src/NTP.d b/project/Debug/Core/Src/NTP.d new file mode 100644 index 0000000..3a4f1d0 --- /dev/null +++ b/project/Debug/Core/Src/NTP.d @@ -0,0 +1,204 @@ +Core/Src/NTP.o: ../Core/Src/NTP.c ../Core/Inc/NTP.h ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../LWIP/Target/ethernetif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Core/Inc/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h +../Core/Inc/NTP.h: +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: 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+../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../LWIP/Target/ethernetif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Core/Inc/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: diff --git a/project/Debug/Core/Src/NTP.o b/project/Debug/Core/Src/NTP.o new file mode 100644 index 0000000..aa26cd5 Binary files /dev/null and b/project/Debug/Core/Src/NTP.o differ diff --git a/project/Debug/Core/Src/NTP.su b/project/Debug/Core/Src/NTP.su new file mode 100644 index 0000000..371c32a --- /dev/null +++ b/project/Debug/Core/Src/NTP.su @@ -0,0 +1,3 @@ +../Core/Src/NTP.c:11:10:NTPToEpochUnix 32 static +../Core/Src/NTP.c:92:6:NTP_DNS_Callback 24 static +../Core/Src/NTP.c:111:6:NTP_RECV_CALLBACK 32 static diff --git a/project/Debug/Core/Src/RTC.cyclo b/project/Debug/Core/Src/RTC.cyclo new file mode 100644 index 0000000..058544a --- /dev/null +++ b/project/Debug/Core/Src/RTC.cyclo @@ -0,0 +1,4 @@ +RTC.c:5:6:Set_Time 3 +RTC.c:19:6:Get_Time 1 +RTC.c:27:6:Ts_To_RTC 1 +RTC.c:37:6:RTC_To_Ts 1 diff --git a/project/Debug/Core/Src/RTC.d b/project/Debug/Core/Src/RTC.d new file mode 100644 index 0000000..75b14c8 --- /dev/null +++ b/project/Debug/Core/Src/RTC.d @@ -0,0 +1,95 @@ +Core/Src/RTC.o: ../Core/Src/RTC.c ../Core/Inc/RTC.h ../Core/Inc/debug.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h ../Core/Inc/Time.h +../Core/Inc/RTC.h: +../Core/Inc/debug.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Core/Inc/Time.h: diff --git a/project/Debug/Core/Src/RTC.o b/project/Debug/Core/Src/RTC.o new file mode 100644 index 0000000..519a4ec Binary files /dev/null and b/project/Debug/Core/Src/RTC.o differ diff --git a/project/Debug/Core/Src/RTC.su b/project/Debug/Core/Src/RTC.su new file mode 100644 index 0000000..ff8fe81 --- /dev/null +++ b/project/Debug/Core/Src/RTC.su @@ -0,0 +1,4 @@ +../Core/Src/RTC.c:5:6:Set_Time 8 static +../Core/Src/RTC.c:19:6:Get_Time 16 static +../Core/Src/RTC.c:27:6:Ts_To_RTC 24 static +../Core/Src/RTC.c:37:6:RTC_To_Ts 24 static diff --git a/project/Debug/Core/Src/Time.cyclo b/project/Debug/Core/Src/Time.cyclo new file mode 100644 index 0000000..4afc0da --- /dev/null +++ b/project/Debug/Core/Src/Time.cyclo @@ -0,0 +1,5 @@ +Time.c:17:9:IsDST 10 +Time.c:64:6:breakTime 15 +Time.c:140:10:makeTime 13 +Time.c:192:6:toTimeZone 2 +Time.c:208:6:TimeDiff 1 diff --git a/project/Debug/Core/Src/Time.d b/project/Debug/Core/Src/Time.d new file mode 100644 index 0000000..3ac84ad --- /dev/null +++ b/project/Debug/Core/Src/Time.d @@ -0,0 +1,94 @@ +Core/Src/Time.o: ../Core/Src/Time.c ../Core/Inc/Time.h \ + ../Core/Inc/debug.h ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Core/Inc/Time.h: +../Core/Inc/debug.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Core/Src/Time.o b/project/Debug/Core/Src/Time.o new file mode 100644 index 0000000..f94a2b5 Binary files /dev/null and b/project/Debug/Core/Src/Time.o differ diff --git a/project/Debug/Core/Src/Time.su b/project/Debug/Core/Src/Time.su new file mode 100644 index 0000000..97bff99 --- /dev/null +++ b/project/Debug/Core/Src/Time.su @@ -0,0 +1,5 @@ +../Core/Src/Time.c:17:9:IsDST 40 static +../Core/Src/Time.c:64:6:breakTime 48 static +../Core/Src/Time.c:140:10:makeTime 40 static +../Core/Src/Time.c:192:6:toTimeZone 32 static +../Core/Src/Time.c:208:6:TimeDiff 32 static diff --git a/project/Debug/Core/Src/app_main.cyclo b/project/Debug/Core/Src/app_main.cyclo new file mode 100644 index 0000000..977c3a2 --- /dev/null +++ b/project/Debug/Core/Src/app_main.cyclo @@ -0,0 +1 @@ +app_main.c:14:6:app_main 6 diff --git a/project/Debug/Core/Src/app_main.d b/project/Debug/Core/Src/app_main.d new file mode 100644 index 0000000..3553988 --- /dev/null +++ b/project/Debug/Core/Src/app_main.d @@ -0,0 +1,226 @@ +Core/Src/app_main.o: ../Core/Src/app_main.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + 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../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../LWIP/Target/ethernetif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Core/Inc/NTP.h ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Core/Inc/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Core/Inc/Time.h ../Core/Inc/RTC.h ../Core/Inc/ds3231_for_stm32_hal.h \ + ../Core/Inc/main.h ../Core/Inc/clock.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h \ + ../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h \ + ../Core/Inc/debug.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../LWIP/Target/ethernetif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Core/Inc/NTP.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Core/Inc/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Core/Inc/Time.h: +../Core/Inc/RTC.h: +../Core/Inc/ds3231_for_stm32_hal.h: +../Core/Inc/main.h: +../Core/Inc/clock.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h: +../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h: +../Core/Inc/debug.h: diff --git a/project/Debug/Core/Src/app_main.o b/project/Debug/Core/Src/app_main.o new file mode 100644 index 0000000..cd897b0 Binary files /dev/null and b/project/Debug/Core/Src/app_main.o differ diff --git a/project/Debug/Core/Src/app_main.su b/project/Debug/Core/Src/app_main.su new file mode 100644 index 0000000..a9004ff --- /dev/null +++ b/project/Debug/Core/Src/app_main.su @@ -0,0 +1 @@ +../Core/Src/app_main.c:14:6:app_main 96 static diff --git a/project/Debug/Core/Src/clock.cyclo b/project/Debug/Core/Src/clock.cyclo new file mode 100644 index 0000000..eecd664 --- /dev/null +++ b/project/Debug/Core/Src/clock.cyclo @@ -0,0 +1,3 @@ +clock.c:26:6:Clock_Draw_Outline 3 +clock.c:61:6:Clock_Draw_Hands 1 +clock.c:85:6:Clock_Write_Date 1 diff --git a/project/Debug/Core/Src/clock.d b/project/Debug/Core/Src/clock.d new file mode 100644 index 0000000..8878dbe --- /dev/null +++ b/project/Debug/Core/Src/clock.d @@ -0,0 +1,88 @@ +Core/Src/clock.o: ../Core/Src/clock.c ../Core/Inc/clock.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h \ + ../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h +../Core/Inc/clock.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h: +../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h: diff --git a/project/Debug/Core/Src/clock.o b/project/Debug/Core/Src/clock.o new file mode 100644 index 0000000..ef7be18 Binary files /dev/null and b/project/Debug/Core/Src/clock.o differ diff --git a/project/Debug/Core/Src/clock.su b/project/Debug/Core/Src/clock.su new file mode 100644 index 0000000..64d2880 --- /dev/null +++ b/project/Debug/Core/Src/clock.su @@ -0,0 +1,3 @@ +../Core/Src/clock.c:26:6:Clock_Draw_Outline 64 static +../Core/Src/clock.c:61:6:Clock_Draw_Hands 56 static +../Core/Src/clock.c:85:6:Clock_Write_Date 40 static diff --git a/project/Debug/Core/Src/debug.cyclo b/project/Debug/Core/Src/debug.cyclo new file mode 100644 index 0000000..0f59c10 --- /dev/null +++ b/project/Debug/Core/Src/debug.cyclo @@ -0,0 +1,2 @@ +debug.c:11:5:_write 5 +debug.c:35:5:_read 3 diff --git a/project/Debug/Core/Src/debug.d b/project/Debug/Core/Src/debug.d new file mode 100644 index 0000000..8baa6cb --- /dev/null +++ b/project/Debug/Core/Src/debug.d @@ -0,0 +1,93 @@ +Core/Src/debug.o: ../Core/Src/debug.c ../Core/Inc/debug.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Core/Inc/debug.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Core/Src/debug.o b/project/Debug/Core/Src/debug.o new file mode 100644 index 0000000..6705b4e Binary files /dev/null and b/project/Debug/Core/Src/debug.o differ diff --git a/project/Debug/Core/Src/debug.su b/project/Debug/Core/Src/debug.su new file mode 100644 index 0000000..a339171 --- /dev/null +++ b/project/Debug/Core/Src/debug.su @@ -0,0 +1,2 @@ +../Core/Src/debug.c:11:5:_write 32 static +../Core/Src/debug.c:35:5:_read 32 static diff --git a/project/Debug/Core/Src/ds3231_for_stm32_hal.cyclo b/project/Debug/Core/Src/ds3231_for_stm32_hal.cyclo new file mode 100644 index 0000000..6ed7441 --- /dev/null +++ b/project/Debug/Core/Src/ds3231_for_stm32_hal.cyclo @@ -0,0 +1,26 @@ +ds3231_for_stm32_hal.c:17:6:DS3231_Init 1 +ds3231_for_stm32_hal.c:31:6:DS3231_SetRegByte 1 +ds3231_for_stm32_hal.c:41:9:DS3231_GetRegByte 1 +ds3231_for_stm32_hal.c:52:6:DS3231_EnableBatterySquareWave 1 +ds3231_for_stm32_hal.c:61:6:DS3231_SetInterruptMode 1 +ds3231_for_stm32_hal.c:70:6:DS3231_SetRateSelect 1 +ds3231_for_stm32_hal.c:79:6:DS3231_EnableOscillator 2 +ds3231_for_stm32_hal.c:88:6:DS3231_EnableAlarm2 1 +ds3231_for_stm32_hal.c:97:6:DS3231_ClearAlarm2Flag 1 +ds3231_for_stm32_hal.c:107:6:DS3231_SetAlarm2Time 1 +ds3231_for_stm32_hal.c:130:6:DS3231_SetAlarm2Mode 1 +ds3231_for_stm32_hal.c:144:6:DS3231_EnableAlarm1 1 +ds3231_for_stm32_hal.c:153:6:DS3231_ClearAlarm1Flag 1 +ds3231_for_stm32_hal.c:163:6:DS3231_SetAlarm1Time 1 +ds3231_for_stm32_hal.c:190:6:DS3231_SetAlarm1Mode 1 +ds3231_for_stm32_hal.c:206:9:DS3231_IsOscillatorStopped 1 +ds3231_for_stm32_hal.c:214:9:DS3231_Is32kHzEnabled 1 +ds3231_for_stm32_hal.c:222:9:DS3231_IsAlarm1Triggered 1 +ds3231_for_stm32_hal.c:230:9:DS3231_IsAlarm2Triggered 1 +ds3231_for_stm32_hal.c:238:6:DS3231_GetTime 1 +ds3231_for_stm32_hal.c:258:6:DS3231_SetTime 1 +ds3231_for_stm32_hal.c:279:9:DS3231_DecodeBCD 1 +ds3231_for_stm32_hal.c:288:9:DS3231_EncodeBCD 1 +ds3231_for_stm32_hal.c:296:6:DS3231_Enable32kHzOutput 1 +ds3231_for_stm32_hal.c:305:8:DS3231_GetTemperatureInteger 1 +ds3231_for_stm32_hal.c:313:9:DS3231_GetTemperatureFraction 1 diff --git a/project/Debug/Core/Src/ds3231_for_stm32_hal.d b/project/Debug/Core/Src/ds3231_for_stm32_hal.d new file mode 100644 index 0000000..150619f --- /dev/null +++ b/project/Debug/Core/Src/ds3231_for_stm32_hal.d @@ -0,0 +1,98 @@ +Core/Src/ds3231_for_stm32_hal.o: ../Core/Src/ds3231_for_stm32_hal.c \ + ../Core/Inc/ds3231_for_stm32_hal.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Core/Inc/Time.h ../Core/Inc/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Core/Inc/ds3231_for_stm32_hal.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Core/Inc/Time.h: +../Core/Inc/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Core/Src/ds3231_for_stm32_hal.o b/project/Debug/Core/Src/ds3231_for_stm32_hal.o new file mode 100644 index 0000000..098df1e Binary files /dev/null and b/project/Debug/Core/Src/ds3231_for_stm32_hal.o differ diff --git a/project/Debug/Core/Src/ds3231_for_stm32_hal.su b/project/Debug/Core/Src/ds3231_for_stm32_hal.su new file mode 100644 index 0000000..4102eac --- /dev/null +++ b/project/Debug/Core/Src/ds3231_for_stm32_hal.su @@ -0,0 +1,26 @@ +../Core/Src/ds3231_for_stm32_hal.c:17:6:DS3231_Init 16 static +../Core/Src/ds3231_for_stm32_hal.c:31:6:DS3231_SetRegByte 32 static +../Core/Src/ds3231_for_stm32_hal.c:41:9:DS3231_GetRegByte 32 static +../Core/Src/ds3231_for_stm32_hal.c:52:6:DS3231_EnableBatterySquareWave 24 static +../Core/Src/ds3231_for_stm32_hal.c:61:6:DS3231_SetInterruptMode 24 static +../Core/Src/ds3231_for_stm32_hal.c:70:6:DS3231_SetRateSelect 24 static +../Core/Src/ds3231_for_stm32_hal.c:79:6:DS3231_EnableOscillator 24 static +../Core/Src/ds3231_for_stm32_hal.c:88:6:DS3231_EnableAlarm2 24 static +../Core/Src/ds3231_for_stm32_hal.c:97:6:DS3231_ClearAlarm2Flag 16 static +../Core/Src/ds3231_for_stm32_hal.c:107:6:DS3231_SetAlarm2Time 24 static +../Core/Src/ds3231_for_stm32_hal.c:130:6:DS3231_SetAlarm2Mode 24 static +../Core/Src/ds3231_for_stm32_hal.c:144:6:DS3231_EnableAlarm1 24 static +../Core/Src/ds3231_for_stm32_hal.c:153:6:DS3231_ClearAlarm1Flag 16 static +../Core/Src/ds3231_for_stm32_hal.c:163:6:DS3231_SetAlarm1Time 24 static +../Core/Src/ds3231_for_stm32_hal.c:190:6:DS3231_SetAlarm1Mode 24 static +../Core/Src/ds3231_for_stm32_hal.c:206:9:DS3231_IsOscillatorStopped 8 static +../Core/Src/ds3231_for_stm32_hal.c:214:9:DS3231_Is32kHzEnabled 8 static +../Core/Src/ds3231_for_stm32_hal.c:222:9:DS3231_IsAlarm1Triggered 8 static +../Core/Src/ds3231_for_stm32_hal.c:230:9:DS3231_IsAlarm2Triggered 8 static +../Core/Src/ds3231_for_stm32_hal.c:238:6:DS3231_GetTime 24 static +../Core/Src/ds3231_for_stm32_hal.c:258:6:DS3231_SetTime 24 static +../Core/Src/ds3231_for_stm32_hal.c:279:9:DS3231_DecodeBCD 16 static +../Core/Src/ds3231_for_stm32_hal.c:288:9:DS3231_EncodeBCD 16 static +../Core/Src/ds3231_for_stm32_hal.c:296:6:DS3231_Enable32kHzOutput 24 static +../Core/Src/ds3231_for_stm32_hal.c:305:8:DS3231_GetTemperatureInteger 8 static +../Core/Src/ds3231_for_stm32_hal.c:313:9:DS3231_GetTemperatureFraction 8 static diff --git a/project/Debug/Core/Src/freertos.cyclo b/project/Debug/Core/Src/freertos.cyclo new file mode 100644 index 0000000..5472dc2 --- /dev/null +++ b/project/Debug/Core/Src/freertos.cyclo @@ -0,0 +1 @@ +freertos.c:62:6:vApplicationGetIdleTaskMemory 1 diff --git a/project/Debug/Core/Src/freertos.d b/project/Debug/Core/Src/freertos.d new file mode 100644 index 0000000..425e216 --- /dev/null +++ b/project/Debug/Core/Src/freertos.d @@ -0,0 +1,96 @@ +Core/Src/freertos.o: ../Core/Src/freertos.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Core/Inc/main.h ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Core/Src/freertos.o b/project/Debug/Core/Src/freertos.o new file mode 100644 index 0000000..a8cc354 Binary files /dev/null and b/project/Debug/Core/Src/freertos.o differ diff --git a/project/Debug/Core/Src/freertos.su b/project/Debug/Core/Src/freertos.su new file mode 100644 index 0000000..ef2a7c6 --- /dev/null +++ b/project/Debug/Core/Src/freertos.su @@ -0,0 +1 @@ +../Core/Src/freertos.c:62:6:vApplicationGetIdleTaskMemory 24 static diff --git a/project/Debug/Core/Src/main.cyclo b/project/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..c173fc2 --- /dev/null +++ b/project/Debug/Core/Src/main.cyclo @@ -0,0 +1,11 @@ +main.c:84:5:main 1 +main.c:193:6:SystemClock_Config 4 +main.c:252:13:MX_DMA2D_Init 3 +main.c:289:13:MX_LTDC_Init 4 +main.c:371:13:MX_RTC_Init 2 +main.c:406:13:MX_USART1_UART_Init 2 +main.c:437:13:MX_FMC_Init 2 +main.c:488:13:MX_GPIO_Init 1 +main.c:544:13:app_main 1 +main.c:565:6:HAL_TIM_PeriodElapsedCallback 2 +main.c:582:6:Error_Handler 1 diff --git a/project/Debug/Core/Src/main.d b/project/Debug/Core/Src/main.d new file mode 100644 index 0000000..8cb2da7 --- /dev/null +++ b/project/Debug/Core/Src/main.d @@ -0,0 +1,215 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../LWIP/Target/ethernetif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Core/Inc/NTP.h ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Core/Inc/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h \ + ../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../LWIP/Target/ethernetif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Core/Inc/NTP.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Core/Inc/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h: +../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h: diff --git a/project/Debug/Core/Src/main.o b/project/Debug/Core/Src/main.o new file mode 100644 index 0000000..178a0a2 Binary files /dev/null and b/project/Debug/Core/Src/main.o differ diff --git a/project/Debug/Core/Src/main.su b/project/Debug/Core/Src/main.su new file mode 100644 index 0000000..4a2d625 --- /dev/null +++ b/project/Debug/Core/Src/main.su @@ -0,0 +1,11 @@ +../Core/Src/main.c:84:5:main 48 static +../Core/Src/main.c:193:6:SystemClock_Config 88 static +../Core/Src/main.c:252:13:MX_DMA2D_Init 8 static +../Core/Src/main.c:289:13:MX_LTDC_Init 112 static +../Core/Src/main.c:371:13:MX_RTC_Init 8 static +../Core/Src/main.c:406:13:MX_USART1_UART_Init 8 static +../Core/Src/main.c:437:13:MX_FMC_Init 40 static +../Core/Src/main.c:488:13:MX_GPIO_Init 72 static +../Core/Src/main.c:544:13:app_main 16 static +../Core/Src/main.c:565:6:HAL_TIM_PeriodElapsedCallback 16 static +../Core/Src/main.c:582:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/project/Debug/Core/Src/stm32f7xx_hal_msp.cyclo b/project/Debug/Core/Src/stm32f7xx_hal_msp.cyclo new file mode 100644 index 0000000..0f50047 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_msp.cyclo @@ -0,0 +1,13 @@ +stm32f7xx_hal_msp.c:63:6:HAL_MspInit 1 +stm32f7xx_hal_msp.c:87:6:HAL_DMA2D_MspInit 2 +stm32f7xx_hal_msp.c:109:6:HAL_DMA2D_MspDeInit 2 +stm32f7xx_hal_msp.c:131:6:HAL_LTDC_MspInit 3 +stm32f7xx_hal_msp.c:245:6:HAL_LTDC_MspDeInit 2 +stm32f7xx_hal_msp.c:312:6:HAL_RTC_MspInit 3 +stm32f7xx_hal_msp.c:345:6:HAL_RTC_MspDeInit 2 +stm32f7xx_hal_msp.c:367:6:HAL_UART_MspInit 3 +stm32f7xx_hal_msp.c:422:6:HAL_UART_MspDeInit 2 +stm32f7xx_hal_msp.c:449:13:HAL_FMC_MspInit 2 +stm32f7xx_hal_msp.c:548:6:HAL_SDRAM_MspInit 1 +stm32f7xx_hal_msp.c:560:13:HAL_FMC_MspDeInit 2 +stm32f7xx_hal_msp.c:632:6:HAL_SDRAM_MspDeInit 1 diff --git a/project/Debug/Core/Src/stm32f7xx_hal_msp.d b/project/Debug/Core/Src/stm32f7xx_hal_msp.d new file mode 100644 index 0000000..c84e690 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_msp.d @@ -0,0 +1,78 @@ +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Core/Src/stm32f7xx_hal_msp.o b/project/Debug/Core/Src/stm32f7xx_hal_msp.o new file mode 100644 index 0000000..6334cec Binary files /dev/null and b/project/Debug/Core/Src/stm32f7xx_hal_msp.o differ diff --git a/project/Debug/Core/Src/stm32f7xx_hal_msp.su b/project/Debug/Core/Src/stm32f7xx_hal_msp.su new file mode 100644 index 0000000..1530f34 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_msp.su @@ -0,0 +1,13 @@ +../Core/Src/stm32f7xx_hal_msp.c:63:6:HAL_MspInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:87:6:HAL_DMA2D_MspInit 24 static +../Core/Src/stm32f7xx_hal_msp.c:109:6:HAL_DMA2D_MspDeInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:131:6:HAL_LTDC_MspInit 192 static +../Core/Src/stm32f7xx_hal_msp.c:245:6:HAL_LTDC_MspDeInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:312:6:HAL_RTC_MspInit 152 static +../Core/Src/stm32f7xx_hal_msp.c:345:6:HAL_RTC_MspDeInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:367:6:HAL_UART_MspInit 184 static +../Core/Src/stm32f7xx_hal_msp.c:422:6:HAL_UART_MspDeInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:449:13:HAL_FMC_MspInit 32 static +../Core/Src/stm32f7xx_hal_msp.c:548:6:HAL_SDRAM_MspInit 16 static +../Core/Src/stm32f7xx_hal_msp.c:560:13:HAL_FMC_MspDeInit 8 static +../Core/Src/stm32f7xx_hal_msp.c:632:6:HAL_SDRAM_MspDeInit 16 static diff --git a/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.cyclo b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.cyclo new file mode 100644 index 0000000..2614c12 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.cyclo @@ -0,0 +1,3 @@ +stm32f7xx_hal_timebase_tim.c:41:19:HAL_InitTick 4 +stm32f7xx_hal_timebase_tim.c:110:6:HAL_SuspendTick 1 +stm32f7xx_hal_timebase_tim.c:122:6:HAL_ResumeTick 1 diff --git a/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d new file mode 100644 index 0000000..56e37c0 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d @@ -0,0 +1,78 @@ +Core/Src/stm32f7xx_hal_timebase_tim.o: \ + ../Core/Src/stm32f7xx_hal_timebase_tim.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o new file mode 100644 index 0000000..c9b60ff Binary files /dev/null and b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o differ diff --git a/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su new file mode 100644 index 0000000..87d0265 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su @@ -0,0 +1,3 @@ +../Core/Src/stm32f7xx_hal_timebase_tim.c:41:19:HAL_InitTick 56 static +../Core/Src/stm32f7xx_hal_timebase_tim.c:110:6:HAL_SuspendTick 4 static +../Core/Src/stm32f7xx_hal_timebase_tim.c:122:6:HAL_ResumeTick 4 static diff --git a/project/Debug/Core/Src/stm32f7xx_it.cyclo b/project/Debug/Core/Src/stm32f7xx_it.cyclo new file mode 100644 index 0000000..57d3bba --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_it.cyclo @@ -0,0 +1,2 @@ +stm32f7xx_it.c:79:6:TIM1_UP_TIM10_IRQHandler 1 +stm32f7xx_it.c:93:6:ETH_IRQHandler 1 diff --git a/project/Debug/Core/Src/stm32f7xx_it.d b/project/Debug/Core/Src/stm32f7xx_it.d new file mode 100644 index 0000000..13b5674 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_it.d @@ -0,0 +1,80 @@ +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Core/Inc/stm32f7xx_it.h +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Core/Inc/stm32f7xx_it.h: diff --git a/project/Debug/Core/Src/stm32f7xx_it.o b/project/Debug/Core/Src/stm32f7xx_it.o new file mode 100644 index 0000000..f0e2a40 Binary files /dev/null and b/project/Debug/Core/Src/stm32f7xx_it.o differ diff --git a/project/Debug/Core/Src/stm32f7xx_it.su b/project/Debug/Core/Src/stm32f7xx_it.su new file mode 100644 index 0000000..bbaa402 --- /dev/null +++ b/project/Debug/Core/Src/stm32f7xx_it.su @@ -0,0 +1,2 @@ +../Core/Src/stm32f7xx_it.c:79:6:TIM1_UP_TIM10_IRQHandler 8 static +../Core/Src/stm32f7xx_it.c:93:6:ETH_IRQHandler 8 static diff --git a/project/Debug/Core/Src/subdir.mk b/project/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..d6c41d5 --- /dev/null +++ b/project/Debug/Core/Src/subdir.mk @@ -0,0 +1,69 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/NTP.c \ +../Core/Src/RTC.c \ +../Core/Src/Time.c \ +../Core/Src/app_main.c \ +../Core/Src/clock.c \ +../Core/Src/debug.c \ +../Core/Src/ds3231_for_stm32_hal.c \ +../Core/Src/freertos.c \ +../Core/Src/main.c \ +../Core/Src/stm32f7xx_hal_msp.c \ +../Core/Src/stm32f7xx_hal_timebase_tim.c \ +../Core/Src/stm32f7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f7xx.c + +OBJS += \ +./Core/Src/NTP.o \ +./Core/Src/RTC.o \ +./Core/Src/Time.o \ +./Core/Src/app_main.o \ +./Core/Src/clock.o \ +./Core/Src/debug.o \ +./Core/Src/ds3231_for_stm32_hal.o \ +./Core/Src/freertos.o \ +./Core/Src/main.o \ +./Core/Src/stm32f7xx_hal_msp.o \ +./Core/Src/stm32f7xx_hal_timebase_tim.o \ +./Core/Src/stm32f7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f7xx.o + +C_DEPS += \ +./Core/Src/NTP.d \ +./Core/Src/RTC.d \ +./Core/Src/Time.d \ +./Core/Src/app_main.d \ +./Core/Src/clock.d \ +./Core/Src/debug.d \ +./Core/Src/ds3231_for_stm32_hal.d \ +./Core/Src/freertos.d \ +./Core/Src/main.d \ +./Core/Src/stm32f7xx_hal_msp.d \ +./Core/Src/stm32f7xx_hal_timebase_tim.d \ +./Core/Src/stm32f7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f7xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/NTP.cyclo ./Core/Src/NTP.d ./Core/Src/NTP.o ./Core/Src/NTP.su ./Core/Src/RTC.cyclo ./Core/Src/RTC.d ./Core/Src/RTC.o ./Core/Src/RTC.su ./Core/Src/Time.cyclo ./Core/Src/Time.d ./Core/Src/Time.o ./Core/Src/Time.su ./Core/Src/app_main.cyclo ./Core/Src/app_main.d ./Core/Src/app_main.o ./Core/Src/app_main.su ./Core/Src/clock.cyclo ./Core/Src/clock.d ./Core/Src/clock.o ./Core/Src/clock.su ./Core/Src/debug.cyclo ./Core/Src/debug.d ./Core/Src/debug.o ./Core/Src/debug.su ./Core/Src/ds3231_for_stm32_hal.cyclo ./Core/Src/ds3231_for_stm32_hal.d ./Core/Src/ds3231_for_stm32_hal.o ./Core/Src/ds3231_for_stm32_hal.su ./Core/Src/freertos.cyclo ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f7xx_hal_msp.cyclo ./Core/Src/stm32f7xx_hal_msp.d ./Core/Src/stm32f7xx_hal_msp.o ./Core/Src/stm32f7xx_hal_msp.su ./Core/Src/stm32f7xx_hal_timebase_tim.cyclo ./Core/Src/stm32f7xx_hal_timebase_tim.d ./Core/Src/stm32f7xx_hal_timebase_tim.o ./Core/Src/stm32f7xx_hal_timebase_tim.su ./Core/Src/stm32f7xx_it.cyclo ./Core/Src/stm32f7xx_it.d ./Core/Src/stm32f7xx_it.o ./Core/Src/stm32f7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f7xx.cyclo ./Core/Src/system_stm32f7xx.d ./Core/Src/system_stm32f7xx.o ./Core/Src/system_stm32f7xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/project/Debug/Core/Src/syscalls.cyclo b/project/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..9e7800b --- /dev/null +++ b/project/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +syscalls.c:44:6:initialise_monitor_handles 1 +syscalls.c:48:5:_getpid 1 +syscalls.c:53:5:_kill 1 +syscalls.c:59:6:_exit 1 +syscalls.c:65:27:_read 2 +syscalls.c:77:27:_write 2 +syscalls.c:88:5:_close 1 +syscalls.c:94:5:_fstat 1 +syscalls.c:100:5:_isatty 1 +syscalls.c:105:5:_lseek 1 +syscalls.c:110:5:_open 1 +syscalls.c:116:5:_wait 1 +syscalls.c:122:5:_unlink 1 +syscalls.c:128:5:_times 1 +syscalls.c:133:5:_stat 1 +syscalls.c:139:5:_link 1 +syscalls.c:145:5:_fork 1 +syscalls.c:151:5:_execve 1 diff --git a/project/Debug/Core/Src/syscalls.d b/project/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..27f6ff8 --- /dev/null +++ b/project/Debug/Core/Src/syscalls.d @@ -0,0 +1,92 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Core/Src/syscalls.o b/project/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..6a671c0 Binary files /dev/null and b/project/Debug/Core/Src/syscalls.o differ diff --git a/project/Debug/Core/Src/syscalls.su b/project/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..46e64cc --- /dev/null +++ b/project/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:59:6:_exit 16 static +../Core/Src/syscalls.c:65:27:_read 32 static +../Core/Src/syscalls.c:77:27:_write 32 static +../Core/Src/syscalls.c:88:5:_close 16 static +../Core/Src/syscalls.c:94:5:_fstat 16 static +../Core/Src/syscalls.c:100:5:_isatty 16 static +../Core/Src/syscalls.c:105:5:_lseek 24 static +../Core/Src/syscalls.c:110:5:_open 12 static +../Core/Src/syscalls.c:116:5:_wait 16 static +../Core/Src/syscalls.c:122:5:_unlink 16 static +../Core/Src/syscalls.c:128:5:_times 16 static +../Core/Src/syscalls.c:133:5:_stat 16 static +../Core/Src/syscalls.c:139:5:_link 16 static +../Core/Src/syscalls.c:145:5:_fork 4 static +../Core/Src/syscalls.c:151:5:_execve 24 static diff --git a/project/Debug/Core/Src/sysmem.cyclo b/project/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..611be9f --- /dev/null +++ b/project/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +sysmem.c:53:7:_sbrk 3 diff --git a/project/Debug/Core/Src/sysmem.d b/project/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..3bddea0 --- /dev/null +++ b/project/Debug/Core/Src/sysmem.d @@ -0,0 +1,92 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Core/Src/sysmem.o b/project/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..ef39ff6 Binary files /dev/null and b/project/Debug/Core/Src/sysmem.o differ diff --git a/project/Debug/Core/Src/sysmem.su b/project/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..12d5f17 --- /dev/null +++ b/project/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/project/Debug/Core/Src/system_stm32f7xx.cyclo b/project/Debug/Core/Src/system_stm32f7xx.cyclo new file mode 100644 index 0000000..154ef7c --- /dev/null +++ b/project/Debug/Core/Src/system_stm32f7xx.cyclo @@ -0,0 +1,2 @@ +system_stm32f7xx.c:150:6:SystemInit 1 +system_stm32f7xx.c:219:6:SystemCoreClockUpdate 6 diff --git a/project/Debug/Core/Src/system_stm32f7xx.d b/project/Debug/Core/Src/system_stm32f7xx.d new file mode 100644 index 0000000..27fa23c --- /dev/null +++ b/project/Debug/Core/Src/system_stm32f7xx.d @@ -0,0 +1,77 @@ +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Core/Src/system_stm32f7xx.o b/project/Debug/Core/Src/system_stm32f7xx.o new file mode 100644 index 0000000..bcd24c4 Binary files /dev/null and b/project/Debug/Core/Src/system_stm32f7xx.o differ diff --git a/project/Debug/Core/Src/system_stm32f7xx.su b/project/Debug/Core/Src/system_stm32f7xx.su new file mode 100644 index 0000000..446e85e --- /dev/null +++ b/project/Debug/Core/Src/system_stm32f7xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f7xx.c:150:6:SystemInit 4 static +../Core/Src/system_stm32f7xx.c:219:6:SystemCoreClockUpdate 32 static diff --git a/project/Debug/Core/Startup/startup_stm32f746nghx.d b/project/Debug/Core/Startup/startup_stm32f746nghx.d new file mode 100644 index 0000000..d288a1a --- /dev/null +++ b/project/Debug/Core/Startup/startup_stm32f746nghx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f746nghx.o: \ + ../Core/Startup/startup_stm32f746nghx.s diff --git a/project/Debug/Core/Startup/startup_stm32f746nghx.o b/project/Debug/Core/Startup/startup_stm32f746nghx.o new file mode 100644 index 0000000..3b74e58 Binary files /dev/null and b/project/Debug/Core/Startup/startup_stm32f746nghx.o differ diff --git a/project/Debug/Core/Startup/subdir.mk b/project/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..87b38a4 --- /dev/null +++ b/project/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f746nghx.s + +OBJS += \ +./Core/Startup/startup_stm32f746nghx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f746nghx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32f746nghx.d ./Core/Startup/startup_stm32f746nghx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/project/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo new file mode 100644 index 0000000..de46a73 --- /dev/null +++ b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo @@ -0,0 +1,14 @@ +lan8742.c:63:10:LAN8742_RegisterBusIO 5 +lan8742.c:88:10:LAN8742_Init 15 +lan8742.c:188:9:LAN8742_DeInit 4 +lan8742.c:213:9:LAN8742_DisablePowerDownMode 3 +lan8742.c:243:9:LAN8742_EnablePowerDownMode 3 +lan8742.c:273:9:LAN8742_StartAutoNego 3 +lan8742.c:309:9:LAN8742_GetLinkState 15 +lan8742.c:401:9:LAN8742_SetLinkState 7 +lan8742.c:453:9:LAN8742_EnableLoopbackMode 3 +lan8742.c:483:9:LAN8742_DisableLoopbackMode 3 +lan8742.c:523:9:LAN8742_EnableIT 3 +lan8742.c:563:9:LAN8742_DisableIT 3 +lan8742.c:602:10:LAN8742_ClearIT 2 +lan8742.c:632:9:LAN8742_GetITStatus 2 diff --git a/project/Debug/Drivers/BSP/Components/lan8742/lan8742.d b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.d new file mode 100644 index 0000000..47f281d --- /dev/null +++ b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.d @@ -0,0 +1,4 @@ +Drivers/BSP/Components/lan8742/lan8742.o: \ + ../Drivers/BSP/Components/lan8742/lan8742.c \ + ../Drivers/BSP/Components/lan8742/lan8742.h +../Drivers/BSP/Components/lan8742/lan8742.h: diff --git a/project/Debug/Drivers/BSP/Components/lan8742/lan8742.o b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.o new file mode 100644 index 0000000..8870e8c Binary files /dev/null and b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.o differ diff --git a/project/Debug/Drivers/BSP/Components/lan8742/lan8742.su b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.su new file mode 100644 index 0000000..c75843a --- /dev/null +++ b/project/Debug/Drivers/BSP/Components/lan8742/lan8742.su @@ -0,0 +1,14 @@ +../Drivers/BSP/Components/lan8742/lan8742.c:63:10:LAN8742_RegisterBusIO 16 static +../Drivers/BSP/Components/lan8742/lan8742.c:88:10:LAN8742_Init 32 static +../Drivers/BSP/Components/lan8742/lan8742.c:188:9:LAN8742_DeInit 16 static +../Drivers/BSP/Components/lan8742/lan8742.c:213:9:LAN8742_DisablePowerDownMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:243:9:LAN8742_EnablePowerDownMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:273:9:LAN8742_StartAutoNego 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:309:9:LAN8742_GetLinkState 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:401:9:LAN8742_SetLinkState 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:453:9:LAN8742_EnableLoopbackMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:483:9:LAN8742_DisableLoopbackMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:523:9:LAN8742_EnableIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:563:9:LAN8742_DisableIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:602:10:LAN8742_ClearIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:632:9:LAN8742_GetITStatus 24 static diff --git a/project/Debug/Drivers/BSP/Components/lan8742/subdir.mk b/project/Debug/Drivers/BSP/Components/lan8742/subdir.mk new file mode 100644 index 0000000..4b04d26 --- /dev/null +++ b/project/Debug/Drivers/BSP/Components/lan8742/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/BSP/Components/lan8742/lan8742.c + +OBJS += \ +./Drivers/BSP/Components/lan8742/lan8742.o + +C_DEPS += \ +./Drivers/BSP/Components/lan8742/lan8742.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/BSP/Components/lan8742/%.o Drivers/BSP/Components/lan8742/%.su Drivers/BSP/Components/lan8742/%.cyclo: ../Drivers/BSP/Components/lan8742/%.c Drivers/BSP/Components/lan8742/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-BSP-2f-Components-2f-lan8742 + +clean-Drivers-2f-BSP-2f-Components-2f-lan8742: + -$(RM) ./Drivers/BSP/Components/lan8742/lan8742.cyclo ./Drivers/BSP/Components/lan8742/lan8742.d ./Drivers/BSP/Components/lan8742/lan8742.o ./Drivers/BSP/Components/lan8742/lan8742.su + +.PHONY: clean-Drivers-2f-BSP-2f-Components-2f-lan8742 + diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.cyclo b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.cyclo new file mode 100644 index 0000000..761fe7c --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.cyclo @@ -0,0 +1,34 @@ +stm32746g_discovery.c:161:10:BSP_GetVersion 1 +stm32746g_discovery.c:173:6:BSP_LED_Init 2 +stm32746g_discovery.c:205:6:BSP_LED_DeInit 2 +stm32746g_discovery.c:228:6:BSP_LED_On 2 +stm32746g_discovery.c:246:6:BSP_LED_Off 2 +stm32746g_discovery.c:264:6:BSP_LED_Toggle 2 +stm32746g_discovery.c:292:6:BSP_PB_Init 6 +stm32746g_discovery.c:346:6:BSP_PB_DeInit 1 +stm32746g_discovery.c:368:10:BSP_PB_GetState 1 +stm32746g_discovery.c:383:6:BSP_COM_Init 4 +stm32746g_discovery.c:423:6:BSP_COM_DeInit 2 +stm32746g_discovery.c:449:13:I2Cx_MspInit 2 +stm32746g_discovery.c:536:13:I2Cx_Init 3 +stm32746g_discovery.c:574:26:I2Cx_ReadMultiple 2 +stm32746g_discovery.c:604:26:I2Cx_WriteMultiple 2 +stm32746g_discovery.c:632:26:I2Cx_IsDeviceReady 1 +stm32746g_discovery.c:643:13:I2Cx_Error 1 +stm32746g_discovery.c:662:6:AUDIO_IO_Init 1 +stm32746g_discovery.c:671:6:AUDIO_IO_DeInit 1 +stm32746g_discovery.c:682:6:AUDIO_IO_Write 1 +stm32746g_discovery.c:699:10:AUDIO_IO_Read 1 +stm32746g_discovery.c:719:6:AUDIO_IO_Delay 1 +stm32746g_discovery.c:730:6:CAMERA_IO_Init 1 +stm32746g_discovery.c:742:6:CAMERA_IO_Write 1 +stm32746g_discovery.c:753:9:CAMERA_IO_Read 1 +stm32746g_discovery.c:767:6:CAMERA_Delay 1 +stm32746g_discovery.c:778:6:EEPROM_IO_Init 1 +stm32746g_discovery.c:791:19:EEPROM_IO_WriteData 1 +stm32746g_discovery.c:804:19:EEPROM_IO_ReadData 1 +stm32746g_discovery.c:816:19:EEPROM_IO_IsDeviceReady 1 +stm32746g_discovery.c:827:6:TS_IO_Init 1 +stm32746g_discovery.c:839:6:TS_IO_Write 1 +stm32746g_discovery.c:850:9:TS_IO_Read 1 +stm32746g_discovery.c:864:6:TS_IO_Delay 1 diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.d b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.d new file mode 100644 index 0000000..834cde8 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.d @@ -0,0 +1,80 @@ +Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o: \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o new file mode 100644 index 0000000..841a42a Binary files /dev/null and b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o differ diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.su b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.su new file mode 100644 index 0000000..211a363 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.su @@ -0,0 +1,34 @@ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:161:10:BSP_GetVersion 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:173:6:BSP_LED_Init 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:205:6:BSP_LED_DeInit 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:228:6:BSP_LED_On 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:246:6:BSP_LED_Off 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:264:6:BSP_LED_Toggle 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:292:6:BSP_PB_Init 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:346:6:BSP_PB_DeInit 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:368:10:BSP_PB_GetState 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:383:6:BSP_COM_Init 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:423:6:BSP_COM_DeInit 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:449:13:I2Cx_MspInit 56 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:536:13:I2Cx_Init 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:574:26:I2Cx_ReadMultiple 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:604:26:I2Cx_WriteMultiple 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:632:26:I2Cx_IsDeviceReady 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:643:13:I2Cx_Error 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:662:6:AUDIO_IO_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:671:6:AUDIO_IO_DeInit 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:682:6:AUDIO_IO_Write 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:699:10:AUDIO_IO_Read 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:719:6:AUDIO_IO_Delay 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:730:6:CAMERA_IO_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:742:6:CAMERA_IO_Write 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:753:9:CAMERA_IO_Read 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:767:6:CAMERA_Delay 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:778:6:EEPROM_IO_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:791:19:EEPROM_IO_WriteData 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:804:19:EEPROM_IO_ReadData 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:816:19:EEPROM_IO_IsDeviceReady 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:827:6:TS_IO_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:839:6:TS_IO_Write 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:850:9:TS_IO_Read 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c:864:6:TS_IO_Delay 16 static diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.cyclo b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.cyclo new file mode 100644 index 0000000..e2334f6 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.cyclo @@ -0,0 +1,56 @@ +stm32746g_discovery_lcd.c:149:9:BSP_LCD_Init 2 +stm32746g_discovery_lcd.c:211:9:BSP_LCD_DeInit 1 +stm32746g_discovery_lcd.c:232:10:BSP_LCD_GetXSize 1 +stm32746g_discovery_lcd.c:241:10:BSP_LCD_GetYSize 1 +stm32746g_discovery_lcd.c:251:6:BSP_LCD_SetXSize 1 +stm32746g_discovery_lcd.c:261:6:BSP_LCD_SetYSize 1 +stm32746g_discovery_lcd.c:272:6:BSP_LCD_LayerDefaultInit 1 +stm32746g_discovery_lcd.c:306:6:BSP_LCD_LayerRgb565Init 1 +stm32746g_discovery_lcd.c:339:6:BSP_LCD_SelectLayer 1 +stm32746g_discovery_lcd.c:353:6:BSP_LCD_SetLayerVisible 2 +stm32746g_discovery_lcd.c:375:6:BSP_LCD_SetLayerVisible_NoReload 2 +stm32746g_discovery_lcd.c:395:6:BSP_LCD_SetTransparency 1 +stm32746g_discovery_lcd.c:407:6:BSP_LCD_SetTransparency_NoReload 1 +stm32746g_discovery_lcd.c:418:6:BSP_LCD_SetLayerAddress 1 +stm32746g_discovery_lcd.c:429:6:BSP_LCD_SetLayerAddress_NoReload 1 +stm32746g_discovery_lcd.c:443:6:BSP_LCD_SetLayerWindow 1 +stm32746g_discovery_lcd.c:461:6:BSP_LCD_SetLayerWindow_NoReload 1 +stm32746g_discovery_lcd.c:476:6:BSP_LCD_SetColorKeying 1 +stm32746g_discovery_lcd.c:489:6:BSP_LCD_SetColorKeying_NoReload 1 +stm32746g_discovery_lcd.c:501:6:BSP_LCD_ResetColorKeying 1 +stm32746g_discovery_lcd.c:512:6:BSP_LCD_ResetColorKeying_NoReload 1 +stm32746g_discovery_lcd.c:525:6:BSP_LCD_Reload 1 +stm32746g_discovery_lcd.c:535:6:BSP_LCD_SetTextColor 1 +stm32746g_discovery_lcd.c:544:10:BSP_LCD_GetTextColor 1 +stm32746g_discovery_lcd.c:554:6:BSP_LCD_SetBackColor 1 +stm32746g_discovery_lcd.c:563:10:BSP_LCD_GetBackColor 1 +stm32746g_discovery_lcd.c:573:6:BSP_LCD_SetFont 1 +stm32746g_discovery_lcd.c:582:8:BSP_LCD_GetFont 1 +stm32746g_discovery_lcd.c:593:10:BSP_LCD_ReadPixel 6 +stm32746g_discovery_lcd.c:628:6:BSP_LCD_Clear 1 +stm32746g_discovery_lcd.c:639:6:BSP_LCD_ClearStringLine 1 +stm32746g_discovery_lcd.c:659:6:BSP_LCD_DisplayChar 2 +stm32746g_discovery_lcd.c:677:6:BSP_LCD_DisplayStringAt 9 +stm32746g_discovery_lcd.c:738:6:BSP_LCD_DisplayStringAtLine 1 +stm32746g_discovery_lcd.c:750:6:BSP_LCD_DrawHLine 2 +stm32746g_discovery_lcd.c:775:6:BSP_LCD_DrawVLine 2 +stm32746g_discovery_lcd.c:801:6:BSP_LCD_DrawLine 8 +stm32746g_discovery_lcd.c:876:6:BSP_LCD_DrawRect 1 +stm32746g_discovery_lcd.c:894:6:BSP_LCD_DrawCircle 3 +stm32746g_discovery_lcd.c:941:6:BSP_LCD_DrawPolygon 3 +stm32746g_discovery_lcd.c:969:6:BSP_LCD_DrawEllipse 6 +stm32746g_discovery_lcd.c:1002:6:BSP_LCD_DrawPixel 2 +stm32746g_discovery_lcd.c:1022:6:BSP_LCD_DrawBitmap 4 +stm32746g_discovery_lcd.c:1080:6:BSP_LCD_FillRect 2 +stm32746g_discovery_lcd.c:1107:6:BSP_LCD_FillCircle 5 +stm32746g_discovery_lcd.c:1155:6:BSP_LCD_FillPolygon 10 +stm32746g_discovery_lcd.c:1223:6:BSP_LCD_FillEllipse 6 +stm32746g_discovery_lcd.c:1253:6:BSP_LCD_DisplayOn 1 +stm32746g_discovery_lcd.c:1265:6:BSP_LCD_DisplayOff 1 +stm32746g_discovery_lcd.c:1279:13:BSP_LCD_MspInit 1 +stm32746g_discovery_lcd.c:1351:13:BSP_LCD_MspDeInit 1 +stm32746g_discovery_lcd.c:1400:13:BSP_LCD_ClockConfig 1 +stm32746g_discovery_lcd.c:1428:13:DrawChar 9 +stm32746g_discovery_lcd.c:1487:13:FillTriangle 8 +stm32746g_discovery_lcd.c:1565:13:LL_FillBuffer 5 +stm32746g_discovery_lcd.c:1603:13:LL_ConvertLineToARGB8888 4 diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.d b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.d new file mode 100644 index 0000000..57ac062 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.d @@ -0,0 +1,100 @@ +Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o: \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h \ + ../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font24.c \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font20.c \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font16.c \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font12.c \ + ../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font8.c +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h: +../Drivers/BSP/STM32746G-Discovery/../Components/rk043fn48h/rk043fn48h.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font24.c: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/fonts.h: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font20.c: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font16.c: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font12.c: +../Drivers/BSP/STM32746G-Discovery/../../../Utilities/Fonts/font8.c: diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o new file mode 100644 index 0000000..241488d Binary files /dev/null and b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o differ diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.su b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.su new file mode 100644 index 0000000..c500f9b --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.su @@ -0,0 +1,56 @@ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:149:9:BSP_LCD_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:211:9:BSP_LCD_DeInit 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:232:10:BSP_LCD_GetXSize 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:241:10:BSP_LCD_GetYSize 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:251:6:BSP_LCD_SetXSize 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:261:6:BSP_LCD_SetYSize 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:272:6:BSP_LCD_LayerDefaultInit 72 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:306:6:BSP_LCD_LayerRgb565Init 72 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:339:6:BSP_LCD_SelectLayer 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:353:6:BSP_LCD_SetLayerVisible 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:375:6:BSP_LCD_SetLayerVisible_NoReload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:395:6:BSP_LCD_SetTransparency 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:407:6:BSP_LCD_SetTransparency_NoReload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:418:6:BSP_LCD_SetLayerAddress 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:429:6:BSP_LCD_SetLayerAddress_NoReload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:443:6:BSP_LCD_SetLayerWindow 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:461:6:BSP_LCD_SetLayerWindow_NoReload 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:476:6:BSP_LCD_SetColorKeying 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:489:6:BSP_LCD_SetColorKeying_NoReload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:501:6:BSP_LCD_ResetColorKeying 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:512:6:BSP_LCD_ResetColorKeying_NoReload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:525:6:BSP_LCD_Reload 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:535:6:BSP_LCD_SetTextColor 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:544:10:BSP_LCD_GetTextColor 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:554:6:BSP_LCD_SetBackColor 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:563:10:BSP_LCD_GetBackColor 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:573:6:BSP_LCD_SetFont 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:582:8:BSP_LCD_GetFont 4 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:593:10:BSP_LCD_ReadPixel 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:628:6:BSP_LCD_Clear 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:639:6:BSP_LCD_ClearStringLine 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:659:6:BSP_LCD_DisplayChar 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:677:6:BSP_LCD_DisplayStringAt 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:738:6:BSP_LCD_DisplayStringAtLine 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:750:6:BSP_LCD_DrawHLine 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:775:6:BSP_LCD_DrawVLine 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:801:6:BSP_LCD_DrawLine 56 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:876:6:BSP_LCD_DrawRect 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:894:6:BSP_LCD_DrawCircle 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:941:6:BSP_LCD_DrawPolygon 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:969:6:BSP_LCD_DrawEllipse 64 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1002:6:BSP_LCD_DrawPixel 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1022:6:BSP_LCD_DrawBitmap 56 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1080:6:BSP_LCD_FillRect 48 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1107:6:BSP_LCD_FillCircle 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1155:6:BSP_LCD_FillPolygon 64 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1223:6:BSP_LCD_FillEllipse 56 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1253:6:BSP_LCD_DisplayOn 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1265:6:BSP_LCD_DisplayOff 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1279:13:BSP_LCD_MspInit 72 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1351:13:BSP_LCD_MspDeInit 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1400:13:BSP_LCD_ClockConfig 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1428:13:DrawChar 40 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1487:13:FillTriangle 56 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1565:13:LL_FillBuffer 32 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c:1603:13:LL_ConvertLineToARGB8888 32 static diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.cyclo b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.cyclo new file mode 100644 index 0000000..9738346 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.cyclo @@ -0,0 +1,10 @@ +stm32746g_discovery_sdram.c:131:9:BSP_SDRAM_Init 2 +stm32746g_discovery_sdram.c:180:9:BSP_SDRAM_DeInit 2 +stm32746g_discovery_sdram.c:206:6:BSP_SDRAM_Initialization_sequence 1 +stm32746g_discovery_sdram.c:268:9:BSP_SDRAM_ReadData 2 +stm32746g_discovery_sdram.c:287:9:BSP_SDRAM_ReadData_DMA 2 +stm32746g_discovery_sdram.c:306:9:BSP_SDRAM_WriteData 2 +stm32746g_discovery_sdram.c:325:9:BSP_SDRAM_WriteData_DMA 2 +stm32746g_discovery_sdram.c:342:9:BSP_SDRAM_Sendcmd 2 +stm32746g_discovery_sdram.c:360:13:BSP_SDRAM_MspInit 1 +stm32746g_discovery_sdram.c:451:13:BSP_SDRAM_MspDeInit 1 diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.d b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.d new file mode 100644 index 0000000..a051b25 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.d @@ -0,0 +1,80 @@ +Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o: \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c \ + ../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o new file mode 100644 index 0000000..c081151 Binary files /dev/null and b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o differ diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.su b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.su new file mode 100644 index 0000000..eca2b24 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.su @@ -0,0 +1,10 @@ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:131:9:BSP_SDRAM_Init 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:180:9:BSP_SDRAM_DeInit 8 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:206:6:BSP_SDRAM_Initialization_sequence 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:268:9:BSP_SDRAM_ReadData 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:287:9:BSP_SDRAM_ReadData_DMA 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:306:9:BSP_SDRAM_WriteData 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:325:9:BSP_SDRAM_WriteData_DMA 24 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:342:9:BSP_SDRAM_Sendcmd 16 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:360:13:BSP_SDRAM_MspInit 72 static +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c:451:13:BSP_SDRAM_MspDeInit 16 static diff --git a/project/Debug/Drivers/BSP/STM32746G-Discovery/subdir.mk b/project/Debug/Drivers/BSP/STM32746G-Discovery/subdir.mk new file mode 100644 index 0000000..76e2194 --- /dev/null +++ b/project/Debug/Drivers/BSP/STM32746G-Discovery/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c \ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c \ +../Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c + +OBJS += \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o + +C_DEPS += \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.d \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.d \ +./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/BSP/STM32746G-Discovery/%.o Drivers/BSP/STM32746G-Discovery/%.su Drivers/BSP/STM32746G-Discovery/%.cyclo: ../Drivers/BSP/STM32746G-Discovery/%.c Drivers/BSP/STM32746G-Discovery/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-BSP-2f-STM32746G-2d-Discovery + +clean-Drivers-2f-BSP-2f-STM32746G-2d-Discovery: + -$(RM) ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.cyclo ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.d ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.su ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.cyclo ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.d ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.su ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.cyclo ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.d ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.su + +.PHONY: clean-Drivers-2f-BSP-2f-STM32746G-2d-Discovery + diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.cyclo new file mode 100644 index 0000000..b334481 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.cyclo @@ -0,0 +1,29 @@ +stm32f7xx_hal.c:138:19:HAL_Init 1 +stm32f7xx_hal.c:168:19:HAL_DeInit 1 +stm32f7xx_hal.c:197:13:HAL_MspInit 1 +stm32f7xx_hal.c:208:13:HAL_MspDeInit 1 +stm32f7xx_hal.c:231:26:HAL_InitTick 3 +stm32f7xx_hal.c:290:13:HAL_IncTick 1 +stm32f7xx_hal.c:301:17:HAL_GetTick 1 +stm32f7xx_hal.c:310:10:HAL_GetTickPrio 1 +stm32f7xx_hal.c:319:19:HAL_SetTickFreq 3 +stm32f7xx_hal.c:351:21:HAL_GetTickFreq 1 +stm32f7xx_hal.c:367:13:HAL_Delay 3 +stm32f7xx_hal.c:393:13:HAL_SuspendTick 1 +stm32f7xx_hal.c:409:13:HAL_ResumeTick 1 +stm32f7xx_hal.c:419:10:HAL_GetHalVersion 1 +stm32f7xx_hal.c:428:10:HAL_GetREVID 1 +stm32f7xx_hal.c:437:10:HAL_GetDEVID 1 +stm32f7xx_hal.c:446:10:HAL_GetUIDw0 1 +stm32f7xx_hal.c:455:10:HAL_GetUIDw1 1 +stm32f7xx_hal.c:464:10:HAL_GetUIDw2 1 +stm32f7xx_hal.c:473:6:HAL_DBGMCU_EnableDBGSleepMode 1 +stm32f7xx_hal.c:482:6:HAL_DBGMCU_DisableDBGSleepMode 1 +stm32f7xx_hal.c:491:6:HAL_DBGMCU_EnableDBGStopMode 1 +stm32f7xx_hal.c:500:6:HAL_DBGMCU_DisableDBGStopMode 1 +stm32f7xx_hal.c:509:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +stm32f7xx_hal.c:518:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +stm32f7xx_hal.c:529:6:HAL_EnableCompensationCell 1 +stm32f7xx_hal.c:540:6:HAL_DisableCompensationCell 1 +stm32f7xx_hal.c:553:6:HAL_EnableFMCMemorySwapping 1 +stm32f7xx_hal.c:566:6:HAL_DisableFMCMemorySwapping 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d new file mode 100644 index 0000000..210ec98 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o new file mode 100644 index 0000000..c8b62ab Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su new file mode 100644 index 0000000..69773d2 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su @@ -0,0 +1,29 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:138:19:HAL_Init 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:168:19:HAL_DeInit 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:197:13:HAL_MspInit 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:208:13:HAL_MspDeInit 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:231:26:HAL_InitTick 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:290:13:HAL_IncTick 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:301:17:HAL_GetTick 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:310:10:HAL_GetTickPrio 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:319:19:HAL_SetTickFreq 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:351:21:HAL_GetTickFreq 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:367:13:HAL_Delay 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:393:13:HAL_SuspendTick 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:409:13:HAL_ResumeTick 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:419:10:HAL_GetHalVersion 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:428:10:HAL_GetREVID 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:437:10:HAL_GetDEVID 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:446:10:HAL_GetUIDw0 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:455:10:HAL_GetUIDw1 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:464:10:HAL_GetUIDw2 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:473:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:482:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:491:6:HAL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:500:6:HAL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:509:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:518:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:529:6:HAL_EnableCompensationCell 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:540:6:HAL_DisableCompensationCell 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:553:6:HAL_EnableFMCMemorySwapping 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c:566:6:HAL_DisableFMCMemorySwapping 4 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.cyclo new file mode 100644 index 0000000..4dd4ae6 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.cyclo @@ -0,0 +1,32 @@ +core_cm7.h:1865:22:__NVIC_SetPriorityGrouping 1 +core_cm7.h:1884:26:__NVIC_GetPriorityGrouping 1 +core_cm7.h:1896:22:__NVIC_EnableIRQ 2 +core_cm7.h:1932:22:__NVIC_DisableIRQ 2 +core_cm7.h:1951:26:__NVIC_GetPendingIRQ 2 +core_cm7.h:1970:22:__NVIC_SetPendingIRQ 2 +core_cm7.h:1985:22:__NVIC_ClearPendingIRQ 2 +core_cm7.h:2002:26:__NVIC_GetActive 2 +core_cm7.h:2024:22:__NVIC_SetPriority 2 +core_cm7.h:2046:26:__NVIC_GetPriority 2 +core_cm7.h:2071:26:NVIC_EncodePriority 2 +core_cm7.h:2098:22:NVIC_DecodePriority 2 +core_cm7.h:2147:34:__NVIC_SystemReset 1 +core_cm7.h:2564:26:SysTick_Config 2 +stm32f7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping 1 +stm32f7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority 1 +stm32f7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ 1 +stm32f7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ 1 +stm32f7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset 0 +stm32f7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config 1 +stm32f7xx_hal_cortex.c:257:6:HAL_MPU_Disable 1 +stm32f7xx_hal_cortex.c:280:6:HAL_MPU_Enable 1 +stm32f7xx_hal_cortex.c:299:6:HAL_MPU_ConfigRegion 2 +stm32f7xx_hal_cortex.c:343:10:HAL_NVIC_GetPriorityGrouping 1 +stm32f7xx_hal_cortex.c:370:6:HAL_NVIC_GetPriority 1 +stm32f7xx_hal_cortex.c:385:6:HAL_NVIC_SetPendingIRQ 1 +stm32f7xx_hal_cortex.c:403:10:HAL_NVIC_GetPendingIRQ 1 +stm32f7xx_hal_cortex.c:419:6:HAL_NVIC_ClearPendingIRQ 1 +stm32f7xx_hal_cortex.c:436:10:HAL_NVIC_GetActive 1 +stm32f7xx_hal_cortex.c:453:6:HAL_SYSTICK_CLKSourceConfig 2 +stm32f7xx_hal_cortex.c:471:6:HAL_SYSTICK_IRQHandler 1 +stm32f7xx_hal_cortex.c:480:13:HAL_SYSTICK_Callback 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d new file mode 100644 index 0000000..dbc5f9e --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o new file mode 100644 index 0000000..609e8c2 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su new file mode 100644 index 0000000..f7e84d7 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su @@ -0,0 +1,32 @@ +../Drivers/CMSIS/Include/core_cm7.h:1865:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm7.h:1884:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm7.h:1896:22:__NVIC_EnableIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:1932:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm7.h:1951:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:1970:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:1985:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:2002:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm7.h:2024:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm7.h:2046:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm7.h:2071:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm7.h:2098:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm7.h:2147:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm7.h:2564:26:SysTick_Config 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:257:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:280:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:299:6:HAL_MPU_ConfigRegion 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:343:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:370:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:385:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:403:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:419:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:436:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:453:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:471:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c:480:13:HAL_SYSTICK_Callback 4 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.cyclo new file mode 100644 index 0000000..891a79f --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.cyclo @@ -0,0 +1,15 @@ +stm32f7xx_hal_dma.c:171:19:HAL_DMA_Init 8 +stm32f7xx_hal_dma.c:311:19:HAL_DMA_DeInit 3 +stm32f7xx_hal_dma.c:409:19:HAL_DMA_Start 3 +stm32f7xx_hal_dma.c:453:19:HAL_DMA_Start_IT 4 +stm32f7xx_hal_dma.c:516:19:HAL_DMA_Abort 6 +stm32f7xx_hal_dma.c:584:19:HAL_DMA_Abort_IT 2 +stm32f7xx_hal_dma.c:614:19:HAL_DMA_PollForTransfer 15 +stm32f7xx_hal_dma.c:751:6:HAL_DMA_IRQHandler 32 +stm32f7xx_hal_dma.c:974:19:HAL_DMA_RegisterCallback 9 +stm32f7xx_hal_dma.c:1036:19:HAL_DMA_UnRegisterCallback 10 +stm32f7xx_hal_dma.c:1121:22:HAL_DMA_GetState 1 +stm32f7xx_hal_dma.c:1132:10:HAL_DMA_GetError 1 +stm32f7xx_hal_dma.c:1158:13:DMA_SetConfig 2 +stm32f7xx_hal_dma.c:1192:17:DMA_CalcBaseAndBitshift 2 +stm32f7xx_hal_dma.c:1220:26:DMA_CheckFifoParam 15 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d new file mode 100644 index 0000000..159d2cb --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o new file mode 100644 index 0000000..131ec3e Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su new file mode 100644 index 0000000..b81f7bf --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su @@ -0,0 +1,15 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:171:19:HAL_DMA_Init 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:311:19:HAL_DMA_DeInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:409:19:HAL_DMA_Start 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:453:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:516:19:HAL_DMA_Abort 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:584:19:HAL_DMA_Abort_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:614:19:HAL_DMA_PollForTransfer 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:751:6:HAL_DMA_IRQHandler 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:974:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1036:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1121:22:HAL_DMA_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1132:10:HAL_DMA_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1158:13:DMA_SetConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1192:17:DMA_CalcBaseAndBitshift 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c:1220:26:DMA_CheckFifoParam 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.cyclo new file mode 100644 index 0000000..c200508 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.cyclo @@ -0,0 +1,32 @@ +stm32f7xx_hal_dma2d.c:238:19:HAL_DMA2D_Init 3 +stm32f7xx_hal_dma2d.c:316:19:HAL_DMA2D_DeInit 9 +stm32f7xx_hal_dma2d.c:406:13:HAL_DMA2D_MspInit 1 +stm32f7xx_hal_dma2d.c:422:13:HAL_DMA2D_MspDeInit 1 +stm32f7xx_hal_dma2d.c:678:19:HAL_DMA2D_Start 2 +stm32f7xx_hal_dma2d.c:714:19:HAL_DMA2D_Start_IT 2 +stm32f7xx_hal_dma2d.c:751:19:HAL_DMA2D_BlendingStart 2 +stm32f7xx_hal_dma2d.c:788:19:HAL_DMA2D_BlendingStart_IT 2 +stm32f7xx_hal_dma2d.c:822:19:HAL_DMA2D_Abort 3 +stm32f7xx_hal_dma2d.c:871:19:HAL_DMA2D_Suspend 4 +stm32f7xx_hal_dma2d.c:920:19:HAL_DMA2D_Resume 2 +stm32f7xx_hal_dma2d.c:948:19:HAL_DMA2D_EnableCLUT 3 +stm32f7xx_hal_dma2d.c:984:19:HAL_DMA2D_CLUTStartLoad 3 +stm32f7xx_hal_dma2d.c:1038:19:HAL_DMA2D_CLUTStartLoad_IT 3 +stm32f7xx_hal_dma2d.c:1102:19:HAL_DMA2D_CLUTLoad 3 +stm32f7xx_hal_dma2d.c:1159:19:HAL_DMA2D_CLUTLoad_IT 3 +stm32f7xx_hal_dma2d.c:1217:19:HAL_DMA2D_CLUTLoading_Abort 4 +stm32f7xx_hal_dma2d.c:1274:19:HAL_DMA2D_CLUTLoading_Suspend 9 +stm32f7xx_hal_dma2d.c:1339:19:HAL_DMA2D_CLUTLoading_Resume 6 +stm32f7xx_hal_dma2d.c:1382:19:HAL_DMA2D_PollForTransfer 18 +stm32f7xx_hal_dma2d.c:1510:6:HAL_DMA2D_IRQHandler 17 +stm32f7xx_hal_dma2d.c:1680:13:HAL_DMA2D_LineEventCallback 1 +stm32f7xx_hal_dma2d.c:1696:13:HAL_DMA2D_CLUTLoadingCpltCallback 1 +stm32f7xx_hal_dma2d.c:1739:19:HAL_DMA2D_ConfigLayer 9 +stm32f7xx_hal_dma2d.c:1846:19:HAL_DMA2D_ConfigCLUT 3 +stm32f7xx_hal_dma2d.c:1900:19:HAL_DMA2D_ProgramLineEvent 3 +stm32f7xx_hal_dma2d.c:1936:19:HAL_DMA2D_EnableDeadTime 2 +stm32f7xx_hal_dma2d.c:1959:19:HAL_DMA2D_DisableDeadTime 2 +stm32f7xx_hal_dma2d.c:1985:19:HAL_DMA2D_ConfigDeadTime 2 +stm32f7xx_hal_dma2d.c:2030:24:HAL_DMA2D_GetState 1 +stm32f7xx_hal_dma2d.c:2041:10:HAL_DMA2D_GetError 1 +stm32f7xx_hal_dma2d.c:2069:13:DMA2D_SetConfig 6 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d new file mode 100644 index 0000000..b46e9bf --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o new file mode 100644 index 0000000..4b08678 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su new file mode 100644 index 0000000..03f3ac7 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su @@ -0,0 +1,32 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:238:19:HAL_DMA2D_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:316:19:HAL_DMA2D_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:406:13:HAL_DMA2D_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:422:13:HAL_DMA2D_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:678:19:HAL_DMA2D_Start 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:714:19:HAL_DMA2D_Start_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:751:19:HAL_DMA2D_BlendingStart 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:788:19:HAL_DMA2D_BlendingStart_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:822:19:HAL_DMA2D_Abort 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:871:19:HAL_DMA2D_Suspend 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:920:19:HAL_DMA2D_Resume 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:948:19:HAL_DMA2D_EnableCLUT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:984:19:HAL_DMA2D_CLUTStartLoad 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1038:19:HAL_DMA2D_CLUTStartLoad_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1102:19:HAL_DMA2D_CLUTLoad 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1159:19:HAL_DMA2D_CLUTLoad_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1217:19:HAL_DMA2D_CLUTLoading_Abort 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1274:19:HAL_DMA2D_CLUTLoading_Suspend 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1339:19:HAL_DMA2D_CLUTLoading_Resume 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1382:19:HAL_DMA2D_PollForTransfer 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1510:6:HAL_DMA2D_IRQHandler 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1680:13:HAL_DMA2D_LineEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1696:13:HAL_DMA2D_CLUTLoadingCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1739:19:HAL_DMA2D_ConfigLayer 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1846:19:HAL_DMA2D_ConfigCLUT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1900:19:HAL_DMA2D_ProgramLineEvent 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1936:19:HAL_DMA2D_EnableDeadTime 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1959:19:HAL_DMA2D_DisableDeadTime 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:1985:19:HAL_DMA2D_ConfigDeadTime 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:2030:24:HAL_DMA2D_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:2041:10:HAL_DMA2D_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c:2069:13:DMA2D_SetConfig 48 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.cyclo new file mode 100644 index 0000000..d95bb49 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.cyclo @@ -0,0 +1,4 @@ +stm32f7xx_hal_dma_ex.c:102:19:HAL_DMAEx_MultiBufferStart 4 +stm32f7xx_hal_dma_ex.c:156:19:HAL_DMAEx_MultiBufferStart_IT 261 +stm32f7xx_hal_dma_ex.c:234:19:HAL_DMAEx_ChangeMemory 2 +stm32f7xx_hal_dma_ex.c:271:13:DMA_MultiBufferSetConfig 2 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d new file mode 100644 index 0000000..8223b87 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o new file mode 100644 index 0000000..3880b3d Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su new file mode 100644 index 0000000..be4e912 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su @@ -0,0 +1,4 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c:102:19:HAL_DMAEx_MultiBufferStart 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c:156:19:HAL_DMAEx_MultiBufferStart_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c:234:19:HAL_DMAEx_ChangeMemory 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c:271:13:DMA_MultiBufferSetConfig 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d new file mode 100644 index 0000000..e31258a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o new file mode 100644 index 0000000..b85b376 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.cyclo new file mode 100644 index 0000000..8e3aa42 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.cyclo @@ -0,0 +1,57 @@ +stm32f7xx_hal_eth.c:335:19:HAL_ETH_Init 5 +stm32f7xx_hal_eth.c:421:19:HAL_ETH_DeInit 1 +stm32f7xx_hal_eth.c:454:13:HAL_ETH_MspInit 1 +stm32f7xx_hal_eth.c:469:13:HAL_ETH_MspDeInit 1 +stm32f7xx_hal_eth.c:697:19:HAL_ETH_Start 2 +stm32f7xx_hal_eth.c:754:19:HAL_ETH_Start_IT 2 +stm32f7xx_hal_eth.c:831:19:HAL_ETH_Stop 2 +stm32f7xx_hal_eth.c:883:19:HAL_ETH_Stop_IT 3 +stm32f7xx_hal_eth.c:952:19:HAL_ETH_Transmit 10 +stm32f7xx_hal_eth.c:1027:19:HAL_ETH_Transmit_IT 6 +stm32f7xx_hal_eth.c:1079:19:HAL_ETH_ReadData 14 +stm32f7xx_hal_eth.c:1194:13:ETH_UpdateDescriptor 9 +stm32f7xx_hal_eth.c:1274:19:HAL_ETH_RegisterRxAllocateCallback 2 +stm32f7xx_hal_eth.c:1295:19:HAL_ETH_UnRegisterRxAllocateCallback 1 +stm32f7xx_hal_eth.c:1308:13:HAL_ETH_RxAllocateCallback 1 +stm32f7xx_hal_eth.c:1325:13:HAL_ETH_RxLinkCallback 1 +stm32f7xx_hal_eth.c:1344:19:HAL_ETH_RegisterRxLinkCallback 2 +stm32f7xx_hal_eth.c:1364:19:HAL_ETH_UnRegisterRxLinkCallback 1 +stm32f7xx_hal_eth.c:1379:19:HAL_ETH_GetRxDataErrorCode 1 +stm32f7xx_hal_eth.c:1394:19:HAL_ETH_RegisterTxFreeCallback 2 +stm32f7xx_hal_eth.c:1414:19:HAL_ETH_UnRegisterTxFreeCallback 1 +stm32f7xx_hal_eth.c:1427:13:HAL_ETH_TxFreeCallback 1 +stm32f7xx_hal_eth.c:1442:19:HAL_ETH_ReleaseTxPacket 6 +stm32f7xx_hal_eth.c:1869:6:HAL_ETH_IRQHandler 10 +stm32f7xx_hal_eth.c:1988:13:HAL_ETH_TxCpltCallback 1 +stm32f7xx_hal_eth.c:2003:13:HAL_ETH_RxCpltCallback 1 +stm32f7xx_hal_eth.c:2018:13:HAL_ETH_ErrorCallback 1 +stm32f7xx_hal_eth.c:2033:13:HAL_ETH_PMTCallback 1 +stm32f7xx_hal_eth.c:2049:13:HAL_ETH_WakeUpCallback 1 +stm32f7xx_hal_eth.c:2067:19:HAL_ETH_ReadPHYRegister 3 +stm32f7xx_hal_eth.c:2119:19:HAL_ETH_WritePHYRegister 3 +stm32f7xx_hal_eth.c:2187:19:HAL_ETH_GetMACConfig 2 +stm32f7xx_hal_eth.c:2230:19:HAL_ETH_GetDMAConfig 2 +stm32f7xx_hal_eth.c:2268:19:HAL_ETH_SetMACConfig 3 +stm32f7xx_hal_eth.c:2295:19:HAL_ETH_SetDMAConfig 3 +stm32f7xx_hal_eth.c:2320:6:HAL_ETH_SetMDIOClockRange 9 +stm32f7xx_hal_eth.c:2372:19:HAL_ETH_SetMACFilterConfig 3 +stm32f7xx_hal_eth.c:2413:19:HAL_ETH_GetMACFilterConfig 2 +stm32f7xx_hal_eth.c:2450:19:HAL_ETH_SetSourceMACAddrMatch 2 +stm32f7xx_hal_eth.c:2485:19:HAL_ETH_SetHashTable 2 +stm32f7xx_hal_eth.c:2521:6:HAL_ETH_SetRxVLANIdentifier 2 +stm32f7xx_hal_eth.c:2549:6:HAL_ETH_EnterPowerDownMode 1 +stm32f7xx_hal_eth.c:2567:6:HAL_ETH_ExitPowerDownMode 2 +stm32f7xx_hal_eth.c:2604:19:HAL_ETH_SetWakeUpFilter 3 +stm32f7xx_hal_eth.c:2653:22:HAL_ETH_GetState 1 +stm32f7xx_hal_eth.c:2664:10:HAL_ETH_GetError 1 +stm32f7xx_hal_eth.c:2675:10:HAL_ETH_GetDMAError 1 +stm32f7xx_hal_eth.c:2686:10:HAL_ETH_GetMACError 1 +stm32f7xx_hal_eth.c:2697:10:HAL_ETH_GetMACWakeUpSource 1 +stm32f7xx_hal_eth.c:2720:13:ETH_FlushTransmitFIFO 1 +stm32f7xx_hal_eth.c:2734:13:ETH_SetMACConfig 9 +stm32f7xx_hal_eth.c:2791:13:ETH_SetDMAConfig 3 +stm32f7xx_hal_eth.c:2845:13:ETH_MACDMAConfig 1 +stm32f7xx_hal_eth.c:2909:13:ETH_MACAddressConfig 1 +stm32f7xx_hal_eth.c:2934:13:ETH_DMATxDescListInit 3 +stm32f7xx_hal_eth.c:2980:13:ETH_DMARxDescListInit 3 +stm32f7xx_hal_eth.c:3037:17:ETH_Prepare_Tx_Descriptors 14 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.d new file mode 100644 index 0000000..c987073 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o new file mode 100644 index 0000000..98d6b92 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.su new file mode 100644 index 0000000..2c504c3 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.su @@ -0,0 +1,57 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:335:19:HAL_ETH_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:421:19:HAL_ETH_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:454:13:HAL_ETH_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:469:13:HAL_ETH_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:697:19:HAL_ETH_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:754:19:HAL_ETH_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:831:19:HAL_ETH_Stop 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:883:19:HAL_ETH_Stop_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:952:19:HAL_ETH_Transmit 32 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1027:19:HAL_ETH_Transmit_IT 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1079:19:HAL_ETH_ReadData 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1194:13:ETH_UpdateDescriptor 40 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1274:19:HAL_ETH_RegisterRxAllocateCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1295:19:HAL_ETH_UnRegisterRxAllocateCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1308:13:HAL_ETH_RxAllocateCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1325:13:HAL_ETH_RxLinkCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1344:19:HAL_ETH_RegisterRxLinkCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1364:19:HAL_ETH_UnRegisterRxLinkCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1379:19:HAL_ETH_GetRxDataErrorCode 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1394:19:HAL_ETH_RegisterTxFreeCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1414:19:HAL_ETH_UnRegisterTxFreeCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1427:13:HAL_ETH_TxFreeCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1442:19:HAL_ETH_ReleaseTxPacket 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1869:6:HAL_ETH_IRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:1988:13:HAL_ETH_TxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2003:13:HAL_ETH_RxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2018:13:HAL_ETH_ErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2033:13:HAL_ETH_PMTCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2049:13:HAL_ETH_WakeUpCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2067:19:HAL_ETH_ReadPHYRegister 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2119:19:HAL_ETH_WritePHYRegister 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2187:19:HAL_ETH_GetMACConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2230:19:HAL_ETH_GetDMAConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2268:19:HAL_ETH_SetMACConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2295:19:HAL_ETH_SetDMAConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2320:6:HAL_ETH_SetMDIOClockRange 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2372:19:HAL_ETH_SetMACFilterConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2413:19:HAL_ETH_GetMACFilterConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2450:19:HAL_ETH_SetSourceMACAddrMatch 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2485:19:HAL_ETH_SetHashTable 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2521:6:HAL_ETH_SetRxVLANIdentifier 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2549:6:HAL_ETH_EnterPowerDownMode 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2567:6:HAL_ETH_ExitPowerDownMode 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2604:19:HAL_ETH_SetWakeUpFilter 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2653:22:HAL_ETH_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2664:10:HAL_ETH_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2675:10:HAL_ETH_GetDMAError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2686:10:HAL_ETH_GetMACError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2697:10:HAL_ETH_GetMACWakeUpSource 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2720:13:ETH_FlushTransmitFIFO 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2734:13:ETH_SetMACConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2791:13:ETH_SetDMAConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2845:13:ETH_MACDMAConfig 160 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2909:13:ETH_MACAddressConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2934:13:ETH_DMATxDescListInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:2980:13:ETH_DMARxDescListInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c:3037:17:ETH_Prepare_Tx_Descriptors 56 static,ignoring_inline_asm diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.cyclo new file mode 100644 index 0000000..4373638 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +stm32f7xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 9 +stm32f7xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 9 +stm32f7xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 4 +stm32f7xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 2 +stm32f7xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 2 +stm32f7xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 3 +stm32f7xx_hal_exti.c:466:10:HAL_EXTI_GetPending 1 +stm32f7xx_hal_exti.c:495:6:HAL_EXTI_ClearPending 1 +stm32f7xx_hal_exti.c:516:6:HAL_EXTI_GenerateSWI 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d new file mode 100644 index 0000000..c38f2f6 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o new file mode 100644 index 0000000..f5d2c71 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su new file mode 100644 index 0000000..df3941d --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:495:6:HAL_EXTI_ClearPending 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c:516:6:HAL_EXTI_GenerateSWI 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.cyclo new file mode 100644 index 0000000..d510fe5 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.cyclo @@ -0,0 +1,17 @@ +stm32f7xx_hal_flash.c:162:19:HAL_FLASH_Program 7 +stm32f7xx_hal_flash.c:231:19:HAL_FLASH_Program_IT 6 +stm32f7xx_hal_flash.c:293:6:HAL_FLASH_IRQHandler 13 +stm32f7xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 1 +stm32f7xx_hal_flash.c:446:13:HAL_FLASH_OperationErrorCallback 1 +stm32f7xx_hal_flash.c:478:19:HAL_FLASH_Unlock 3 +stm32f7xx_hal_flash.c:502:19:HAL_FLASH_Lock 1 +stm32f7xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 2 +stm32f7xx_hal_flash.c:534:19:HAL_FLASH_OB_Lock 1 +stm32f7xx_hal_flash.c:546:19:HAL_FLASH_OB_Launch 1 +stm32f7xx_hal_flash.c:582:10:HAL_FLASH_GetError 1 +stm32f7xx_hal_flash.c:596:19:FLASH_WaitForLastOperation 7 +stm32f7xx_hal_flash.c:651:13:FLASH_Program_DoubleWord 1 +stm32f7xx_hal_flash.c:688:13:FLASH_Program_Word 1 +stm32f7xx_hal_flash.c:717:13:FLASH_Program_HalfWord 1 +stm32f7xx_hal_flash.c:747:13:FLASH_Program_Byte 1 +stm32f7xx_hal_flash.c:768:13:FLASH_SetErrorCode 6 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d new file mode 100644 index 0000000..7597c9d --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o new file mode 100644 index 0000000..d22a562 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su new file mode 100644 index 0000000..dfa85a0 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su @@ -0,0 +1,17 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:162:19:HAL_FLASH_Program 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:231:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:293:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:446:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:478:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:502:19:HAL_FLASH_Lock 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:534:19:HAL_FLASH_OB_Lock 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:546:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:582:10:HAL_FLASH_GetError 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:596:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:651:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:688:13:FLASH_Program_Word 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:717:13:FLASH_Program_HalfWord 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:747:13:FLASH_Program_Byte 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c:768:13:FLASH_SetErrorCode 4 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.cyclo new file mode 100644 index 0000000..cace406 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.cyclo @@ -0,0 +1,17 @@ +stm32f7xx_hal_flash_ex.c:156:19:HAL_FLASHEx_Erase 6 +stm32f7xx_hal_flash_ex.c:229:19:HAL_FLASHEx_Erase_IT 3 +stm32f7xx_hal_flash_ex.c:285:19:HAL_FLASHEx_OBProgram 9 +stm32f7xx_hal_flash_ex.c:384:6:HAL_FLASHEx_OBGetConfig 1 +stm32f7xx_hal_flash_ex.c:639:13:FLASH_MassErase 1 +stm32f7xx_hal_flash_ex.c:670:6:FLASH_Erase_Sector 4 +stm32f7xx_hal_flash_ex.c:711:17:FLASH_OB_GetWRP 1 +stm32f7xx_hal_flash_ex.c:745:26:FLASH_OB_UserConfig 2 +stm32f7xx_hal_flash_ex.c:783:17:FLASH_OB_GetUser 1 +stm32f7xx_hal_flash_ex.c:806:26:FLASH_OB_EnableWRP 2 +stm32f7xx_hal_flash_ex.c:842:26:FLASH_OB_DisableWRP 2 +stm32f7xx_hal_flash_ex.c:873:26:FLASH_OB_RDP_LevelConfig 2 +stm32f7xx_hal_flash_ex.c:901:26:FLASH_OB_BOR_LevelConfig 1 +stm32f7xx_hal_flash_ex.c:932:26:FLASH_OB_BootAddressConfig 3 +stm32f7xx_hal_flash_ex.c:965:16:FLASH_OB_GetRDP 3 +stm32f7xx_hal_flash_ex.c:993:17:FLASH_OB_GetBOR 1 +stm32f7xx_hal_flash_ex.c:1016:17:FLASH_OB_GetBootAddress 2 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d new file mode 100644 index 0000000..8c0c6be --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o new file mode 100644 index 0000000..782efc2 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su new file mode 100644 index 0000000..2b8712c --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su @@ -0,0 +1,17 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:156:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:229:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:285:19:HAL_FLASHEx_OBProgram 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:384:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:639:13:FLASH_MassErase 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:670:6:FLASH_Erase_Sector 24 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:711:17:FLASH_OB_GetWRP 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:745:26:FLASH_OB_UserConfig 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:783:17:FLASH_OB_GetUser 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:806:26:FLASH_OB_EnableWRP 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:842:26:FLASH_OB_DisableWRP 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:873:26:FLASH_OB_RDP_LevelConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:901:26:FLASH_OB_BOR_LevelConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:932:26:FLASH_OB_BootAddressConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:965:16:FLASH_OB_GetRDP 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:993:17:FLASH_OB_GetBOR 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c:1016:17:FLASH_OB_GetBootAddress 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.cyclo new file mode 100644 index 0000000..22f5627 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +stm32f7xx_hal_gpio.c:162:6:HAL_GPIO_Init 22 +stm32f7xx_hal_gpio.c:291:6:HAL_GPIO_DeInit 14 +stm32f7xx_hal_gpio.c:370:15:HAL_GPIO_ReadPin 2 +stm32f7xx_hal_gpio.c:404:6:HAL_GPIO_WritePin 2 +stm32f7xx_hal_gpio.c:426:6:HAL_GPIO_TogglePin 1 +stm32f7xx_hal_gpio.c:451:19:HAL_GPIO_LockPin 2 +stm32f7xx_hal_gpio.c:485:6:HAL_GPIO_EXTI_IRQHandler 2 +stm32f7xx_hal_gpio.c:500:13:HAL_GPIO_EXTI_Callback 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d new file mode 100644 index 0000000..9fe27b3 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o new file mode 100644 index 0000000..8939abd Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su new file mode 100644 index 0000000..c2ced84 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:162:6:HAL_GPIO_Init 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:291:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:370:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:404:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:426:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:451:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:485:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c:500:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.cyclo new file mode 100644 index 0000000..39d87c2 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.cyclo @@ -0,0 +1,81 @@ +stm32f7xx_hal_i2c.c:528:19:HAL_I2C_Init 5 +stm32f7xx_hal_i2c.c:638:19:HAL_I2C_DeInit 2 +stm32f7xx_hal_i2c.c:684:13:HAL_I2C_MspInit 1 +stm32f7xx_hal_i2c.c:700:13:HAL_I2C_MspDeInit 1 +stm32f7xx_hal_i2c.c:1107:19:HAL_I2C_Master_Transmit 12 +stm32f7xx_hal_i2c.c:1226:19:HAL_I2C_Master_Receive 12 +stm32f7xx_hal_i2c.c:1344:19:HAL_I2C_Slave_Transmit 14 +stm32f7xx_hal_i2c.c:1487:19:HAL_I2C_Slave_Receive 12 +stm32f7xx_hal_i2c.c:1617:19:HAL_I2C_Master_Transmit_IT 5 +stm32f7xx_hal_i2c.c:1688:19:HAL_I2C_Master_Receive_IT 5 +stm32f7xx_hal_i2c.c:1757:19:HAL_I2C_Slave_Transmit_IT 3 +stm32f7xx_hal_i2c.c:1807:19:HAL_I2C_Slave_Receive_IT 3 +stm32f7xx_hal_i2c.c:1859:19:HAL_I2C_Master_Transmit_DMA 8 +stm32f7xx_hal_i2c.c:2006:19:HAL_I2C_Master_Receive_DMA 8 +stm32f7xx_hal_i2c.c:2151:19:HAL_I2C_Slave_Transmit_DMA 7 +stm32f7xx_hal_i2c.c:2255:19:HAL_I2C_Slave_Receive_DMA 7 +stm32f7xx_hal_i2c.c:2363:19:HAL_I2C_Mem_Write 15 +stm32f7xx_hal_i2c.c:2500:19:HAL_I2C_Mem_Read 15 +stm32f7xx_hal_i2c.c:2637:19:HAL_I2C_Mem_Write_IT 7 +stm32f7xx_hal_i2c.c:2724:19:HAL_I2C_Mem_Read_IT 7 +stm32f7xx_hal_i2c.c:2810:19:HAL_I2C_Mem_Write_DMA 10 +stm32f7xx_hal_i2c.c:2956:19:HAL_I2C_Mem_Read_DMA 10 +stm32f7xx_hal_i2c.c:3101:19:HAL_I2C_IsDeviceReady 16 +stm32f7xx_hal_i2c.c:3243:19:HAL_I2C_Master_Seq_Transmit_IT 9 +stm32f7xx_hal_i2c.c:3334:19:HAL_I2C_Master_Seq_Transmit_DMA 12 +stm32f7xx_hal_i2c.c:3502:19:HAL_I2C_Master_Seq_Receive_IT 9 +stm32f7xx_hal_i2c.c:3589:19:HAL_I2C_Master_Seq_Receive_DMA 12 +stm32f7xx_hal_i2c.c:3755:19:HAL_I2C_Slave_Seq_Transmit_IT 11 +stm32f7xx_hal_i2c.c:3855:19:HAL_I2C_Slave_Seq_Transmit_DMA 17 +stm32f7xx_hal_i2c.c:4039:19:HAL_I2C_Slave_Seq_Receive_IT 11 +stm32f7xx_hal_i2c.c:4139:19:HAL_I2C_Slave_Seq_Receive_DMA 17 +stm32f7xx_hal_i2c.c:4319:19:HAL_I2C_EnableListen_IT 2 +stm32f7xx_hal_i2c.c:4343:19:HAL_I2C_DisableListen_IT 2 +stm32f7xx_hal_i2c.c:4376:19:HAL_I2C_Master_Abort_IT 5 +stm32f7xx_hal_i2c.c:4438:6:HAL_I2C_EV_IRQHandler 2 +stm32f7xx_hal_i2c.c:4457:6:HAL_I2C_ER_IRQHandler 8 +stm32f7xx_hal_i2c.c:4509:13:HAL_I2C_MasterTxCpltCallback 1 +stm32f7xx_hal_i2c.c:4525:13:HAL_I2C_MasterRxCpltCallback 1 +stm32f7xx_hal_i2c.c:4540:13:HAL_I2C_SlaveTxCpltCallback 1 +stm32f7xx_hal_i2c.c:4556:13:HAL_I2C_SlaveRxCpltCallback 1 +stm32f7xx_hal_i2c.c:4574:13:HAL_I2C_AddrCallback 1 +stm32f7xx_hal_i2c.c:4592:13:HAL_I2C_ListenCpltCallback 1 +stm32f7xx_hal_i2c.c:4608:13:HAL_I2C_MemTxCpltCallback 1 +stm32f7xx_hal_i2c.c:4624:13:HAL_I2C_MemRxCpltCallback 1 +stm32f7xx_hal_i2c.c:4640:13:HAL_I2C_ErrorCallback 1 +stm32f7xx_hal_i2c.c:4656:13:HAL_I2C_AbortCpltCallback 1 +stm32f7xx_hal_i2c.c:4691:22:HAL_I2C_GetState 1 +stm32f7xx_hal_i2c.c:4703:21:HAL_I2C_GetMode 1 +stm32f7xx_hal_i2c.c:4714:10:HAL_I2C_GetError 1 +stm32f7xx_hal_i2c.c:4739:26:I2C_Master_ISR_IT 22 +stm32f7xx_hal_i2c.c:4885:26:I2C_Mem_ISR_IT 20 +stm32f7xx_hal_i2c.c:5022:26:I2C_Slave_ISR_IT 25 +stm32f7xx_hal_i2c.c:5163:26:I2C_Master_ISR_DMA 18 +stm32f7xx_hal_i2c.c:5303:26:I2C_Mem_ISR_DMA 18 +stm32f7xx_hal_i2c.c:5442:26:I2C_Slave_ISR_DMA 27 +stm32f7xx_hal_i2c.c:5587:26:I2C_RequestMemoryWrite 5 +stm32f7xx_hal_i2c.c:5642:26:I2C_RequestMemoryRead 5 +stm32f7xx_hal_i2c.c:5691:13:I2C_ITAddrCplt 5 +stm32f7xx_hal_i2c.c:5786:13:I2C_ITMasterSeqCplt 2 +stm32f7xx_hal_i2c.c:5839:13:I2C_ITSlaveSeqCplt 5 +stm32f7xx_hal_i2c.c:5913:13:I2C_ITMasterCplt 12 +stm32f7xx_hal_i2c.c:6056:13:I2C_ITSlaveCplt 16 +stm32f7xx_hal_i2c.c:6215:13:I2C_ITListenCplt 3 +stm32f7xx_hal_i2c.c:6266:13:I2C_ITError 17 +stm32f7xx_hal_i2c.c:6378:13:I2C_TreatErrorCallback 2 +stm32f7xx_hal_i2c.c:6416:13:I2C_Flush_TXDR 3 +stm32f7xx_hal_i2c.c:6437:13:I2C_DMAMasterTransmitCplt 4 +stm32f7xx_hal_i2c.c:6487:13:I2C_DMASlaveTransmitCplt 3 +stm32f7xx_hal_i2c.c:6515:13:I2C_DMAMasterReceiveCplt 4 +stm32f7xx_hal_i2c.c:6565:13:I2C_DMASlaveReceiveCplt 3 +stm32f7xx_hal_i2c.c:6593:13:I2C_DMAError 7 +stm32f7xx_hal_i2c.c:6632:13:I2C_DMAAbort 3 +stm32f7xx_hal_i2c.c:6661:26:I2C_WaitOnFlagUntilTimeout 5 +stm32f7xx_hal_i2c.c:6692:26:I2C_WaitOnTXISFlagUntilTimeout 6 +stm32f7xx_hal_i2c.c:6730:26:I2C_WaitOnSTOPFlagUntilTimeout 5 +stm32f7xx_hal_i2c.c:6765:26:I2C_WaitOnRXNEFlagUntilTimeout 9 +stm32f7xx_hal_i2c.c:6838:26:I2C_IsErrorOccurred 17 +stm32f7xx_hal_i2c.c:6979:13:I2C_TransferConfig 1 +stm32f7xx_hal_i2c.c:7006:13:I2C_Enable_IRQ 12 +stm32f7xx_hal_i2c.c:7083:13:I2C_Disable_IRQ 9 +stm32f7xx_hal_i2c.c:7146:13:I2C_ConvertOtherXferOptions 3 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d new file mode 100644 index 0000000..e8aa16e --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o new file mode 100644 index 0000000..0b0ca10 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su new file mode 100644 index 0000000..d7a155a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su @@ -0,0 +1,81 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:528:19:HAL_I2C_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:638:19:HAL_I2C_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:684:13:HAL_I2C_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:700:13:HAL_I2C_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1107:19:HAL_I2C_Master_Transmit 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1226:19:HAL_I2C_Master_Receive 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1344:19:HAL_I2C_Slave_Transmit 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1487:19:HAL_I2C_Slave_Receive 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1617:19:HAL_I2C_Master_Transmit_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1688:19:HAL_I2C_Master_Receive_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1757:19:HAL_I2C_Slave_Transmit_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1807:19:HAL_I2C_Slave_Receive_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:1859:19:HAL_I2C_Master_Transmit_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2006:19:HAL_I2C_Master_Receive_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2151:19:HAL_I2C_Slave_Transmit_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2255:19:HAL_I2C_Slave_Receive_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2363:19:HAL_I2C_Mem_Write 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2500:19:HAL_I2C_Mem_Read 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2637:19:HAL_I2C_Mem_Write_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2724:19:HAL_I2C_Mem_Read_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2810:19:HAL_I2C_Mem_Write_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:2956:19:HAL_I2C_Mem_Read_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3101:19:HAL_I2C_IsDeviceReady 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3243:19:HAL_I2C_Master_Seq_Transmit_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3334:19:HAL_I2C_Master_Seq_Transmit_DMA 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3502:19:HAL_I2C_Master_Seq_Receive_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3589:19:HAL_I2C_Master_Seq_Receive_DMA 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3755:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:3855:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4039:19:HAL_I2C_Slave_Seq_Receive_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4139:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4319:19:HAL_I2C_EnableListen_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4343:19:HAL_I2C_DisableListen_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4376:19:HAL_I2C_Master_Abort_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4438:6:HAL_I2C_EV_IRQHandler 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4457:6:HAL_I2C_ER_IRQHandler 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4509:13:HAL_I2C_MasterTxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4525:13:HAL_I2C_MasterRxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4540:13:HAL_I2C_SlaveTxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4556:13:HAL_I2C_SlaveRxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4574:13:HAL_I2C_AddrCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4592:13:HAL_I2C_ListenCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4608:13:HAL_I2C_MemTxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4624:13:HAL_I2C_MemRxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4640:13:HAL_I2C_ErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4656:13:HAL_I2C_AbortCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4691:22:HAL_I2C_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4703:21:HAL_I2C_GetMode 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4714:10:HAL_I2C_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4739:26:I2C_Master_ISR_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:4885:26:I2C_Mem_ISR_IT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5022:26:I2C_Slave_ISR_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5163:26:I2C_Master_ISR_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5303:26:I2C_Mem_ISR_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5442:26:I2C_Slave_ISR_DMA 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5587:26:I2C_RequestMemoryWrite 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5642:26:I2C_RequestMemoryRead 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5691:13:I2C_ITAddrCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5786:13:I2C_ITMasterSeqCplt 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5839:13:I2C_ITSlaveSeqCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:5913:13:I2C_ITMasterCplt 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6056:13:I2C_ITSlaveCplt 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6215:13:I2C_ITListenCplt 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6266:13:I2C_ITError 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6378:13:I2C_TreatErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6416:13:I2C_Flush_TXDR 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6437:13:I2C_DMAMasterTransmitCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6487:13:I2C_DMASlaveTransmitCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6515:13:I2C_DMAMasterReceiveCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6565:13:I2C_DMASlaveReceiveCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6593:13:I2C_DMAError 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6632:13:I2C_DMAAbort 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6661:26:I2C_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6692:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6730:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6765:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6838:26:I2C_IsErrorOccurred 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:6979:13:I2C_TransferConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:7006:13:I2C_Enable_IRQ 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:7083:13:I2C_Disable_IRQ 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c:7146:13:I2C_ConvertOtherXferOptions 16 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.cyclo new file mode 100644 index 0000000..44c905a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.cyclo @@ -0,0 +1,4 @@ +stm32f7xx_hal_i2c_ex.c:91:19:HAL_I2CEx_ConfigAnalogFilter 3 +stm32f7xx_hal_i2c_ex.c:135:19:HAL_I2CEx_ConfigDigitalFilter 3 +stm32f7xx_hal_i2c_ex.c:215:6:HAL_I2CEx_EnableFastModePlus 1 +stm32f7xx_hal_i2c_ex.c:244:6:HAL_I2CEx_DisableFastModePlus 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d new file mode 100644 index 0000000..0b7d1c5 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o new file mode 100644 index 0000000..380c420 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su new file mode 100644 index 0000000..68d2d7a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su @@ -0,0 +1,4 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c:91:19:HAL_I2CEx_ConfigAnalogFilter 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c:135:19:HAL_I2CEx_ConfigDigitalFilter 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c:215:6:HAL_I2CEx_EnableFastModePlus 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c:244:6:HAL_I2CEx_DisableFastModePlus 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.cyclo new file mode 100644 index 0000000..b5a1d90 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.cyclo @@ -0,0 +1,40 @@ +stm32f7xx_hal_ltdc.c:213:19:HAL_LTDC_Init 3 +stm32f7xx_hal_ltdc.c:323:19:HAL_LTDC_DeInit 4 +stm32f7xx_hal_ltdc.c:393:13:HAL_LTDC_MspInit 1 +stm32f7xx_hal_ltdc.c:409:13:HAL_LTDC_MspDeInit 1 +stm32f7xx_hal_ltdc.c:625:6:HAL_LTDC_IRQHandler 9 +stm32f7xx_hal_ltdc.c:743:13:HAL_LTDC_ErrorCallback 1 +stm32f7xx_hal_ltdc.c:759:13:HAL_LTDC_LineEventCallback 1 +stm32f7xx_hal_ltdc.c:775:13:HAL_LTDC_ReloadEventCallback 1 +stm32f7xx_hal_ltdc.c:825:19:HAL_LTDC_ConfigLayer 2 +stm32f7xx_hal_ltdc.c:875:19:HAL_LTDC_ConfigColorKeying 2 +stm32f7xx_hal_ltdc.c:913:19:HAL_LTDC_ConfigCLUT 4 +stm32f7xx_hal_ltdc.c:964:19:HAL_LTDC_EnableColorKeying 2 +stm32f7xx_hal_ltdc.c:999:19:HAL_LTDC_DisableColorKeying 2 +stm32f7xx_hal_ltdc.c:1034:19:HAL_LTDC_EnableCLUT 2 +stm32f7xx_hal_ltdc.c:1069:19:HAL_LTDC_DisableCLUT 2 +stm32f7xx_hal_ltdc.c:1102:19:HAL_LTDC_EnableDither 2 +stm32f7xx_hal_ltdc.c:1129:19:HAL_LTDC_DisableDither 2 +stm32f7xx_hal_ltdc.c:1160:19:HAL_LTDC_SetWindowSize 2 +stm32f7xx_hal_ltdc.c:1216:19:HAL_LTDC_SetWindowPosition 2 +stm32f7xx_hal_ltdc.c:1267:19:HAL_LTDC_SetPixelFormat 2 +stm32f7xx_hal_ltdc.c:1312:19:HAL_LTDC_SetAlpha 2 +stm32f7xx_hal_ltdc.c:1356:19:HAL_LTDC_SetAddress 2 +stm32f7xx_hal_ltdc.c:1405:19:HAL_LTDC_SetPitch 8 +stm32f7xx_hal_ltdc.c:1474:19:HAL_LTDC_ProgramLineEvent 2 +stm32f7xx_hal_ltdc.c:1513:20:HAL_LTDC_Reload 2 +stm32f7xx_hal_ltdc.c:1552:19:HAL_LTDC_ConfigLayer_NoReload 2 +stm32f7xx_hal_ltdc.c:1602:19:HAL_LTDC_SetWindowSize_NoReload 2 +stm32f7xx_hal_ltdc.c:1657:19:HAL_LTDC_SetWindowPosition_NoReload 2 +stm32f7xx_hal_ltdc.c:1707:19:HAL_LTDC_SetPixelFormat_NoReload 2 +stm32f7xx_hal_ltdc.c:1750:19:HAL_LTDC_SetAlpha_NoReload 2 +stm32f7xx_hal_ltdc.c:1793:19:HAL_LTDC_SetAddress_NoReload 2 +stm32f7xx_hal_ltdc.c:1840:19:HAL_LTDC_SetPitch_NoReload 8 +stm32f7xx_hal_ltdc.c:1907:19:HAL_LTDC_ConfigColorKeying_NoReload 2 +stm32f7xx_hal_ltdc.c:1941:19:HAL_LTDC_EnableColorKeying_NoReload 2 +stm32f7xx_hal_ltdc.c:1974:19:HAL_LTDC_DisableColorKeying_NoReload 2 +stm32f7xx_hal_ltdc.c:2007:19:HAL_LTDC_EnableCLUT_NoReload 2 +stm32f7xx_hal_ltdc.c:2040:19:HAL_LTDC_DisableCLUT_NoReload 2 +stm32f7xx_hal_ltdc.c:2089:23:HAL_LTDC_GetState 1 +stm32f7xx_hal_ltdc.c:2100:10:HAL_LTDC_GetError 1 +stm32f7xx_hal_ltdc.c:2126:13:LTDC_SetConfig 7 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d new file mode 100644 index 0000000..e914b0d --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o new file mode 100644 index 0000000..c1c8821 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su new file mode 100644 index 0000000..200a4ae --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su @@ -0,0 +1,40 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:213:19:HAL_LTDC_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:323:19:HAL_LTDC_DeInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:393:13:HAL_LTDC_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:409:13:HAL_LTDC_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:625:6:HAL_LTDC_IRQHandler 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:743:13:HAL_LTDC_ErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:759:13:HAL_LTDC_LineEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:775:13:HAL_LTDC_ReloadEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:825:19:HAL_LTDC_ConfigLayer 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:875:19:HAL_LTDC_ConfigColorKeying 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:913:19:HAL_LTDC_ConfigCLUT 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:964:19:HAL_LTDC_EnableColorKeying 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:999:19:HAL_LTDC_DisableColorKeying 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1034:19:HAL_LTDC_EnableCLUT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1069:19:HAL_LTDC_DisableCLUT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1102:19:HAL_LTDC_EnableDither 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1129:19:HAL_LTDC_DisableDither 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1160:19:HAL_LTDC_SetWindowSize 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1216:19:HAL_LTDC_SetWindowPosition 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1267:19:HAL_LTDC_SetPixelFormat 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1312:19:HAL_LTDC_SetAlpha 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1356:19:HAL_LTDC_SetAddress 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1405:19:HAL_LTDC_SetPitch 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1474:19:HAL_LTDC_ProgramLineEvent 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1513:20:HAL_LTDC_Reload 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1552:19:HAL_LTDC_ConfigLayer_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1602:19:HAL_LTDC_SetWindowSize_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1657:19:HAL_LTDC_SetWindowPosition_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1707:19:HAL_LTDC_SetPixelFormat_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1750:19:HAL_LTDC_SetAlpha_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1793:19:HAL_LTDC_SetAddress_NoReload 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1840:19:HAL_LTDC_SetPitch_NoReload 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1907:19:HAL_LTDC_ConfigColorKeying_NoReload 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1941:19:HAL_LTDC_EnableColorKeying_NoReload 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:1974:19:HAL_LTDC_DisableColorKeying_NoReload 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:2007:19:HAL_LTDC_EnableCLUT_NoReload 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:2040:19:HAL_LTDC_DisableCLUT_NoReload 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:2089:23:HAL_LTDC_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:2100:10:HAL_LTDC_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c:2126:13:LTDC_SetConfig 40 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d new file mode 100644 index 0000000..3bf293d --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o new file mode 100644 index 0000000..6849b92 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.cyclo new file mode 100644 index 0000000..face67e --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.cyclo @@ -0,0 +1,17 @@ +stm32f7xx_hal_pwr.c:99:6:HAL_PWR_DeInit 1 +stm32f7xx_hal_pwr.c:112:6:HAL_PWR_EnableBkUpAccess 1 +stm32f7xx_hal_pwr.c:125:6:HAL_PWR_DisableBkUpAccess 1 +stm32f7xx_hal_pwr.c:259:6:HAL_PWR_ConfigPVD 5 +stm32f7xx_hal_pwr.c:302:6:HAL_PWR_EnablePVD 1 +stm32f7xx_hal_pwr.c:312:6:HAL_PWR_DisablePVD 1 +stm32f7xx_hal_pwr.c:335:6:HAL_PWR_EnableWakeUpPin 1 +stm32f7xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 1 +stm32f7xx_hal_pwr.c:386:6:HAL_PWR_EnterSLEEPMode 2 +stm32f7xx_hal_pwr.c:433:6:HAL_PWR_EnterSTOPMode 2 +stm32f7xx_hal_pwr.c:486:6:HAL_PWR_EnterSTANDBYMode 1 +stm32f7xx_hal_pwr.c:507:6:HAL_PWR_PVD_IRQHandler 2 +stm32f7xx_hal_pwr.c:524:13:HAL_PWR_PVDCallback 1 +stm32f7xx_hal_pwr.c:539:6:HAL_PWR_EnableSleepOnExit 1 +stm32f7xx_hal_pwr.c:551:6:HAL_PWR_DisableSleepOnExit 1 +stm32f7xx_hal_pwr.c:563:6:HAL_PWR_EnableSEVOnPend 1 +stm32f7xx_hal_pwr.c:575:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d new file mode 100644 index 0000000..bf255e0 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o new file mode 100644 index 0000000..a5a3f0d Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su new file mode 100644 index 0000000..a81785a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su @@ -0,0 +1,17 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:99:6:HAL_PWR_DeInit 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:112:6:HAL_PWR_EnableBkUpAccess 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:125:6:HAL_PWR_DisableBkUpAccess 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:259:6:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:302:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:312:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:335:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:386:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:433:6:HAL_PWR_EnterSTOPMode 24 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:486:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:507:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:524:13:HAL_PWR_PVDCallback 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:539:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:551:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:563:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c:575:6:HAL_PWR_DisableSEVOnPend 4 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..7b91566 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.cyclo @@ -0,0 +1,13 @@ +stm32f7xx_hal_pwr_ex.c:134:19:HAL_PWREx_EnableBkUpReg 3 +stm32f7xx_hal_pwr_ex.c:163:19:HAL_PWREx_DisableBkUpReg 3 +stm32f7xx_hal_pwr_ex.c:192:6:HAL_PWREx_EnableFlashPowerDown 1 +stm32f7xx_hal_pwr_ex.c:202:6:HAL_PWREx_DisableFlashPowerDown 1 +stm32f7xx_hal_pwr_ex.c:212:6:HAL_PWREx_EnableMainRegulatorLowVoltage 1 +stm32f7xx_hal_pwr_ex.c:222:6:HAL_PWREx_DisableMainRegulatorLowVoltage 1 +stm32f7xx_hal_pwr_ex.c:232:6:HAL_PWREx_EnableLowRegulatorLowVoltage 1 +stm32f7xx_hal_pwr_ex.c:242:6:HAL_PWREx_DisableLowRegulatorLowVoltage 1 +stm32f7xx_hal_pwr_ex.c:258:19:HAL_PWREx_EnableOverDrive 5 +stm32f7xx_hal_pwr_ex.c:304:19:HAL_PWREx_DisableOverDrive 5 +stm32f7xx_hal_pwr_ex.c:378:19:HAL_PWREx_EnterUnderDriveSTOPMode 4 +stm32f7xx_hal_pwr_ex.c:444:10:HAL_PWREx_GetVoltageRange 1 +stm32f7xx_hal_pwr_ex.c:476:19:HAL_PWREx_ControlVoltageScaling 8 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d new file mode 100644 index 0000000..04a2467 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o new file mode 100644 index 0000000..12be2b6 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su new file mode 100644 index 0000000..8797f54 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su @@ -0,0 +1,13 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:134:19:HAL_PWREx_EnableBkUpReg 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:163:19:HAL_PWREx_DisableBkUpReg 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:192:6:HAL_PWREx_EnableFlashPowerDown 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:202:6:HAL_PWREx_DisableFlashPowerDown 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:212:6:HAL_PWREx_EnableMainRegulatorLowVoltage 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:222:6:HAL_PWREx_DisableMainRegulatorLowVoltage 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:232:6:HAL_PWREx_EnableLowRegulatorLowVoltage 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:242:6:HAL_PWREx_DisableLowRegulatorLowVoltage 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:258:19:HAL_PWREx_EnableOverDrive 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:304:19:HAL_PWREx_DisableOverDrive 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:378:19:HAL_PWREx_EnterUnderDriveSTOPMode 32 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:444:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c:476:19:HAL_PWREx_ControlVoltageScaling 32 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.cyclo new file mode 100644 index 0000000..4142ae7 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.cyclo @@ -0,0 +1,14 @@ +stm32f7xx_hal_rcc.c:196:19:HAL_RCC_DeInit 14 +stm32f7xx_hal_rcc.c:342:19:HAL_RCC_OscConfig 62 +stm32f7xx_hal_rcc.c:722:19:HAL_RCC_ClockConfig 19 +stm32f7xx_hal_rcc.c:903:6:HAL_RCC_MCOConfig 2 +stm32f7xx_hal_rcc.c:957:6:HAL_RCC_EnableCSS 1 +stm32f7xx_hal_rcc.c:966:6:HAL_RCC_DisableCSS 1 +stm32f7xx_hal_rcc.c:1001:10:HAL_RCC_GetSysClockFreq 6 +stm32f7xx_hal_rcc.c:1055:10:HAL_RCC_GetHCLKFreq 1 +stm32f7xx_hal_rcc.c:1066:10:HAL_RCC_GetPCLK1Freq 1 +stm32f7xx_hal_rcc.c:1078:10:HAL_RCC_GetPCLK2Freq 1 +stm32f7xx_hal_rcc.c:1091:6:HAL_RCC_GetOscConfig 8 +stm32f7xx_hal_rcc.c:1173:6:HAL_RCC_GetClockConfig 1 +stm32f7xx_hal_rcc.c:1199:6:HAL_RCC_NMI_IRQHandler 2 +stm32f7xx_hal_rcc.c:1216:13:HAL_RCC_CSSCallback 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d new file mode 100644 index 0000000..4aa9cb0 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o new file mode 100644 index 0000000..aff5eea Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su new file mode 100644 index 0000000..820ba81 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su @@ -0,0 +1,14 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:196:19:HAL_RCC_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:342:19:HAL_RCC_OscConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:722:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:903:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:957:6:HAL_RCC_EnableCSS 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:966:6:HAL_RCC_DisableCSS 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1001:10:HAL_RCC_GetSysClockFreq 96 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1055:10:HAL_RCC_GetHCLKFreq 4 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1066:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1078:10:HAL_RCC_GetPCLK2Freq 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1091:6:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1173:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1199:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c:1216:13:HAL_RCC_CSSCallback 4 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..bed8987 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.cyclo @@ -0,0 +1,7 @@ +stm32f7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 64 +stm32f7xx_hal_rcc_ex.c:665:6:HAL_RCCEx_GetPeriphCLKConfig 2 +stm32f7xx_hal_rcc_ex.c:1383:10:HAL_RCCEx_GetPeriphCLKFreq 15 +stm32f7xx_hal_rcc_ex.c:1586:19:HAL_RCCEx_EnablePLLI2S 5 +stm32f7xx_hal_rcc_ex.c:1647:19:HAL_RCCEx_DisablePLLI2S 3 +stm32f7xx_hal_rcc_ex.c:1674:19:HAL_RCCEx_EnablePLLSAI 5 +stm32f7xx_hal_rcc_ex.c:1736:19:HAL_RCCEx_DisablePLLSAI 3 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d new file mode 100644 index 0000000..24d3fa1 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o new file mode 100644 index 0000000..77b236b Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su new file mode 100644 index 0000000..57af89e --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su @@ -0,0 +1,7 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:665:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:1383:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:1586:19:HAL_RCCEx_EnablePLLI2S 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:1647:19:HAL_RCCEx_DisablePLLI2S 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:1674:19:HAL_RCCEx_EnablePLLSAI 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c:1736:19:HAL_RCCEx_DisablePLLSAI 16 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.cyclo new file mode 100644 index 0000000..fca333f --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.cyclo @@ -0,0 +1,26 @@ +stm32f7xx_hal_rtc.c:254:19:HAL_RTC_Init 7 +stm32f7xx_hal_rtc.c:367:19:HAL_RTC_DeInit 3 +stm32f7xx_hal_rtc.c:651:13:HAL_RTC_MspInit 1 +stm32f7xx_hal_rtc.c:667:13:HAL_RTC_MspDeInit 1 +stm32f7xx_hal_rtc.c:708:19:HAL_RTC_SetTime 7 +stm32f7xx_hal_rtc.c:822:19:HAL_RTC_GetTime 2 +stm32f7xx_hal_rtc.c:867:19:HAL_RTC_SetDate 7 +stm32f7xx_hal_rtc.c:956:19:HAL_RTC_GetDate 2 +stm32f7xx_hal_rtc.c:1014:19:HAL_RTC_SetAlarm 10 +stm32f7xx_hal_rtc.c:1211:19:HAL_RTC_SetAlarm_IT 10 +stm32f7xx_hal_rtc.c:1403:19:HAL_RTC_DeactivateAlarm 7 +stm32f7xx_hal_rtc.c:1501:19:HAL_RTC_GetAlarm 3 +stm32f7xx_hal_rtc.c:1552:6:HAL_RTC_AlarmIRQHandler 5 +stm32f7xx_hal_rtc.c:1603:13:HAL_RTC_AlarmAEventCallback 1 +stm32f7xx_hal_rtc.c:1620:19:HAL_RTC_PollForAlarmAEvent 5 +stm32f7xx_hal_rtc.c:1684:19:HAL_RTC_WaitForSynchro 3 +stm32f7xx_hal_rtc.c:1713:6:HAL_RTC_DST_Add1Hour 1 +stm32f7xx_hal_rtc.c:1727:6:HAL_RTC_DST_Sub1Hour 1 +stm32f7xx_hal_rtc.c:1741:6:HAL_RTC_DST_SetStoreOperation 1 +stm32f7xx_hal_rtc.c:1754:6:HAL_RTC_DST_ClearStoreOperation 1 +stm32f7xx_hal_rtc.c:1766:10:HAL_RTC_DST_ReadStoreOperation 1 +stm32f7xx_hal_rtc.c:1795:21:HAL_RTC_GetState 1 +stm32f7xx_hal_rtc.c:1821:19:RTC_EnterInitMode 5 +stm32f7xx_hal_rtc.c:1856:19:RTC_ExitInitMode 3 +stm32f7xx_hal_rtc.c:1882:9:RTC_ByteToBcd2 2 +stm32f7xx_hal_rtc.c:1900:9:RTC_Bcd2ToByte 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d new file mode 100644 index 0000000..ec19e7b --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o new file mode 100644 index 0000000..6372259 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su new file mode 100644 index 0000000..1a3eba9 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su @@ -0,0 +1,26 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:254:19:HAL_RTC_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:367:19:HAL_RTC_DeInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:651:13:HAL_RTC_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:667:13:HAL_RTC_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:708:19:HAL_RTC_SetTime 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:822:19:HAL_RTC_GetTime 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:867:19:HAL_RTC_SetDate 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:956:19:HAL_RTC_GetDate 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1014:19:HAL_RTC_SetAlarm 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1211:19:HAL_RTC_SetAlarm_IT 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1403:19:HAL_RTC_DeactivateAlarm 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1501:19:HAL_RTC_GetAlarm 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1552:6:HAL_RTC_AlarmIRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1603:13:HAL_RTC_AlarmAEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1620:19:HAL_RTC_PollForAlarmAEvent 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1684:19:HAL_RTC_WaitForSynchro 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1713:6:HAL_RTC_DST_Add1Hour 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1727:6:HAL_RTC_DST_Sub1Hour 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1741:6:HAL_RTC_DST_SetStoreOperation 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1754:6:HAL_RTC_DST_ClearStoreOperation 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1766:10:HAL_RTC_DST_ReadStoreOperation 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1795:21:HAL_RTC_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1821:19:RTC_EnterInitMode 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1856:19:RTC_ExitInitMode 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1882:9:RTC_ByteToBcd2 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c:1900:9:RTC_Bcd2ToByte 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.cyclo new file mode 100644 index 0000000..85a9101 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.cyclo @@ -0,0 +1,37 @@ +stm32f7xx_hal_rtc_ex.c:167:19:HAL_RTCEx_SetTimeStamp 2 +stm32f7xx_hal_rtc_ex.c:236:19:HAL_RTCEx_SetTimeStamp_IT 2 +stm32f7xx_hal_rtc_ex.c:299:19:HAL_RTCEx_DeactivateTimeStamp 2 +stm32f7xx_hal_rtc_ex.c:338:19:HAL_RTCEx_SetInternalTimeStamp 2 +stm32f7xx_hal_rtc_ex.c:369:19:HAL_RTCEx_DeactivateInternalTimeStamp 2 +stm32f7xx_hal_rtc_ex.c:405:19:HAL_RTCEx_GetTimeStamp 2 +stm32f7xx_hal_rtc_ex.c:462:19:HAL_RTCEx_SetTamper 20 +stm32f7xx_hal_rtc_ex.c:617:19:HAL_RTCEx_SetTamper_IT 17 +stm32f7xx_hal_rtc_ex.c:766:19:HAL_RTCEx_DeactivateTamper 5 +stm32f7xx_hal_rtc_ex.c:808:6:HAL_RTCEx_TamperTimeStampIRQHandler 9 +stm32f7xx_hal_rtc_ex.c:896:13:HAL_RTCEx_TimeStampEventCallback 1 +stm32f7xx_hal_rtc_ex.c:912:13:HAL_RTCEx_Tamper1EventCallback 1 +stm32f7xx_hal_rtc_ex.c:928:13:HAL_RTCEx_Tamper2EventCallback 1 +stm32f7xx_hal_rtc_ex.c:944:13:HAL_RTCEx_Tamper3EventCallback 1 +stm32f7xx_hal_rtc_ex.c:961:19:HAL_RTCEx_PollForTimeStampEvent 6 +stm32f7xx_hal_rtc_ex.c:1004:19:HAL_RTCEx_PollForTamper1Event 5 +stm32f7xx_hal_rtc_ex.c:1040:19:HAL_RTCEx_PollForTamper2Event 5 +stm32f7xx_hal_rtc_ex.c:1076:19:HAL_RTCEx_PollForTamper3Event 5 +stm32f7xx_hal_rtc_ex.c:1128:19:HAL_RTCEx_SetWakeUpTimer 7 +stm32f7xx_hal_rtc_ex.c:1224:19:HAL_RTCEx_SetWakeUpTimer_IT 7 +stm32f7xx_hal_rtc_ex.c:1323:19:HAL_RTCEx_DeactivateWakeUpTimer 4 +stm32f7xx_hal_rtc_ex.c:1378:10:HAL_RTCEx_GetWakeUpTimer 1 +stm32f7xx_hal_rtc_ex.c:1395:6:HAL_RTCEx_WakeUpTimerIRQHandler 2 +stm32f7xx_hal_rtc_ex.c:1424:13:HAL_RTCEx_WakeUpTimerEventCallback 1 +stm32f7xx_hal_rtc_ex.c:1441:19:HAL_RTCEx_PollForWakeUpTimerEvent 5 +stm32f7xx_hal_rtc_ex.c:1507:6:HAL_RTCEx_BKUPWrite 1 +stm32f7xx_hal_rtc_ex.c:1530:10:HAL_RTCEx_BKUPRead 1 +stm32f7xx_hal_rtc_ex.c:1564:19:HAL_RTCEx_SetSmoothCalib 5 +stm32f7xx_hal_rtc_ex.c:1636:19:HAL_RTCEx_SetSynchroShift 7 +stm32f7xx_hal_rtc_ex.c:1731:19:HAL_RTCEx_SetCalibrationOutPut 2 +stm32f7xx_hal_rtc_ex.c:1770:19:HAL_RTCEx_DeactivateCalibrationOutPut 2 +stm32f7xx_hal_rtc_ex.c:1800:19:HAL_RTCEx_SetRefClock 4 +stm32f7xx_hal_rtc_ex.c:1844:19:HAL_RTCEx_DeactivateRefClock 4 +stm32f7xx_hal_rtc_ex.c:1890:19:HAL_RTCEx_EnableBypassShadow 2 +stm32f7xx_hal_rtc_ex.c:1923:19:HAL_RTCEx_DisableBypassShadow 2 +stm32f7xx_hal_rtc_ex.c:1973:13:HAL_RTCEx_AlarmBEventCallback 1 +stm32f7xx_hal_rtc_ex.c:1990:19:HAL_RTCEx_PollForAlarmBEvent 5 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d new file mode 100644 index 0000000..ac63fff --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o new file mode 100644 index 0000000..3984637 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su new file mode 100644 index 0000000..39c69b2 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su @@ -0,0 +1,37 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:167:19:HAL_RTCEx_SetTimeStamp 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:236:19:HAL_RTCEx_SetTimeStamp_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:299:19:HAL_RTCEx_DeactivateTimeStamp 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:338:19:HAL_RTCEx_SetInternalTimeStamp 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:369:19:HAL_RTCEx_DeactivateInternalTimeStamp 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:405:19:HAL_RTCEx_GetTimeStamp 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:462:19:HAL_RTCEx_SetTamper 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:617:19:HAL_RTCEx_SetTamper_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:766:19:HAL_RTCEx_DeactivateTamper 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:808:6:HAL_RTCEx_TamperTimeStampIRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:896:13:HAL_RTCEx_TimeStampEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:912:13:HAL_RTCEx_Tamper1EventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:928:13:HAL_RTCEx_Tamper2EventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:944:13:HAL_RTCEx_Tamper3EventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:961:19:HAL_RTCEx_PollForTimeStampEvent 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1004:19:HAL_RTCEx_PollForTamper1Event 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1040:19:HAL_RTCEx_PollForTamper2Event 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1076:19:HAL_RTCEx_PollForTamper3Event 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1128:19:HAL_RTCEx_SetWakeUpTimer 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1224:19:HAL_RTCEx_SetWakeUpTimer_IT 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1323:19:HAL_RTCEx_DeactivateWakeUpTimer 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1378:10:HAL_RTCEx_GetWakeUpTimer 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1395:6:HAL_RTCEx_WakeUpTimerIRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1424:13:HAL_RTCEx_WakeUpTimerEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1441:19:HAL_RTCEx_PollForWakeUpTimerEvent 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1507:6:HAL_RTCEx_BKUPWrite 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1530:10:HAL_RTCEx_BKUPRead 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1564:19:HAL_RTCEx_SetSmoothCalib 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1636:19:HAL_RTCEx_SetSynchroShift 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1731:19:HAL_RTCEx_SetCalibrationOutPut 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1770:19:HAL_RTCEx_DeactivateCalibrationOutPut 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1800:19:HAL_RTCEx_SetRefClock 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1844:19:HAL_RTCEx_DeactivateRefClock 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1890:19:HAL_RTCEx_EnableBypassShadow 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1923:19:HAL_RTCEx_DisableBypassShadow 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1973:13:HAL_RTCEx_AlarmBEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c:1990:19:HAL_RTCEx_PollForAlarmBEvent 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.cyclo new file mode 100644 index 0000000..a34bfd8 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.cyclo @@ -0,0 +1,26 @@ +stm32f7xx_hal_sdram.c:165:19:HAL_SDRAM_Init 3 +stm32f7xx_hal_sdram.c:214:19:HAL_SDRAM_DeInit 1 +stm32f7xx_hal_sdram.c:247:13:HAL_SDRAM_MspInit 1 +stm32f7xx_hal_sdram.c:263:13:HAL_SDRAM_MspDeInit 1 +stm32f7xx_hal_sdram.c:279:6:HAL_SDRAM_IRQHandler 2 +stm32f7xx_hal_sdram.c:302:13:HAL_SDRAM_RefreshErrorCallback 1 +stm32f7xx_hal_sdram.c:318:13:HAL_SDRAM_DMA_XferCpltCallback 1 +stm32f7xx_hal_sdram.c:333:13:HAL_SDRAM_DMA_XferErrorCallback 1 +stm32f7xx_hal_sdram.c:370:19:HAL_SDRAM_Read_8b 6 +stm32f7xx_hal_sdram.c:422:19:HAL_SDRAM_Write_8b 5 +stm32f7xx_hal_sdram.c:473:19:HAL_SDRAM_Read_16b 7 +stm32f7xx_hal_sdram.c:533:19:HAL_SDRAM_Write_16b 6 +stm32f7xx_hal_sdram.c:592:19:HAL_SDRAM_Read_32b 6 +stm32f7xx_hal_sdram.c:644:19:HAL_SDRAM_Write_32b 5 +stm32f7xx_hal_sdram.c:695:19:HAL_SDRAM_Read_DMA 6 +stm32f7xx_hal_sdram.c:748:19:HAL_SDRAM_Write_DMA 4 +stm32f7xx_hal_sdram.c:1011:19:HAL_SDRAM_WriteProtection_Enable 3 +stm32f7xx_hal_sdram.c:1043:19:HAL_SDRAM_WriteProtection_Disable 3 +stm32f7xx_hal_sdram.c:1079:19:HAL_SDRAM_SendCommand 5 +stm32f7xx_hal_sdram.c:1122:19:HAL_SDRAM_ProgramRefreshRate 3 +stm32f7xx_hal_sdram.c:1155:19:HAL_SDRAM_SetAutoRefreshNumber 3 +stm32f7xx_hal_sdram.c:1187:10:HAL_SDRAM_GetModeStatus 1 +stm32f7xx_hal_sdram.c:1218:24:HAL_SDRAM_GetState 1 +stm32f7xx_hal_sdram.c:1236:13:SDRAM_DMACplt 1 +stm32f7xx_hal_sdram.c:1258:13:SDRAM_DMACpltProt 1 +stm32f7xx_hal_sdram.c:1280:13:SDRAM_DMAError 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d new file mode 100644 index 0000000..6a6673d --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o new file mode 100644 index 0000000..7a6c63d Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su new file mode 100644 index 0000000..355c673 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su @@ -0,0 +1,26 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:165:19:HAL_SDRAM_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:214:19:HAL_SDRAM_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:247:13:HAL_SDRAM_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:263:13:HAL_SDRAM_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:279:6:HAL_SDRAM_IRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:302:13:HAL_SDRAM_RefreshErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:318:13:HAL_SDRAM_DMA_XferCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:333:13:HAL_SDRAM_DMA_XferErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:370:19:HAL_SDRAM_Read_8b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:422:19:HAL_SDRAM_Write_8b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:473:19:HAL_SDRAM_Read_16b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:533:19:HAL_SDRAM_Write_16b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:592:19:HAL_SDRAM_Read_32b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:644:19:HAL_SDRAM_Write_32b 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:695:19:HAL_SDRAM_Read_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:748:19:HAL_SDRAM_Write_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1011:19:HAL_SDRAM_WriteProtection_Enable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1043:19:HAL_SDRAM_WriteProtection_Disable 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1079:19:HAL_SDRAM_SendCommand 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1122:19:HAL_SDRAM_ProgramRefreshRate 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1155:19:HAL_SDRAM_SetAutoRefreshNumber 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1187:10:HAL_SDRAM_GetModeStatus 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1218:24:HAL_SDRAM_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1236:13:SDRAM_DMACplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1258:13:SDRAM_DMACpltProt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c:1280:13:SDRAM_DMAError 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.cyclo new file mode 100644 index 0000000..5fdf045 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.cyclo @@ -0,0 +1,121 @@ +stm32f7xx_hal_tim.c:269:19:HAL_TIM_Base_Init 3 +stm32f7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit 3 +stm32f7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit 1 +stm32f7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit 1 +stm32f7xx_hal_tim.c:403:19:HAL_TIM_Base_Start 12 +stm32f7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop 3 +stm32f7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT 12 +stm32f7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT 3 +stm32f7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA 16 +stm32f7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA 3 +stm32f7xx_hal_tim.c:653:19:HAL_TIM_OC_Init 3 +stm32f7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit 3 +stm32f7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit 1 +stm32f7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit 1 +stm32f7xx_hal_tim.c:794:19:HAL_TIM_OC_Start 25 +stm32f7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop 13 +stm32f7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT 30 +stm32f7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT 18 +stm32f7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA 42 +stm32f7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA 18 +stm32f7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init 3 +stm32f7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit 3 +stm32f7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit 1 +stm32f7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit 1 +stm32f7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start 25 +stm32f7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop 13 +stm32f7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT 30 +stm32f7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT 18 +stm32f7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA 42 +stm32f7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA 18 +stm32f7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init 3 +stm32f7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit 3 +stm32f7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit 1 +stm32f7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit 1 +stm32f7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start 29 +stm32f7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop 11 +stm32f7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT 34 +stm32f7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT 16 +stm32f7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA 41 +stm32f7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA 16 +stm32f7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init 3 +stm32f7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit 3 +stm32f7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit 1 +stm32f7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit 1 +stm32f7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start 8 +stm32f7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop 8 +stm32f7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT 8 +stm32f7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT 8 +stm32f7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init 3 +stm32f7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit 3 +stm32f7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit 1 +stm32f7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit 1 +stm32f7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start 13 +stm32f7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop 15 +stm32f7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT 13 +stm32f7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT 15 +stm32f7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA 32 +stm32f7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA 15 +stm32f7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler 23 +stm32f7xx_hal_tim.c:4064:19:HAL_TIM_OC_ConfigChannel 8 +stm32f7xx_hal_tim.c:4163:19:HAL_TIM_IC_ConfigChannel 6 +stm32f7xx_hal_tim.c:4264:19:HAL_TIM_PWM_ConfigChannel 8 +stm32f7xx_hal_tim.c:4412:19:HAL_TIM_OnePulse_ConfigChannel 8 +stm32f7xx_hal_tim.c:4567:19:HAL_TIM_DMABurst_WriteStart 1 +stm32f7xx_hal_tim.c:4626:19:HAL_TIM_DMABurst_MultiWriteStart 25 +stm32f7xx_hal_tim.c:4810:19:HAL_TIM_DMABurst_WriteStop 14 +stm32f7xx_hal_tim.c:4918:19:HAL_TIM_DMABurst_ReadStart 1 +stm32f7xx_hal_tim.c:4976:19:HAL_TIM_DMABurst_MultiReadStart 25 +stm32f7xx_hal_tim.c:5160:19:HAL_TIM_DMABurst_ReadStop 14 +stm32f7xx_hal_tim.c:5244:19:HAL_TIM_GenerateEvent 2 +stm32f7xx_hal_tim.c:5283:19:HAL_TIM_ConfigOCrefClear 18 +stm32f7xx_hal_tim.c:5441:19:HAL_TIM_ConfigClockSource 20 +stm32f7xx_hal_tim.c:5595:19:HAL_TIM_ConfigTI1Input 1 +stm32f7xx_hal_tim.c:5627:19:HAL_TIM_SlaveConfigSynchro 3 +stm32f7xx_hal_tim.c:5667:19:HAL_TIM_SlaveConfigSynchro_IT 3 +stm32f7xx_hal_tim.c:5710:10:HAL_TIM_ReadCapturedValue 5 +stm32f7xx_hal_tim.c:5794:13:HAL_TIM_PeriodElapsedCallback 1 +stm32f7xx_hal_tim.c:5809:13:HAL_TIM_PeriodElapsedHalfCpltCallback 1 +stm32f7xx_hal_tim.c:5824:13:HAL_TIM_OC_DelayElapsedCallback 1 +stm32f7xx_hal_tim.c:5839:13:HAL_TIM_IC_CaptureCallback 1 +stm32f7xx_hal_tim.c:5854:13:HAL_TIM_IC_CaptureHalfCpltCallback 1 +stm32f7xx_hal_tim.c:5869:13:HAL_TIM_PWM_PulseFinishedCallback 1 +stm32f7xx_hal_tim.c:5884:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 1 +stm32f7xx_hal_tim.c:5899:13:HAL_TIM_TriggerCallback 1 +stm32f7xx_hal_tim.c:5914:13:HAL_TIM_TriggerHalfCpltCallback 1 +stm32f7xx_hal_tim.c:5929:13:HAL_TIM_ErrorCallback 1 +stm32f7xx_hal_tim.c:6498:22:HAL_TIM_Base_GetState 1 +stm32f7xx_hal_tim.c:6508:22:HAL_TIM_OC_GetState 1 +stm32f7xx_hal_tim.c:6518:22:HAL_TIM_PWM_GetState 1 +stm32f7xx_hal_tim.c:6528:22:HAL_TIM_IC_GetState 1 +stm32f7xx_hal_tim.c:6538:22:HAL_TIM_OnePulse_GetState 1 +stm32f7xx_hal_tim.c:6548:22:HAL_TIM_Encoder_GetState 1 +stm32f7xx_hal_tim.c:6558:23:HAL_TIM_GetActiveChannel 1 +stm32f7xx_hal_tim.c:6576:29:HAL_TIM_GetChannelState 6 +stm32f7xx_hal_tim.c:6593:30:HAL_TIM_DMABurstState 1 +stm32f7xx_hal_tim.c:6618:6:TIM_DMAError 5 +stm32f7xx_hal_tim.c:6661:13:TIM_DMADelayPulseCplt 9 +stm32f7xx_hal_tim.c:6720:6:TIM_DMADelayPulseHalfCplt 5 +stm32f7xx_hal_tim.c:6759:6:TIM_DMACaptureCplt 9 +stm32f7xx_hal_tim.c:6822:6:TIM_DMACaptureHalfCplt 5 +stm32f7xx_hal_tim.c:6861:13:TIM_DMAPeriodElapsedCplt 2 +stm32f7xx_hal_tim.c:6882:13:TIM_DMAPeriodElapsedHalfCplt 1 +stm32f7xx_hal_tim.c:6898:13:TIM_DMATriggerCplt 2 +stm32f7xx_hal_tim.c:6919:13:TIM_DMATriggerHalfCplt 1 +stm32f7xx_hal_tim.c:6936:6:TIM_Base_SetConfig 21 +stm32f7xx_hal_tim.c:6984:13:TIM_OC1_SetConfig 5 +stm32f7xx_hal_tim.c:7059:6:TIM_OC2_SetConfig 5 +stm32f7xx_hal_tim.c:7135:13:TIM_OC3_SetConfig 5 +stm32f7xx_hal_tim.c:7209:13:TIM_OC4_SetConfig 3 +stm32f7xx_hal_tim.c:7269:13:TIM_OC5_SetConfig 3 +stm32f7xx_hal_tim.c:7322:13:TIM_OC6_SetConfig 3 +stm32f7xx_hal_tim.c:7376:26:TIM_SlaveTimer_SetConfig 16 +stm32f7xx_hal_tim.c:7510:6:TIM_TI1_SetConfig 10 +stm32f7xx_hal_tim.c:7557:13:TIM_TI1_ConfigInputStage 1 +stm32f7xx_hal_tim.c:7600:13:TIM_TI2_SetConfig 1 +stm32f7xx_hal_tim.c:7640:13:TIM_TI2_ConfigInputStage 1 +stm32f7xx_hal_tim.c:7683:13:TIM_TI3_SetConfig 1 +stm32f7xx_hal_tim.c:7731:13:TIM_TI4_SetConfig 1 +stm32f7xx_hal_tim.c:7774:13:TIM_ITRx_SetConfig 1 +stm32f7xx_hal_tim.c:7804:6:TIM_ETR_SetConfig 1 +stm32f7xx_hal_tim.c:7836:6:TIM_CCxChannelCmd 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d new file mode 100644 index 0000000..54fff7a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o new file mode 100644 index 0000000..6981dfe Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su new file mode 100644 index 0000000..19779ea --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su @@ -0,0 +1,121 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:269:19:HAL_TIM_Base_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:403:19:HAL_TIM_Base_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:653:19:HAL_TIM_OC_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:794:19:HAL_TIM_OC_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4064:19:HAL_TIM_OC_ConfigChannel 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4163:19:HAL_TIM_IC_ConfigChannel 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4264:19:HAL_TIM_PWM_ConfigChannel 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4412:19:HAL_TIM_OnePulse_ConfigChannel 56 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4567:19:HAL_TIM_DMABurst_WriteStart 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4626:19:HAL_TIM_DMABurst_MultiWriteStart 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4810:19:HAL_TIM_DMABurst_WriteStop 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4918:19:HAL_TIM_DMABurst_ReadStart 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:4976:19:HAL_TIM_DMABurst_MultiReadStart 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:5160:19:HAL_TIM_DMABurst_ReadStop 24 static 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+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6720:6:TIM_DMADelayPulseHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6759:6:TIM_DMACaptureCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6822:6:TIM_DMACaptureHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6861:13:TIM_DMAPeriodElapsedCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6882:13:TIM_DMAPeriodElapsedHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6898:13:TIM_DMATriggerCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6919:13:TIM_DMATriggerHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6936:6:TIM_Base_SetConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:6984:13:TIM_OC1_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7059:6:TIM_OC2_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7135:13:TIM_OC3_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7209:13:TIM_OC4_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7269:13:TIM_OC5_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7322:13:TIM_OC6_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7376:26:TIM_SlaveTimer_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7510:6:TIM_TI1_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7557:13:TIM_TI1_ConfigInputStage 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7600:13:TIM_TI2_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7640:13:TIM_TI2_ConfigInputStage 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7683:13:TIM_TI3_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7731:13:TIM_TI4_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7774:13:TIM_ITRx_SetConfig 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7804:6:TIM_ETR_SetConfig 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c:7836:6:TIM_CCxChannelCmd 32 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.cyclo new file mode 100644 index 0000000..f96b900 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.cyclo @@ -0,0 +1,44 @@ +stm32f7xx_hal_tim_ex.c:139:19:HAL_TIMEx_HallSensor_Init 3 +stm32f7xx_hal_tim_ex.c:241:19:HAL_TIMEx_HallSensor_DeInit 3 +stm32f7xx_hal_tim_ex.c:286:13:HAL_TIMEx_HallSensor_MspInit 1 +stm32f7xx_hal_tim_ex.c:301:13:HAL_TIMEx_HallSensor_MspDeInit 1 +stm32f7xx_hal_tim_ex.c:316:19:HAL_TIMEx_HallSensor_Start 15 +stm32f7xx_hal_tim_ex.c:370:19:HAL_TIMEx_HallSensor_Stop 3 +stm32f7xx_hal_tim_ex.c:398:19:HAL_TIMEx_HallSensor_Start_IT 15 +stm32f7xx_hal_tim_ex.c:455:19:HAL_TIMEx_HallSensor_Stop_IT 3 +stm32f7xx_hal_tim_ex.c:488:19:HAL_TIMEx_HallSensor_Start_DMA 18 +stm32f7xx_hal_tim_ex.c:564:19:HAL_TIMEx_HallSensor_Stop_DMA 3 +stm32f7xx_hal_tim_ex.c:626:19:HAL_TIMEx_OCN_Start 18 +stm32f7xx_hal_tim_ex.c:677:19:HAL_TIMEx_OCN_Stop 8 +stm32f7xx_hal_tim_ex.c:709:19:HAL_TIMEx_OCN_Start_IT 23 +stm32f7xx_hal_tim_ex.c:796:19:HAL_TIMEx_OCN_Stop_IT 14 +stm32f7xx_hal_tim_ex.c:871:19:HAL_TIMEx_OCN_Start_DMA 32 +stm32f7xx_hal_tim_ex.c:1009:19:HAL_TIMEx_OCN_Stop_DMA 13 +stm32f7xx_hal_tim_ex.c:1110:19:HAL_TIMEx_PWMN_Start 18 +stm32f7xx_hal_tim_ex.c:1160:19:HAL_TIMEx_PWMN_Stop 8 +stm32f7xx_hal_tim_ex.c:1192:19:HAL_TIMEx_PWMN_Start_IT 23 +stm32f7xx_hal_tim_ex.c:1278:19:HAL_TIMEx_PWMN_Stop_IT 14 +stm32f7xx_hal_tim_ex.c:1353:19:HAL_TIMEx_PWMN_Start_DMA 32 +stm32f7xx_hal_tim_ex.c:1491:19:HAL_TIMEx_PWMN_Stop_DMA 13 +stm32f7xx_hal_tim_ex.c:1582:19:HAL_TIMEx_OnePulseN_Start 6 +stm32f7xx_hal_tim_ex.c:1631:19:HAL_TIMEx_OnePulseN_Stop 6 +stm32f7xx_hal_tim_ex.c:1670:19:HAL_TIMEx_OnePulseN_Start_IT 6 +stm32f7xx_hal_tim_ex.c:1725:19:HAL_TIMEx_OnePulseN_Stop_IT 6 +stm32f7xx_hal_tim_ex.c:1805:19:HAL_TIMEx_ConfigCommutEvent 6 +stm32f7xx_hal_tim_ex.c:1861:19:HAL_TIMEx_ConfigCommutEvent_IT 6 +stm32f7xx_hal_tim_ex.c:1918:19:HAL_TIMEx_ConfigCommutEvent_DMA 6 +stm32f7xx_hal_tim_ex.c:1967:19:HAL_TIMEx_MasterConfigSynchronization 12 +stm32f7xx_hal_tim_ex.c:2040:19:HAL_TIMEx_ConfigBreakDeadTime 4 +stm32f7xx_hal_tim_ex.c:2243:19:HAL_TIMEx_RemapConfig 2 +stm32f7xx_hal_tim_ex.c:2272:19:HAL_TIMEx_GroupChannel5 2 +stm32f7xx_hal_tim_ex.c:2322:13:HAL_TIMEx_CommutCallback 1 +stm32f7xx_hal_tim_ex.c:2336:13:HAL_TIMEx_CommutHalfCpltCallback 1 +stm32f7xx_hal_tim_ex.c:2351:13:HAL_TIMEx_BreakCallback 1 +stm32f7xx_hal_tim_ex.c:2366:13:HAL_TIMEx_Break2Callback 1 +stm32f7xx_hal_tim_ex.c:2399:22:HAL_TIMEx_HallSensor_GetState 1 +stm32f7xx_hal_tim_ex.c:2414:29:HAL_TIMEx_GetChannelNState 4 +stm32f7xx_hal_tim_ex.c:2443:6:TIMEx_DMACommutationCplt 1 +stm32f7xx_hal_tim_ex.c:2462:6:TIMEx_DMACommutationHalfCplt 1 +stm32f7xx_hal_tim_ex.c:2482:13:TIM_DMADelayPulseNCplt 9 +stm32f7xx_hal_tim_ex.c:2541:13:TIM_DMAErrorCCxN 4 +stm32f7xx_hal_tim_ex.c:2586:13:TIM_CCxNChannelCmd 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d new file mode 100644 index 0000000..8c5c2f5 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o new file mode 100644 index 0000000..c352408 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su new file mode 100644 index 0000000..2e231c3 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su @@ -0,0 +1,44 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:139:19:HAL_TIMEx_HallSensor_Init 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:241:19:HAL_TIMEx_HallSensor_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:286:13:HAL_TIMEx_HallSensor_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:301:13:HAL_TIMEx_HallSensor_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:316:19:HAL_TIMEx_HallSensor_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:370:19:HAL_TIMEx_HallSensor_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:398:19:HAL_TIMEx_HallSensor_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:455:19:HAL_TIMEx_HallSensor_Stop_IT 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:488:19:HAL_TIMEx_HallSensor_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:564:19:HAL_TIMEx_HallSensor_Stop_DMA 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:626:19:HAL_TIMEx_OCN_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:677:19:HAL_TIMEx_OCN_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:709:19:HAL_TIMEx_OCN_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:796:19:HAL_TIMEx_OCN_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:871:19:HAL_TIMEx_OCN_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1009:19:HAL_TIMEx_OCN_Stop_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1110:19:HAL_TIMEx_PWMN_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1160:19:HAL_TIMEx_PWMN_Stop 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1192:19:HAL_TIMEx_PWMN_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1278:19:HAL_TIMEx_PWMN_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1353:19:HAL_TIMEx_PWMN_Start_DMA 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1491:19:HAL_TIMEx_PWMN_Stop_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1582:19:HAL_TIMEx_OnePulseN_Start 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1631:19:HAL_TIMEx_OnePulseN_Stop 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1670:19:HAL_TIMEx_OnePulseN_Start_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1725:19:HAL_TIMEx_OnePulseN_Stop_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1805:19:HAL_TIMEx_ConfigCommutEvent 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1861:19:HAL_TIMEx_ConfigCommutEvent_IT 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1918:19:HAL_TIMEx_ConfigCommutEvent_DMA 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:1967:19:HAL_TIMEx_MasterConfigSynchronization 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2040:19:HAL_TIMEx_ConfigBreakDeadTime 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2243:19:HAL_TIMEx_RemapConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2272:19:HAL_TIMEx_GroupChannel5 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2322:13:HAL_TIMEx_CommutCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2336:13:HAL_TIMEx_CommutHalfCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2351:13:HAL_TIMEx_BreakCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2366:13:HAL_TIMEx_Break2Callback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2399:22:HAL_TIMEx_HallSensor_GetState 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2414:29:HAL_TIMEx_GetChannelNState 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2443:6:TIMEx_DMACommutationCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2462:6:TIMEx_DMACommutationHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2482:13:TIM_DMADelayPulseNCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2541:13:TIM_DMAErrorCCxN 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c:2586:13:TIM_CCxNChannelCmd 32 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.cyclo new file mode 100644 index 0000000..52d2dfe --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.cyclo @@ -0,0 +1,66 @@ +stm32f7xx_hal_uart.c:289:19:HAL_UART_Init 5 +stm32f7xx_hal_uart.c:362:19:HAL_HalfDuplex_Init 5 +stm32f7xx_hal_uart.c:435:19:HAL_LIN_Init 7 +stm32f7xx_hal_uart.c:532:19:HAL_MultiProcessor_Init 6 +stm32f7xx_hal_uart.c:606:19:HAL_UART_DeInit 2 +stm32f7xx_hal_uart.c:653:13:HAL_UART_MspInit 1 +stm32f7xx_hal_uart.c:668:13:HAL_UART_MspDeInit 1 +stm32f7xx_hal_uart.c:1094:19:HAL_UART_Transmit 10 +stm32f7xx_hal_uart.c:1175:19:HAL_UART_Receive 15 +stm32f7xx_hal_uart.c:1257:19:HAL_UART_Transmit_IT 7 +stm32f7xx_hal_uart.c:1306:19:HAL_UART_Receive_IT 6 +stm32f7xx_hal_uart.c:1344:19:HAL_UART_Transmit_DMA 7 +stm32f7xx_hal_uart.c:1414:19:HAL_UART_Receive_DMA 6 +stm32f7xx_hal_uart.c:1447:19:HAL_UART_DMAPause 9 +stm32f7xx_hal_uart.c:1477:19:HAL_UART_DMAResume 8 +stm32f7xx_hal_uart.c:1508:19:HAL_UART_DMAStop 13 +stm32f7xx_hal_uart.c:1583:19:HAL_UART_Abort 15 +stm32f7xx_hal_uart.c:1680:19:HAL_UART_AbortTransmit 7 +stm32f7xx_hal_uart.c:1733:19:HAL_UART_AbortReceive 10 +stm32f7xx_hal_uart.c:1801:19:HAL_UART_Abort_IT 18 +stm32f7xx_hal_uart.c:1948:19:HAL_UART_AbortTransmit_IT 6 +stm32f7xx_hal_uart.c:2033:19:HAL_UART_AbortReceive_IT 9 +stm32f7xx_hal_uart.c:2126:6:HAL_UART_IRQHandler 50 +stm32f7xx_hal_uart.c:2432:13:HAL_UART_TxCpltCallback 1 +stm32f7xx_hal_uart.c:2447:13:HAL_UART_TxHalfCpltCallback 1 +stm32f7xx_hal_uart.c:2462:13:HAL_UART_RxCpltCallback 1 +stm32f7xx_hal_uart.c:2477:13:HAL_UART_RxHalfCpltCallback 1 +stm32f7xx_hal_uart.c:2492:13:HAL_UART_ErrorCallback 1 +stm32f7xx_hal_uart.c:2507:13:HAL_UART_AbortCpltCallback 1 +stm32f7xx_hal_uart.c:2522:13:HAL_UART_AbortTransmitCpltCallback 1 +stm32f7xx_hal_uart.c:2537:13:HAL_UART_AbortReceiveCpltCallback 1 +stm32f7xx_hal_uart.c:2554:13:HAL_UARTEx_RxEventCallback 1 +stm32f7xx_hal_uart.c:2619:6:HAL_UART_ReceiverTimeout_Config 1 +stm32f7xx_hal_uart.c:2631:19:HAL_UART_EnableReceiverTimeout 3 +stm32f7xx_hal_uart.c:2662:19:HAL_UART_DisableReceiverTimeout 3 +stm32f7xx_hal_uart.c:2693:19:HAL_MultiProcessor_EnableMuteMode 3 +stm32f7xx_hal_uart.c:2713:19:HAL_MultiProcessor_DisableMuteMode 3 +stm32f7xx_hal_uart.c:2733:6:HAL_MultiProcessor_EnterMuteMode 1 +stm32f7xx_hal_uart.c:2743:19:HAL_HalfDuplex_EnableTransmitter 4 +stm32f7xx_hal_uart.c:2766:19:HAL_HalfDuplex_EnableReceiver 4 +stm32f7xx_hal_uart.c:2790:19:HAL_LIN_SendBreak 2 +stm32f7xx_hal_uart.c:2835:23:HAL_UART_GetState 1 +stm32f7xx_hal_uart.c:2851:10:HAL_UART_GetError 1 +stm32f7xx_hal_uart.c:2899:19:UART_SetConfig 70 +stm32f7xx_hal_uart.c:3043:6:UART_AdvFeatureConfig 10 +stm32f7xx_hal_uart.c:3117:19:UART_CheckIdleState 3 +stm32f7xx_hal_uart.c:3172:19:UART_WaitOnFlagUntilTimeout 11 +stm32f7xx_hal_uart.c:3234:19:UART_Start_Receive_IT 13 +stm32f7xx_hal_uart.c:3283:19:UART_Start_Receive_DMA 7 +stm32f7xx_hal_uart.c:3340:13:UART_EndTxTransfer 2 +stm32f7xx_hal_uart.c:3355:13:UART_EndRxTransfer 5 +stm32f7xx_hal_uart.c:3381:13:UART_DMATransmitCplt 4 +stm32f7xx_hal_uart.c:3415:13:UART_DMATxHalfCplt 1 +stm32f7xx_hal_uart.c:3433:13:UART_DMAReceiveCplt 8 +stm32f7xx_hal_uart.c:3494:13:UART_DMARxHalfCplt 2 +stm32f7xx_hal_uart.c:3532:13:UART_DMAError 5 +stm32f7xx_hal_uart.c:3572:13:UART_DMAAbortOnError 1 +stm32f7xx_hal_uart.c:3595:13:UART_DMATxAbortCallback 3 +stm32f7xx_hal_uart.c:3645:13:UART_DMARxAbortCallback 3 +stm32f7xx_hal_uart.c:3697:13:UART_DMATxOnlyAbortCallback 1 +stm32f7xx_hal_uart.c:3725:13:UART_DMARxOnlyAbortCallback 1 +stm32f7xx_hal_uart.c:3758:13:UART_TxISR_8BIT 5 +stm32f7xx_hal_uart.c:3787:13:UART_TxISR_16BIT 5 +stm32f7xx_hal_uart.c:3819:13:UART_EndTransmit_IT 2 +stm32f7xx_hal_uart.c:3844:13:UART_RxISR_8BIT 8 +stm32f7xx_hal_uart.c:3925:13:UART_RxISR_16BIT 8 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d new file mode 100644 index 0000000..a917737 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o new file mode 100644 index 0000000..f16bdcd Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su new file mode 100644 index 0000000..bc135ff --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su @@ -0,0 +1,66 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:289:19:HAL_UART_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:362:19:HAL_HalfDuplex_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:435:19:HAL_LIN_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:532:19:HAL_MultiProcessor_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:606:19:HAL_UART_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:653:13:HAL_UART_MspInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:668:13:HAL_UART_MspDeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1094:19:HAL_UART_Transmit 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1175:19:HAL_UART_Receive 48 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1257:19:HAL_UART_Transmit_IT 48 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1306:19:HAL_UART_Receive_IT 48 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1344:19:HAL_UART_Transmit_DMA 48 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1414:19:HAL_UART_Receive_DMA 48 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1447:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1477:19:HAL_UART_DMAResume 112 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1508:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1583:19:HAL_UART_Abort 136 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1680:19:HAL_UART_AbortTransmit 64 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1733:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1801:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:1948:19:HAL_UART_AbortTransmit_IT 64 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2033:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2126:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2432:13:HAL_UART_TxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2447:13:HAL_UART_TxHalfCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2462:13:HAL_UART_RxCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2477:13:HAL_UART_RxHalfCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2492:13:HAL_UART_ErrorCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2507:13:HAL_UART_AbortCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2522:13:HAL_UART_AbortTransmitCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2537:13:HAL_UART_AbortReceiveCpltCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2554:13:HAL_UARTEx_RxEventCallback 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2619:6:HAL_UART_ReceiverTimeout_Config 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2631:19:HAL_UART_EnableReceiverTimeout 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2662:19:HAL_UART_DisableReceiverTimeout 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2693:19:HAL_MultiProcessor_EnableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2713:19:HAL_MultiProcessor_DisableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2733:6:HAL_MultiProcessor_EnterMuteMode 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2743:19:HAL_HalfDuplex_EnableTransmitter 64 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2766:19:HAL_HalfDuplex_EnableReceiver 64 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2790:19:HAL_LIN_SendBreak 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2835:23:HAL_UART_GetState 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2851:10:HAL_UART_GetError 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:2899:19:UART_SetConfig 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3043:6:UART_AdvFeatureConfig 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3117:19:UART_CheckIdleState 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3172:19:UART_WaitOnFlagUntilTimeout 120 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3234:19:UART_Start_Receive_IT 96 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3283:19:UART_Start_Receive_DMA 96 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3340:13:UART_EndTxTransfer 40 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3355:13:UART_EndRxTransfer 88 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3381:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3415:13:UART_DMATxHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3433:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3494:13:UART_DMARxHalfCplt 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3532:13:UART_DMAError 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3572:13:UART_DMAAbortOnError 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3595:13:UART_DMATxAbortCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3645:13:UART_DMARxAbortCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3697:13:UART_DMATxOnlyAbortCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3725:13:UART_DMARxOnlyAbortCallback 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3758:13:UART_TxISR_8BIT 64 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3787:13:UART_TxISR_16BIT 72 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3819:13:UART_EndTransmit_IT 40 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3844:13:UART_RxISR_8BIT 96 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c:3925:13:UART_RxISR_16BIT 96 static,ignoring_inline_asm diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.cyclo new file mode 100644 index 0000000..8ae026a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.cyclo @@ -0,0 +1,6 @@ +stm32f7xx_hal_uart_ex.c:150:19:HAL_RS485Ex_Init 5 +stm32f7xx_hal_uart_ex.c:347:19:HAL_MultiProcessorEx_AddressLength_Set 2 +stm32f7xx_hal_uart_ex.c:494:19:HAL_UARTEx_ReceiveToIdle 20 +stm32f7xx_hal_uart_ex.c:617:19:HAL_UARTEx_ReceiveToIdle_IT 7 +stm32f7xx_hal_uart_ex.c:678:19:HAL_UARTEx_ReceiveToIdle_DMA 7 +stm32f7xx_hal_uart_ex.c:746:29:HAL_UARTEx_GetRxEventType 1 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d new file mode 100644 index 0000000..ba8d2fb --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o new file mode 100644 index 0000000..c47b2ff Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su new file mode 100644 index 0000000..d2a641f --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:150:19:HAL_RS485Ex_Init 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:347:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:494:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:617:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:678:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c:746:29:HAL_UARTEx_GetRxEventType 16 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.cyclo b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.cyclo new file mode 100644 index 0000000..b6e2dec --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.cyclo @@ -0,0 +1,22 @@ +stm32f7xx_ll_fmc.c:189:20:FMC_NORSRAM_Init 5 +stm32f7xx_ll_fmc.c:286:19:FMC_NORSRAM_DeInit 2 +stm32f7xx_ll_fmc.c:323:19:FMC_NORSRAM_Timing_Init 2 +stm32f7xx_ll_fmc.c:371:19:FMC_NORSRAM_Extended_Timing_Init 2 +stm32f7xx_ll_fmc.c:429:19:FMC_NORSRAM_WriteOperation_Enable 1 +stm32f7xx_ll_fmc.c:447:19:FMC_NORSRAM_WriteOperation_Disable 1 +stm32f7xx_ll_fmc.c:517:19:FMC_NAND_Init 1 +stm32f7xx_ll_fmc.c:549:19:FMC_NAND_CommonSpace_Timing_Init 1 +stm32f7xx_ll_fmc.c:580:19:FMC_NAND_AttributeSpace_Timing_Init 1 +stm32f7xx_ll_fmc.c:609:19:FMC_NAND_DeInit 1 +stm32f7xx_ll_fmc.c:657:19:FMC_NAND_ECC_Enable 1 +stm32f7xx_ll_fmc.c:679:19:FMC_NAND_ECC_Disable 1 +stm32f7xx_ll_fmc.c:702:19:FMC_NAND_GetECC 5 +stm32f7xx_ll_fmc.c:788:19:FMC_SDRAM_Init 2 +stm32f7xx_ll_fmc.c:850:19:FMC_SDRAM_Timing_Init 2 +stm32f7xx_ll_fmc.c:902:19:FMC_SDRAM_DeInit 1 +stm32f7xx_ll_fmc.c:943:19:FMC_SDRAM_WriteProtection_Enable 1 +stm32f7xx_ll_fmc.c:960:19:FMC_SDRAM_WriteProtection_Disable 1 +stm32f7xx_ll_fmc.c:980:19:FMC_SDRAM_SendCommand 1 +stm32f7xx_ll_fmc.c:1006:19:FMC_SDRAM_ProgramRefreshRate 1 +stm32f7xx_ll_fmc.c:1024:19:FMC_SDRAM_SetAutoRefreshNumber 1 +stm32f7xx_ll_fmc.c:1046:10:FMC_SDRAM_GetModeStatus 2 diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d new file mode 100644 index 0000000..5d5150a --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d @@ -0,0 +1,78 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o new file mode 100644 index 0000000..6a59a67 Binary files /dev/null and b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o differ diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su new file mode 100644 index 0000000..678718b --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su @@ -0,0 +1,22 @@ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:189:20:FMC_NORSRAM_Init 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:286:19:FMC_NORSRAM_DeInit 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:323:19:FMC_NORSRAM_Timing_Init 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:371:19:FMC_NORSRAM_Extended_Timing_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:429:19:FMC_NORSRAM_WriteOperation_Enable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:447:19:FMC_NORSRAM_WriteOperation_Disable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:517:19:FMC_NAND_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:549:19:FMC_NAND_CommonSpace_Timing_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:580:19:FMC_NAND_AttributeSpace_Timing_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:609:19:FMC_NAND_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:657:19:FMC_NAND_ECC_Enable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:679:19:FMC_NAND_ECC_Disable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:702:19:FMC_NAND_GetECC 32 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:788:19:FMC_SDRAM_Init 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:850:19:FMC_SDRAM_Timing_Init 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:902:19:FMC_SDRAM_DeInit 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:943:19:FMC_SDRAM_WriteProtection_Enable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:960:19:FMC_SDRAM_WriteProtection_Disable 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:980:19:FMC_SDRAM_SendCommand 24 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:1006:19:FMC_SDRAM_ProgramRefreshRate 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:1024:19:FMC_SDRAM_SetAutoRefreshNumber 16 static +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c:1046:10:FMC_SDRAM_GetModeStatus 24 static diff --git a/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..a1dc426 --- /dev/null +++ b/project/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,106 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c + +OBJS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + +C_DEPS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F7xx_HAL_Driver/Src/%.o Drivers/STM32F7xx_HAL_Driver/Src/%.su Drivers/STM32F7xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F7xx_HAL_Driver/Src/%.c Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32F7xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32F7xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + -$(RM) ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.cyclo ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su + +.PHONY: clean-Drivers-2f-STM32F7xx_HAL_Driver-2f-Src + diff --git a/project/Debug/LWIP/App/lwip.cyclo b/project/Debug/LWIP/App/lwip.cyclo new file mode 100644 index 0000000..873c9c4 --- /dev/null +++ b/project/Debug/LWIP/App/lwip.cyclo @@ -0,0 +1,2 @@ +lwip.c:55:6:MX_LWIP_Init 2 +lwip.c:111:13:ethernet_link_status_updated 1 diff --git a/project/Debug/LWIP/App/lwip.d b/project/Debug/LWIP/App/lwip.d new file mode 100644 index 0000000..56aa4fc --- /dev/null +++ b/project/Debug/LWIP/App/lwip.d @@ -0,0 +1,193 @@ +LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../LWIP/Target/ethernetif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../LWIP/Target/ethernetif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/init.h: diff --git a/project/Debug/LWIP/App/lwip.o b/project/Debug/LWIP/App/lwip.o new file mode 100644 index 0000000..376eaed Binary files /dev/null and b/project/Debug/LWIP/App/lwip.o differ diff --git a/project/Debug/LWIP/App/lwip.su b/project/Debug/LWIP/App/lwip.su new file mode 100644 index 0000000..3307329 --- /dev/null +++ b/project/Debug/LWIP/App/lwip.su @@ -0,0 +1,2 @@ +../LWIP/App/lwip.c:55:6:MX_LWIP_Init 64 static +../LWIP/App/lwip.c:111:13:ethernet_link_status_updated 16 static diff --git a/project/Debug/LWIP/App/subdir.mk b/project/Debug/LWIP/App/subdir.mk new file mode 100644 index 0000000..b041273 --- /dev/null +++ b/project/Debug/LWIP/App/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../LWIP/App/lwip.c + +OBJS += \ +./LWIP/App/lwip.o + +C_DEPS += \ +./LWIP/App/lwip.d + + +# Each subdirectory must supply rules for building sources it contributes +LWIP/App/%.o LWIP/App/%.su LWIP/App/%.cyclo: ../LWIP/App/%.c LWIP/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-LWIP-2f-App + +clean-LWIP-2f-App: + -$(RM) ./LWIP/App/lwip.cyclo ./LWIP/App/lwip.d ./LWIP/App/lwip.o ./LWIP/App/lwip.su + +.PHONY: clean-LWIP-2f-App + diff --git a/project/Debug/LWIP/Target/ethernetif.cyclo b/project/Debug/LWIP/Target/ethernetif.cyclo new file mode 100644 index 0000000..4105ca2 --- /dev/null +++ b/project/Debug/LWIP/Target/ethernetif.cyclo @@ -0,0 +1,24 @@ +core_cm7.h:2464:22:SCB_InvalidateDCache_by_Addr 2 +ethernetif.c:158:6:HAL_ETH_RxCpltCallback 1 +ethernetif.c:167:6:HAL_ETH_TxCpltCallback 1 +ethernetif.c:176:6:HAL_ETH_ErrorCallback 2 +ethernetif.c:198:13:low_level_init 7 +ethernetif.c:360:14:low_level_output 6 +ethernetif.c:415:22:low_level_input 2 +ethernetif.c:436:13:ethernetif_input 5 +ethernetif.c:493:7:ethernetif_init 2 +ethernetif.c:544:6:pbuf_free_custom 2 +ethernetif.c:567:7:sys_jiffies 1 +ethernetif.c:578:7:sys_now 1 +ethernetif.c:591:6:HAL_ETH_MspInit 2 +ethernetif.c:646:6:HAL_ETH_MspDeInit 2 +ethernetif.c:690:9:ETH_PHY_IO_Init 1 +ethernetif.c:707:9:ETH_PHY_IO_DeInit 1 +ethernetif.c:719:9:ETH_PHY_IO_ReadReg 2 +ethernetif.c:736:9:ETH_PHY_IO_WriteReg 2 +ethernetif.c:750:9:ETH_PHY_IO_GetTick 1 +ethernetif.c:760:6:ethernet_link_thread 10 +ethernetif.c:830:6:HAL_ETH_RxAllocateCallback 2 +ethernetif.c:852:6:HAL_ETH_RxLinkCallback 3 +ethernetif.c:892:6:HAL_ETH_TxFreeCallback 1 +ethernetif.c:907:13:ethernetif_notify_conn_changed 1 diff --git a/project/Debug/LWIP/Target/ethernetif.d b/project/Debug/LWIP/Target/ethernetif.d new file mode 100644 index 0000000..afe4097 --- /dev/null +++ b/project/Debug/LWIP/Target/ethernetif.d @@ -0,0 +1,181 @@ +LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \ + ../LWIP/Target/ethernetif.h ../Drivers/BSP/Components/lan8742/lan8742.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h: +../LWIP/Target/ethernetif.h: +../Drivers/BSP/Components/lan8742/lan8742.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: diff --git a/project/Debug/LWIP/Target/ethernetif.o b/project/Debug/LWIP/Target/ethernetif.o new file mode 100644 index 0000000..6119434 Binary files /dev/null and b/project/Debug/LWIP/Target/ethernetif.o differ diff --git a/project/Debug/LWIP/Target/ethernetif.su b/project/Debug/LWIP/Target/ethernetif.su new file mode 100644 index 0000000..0d96a0d --- /dev/null +++ b/project/Debug/LWIP/Target/ethernetif.su @@ -0,0 +1,24 @@ +../Drivers/CMSIS/Include/core_cm7.h:2464:22:SCB_InvalidateDCache_by_Addr 32 static,ignoring_inline_asm +../LWIP/Target/ethernetif.c:158:6:HAL_ETH_RxCpltCallback 16 static +../LWIP/Target/ethernetif.c:167:6:HAL_ETH_TxCpltCallback 16 static +../LWIP/Target/ethernetif.c:176:6:HAL_ETH_ErrorCallback 16 static +../LWIP/Target/ethernetif.c:198:13:low_level_init 176 static +../LWIP/Target/ethernetif.c:360:14:low_level_output 80 static +../LWIP/Target/ethernetif.c:415:22:low_level_input 24 static +../LWIP/Target/ethernetif.c:436:13:ethernetif_input 24 static +../LWIP/Target/ethernetif.c:493:7:ethernetif_init 16 static +../LWIP/Target/ethernetif.c:544:6:pbuf_free_custom 24 static +../LWIP/Target/ethernetif.c:567:7:sys_jiffies 8 static +../LWIP/Target/ethernetif.c:578:7:sys_now 8 static +../LWIP/Target/ethernetif.c:591:6:HAL_ETH_MspInit 64 static +../LWIP/Target/ethernetif.c:646:6:HAL_ETH_MspDeInit 16 static +../LWIP/Target/ethernetif.c:690:9:ETH_PHY_IO_Init 8 static +../LWIP/Target/ethernetif.c:707:9:ETH_PHY_IO_DeInit 4 static +../LWIP/Target/ethernetif.c:719:9:ETH_PHY_IO_ReadReg 24 static +../LWIP/Target/ethernetif.c:736:9:ETH_PHY_IO_WriteReg 24 static +../LWIP/Target/ethernetif.c:750:9:ETH_PHY_IO_GetTick 8 static +../LWIP/Target/ethernetif.c:760:6:ethernet_link_thread 136 static +../LWIP/Target/ethernetif.c:830:6:HAL_ETH_RxAllocateCallback 32 static +../LWIP/Target/ethernetif.c:852:6:HAL_ETH_RxLinkCallback 40 static +../LWIP/Target/ethernetif.c:892:6:HAL_ETH_TxFreeCallback 16 static +../LWIP/Target/ethernetif.c:907:13:ethernetif_notify_conn_changed 16 static diff --git a/project/Debug/LWIP/Target/subdir.mk b/project/Debug/LWIP/Target/subdir.mk new file mode 100644 index 0000000..ff27c9c --- /dev/null +++ b/project/Debug/LWIP/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../LWIP/Target/ethernetif.c + +OBJS += \ +./LWIP/Target/ethernetif.o + +C_DEPS += \ +./LWIP/Target/ethernetif.d + + +# Each subdirectory must supply rules for building sources it contributes +LWIP/Target/%.o LWIP/Target/%.su LWIP/Target/%.cyclo: ../LWIP/Target/%.c LWIP/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-LWIP-2f-Target + +clean-LWIP-2f-Target: + -$(RM) ./LWIP/Target/ethernetif.cyclo ./LWIP/Target/ethernetif.d ./LWIP/Target/ethernetif.o ./LWIP/Target/ethernetif.su + +.PHONY: clean-LWIP-2f-Target + diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo new file mode 100644 index 0000000..b5e45d8 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo @@ -0,0 +1,56 @@ +cmsis_os.c:103:31:makeFreeRtosPriority 2 +cmsis_os.c:116:19:makeCmsisPriority 2 +cmsis_os.c:130:12:inHandlerMode 1 +cmsis_os.c:150:10:osKernelStart 1 +cmsis_os.c:165:9:osKernelRunning 2 +cmsis_os.c:184:10:osKernelSysTick 2 +cmsis_os.c:202:12:osThreadCreate 4 +cmsis_os.c:240:12:osThreadGetId 1 +cmsis_os.c:255:10:osThreadTerminate 1 +cmsis_os.c:270:10:osThreadYield 1 +cmsis_os.c:284:10:osThreadSetPriority 1 +cmsis_os.c:300:12:osThreadGetPriority 2 +cmsis_os.c:322:10:osDelay 2 +cmsis_os.c:357:11:osTimerCreate 1 +cmsis_os.c:404:10:osTimerStart 1 +cmsis_os.c:443:10:osTimerStop 1 +cmsis_os.c:472:10:osTimerDelete 1 +cmsis_os.c:502:9:osSignalSet 5 +cmsis_os.c:543:9:osSignalWait 8 +cmsis_os.c:597:11:osMutexCreate 2 +cmsis_os.c:626:10:osMutexWait 9 +cmsis_os.c:666:10:osMutexRelease 5 +cmsis_os.c:690:10:osMutexDelete 2 +cmsis_os.c:712:15:osSemaphoreCreate 5 +cmsis_os.c:779:9:osSemaphoreWait 9 +cmsis_os.c:819:10:osSemaphoreRelease 5 +cmsis_os.c:846:10:osSemaphoreDelete 2 +cmsis_os.c:883:10:osPoolCreate 5 +cmsis_os.c:936:7:osPoolAlloc 5 +cmsis_os.c:977:7:osPoolCAlloc 2 +cmsis_os.c:996:10:osPoolFree 6 +cmsis_os.c:1040:14:osMessageCreate 3 +cmsis_os.c:1067:10:osMessagePut 6 +cmsis_os.c:1099:9:osMessageGet 10 +cmsis_os.c:1168:11:osMailCreate 4 +cmsis_os.c:1214:7:osMailAlloc 2 +cmsis_os.c:1236:7:osMailCAlloc 3 +cmsis_os.c:1257:10:osMailPut 6 +cmsis_os.c:1290:9:osMailGet 10 +cmsis_os.c:1346:10:osMailFree 2 +cmsis_os.c:1362:6:osSystickHandler 2 +cmsis_os.c:1432:10:osThreadSuspend 1 +cmsis_os.c:1448:10:osThreadResume 3 +cmsis_os.c:1472:10:osThreadSuspendAll 1 +cmsis_os.c:1483:10:osThreadResumeAll 2 +cmsis_os.c:1500:10:osDelayUntil 1 +cmsis_os.c:1520:10:osAbortDelay 1 +cmsis_os.c:1541:10:osThreadList 1 +cmsis_os.c:1555:9:osMessagePeek 7 +cmsis_os.c:1596:10:osMessageWaiting 2 +cmsis_os.c:1612:10:osMessageAvailableSpace 1 +cmsis_os.c:1622:10:osMessageDelete 2 +cmsis_os.c:1638:11:osRecursiveMutexCreate 1 +cmsis_os.c:1664:10:osRecursiveMutexRelease 1 +cmsis_os.c:1685:10:osRecursiveMutexWait 1 +cmsis_os.c:1724:10:osSemaphoreGetCount 1 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d new file mode 100644 index 0000000..bbd3cae --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d @@ -0,0 +1,38 @@ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o new file mode 100644 index 0000000..4c6f5ce Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su new file mode 100644 index 0000000..ab773ef --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su @@ -0,0 +1,56 @@ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:103:31:makeFreeRtosPriority 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:116:19:makeCmsisPriority 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:130:12:inHandlerMode 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:150:10:osKernelStart 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:165:9:osKernelRunning 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:184:10:osKernelSysTick 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:202:12:osThreadCreate 56 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:240:12:osThreadGetId 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:255:10:osThreadTerminate 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:270:10:osThreadYield 4 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:284:10:osThreadSetPriority 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:300:12:osThreadGetPriority 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:322:10:osDelay 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:357:11:osTimerCreate 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:404:10:osTimerStart 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:443:10:osTimerStop 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:472:10:osTimerDelete 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:502:9:osSignalSet 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:543:9:osSignalWait 48 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:597:11:osMutexCreate 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:626:10:osMutexWait 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:666:10:osMutexRelease 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:690:10:osMutexDelete 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:712:15:osSemaphoreCreate 32 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:779:9:osSemaphoreWait 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:819:10:osSemaphoreRelease 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:846:10:osSemaphoreDelete 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:883:10:osPoolCreate 32 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:936:7:osPoolAlloc 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:977:7:osPoolCAlloc 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:996:10:osPoolFree 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1040:14:osMessageCreate 32 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1067:10:osMessagePut 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1099:9:osMessageGet 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1168:11:osMailCreate 40 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1214:7:osMailAlloc 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1236:7:osMailCAlloc 24 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1257:10:osMailPut 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1290:9:osMailGet 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1346:10:osMailFree 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1362:6:osSystickHandler 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1432:10:osThreadSuspend 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1448:10:osThreadResume 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1472:10:osThreadSuspendAll 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1483:10:osThreadResumeAll 8 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1500:10:osDelayUntil 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1520:10:osAbortDelay 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1541:10:osThreadList 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1555:9:osMessagePeek 48 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1596:10:osMessageWaiting 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1612:10:osMessageAvailableSpace 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1622:10:osMessageDelete 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1638:11:osRecursiveMutexCreate 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1664:10:osRecursiveMutexRelease 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1685:10:osRecursiveMutexWait 16 static +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c:1724:10:osSemaphoreGetCount 16 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk new file mode 100644 index 0000000..b3f8606 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.o Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.su Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/%.c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-CMSIS_RTOS + diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d new file mode 100644 index 0000000..bcf8508 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d @@ -0,0 +1,22 @@ +Middlewares/Third_Party/FreeRTOS/Source/croutine.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o new file mode 100644 index 0000000..7e600fb Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo new file mode 100644 index 0000000..4f6c3e9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo @@ -0,0 +1,11 @@ +event_groups.c:93:21:xEventGroupCreateStatic 4 +event_groups.c:145:21:xEventGroupCreate 2 +event_groups.c:191:13:xEventGroupSync 12 +event_groups.c:311:13:xEventGroupWaitBits 17 +event_groups.c:461:13:xEventGroupClearBits 3 +event_groups.c:503:13:xEventGroupGetBitsFromISR 1 +event_groups.c:519:13:xEventGroupSetBits 9 +event_groups.c:613:6:vEventGroupDelete 4 +event_groups.c:657:6:vEventGroupSetBitsCallback 1 +event_groups.c:665:6:vEventGroupClearBitsCallback 1 +event_groups.c:671:19:prvTestWaitCondition 4 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d new file mode 100644 index 0000000..ee6c017 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d @@ -0,0 +1,28 @@ +Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o new file mode 100644 index 0000000..a6d53f5 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su new file mode 100644 index 0000000..b97429e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:93:21:xEventGroupCreateStatic 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:145:21:xEventGroupCreate 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:191:13:xEventGroupSync 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:311:13:xEventGroupWaitBits 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:461:13:xEventGroupClearBits 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:503:13:xEventGroupGetBitsFromISR 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:519:13:xEventGroupSetBits 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:613:6:vEventGroupDelete 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:657:6:vEventGroupSetBitsCallback 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:665:6:vEventGroupClearBitsCallback 16 static +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c:671:19:prvTestWaitCondition 32 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo new file mode 100644 index 0000000..dfff30c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.cyclo @@ -0,0 +1,5 @@ +list.c:37:6:vListInitialise 1 +list.c:62:6:vListInitialiseItem 1 +list.c:74:6:vListInsertEnd 1 +list.c:103:6:vListInsert 3 +list.c:170:13:uxListRemove 2 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d new file mode 100644 index 0000000..a7721f0 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d @@ -0,0 +1,18 @@ +Middlewares/Third_Party/FreeRTOS/Source/list.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/list.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o new file mode 100644 index 0000000..47924d9 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su new file mode 100644 index 0000000..85c9323 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/FreeRTOS/Source/list.c:37:6:vListInitialise 16 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:62:6:vListInitialiseItem 16 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:74:6:vListInsertEnd 24 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:103:6:vListInsert 24 static +../Middlewares/Third_Party/FreeRTOS/Source/list.c:170:13:uxListRemove 24 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.cyclo new file mode 100644 index 0000000..51e9be3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.cyclo @@ -0,0 +1,13 @@ +port.c:181:14:pxPortInitialiseStack 1 +port.c:211:13:prvTaskExitError 3 +port.c:236:6:SVC_Handler 1 +port.c:255:13:prvPortStartFirstTask 1 +port.c:281:12:xPortStartScheduler 3 +port.c:383:6:vPortEndScheduler 2 +port.c:391:6:vPortEnterCritical 3 +port.c:408:6:vPortExitCritical 3 +port.c:419:6:PendSV_Handler 1 +port.c:478:6:SysTick_Handler 2 +port.c:669:30:vPortSetupTimerInterrupt 1 +port.c:691:13:vPortEnableVFP 1 +port.c:707:7:vPortValidateInterruptPriority 4 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d new file mode 100644 index 0000000..be2e557 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d @@ -0,0 +1,20 @@ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o new file mode 100644 index 0000000..4b5dfa0 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su new file mode 100644 index 0000000..5b45ba7 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su @@ -0,0 +1,13 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:181:14:pxPortInitialiseStack 24 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:211:13:prvTaskExitError 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:236:6:SVC_Handler 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:255:13:prvPortStartFirstTask 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:281:12:xPortStartScheduler 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:383:6:vPortEndScheduler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:391:6:vPortEnterCritical 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:408:6:vPortExitCritical 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:419:6:PendSV_Handler 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:478:6:SysTick_Handler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:669:30:vPortSetupTimerInterrupt 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:691:13:vPortEnableVFP 0 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c:707:7:vPortValidateInterruptPriority 24 static,ignoring_inline_asm diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk new file mode 100644 index 0000000..7765289 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM7-2f-r0p1 + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM7-2f-r0p1: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-GCC-2f-ARM_CM7-2f-r0p1 + diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo new file mode 100644 index 0000000..6e234f5 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo @@ -0,0 +1,7 @@ +heap_4.c:113:7:pvPortMalloc 15 +heap_4.c:263:6:vPortFree 6 +heap_4.c:311:8:xPortGetFreeHeapSize 1 +heap_4.c:317:8:xPortGetMinimumEverFreeHeapSize 1 +heap_4.c:323:6:vPortInitialiseBlocks 1 +heap_4.c:329:13:prvHeapInit 2 +heap_4.c:377:13:prvInsertBlockIntoFreeList 6 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d new file mode 100644 index 0000000..ffc0888 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d @@ -0,0 +1,20 @@ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o new file mode 100644 index 0000000..073d789 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su new file mode 100644 index 0000000..4047e29 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su @@ -0,0 +1,7 @@ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:113:7:pvPortMalloc 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:263:6:vPortFree 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:311:8:xPortGetFreeHeapSize 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:317:8:xPortGetMinimumEverFreeHeapSize 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:323:6:vPortInitialiseBlocks 4 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:329:13:prvHeapInit 24 static +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c:377:13:prvInsertBlockIntoFreeList 24 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk new file mode 100644 index 0000000..baf357f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.o Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.su Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/%.c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source-2f-portable-2f-MemMang + diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo new file mode 100644 index 0000000..480f842 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo @@ -0,0 +1,30 @@ +queue.c:255:12:xQueueGenericReset 5 +queue.c:310:16:xQueueGenericCreateStatic 11 +queue.c:368:16:xQueueGenericCreate 4 +queue.c:429:13:prvInitialiseNewQueue 2 +queue.c:473:14:prvInitialiseMutex 2 +queue.c:503:16:xQueueCreateMutex 1 +queue.c:519:16:xQueueCreateMutexStatic 1 +queue.c:747:12:xQueueGenericSend 23 +queue.c:957:12:xQueueGenericSendFromISR 14 +queue.c:1108:12:xQueueGiveFromISR 11 +queue.c:1273:12:xQueueReceive 19 +queue.c:1414:12:xQueueSemaphoreTake 21 +queue.c:1632:12:xQueuePeek 19 +queue.c:1781:12:xQueueReceiveFromISR 10 +queue.c:1872:12:xQueuePeekFromISR 7 +queue.c:1926:13:uxQueueMessagesWaiting 2 +queue.c:1942:13:uxQueueSpacesAvailable 2 +queue.c:1959:13:uxQueueMessagesWaitingFromISR 2 +queue.c:1971:6:vQueueDelete 3 +queue.c:2045:21:prvGetDisinheritPriorityAfterTimeout 2 +queue.c:2070:19:prvCopyDataToQueue 8 +queue.c:2149:13:prvCopyDataFromQueue 3 +queue.c:2167:13:prvUnlockQueue 7 +queue.c:2287:19:prvIsQueueEmpty 2 +queue.c:2308:12:xQueueIsQueueEmptyFromISR 3 +queue.c:2327:19:prvIsQueueFull 2 +queue.c:2348:12:xQueueIsQueueFullFromISR 3 +queue.c:2644:7:vQueueAddToRegistry 3 +queue.c:2673:14:pcQueueGetName 3 +queue.c:2701:7:vQueueUnregisterQueue 3 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d new file mode 100644 index 0000000..4634bd2 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d @@ -0,0 +1,24 @@ +Middlewares/Third_Party/FreeRTOS/Source/queue.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o new file mode 100644 index 0000000..ca8e9f7 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su new file mode 100644 index 0000000..dfc49f8 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su @@ -0,0 +1,30 @@ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:255:12:xQueueGenericReset 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:310:16:xQueueGenericCreateStatic 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:368:16:xQueueGenericCreate 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:429:13:prvInitialiseNewQueue 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:473:14:prvInitialiseMutex 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:503:16:xQueueCreateMutex 32 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:519:16:xQueueCreateMutexStatic 40 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:747:12:xQueueGenericSend 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:957:12:xQueueGenericSendFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1108:12:xQueueGiveFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1273:12:xQueueReceive 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1414:12:xQueueSemaphoreTake 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1632:12:xQueuePeek 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1781:12:xQueueReceiveFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1872:12:xQueuePeekFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1926:13:uxQueueMessagesWaiting 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1942:13:uxQueueSpacesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1959:13:uxQueueMessagesWaitingFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:1971:6:vQueueDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2045:21:prvGetDisinheritPriorityAfterTimeout 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2070:19:prvCopyDataToQueue 32 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2149:13:prvCopyDataFromQueue 16 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2167:13:prvUnlockQueue 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2287:19:prvIsQueueEmpty 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2308:12:xQueueIsQueueEmptyFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2327:19:prvIsQueueFull 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2348:12:xQueueIsQueueFullFromISR 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2644:7:vQueueAddToRegistry 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2673:14:pcQueueGetName 24 static +../Middlewares/Third_Party/FreeRTOS/Source/queue.c:2701:7:vQueueUnregisterQueue 24 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo new file mode 100644 index 0000000..8bedd57 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo @@ -0,0 +1,22 @@ +stream_buffer.c:219:23:xStreamBufferGenericCreate 7 +stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 10 +stream_buffer.c:359:6:vStreamBufferDelete 3 +stream_buffer.c:392:12:xStreamBufferReset 4 +stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 4 +stream_buffer.c:470:8:xStreamBufferSpacesAvailable 3 +stream_buffer.c:494:8:xStreamBufferBytesAvailable 2 +stream_buffer.c:506:8:xStreamBufferSend 13 +stream_buffer.c:610:8:xStreamBufferSendFromISR 7 +stream_buffer.c:661:15:prvWriteMessageToBuffer 5 +stream_buffer.c:713:8:xStreamBufferReceive 11 +stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 5 +stream_buffer.c:861:8:xStreamBufferReceiveFromISR 7 +stream_buffer.c:918:15:prvReadMessageFromBuffer 3 +stream_buffer.c:970:12:xStreamBufferIsEmpty 3 +stream_buffer.c:993:12:xStreamBufferIsFull 4 +stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 3 +stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 3 +stream_buffer.c:1088:15:prvWriteBytesToBuffer 6 +stream_buffer.c:1134:15:prvReadBytesFromBuffer 7 +stream_buffer.c:1189:15:prvBytesInBuffer 2 +stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 2 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d new file mode 100644 index 0000000..4d6c457 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d @@ -0,0 +1,22 @@ +Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o new file mode 100644 index 0000000..64238f8 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su new file mode 100644 index 0000000..ea54a6c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su @@ -0,0 +1,22 @@ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:219:23:xStreamBufferGenericCreate 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:359:6:vStreamBufferDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:392:12:xStreamBufferReset 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:470:8:xStreamBufferSpacesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:494:8:xStreamBufferBytesAvailable 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:506:8:xStreamBufferSend 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:610:8:xStreamBufferSendFromISR 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:661:15:prvWriteMessageToBuffer 32 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:713:8:xStreamBufferReceive 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:861:8:xStreamBufferReceiveFromISR 72 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:918:15:prvReadMessageFromBuffer 40 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:970:12:xStreamBufferIsEmpty 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:993:12:xStreamBufferIsFull 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 56 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1088:15:prvWriteBytesToBuffer 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1134:15:prvReadBytesFromBuffer 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1189:15:prvBytesInBuffer 24 static +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 32 static,ignoring_inline_asm diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk new file mode 100644 index 0000000..73b3e96 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -0,0 +1,45 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ +../Middlewares/Third_Party/FreeRTOS/Source/list.c \ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \ +./Middlewares/Third_Party/FreeRTOS/Source/list.o \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.o \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \ +./Middlewares/Third_Party/FreeRTOS/Source/list.d \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.d \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/%.o Middlewares/Third_Party/FreeRTOS/Source/%.su Middlewares/Third_Party/FreeRTOS/Source/%.cyclo: ../Middlewares/Third_Party/FreeRTOS/Source/%.c Middlewares/Third_Party/FreeRTOS/Source/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source + +clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source: + -$(RM) ./Middlewares/Third_Party/FreeRTOS/Source/croutine.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/croutine.d ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o ./Middlewares/Third_Party/FreeRTOS/Source/croutine.su ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.su ./Middlewares/Third_Party/FreeRTOS/Source/list.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/list.d ./Middlewares/Third_Party/FreeRTOS/Source/list.o ./Middlewares/Third_Party/FreeRTOS/Source/list.su ./Middlewares/Third_Party/FreeRTOS/Source/queue.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/queue.d ./Middlewares/Third_Party/FreeRTOS/Source/queue.o ./Middlewares/Third_Party/FreeRTOS/Source/queue.su ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su ./Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/tasks.d ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o ./Middlewares/Third_Party/FreeRTOS/Source/tasks.su ./Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo ./Middlewares/Third_Party/FreeRTOS/Source/timers.d ./Middlewares/Third_Party/FreeRTOS/Source/timers.o ./Middlewares/Third_Party/FreeRTOS/Source/timers.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-FreeRTOS-2f-Source + diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo new file mode 100644 index 0000000..08f333f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.cyclo @@ -0,0 +1,50 @@ +tasks.c:578:15:xTaskCreateStatic 6 +tasks.c:730:13:xTaskCreate 4 +tasks.c:821:13:prvInitialiseNewTask 7 +tasks.c:1072:13:prvAddNewTaskToReadyList 7 +tasks.c:1157:7:vTaskDelete 9 +tasks.c:1333:7:vTaskDelay 4 +tasks.c:1470:14:uxTaskPriorityGet 2 +tasks.c:1492:14:uxTaskPriorityGetFromISR 2 +tasks.c:1532:7:vTaskPrioritySet 14 +tasks.c:1696:7:vTaskSuspend 11 +tasks.c:1797:20:prvTaskIsTaskSuspended 5 +tasks.c:1843:7:vTaskResume 6 +tasks.c:1897:13:xTaskResumeFromISR 5 +tasks.c:1967:6:vTaskStartScheduler 4 +tasks.c:2089:6:vTaskEndScheduler 1 +tasks.c:2100:6:vTaskSuspendAll 1 +tasks.c:2174:12:xTaskResumeAll 11 +tasks.c:2284:12:xTaskGetTickCount 1 +tasks.c:2299:12:xTaskGetTickCountFromISR 1 +tasks.c:2330:13:uxTaskGetNumberOfTasks 1 +tasks.c:2338:7:pcTaskGetName 3 +tasks.c:2665:12:xTaskIncrementTick 11 +tasks.c:2947:6:vTaskSwitchContext 4 +tasks.c:3020:6:vTaskPlaceOnEventList 2 +tasks.c:3037:6:vTaskPlaceOnUnorderedEventList 3 +tasks.c:3094:12:xTaskRemoveFromEventList 4 +tasks.c:3162:6:vTaskRemoveFromUnorderedEventList 4 +tasks.c:3196:6:vTaskSetTimeOutState 2 +tasks.c:3208:6:vTaskInternalSetTimeOutState 1 +tasks.c:3216:12:xTaskCheckForTimeOut 7 +tasks.c:3279:6:vTaskMissedYield 1 +tasks.c:3334:8:prvIdleTask 2 +tasks.c:3546:13:prvInitialiseTaskLists 2 +tasks.c:3578:13:prvCheckTasksWaitingTermination 2 +tasks.c:3826:14:prvDeleteTCB 4 +tasks.c:3880:13:prvResetNextTaskUnblockTime 2 +tasks.c:3906:15:xTaskGetCurrentTaskHandle 1 +tasks.c:3923:13:xTaskGetSchedulerState 3 +tasks.c:3951:13:xTaskPriorityInherit 8 +tasks.c:4038:13:xTaskPriorityDisinherit 8 +tasks.c:4118:7:vTaskPriorityDisinheritAfterTimeout 11 +tasks.c:4533:12:uxTaskResetEventItemValue 1 +tasks.c:4549:15:pvTaskIncrementMutexHeldCount 2 +tasks.c:4566:11:ulTaskNotifyTake 5 +tasks.c:4634:13:xTaskNotifyWait 5 +tasks.c:4714:13:xTaskGenericNotify 13 +tasks.c:4828:13:xTaskGenericNotifyFromISR 15 +tasks.c:4957:7:vTaskNotifyGiveFromISR 7 +tasks.c:5044:13:xTaskNotifyStateClear 3 +tasks.c:5081:13:prvAddCurrentTaskToDelayedList 6 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d new file mode 100644 index 0000000..40c3264 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d @@ -0,0 +1,26 @@ +Middlewares/Third_Party/FreeRTOS/Source/tasks.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o new file mode 100644 index 0000000..0890bee Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su new file mode 100644 index 0000000..aa7f2bf --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su @@ -0,0 +1,50 @@ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:578:15:xTaskCreateStatic 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:730:13:xTaskCreate 56 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:821:13:prvInitialiseNewTask 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1072:13:prvAddNewTaskToReadyList 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1157:7:vTaskDelete 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1333:7:vTaskDelay 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1470:14:uxTaskPriorityGet 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1492:14:uxTaskPriorityGetFromISR 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1532:7:vTaskPrioritySet 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1696:7:vTaskSuspend 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1797:20:prvTaskIsTaskSuspended 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1843:7:vTaskResume 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1897:13:xTaskResumeFromISR 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:1967:6:vTaskStartScheduler 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2089:6:vTaskEndScheduler 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2100:6:vTaskSuspendAll 4 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2174:12:xTaskResumeAll 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2284:12:xTaskGetTickCount 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2299:12:xTaskGetTickCountFromISR 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2330:13:uxTaskGetNumberOfTasks 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2338:7:pcTaskGetName 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2665:12:xTaskIncrementTick 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:2947:6:vTaskSwitchContext 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3020:6:vTaskPlaceOnEventList 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3037:6:vTaskPlaceOnUnorderedEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3094:12:xTaskRemoveFromEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3162:6:vTaskRemoveFromUnorderedEventList 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3196:6:vTaskSetTimeOutState 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3208:6:vTaskInternalSetTimeOutState 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3216:12:xTaskCheckForTimeOut 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3279:6:vTaskMissedYield 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3334:8:prvIdleTask 16 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3546:13:prvInitialiseTaskLists 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3578:13:prvCheckTasksWaitingTermination 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3826:14:prvDeleteTCB 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3880:13:prvResetNextTaskUnblockTime 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3906:15:xTaskGetCurrentTaskHandle 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3923:13:xTaskGetSchedulerState 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:3951:13:xTaskPriorityInherit 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4038:13:xTaskPriorityDisinherit 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4118:7:vTaskPriorityDisinheritAfterTimeout 40 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4533:12:uxTaskResetEventItemValue 16 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4549:15:pvTaskIncrementMutexHeldCount 4 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4566:11:ulTaskNotifyTake 24 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4634:13:xTaskNotifyWait 32 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4714:13:xTaskGenericNotify 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4828:13:xTaskGenericNotifyFromISR 64 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:4957:7:vTaskNotifyGiveFromISR 48 static,ignoring_inline_asm +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5044:13:xTaskNotifyStateClear 24 static +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c:5081:13:prvAddCurrentTaskToDelayedList 24 static diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d new file mode 100644 index 0000000..2d4cc50 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d @@ -0,0 +1,26 @@ +Middlewares/Third_Party/FreeRTOS/Source/timers.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/timers.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o new file mode 100644 index 0000000..0d3b19e Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o differ diff --git a/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/project/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo new file mode 100644 index 0000000..a2be8ca --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo @@ -0,0 +1,29 @@ +api_lib.c:118:1:netconn_apimsg 2 +api_lib.c:149:1:netconn_new_with_proto_and_callback 7 +api_lib.c:192:1:netconn_prepare_delete 3 +api_lib.c:233:1:netconn_delete 3 +api_lib.c:269:1:netconn_getaddr 4 +api_lib.c:307:1:netconn_bind 3 +api_lib.c:351:1:netconn_bind_if 2 +api_lib.c:377:1:netconn_connect 3 +api_lib.c:409:1:netconn_disconnect 2 +api_lib.c:434:1:netconn_listen_with_backlog 2 +api_lib.c:471:1:netconn_accept 11 +api_lib.c:579:1:netconn_recv_data 17 +api_lib.c:677:1:netconn_tcp_recvd_msg 3 +api_lib.c:689:1:netconn_tcp_recvd 3 +api_lib.c:703:1:netconn_recv_data_tcp 11 +api_lib.c:782:1:netconn_recv_tcp_pbuf 3 +api_lib.c:803:1:netconn_recv_tcp_pbuf_flags 3 +api_lib.c:822:1:netconn_recv_udp_raw_netbuf 3 +api_lib.c:842:1:netconn_recv_udp_raw_netbuf_flags 3 +api_lib.c:860:1:netconn_recv 7 +api_lib.c:922:1:netconn_sendto 3 +api_lib.c:941:1:netconn_send 2 +api_lib.c:974:1:netconn_write_partly 1 +api_lib.c:997:1:netconn_write_vectors_partly 16 +api_lib.c:1089:1:netconn_close_shutdown 2 +api_lib.c:1125:1:netconn_close 1 +api_lib.c:1139:1:netconn_err 2 +api_lib.c:1163:1:netconn_shutdown 3 +api_lib.c:1274:1:netconn_gethostbyname 5 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d new file mode 100644 index 0000000..a653065 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d @@ -0,0 +1,199 @@ +Middlewares/Third_Party/LwIP/src/api/api_lib.o: \ + ../Middlewares/Third_Party/LwIP/src/api/api_lib.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o new file mode 100644 index 0000000..8b44f90 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su new file mode 100644 index 0000000..854a6ac --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su @@ -0,0 +1,29 @@ +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:118:1:netconn_apimsg 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:149:1:netconn_new_with_proto_and_callback 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:192:1:netconn_prepare_delete 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:233:1:netconn_delete 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:269:1:netconn_getaddr 64 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:307:1:netconn_bind 64 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:351:1:netconn_bind_if 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:377:1:netconn_connect 64 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:409:1:netconn_disconnect 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:434:1:netconn_listen_with_backlog 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:471:1:netconn_accept 32 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:579:1:netconn_recv_data 40 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:677:1:netconn_tcp_recvd_msg 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:689:1:netconn_tcp_recvd 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:703:1:netconn_recv_data_tcp 72 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:782:1:netconn_recv_tcp_pbuf 16 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:803:1:netconn_recv_tcp_pbuf_flags 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:822:1:netconn_recv_udp_raw_netbuf 16 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:842:1:netconn_recv_udp_raw_netbuf_flags 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:860:1:netconn_recv 32 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:922:1:netconn_sendto 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:941:1:netconn_send 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:974:1:netconn_write_partly 40 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:997:1:netconn_write_vectors_partly 80 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1089:1:netconn_close_shutdown 56 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1125:1:netconn_close 16 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1139:1:netconn_err 24 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1163:1:netconn_shutdown 16 static +../Middlewares/Third_Party/LwIP/src/api/api_lib.c:1274:1:netconn_gethostbyname 48 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo new file mode 100644 index 0000000..5814899 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo @@ -0,0 +1,30 @@ +api_msg.c:115:1:lwip_netconn_err_to_msg 6 +api_msg.c:131:1:lwip_netconn_is_err_msg 5 +api_msg.c:218:1:recv_udp 10 +api_msg.c:293:1:recv_tcp 11 +api_msg.c:357:1:poll_tcp 11 +api_msg.c:398:1:sent_tcp 9 +api_msg.c:432:1:err_tcp 15 +api_msg.c:514:1:setup_tcp 1 +api_msg.c:533:1:accept_function 12 +api_msg.c:609:1:pcb_new 8 +api_msg.c:680:1:lwip_netconn_do_newconn 2 +api_msg.c:705:1:netconn_alloc 6 +api_msg.c:794:1:netconn_free 4 +api_msg.c:827:1:netconn_drain 9 +api_msg.c:920:1:lwip_netconn_do_close_internal 36 +api_msg.c:1113:1:lwip_netconn_do_delconn 19 +api_msg.c:1216:1:lwip_netconn_do_bind 4 +api_msg.c:1256:1:lwip_netconn_do_bind_if 5 +api_msg.c:1301:1:lwip_netconn_do_connected 14 +api_msg.c:1350:1:lwip_netconn_do_connect 11 +api_msg.c:1425:1:lwip_netconn_do_disconnect 2 +api_msg.c:1449:1:lwip_netconn_do_listen 10 +api_msg.c:1532:1:lwip_netconn_do_send 5 +api_msg.c:1589:1:lwip_netconn_do_recv 5 +api_msg.c:1640:1:lwip_netconn_do_writemore 42 +api_msg.c:1813:1:lwip_netconn_do_write 10 +api_msg.c:1867:1:lwip_netconn_do_getaddr 11 +api_msg.c:1934:1:lwip_netconn_do_close 12 +api_msg.c:2117:1:lwip_netconn_do_dns_found 2 +api_msg.c:2143:1:lwip_netconn_do_gethostbyname 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d new file mode 100644 index 0000000..367b229 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d @@ -0,0 +1,199 @@ +Middlewares/Third_Party/LwIP/src/api/api_msg.o: \ + ../Middlewares/Third_Party/LwIP/src/api/api_msg.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o new file mode 100644 index 0000000..66109ab Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su new file mode 100644 index 0000000..2084657 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su @@ -0,0 +1,30 @@ +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:115:1:lwip_netconn_err_to_msg 16 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:131:1:lwip_netconn_is_err_msg 16 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:218:1:recv_udp 40 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:293:1:recv_tcp 40 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:357:1:poll_tcp 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:398:1:sent_tcp 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:432:1:err_tcp 40 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:514:1:setup_tcp 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:533:1:accept_function 48 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:609:1:pcb_new 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:680:1:lwip_netconn_do_newconn 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:705:1:netconn_alloc 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:794:1:netconn_free 16 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:827:1:netconn_drain 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:920:1:lwip_netconn_do_close_internal 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1113:1:lwip_netconn_do_delconn 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1216:1:lwip_netconn_do_bind 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1256:1:lwip_netconn_do_bind_if 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1301:1:lwip_netconn_do_connected 40 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1350:1:lwip_netconn_do_connect 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1425:1:lwip_netconn_do_disconnect 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1449:1:lwip_netconn_do_listen 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1532:1:lwip_netconn_do_send 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1589:1:lwip_netconn_do_recv 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1640:1:lwip_netconn_do_writemore 40 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1813:1:lwip_netconn_do_write 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1867:1:lwip_netconn_do_getaddr 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:1934:1:lwip_netconn_do_close 24 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:2117:1:lwip_netconn_do_dns_found 32 static +../Middlewares/Third_Party/LwIP/src/api/api_msg.c:2143:1:lwip_netconn_do_gethostbyname 40 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo new file mode 100644 index 0000000..9abc784 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo @@ -0,0 +1 @@ +err.c:69:1:err_to_errno 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.d new file mode 100644 index 0000000..bbd15c9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.d @@ -0,0 +1,135 @@ +Middlewares/Third_Party/LwIP/src/api/err.o: \ + ../Middlewares/Third_Party/LwIP/src/api/err.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.o new file mode 100644 index 0000000..bb185cc Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.su new file mode 100644 index 0000000..e596201 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/err.su @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/api/err.c:69:1:err_to_errno 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo new file mode 100644 index 0000000..98ff4c7 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo @@ -0,0 +1,2 @@ +if_api.c:61:1:lwip_if_indextoname 1 +if_api.c:86:1:lwip_if_nametoindex 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d new file mode 100644 index 0000000..74546da --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d @@ -0,0 +1,169 @@ +Middlewares/Third_Party/LwIP/src/api/if_api.o: \ + ../Middlewares/Third_Party/LwIP/src/api/if_api.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o new file mode 100644 index 0000000..137f0e1 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su new file mode 100644 index 0000000..72be15e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su @@ -0,0 +1,2 @@ +../Middlewares/Third_Party/LwIP/src/api/if_api.c:61:1:lwip_if_indextoname 16 static +../Middlewares/Third_Party/LwIP/src/api/if_api.c:86:1:lwip_if_nametoindex 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo new file mode 100644 index 0000000..67a52b4 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo @@ -0,0 +1,9 @@ +netbuf.c:63:9:netbuf_new 2 +netbuf.c:81:1:netbuf_delete 3 +netbuf.c:102:1:netbuf_alloc 5 +netbuf.c:127:1:netbuf_free 3 +netbuf.c:151:1:netbuf_ref 4 +netbuf.c:176:1:netbuf_chain 3 +netbuf.c:196:1:netbuf_data 5 +netbuf.c:222:1:netbuf_next 4 +netbuf.c:244:1:netbuf_first 2 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d new file mode 100644 index 0000000..ea1c3d7 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d @@ -0,0 +1,119 @@ +Middlewares/Third_Party/LwIP/src/api/netbuf.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netbuf.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o new file mode 100644 index 0000000..6395357 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su new file mode 100644 index 0000000..0a5bba8 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:63:9:netbuf_new 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:81:1:netbuf_delete 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:102:1:netbuf_alloc 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:127:1:netbuf_free 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:151:1:netbuf_ref 24 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:176:1:netbuf_chain 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:196:1:netbuf_data 24 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:222:1:netbuf_next 16 static +../Middlewares/Third_Party/LwIP/src/api/netbuf.c:244:1:netbuf_first 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.cyclo new file mode 100644 index 0000000..467891d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.cyclo @@ -0,0 +1,4 @@ +netdb.c:87:1:lwip_gethostbyname 2 +netdb.c:162:1:lwip_gethostbyname_r 8 +netdb.c:236:1:lwip_freeaddrinfo 2 +netdb.c:269:1:lwip_getaddrinfo 24 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d new file mode 100644 index 0000000..6b196a3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d @@ -0,0 +1,171 @@ +Middlewares/Third_Party/LwIP/src/api/netdb.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netdb.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h +../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o new file mode 100644 index 0000000..45a8346 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.su new file mode 100644 index 0000000..5db8f22 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.su @@ -0,0 +1,4 @@ +../Middlewares/Third_Party/LwIP/src/api/netdb.c:87:1:lwip_gethostbyname 24 static +../Middlewares/Third_Party/LwIP/src/api/netdb.c:162:1:lwip_gethostbyname_r 48 static +../Middlewares/Third_Party/LwIP/src/api/netdb.c:236:1:lwip_freeaddrinfo 24 static +../Middlewares/Third_Party/LwIP/src/api/netdb.c:269:1:lwip_getaddrinfo 64 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d new file mode 100644 index 0000000..8f1eb9e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/api/netifapi.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netifapi.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o new file mode 100644 index 0000000..150c4f8 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo new file mode 100644 index 0000000..c44da07 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo @@ -0,0 +1,54 @@ +sockets.c:320:1:lwip_socket_thread_init 1 +sockets.c:327:1:lwip_socket_thread_cleanup 1 +sockets.c:411:1:tryget_socket_unconn_nouse 3 +sockets.c:422:1:lwip_socket_dbg_get_socket 1 +sockets.c:429:1:tryget_socket_unconn 1 +sockets.c:442:1:tryget_socket_unconn_locked 1 +sockets.c:460:1:tryget_socket 3 +sockets.c:479:1:get_socket 2 +sockets.c:501:1:alloc_socket 6 +sockets.c:548:1:free_socket_locked 1 +sockets.c:572:1:free_socket_free_elements 4 +sockets.c:594:1:free_socket 2 +sockets.c:620:1:lwip_accept 21 +sockets.c:718:1:lwip_bind 9 +sockets.c:772:1:lwip_close 6 +sockets.c:813:1:lwip_connect 11 +sockets.c:881:1:lwip_listen 8 +sockets.c:920:1:lwip_recv_tcp 22 +sockets.c:1023:1:lwip_sock_make_addr 6 +sockets.c:1056:1:lwip_recv_tcp_from 6 +sockets.c:1088:1:lwip_recvfrom_udp_raw 18 +sockets.c:1199:1:lwip_recvfrom 9 +sockets.c:1252:1:lwip_read 1 +sockets.c:1258:1:lwip_readv 1 +sockets.c:1275:1:lwip_recv 1 +sockets.c:1281:1:lwip_recvmsg 24 +sockets.c:1382:1:lwip_send 6 +sockets.c:1422:1:lwip_sendmsg 30 +sockets.c:1585:1:lwip_sendto 16 +sockets.c:1685:1:lwip_socket 8 +sockets.c:1746:1:lwip_write 1 +sockets.c:1752:1:lwip_writev 1 +sockets.c:1771:1:lwip_link_select_cb 2 +sockets.c:1795:1:lwip_unlink_select_cb 5 +sockets.c:1835:1:lwip_selscan 32 +sockets.c:1964:1:lwip_select 43 +sockets.c:2193:1:lwip_pollscan 19 +sockets.c:2319:1:lwip_poll 13 +sockets.c:2438:1:lwip_poll_should_wake 8 +sockets.c:2477:1:event_callback 15 +sockets.c:2576:13:select_check_waiters 19 +sockets.c:2655:1:lwip_shutdown 12 +sockets.c:2700:1:lwip_getaddrname 6 +sockets.c:2747:1:lwip_getpeername 1 +sockets.c:2753:1:lwip_getsockname 1 +sockets.c:2759:1:lwip_getsockopt 7 +sockets.c:2859:1:lwip_sockopt_to_ipopt 5 +sockets.c:2882:1:lwip_getsockopt_impl 55 +sockets.c:3205:1:lwip_setsockopt 6 +sockets.c:3303:1:lwip_setsockopt_impl 47 +sockets.c:3743:1:lwip_ioctl 8 +sockets.c:3836:1:lwip_fcntl 14 +sockets.c:3919:1:lwip_inet_ntop 4 +sockets.c:3952:1:lwip_inet_pton 2 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d new file mode 100644 index 0000000..2c86e2e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d @@ -0,0 +1,203 @@ +Middlewares/Third_Party/LwIP/src/api/sockets.o: \ + ../Middlewares/Third_Party/LwIP/src/api/sockets.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o new file mode 100644 index 0000000..5b8b2ec Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su new file mode 100644 index 0000000..ed667b3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su @@ -0,0 +1,54 @@ +../Middlewares/Third_Party/LwIP/src/api/sockets.c:320:1:lwip_socket_thread_init 4 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:327:1:lwip_socket_thread_cleanup 4 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:411:1:tryget_socket_unconn_nouse 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:422:1:lwip_socket_dbg_get_socket 16 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:429:1:tryget_socket_unconn 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:442:1:tryget_socket_unconn_locked 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:460:1:tryget_socket 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:479:1:get_socket 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:501:1:alloc_socket 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:548:1:free_socket_locked 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:572:1:free_socket_free_elements 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:594:1:free_socket 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:620:1:lwip_accept 112 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:718:1:lwip_bind 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:772:1:lwip_close 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:813:1:lwip_connect 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:881:1:lwip_listen 40 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:920:1:lwip_recv_tcp 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1023:1:lwip_sock_make_addr 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1056:1:lwip_recv_tcp_from 40 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1088:1:lwip_recvfrom_udp_raw 64 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1199:1:lwip_recvfrom 96 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1252:1:lwip_read 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1258:1:lwip_readv 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1275:1:lwip_recv 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1281:1:lwip_recvmsg 80 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1382:1:lwip_send 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1422:1:lwip_sendmsg 120 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1585:1:lwip_sendto 64 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1685:1:lwip_socket 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1746:1:lwip_write 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1752:1:lwip_writev 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1771:1:lwip_link_select_cb 16 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1795:1:lwip_unlink_select_cb 16 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1835:1:lwip_selscan 104 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:1964:1:lwip_select 136 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2193:1:lwip_pollscan 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2319:1:lwip_poll 72 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2438:1:lwip_poll_should_wake 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2477:1:event_callback 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2576:13:select_check_waiters 40 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2655:1:lwip_shutdown 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2700:1:lwip_getaddrname 72 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2747:1:lwip_getpeername 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2753:1:lwip_getsockname 24 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2759:1:lwip_getsockopt 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2859:1:lwip_sockopt_to_ipopt 16 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:2882:1:lwip_getsockopt_impl 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3205:1:lwip_setsockopt 48 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3303:1:lwip_setsockopt_impl 40 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3743:1:lwip_ioctl 40 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3836:1:lwip_fcntl 56 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3919:1:lwip_inet_ntop 32 static +../Middlewares/Third_Party/LwIP/src/api/sockets.c:3952:1:lwip_inet_pton 32 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk new file mode 100644 index 0000000..f777deb --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/api/api_lib.c \ +../Middlewares/Third_Party/LwIP/src/api/api_msg.c \ +../Middlewares/Third_Party/LwIP/src/api/err.c \ +../Middlewares/Third_Party/LwIP/src/api/if_api.c \ +../Middlewares/Third_Party/LwIP/src/api/netbuf.c \ +../Middlewares/Third_Party/LwIP/src/api/netdb.c \ +../Middlewares/Third_Party/LwIP/src/api/netifapi.c \ +../Middlewares/Third_Party/LwIP/src/api/sockets.c \ +../Middlewares/Third_Party/LwIP/src/api/tcpip.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/api/api_lib.o \ +./Middlewares/Third_Party/LwIP/src/api/api_msg.o \ +./Middlewares/Third_Party/LwIP/src/api/err.o \ +./Middlewares/Third_Party/LwIP/src/api/if_api.o \ +./Middlewares/Third_Party/LwIP/src/api/netbuf.o \ +./Middlewares/Third_Party/LwIP/src/api/netdb.o \ +./Middlewares/Third_Party/LwIP/src/api/netifapi.o \ +./Middlewares/Third_Party/LwIP/src/api/sockets.o \ +./Middlewares/Third_Party/LwIP/src/api/tcpip.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/api/api_lib.d \ +./Middlewares/Third_Party/LwIP/src/api/api_msg.d \ +./Middlewares/Third_Party/LwIP/src/api/err.d \ +./Middlewares/Third_Party/LwIP/src/api/if_api.d \ +./Middlewares/Third_Party/LwIP/src/api/netbuf.d \ +./Middlewares/Third_Party/LwIP/src/api/netdb.d \ +./Middlewares/Third_Party/LwIP/src/api/netifapi.d \ +./Middlewares/Third_Party/LwIP/src/api/sockets.d \ +./Middlewares/Third_Party/LwIP/src/api/tcpip.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/api/%.o Middlewares/Third_Party/LwIP/src/api/%.su Middlewares/Third_Party/LwIP/src/api/%.cyclo: ../Middlewares/Third_Party/LwIP/src/api/%.c Middlewares/Third_Party/LwIP/src/api/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api: + -$(RM) ./Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo ./Middlewares/Third_Party/LwIP/src/api/api_lib.d ./Middlewares/Third_Party/LwIP/src/api/api_lib.o ./Middlewares/Third_Party/LwIP/src/api/api_lib.su ./Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo ./Middlewares/Third_Party/LwIP/src/api/api_msg.d ./Middlewares/Third_Party/LwIP/src/api/api_msg.o ./Middlewares/Third_Party/LwIP/src/api/api_msg.su ./Middlewares/Third_Party/LwIP/src/api/err.cyclo ./Middlewares/Third_Party/LwIP/src/api/err.d ./Middlewares/Third_Party/LwIP/src/api/err.o ./Middlewares/Third_Party/LwIP/src/api/err.su ./Middlewares/Third_Party/LwIP/src/api/if_api.cyclo ./Middlewares/Third_Party/LwIP/src/api/if_api.d ./Middlewares/Third_Party/LwIP/src/api/if_api.o ./Middlewares/Third_Party/LwIP/src/api/if_api.su ./Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo ./Middlewares/Third_Party/LwIP/src/api/netbuf.d ./Middlewares/Third_Party/LwIP/src/api/netbuf.o ./Middlewares/Third_Party/LwIP/src/api/netbuf.su ./Middlewares/Third_Party/LwIP/src/api/netdb.cyclo ./Middlewares/Third_Party/LwIP/src/api/netdb.d ./Middlewares/Third_Party/LwIP/src/api/netdb.o ./Middlewares/Third_Party/LwIP/src/api/netdb.su ./Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo ./Middlewares/Third_Party/LwIP/src/api/netifapi.d ./Middlewares/Third_Party/LwIP/src/api/netifapi.o ./Middlewares/Third_Party/LwIP/src/api/netifapi.su ./Middlewares/Third_Party/LwIP/src/api/sockets.cyclo ./Middlewares/Third_Party/LwIP/src/api/sockets.d ./Middlewares/Third_Party/LwIP/src/api/sockets.o ./Middlewares/Third_Party/LwIP/src/api/sockets.su ./Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo ./Middlewares/Third_Party/LwIP/src/api/tcpip.d ./Middlewares/Third_Party/LwIP/src/api/tcpip.o ./Middlewares/Third_Party/LwIP/src/api/tcpip.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo new file mode 100644 index 0000000..58c31f3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo @@ -0,0 +1,17 @@ +tcpip.c:84:1:tcpip_timeouts_mbox_fetch 4 +tcpip.c:127:1:tcpip_thread 3 +tcpip.c:156:1:tcpip_thread_handle_msg 6 +tcpip.c:240:1:tcpip_inpkt 4 +tcpip.c:283:1:tcpip_input 2 +tcpip.c:309:1:tcpip_callback 3 +tcpip.c:345:1:tcpip_try_callback 4 +tcpip.c:437:1:tcpip_send_msg_wait_sem 1 +tcpip.c:473:1:tcpip_api_call 1 +tcpip.c:531:1:tcpip_callbackmsg_new 2 +tcpip.c:552:1:tcpip_callbackmsg_delete 1 +tcpip.c:567:1:tcpip_callbackmsg_trycallback 2 +tcpip.c:586:1:tcpip_callbackmsg_trycallback_fromisr 2 +tcpip.c:602:1:tcpip_init 3 +tcpip.c:627:1:pbuf_free_int 1 +tcpip.c:640:1:pbuf_free_callback 1 +tcpip.c:653:1:mem_free_callback 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d new file mode 100644 index 0000000..255883b --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d @@ -0,0 +1,185 @@ +Middlewares/Third_Party/LwIP/src/api/tcpip.o: \ + ../Middlewares/Third_Party/LwIP/src/api/tcpip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/init.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o new file mode 100644 index 0000000..62aca7e Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su new file mode 100644 index 0000000..01701b0 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su @@ -0,0 +1,17 @@ +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:84:1:tcpip_timeouts_mbox_fetch 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:127:1:tcpip_thread 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:156:1:tcpip_thread_handle_msg 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:240:1:tcpip_inpkt 32 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:283:1:tcpip_input 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:309:1:tcpip_callback 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:345:1:tcpip_try_callback 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:437:1:tcpip_send_msg_wait_sem 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:473:1:tcpip_api_call 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:531:1:tcpip_callbackmsg_new 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:552:1:tcpip_callbackmsg_delete 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:567:1:tcpip_callbackmsg_trycallback 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:586:1:tcpip_callbackmsg_trycallback_fromisr 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:602:1:tcpip_init 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:627:1:pbuf_free_int 24 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:640:1:pbuf_free_callback 16 static +../Middlewares/Third_Party/LwIP/src/api/tcpip.c:653:1:mem_free_callback 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo new file mode 100644 index 0000000..7176eb4 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo @@ -0,0 +1,38 @@ +mqtt.c:170:1:msg_generate_packet_id 2 +mqtt.c:184:1:mqtt_ringbuf_put 2 +mqtt.c:195:1:mqtt_ringbuf_get_ptr 1 +mqtt.c:201:1:mqtt_ringbuf_advance_get_idx 3 +mqtt.c:213:1:mqtt_ringbuf_len 2 +mqtt.c:234:1:mqtt_output_send 13 +mqtt.c:287:1:mqtt_create_request 4 +mqtt.c:313:1:mqtt_append_request 5 +mqtt.c:342:1:mqtt_delete_request 2 +mqtt.c:356:1:mqtt_take_request 7 +mqtt.c:391:1:mqtt_request_time_elapsed 6 +mqtt.c:420:1:mqtt_clear_requests 3 +mqtt.c:436:1:mqtt_init_requests 3 +mqtt.c:451:1:mqtt_output_append_u8 1 +mqtt.c:457:6:mqtt_output_append_u16 1 +mqtt.c:464:1:mqtt_output_append_buf 2 +mqtt.c:473:1:mqtt_output_append_string 2 +mqtt.c:494:1:mqtt_output_append_fixed_header 3 +mqtt.c:514:1:mqtt_output_check_space 3 +mqtt.c:537:1:mqtt_close 6 +mqtt.c:576:1:mqtt_cyclic_timer 10 +mqtt.c:635:1:pub_ack_rec_rel_response 2 +mqtt.c:656:1:mqtt_incomming_suback 3 +mqtt.c:672:1:mqtt_message_received 38 +mqtt.c:839:1:mqtt_parse_incoming 14 +mqtt.c:932:1:mqtt_tcp_recv_cb 7 +mqtt.c:976:1:mqtt_tcp_sent_cb 4 +mqtt.c:1009:1:mqtt_tcp_err_cb 2 +mqtt.c:1027:1:mqtt_tcp_poll_cb 2 +mqtt.c:1044:1:mqtt_tcp_connect_cb 2 +mqtt.c:1097:1:mqtt_publish 12 +mqtt.c:1173:1:mqtt_sub_unsub 11 +mqtt.c:1238:1:mqtt_set_inpub_callback 2 +mqtt.c:1254:1:mqtt_client_new 1 +mqtt.c:1266:1:mqtt_client_free 1 +mqtt.c:1283:1:mqtt_client_connect 30 +mqtt.c:1437:1:mqtt_disconnect 3 +mqtt.c:1456:1:mqtt_client_is_connected 2 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d new file mode 100644 index 0000000..0f25292 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d @@ -0,0 +1,191 @@ +Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \ + ../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o new file mode 100644 index 0000000..e45618c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su new file mode 100644 index 0000000..ba06686 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su @@ -0,0 +1,38 @@ +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:170:1:msg_generate_packet_id 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:184:1:mqtt_ringbuf_put 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:195:1:mqtt_ringbuf_get_ptr 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:201:1:mqtt_ringbuf_advance_get_idx 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:213:1:mqtt_ringbuf_len 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:234:1:mqtt_output_send 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:287:1:mqtt_create_request 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:313:1:mqtt_append_request 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:342:1:mqtt_delete_request 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:356:1:mqtt_take_request 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:391:1:mqtt_request_time_elapsed 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:420:1:mqtt_clear_requests 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:436:1:mqtt_init_requests 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:451:1:mqtt_output_append_u8 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:457:6:mqtt_output_append_u16 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:464:1:mqtt_output_append_buf 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:473:1:mqtt_output_append_string 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:494:1:mqtt_output_append_fixed_header 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:514:1:mqtt_output_check_space 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:537:1:mqtt_close 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:576:1:mqtt_cyclic_timer 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:635:1:pub_ack_rec_rel_response 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:656:1:mqtt_incomming_suback 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:672:1:mqtt_message_received 72 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:839:1:mqtt_parse_incoming 40 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:932:1:mqtt_tcp_recv_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:976:1:mqtt_tcp_sent_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1009:1:mqtt_tcp_err_cb 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1027:1:mqtt_tcp_poll_cb 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1044:1:mqtt_tcp_connect_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1097:1:mqtt_publish 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1173:1:mqtt_sub_unsub 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1238:1:mqtt_set_inpub_callback 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1254:1:mqtt_client_new 8 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1266:1:mqtt_client_free 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1283:1:mqtt_client_connect 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1437:1:mqtt_disconnect 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1456:1:mqtt_client_is_connected 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk new file mode 100644 index 0000000..35f207a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/apps/mqtt/%.o Middlewares/Third_Party/LwIP/src/apps/mqtt/%.su Middlewares/Third_Party/LwIP/src/apps/mqtt/%.cyclo: ../Middlewares/Third_Party/LwIP/src/apps/mqtt/%.c Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt: + -$(RM) ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d new file mode 100644 index 0000000..5800a97 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/altcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o new file mode 100644 index 0000000..2f4aed5 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d new file mode 100644 index 0000000..0ff18f9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o new file mode 100644 index 0000000..6499b5c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d new file mode 100644 index 0000000..529c16a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o new file mode 100644 index 0000000..6ca849d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo new file mode 100644 index 0000000..5e7d292 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo @@ -0,0 +1,6 @@ +def.c:76:1:lwip_htons 1 +def.c:90:1:lwip_htonl 1 +def.c:105:1:lwip_strnstr 6 +def.c:128:1:lwip_stricmp 6 +def.c:163:1:lwip_strnicmp 7 +def.c:199:1:lwip_itoa 8 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.d new file mode 100644 index 0000000..ce55eeb --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/core/def.o: \ + ../Middlewares/Third_Party/LwIP/src/core/def.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.o new file mode 100644 index 0000000..a6e6b20 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.su new file mode 100644 index 0000000..ddb6a0a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/def.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/def.c:76:1:lwip_htons 16 static +../Middlewares/Third_Party/LwIP/src/core/def.c:90:1:lwip_htonl 16 static +../Middlewares/Third_Party/LwIP/src/core/def.c:105:1:lwip_strnstr 32 static +../Middlewares/Third_Party/LwIP/src/core/def.c:128:1:lwip_stricmp 24 static +../Middlewares/Third_Party/LwIP/src/core/def.c:163:1:lwip_strnicmp 32 static +../Middlewares/Third_Party/LwIP/src/core/def.c:199:1:lwip_itoa 40 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.cyclo new file mode 100644 index 0000000..7e74de6 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.cyclo @@ -0,0 +1,20 @@ +dns.c:315:1:dns_init 1 +dns.c:361:1:dns_setserver 3 +dns.c:381:1:dns_getserver 2 +dns.c:395:1:dns_tmr 1 +dns.c:602:1:dns_lookup 5 +dns.c:651:1:dns_compare_name 13 +dns.c:708:1:dns_skip_name 8 +dns.c:748:1:dns_send 8 +dns.c:866:1:dns_alloc_random_port 5 +dns.c:900:1:dns_alloc_pcb 8 +dns.c:942:1:dns_call_found 9 +dns.c:1000:1:dns_create_txid 4 +dns.c:1024:1:dns_backupserver_available 4 +dns.c:1047:1:dns_check_entry 11 +dns.c:1124:1:dns_check_entries 2 +dns.c:1137:1:dns_correct_response 4 +dns.c:1170:1:dns_recv 26 +dns.c:1375:1:dns_enqueue 17 +dns.c:1526:1:dns_gethostbyname 1 +dns.c:1547:1:dns_gethostbyname_addrtype 8 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d new file mode 100644 index 0000000..09eed58 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d @@ -0,0 +1,137 @@ +Middlewares/Third_Party/LwIP/src/core/dns.o: \ + ../Middlewares/Third_Party/LwIP/src/core/dns.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o new file mode 100644 index 0000000..24c8aaa Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.su new file mode 100644 index 0000000..4067b86 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/dns.su @@ -0,0 +1,20 @@ +../Middlewares/Third_Party/LwIP/src/core/dns.c:315:1:dns_init 4 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:361:1:dns_setserver 16 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:381:1:dns_getserver 16 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:395:1:dns_tmr 8 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:602:1:dns_lookup 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:651:1:dns_compare_name 40 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:708:1:dns_skip_name 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:748:1:dns_send 72 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:866:1:dns_alloc_random_port 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:900:1:dns_alloc_pcb 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:942:1:dns_call_found 32 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1000:1:dns_create_txid 16 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1024:1:dns_backupserver_available 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1047:1:dns_check_entry 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1124:1:dns_check_entries 16 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1137:1:dns_correct_response 24 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1170:1:dns_recv 80 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1375:1:dns_enqueue 48 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1526:1:dns_gethostbyname 32 static +../Middlewares/Third_Party/LwIP/src/core/dns.c:1547:1:dns_gethostbyname_addrtype 32 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo new file mode 100644 index 0000000..0ccd63c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo @@ -0,0 +1,9 @@ +inet_chksum.c:133:1:lwip_standard_chksum 6 +inet_chksum.c:260:1:inet_cksum_pseudo_base 4 +inet_chksum.c:310:1:inet_chksum_pseudo 1 +inet_chksum.c:379:1:ip_chksum_pseudo 1 +inet_chksum.c:399:1:inet_cksum_pseudo_partial_base 7 +inet_chksum.c:456:1:inet_chksum_pseudo_partial 1 +inet_chksum.c:526:1:ip_chksum_pseudo_partial 1 +inet_chksum.c:555:1:inet_chksum 1 +inet_chksum.c:568:1:inet_chksum_pbuf 4 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d new file mode 100644 index 0000000..757e35b --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d @@ -0,0 +1,107 @@ +Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \ + ../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o new file mode 100644 index 0000000..ad07888 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su new file mode 100644 index 0000000..f49ae34 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:133:1:lwip_standard_chksum 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:260:1:inet_cksum_pseudo_base 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:310:1:inet_chksum_pseudo 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:379:1:ip_chksum_pseudo 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:399:1:inet_cksum_pseudo_partial_base 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:456:1:inet_chksum_pseudo_partial 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:526:1:ip_chksum_pseudo_partial 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:555:1:inet_chksum 16 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:568:1:inet_chksum_pbuf 32 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo new file mode 100644 index 0000000..e3fd1ba --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo @@ -0,0 +1 @@ +init.c:332:1:lwip_init 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.d new file mode 100644 index 0000000..09d38de --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.d @@ -0,0 +1,219 @@ +Middlewares/Third_Party/LwIP/src/core/init.o: \ + ../Middlewares/Third_Party/LwIP/src/core/init.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/init.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.o new file mode 100644 index 0000000..0cd9bbb Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.su new file mode 100644 index 0000000..2da7773 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/init.su @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/core/init.c:332:1:lwip_init 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d new file mode 100644 index 0000000..e1ebda0 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d @@ -0,0 +1,129 @@ +Middlewares/Third_Party/LwIP/src/core/ip.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o new file mode 100644 index 0000000..3e4e372 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ip.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d new file mode 100644 index 0000000..5f23d36 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o new file mode 100644 index 0000000..6c368d5 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo new file mode 100644 index 0000000..539498a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo @@ -0,0 +1,37 @@ +dhcp.c:226:1:dhcp_inc_pcb_refcount 4 +dhcp.c:253:1:dhcp_dec_pcb_refcount 3 +dhcp.c:277:1:dhcp_handle_nak 1 +dhcp.c:303:1:dhcp_check 2 +dhcp.c:332:1:dhcp_handle_offer 2 +dhcp.c:366:1:dhcp_select 7 +dhcp.c:430:1:dhcp_coarse_tmr 10 +dhcp.c:468:1:dhcp_fine_tmr 5 +dhcp.c:499:1:dhcp_timeout 9 +dhcp.c:546:1:dhcp_t1_timeout 6 +dhcp.c:573:1:dhcp_t2_timeout 7 +dhcp.c:599:1:dhcp_handle_ack 8 +dhcp.c:690:1:dhcp_set_struct 4 +dhcp.c:712:6:dhcp_cleanup 3 +dhcp.c:737:1:dhcp_start 10 +dhcp.c:814:1:dhcp_inform 4 +dhcp.c:858:1:dhcp_network_changed 8 +dhcp.c:903:1:dhcp_arp_reply 5 +dhcp.c:935:1:dhcp_decline 3 +dhcp.c:981:1:dhcp_discover 5 +dhcp.c:1040:1:dhcp_bind 18 +dhcp.c:1150:1:dhcp_renew 5 +dhcp.c:1206:1:dhcp_rebind 5 +dhcp.c:1260:1:dhcp_reboot 5 +dhcp.c:1318:1:dhcp_release_and_stop 6 +dhcp.c:1394:1:dhcp_release 1 +dhcp.c:1406:1:dhcp_stop 1 +dhcp.c:1417:1:dhcp_set_state 2 +dhcp.c:1432:1:dhcp_option 2 +dhcp.c:1444:1:dhcp_option_byte 2 +dhcp.c:1452:1:dhcp_option_short 2 +dhcp.c:1461:1:dhcp_option_long 2 +dhcp.c:1507:1:dhcp_parse_reply 53 +dhcp.c:1754:1:dhcp_recv 24 +dhcp.c:1874:1:dhcp_create_msg 16 +dhcp.c:1960:1:dhcp_option_trailer 4 +dhcp.c:1980:1:dhcp_supplied_address 6 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d new file mode 100644 index 0000000..22e0c68 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d @@ -0,0 +1,151 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o new file mode 100644 index 0000000..9dd4893 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su new file mode 100644 index 0000000..88532f5 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su @@ -0,0 +1,37 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:226:1:dhcp_inc_pcb_refcount 8 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:253:1:dhcp_dec_pcb_refcount 8 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:277:1:dhcp_handle_nak 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:303:1:dhcp_check 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:332:1:dhcp_handle_offer 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:366:1:dhcp_select 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:430:1:dhcp_coarse_tmr 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:468:1:dhcp_fine_tmr 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:499:1:dhcp_timeout 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:546:1:dhcp_t1_timeout 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:573:1:dhcp_t2_timeout 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:599:1:dhcp_handle_ack 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:690:1:dhcp_set_struct 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:712:6:dhcp_cleanup 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:737:1:dhcp_start 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:814:1:dhcp_inform 88 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:858:1:dhcp_network_changed 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:903:1:dhcp_arp_reply 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:935:1:dhcp_decline 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:981:1:dhcp_discover 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1040:1:dhcp_bind 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1150:1:dhcp_renew 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1206:1:dhcp_rebind 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1260:1:dhcp_reboot 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1318:1:dhcp_release_and_stop 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1394:1:dhcp_release 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1406:1:dhcp_stop 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1417:1:dhcp_set_state 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1432:1:dhcp_option 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1444:1:dhcp_option_byte 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1452:1:dhcp_option_short 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1461:1:dhcp_option_long 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1507:1:dhcp_parse_reply 72 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1754:1:dhcp_recv 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1874:1:dhcp_create_msg 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1960:1:dhcp_option_trailer 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c:1980:1:dhcp_supplied_address 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo new file mode 100644 index 0000000..5fc1a3d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo @@ -0,0 +1,14 @@ +etharp.c:168:1:etharp_free_entry 2 +etharp.c:197:1:etharp_tmr 9 +etharp.c:256:1:etharp_find_entry 29 +etharp.c:422:1:etharp_update_arp_entry 8 +etharp.c:559:1:etharp_cleanup_netif 4 +etharp.c:583:1:etharp_find_addr 5 +etharp.c:612:1:etharp_get_entry 6 +etharp.c:641:1:etharp_input 11 +etharp.c:748:1:etharp_output_to_arp_index 7 +etharp.c:791:1:etharp_output 16 +etharp.c:933:1:etharp_query 23 +etharp.c:1101:1:etharp_raw 5 +etharp.c:1181:1:etharp_request_dst 1 +etharp.c:1198:1:etharp_request 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d new file mode 100644 index 0000000..2001c5b --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d @@ -0,0 +1,151 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o new file mode 100644 index 0000000..bf7f4aa Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su new file mode 100644 index 0000000..1528cfc --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su @@ -0,0 +1,14 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:168:1:etharp_free_entry 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:197:1:etharp_tmr 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:256:1:etharp_find_entry 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:422:1:etharp_update_arp_entry 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:559:1:etharp_cleanup_netif 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:583:1:etharp_find_addr 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:612:1:etharp_get_entry 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:641:1:etharp_input 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:748:1:etharp_output_to_arp_index 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:791:1:etharp_output 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:933:1:etharp_query 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1101:1:etharp_raw 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1181:1:etharp_request_dst 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1198:1:etharp_request 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo new file mode 100644 index 0000000..95cba53 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo @@ -0,0 +1,4 @@ +icmp.c:80:1:icmp_input 16 +icmp.c:308:1:icmp_dest_unreach 1 +icmp.c:323:1:icmp_time_exceeded 1 +icmp.c:340:1:icmp_send_response 4 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d new file mode 100644 index 0000000..753f278 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d @@ -0,0 +1,135 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o new file mode 100644 index 0000000..4c3a4b1 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su new file mode 100644 index 0000000..ff5baf3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su @@ -0,0 +1,4 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:80:1:icmp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:308:1:icmp_dest_unreach 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:323:1:icmp_time_exceeded 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:340:1:icmp_send_response 56 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d new file mode 100644 index 0000000..8d3107b --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o new file mode 100644 index 0000000..5ea4879 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo new file mode 100644 index 0000000..2c46d85 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo @@ -0,0 +1,6 @@ +ip4.c:152:1:ip4_route 13 +ip4.c:374:1:ip4_input_accept 5 +ip4.c:426:1:ip4_input 30 +ip4.c:787:1:ip4_output_if 4 +ip4.c:827:1:ip4_output_if_src 9 +ip4.c:1028:1:ip4_output 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d new file mode 100644 index 0000000..7295204 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d @@ -0,0 +1,157 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o new file mode 100644 index 0000000..4db5dd2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su new file mode 100644 index 0000000..606042c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:152:1:ip4_route 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:374:1:ip4_input_accept 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:426:1:ip4_input 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:787:1:ip4_output_if 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:827:1:ip4_output_if_src 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:1028:1:ip4_output 48 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo new file mode 100644 index 0000000..fa20a6d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo @@ -0,0 +1,6 @@ +ip4_addr.c:58:1:ip4_addr_isbroadcast_u32 7 +ip4_addr.c:93:1:ip4_addr_netmask_valid 5 +ip4_addr.c:123:1:ipaddr_addr 2 +ip4_addr.c:145:1:ip4addr_aton 28 +ip4_addr.c:267:1:ip4addr_ntoa 1 +ip4_addr.c:283:1:ip4addr_ntoa_r 6 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d new file mode 100644 index 0000000..e864f28 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d @@ -0,0 +1,119 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o new file mode 100644 index 0000000..99f5347 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su new file mode 100644 index 0000000..c8832bb --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:58:1:ip4_addr_isbroadcast_u32 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:93:1:ip4_addr_netmask_valid 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:123:1:ipaddr_addr 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:145:1:ip4addr_aton 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:267:1:ip4addr_ntoa 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:283:1:ip4addr_ntoa_r 56 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo new file mode 100644 index 0000000..8e5e681 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo @@ -0,0 +1,11 @@ +ip4_frag.c:128:1:ip_reass_tmr 3 +ip4_frag.c:164:1:ip_reass_free_complete_datagram 9 +ip4_frag.c:227:1:ip_reass_remove_oldest_datagram 11 +ip4_frag.c:278:1:ip_reass_enqueue_new_datagram 4 +ip4_frag.c:317:1:ip_reass_dequeue_datagram 3 +ip4_frag.c:344:1:ip_reass_chain_frag_into_datagram_and_validate 30 +ip4_frag.c:503:1:ip4_reass 28 +ip4_frag.c:699:1:ip_frag_alloc_pbuf_custom_ref 1 +ip4_frag.c:706:1:ip_frag_free_pbuf_custom_ref 2 +ip4_frag.c:715:1:ipfrag_free_pbuf_custom 4 +ip4_frag.c:740:1:ip4_frag 15 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d new file mode 100644 index 0000000..3c87e4e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d @@ -0,0 +1,137 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o new file mode 100644 index 0000000..78d397e Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su new file mode 100644 index 0000000..e7ecbae --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:128:1:ip_reass_tmr 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:164:1:ip_reass_free_complete_datagram 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:227:1:ip_reass_remove_oldest_datagram 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:278:1:ip_reass_enqueue_new_datagram 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:317:1:ip_reass_dequeue_datagram 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:344:1:ip_reass_chain_frag_into_datagram_and_validate 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:503:1:ip4_reass 64 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:699:1:ip_frag_alloc_pbuf_custom_ref 8 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:706:1:ip_frag_free_pbuf_custom_ref 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:715:1:ipfrag_free_pbuf_custom 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:740:1:ip4_frag 88 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk new file mode 100644 index 0000000..cfc9276 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/ipv4/%.o Middlewares/Third_Party/LwIP/src/core/ipv4/%.su Middlewares/Third_Party/LwIP/src/core/ipv4/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv4/%.c Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4 + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4 + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d new file mode 100644 index 0000000..ddcfef5 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o new file mode 100644 index 0000000..277f1ff Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d new file mode 100644 index 0000000..f7cfb56 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o new file mode 100644 index 0000000..fa5899d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d new file mode 100644 index 0000000..d972660 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o new file mode 100644 index 0000000..16e657b Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d new file mode 100644 index 0000000..82083dc --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o new file mode 100644 index 0000000..b0af365 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d new file mode 100644 index 0000000..39cbead --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o new file mode 100644 index 0000000..44dafa5 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d new file mode 100644 index 0000000..3caf305 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o new file mode 100644 index 0000000..31ffe5c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d new file mode 100644 index 0000000..3a61d8a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d @@ -0,0 +1,137 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o new file mode 100644 index 0000000..355ac25 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d new file mode 100644 index 0000000..91cb2dd --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o new file mode 100644 index 0000000..ef0bf77 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d new file mode 100644 index 0000000..1f9d7bc --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o new file mode 100644 index 0000000..f80727d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk new file mode 100644 index 0000000..a90edda --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/ipv6/%.o Middlewares/Third_Party/LwIP/src/core/ipv6/%.su Middlewares/Third_Party/LwIP/src/core/ipv6/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv6/%.c Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6 + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6 + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo new file mode 100644 index 0000000..ceb964f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo @@ -0,0 +1,9 @@ +mem.c:451:1:ptr_to_mem 1 +mem.c:457:1:mem_to_ptr 1 +mem.c:474:1:plug_holes 14 +mem.c:516:1:mem_init 2 +mem.c:551:1:mem_link_valid 7 +mem.c:617:1:mem_free 8 +mem.c:699:1:mem_trim 19 +mem.c:831:1:mem_malloc 19 +mem.c:999:1:mem_calloc 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d new file mode 100644 index 0000000..b2f7ea7 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d @@ -0,0 +1,145 @@ +Middlewares/Third_Party/LwIP/src/core/mem.o: \ + ../Middlewares/Third_Party/LwIP/src/core/mem.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o new file mode 100644 index 0000000..dbbcde4 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su new file mode 100644 index 0000000..cf61ec5 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/mem.c:451:1:ptr_to_mem 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:457:1:mem_to_ptr 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:474:1:plug_holes 32 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:551:1:mem_link_valid 32 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free 40 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:699:1:mem_trim 40 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:831:1:mem_malloc 40 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:999:1:mem_calloc 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo new file mode 100644 index 0000000..3f8883c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo @@ -0,0 +1,8 @@ +memp.c:175:1:memp_init_pool 2 +memp.c:224:1:memp_init 2 +memp.c:245:1:do_memp_malloc_pool 3 +memp.c:311:1:memp_malloc_pool 3 +memp.c:337:1:memp_malloc 2 +memp.c:359:1:do_memp_free_pool 2 +memp.c:403:1:memp_free_pool 4 +memp.c:420:1:memp_free 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d new file mode 100644 index 0000000..f719615 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d @@ -0,0 +1,231 @@ +Middlewares/Third_Party/LwIP/src/core/memp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/memp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o new file mode 100644 index 0000000..f0a5f78 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su new file mode 100644 index 0000000..822791f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su @@ -0,0 +1,8 @@ +../Middlewares/Third_Party/LwIP/src/core/memp.c:175:1:memp_init_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:224:1:memp_init 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:245:1:do_memp_malloc_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:311:1:memp_malloc_pool 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:337:1:memp_malloc 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:359:1:do_memp_free_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:403:1:memp_free_pool 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:420:1:memp_free 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo new file mode 100644 index 0000000..bdc74a6 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo @@ -0,0 +1,25 @@ +netif.c:177:1:netif_init 1 +netif.c:217:1:netif_input 4 +netif.c:239:1:netif_add_noaddr 1 +netif.c:276:1:netif_add 14 +netif.c:442:1:netif_do_ip_addr_changed 1 +netif.c:457:1:netif_do_set_ipaddr 5 +netif.c:500:1:netif_set_ipaddr 3 +netif.c:523:1:netif_do_set_netmask 3 +netif.c:560:1:netif_set_netmask 3 +netif.c:587:1:netif_do_set_gw 3 +netif.c:621:1:netif_set_gw 3 +netif.c:658:1:netif_set_addr 8 +netif.c:737:1:netif_remove 8 +netif.c:822:1:netif_set_default 1 +netif.c:844:1:netif_set_up 3 +netif.c:875:1:netif_issue_reports 7 +netif.c:919:1:netif_set_down 4 +netif.c:988:1:netif_set_link_up 4 +netif.c:1026:1:netif_set_link_down 4 +netif.c:1051:1:netif_set_link_callback 2 +netif.c:1619:1:netif_null_output_ip4 1 +netif.c:1637:1:netif_name_to_index 2 +netif.c:1656:1:netif_index_to_name 2 +netif.c:1676:1:netif_get_by_index 4 +netif.c:1701:1:netif_find 6 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d new file mode 100644 index 0000000..3de9e44 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d @@ -0,0 +1,201 @@ +Middlewares/Third_Party/LwIP/src/core/netif.o: \ + ../Middlewares/Third_Party/LwIP/src/core/netif.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o new file mode 100644 index 0000000..57c1d60 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su new file mode 100644 index 0000000..6558e89 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su @@ -0,0 +1,25 @@ +../Middlewares/Third_Party/LwIP/src/core/netif.c:177:1:netif_init 4 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:217:1:netif_input 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:239:1:netif_add_noaddr 40 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:276:1:netif_add 32 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:442:1:netif_do_ip_addr_changed 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:457:1:netif_do_set_ipaddr 32 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:500:1:netif_set_ipaddr 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:523:1:netif_do_set_netmask 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:560:1:netif_set_netmask 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:587:1:netif_do_set_gw 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:621:1:netif_set_gw 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:658:1:netif_set_addr 40 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:737:1:netif_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:822:1:netif_set_default 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:844:1:netif_set_up 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:875:1:netif_issue_reports 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:919:1:netif_set_down 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:988:1:netif_set_link_up 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1026:1:netif_set_link_down 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1051:1:netif_set_link_callback 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1619:1:netif_null_output_ip4 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1637:1:netif_name_to_index 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1656:1:netif_index_to_name 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1676:1:netif_get_by_index 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1701:1:netif_find 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo new file mode 100644 index 0000000..4443a1d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo @@ -0,0 +1,37 @@ +pbuf.c:128:1:pbuf_free_ooseq 3 +pbuf.c:148:1:pbuf_free_ooseq_callback 1 +pbuf.c:157:1:pbuf_pool_is_empty 3 +pbuf.c:179:1:pbuf_init_alloced_pbuf 1 +pbuf.c:224:1:pbuf_alloc 17 +pbuf.c:327:1:pbuf_alloc_reference 4 +pbuf.c:363:1:pbuf_alloced_custom 3 +pbuf.c:402:1:pbuf_realloc 10 +pbuf.c:473:1:pbuf_add_header_impl 9 +pbuf.c:551:1:pbuf_add_header 1 +pbuf.c:561:1:pbuf_add_header_force 1 +pbuf.c:582:1:pbuf_remove_header 6 +pbuf.c:616:1:pbuf_header_impl 2 +pbuf.c:646:1:pbuf_header 1 +pbuf.c:656:1:pbuf_header_force 1 +pbuf.c:671:1:pbuf_free_header 4 +pbuf.c:725:1:pbuf_free 11 +pbuf.c:809:1:pbuf_clen 2 +pbuf.c:829:1:pbuf_ref 3 +pbuf.c:853:1:pbuf_cat 6 +pbuf.c:895:1:pbuf_chain 1 +pbuf.c:912:1:pbuf_dechain 5 +pbuf.c:961:1:pbuf_copy 18 +pbuf.c:1027:1:pbuf_copy_partial 8 +pbuf.c:1074:1:pbuf_get_contiguous 7 +pbuf.c:1152:1:pbuf_skip_const 4 +pbuf.c:1178:1:pbuf_skip 1 +pbuf.c:1196:1:pbuf_take 12 +pbuf.c:1240:1:pbuf_take_at 6 +pbuf.c:1278:1:pbuf_coalesce 3 +pbuf.c:1306:1:pbuf_clone 3 +pbuf.c:1371:1:pbuf_get_at 2 +pbuf.c:1389:1:pbuf_try_get_at 3 +pbuf.c:1411:1:pbuf_put_at 3 +pbuf.c:1434:1:pbuf_memcmp 6 +pbuf.c:1476:1:pbuf_memfind 4 +pbuf.c:1503:1:pbuf_strstr 5 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d new file mode 100644 index 0000000..71d6686 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d @@ -0,0 +1,183 @@ +Middlewares/Third_Party/LwIP/src/core/pbuf.o: \ + ../Middlewares/Third_Party/LwIP/src/core/pbuf.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o new file mode 100644 index 0000000..02a642c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su new file mode 100644 index 0000000..c1cc3a5 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su @@ -0,0 +1,37 @@ +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:128:1:pbuf_free_ooseq 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:148:1:pbuf_free_ooseq_callback 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:179:1:pbuf_init_alloced_pbuf 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:224:1:pbuf_alloc 56 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:327:1:pbuf_alloc_reference 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:363:1:pbuf_alloced_custom 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:402:1:pbuf_realloc 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:473:1:pbuf_add_header_impl 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:551:1:pbuf_add_header 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:561:1:pbuf_add_header_force 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:582:1:pbuf_remove_header 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:616:1:pbuf_header_impl 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:646:1:pbuf_header 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:656:1:pbuf_header_force 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:671:1:pbuf_free_header 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:725:1:pbuf_free 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:809:1:pbuf_clen 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:829:1:pbuf_ref 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:853:1:pbuf_cat 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:895:1:pbuf_chain 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:912:1:pbuf_dechain 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:961:1:pbuf_copy 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1027:1:pbuf_copy_partial 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1074:1:pbuf_get_contiguous 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1152:1:pbuf_skip_const 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1178:1:pbuf_skip 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1196:1:pbuf_take 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1240:1:pbuf_take_at 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1278:1:pbuf_coalesce 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1306:1:pbuf_clone 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1371:1:pbuf_get_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1389:1:pbuf_try_get_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1411:1:pbuf_put_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1434:1:pbuf_memcmp 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1476:1:pbuf_memfind 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1503:1:pbuf_strstr 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d new file mode 100644 index 0000000..61a375e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/raw.o: \ + ../Middlewares/Third_Party/LwIP/src/core/raw.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o new file mode 100644 index 0000000..2469692 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/raw.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d new file mode 100644 index 0000000..7fb9ec2 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/stats.o: \ + ../Middlewares/Third_Party/LwIP/src/core/stats.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o new file mode 100644 index 0000000..2865940 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/stats.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk new file mode 100644 index 0000000..05ff73d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk @@ -0,0 +1,84 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/altcp.c \ +../Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c \ +../Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c \ +../Middlewares/Third_Party/LwIP/src/core/def.c \ +../Middlewares/Third_Party/LwIP/src/core/dns.c \ +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c \ +../Middlewares/Third_Party/LwIP/src/core/init.c \ +../Middlewares/Third_Party/LwIP/src/core/ip.c \ +../Middlewares/Third_Party/LwIP/src/core/mem.c \ +../Middlewares/Third_Party/LwIP/src/core/memp.c \ +../Middlewares/Third_Party/LwIP/src/core/netif.c \ +../Middlewares/Third_Party/LwIP/src/core/pbuf.c \ +../Middlewares/Third_Party/LwIP/src/core/raw.c \ +../Middlewares/Third_Party/LwIP/src/core/stats.c \ +../Middlewares/Third_Party/LwIP/src/core/sys.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c \ +../Middlewares/Third_Party/LwIP/src/core/timeouts.c \ +../Middlewares/Third_Party/LwIP/src/core/udp.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/altcp.o \ +./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o \ +./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o \ +./Middlewares/Third_Party/LwIP/src/core/def.o \ +./Middlewares/Third_Party/LwIP/src/core/dns.o \ +./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o \ +./Middlewares/Third_Party/LwIP/src/core/init.o \ +./Middlewares/Third_Party/LwIP/src/core/ip.o \ +./Middlewares/Third_Party/LwIP/src/core/mem.o \ +./Middlewares/Third_Party/LwIP/src/core/memp.o \ +./Middlewares/Third_Party/LwIP/src/core/netif.o \ +./Middlewares/Third_Party/LwIP/src/core/pbuf.o \ +./Middlewares/Third_Party/LwIP/src/core/raw.o \ +./Middlewares/Third_Party/LwIP/src/core/stats.o \ +./Middlewares/Third_Party/LwIP/src/core/sys.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp_in.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp_out.o \ +./Middlewares/Third_Party/LwIP/src/core/timeouts.o \ +./Middlewares/Third_Party/LwIP/src/core/udp.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/altcp.d \ +./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d \ +./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d \ +./Middlewares/Third_Party/LwIP/src/core/def.d \ +./Middlewares/Third_Party/LwIP/src/core/dns.d \ +./Middlewares/Third_Party/LwIP/src/core/inet_chksum.d \ +./Middlewares/Third_Party/LwIP/src/core/init.d \ +./Middlewares/Third_Party/LwIP/src/core/ip.d \ +./Middlewares/Third_Party/LwIP/src/core/mem.d \ +./Middlewares/Third_Party/LwIP/src/core/memp.d \ +./Middlewares/Third_Party/LwIP/src/core/netif.d \ +./Middlewares/Third_Party/LwIP/src/core/pbuf.d \ +./Middlewares/Third_Party/LwIP/src/core/raw.d \ +./Middlewares/Third_Party/LwIP/src/core/stats.d \ +./Middlewares/Third_Party/LwIP/src/core/sys.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp_in.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp_out.d \ +./Middlewares/Third_Party/LwIP/src/core/timeouts.d \ +./Middlewares/Third_Party/LwIP/src/core/udp.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/%.o Middlewares/Third_Party/LwIP/src/core/%.su Middlewares/Third_Party/LwIP/src/core/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/%.c Middlewares/Third_Party/LwIP/src/core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/altcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp.d ./Middlewares/Third_Party/LwIP/src/core/altcp.o ./Middlewares/Third_Party/LwIP/src/core/altcp.su ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su ./Middlewares/Third_Party/LwIP/src/core/def.cyclo ./Middlewares/Third_Party/LwIP/src/core/def.d ./Middlewares/Third_Party/LwIP/src/core/def.o ./Middlewares/Third_Party/LwIP/src/core/def.su ./Middlewares/Third_Party/LwIP/src/core/dns.cyclo ./Middlewares/Third_Party/LwIP/src/core/dns.d ./Middlewares/Third_Party/LwIP/src/core/dns.o ./Middlewares/Third_Party/LwIP/src/core/dns.su ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.d ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.su ./Middlewares/Third_Party/LwIP/src/core/init.cyclo ./Middlewares/Third_Party/LwIP/src/core/init.d ./Middlewares/Third_Party/LwIP/src/core/init.o ./Middlewares/Third_Party/LwIP/src/core/init.su ./Middlewares/Third_Party/LwIP/src/core/ip.cyclo ./Middlewares/Third_Party/LwIP/src/core/ip.d ./Middlewares/Third_Party/LwIP/src/core/ip.o ./Middlewares/Third_Party/LwIP/src/core/ip.su ./Middlewares/Third_Party/LwIP/src/core/mem.cyclo ./Middlewares/Third_Party/LwIP/src/core/mem.d ./Middlewares/Third_Party/LwIP/src/core/mem.o ./Middlewares/Third_Party/LwIP/src/core/mem.su ./Middlewares/Third_Party/LwIP/src/core/memp.cyclo ./Middlewares/Third_Party/LwIP/src/core/memp.d ./Middlewares/Third_Party/LwIP/src/core/memp.o ./Middlewares/Third_Party/LwIP/src/core/memp.su ./Middlewares/Third_Party/LwIP/src/core/netif.cyclo ./Middlewares/Third_Party/LwIP/src/core/netif.d ./Middlewares/Third_Party/LwIP/src/core/netif.o ./Middlewares/Third_Party/LwIP/src/core/netif.su ./Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo ./Middlewares/Third_Party/LwIP/src/core/pbuf.d ./Middlewares/Third_Party/LwIP/src/core/pbuf.o ./Middlewares/Third_Party/LwIP/src/core/pbuf.su ./Middlewares/Third_Party/LwIP/src/core/raw.cyclo ./Middlewares/Third_Party/LwIP/src/core/raw.d ./Middlewares/Third_Party/LwIP/src/core/raw.o ./Middlewares/Third_Party/LwIP/src/core/raw.su ./Middlewares/Third_Party/LwIP/src/core/stats.cyclo ./Middlewares/Third_Party/LwIP/src/core/stats.d ./Middlewares/Third_Party/LwIP/src/core/stats.o ./Middlewares/Third_Party/LwIP/src/core/stats.su ./Middlewares/Third_Party/LwIP/src/core/sys.cyclo ./Middlewares/Third_Party/LwIP/src/core/sys.d ./Middlewares/Third_Party/LwIP/src/core/sys.o ./Middlewares/Third_Party/LwIP/src/core/sys.su ./Middlewares/Third_Party/LwIP/src/core/tcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp.d ./Middlewares/Third_Party/LwIP/src/core/tcp.o ./Middlewares/Third_Party/LwIP/src/core/tcp.su ./Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp_in.d ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o ./Middlewares/Third_Party/LwIP/src/core/tcp_in.su ./Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp_out.d ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o ./Middlewares/Third_Party/LwIP/src/core/tcp_out.su ./Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo ./Middlewares/Third_Party/LwIP/src/core/timeouts.d ./Middlewares/Third_Party/LwIP/src/core/timeouts.o ./Middlewares/Third_Party/LwIP/src/core/timeouts.su ./Middlewares/Third_Party/LwIP/src/core/udp.cyclo ./Middlewares/Third_Party/LwIP/src/core/udp.d ./Middlewares/Third_Party/LwIP/src/core/udp.o ./Middlewares/Third_Party/LwIP/src/core/udp.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo new file mode 100644 index 0000000..be10ace --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo @@ -0,0 +1 @@ +sys.c:135:1:sys_msleep 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d new file mode 100644 index 0000000..fc3da0d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d @@ -0,0 +1,131 @@ +Middlewares/Third_Party/LwIP/src/core/sys.o: \ + ../Middlewares/Third_Party/LwIP/src/core/sys.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o new file mode 100644 index 0000000..19082cd Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su new file mode 100644 index 0000000..d5daec3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/core/sys.c:135:1:sys_msleep 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo new file mode 100644 index 0000000..602e4be --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo @@ -0,0 +1,52 @@ +tcp.c:201:1:tcp_init 1 +tcp.c:210:1:tcp_free 2 +tcp.c:221:1:tcp_free_listen 2 +tcp.c:234:1:tcp_tmr 2 +tcp.c:251:1:tcp_remove_listener 4 +tcp.c:269:1:tcp_listen_closed 4 +tcp.c:348:1:tcp_close_shutdown 20 +tcp.c:409:1:tcp_close_shutdown_fin 11 +tcp.c:484:1:tcp_close 3 +tcp.c:515:1:tcp_shutdown 10 +tcp.c:563:1:tcp_abandon 14 +tcp.c:638:1:tcp_abort 1 +tcp.c:661:1:tcp_bind 17 +tcp.c:763:1:tcp_bind_netif 2 +tcp.c:778:1:tcp_accept_null 2 +tcp.c:825:1:tcp_listen_with_backlog 1 +tcp.c:848:1:tcp_listen_with_backlog_and_err 10 +tcp.c:930:1:tcp_update_rcv_ann_wnd 5 +tcp.c:968:1:tcp_recved 6 +tcp.c:1011:1:tcp_new_port 6 +tcp.c:1067:1:tcp_connect 18 +tcp.c:1192:1:tcp_slowtmr 63 +tcp.c:1479:1:tcp_fasttmr 7 +tcp.c:1526:1:tcp_txnow 3 +tcp.c:1539:1:tcp_process_refused_data 9 +tcp.c:1608:1:tcp_segs_free 2 +tcp.c:1623:1:tcp_seg_free 3 +tcp.c:1644:1:tcp_setprio 2 +tcp.c:1662:1:tcp_seg_copy 3 +tcp.c:1684:1:tcp_recv_null 4 +tcp.c:1706:1:tcp_kill_prio 8 +tcp.c:1752:1:tcp_kill_state 7 +tcp.c:1784:1:tcp_kill_timewait 4 +tcp.c:1811:1:tcp_handle_closepend 3 +tcp.c:1834:1:tcp_alloc 6 +tcp.c:1945:1:tcp_new 1 +tcp.c:1962:1:tcp_new_ip_type 1 +tcp.c:1988:1:tcp_arg 2 +tcp.c:2011:1:tcp_recv 3 +tcp.c:2031:1:tcp_sent 3 +tcp.c:2057:1:tcp_err 3 +tcp.c:2076:1:tcp_accept 3 +tcp.c:2105:1:tcp_poll 3 +tcp.c:2127:1:tcp_pcb_purge 7 +tcp.c:2177:1:tcp_pcb_remove 13 +tcp.c:2215:1:tcp_next_iss 2 +tcp.c:2238:1:tcp_eff_send_mss_netif 5 +tcp.c:2299:1:tcp_netif_ip_addr_changed_pcblist 4 +tcp.c:2331:1:tcp_netif_ip_addr_changed 7 +tcp.c:2354:1:tcp_debug_state_str 1 +tcp.c:2360:1:tcp_tcp_get_tcp_addrinfo 7 +tcp.c:2386:1:tcp_free_ooseq 2 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d new file mode 100644 index 0000000..9e8cfb9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d @@ -0,0 +1,143 @@ +Middlewares/Third_Party/LwIP/src/core/tcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o new file mode 100644 index 0000000..a567a18 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su new file mode 100644 index 0000000..17c1295 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su @@ -0,0 +1,52 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp.c:201:1:tcp_init 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:210:1:tcp_free 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:221:1:tcp_free_listen 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:234:1:tcp_tmr 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:251:1:tcp_remove_listener 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:269:1:tcp_listen_closed 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:348:1:tcp_close_shutdown 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:409:1:tcp_close_shutdown_fin 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:484:1:tcp_close 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:515:1:tcp_shutdown 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:563:1:tcp_abandon 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:638:1:tcp_abort 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:661:1:tcp_bind 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:763:1:tcp_bind_netif 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:778:1:tcp_accept_null 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:825:1:tcp_listen_with_backlog 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:848:1:tcp_listen_with_backlog_and_err 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:930:1:tcp_update_rcv_ann_wnd 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:968:1:tcp_recved 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1011:1:tcp_new_port 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1067:1:tcp_connect 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1192:1:tcp_slowtmr 80 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1479:1:tcp_fasttmr 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1526:1:tcp_txnow 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1539:1:tcp_process_refused_data 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1608:1:tcp_segs_free 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1623:1:tcp_seg_free 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1644:1:tcp_setprio 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1662:1:tcp_seg_copy 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1684:1:tcp_recv_null 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1706:1:tcp_kill_prio 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1752:1:tcp_kill_state 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1784:1:tcp_kill_timewait 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1811:1:tcp_handle_closepend 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1834:1:tcp_alloc 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1945:1:tcp_new 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1962:1:tcp_new_ip_type 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1988:1:tcp_arg 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2011:1:tcp_recv 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2031:1:tcp_sent 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2057:1:tcp_err 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2076:1:tcp_accept 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2105:1:tcp_poll 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2127:1:tcp_pcb_purge 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2177:1:tcp_pcb_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2215:1:tcp_next_iss 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2238:1:tcp_eff_send_mss_netif 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2299:1:tcp_netif_ip_addr_changed_pcblist 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2331:1:tcp_netif_ip_addr_changed 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2354:1:tcp_debug_state_str 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2360:1:tcp_tcp_get_tcp_addrinfo 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2386:1:tcp_free_ooseq 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo new file mode 100644 index 0000000..8596770 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo @@ -0,0 +1,11 @@ +tcp_in.c:118:1:tcp_input 73 +tcp_in.c:600:1:tcp_input_delayed_close 5 +tcp_in.c:630:1:tcp_listen_input 8 +tcp_in.c:739:1:tcp_timewait_input 8 +tcp_in.c:788:1:tcp_process 72 +tcp_in.c:1051:1:tcp_oos_insert_segment 8 +tcp_in.c:1088:1:tcp_free_acked_segments 8 +tcp_in.c:1141:1:tcp_receive 109 +tcp_in.c:1888:1:tcp_get_next_optbyte 3 +tcp_in.c:1909:1:tcp_parseopt 13 +tcp_in.c:2029:1:tcp_trigger_input_pcb_close 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d new file mode 100644 index 0000000..bba99ed --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d @@ -0,0 +1,145 @@ +Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp_in.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o new file mode 100644 index 0000000..f9ac169 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su new file mode 100644 index 0000000..0578f9e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:118:1:tcp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:600:1:tcp_input_delayed_close 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:630:1:tcp_listen_input 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:739:1:tcp_timewait_input 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:788:1:tcp_process 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1051:1:tcp_oos_insert_segment 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1088:1:tcp_free_acked_segments 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1141:1:tcp_receive 96 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1888:1:tcp_get_next_optbyte 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1909:1:tcp_parseopt 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:2029:1:tcp_trigger_input_pcb_close 4 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo new file mode 100644 index 0000000..fa93be3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo @@ -0,0 +1,24 @@ +tcp_out.c:132:1:tcp_route 3 +tcp_out.c:158:1:tcp_create_segment 6 +tcp_out.c:225:1:tcp_pbuf_prealloc 11 +tcp_out.c:305:1:tcp_write_checks 14 +tcp_out.c:390:1:tcp_write 55 +tcp_out.c:827:1:tcp_split_unsent_seg 15 +tcp_out.c:1001:1:tcp_send_fin 5 +tcp_out.c:1032:1:tcp_enqueue_flags 17 +tcp_out.c:1237:1:tcp_output 42 +tcp_out.c:1432:1:tcp_output_segment_busy 3 +tcp_out.c:1455:1:tcp_output_segment 9 +tcp_out.c:1631:1:tcp_rexmit_rto_prepare 7 +tcp_out.c:1686:1:tcp_rexmit_rto_commit 3 +tcp_out.c:1707:1:tcp_rexmit_rto 3 +tcp_out.c:1724:1:tcp_rexmit 8 +tcp_out.c:1783:1:tcp_rexmit_fast 7 +tcp_out.c:1818:1:tcp_output_alloc_header_common 3 +tcp_out.c:1853:1:tcp_output_alloc_header 3 +tcp_out.c:1872:1:tcp_output_fill_options 3 +tcp_out.c:1921:1:tcp_output_control_segment 4 +tcp_out.c:1980:1:tcp_rst 4 +tcp_out.c:2019:1:tcp_send_empty_ack 4 +tcp_out.c:2078:1:tcp_keepalive 3 +tcp_out.c:2116:1:tcp_zero_window_probe 9 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d new file mode 100644 index 0000000..3b2f8a4 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d @@ -0,0 +1,143 @@ +Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp_out.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o new file mode 100644 index 0000000..cc842a0 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su new file mode 100644 index 0000000..4b15556 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su @@ -0,0 +1,24 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:132:1:tcp_route 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:158:1:tcp_create_segment 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:225:1:tcp_pbuf_prealloc 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:305:1:tcp_write_checks 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:390:1:tcp_write 120 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:827:1:tcp_split_unsent_seg 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1001:1:tcp_send_fin 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1032:1:tcp_enqueue_flags 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1237:1:tcp_output 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1432:1:tcp_output_segment_busy 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1455:1:tcp_output_segment 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1631:1:tcp_rexmit_rto_prepare 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1686:1:tcp_rexmit_rto_commit 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1707:1:tcp_rexmit_rto 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1724:1:tcp_rexmit 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1783:1:tcp_rexmit_fast 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1818:1:tcp_output_alloc_header_common 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1853:1:tcp_output_alloc_header 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1872:1:tcp_output_fill_options 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1921:1:tcp_output_control_segment 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1980:1:tcp_rst 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2019:1:tcp_send_empty_ack 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2078:1:tcp_keepalive 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2116:1:tcp_zero_window_probe 56 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo new file mode 100644 index 0000000..a81df8d --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo @@ -0,0 +1,10 @@ +timeouts.c:144:1:tcpip_tcp_timer 3 +timeouts.c:166:1:tcp_timer_needed 4 +timeouts.c:183:1:sys_timeout_abs 8 +timeouts.c:232:1:lwip_cyclic_timer 2 +timeouts.c:264:6:sys_timeouts_init 2 +timeouts.c:290:1:sys_timeout 2 +timeouts.c:317:1:sys_untimeout 6 +timeouts.c:352:1:sys_check_timeouts 4 +timeouts.c:404:1:sys_restart_timeouts 3 +timeouts.c:426:1:sys_timeouts_sleeptime 4 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d new file mode 100644 index 0000000..16707a2 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d @@ -0,0 +1,215 @@ +Middlewares/Third_Party/LwIP/src/core/timeouts.o: \ + ../Middlewares/Third_Party/LwIP/src/core/timeouts.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o new file mode 100644 index 0000000..01586c9 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su new file mode 100644 index 0000000..89b582f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su @@ -0,0 +1,10 @@ +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:144:1:tcpip_tcp_timer 16 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:166:1:tcp_timer_needed 8 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:183:1:sys_timeout_abs 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:232:1:lwip_cyclic_timer 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:264:6:sys_timeouts_init 16 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:290:1:sys_timeout 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:317:1:sys_untimeout 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:352:1:sys_check_timeouts 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:404:1:sys_restart_timeouts 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:426:1:sys_timeouts_sleeptime 16 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo new file mode 100644 index 0000000..26495b8 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo @@ -0,0 +1,17 @@ +udp.c:87:1:udp_init 1 +udp.c:100:1:udp_new_port 5 +udp.c:130:1:udp_input_local_match 13 +udp.c:194:1:udp_input 25 +udp.c:467:1:udp_send 3 +udp.c:520:1:udp_sendto 6 +udp.c:624:1:udp_sendto_if 9 +udp.c:699:1:udp_sendto_if_src 14 +udp.c:932:1:udp_bind 17 +udp.c:1042:1:udp_bind_netif 2 +udp.c:1071:1:udp_connect 8 +udp.c:1126:1:udp_disconnect 2 +udp.c:1158:1:udp_recv 2 +udp.c:1179:1:udp_remove 6 +udp.c:1218:1:udp_new 2 +udp.c:1255:1:udp_new_ip_type 1 +udp.c:1278:6:udp_netif_ip_addr_changed 7 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d new file mode 100644 index 0000000..48757b4 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d @@ -0,0 +1,147 @@ +Middlewares/Third_Party/LwIP/src/core/udp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/udp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o new file mode 100644 index 0000000..422e31a Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su new file mode 100644 index 0000000..3865a30 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su @@ -0,0 +1,17 @@ +../Middlewares/Third_Party/LwIP/src/core/udp.c:87:1:udp_init 8 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:100:1:udp_new_port 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:130:1:udp_input_local_match 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:194:1:udp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:467:1:udp_send 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:520:1:udp_sendto 40 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:624:1:udp_sendto_if 40 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:699:1:udp_sendto_if_src 56 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:932:1:udp_bind 32 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1042:1:udp_bind_netif 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1071:1:udp_connect 32 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1126:1:udp_disconnect 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1158:1:udp_recv 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1179:1:udp_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1218:1:udp_new 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1255:1:udp_new_ip_type 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1278:6:udp_netif_ip_addr_changed 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d new file mode 100644 index 0000000..46ed056 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d @@ -0,0 +1,181 @@ +Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/bridgeif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h: +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o new file mode 100644 index 0000000..38c64ae Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo new file mode 100644 index 0000000..d890aea --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo @@ -0,0 +1,5 @@ +bridgeif_fdb.c:76:1:bridgeif_fdb_update_src 10 +bridgeif_fdb.c:128:1:bridgeif_fdb_get_dst_ports 5 +bridgeif_fdb.c:153:1:bridgeif_fdb_age_one_second 7 +bridgeif_fdb.c:180:1:bridgeif_age_tmr 2 +bridgeif_fdb.c:195:1:bridgeif_fdb_init 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d new file mode 100644 index 0000000..691ea38 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d @@ -0,0 +1,169 @@ +Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h: +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o new file mode 100644 index 0000000..991335a Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su new file mode 100644 index 0000000..d4ac644 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:76:1:bridgeif_fdb_update_src 40 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:128:1:bridgeif_fdb_get_dst_ports 32 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:153:1:bridgeif_fdb_age_one_second 32 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:180:1:bridgeif_age_tmr 24 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:195:1:bridgeif_fdb_init 32 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo new file mode 100644 index 0000000..63110ee --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo @@ -0,0 +1,2 @@ +ethernet.c:81:1:ethernet_input 14 +ethernet.c:270:1:ethernet_output 3 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d new file mode 100644 index 0000000..b72404f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d @@ -0,0 +1,143 @@ +Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ethernet.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o new file mode 100644 index 0000000..9b491e5 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su new file mode 100644 index 0000000..b04052e --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su @@ -0,0 +1,2 @@ +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:81:1:ethernet_input 32 static +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:270:1:ethernet_output 32 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d new file mode 100644 index 0000000..9814a18 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d @@ -0,0 +1,95 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o new file mode 100644 index 0000000..309574c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d new file mode 100644 index 0000000..4898371 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d @@ -0,0 +1,95 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o new file mode 100644 index 0000000..1520d6c Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d new file mode 100644 index 0000000..601dac6 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d @@ -0,0 +1,95 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o new file mode 100644 index 0000000..e61e166 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d new file mode 100644 index 0000000..ef39ed2 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o new file mode 100644 index 0000000..00dcf7f Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d new file mode 100644 index 0000000..c6aad07 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o new file mode 100644 index 0000000..7918096 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d new file mode 100644 index 0000000..d6e6101 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o new file mode 100644 index 0000000..4cd9ba2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d new file mode 100644 index 0000000..2b8708c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o new file mode 100644 index 0000000..2cd1a3d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d new file mode 100644 index 0000000..f8d4209 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o new file mode 100644 index 0000000..97ad13f Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d new file mode 100644 index 0000000..8c7e106 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o new file mode 100644 index 0000000..dc62fd6 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d new file mode 100644 index 0000000..19020a4 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o new file mode 100644 index 0000000..8dadc76 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d new file mode 100644 index 0000000..9b1c0b6 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o new file mode 100644 index 0000000..97cdf44 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d new file mode 100644 index 0000000..2cd647a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o new file mode 100644 index 0000000..18fe8ef Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d new file mode 100644 index 0000000..48865e3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o new file mode 100644 index 0000000..7d543ed Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d new file mode 100644 index 0000000..9836d74 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o new file mode 100644 index 0000000..5622177 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d new file mode 100644 index 0000000..96db42c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o new file mode 100644 index 0000000..a436103 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d new file mode 100644 index 0000000..0ed9842 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o new file mode 100644 index 0000000..6a08272 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d new file mode 100644 index 0000000..6a4798f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o new file mode 100644 index 0000000..59242e2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d new file mode 100644 index 0000000..104d42b --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o new file mode 100644 index 0000000..6d27f35 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d new file mode 100644 index 0000000..fa7a4f3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o new file mode 100644 index 0000000..edea0ed Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d new file mode 100644 index 0000000..1052f61 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o new file mode 100644 index 0000000..8d786c6 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d new file mode 100644 index 0000000..69f9f3a --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o new file mode 100644 index 0000000..9f2ce86 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d new file mode 100644 index 0000000..3b48249 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o new file mode 100644 index 0000000..eec3afb Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d new file mode 100644 index 0000000..3853deb --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o new file mode 100644 index 0000000..5ca0ea3 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d new file mode 100644 index 0000000..7858090 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o new file mode 100644 index 0000000..7817c3d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d new file mode 100644 index 0000000..235c372 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o new file mode 100644 index 0000000..cc60df2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk new file mode 100644 index 0000000..8e100bb --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk @@ -0,0 +1,99 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/netif/ppp/%.o Middlewares/Third_Party/LwIP/src/netif/ppp/%.su Middlewares/Third_Party/LwIP/src/netif/ppp/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/ppp/%.c Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp: + -$(RM) ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d new file mode 100644 index 0000000..24de7a1 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o new file mode 100644 index 0000000..01feeae Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d new file mode 100644 index 0000000..2b2bcd8 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o new file mode 100644 index 0000000..fccace2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d new file mode 100644 index 0000000..b697b27 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o new file mode 100644 index 0000000..e76485d Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo new file mode 100644 index 0000000..29aabe0 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo @@ -0,0 +1,7 @@ +slipif.c:116:1:slipif_output 8 +slipif.c:172:1:slipif_output_v4 1 +slipif.c:207:1:slipif_rxbyte 18 +slipif.c:310:1:slipif_rxbyte_input 3 +slipif.c:330:1:slipif_loop_thread 2 +slipif.c:360:1:slipif_init 4 +slipif.c:426:1:slipif_poll 4 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d new file mode 100644 index 0000000..a49d421 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d @@ -0,0 +1,163 @@ +Middlewares/Third_Party/LwIP/src/netif/slipif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/slipif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/slipif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h +../Middlewares/Third_Party/LwIP/src/include/netif/slipif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o new file mode 100644 index 0000000..7e243d2 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su new file mode 100644 index 0000000..962aea3 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su @@ -0,0 +1,7 @@ +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:116:1:slipif_output 32 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:172:1:slipif_output_v4 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:207:1:slipif_rxbyte 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:310:1:slipif_rxbyte_input 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:330:1:slipif_loop_thread 32 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init 32 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:426:1:slipif_poll 24 static diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk new file mode 100644 index 0000000..f5b512c --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif.c \ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c \ +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c \ +../Middlewares/Third_Party/LwIP/src/netif/slipif.c \ +../Middlewares/Third_Party/LwIP/src/netif/zepif.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o \ +./Middlewares/Third_Party/LwIP/src/netif/ethernet.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o \ +./Middlewares/Third_Party/LwIP/src/netif/slipif.o \ +./Middlewares/Third_Party/LwIP/src/netif/zepif.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif.d \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d \ +./Middlewares/Third_Party/LwIP/src/netif/ethernet.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d \ +./Middlewares/Third_Party/LwIP/src/netif/slipif.d \ +./Middlewares/Third_Party/LwIP/src/netif/zepif.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/netif/%.o Middlewares/Third_Party/LwIP/src/netif/%.su Middlewares/Third_Party/LwIP/src/netif/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/%.c Middlewares/Third_Party/LwIP/src/netif/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif: + -$(RM) ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.su ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su ./Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ethernet.d ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o ./Middlewares/Third_Party/LwIP/src/netif/ethernet.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su ./Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/slipif.d ./Middlewares/Third_Party/LwIP/src/netif/slipif.o ./Middlewares/Third_Party/LwIP/src/netif/slipif.su ./Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/zepif.d ./Middlewares/Third_Party/LwIP/src/netif/zepif.o ./Middlewares/Third_Party/LwIP/src/netif/zepif.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d new file mode 100644 index 0000000..45276dd --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d @@ -0,0 +1,97 @@ +Middlewares/Third_Party/LwIP/src/netif/zepif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/zepif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/zepif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h +../Middlewares/Third_Party/LwIP/src/include/netif/zepif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o new file mode 100644 index 0000000..aeeb96a Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.su b/project/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.su new file mode 100644 index 0000000..e69de29 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk new file mode 100644 index 0000000..73694be --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/system/OS/sys_arch.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/system/OS/%.o Middlewares/Third_Party/LwIP/system/OS/%.su Middlewares/Third_Party/LwIP/system/OS/%.cyclo: ../Middlewares/Third_Party/LwIP/system/OS/%.c Middlewares/Third_Party/LwIP/system/OS/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx -c -I../LWIP/App -I../Drivers/BSP/STM32746G-Discovery -I../LWIP/Target -I../Core/Inc -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/system/arch -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS: + -$(RM) ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.d ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-system-2f-OS + diff --git a/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo new file mode 100644 index 0000000..85275b9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.cyclo @@ -0,0 +1,23 @@ +sys_arch.c:50:7:sys_mbox_new 2 +sys_arch.c:77:6:sys_mbox_free 1 +sys_arch.c:104:6:sys_mbox_post 2 +sys_arch.c:116:7:sys_mbox_trypost 2 +sys_arch.c:143:7:sys_mbox_trypost_fromisr 1 +sys_arch.c:164:7:sys_arch_mbox_fetch 3 +sys_arch.c:213:7:sys_arch_mbox_tryfetch 2 +sys_arch.c:235:5:sys_mbox_valid 2 +sys_arch.c:243:6:sys_mbox_set_invalid 1 +sys_arch.c:251:7:sys_sem_new 3 +sys_arch.c:303:7:sys_arch_sem_wait 4 +sys_arch.c:341:6:sys_sem_signal 1 +sys_arch.c:348:6:sys_sem_free 1 +sys_arch.c:357:5:sys_sem_valid 2 +sys_arch.c:366:6:sys_sem_set_invalid 1 +sys_arch.c:379:6:sys_init 1 +sys_arch.c:393:7:sys_mutex_new 2 +sys_arch.c:420:6:sys_mutex_free 1 +sys_arch.c:430:6:sys_mutex_lock 1 +sys_arch.c:441:6:sys_mutex_unlock 1 +sys_arch.c:455:14:sys_thread_new 1 +sys_arch.c:486:12:sys_arch_protect 1 +sys_arch.c:506:6:sys_arch_unprotect 1 diff --git a/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d new file mode 100644 index 0000000..b2b6cd9 --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.d @@ -0,0 +1,145 @@ +Middlewares/Third_Party/LwIP/system/OS/sys_arch.o: \ + ../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +../Core/Inc/stm32f7xx_hal_conf.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/system/arch/sys_arch.h: +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: +../Core/Inc/FreeRTOSConfig.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: diff --git a/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o new file mode 100644 index 0000000..dc71607 Binary files /dev/null and b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.o differ diff --git a/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su new file mode 100644 index 0000000..6366b9f --- /dev/null +++ b/project/Debug/Middlewares/Third_Party/LwIP/system/OS/sys_arch.su @@ -0,0 +1,23 @@ +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:50:7:sys_mbox_new 32 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:77:6:sys_mbox_free 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:104:6:sys_mbox_post 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:116:7:sys_mbox_trypost 24 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:143:7:sys_mbox_trypost_fromisr 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:164:7:sys_arch_mbox_fetch 56 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:213:7:sys_arch_mbox_tryfetch 32 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:235:5:sys_mbox_valid 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:243:6:sys_mbox_set_invalid 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:251:7:sys_sem_new 24 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:303:7:sys_arch_sem_wait 24 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:341:6:sys_sem_signal 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:348:6:sys_sem_free 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:357:5:sys_sem_valid 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:366:6:sys_sem_set_invalid 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:379:6:sys_init 8 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:393:7:sys_mutex_new 24 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:420:6:sys_mutex_free 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:430:6:sys_mutex_lock 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:441:6:sys_mutex_unlock 16 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:455:14:sys_thread_new 56 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:486:12:sys_arch_protect 8 static +../Middlewares/Third_Party/LwIP/system/OS/sys_arch.c:506:6:sys_arch_unprotect 16 static diff --git a/project/Debug/NTP.elf b/project/Debug/NTP.elf new file mode 100755 index 0000000..d8aef95 Binary files /dev/null and b/project/Debug/NTP.elf differ diff --git a/project/Debug/NTP.list b/project/Debug/NTP.list new file mode 100644 index 0000000..3404402 --- /dev/null +++ b/project/Debug/NTP.list @@ -0,0 +1,77703 @@ + +NTP.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001c8 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0001e274 080001d0 080001d0 000101d0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00005910 0801e448 0801e448 0002e448 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08023d58 08023d58 00040268 2**0 + CONTENTS + 4 .ARM 00000008 08023d58 08023d58 00033d58 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08023d60 08023d60 00040268 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08023d60 08023d60 00033d60 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08023d64 08023d64 00033d64 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000128 20000000 08023d68 00040000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .RxDecripSection 000000a0 20000128 08023e90 00040128 2**2 + CONTENTS, ALLOC, LOAD, DATA + 10 .TxDecripSection 000000a0 200001c8 08023f30 000401c8 2**2 + CONTENTS, ALLOC, LOAD, DATA + 11 .bss 0000ce88 20000268 08023fd0 00040268 2**2 + ALLOC + 12 ._user_heap_stack 00000600 2000d0f0 08023fd0 0004d0f0 2**0 + ALLOC + 13 .ARM.attributes 00000030 00000000 00000000 00040268 2**0 + CONTENTS, READONLY + 14 .debug_info 000451c6 00000000 00000000 00040298 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_abbrev 00009d4f 00000000 00000000 0008545e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_aranges 000031d8 00000000 00000000 0008f1b0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_ranges 00002f90 00000000 00000000 00092388 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_macro 0003e84c 00000000 00000000 00095318 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_line 0004cb62 00000000 00000000 000d3b64 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_str 0012ae10 00000000 00000000 001206c6 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .comment 00000050 00000000 00000000 0024b4d6 2**0 + CONTENTS, READONLY + 22 .debug_frame 0000dec8 00000000 00000000 0024b528 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080001d0 <__do_global_dtors_aux>: + 80001d0: b510 push {r4, lr} + 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) + 80001d4: 7823 ldrb r3, [r4, #0] + 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> + 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) + 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> + 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) + 80001de: f3af 8000 nop.w + 80001e2: 2301 movs r3, #1 + 80001e4: 7023 strb r3, [r4, #0] + 80001e6: bd10 pop {r4, pc} + 80001e8: 20000268 .word 0x20000268 + 80001ec: 00000000 .word 0x00000000 + 80001f0: 0801e42c .word 0x0801e42c + +080001f4 : + 80001f4: b508 push {r3, lr} + 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) + 80001f8: b11b cbz r3, 8000202 + 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) + 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) + 80001fe: f3af 8000 nop.w + 8000202: bd08 pop {r3, pc} + 8000204: 00000000 .word 0x00000000 + 8000208: 2000026c .word 0x2000026c + 800020c: 0801e42c .word 0x0801e42c + +08000210 : + 8000210: 4603 mov r3, r0 + 8000212: f813 2b01 ldrb.w r2, [r3], #1 + 8000216: 2a00 cmp r2, #0 + 8000218: d1fb bne.n 8000212 + 800021a: 1a18 subs r0, r3, r0 + 800021c: 3801 subs r0, #1 + 800021e: 4770 bx lr + +08000220 : + 8000220: f001 01ff and.w r1, r1, #255 ; 0xff + 8000224: 2a10 cmp r2, #16 + 8000226: db2b blt.n 8000280 + 8000228: f010 0f07 tst.w r0, #7 + 800022c: d008 beq.n 8000240 + 800022e: f810 3b01 ldrb.w r3, [r0], #1 + 8000232: 3a01 subs r2, #1 + 8000234: 428b cmp r3, r1 + 8000236: d02d beq.n 8000294 + 8000238: f010 0f07 tst.w r0, #7 + 800023c: b342 cbz r2, 8000290 + 800023e: d1f6 bne.n 800022e + 8000240: b4f0 push {r4, r5, r6, r7} + 8000242: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000246: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800024a: f022 0407 bic.w r4, r2, #7 + 800024e: f07f 0700 mvns.w r7, #0 + 8000252: 2300 movs r3, #0 + 8000254: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000258: 3c08 subs r4, #8 + 800025a: ea85 0501 eor.w r5, r5, r1 + 800025e: ea86 0601 eor.w r6, r6, r1 + 8000262: fa85 f547 uadd8 r5, r5, r7 + 8000266: faa3 f587 sel r5, r3, r7 + 800026a: fa86 f647 uadd8 r6, r6, r7 + 800026e: faa5 f687 sel r6, r5, r7 + 8000272: b98e cbnz r6, 8000298 + 8000274: d1ee bne.n 8000254 + 8000276: bcf0 pop {r4, r5, r6, r7} + 8000278: f001 01ff and.w r1, r1, #255 ; 0xff + 800027c: f002 0207 and.w r2, r2, #7 + 8000280: b132 cbz r2, 8000290 + 8000282: f810 3b01 ldrb.w r3, [r0], #1 + 8000286: 3a01 subs r2, #1 + 8000288: ea83 0301 eor.w r3, r3, r1 + 800028c: b113 cbz r3, 8000294 + 800028e: d1f8 bne.n 8000282 + 8000290: 2000 movs r0, #0 + 8000292: 4770 bx lr + 8000294: 3801 subs r0, #1 + 8000296: 4770 bx lr + 8000298: 2d00 cmp r5, #0 + 800029a: bf06 itte eq + 800029c: 4635 moveq r5, r6 + 800029e: 3803 subeq r0, #3 + 80002a0: 3807 subne r0, #7 + 80002a2: f015 0f01 tst.w r5, #1 + 80002a6: d107 bne.n 80002b8 + 80002a8: 3001 adds r0, #1 + 80002aa: f415 7f80 tst.w r5, #256 ; 0x100 + 80002ae: bf02 ittt eq + 80002b0: 3001 addeq r0, #1 + 80002b2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 80002b6: 3001 addeq r0, #1 + 80002b8: bcf0 pop {r4, r5, r6, r7} + 80002ba: 3801 subs r0, #1 + 80002bc: 4770 bx lr + 80002be: bf00 nop + +080002c0 <__aeabi_drsub>: + 80002c0: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 80002c4: e002 b.n 80002cc <__adddf3> + 80002c6: bf00 nop + +080002c8 <__aeabi_dsub>: + 80002c8: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +080002cc <__adddf3>: + 80002cc: b530 push {r4, r5, lr} + 80002ce: ea4f 0441 mov.w r4, r1, lsl #1 + 80002d2: ea4f 0543 mov.w r5, r3, lsl #1 + 80002d6: ea94 0f05 teq r4, r5 + 80002da: bf08 it eq + 80002dc: ea90 0f02 teqeq r0, r2 + 80002e0: bf1f itttt ne + 80002e2: ea54 0c00 orrsne.w ip, r4, r0 + 80002e6: ea55 0c02 orrsne.w ip, r5, r2 + 80002ea: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 80002ee: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80002f2: f000 80e2 beq.w 80004ba <__adddf3+0x1ee> + 80002f6: ea4f 5454 mov.w r4, r4, lsr #21 + 80002fa: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 80002fe: bfb8 it lt + 8000300: 426d neglt r5, r5 + 8000302: dd0c ble.n 800031e <__adddf3+0x52> + 8000304: 442c add r4, r5 + 8000306: ea80 0202 eor.w r2, r0, r2 + 800030a: ea81 0303 eor.w r3, r1, r3 + 800030e: ea82 0000 eor.w r0, r2, r0 + 8000312: ea83 0101 eor.w r1, r3, r1 + 8000316: ea80 0202 eor.w r2, r0, r2 + 800031a: ea81 0303 eor.w r3, r1, r3 + 800031e: 2d36 cmp r5, #54 ; 0x36 + 8000320: bf88 it hi + 8000322: bd30 pophi {r4, r5, pc} + 8000324: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000328: ea4f 3101 mov.w r1, r1, lsl #12 + 800032c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 8000330: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 8000334: d002 beq.n 800033c <__adddf3+0x70> + 8000336: 4240 negs r0, r0 + 8000338: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800033c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 8000340: ea4f 3303 mov.w r3, r3, lsl #12 + 8000344: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 8000348: d002 beq.n 8000350 <__adddf3+0x84> + 800034a: 4252 negs r2, r2 + 800034c: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000350: ea94 0f05 teq r4, r5 + 8000354: f000 80a7 beq.w 80004a6 <__adddf3+0x1da> + 8000358: f1a4 0401 sub.w r4, r4, #1 + 800035c: f1d5 0e20 rsbs lr, r5, #32 + 8000360: db0d blt.n 800037e <__adddf3+0xb2> + 8000362: fa02 fc0e lsl.w ip, r2, lr + 8000366: fa22 f205 lsr.w r2, r2, r5 + 800036a: 1880 adds r0, r0, r2 + 800036c: f141 0100 adc.w r1, r1, #0 + 8000370: fa03 f20e lsl.w r2, r3, lr + 8000374: 1880 adds r0, r0, r2 + 8000376: fa43 f305 asr.w r3, r3, r5 + 800037a: 4159 adcs r1, r3 + 800037c: e00e b.n 800039c <__adddf3+0xd0> + 800037e: f1a5 0520 sub.w r5, r5, #32 + 8000382: f10e 0e20 add.w lr, lr, #32 + 8000386: 2a01 cmp r2, #1 + 8000388: fa03 fc0e lsl.w ip, r3, lr + 800038c: bf28 it cs + 800038e: f04c 0c02 orrcs.w ip, ip, #2 + 8000392: fa43 f305 asr.w r3, r3, r5 + 8000396: 18c0 adds r0, r0, r3 + 8000398: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 800039c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80003a0: d507 bpl.n 80003b2 <__adddf3+0xe6> + 80003a2: f04f 0e00 mov.w lr, #0 + 80003a6: f1dc 0c00 rsbs ip, ip, #0 + 80003aa: eb7e 0000 sbcs.w r0, lr, r0 + 80003ae: eb6e 0101 sbc.w r1, lr, r1 + 80003b2: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 80003b6: d31b bcc.n 80003f0 <__adddf3+0x124> + 80003b8: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 80003bc: d30c bcc.n 80003d8 <__adddf3+0x10c> + 80003be: 0849 lsrs r1, r1, #1 + 80003c0: ea5f 0030 movs.w r0, r0, rrx + 80003c4: ea4f 0c3c mov.w ip, ip, rrx + 80003c8: f104 0401 add.w r4, r4, #1 + 80003cc: ea4f 5244 mov.w r2, r4, lsl #21 + 80003d0: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 80003d4: f080 809a bcs.w 800050c <__adddf3+0x240> + 80003d8: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 80003dc: bf08 it eq + 80003de: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80003e2: f150 0000 adcs.w r0, r0, #0 + 80003e6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80003ea: ea41 0105 orr.w r1, r1, r5 + 80003ee: bd30 pop {r4, r5, pc} + 80003f0: ea5f 0c4c movs.w ip, ip, lsl #1 + 80003f4: 4140 adcs r0, r0 + 80003f6: eb41 0101 adc.w r1, r1, r1 + 80003fa: 3c01 subs r4, #1 + 80003fc: bf28 it cs + 80003fe: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 + 8000402: d2e9 bcs.n 80003d8 <__adddf3+0x10c> + 8000404: f091 0f00 teq r1, #0 + 8000408: bf04 itt eq + 800040a: 4601 moveq r1, r0 + 800040c: 2000 moveq r0, #0 + 800040e: fab1 f381 clz r3, r1 + 8000412: bf08 it eq + 8000414: 3320 addeq r3, #32 + 8000416: f1a3 030b sub.w r3, r3, #11 + 800041a: f1b3 0220 subs.w r2, r3, #32 + 800041e: da0c bge.n 800043a <__adddf3+0x16e> + 8000420: 320c adds r2, #12 + 8000422: dd08 ble.n 8000436 <__adddf3+0x16a> + 8000424: f102 0c14 add.w ip, r2, #20 + 8000428: f1c2 020c rsb r2, r2, #12 + 800042c: fa01 f00c lsl.w r0, r1, ip + 8000430: fa21 f102 lsr.w r1, r1, r2 + 8000434: e00c b.n 8000450 <__adddf3+0x184> + 8000436: f102 0214 add.w r2, r2, #20 + 800043a: bfd8 it le + 800043c: f1c2 0c20 rsble ip, r2, #32 + 8000440: fa01 f102 lsl.w r1, r1, r2 + 8000444: fa20 fc0c lsr.w ip, r0, ip + 8000448: bfdc itt le + 800044a: ea41 010c orrle.w r1, r1, ip + 800044e: 4090 lslle r0, r2 + 8000450: 1ae4 subs r4, r4, r3 + 8000452: bfa2 ittt ge + 8000454: eb01 5104 addge.w r1, r1, r4, lsl #20 + 8000458: 4329 orrge r1, r5 + 800045a: bd30 popge {r4, r5, pc} + 800045c: ea6f 0404 mvn.w r4, r4 + 8000460: 3c1f subs r4, #31 + 8000462: da1c bge.n 800049e <__adddf3+0x1d2> + 8000464: 340c adds r4, #12 + 8000466: dc0e bgt.n 8000486 <__adddf3+0x1ba> + 8000468: f104 0414 add.w r4, r4, #20 + 800046c: f1c4 0220 rsb r2, r4, #32 + 8000470: fa20 f004 lsr.w r0, r0, r4 + 8000474: fa01 f302 lsl.w r3, r1, r2 + 8000478: ea40 0003 orr.w r0, r0, r3 + 800047c: fa21 f304 lsr.w r3, r1, r4 + 8000480: ea45 0103 orr.w r1, r5, r3 + 8000484: bd30 pop {r4, r5, pc} + 8000486: f1c4 040c rsb r4, r4, #12 + 800048a: f1c4 0220 rsb r2, r4, #32 + 800048e: fa20 f002 lsr.w r0, r0, r2 + 8000492: fa01 f304 lsl.w r3, r1, r4 + 8000496: ea40 0003 orr.w r0, r0, r3 + 800049a: 4629 mov r1, r5 + 800049c: bd30 pop {r4, r5, pc} + 800049e: fa21 f004 lsr.w r0, r1, r4 + 80004a2: 4629 mov r1, r5 + 80004a4: bd30 pop {r4, r5, pc} + 80004a6: f094 0f00 teq r4, #0 + 80004aa: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 80004ae: bf06 itte eq + 80004b0: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 80004b4: 3401 addeq r4, #1 + 80004b6: 3d01 subne r5, #1 + 80004b8: e74e b.n 8000358 <__adddf3+0x8c> + 80004ba: ea7f 5c64 mvns.w ip, r4, asr #21 + 80004be: bf18 it ne + 80004c0: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80004c4: d029 beq.n 800051a <__adddf3+0x24e> + 80004c6: ea94 0f05 teq r4, r5 + 80004ca: bf08 it eq + 80004cc: ea90 0f02 teqeq r0, r2 + 80004d0: d005 beq.n 80004de <__adddf3+0x212> + 80004d2: ea54 0c00 orrs.w ip, r4, r0 + 80004d6: bf04 itt eq + 80004d8: 4619 moveq r1, r3 + 80004da: 4610 moveq r0, r2 + 80004dc: bd30 pop {r4, r5, pc} + 80004de: ea91 0f03 teq r1, r3 + 80004e2: bf1e ittt ne + 80004e4: 2100 movne r1, #0 + 80004e6: 2000 movne r0, #0 + 80004e8: bd30 popne {r4, r5, pc} + 80004ea: ea5f 5c54 movs.w ip, r4, lsr #21 + 80004ee: d105 bne.n 80004fc <__adddf3+0x230> + 80004f0: 0040 lsls r0, r0, #1 + 80004f2: 4149 adcs r1, r1 + 80004f4: bf28 it cs + 80004f6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 80004fa: bd30 pop {r4, r5, pc} + 80004fc: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 8000500: bf3c itt cc + 8000502: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 8000506: bd30 popcc {r4, r5, pc} + 8000508: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 800050c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 8000510: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 8000514: f04f 0000 mov.w r0, #0 + 8000518: bd30 pop {r4, r5, pc} + 800051a: ea7f 5c64 mvns.w ip, r4, asr #21 + 800051e: bf1a itte ne + 8000520: 4619 movne r1, r3 + 8000522: 4610 movne r0, r2 + 8000524: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 8000528: bf1c itt ne + 800052a: 460b movne r3, r1 + 800052c: 4602 movne r2, r0 + 800052e: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 8000532: bf06 itte eq + 8000534: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 8000538: ea91 0f03 teqeq r1, r3 + 800053c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 8000540: bd30 pop {r4, r5, pc} + 8000542: bf00 nop + +08000544 <__aeabi_ui2d>: + 8000544: f090 0f00 teq r0, #0 + 8000548: bf04 itt eq + 800054a: 2100 moveq r1, #0 + 800054c: 4770 bxeq lr + 800054e: b530 push {r4, r5, lr} + 8000550: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000554: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000558: f04f 0500 mov.w r5, #0 + 800055c: f04f 0100 mov.w r1, #0 + 8000560: e750 b.n 8000404 <__adddf3+0x138> + 8000562: bf00 nop + +08000564 <__aeabi_i2d>: + 8000564: f090 0f00 teq r0, #0 + 8000568: bf04 itt eq + 800056a: 2100 moveq r1, #0 + 800056c: 4770 bxeq lr + 800056e: b530 push {r4, r5, lr} + 8000570: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000574: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000578: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 800057c: bf48 it mi + 800057e: 4240 negmi r0, r0 + 8000580: f04f 0100 mov.w r1, #0 + 8000584: e73e b.n 8000404 <__adddf3+0x138> + 8000586: bf00 nop + +08000588 <__aeabi_f2d>: + 8000588: 0042 lsls r2, r0, #1 + 800058a: ea4f 01e2 mov.w r1, r2, asr #3 + 800058e: ea4f 0131 mov.w r1, r1, rrx + 8000592: ea4f 7002 mov.w r0, r2, lsl #28 + 8000596: bf1f itttt ne + 8000598: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 800059c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 80005a0: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 80005a4: 4770 bxne lr + 80005a6: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 80005aa: bf08 it eq + 80005ac: 4770 bxeq lr + 80005ae: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 80005b2: bf04 itt eq + 80005b4: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 80005b8: 4770 bxeq lr + 80005ba: b530 push {r4, r5, lr} + 80005bc: f44f 7460 mov.w r4, #896 ; 0x380 + 80005c0: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80005c4: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 80005c8: e71c b.n 8000404 <__adddf3+0x138> + 80005ca: bf00 nop + +080005cc <__aeabi_ul2d>: + 80005cc: ea50 0201 orrs.w r2, r0, r1 + 80005d0: bf08 it eq + 80005d2: 4770 bxeq lr + 80005d4: b530 push {r4, r5, lr} + 80005d6: f04f 0500 mov.w r5, #0 + 80005da: e00a b.n 80005f2 <__aeabi_l2d+0x16> + +080005dc <__aeabi_l2d>: + 80005dc: ea50 0201 orrs.w r2, r0, r1 + 80005e0: bf08 it eq + 80005e2: 4770 bxeq lr + 80005e4: b530 push {r4, r5, lr} + 80005e6: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 80005ea: d502 bpl.n 80005f2 <__aeabi_l2d+0x16> + 80005ec: 4240 negs r0, r0 + 80005ee: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80005f2: f44f 6480 mov.w r4, #1024 ; 0x400 + 80005f6: f104 0432 add.w r4, r4, #50 ; 0x32 + 80005fa: ea5f 5c91 movs.w ip, r1, lsr #22 + 80005fe: f43f aed8 beq.w 80003b2 <__adddf3+0xe6> + 8000602: f04f 0203 mov.w r2, #3 + 8000606: ea5f 0cdc movs.w ip, ip, lsr #3 + 800060a: bf18 it ne + 800060c: 3203 addne r2, #3 + 800060e: ea5f 0cdc movs.w ip, ip, lsr #3 + 8000612: bf18 it ne + 8000614: 3203 addne r2, #3 + 8000616: eb02 02dc add.w r2, r2, ip, lsr #3 + 800061a: f1c2 0320 rsb r3, r2, #32 + 800061e: fa00 fc03 lsl.w ip, r0, r3 + 8000622: fa20 f002 lsr.w r0, r0, r2 + 8000626: fa01 fe03 lsl.w lr, r1, r3 + 800062a: ea40 000e orr.w r0, r0, lr + 800062e: fa21 f102 lsr.w r1, r1, r2 + 8000632: 4414 add r4, r2 + 8000634: e6bd b.n 80003b2 <__adddf3+0xe6> + 8000636: bf00 nop + +08000638 <__aeabi_dmul>: + 8000638: b570 push {r4, r5, r6, lr} + 800063a: f04f 0cff mov.w ip, #255 ; 0xff + 800063e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000642: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 8000646: bf1d ittte ne + 8000648: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 800064c: ea94 0f0c teqne r4, ip + 8000650: ea95 0f0c teqne r5, ip + 8000654: f000 f8de bleq 8000814 <__aeabi_dmul+0x1dc> + 8000658: 442c add r4, r5 + 800065a: ea81 0603 eor.w r6, r1, r3 + 800065e: ea21 514c bic.w r1, r1, ip, lsl #21 + 8000662: ea23 534c bic.w r3, r3, ip, lsl #21 + 8000666: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 800066a: bf18 it ne + 800066c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000670: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000674: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8000678: d038 beq.n 80006ec <__aeabi_dmul+0xb4> + 800067a: fba0 ce02 umull ip, lr, r0, r2 + 800067e: f04f 0500 mov.w r5, #0 + 8000682: fbe1 e502 umlal lr, r5, r1, r2 + 8000686: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 800068a: fbe0 e503 umlal lr, r5, r0, r3 + 800068e: f04f 0600 mov.w r6, #0 + 8000692: fbe1 5603 umlal r5, r6, r1, r3 + 8000696: f09c 0f00 teq ip, #0 + 800069a: bf18 it ne + 800069c: f04e 0e01 orrne.w lr, lr, #1 + 80006a0: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 80006a4: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 80006a8: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 80006ac: d204 bcs.n 80006b8 <__aeabi_dmul+0x80> + 80006ae: ea5f 0e4e movs.w lr, lr, lsl #1 + 80006b2: 416d adcs r5, r5 + 80006b4: eb46 0606 adc.w r6, r6, r6 + 80006b8: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 80006bc: ea41 5155 orr.w r1, r1, r5, lsr #21 + 80006c0: ea4f 20c5 mov.w r0, r5, lsl #11 + 80006c4: ea40 505e orr.w r0, r0, lr, lsr #21 + 80006c8: ea4f 2ece mov.w lr, lr, lsl #11 + 80006cc: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80006d0: bf88 it hi + 80006d2: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80006d6: d81e bhi.n 8000716 <__aeabi_dmul+0xde> + 80006d8: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 80006dc: bf08 it eq + 80006de: ea5f 0e50 movseq.w lr, r0, lsr #1 + 80006e2: f150 0000 adcs.w r0, r0, #0 + 80006e6: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80006ea: bd70 pop {r4, r5, r6, pc} + 80006ec: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 80006f0: ea46 0101 orr.w r1, r6, r1 + 80006f4: ea40 0002 orr.w r0, r0, r2 + 80006f8: ea81 0103 eor.w r1, r1, r3 + 80006fc: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8000700: bfc2 ittt gt + 8000702: ebd4 050c rsbsgt r5, r4, ip + 8000706: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 800070a: bd70 popgt {r4, r5, r6, pc} + 800070c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000710: f04f 0e00 mov.w lr, #0 + 8000714: 3c01 subs r4, #1 + 8000716: f300 80ab bgt.w 8000870 <__aeabi_dmul+0x238> + 800071a: f114 0f36 cmn.w r4, #54 ; 0x36 + 800071e: bfde ittt le + 8000720: 2000 movle r0, #0 + 8000722: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 8000726: bd70 pople {r4, r5, r6, pc} + 8000728: f1c4 0400 rsb r4, r4, #0 + 800072c: 3c20 subs r4, #32 + 800072e: da35 bge.n 800079c <__aeabi_dmul+0x164> + 8000730: 340c adds r4, #12 + 8000732: dc1b bgt.n 800076c <__aeabi_dmul+0x134> + 8000734: f104 0414 add.w r4, r4, #20 + 8000738: f1c4 0520 rsb r5, r4, #32 + 800073c: fa00 f305 lsl.w r3, r0, r5 + 8000740: fa20 f004 lsr.w r0, r0, r4 + 8000744: fa01 f205 lsl.w r2, r1, r5 + 8000748: ea40 0002 orr.w r0, r0, r2 + 800074c: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 8000750: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000754: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000758: fa21 f604 lsr.w r6, r1, r4 + 800075c: eb42 0106 adc.w r1, r2, r6 + 8000760: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000764: bf08 it eq + 8000766: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800076a: bd70 pop {r4, r5, r6, pc} + 800076c: f1c4 040c rsb r4, r4, #12 + 8000770: f1c4 0520 rsb r5, r4, #32 + 8000774: fa00 f304 lsl.w r3, r0, r4 + 8000778: fa20 f005 lsr.w r0, r0, r5 + 800077c: fa01 f204 lsl.w r2, r1, r4 + 8000780: ea40 0002 orr.w r0, r0, r2 + 8000784: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000788: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 800078c: f141 0100 adc.w r1, r1, #0 + 8000790: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000794: bf08 it eq + 8000796: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800079a: bd70 pop {r4, r5, r6, pc} + 800079c: f1c4 0520 rsb r5, r4, #32 + 80007a0: fa00 f205 lsl.w r2, r0, r5 + 80007a4: ea4e 0e02 orr.w lr, lr, r2 + 80007a8: fa20 f304 lsr.w r3, r0, r4 + 80007ac: fa01 f205 lsl.w r2, r1, r5 + 80007b0: ea43 0302 orr.w r3, r3, r2 + 80007b4: fa21 f004 lsr.w r0, r1, r4 + 80007b8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80007bc: fa21 f204 lsr.w r2, r1, r4 + 80007c0: ea20 0002 bic.w r0, r0, r2 + 80007c4: eb00 70d3 add.w r0, r0, r3, lsr #31 + 80007c8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80007cc: bf08 it eq + 80007ce: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80007d2: bd70 pop {r4, r5, r6, pc} + 80007d4: f094 0f00 teq r4, #0 + 80007d8: d10f bne.n 80007fa <__aeabi_dmul+0x1c2> + 80007da: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 80007de: 0040 lsls r0, r0, #1 + 80007e0: eb41 0101 adc.w r1, r1, r1 + 80007e4: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80007e8: bf08 it eq + 80007ea: 3c01 subeq r4, #1 + 80007ec: d0f7 beq.n 80007de <__aeabi_dmul+0x1a6> + 80007ee: ea41 0106 orr.w r1, r1, r6 + 80007f2: f095 0f00 teq r5, #0 + 80007f6: bf18 it ne + 80007f8: 4770 bxne lr + 80007fa: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 80007fe: 0052 lsls r2, r2, #1 + 8000800: eb43 0303 adc.w r3, r3, r3 + 8000804: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 8000808: bf08 it eq + 800080a: 3d01 subeq r5, #1 + 800080c: d0f7 beq.n 80007fe <__aeabi_dmul+0x1c6> + 800080e: ea43 0306 orr.w r3, r3, r6 + 8000812: 4770 bx lr + 8000814: ea94 0f0c teq r4, ip + 8000818: ea0c 5513 and.w r5, ip, r3, lsr #20 + 800081c: bf18 it ne + 800081e: ea95 0f0c teqne r5, ip + 8000822: d00c beq.n 800083e <__aeabi_dmul+0x206> + 8000824: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000828: bf18 it ne + 800082a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 800082e: d1d1 bne.n 80007d4 <__aeabi_dmul+0x19c> + 8000830: ea81 0103 eor.w r1, r1, r3 + 8000834: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000838: f04f 0000 mov.w r0, #0 + 800083c: bd70 pop {r4, r5, r6, pc} + 800083e: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000842: bf06 itte eq + 8000844: 4610 moveq r0, r2 + 8000846: 4619 moveq r1, r3 + 8000848: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 800084c: d019 beq.n 8000882 <__aeabi_dmul+0x24a> + 800084e: ea94 0f0c teq r4, ip + 8000852: d102 bne.n 800085a <__aeabi_dmul+0x222> + 8000854: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 8000858: d113 bne.n 8000882 <__aeabi_dmul+0x24a> + 800085a: ea95 0f0c teq r5, ip + 800085e: d105 bne.n 800086c <__aeabi_dmul+0x234> + 8000860: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 8000864: bf1c itt ne + 8000866: 4610 movne r0, r2 + 8000868: 4619 movne r1, r3 + 800086a: d10a bne.n 8000882 <__aeabi_dmul+0x24a> + 800086c: ea81 0103 eor.w r1, r1, r3 + 8000870: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000874: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000878: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800087c: f04f 0000 mov.w r0, #0 + 8000880: bd70 pop {r4, r5, r6, pc} + 8000882: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000886: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 800088a: bd70 pop {r4, r5, r6, pc} + +0800088c <__aeabi_ddiv>: + 800088c: b570 push {r4, r5, r6, lr} + 800088e: f04f 0cff mov.w ip, #255 ; 0xff + 8000892: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000896: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800089a: bf1d ittte ne + 800089c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80008a0: ea94 0f0c teqne r4, ip + 80008a4: ea95 0f0c teqne r5, ip + 80008a8: f000 f8a7 bleq 80009fa <__aeabi_ddiv+0x16e> + 80008ac: eba4 0405 sub.w r4, r4, r5 + 80008b0: ea81 0e03 eor.w lr, r1, r3 + 80008b4: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80008b8: ea4f 3101 mov.w r1, r1, lsl #12 + 80008bc: f000 8088 beq.w 80009d0 <__aeabi_ddiv+0x144> + 80008c0: ea4f 3303 mov.w r3, r3, lsl #12 + 80008c4: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 80008c8: ea45 1313 orr.w r3, r5, r3, lsr #4 + 80008cc: ea43 6312 orr.w r3, r3, r2, lsr #24 + 80008d0: ea4f 2202 mov.w r2, r2, lsl #8 + 80008d4: ea45 1511 orr.w r5, r5, r1, lsr #4 + 80008d8: ea45 6510 orr.w r5, r5, r0, lsr #24 + 80008dc: ea4f 2600 mov.w r6, r0, lsl #8 + 80008e0: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 80008e4: 429d cmp r5, r3 + 80008e6: bf08 it eq + 80008e8: 4296 cmpeq r6, r2 + 80008ea: f144 04fd adc.w r4, r4, #253 ; 0xfd + 80008ee: f504 7440 add.w r4, r4, #768 ; 0x300 + 80008f2: d202 bcs.n 80008fa <__aeabi_ddiv+0x6e> + 80008f4: 085b lsrs r3, r3, #1 + 80008f6: ea4f 0232 mov.w r2, r2, rrx + 80008fa: 1ab6 subs r6, r6, r2 + 80008fc: eb65 0503 sbc.w r5, r5, r3 + 8000900: 085b lsrs r3, r3, #1 + 8000902: ea4f 0232 mov.w r2, r2, rrx + 8000906: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 800090a: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 800090e: ebb6 0e02 subs.w lr, r6, r2 + 8000912: eb75 0e03 sbcs.w lr, r5, r3 + 8000916: bf22 ittt cs + 8000918: 1ab6 subcs r6, r6, r2 + 800091a: 4675 movcs r5, lr + 800091c: ea40 000c orrcs.w r0, r0, ip + 8000920: 085b lsrs r3, r3, #1 + 8000922: ea4f 0232 mov.w r2, r2, rrx + 8000926: ebb6 0e02 subs.w lr, r6, r2 + 800092a: eb75 0e03 sbcs.w lr, r5, r3 + 800092e: bf22 ittt cs + 8000930: 1ab6 subcs r6, r6, r2 + 8000932: 4675 movcs r5, lr + 8000934: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000938: 085b lsrs r3, r3, #1 + 800093a: ea4f 0232 mov.w r2, r2, rrx + 800093e: ebb6 0e02 subs.w lr, r6, r2 + 8000942: eb75 0e03 sbcs.w lr, r5, r3 + 8000946: bf22 ittt cs + 8000948: 1ab6 subcs r6, r6, r2 + 800094a: 4675 movcs r5, lr + 800094c: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000950: 085b lsrs r3, r3, #1 + 8000952: ea4f 0232 mov.w r2, r2, rrx + 8000956: ebb6 0e02 subs.w lr, r6, r2 + 800095a: eb75 0e03 sbcs.w lr, r5, r3 + 800095e: bf22 ittt cs + 8000960: 1ab6 subcs r6, r6, r2 + 8000962: 4675 movcs r5, lr + 8000964: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000968: ea55 0e06 orrs.w lr, r5, r6 + 800096c: d018 beq.n 80009a0 <__aeabi_ddiv+0x114> + 800096e: ea4f 1505 mov.w r5, r5, lsl #4 + 8000972: ea45 7516 orr.w r5, r5, r6, lsr #28 + 8000976: ea4f 1606 mov.w r6, r6, lsl #4 + 800097a: ea4f 03c3 mov.w r3, r3, lsl #3 + 800097e: ea43 7352 orr.w r3, r3, r2, lsr #29 + 8000982: ea4f 02c2 mov.w r2, r2, lsl #3 + 8000986: ea5f 1c1c movs.w ip, ip, lsr #4 + 800098a: d1c0 bne.n 800090e <__aeabi_ddiv+0x82> + 800098c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000990: d10b bne.n 80009aa <__aeabi_ddiv+0x11e> + 8000992: ea41 0100 orr.w r1, r1, r0 + 8000996: f04f 0000 mov.w r0, #0 + 800099a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 800099e: e7b6 b.n 800090e <__aeabi_ddiv+0x82> + 80009a0: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80009a4: bf04 itt eq + 80009a6: 4301 orreq r1, r0 + 80009a8: 2000 moveq r0, #0 + 80009aa: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80009ae: bf88 it hi + 80009b0: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80009b4: f63f aeaf bhi.w 8000716 <__aeabi_dmul+0xde> + 80009b8: ebb5 0c03 subs.w ip, r5, r3 + 80009bc: bf04 itt eq + 80009be: ebb6 0c02 subseq.w ip, r6, r2 + 80009c2: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80009c6: f150 0000 adcs.w r0, r0, #0 + 80009ca: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80009ce: bd70 pop {r4, r5, r6, pc} + 80009d0: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 80009d4: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 80009d8: eb14 045c adds.w r4, r4, ip, lsr #1 + 80009dc: bfc2 ittt gt + 80009de: ebd4 050c rsbsgt r5, r4, ip + 80009e2: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80009e6: bd70 popgt {r4, r5, r6, pc} + 80009e8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80009ec: f04f 0e00 mov.w lr, #0 + 80009f0: 3c01 subs r4, #1 + 80009f2: e690 b.n 8000716 <__aeabi_dmul+0xde> + 80009f4: ea45 0e06 orr.w lr, r5, r6 + 80009f8: e68d b.n 8000716 <__aeabi_dmul+0xde> + 80009fa: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80009fe: ea94 0f0c teq r4, ip + 8000a02: bf08 it eq + 8000a04: ea95 0f0c teqeq r5, ip + 8000a08: f43f af3b beq.w 8000882 <__aeabi_dmul+0x24a> + 8000a0c: ea94 0f0c teq r4, ip + 8000a10: d10a bne.n 8000a28 <__aeabi_ddiv+0x19c> + 8000a12: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 8000a16: f47f af34 bne.w 8000882 <__aeabi_dmul+0x24a> + 8000a1a: ea95 0f0c teq r5, ip + 8000a1e: f47f af25 bne.w 800086c <__aeabi_dmul+0x234> + 8000a22: 4610 mov r0, r2 + 8000a24: 4619 mov r1, r3 + 8000a26: e72c b.n 8000882 <__aeabi_dmul+0x24a> + 8000a28: ea95 0f0c teq r5, ip + 8000a2c: d106 bne.n 8000a3c <__aeabi_ddiv+0x1b0> + 8000a2e: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000a32: f43f aefd beq.w 8000830 <__aeabi_dmul+0x1f8> + 8000a36: 4610 mov r0, r2 + 8000a38: 4619 mov r1, r3 + 8000a3a: e722 b.n 8000882 <__aeabi_dmul+0x24a> + 8000a3c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000a40: bf18 it ne + 8000a42: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000a46: f47f aec5 bne.w 80007d4 <__aeabi_dmul+0x19c> + 8000a4a: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 8000a4e: f47f af0d bne.w 800086c <__aeabi_dmul+0x234> + 8000a52: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 8000a56: f47f aeeb bne.w 8000830 <__aeabi_dmul+0x1f8> + 8000a5a: e712 b.n 8000882 <__aeabi_dmul+0x24a> + +08000a5c <__gedf2>: + 8000a5c: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff + 8000a60: e006 b.n 8000a70 <__cmpdf2+0x4> + 8000a62: bf00 nop + +08000a64 <__ledf2>: + 8000a64: f04f 0c01 mov.w ip, #1 + 8000a68: e002 b.n 8000a70 <__cmpdf2+0x4> + 8000a6a: bf00 nop + +08000a6c <__cmpdf2>: + 8000a6c: f04f 0c01 mov.w ip, #1 + 8000a70: f84d cd04 str.w ip, [sp, #-4]! + 8000a74: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a78: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a7c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000a80: bf18 it ne + 8000a82: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 8000a86: d01b beq.n 8000ac0 <__cmpdf2+0x54> + 8000a88: b001 add sp, #4 + 8000a8a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 8000a8e: bf0c ite eq + 8000a90: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000a94: ea91 0f03 teqne r1, r3 + 8000a98: bf02 ittt eq + 8000a9a: ea90 0f02 teqeq r0, r2 + 8000a9e: 2000 moveq r0, #0 + 8000aa0: 4770 bxeq lr + 8000aa2: f110 0f00 cmn.w r0, #0 + 8000aa6: ea91 0f03 teq r1, r3 + 8000aaa: bf58 it pl + 8000aac: 4299 cmppl r1, r3 + 8000aae: bf08 it eq + 8000ab0: 4290 cmpeq r0, r2 + 8000ab2: bf2c ite cs + 8000ab4: 17d8 asrcs r0, r3, #31 + 8000ab6: ea6f 70e3 mvncc.w r0, r3, asr #31 + 8000aba: f040 0001 orr.w r0, r0, #1 + 8000abe: 4770 bx lr + 8000ac0: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000ac4: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000ac8: d102 bne.n 8000ad0 <__cmpdf2+0x64> + 8000aca: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000ace: d107 bne.n 8000ae0 <__cmpdf2+0x74> + 8000ad0: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000ad4: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000ad8: d1d6 bne.n 8000a88 <__cmpdf2+0x1c> + 8000ada: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000ade: d0d3 beq.n 8000a88 <__cmpdf2+0x1c> + 8000ae0: f85d 0b04 ldr.w r0, [sp], #4 + 8000ae4: 4770 bx lr + 8000ae6: bf00 nop + +08000ae8 <__aeabi_cdrcmple>: + 8000ae8: 4684 mov ip, r0 + 8000aea: 4610 mov r0, r2 + 8000aec: 4662 mov r2, ip + 8000aee: 468c mov ip, r1 + 8000af0: 4619 mov r1, r3 + 8000af2: 4663 mov r3, ip + 8000af4: e000 b.n 8000af8 <__aeabi_cdcmpeq> + 8000af6: bf00 nop + +08000af8 <__aeabi_cdcmpeq>: + 8000af8: b501 push {r0, lr} + 8000afa: f7ff ffb7 bl 8000a6c <__cmpdf2> + 8000afe: 2800 cmp r0, #0 + 8000b00: bf48 it mi + 8000b02: f110 0f00 cmnmi.w r0, #0 + 8000b06: bd01 pop {r0, pc} + +08000b08 <__aeabi_dcmpeq>: + 8000b08: f84d ed08 str.w lr, [sp, #-8]! + 8000b0c: f7ff fff4 bl 8000af8 <__aeabi_cdcmpeq> + 8000b10: bf0c ite eq + 8000b12: 2001 moveq r0, #1 + 8000b14: 2000 movne r0, #0 + 8000b16: f85d fb08 ldr.w pc, [sp], #8 + 8000b1a: bf00 nop + +08000b1c <__aeabi_dcmplt>: + 8000b1c: f84d ed08 str.w lr, [sp, #-8]! + 8000b20: f7ff ffea bl 8000af8 <__aeabi_cdcmpeq> + 8000b24: bf34 ite cc + 8000b26: 2001 movcc r0, #1 + 8000b28: 2000 movcs r0, #0 + 8000b2a: f85d fb08 ldr.w pc, [sp], #8 + 8000b2e: bf00 nop + +08000b30 <__aeabi_dcmple>: + 8000b30: f84d ed08 str.w lr, [sp, #-8]! + 8000b34: f7ff ffe0 bl 8000af8 <__aeabi_cdcmpeq> + 8000b38: bf94 ite ls + 8000b3a: 2001 movls r0, #1 + 8000b3c: 2000 movhi r0, #0 + 8000b3e: f85d fb08 ldr.w pc, [sp], #8 + 8000b42: bf00 nop + +08000b44 <__aeabi_dcmpge>: + 8000b44: f84d ed08 str.w lr, [sp, #-8]! + 8000b48: f7ff ffce bl 8000ae8 <__aeabi_cdrcmple> + 8000b4c: bf94 ite ls + 8000b4e: 2001 movls r0, #1 + 8000b50: 2000 movhi r0, #0 + 8000b52: f85d fb08 ldr.w pc, [sp], #8 + 8000b56: bf00 nop + +08000b58 <__aeabi_dcmpgt>: + 8000b58: f84d ed08 str.w lr, [sp, #-8]! + 8000b5c: f7ff ffc4 bl 8000ae8 <__aeabi_cdrcmple> + 8000b60: bf34 ite cc + 8000b62: 2001 movcc r0, #1 + 8000b64: 2000 movcs r0, #0 + 8000b66: f85d fb08 ldr.w pc, [sp], #8 + 8000b6a: bf00 nop + +08000b6c <__aeabi_d2iz>: + 8000b6c: ea4f 0241 mov.w r2, r1, lsl #1 + 8000b70: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000b74: d215 bcs.n 8000ba2 <__aeabi_d2iz+0x36> + 8000b76: d511 bpl.n 8000b9c <__aeabi_d2iz+0x30> + 8000b78: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000b7c: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000b80: d912 bls.n 8000ba8 <__aeabi_d2iz+0x3c> + 8000b82: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000b86: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000b8a: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000b8e: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000b92: fa23 f002 lsr.w r0, r3, r2 + 8000b96: bf18 it ne + 8000b98: 4240 negne r0, r0 + 8000b9a: 4770 bx lr + 8000b9c: f04f 0000 mov.w r0, #0 + 8000ba0: 4770 bx lr + 8000ba2: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000ba6: d105 bne.n 8000bb4 <__aeabi_d2iz+0x48> + 8000ba8: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000bac: bf08 it eq + 8000bae: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000bb2: 4770 bx lr + 8000bb4: f04f 0000 mov.w r0, #0 + 8000bb8: 4770 bx lr + 8000bba: bf00 nop + +08000bbc <__aeabi_d2uiz>: + 8000bbc: 004a lsls r2, r1, #1 + 8000bbe: d211 bcs.n 8000be4 <__aeabi_d2uiz+0x28> + 8000bc0: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000bc4: d211 bcs.n 8000bea <__aeabi_d2uiz+0x2e> + 8000bc6: d50d bpl.n 8000be4 <__aeabi_d2uiz+0x28> + 8000bc8: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000bcc: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000bd0: d40e bmi.n 8000bf0 <__aeabi_d2uiz+0x34> + 8000bd2: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000bd6: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000bda: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000bde: fa23 f002 lsr.w r0, r3, r2 + 8000be2: 4770 bx lr + 8000be4: f04f 0000 mov.w r0, #0 + 8000be8: 4770 bx lr + 8000bea: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000bee: d102 bne.n 8000bf6 <__aeabi_d2uiz+0x3a> + 8000bf0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8000bf4: 4770 bx lr + 8000bf6: f04f 0000 mov.w r0, #0 + 8000bfa: 4770 bx lr + +08000bfc <__aeabi_uldivmod>: + 8000bfc: b953 cbnz r3, 8000c14 <__aeabi_uldivmod+0x18> + 8000bfe: b94a cbnz r2, 8000c14 <__aeabi_uldivmod+0x18> + 8000c00: 2900 cmp r1, #0 + 8000c02: bf08 it eq + 8000c04: 2800 cmpeq r0, #0 + 8000c06: bf1c itt ne + 8000c08: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 8000c0c: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 8000c10: f000 b974 b.w 8000efc <__aeabi_idiv0> + 8000c14: f1ad 0c08 sub.w ip, sp, #8 + 8000c18: e96d ce04 strd ip, lr, [sp, #-16]! + 8000c1c: f000 f806 bl 8000c2c <__udivmoddi4> + 8000c20: f8dd e004 ldr.w lr, [sp, #4] + 8000c24: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000c28: b004 add sp, #16 + 8000c2a: 4770 bx lr + +08000c2c <__udivmoddi4>: + 8000c2c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000c30: 9d08 ldr r5, [sp, #32] + 8000c32: 4604 mov r4, r0 + 8000c34: 468e mov lr, r1 + 8000c36: 2b00 cmp r3, #0 + 8000c38: d14d bne.n 8000cd6 <__udivmoddi4+0xaa> + 8000c3a: 428a cmp r2, r1 + 8000c3c: 4694 mov ip, r2 + 8000c3e: d969 bls.n 8000d14 <__udivmoddi4+0xe8> + 8000c40: fab2 f282 clz r2, r2 + 8000c44: b152 cbz r2, 8000c5c <__udivmoddi4+0x30> + 8000c46: fa01 f302 lsl.w r3, r1, r2 + 8000c4a: f1c2 0120 rsb r1, r2, #32 + 8000c4e: fa20 f101 lsr.w r1, r0, r1 + 8000c52: fa0c fc02 lsl.w ip, ip, r2 + 8000c56: ea41 0e03 orr.w lr, r1, r3 + 8000c5a: 4094 lsls r4, r2 + 8000c5c: ea4f 481c mov.w r8, ip, lsr #16 + 8000c60: 0c21 lsrs r1, r4, #16 + 8000c62: fbbe f6f8 udiv r6, lr, r8 + 8000c66: fa1f f78c uxth.w r7, ip + 8000c6a: fb08 e316 mls r3, r8, r6, lr + 8000c6e: ea41 4303 orr.w r3, r1, r3, lsl #16 + 8000c72: fb06 f107 mul.w r1, r6, r7 + 8000c76: 4299 cmp r1, r3 + 8000c78: d90a bls.n 8000c90 <__udivmoddi4+0x64> + 8000c7a: eb1c 0303 adds.w r3, ip, r3 + 8000c7e: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff + 8000c82: f080 811f bcs.w 8000ec4 <__udivmoddi4+0x298> + 8000c86: 4299 cmp r1, r3 + 8000c88: f240 811c bls.w 8000ec4 <__udivmoddi4+0x298> + 8000c8c: 3e02 subs r6, #2 + 8000c8e: 4463 add r3, ip + 8000c90: 1a5b subs r3, r3, r1 + 8000c92: b2a4 uxth r4, r4 + 8000c94: fbb3 f0f8 udiv r0, r3, r8 + 8000c98: fb08 3310 mls r3, r8, r0, r3 + 8000c9c: ea44 4403 orr.w r4, r4, r3, lsl #16 + 8000ca0: fb00 f707 mul.w r7, r0, r7 + 8000ca4: 42a7 cmp r7, r4 + 8000ca6: d90a bls.n 8000cbe <__udivmoddi4+0x92> + 8000ca8: eb1c 0404 adds.w r4, ip, r4 + 8000cac: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8000cb0: f080 810a bcs.w 8000ec8 <__udivmoddi4+0x29c> + 8000cb4: 42a7 cmp r7, r4 + 8000cb6: f240 8107 bls.w 8000ec8 <__udivmoddi4+0x29c> + 8000cba: 4464 add r4, ip + 8000cbc: 3802 subs r0, #2 + 8000cbe: ea40 4006 orr.w r0, r0, r6, lsl #16 + 8000cc2: 1be4 subs r4, r4, r7 + 8000cc4: 2600 movs r6, #0 + 8000cc6: b11d cbz r5, 8000cd0 <__udivmoddi4+0xa4> + 8000cc8: 40d4 lsrs r4, r2 + 8000cca: 2300 movs r3, #0 + 8000ccc: e9c5 4300 strd r4, r3, [r5] + 8000cd0: 4631 mov r1, r6 + 8000cd2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000cd6: 428b cmp r3, r1 + 8000cd8: d909 bls.n 8000cee <__udivmoddi4+0xc2> + 8000cda: 2d00 cmp r5, #0 + 8000cdc: f000 80ef beq.w 8000ebe <__udivmoddi4+0x292> + 8000ce0: 2600 movs r6, #0 + 8000ce2: e9c5 0100 strd r0, r1, [r5] + 8000ce6: 4630 mov r0, r6 + 8000ce8: 4631 mov r1, r6 + 8000cea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000cee: fab3 f683 clz r6, r3 + 8000cf2: 2e00 cmp r6, #0 + 8000cf4: d14a bne.n 8000d8c <__udivmoddi4+0x160> + 8000cf6: 428b cmp r3, r1 + 8000cf8: d302 bcc.n 8000d00 <__udivmoddi4+0xd4> + 8000cfa: 4282 cmp r2, r0 + 8000cfc: f200 80f9 bhi.w 8000ef2 <__udivmoddi4+0x2c6> + 8000d00: 1a84 subs r4, r0, r2 + 8000d02: eb61 0303 sbc.w r3, r1, r3 + 8000d06: 2001 movs r0, #1 + 8000d08: 469e mov lr, r3 + 8000d0a: 2d00 cmp r5, #0 + 8000d0c: d0e0 beq.n 8000cd0 <__udivmoddi4+0xa4> + 8000d0e: e9c5 4e00 strd r4, lr, [r5] + 8000d12: e7dd b.n 8000cd0 <__udivmoddi4+0xa4> + 8000d14: b902 cbnz r2, 8000d18 <__udivmoddi4+0xec> + 8000d16: deff udf #255 ; 0xff + 8000d18: fab2 f282 clz r2, r2 + 8000d1c: 2a00 cmp r2, #0 + 8000d1e: f040 8092 bne.w 8000e46 <__udivmoddi4+0x21a> + 8000d22: eba1 010c sub.w r1, r1, ip + 8000d26: ea4f 471c mov.w r7, ip, lsr #16 + 8000d2a: fa1f fe8c uxth.w lr, ip + 8000d2e: 2601 movs r6, #1 + 8000d30: 0c20 lsrs r0, r4, #16 + 8000d32: fbb1 f3f7 udiv r3, r1, r7 + 8000d36: fb07 1113 mls r1, r7, r3, r1 + 8000d3a: ea40 4101 orr.w r1, r0, r1, lsl #16 + 8000d3e: fb0e f003 mul.w r0, lr, r3 + 8000d42: 4288 cmp r0, r1 + 8000d44: d908 bls.n 8000d58 <__udivmoddi4+0x12c> + 8000d46: eb1c 0101 adds.w r1, ip, r1 + 8000d4a: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff + 8000d4e: d202 bcs.n 8000d56 <__udivmoddi4+0x12a> + 8000d50: 4288 cmp r0, r1 + 8000d52: f200 80cb bhi.w 8000eec <__udivmoddi4+0x2c0> + 8000d56: 4643 mov r3, r8 + 8000d58: 1a09 subs r1, r1, r0 + 8000d5a: b2a4 uxth r4, r4 + 8000d5c: fbb1 f0f7 udiv r0, r1, r7 + 8000d60: fb07 1110 mls r1, r7, r0, r1 + 8000d64: ea44 4401 orr.w r4, r4, r1, lsl #16 + 8000d68: fb0e fe00 mul.w lr, lr, r0 + 8000d6c: 45a6 cmp lr, r4 + 8000d6e: d908 bls.n 8000d82 <__udivmoddi4+0x156> + 8000d70: eb1c 0404 adds.w r4, ip, r4 + 8000d74: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff + 8000d78: d202 bcs.n 8000d80 <__udivmoddi4+0x154> + 8000d7a: 45a6 cmp lr, r4 + 8000d7c: f200 80bb bhi.w 8000ef6 <__udivmoddi4+0x2ca> + 8000d80: 4608 mov r0, r1 + 8000d82: eba4 040e sub.w r4, r4, lr + 8000d86: ea40 4003 orr.w r0, r0, r3, lsl #16 + 8000d8a: e79c b.n 8000cc6 <__udivmoddi4+0x9a> + 8000d8c: f1c6 0720 rsb r7, r6, #32 + 8000d90: 40b3 lsls r3, r6 + 8000d92: fa22 fc07 lsr.w ip, r2, r7 + 8000d96: ea4c 0c03 orr.w ip, ip, r3 + 8000d9a: fa20 f407 lsr.w r4, r0, r7 + 8000d9e: fa01 f306 lsl.w r3, r1, r6 + 8000da2: 431c orrs r4, r3 + 8000da4: 40f9 lsrs r1, r7 + 8000da6: ea4f 491c mov.w r9, ip, lsr #16 + 8000daa: fa00 f306 lsl.w r3, r0, r6 + 8000dae: fbb1 f8f9 udiv r8, r1, r9 + 8000db2: 0c20 lsrs r0, r4, #16 + 8000db4: fa1f fe8c uxth.w lr, ip + 8000db8: fb09 1118 mls r1, r9, r8, r1 + 8000dbc: ea40 4101 orr.w r1, r0, r1, lsl #16 + 8000dc0: fb08 f00e mul.w r0, r8, lr + 8000dc4: 4288 cmp r0, r1 + 8000dc6: fa02 f206 lsl.w r2, r2, r6 + 8000dca: d90b bls.n 8000de4 <__udivmoddi4+0x1b8> + 8000dcc: eb1c 0101 adds.w r1, ip, r1 + 8000dd0: f108 3aff add.w sl, r8, #4294967295 ; 0xffffffff + 8000dd4: f080 8088 bcs.w 8000ee8 <__udivmoddi4+0x2bc> + 8000dd8: 4288 cmp r0, r1 + 8000dda: f240 8085 bls.w 8000ee8 <__udivmoddi4+0x2bc> + 8000dde: f1a8 0802 sub.w r8, r8, #2 + 8000de2: 4461 add r1, ip + 8000de4: 1a09 subs r1, r1, r0 + 8000de6: b2a4 uxth r4, r4 + 8000de8: fbb1 f0f9 udiv r0, r1, r9 + 8000dec: fb09 1110 mls r1, r9, r0, r1 + 8000df0: ea44 4101 orr.w r1, r4, r1, lsl #16 + 8000df4: fb00 fe0e mul.w lr, r0, lr + 8000df8: 458e cmp lr, r1 + 8000dfa: d908 bls.n 8000e0e <__udivmoddi4+0x1e2> + 8000dfc: eb1c 0101 adds.w r1, ip, r1 + 8000e00: f100 34ff add.w r4, r0, #4294967295 ; 0xffffffff + 8000e04: d26c bcs.n 8000ee0 <__udivmoddi4+0x2b4> + 8000e06: 458e cmp lr, r1 + 8000e08: d96a bls.n 8000ee0 <__udivmoddi4+0x2b4> + 8000e0a: 3802 subs r0, #2 + 8000e0c: 4461 add r1, ip + 8000e0e: ea40 4008 orr.w r0, r0, r8, lsl #16 + 8000e12: fba0 9402 umull r9, r4, r0, r2 + 8000e16: eba1 010e sub.w r1, r1, lr + 8000e1a: 42a1 cmp r1, r4 + 8000e1c: 46c8 mov r8, r9 + 8000e1e: 46a6 mov lr, r4 + 8000e20: d356 bcc.n 8000ed0 <__udivmoddi4+0x2a4> + 8000e22: d053 beq.n 8000ecc <__udivmoddi4+0x2a0> + 8000e24: b15d cbz r5, 8000e3e <__udivmoddi4+0x212> + 8000e26: ebb3 0208 subs.w r2, r3, r8 + 8000e2a: eb61 010e sbc.w r1, r1, lr + 8000e2e: fa01 f707 lsl.w r7, r1, r7 + 8000e32: fa22 f306 lsr.w r3, r2, r6 + 8000e36: 40f1 lsrs r1, r6 + 8000e38: 431f orrs r7, r3 + 8000e3a: e9c5 7100 strd r7, r1, [r5] + 8000e3e: 2600 movs r6, #0 + 8000e40: 4631 mov r1, r6 + 8000e42: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000e46: f1c2 0320 rsb r3, r2, #32 + 8000e4a: 40d8 lsrs r0, r3 + 8000e4c: fa0c fc02 lsl.w ip, ip, r2 + 8000e50: fa21 f303 lsr.w r3, r1, r3 + 8000e54: 4091 lsls r1, r2 + 8000e56: 4301 orrs r1, r0 + 8000e58: ea4f 471c mov.w r7, ip, lsr #16 + 8000e5c: fa1f fe8c uxth.w lr, ip + 8000e60: fbb3 f0f7 udiv r0, r3, r7 + 8000e64: fb07 3610 mls r6, r7, r0, r3 + 8000e68: 0c0b lsrs r3, r1, #16 + 8000e6a: ea43 4306 orr.w r3, r3, r6, lsl #16 + 8000e6e: fb00 f60e mul.w r6, r0, lr + 8000e72: 429e cmp r6, r3 + 8000e74: fa04 f402 lsl.w r4, r4, r2 + 8000e78: d908 bls.n 8000e8c <__udivmoddi4+0x260> + 8000e7a: eb1c 0303 adds.w r3, ip, r3 + 8000e7e: f100 38ff add.w r8, r0, #4294967295 ; 0xffffffff + 8000e82: d22f bcs.n 8000ee4 <__udivmoddi4+0x2b8> + 8000e84: 429e cmp r6, r3 + 8000e86: d92d bls.n 8000ee4 <__udivmoddi4+0x2b8> + 8000e88: 3802 subs r0, #2 + 8000e8a: 4463 add r3, ip + 8000e8c: 1b9b subs r3, r3, r6 + 8000e8e: b289 uxth r1, r1 + 8000e90: fbb3 f6f7 udiv r6, r3, r7 + 8000e94: fb07 3316 mls r3, r7, r6, r3 + 8000e98: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000e9c: fb06 f30e mul.w r3, r6, lr + 8000ea0: 428b cmp r3, r1 + 8000ea2: d908 bls.n 8000eb6 <__udivmoddi4+0x28a> + 8000ea4: eb1c 0101 adds.w r1, ip, r1 + 8000ea8: f106 38ff add.w r8, r6, #4294967295 ; 0xffffffff + 8000eac: d216 bcs.n 8000edc <__udivmoddi4+0x2b0> + 8000eae: 428b cmp r3, r1 + 8000eb0: d914 bls.n 8000edc <__udivmoddi4+0x2b0> + 8000eb2: 3e02 subs r6, #2 + 8000eb4: 4461 add r1, ip + 8000eb6: 1ac9 subs r1, r1, r3 + 8000eb8: ea46 4600 orr.w r6, r6, r0, lsl #16 + 8000ebc: e738 b.n 8000d30 <__udivmoddi4+0x104> + 8000ebe: 462e mov r6, r5 + 8000ec0: 4628 mov r0, r5 + 8000ec2: e705 b.n 8000cd0 <__udivmoddi4+0xa4> + 8000ec4: 4606 mov r6, r0 + 8000ec6: e6e3 b.n 8000c90 <__udivmoddi4+0x64> + 8000ec8: 4618 mov r0, r3 + 8000eca: e6f8 b.n 8000cbe <__udivmoddi4+0x92> + 8000ecc: 454b cmp r3, r9 + 8000ece: d2a9 bcs.n 8000e24 <__udivmoddi4+0x1f8> + 8000ed0: ebb9 0802 subs.w r8, r9, r2 + 8000ed4: eb64 0e0c sbc.w lr, r4, ip + 8000ed8: 3801 subs r0, #1 + 8000eda: e7a3 b.n 8000e24 <__udivmoddi4+0x1f8> + 8000edc: 4646 mov r6, r8 + 8000ede: e7ea b.n 8000eb6 <__udivmoddi4+0x28a> + 8000ee0: 4620 mov r0, r4 + 8000ee2: e794 b.n 8000e0e <__udivmoddi4+0x1e2> + 8000ee4: 4640 mov r0, r8 + 8000ee6: e7d1 b.n 8000e8c <__udivmoddi4+0x260> + 8000ee8: 46d0 mov r8, sl + 8000eea: e77b b.n 8000de4 <__udivmoddi4+0x1b8> + 8000eec: 3b02 subs r3, #2 + 8000eee: 4461 add r1, ip + 8000ef0: e732 b.n 8000d58 <__udivmoddi4+0x12c> + 8000ef2: 4630 mov r0, r6 + 8000ef4: e709 b.n 8000d0a <__udivmoddi4+0xde> + 8000ef6: 4464 add r4, ip + 8000ef8: 3802 subs r0, #2 + 8000efa: e742 b.n 8000d82 <__udivmoddi4+0x156> + +08000efc <__aeabi_idiv0>: + 8000efc: 4770 bx lr + 8000efe: bf00 nop + +08000f00 : + void *ptr1; + void *ptr2; +} ptrArray_t; + +uint32_t NTPToEpochUnix(void) +{ + 8000f00: b580 push {r7, lr} + 8000f02: b086 sub sp, #24 + 8000f04: af00 add r7, sp, #0 + uint32_t secsSince1900 = 0UL; + 8000f06: 2300 movs r3, #0 + 8000f08: 60bb str r3, [r7, #8] + ip_addr_t NTP_SERVER_IP; + err_t ret; + struct udp_pcb *udp_pcb; + struct pbuf *pbuf; + NTPState = NTP_IDLE; + 8000f0a: 4b57 ldr r3, [pc, #348] ; (8001068 ) + 8000f0c: 2200 movs r2, #0 + 8000f0e: 701a strb r2, [r3, #0] + debugln("Getting NTP"); + 8000f10: 4856 ldr r0, [pc, #344] ; (800106c ) + 8000f12: f01b f905 bl 801c120 + while (NTPState != NTP_GOT_TIME) + 8000f16: e08a b.n 800102e + { + switch (NTPState) + 8000f18: 4b53 ldr r3, [pc, #332] ; (8001068 ) + 8000f1a: 781b ldrb r3, [r3, #0] + 8000f1c: 2b05 cmp r3, #5 + 8000f1e: f200 8083 bhi.w 8001028 + 8000f22: a201 add r2, pc, #4 ; (adr r2, 8000f28 ) + 8000f24: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8000f28: 08000f41 .word 0x08000f41 + 8000f2c: 08001029 .word 0x08001029 + 8000f30: 08000f83 .word 0x08000f83 + 8000f34: 08001029 .word 0x08001029 + 8000f38: 08001029 .word 0x08001029 + 8000f3c: 08001013 .word 0x08001013 + { + case NTP_IDLE: + ret = dns_gethostbyname(NTP_HOST_NAME, &NTP_SERVER_IP, NTP_DNS_Callback, + 8000f40: 1d3b adds r3, r7, #4 + 8000f42: 1d39 adds r1, r7, #4 + 8000f44: 4a4a ldr r2, [pc, #296] ; (8001070 ) + 8000f46: 484b ldr r0, [pc, #300] ; (8001074 ) + 8000f48: f00e f930 bl 800f1ac + 8000f4c: 4603 mov r3, r0 + 8000f4e: 73fb strb r3, [r7, #15] + &NTP_SERVER_IP); + if (ret == ERR_OK) + 8000f50: f997 300f ldrsb.w r3, [r7, #15] + 8000f54: 2b00 cmp r3, #0 + 8000f56: d103 bne.n 8000f60 + { + NTPState = NTP_DNS_GOT_IP; + 8000f58: 4b43 ldr r3, [pc, #268] ; (8001068 ) + 8000f5a: 2202 movs r2, #2 + 8000f5c: 701a strb r2, [r3, #0] + else + { + debugErrln("Error while getting NTP server IP: %d", ret); + return 0; + } + break; + 8000f5e: e063 b.n 8001028 + else if (ret == ERR_INPROGRESS) + 8000f60: f997 300f ldrsb.w r3, [r7, #15] + 8000f64: f113 0f05 cmn.w r3, #5 + 8000f68: d103 bne.n 8000f72 + NTPState = NTP_Receiving_DNS; + 8000f6a: 4b3f ldr r3, [pc, #252] ; (8001068 ) + 8000f6c: 2201 movs r2, #1 + 8000f6e: 701a strb r2, [r3, #0] + break; + 8000f70: e05a b.n 8001028 + debugErrln("Error while getting NTP server IP: %d", ret); + 8000f72: f997 300f ldrsb.w r3, [r7, #15] + 8000f76: 4619 mov r1, r3 + 8000f78: 483f ldr r0, [pc, #252] ; (8001078 ) + 8000f7a: f01b f84b bl 801c014 + return 0; + 8000f7e: 2300 movs r3, #0 + 8000f80: e06d b.n 800105e + case NTP_Receiving_DNS: + break; + case NTP_DNS_GOT_IP: + pbuf = pbuf_alloc(PBUF_TRANSPORT, NTP_PACKET_SIZE, PBUF_RAM); + 8000f82: f44f 7220 mov.w r2, #640 ; 0x280 + 8000f86: 2130 movs r1, #48 ; 0x30 + 8000f88: 2036 movs r0, #54 ; 0x36 + 8000f8a: f00f fa55 bl 8010438 + 8000f8e: 6138 str r0, [r7, #16] + + if (pbuf == NULL) + 8000f90: 693b ldr r3, [r7, #16] + 8000f92: 2b00 cmp r3, #0 + 8000f94: d104 bne.n 8000fa0 + { + debugErrln("Error while allocating pbuf for NTP packet"); + 8000f96: 4839 ldr r0, [pc, #228] ; (800107c ) + 8000f98: f01b f8c2 bl 801c120 + return 0; + 8000f9c: 2300 movs r3, #0 + 8000f9e: e05e b.n 800105e + } + *((uint32_t*)pbuf->payload) = ntpFirstFourBytes; + 8000fa0: 693b ldr r3, [r7, #16] + 8000fa2: 685b ldr r3, [r3, #4] + 8000fa4: 4a36 ldr r2, [pc, #216] ; (8001080 ) + 8000fa6: 601a str r2, [r3, #0] + pbuf->len = NTP_PACKET_SIZE; + 8000fa8: 693b ldr r3, [r7, #16] + 8000faa: 2230 movs r2, #48 ; 0x30 + 8000fac: 815a strh r2, [r3, #10] + pbuf->tot_len = NTP_PACKET_SIZE; + 8000fae: 693b ldr r3, [r7, #16] + 8000fb0: 2230 movs r2, #48 ; 0x30 + 8000fb2: 811a strh r2, [r3, #8] + + udp_pcb = udp_new(); + 8000fb4: f016 f94c bl 8017250 + 8000fb8: 6178 str r0, [r7, #20] + + udp_connect(udp_pcb, &NTP_SERVER_IP, NTP_PORT); + 8000fba: 1d3b adds r3, r7, #4 + 8000fbc: 227b movs r2, #123 ; 0x7b + 8000fbe: 4619 mov r1, r3 + 8000fc0: 6978 ldr r0, [r7, #20] + 8000fc2: f016 f84d bl 8017060 + + (ret = udp_send(udp_pcb, pbuf)); + 8000fc6: 6939 ldr r1, [r7, #16] + 8000fc8: 6978 ldr r0, [r7, #20] + 8000fca: f015 fdd7 bl 8016b7c + 8000fce: 4603 mov r3, r0 + 8000fd0: 73fb strb r3, [r7, #15] + if (ret != ERR_OK) + 8000fd2: f997 300f ldrsb.w r3, [r7, #15] + 8000fd6: 2b00 cmp r3, #0 + 8000fd8: d00d beq.n 8000ff6 + { + pbuf_free(pbuf); + 8000fda: 6938 ldr r0, [r7, #16] + 8000fdc: f00f fd10 bl 8010a00 + udp_remove(udp_pcb); + 8000fe0: 6978 ldr r0, [r7, #20] + 8000fe2: f016 f8f3 bl 80171cc + debugErrln("Error while sending NTP packet over UDP: %d", ret); + 8000fe6: f997 300f ldrsb.w r3, [r7, #15] + 8000fea: 4619 mov r1, r3 + 8000fec: 4825 ldr r0, [pc, #148] ; (8001084 ) + 8000fee: f01b f811 bl 801c014 + return 0; + 8000ff2: 2300 movs r3, #0 + 8000ff4: e033 b.n 800105e + } + + debugln("NTP packet sent"); + 8000ff6: 4824 ldr r0, [pc, #144] ; (8001088 ) + 8000ff8: f01b f892 bl 801c120 + + udp_recv(udp_pcb, NTP_RECV_CALLBACK, &secsSince1900); + 8000ffc: f107 0308 add.w r3, r7, #8 + 8001000: 461a mov r2, r3 + 8001002: 4922 ldr r1, [pc, #136] ; (800108c ) + 8001004: 6978 ldr r0, [r7, #20] + 8001006: f016 f8c1 bl 801718c + NTPState = NTP_Receiving_UDP; + 800100a: 4b17 ldr r3, [pc, #92] ; (8001068 ) + 800100c: 2203 movs r2, #3 + 800100e: 701a strb r2, [r3, #0] + break; + 8001010: e00a b.n 8001028 + case NTP_Receiving_UDP: + break; + case NTP_GOT_TIME: + break; + case NTP_ERROR: + pbuf_free(pbuf); + 8001012: 6938 ldr r0, [r7, #16] + 8001014: f00f fcf4 bl 8010a00 + udp_disconnect(udp_pcb); + 8001018: 6978 ldr r0, [r7, #20] + 800101a: f016 f88f bl 801713c + udp_remove(udp_pcb); + 800101e: 6978 ldr r0, [r7, #20] + 8001020: f016 f8d4 bl 80171cc + return 0; + 8001024: 2300 movs r3, #0 + 8001026: e01a b.n 800105e + } + vTaskDelay(10); + 8001028: 200a movs r0, #10 + 800102a: f00b fc87 bl 800c93c + while (NTPState != NTP_GOT_TIME) + 800102e: 4b0e ldr r3, [pc, #56] ; (8001068 ) + 8001030: 781b ldrb r3, [r3, #0] + 8001032: 2b04 cmp r3, #4 + 8001034: f47f af70 bne.w 8000f18 + } + udp_disconnect(udp_pcb); + 8001038: 6978 ldr r0, [r7, #20] + 800103a: f016 f87f bl 801713c + udp_remove(udp_pcb); + 800103e: 6978 ldr r0, [r7, #20] + 8001040: f016 f8c4 bl 80171cc + pbuf_free(pbuf); + 8001044: 6938 ldr r0, [r7, #16] + 8001046: f00f fcdb bl 8010a00 + debugln("epoch: %lu", secsSince1900 - SEVENTYYEARS); + 800104a: 68ba ldr r2, [r7, #8] + 800104c: 4b10 ldr r3, [pc, #64] ; (8001090 ) + 800104e: 4413 add r3, r2 + 8001050: 4619 mov r1, r3 + 8001052: 4810 ldr r0, [pc, #64] ; (8001094 ) + 8001054: f01a ffde bl 801c014 + return secsSince1900 - SEVENTYYEARS; + 8001058: 68ba ldr r2, [r7, #8] + 800105a: 4b0d ldr r3, [pc, #52] ; (8001090 ) + 800105c: 4413 add r3, r2 +} + 800105e: 4618 mov r0, r3 + 8001060: 3718 adds r7, #24 + 8001062: 46bd mov sp, r7 + 8001064: bd80 pop {r7, pc} + 8001066: bf00 nop + 8001068: 20000284 .word 0x20000284 + 800106c: 0801e448 .word 0x0801e448 + 8001070: 08001099 .word 0x08001099 + 8001074: 0801e460 .word 0x0801e460 + 8001078: 0801e470 .word 0x0801e470 + 800107c: 0801e4a0 .word 0x0801e4a0 + 8001080: ec0600e3 .word 0xec0600e3 + 8001084: 0801e4d4 .word 0x0801e4d4 + 8001088: 0801e50c .word 0x0801e50c + 800108c: 0800110d .word 0x0800110d + 8001090: 7c558180 .word 0x7c558180 + 8001094: 0801e528 .word 0x0801e528 + +08001098 : + +void NTP_DNS_Callback(const char *name, const ip_addr_t *ipaddr, + void *callback_arg) +{ + 8001098: b580 push {r7, lr} + 800109a: b084 sub sp, #16 + 800109c: af00 add r7, sp, #0 + 800109e: 60f8 str r0, [r7, #12] + 80010a0: 60b9 str r1, [r7, #8] + 80010a2: 607a str r2, [r7, #4] + if (ipaddr == NULL) + 80010a4: 68bb ldr r3, [r7, #8] + 80010a6: 2b00 cmp r3, #0 + 80010a8: d103 bne.n 80010b2 + { + debugErrln("NTP_DNS_Callback: returned and ip_addr_t ptr to NULL"); + 80010aa: 4813 ldr r0, [pc, #76] ; (80010f8 ) + 80010ac: f01b f838 bl 801c120 + return; + 80010b0: e01e b.n 80010f0 + } + if (strncmp(name, NTP_HOST_NAME, strlen(NTP_HOST_NAME)) == 0) + 80010b2: 220c movs r2, #12 + 80010b4: 4911 ldr r1, [pc, #68] ; (80010fc ) + 80010b6: 68f8 ldr r0, [r7, #12] + 80010b8: f01b f955 bl 801c366 + 80010bc: 4603 mov r3, r0 + 80010be: 2b00 cmp r3, #0 + 80010c0: d110 bne.n 80010e4 + { + *((ip_addr_t *)callback_arg) = *ipaddr; + 80010c2: 687b ldr r3, [r7, #4] + 80010c4: 68ba ldr r2, [r7, #8] + 80010c6: 6812 ldr r2, [r2, #0] + 80010c8: 601a str r2, [r3, #0] + debugln("%s: %s", name, ip4addr_ntoa((ip_addr_t *)callback_arg)); + 80010ca: 6878 ldr r0, [r7, #4] + 80010cc: f019 fcf6 bl 801aabc + 80010d0: 4603 mov r3, r0 + 80010d2: 461a mov r2, r3 + 80010d4: 68f9 ldr r1, [r7, #12] + 80010d6: 480a ldr r0, [pc, #40] ; (8001100 ) + 80010d8: f01a ff9c bl 801c014 + NTPState = NTP_DNS_GOT_IP; + 80010dc: 4b09 ldr r3, [pc, #36] ; (8001104 ) + 80010de: 2202 movs r2, #2 + 80010e0: 701a strb r2, [r3, #0] + return; + 80010e2: e005 b.n 80010f0 + } + debugErrln("NTP_DNS_Callback: No DNS resolved"); + 80010e4: 4808 ldr r0, [pc, #32] ; (8001108 ) + 80010e6: f01b f81b bl 801c120 + NTPState = NTP_ERROR; + 80010ea: 4b06 ldr r3, [pc, #24] ; (8001104 ) + 80010ec: 2205 movs r2, #5 + 80010ee: 701a strb r2, [r3, #0] +} + 80010f0: 3710 adds r7, #16 + 80010f2: 46bd mov sp, r7 + 80010f4: bd80 pop {r7, pc} + 80010f6: bf00 nop + 80010f8: 0801e540 .word 0x0801e540 + 80010fc: 0801e460 .word 0x0801e460 + 8001100: 0801e580 .word 0x0801e580 + 8001104: 20000284 .word 0x20000284 + 8001108: 0801e594 .word 0x0801e594 + +0800110c : + +void NTP_RECV_CALLBACK(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + 800110c: b580 push {r7, lr} + 800110e: b086 sub sp, #24 + 8001110: af00 add r7, sp, #0 + 8001112: 60f8 str r0, [r7, #12] + 8001114: 60b9 str r1, [r7, #8] + 8001116: 607a str r2, [r7, #4] + 8001118: 603b str r3, [r7, #0] + uint32_t secsSince1900 = 0UL; + 800111a: 2300 movs r3, #0 + 800111c: 617b str r3, [r7, #20] + + /* process the response */ + if (p->tot_len != NTP_PACKET_SIZE) + 800111e: 687b ldr r3, [r7, #4] + 8001120: 891b ldrh r3, [r3, #8] + 8001122: 2b30 cmp r3, #48 ; 0x30 + 8001124: d009 beq.n 800113a + { + pbuf_free(p); + 8001126: 6878 ldr r0, [r7, #4] + 8001128: f00f fc6a bl 8010a00 + debugErrln("NTP_RECV_CALLBACK: invalid packet size: %d", p->tot_len); + 800112c: 687b ldr r3, [r7, #4] + 800112e: 891b ldrh r3, [r3, #8] + 8001130: 4619 mov r1, r3 + 8001132: 4817 ldr r0, [pc, #92] ; (8001190 ) + 8001134: f01a ff6e bl 801c014 + return; + 8001138: e026 b.n 8001188 + } + /* this is a SNTP response... */ + for (int i = NTP_OFFSET_TIMESTAMPS; i < NTP_OFFSET_TIMESTAMPS + sizeof(uint32_t); i++) + 800113a: 2328 movs r3, #40 ; 0x28 + 800113c: 613b str r3, [r7, #16] + 800113e: e00b b.n 8001158 + { + secsSince1900 = (secsSince1900 << 8) + ((uint8_t*)(p->payload))[i]; + 8001140: 697b ldr r3, [r7, #20] + 8001142: 021b lsls r3, r3, #8 + 8001144: 687a ldr r2, [r7, #4] + 8001146: 6851 ldr r1, [r2, #4] + 8001148: 693a ldr r2, [r7, #16] + 800114a: 440a add r2, r1 + 800114c: 7812 ldrb r2, [r2, #0] + 800114e: 4413 add r3, r2 + 8001150: 617b str r3, [r7, #20] + for (int i = NTP_OFFSET_TIMESTAMPS; i < NTP_OFFSET_TIMESTAMPS + sizeof(uint32_t); i++) + 8001152: 693b ldr r3, [r7, #16] + 8001154: 3301 adds r3, #1 + 8001156: 613b str r3, [r7, #16] + 8001158: 693b ldr r3, [r7, #16] + 800115a: 2b2b cmp r3, #43 ; 0x2b + 800115c: d9f0 bls.n 8001140 + } + + secsSince1900 += (((uint8_t*)(p->payload))[NTP_OFFSET_ROUNDING] > SECONDROUNDINGTHRESHOLD ? 1 : 0); + 800115e: 687b ldr r3, [r7, #4] + 8001160: 685b ldr r3, [r3, #4] + 8001162: 332c adds r3, #44 ; 0x2c + 8001164: 781b ldrb r3, [r3, #0] + 8001166: 2b73 cmp r3, #115 ; 0x73 + 8001168: d901 bls.n 800116e + 800116a: 2301 movs r3, #1 + 800116c: e000 b.n 8001170 + 800116e: 2300 movs r3, #0 + 8001170: 697a ldr r2, [r7, #20] + 8001172: 4413 add r3, r2 + 8001174: 617b str r3, [r7, #20] + + NTPState = NTP_GOT_TIME; + 8001176: 4b07 ldr r3, [pc, #28] ; (8001194 ) + 8001178: 2204 movs r2, #4 + 800117a: 701a strb r2, [r3, #0] + pbuf_free(p); + 800117c: 6878 ldr r0, [r7, #4] + 800117e: f00f fc3f bl 8010a00 + *((uint32_t *)arg) = secsSince1900; + 8001182: 68fb ldr r3, [r7, #12] + 8001184: 697a ldr r2, [r7, #20] + 8001186: 601a str r2, [r3, #0] +} + 8001188: 3718 adds r7, #24 + 800118a: 46bd mov sp, r7 + 800118c: bd80 pop {r7, pc} + 800118e: bf00 nop + 8001190: 0801e5c0 .word 0x0801e5c0 + 8001194: 20000284 .word 0x20000284 + +08001198 : +#include "RTC.h" + +extern RTC_HandleTypeDef hrtc; + +void Set_Time (RTC_TimeTypeDef sTime, RTC_DateTypeDef sDate) +{ + 8001198: b084 sub sp, #16 + 800119a: b580 push {r7, lr} + 800119c: af00 add r7, sp, #0 + 800119e: f107 0c08 add.w ip, r7, #8 + 80011a2: e88c 000f stmia.w ip, {r0, r1, r2, r3} + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) + 80011a6: 2200 movs r2, #0 + 80011a8: f107 0108 add.w r1, r7, #8 + 80011ac: 4812 ldr r0, [pc, #72] ; (80011f8 ) + 80011ae: f007 fd6d bl 8008c8c + 80011b2: 4603 mov r3, r0 + 80011b4: 2b00 cmp r3, #0 + 80011b6: d004 beq.n 80011c2 + { + debugErrln("%s:%d Error putting the time in the RTC", __FILE__, __LINE__); + 80011b8: 2209 movs r2, #9 + 80011ba: 4910 ldr r1, [pc, #64] ; (80011fc ) + 80011bc: 4810 ldr r0, [pc, #64] ; (8001200 ) + 80011be: f01a ff29 bl 801c014 + } + + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) + 80011c2: f107 031c add.w r3, r7, #28 + 80011c6: 2200 movs r2, #0 + 80011c8: 4619 mov r1, r3 + 80011ca: 480b ldr r0, [pc, #44] ; (80011f8 ) + 80011cc: f007 fe56 bl 8008e7c + 80011d0: 4603 mov r3, r0 + 80011d2: 2b00 cmp r3, #0 + 80011d4: d004 beq.n 80011e0 + { + debugErrln("%s:%d Error putting the date in the RTC", __FILE__, __LINE__); + 80011d6: 220e movs r2, #14 + 80011d8: 4908 ldr r1, [pc, #32] ; (80011fc ) + 80011da: 480a ldr r0, [pc, #40] ; (8001204 ) + 80011dc: f01a ff1a bl 801c014 + } + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_DR1, 0x32F2); // backup register just a random value + 80011e0: f243 22f2 movw r2, #13042 ; 0x32f2 + 80011e4: 2101 movs r1, #1 + 80011e6: 4804 ldr r0, [pc, #16] ; (80011f8 ) + 80011e8: f007 ffdc bl 80091a4 +} + 80011ec: bf00 nop + 80011ee: 46bd mov sp, r7 + 80011f0: e8bd 4080 ldmia.w sp!, {r7, lr} + 80011f4: b004 add sp, #16 + 80011f6: 4770 bx lr + 80011f8: 20000628 .word 0x20000628 + 80011fc: 0801e5f8 .word 0x0801e5f8 + 8001200: 0801e60c .word 0x0801e60c + 8001204: 0801e640 .word 0x0801e640 + +08001208 : + +void Get_Time(RTC_DateTypeDef* gDate, RTC_TimeTypeDef* gTime) +{ + 8001208: b580 push {r7, lr} + 800120a: b082 sub sp, #8 + 800120c: af00 add r7, sp, #0 + 800120e: 6078 str r0, [r7, #4] + 8001210: 6039 str r1, [r7, #0] +/* Get the RTC current Time */ + HAL_RTC_GetTime(&hrtc, gTime, RTC_FORMAT_BIN); + 8001212: 2200 movs r2, #0 + 8001214: 6839 ldr r1, [r7, #0] + 8001216: 4806 ldr r0, [pc, #24] ; (8001230 ) + 8001218: f007 fdd2 bl 8008dc0 +/* Get the RTC current Date */ + HAL_RTC_GetDate(&hrtc, gDate, RTC_FORMAT_BIN); + 800121c: 2200 movs r2, #0 + 800121e: 6879 ldr r1, [r7, #4] + 8001220: 4803 ldr r0, [pc, #12] ; (8001230 ) + 8001222: f007 feaf bl 8008f84 +} + 8001226: bf00 nop + 8001228: 3708 adds r7, #8 + 800122a: 46bd mov sp, r7 + 800122c: bd80 pop {r7, pc} + 800122e: bf00 nop + 8001230: 20000628 .word 0x20000628 + +08001234 : + +void Ts_To_RTC(ts* tm, RTC_TimeTypeDef* sTime, RTC_DateTypeDef* sDate) +{ + 8001234: b480 push {r7} + 8001236: b085 sub sp, #20 + 8001238: af00 add r7, sp, #0 + 800123a: 60f8 str r0, [r7, #12] + 800123c: 60b9 str r1, [r7, #8] + 800123e: 607a str r2, [r7, #4] + sTime->Hours = tm->Hour; + 8001240: 68fb ldr r3, [r7, #12] + 8001242: 789a ldrb r2, [r3, #2] + 8001244: 68bb ldr r3, [r7, #8] + 8001246: 701a strb r2, [r3, #0] + sTime->Minutes = tm->Minute; + 8001248: 68fb ldr r3, [r7, #12] + 800124a: 785a ldrb r2, [r3, #1] + 800124c: 68bb ldr r3, [r7, #8] + 800124e: 705a strb r2, [r3, #1] + sTime->Seconds = tm->Second; + 8001250: 68fb ldr r3, [r7, #12] + 8001252: 781a ldrb r2, [r3, #0] + 8001254: 68bb ldr r3, [r7, #8] + 8001256: 709a strb r2, [r3, #2] + sDate->Date = tm->Day; + 8001258: 68fb ldr r3, [r7, #12] + 800125a: 78da ldrb r2, [r3, #3] + 800125c: 687b ldr r3, [r7, #4] + 800125e: 709a strb r2, [r3, #2] + sDate->Month = tm->Month; + 8001260: 68fb ldr r3, [r7, #12] + 8001262: 791a ldrb r2, [r3, #4] + 8001264: 687b ldr r3, [r7, #4] + 8001266: 705a strb r2, [r3, #1] + sDate->Year = tm->Year; + 8001268: 68fb ldr r3, [r7, #12] + 800126a: f9b3 3006 ldrsh.w r3, [r3, #6] + 800126e: b2da uxtb r2, r3 + 8001270: 687b ldr r3, [r7, #4] + 8001272: 70da strb r2, [r3, #3] +} + 8001274: bf00 nop + 8001276: 3714 adds r7, #20 + 8001278: 46bd mov sp, r7 + 800127a: f85d 7b04 ldr.w r7, [sp], #4 + 800127e: 4770 bx lr + +08001280 : + +void RTC_To_Ts(RTC_TimeTypeDef* sTime, RTC_DateTypeDef* sDate, ts* tm) +{ + 8001280: b480 push {r7} + 8001282: b085 sub sp, #20 + 8001284: af00 add r7, sp, #0 + 8001286: 60f8 str r0, [r7, #12] + 8001288: 60b9 str r1, [r7, #8] + 800128a: 607a str r2, [r7, #4] + tm->Hour = sTime->Hours; + 800128c: 68fb ldr r3, [r7, #12] + 800128e: 781a ldrb r2, [r3, #0] + 8001290: 687b ldr r3, [r7, #4] + 8001292: 709a strb r2, [r3, #2] + tm->Minute = sTime->Minutes; + 8001294: 68fb ldr r3, [r7, #12] + 8001296: 785a ldrb r2, [r3, #1] + 8001298: 687b ldr r3, [r7, #4] + 800129a: 705a strb r2, [r3, #1] + tm->Second = sTime->Seconds; + 800129c: 68fb ldr r3, [r7, #12] + 800129e: 789a ldrb r2, [r3, #2] + 80012a0: 687b ldr r3, [r7, #4] + 80012a2: 701a strb r2, [r3, #0] + tm->Day = sDate->Date; + 80012a4: 68bb ldr r3, [r7, #8] + 80012a6: 789a ldrb r2, [r3, #2] + 80012a8: 687b ldr r3, [r7, #4] + 80012aa: 70da strb r2, [r3, #3] + tm->Month = sDate->Month; + 80012ac: 68bb ldr r3, [r7, #8] + 80012ae: 785a ldrb r2, [r3, #1] + 80012b0: 687b ldr r3, [r7, #4] + 80012b2: 711a strb r2, [r3, #4] + tm->Year = sDate->Year; + 80012b4: 68bb ldr r3, [r7, #8] + 80012b6: 78db ldrb r3, [r3, #3] + 80012b8: b21a sxth r2, r3 + 80012ba: 687b ldr r3, [r7, #4] + 80012bc: 80da strh r2, [r3, #6] +} + 80012be: bf00 nop + 80012c0: 3714 adds r7, #20 + 80012c2: 46bd mov sp, r7 + 80012c4: f85d 7b04 ldr.w r7, [sp], #4 + 80012c8: 4770 bx lr + ... + +080012cc : + * + * @param utc the time struct in UTC + * @return returns the value of utc->IsDST which is 0 if not in DST and 1 if in DST + */ +uint8_t IsDST(ts *utc) +{ + 80012cc: b480 push {r7} + 80012ce: b089 sub sp, #36 ; 0x24 + 80012d0: af00 add r7, sp, #0 + 80012d2: 6078 str r0, [r7, #4] + uint8_t nextSunday; + uint16_t y, m, d; + // number of days of each month + uint8_t days[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + 80012d4: 4a60 ldr r2, [pc, #384] ; (8001458 ) + 80012d6: f107 030c add.w r3, r7, #12 + 80012da: ca07 ldmia r2, {r0, r1, r2} + 80012dc: e883 0007 stmia.w r3, {r0, r1, r2} + + // November, December, January, february are out of DST. + if (utc->Month < 3 || utc->Month > 10) + 80012e0: 687b ldr r3, [r7, #4] + 80012e2: 791b ldrb r3, [r3, #4] + 80012e4: 2b02 cmp r3, #2 + 80012e6: d903 bls.n 80012f0 + 80012e8: 687b ldr r3, [r7, #4] + 80012ea: 791b ldrb r3, [r3, #4] + 80012ec: 2b0a cmp r3, #10 + 80012ee: d905 bls.n 80012fc + { + utc->IsDST = 0; + 80012f0: 687b ldr r3, [r7, #4] + 80012f2: 2200 movs r2, #0 + 80012f4: 729a strb r2, [r3, #10] + return utc->IsDST; + 80012f6: 687b ldr r3, [r7, #4] + 80012f8: 7a9b ldrb r3, [r3, #10] + 80012fa: e0a6 b.n 800144a + } + // April to september are in DST + if (utc->Month > 3 && utc->Month < 10) + 80012fc: 687b ldr r3, [r7, #4] + 80012fe: 791b ldrb r3, [r3, #4] + 8001300: 2b03 cmp r3, #3 + 8001302: d909 bls.n 8001318 + 8001304: 687b ldr r3, [r7, #4] + 8001306: 791b ldrb r3, [r3, #4] + 8001308: 2b09 cmp r3, #9 + 800130a: d805 bhi.n 8001318 + { + utc->IsDST = 1; + 800130c: 687b ldr r3, [r7, #4] + 800130e: 2201 movs r2, #1 + 8001310: 729a strb r2, [r3, #10] + return utc->IsDST; + 8001312: 687b ldr r3, [r7, #4] + 8001314: 7a9b ldrb r3, [r3, #10] + 8001316: e098 b.n 800144a + } + + m = utc->Month; + 8001318: 687b ldr r3, [r7, #4] + 800131a: 791b ldrb r3, [r3, #4] + 800131c: 83bb strh r3, [r7, #28] + y = utc->Year + 1970; + 800131e: 687b ldr r3, [r7, #4] + 8001320: f9b3 3006 ldrsh.w r3, [r3, #6] + 8001324: b29b uxth r3, r3 + 8001326: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 800132a: 83fb strh r3, [r7, #30] + days[1] -= (y % 4) || (!(y % 100) && (y % 400)); + 800132c: 7b7a ldrb r2, [r7, #13] + 800132e: 8bfb ldrh r3, [r7, #30] + 8001330: f003 0303 and.w r3, r3, #3 + 8001334: b29b uxth r3, r3 + 8001336: 2b00 cmp r3, #0 + 8001338: d118 bne.n 800136c + 800133a: 8bfb ldrh r3, [r7, #30] + 800133c: 4947 ldr r1, [pc, #284] ; (800145c ) + 800133e: fba1 0103 umull r0, r1, r1, r3 + 8001342: 0949 lsrs r1, r1, #5 + 8001344: 2064 movs r0, #100 ; 0x64 + 8001346: fb00 f101 mul.w r1, r0, r1 + 800134a: 1a5b subs r3, r3, r1 + 800134c: b29b uxth r3, r3 + 800134e: 2b00 cmp r3, #0 + 8001350: d10e bne.n 8001370 + 8001352: 8bfb ldrh r3, [r7, #30] + 8001354: 4941 ldr r1, [pc, #260] ; (800145c ) + 8001356: fba1 0103 umull r0, r1, r1, r3 + 800135a: 09c9 lsrs r1, r1, #7 + 800135c: f44f 70c8 mov.w r0, #400 ; 0x190 + 8001360: fb00 f101 mul.w r1, r0, r1 + 8001364: 1a5b subs r3, r3, r1 + 8001366: b29b uxth r3, r3 + 8001368: 2b00 cmp r3, #0 + 800136a: d001 beq.n 8001370 + 800136c: 2301 movs r3, #1 + 800136e: e000 b.n 8001372 + 8001370: 2300 movs r3, #0 + 8001372: b2db uxtb r3, r3 + 8001374: 1ad3 subs r3, r2, r3 + 8001376: b2db uxtb r3, r3 + 8001378: 737b strb r3, [r7, #13] + d = days[m - 1]; + 800137a: 8bbb ldrh r3, [r7, #28] + 800137c: 3b01 subs r3, #1 + 800137e: 3320 adds r3, #32 + 8001380: 443b add r3, r7 + 8001382: f813 3c14 ldrb.w r3, [r3, #-20] + 8001386: 837b strh r3, [r7, #26] + + // dow is in normal format + nextSunday = days[m - 1] - ((d += m < 3 ? y-- : y - 2, 23 * m / 9 + d + 4 + y / 4 - y / 100 + y / 400) % 7); + 8001388: 8bbb ldrh r3, [r7, #28] + 800138a: 2b02 cmp r3, #2 + 800138c: d803 bhi.n 8001396 + 800138e: 8bfb ldrh r3, [r7, #30] + 8001390: 1e5a subs r2, r3, #1 + 8001392: 83fa strh r2, [r7, #30] + 8001394: e001 b.n 800139a + 8001396: 8bfb ldrh r3, [r7, #30] + 8001398: 3b02 subs r3, #2 + 800139a: b29a uxth r2, r3 + 800139c: 8b7b ldrh r3, [r7, #26] + 800139e: 4413 add r3, r2 + 80013a0: 837b strh r3, [r7, #26] + 80013a2: 8bbb ldrh r3, [r7, #28] + 80013a4: 3b01 subs r3, #1 + 80013a6: 3320 adds r3, #32 + 80013a8: 443b add r3, r7 + 80013aa: f813 0c14 ldrb.w r0, [r3, #-20] + 80013ae: 8bba ldrh r2, [r7, #28] + 80013b0: 4613 mov r3, r2 + 80013b2: 005b lsls r3, r3, #1 + 80013b4: 4413 add r3, r2 + 80013b6: 00db lsls r3, r3, #3 + 80013b8: 1a9b subs r3, r3, r2 + 80013ba: 4a29 ldr r2, [pc, #164] ; (8001460 ) + 80013bc: fb82 1203 smull r1, r2, r2, r3 + 80013c0: 1052 asrs r2, r2, #1 + 80013c2: 17db asrs r3, r3, #31 + 80013c4: 1ad2 subs r2, r2, r3 + 80013c6: 8b7b ldrh r3, [r7, #26] + 80013c8: 4413 add r3, r2 + 80013ca: 3304 adds r3, #4 + 80013cc: 8bfa ldrh r2, [r7, #30] + 80013ce: 0892 lsrs r2, r2, #2 + 80013d0: b292 uxth r2, r2 + 80013d2: 4413 add r3, r2 + 80013d4: 8bfa ldrh r2, [r7, #30] + 80013d6: 4921 ldr r1, [pc, #132] ; (800145c ) + 80013d8: fba1 1202 umull r1, r2, r1, r2 + 80013dc: 0952 lsrs r2, r2, #5 + 80013de: b292 uxth r2, r2 + 80013e0: 1a9b subs r3, r3, r2 + 80013e2: 8bfa ldrh r2, [r7, #30] + 80013e4: 491d ldr r1, [pc, #116] ; (800145c ) + 80013e6: fba1 1202 umull r1, r2, r1, r2 + 80013ea: 09d2 lsrs r2, r2, #7 + 80013ec: b292 uxth r2, r2 + 80013ee: 441a add r2, r3 + 80013f0: 4b1c ldr r3, [pc, #112] ; (8001464 ) + 80013f2: fb83 1302 smull r1, r3, r3, r2 + 80013f6: 4413 add r3, r2 + 80013f8: 1099 asrs r1, r3, #2 + 80013fa: 17d3 asrs r3, r2, #31 + 80013fc: 1ac9 subs r1, r1, r3 + 80013fe: 460b mov r3, r1 + 8001400: 00db lsls r3, r3, #3 + 8001402: 1a5b subs r3, r3, r1 + 8001404: 1ad1 subs r1, r2, r3 + 8001406: b2cb uxtb r3, r1 + 8001408: 1ac3 subs r3, r0, r3 + 800140a: 767b strb r3, [r7, #25] + // Start: Last Sunday in March + if (utc->Month == 3) + 800140c: 687b ldr r3, [r7, #4] + 800140e: 791b ldrb r3, [r3, #4] + 8001410: 2b03 cmp r3, #3 + 8001412: d10d bne.n 8001430 + { + utc->IsDST = utc->Day >= nextSunday ? (utc->Day == nextSunday ? (utc->Hour >= 0) : 1) : 0; + 8001414: 687b ldr r3, [r7, #4] + 8001416: 78db ldrb r3, [r3, #3] + 8001418: 7e7a ldrb r2, [r7, #25] + 800141a: 429a cmp r2, r3 + 800141c: bf94 ite ls + 800141e: 2301 movls r3, #1 + 8001420: 2300 movhi r3, #0 + 8001422: b2db uxtb r3, r3 + 8001424: 461a mov r2, r3 + 8001426: 687b ldr r3, [r7, #4] + 8001428: 729a strb r2, [r3, #10] + return utc->IsDST; + 800142a: 687b ldr r3, [r7, #4] + 800142c: 7a9b ldrb r3, [r3, #10] + 800142e: e00c b.n 800144a + } + + // End: Last Sunday in October + utc->IsDST = utc->Day >= nextSunday ? (utc->Day == nextSunday ? (utc->Hour < 0) : 0) : 1; + 8001430: 687b ldr r3, [r7, #4] + 8001432: 78db ldrb r3, [r3, #3] + 8001434: 7e7a ldrb r2, [r7, #25] + 8001436: 429a cmp r2, r3 + 8001438: bf8c ite hi + 800143a: 2301 movhi r3, #1 + 800143c: 2300 movls r3, #0 + 800143e: b2db uxtb r3, r3 + 8001440: 461a mov r2, r3 + 8001442: 687b ldr r3, [r7, #4] + 8001444: 729a strb r2, [r3, #10] + return utc->IsDST; + 8001446: 687b ldr r3, [r7, #4] + 8001448: 7a9b ldrb r3, [r3, #10] +} + 800144a: 4618 mov r0, r3 + 800144c: 3724 adds r7, #36 ; 0x24 + 800144e: 46bd mov sp, r7 + 8001450: f85d 7b04 ldr.w r7, [sp], #4 + 8001454: 4770 bx lr + 8001456: bf00 nop + 8001458: 0801e674 .word 0x0801e674 + 800145c: 51eb851f .word 0x51eb851f + 8001460: 38e38e39 .word 0x38e38e39 + 8001464: 92492493 .word 0x92492493 + +08001468 : + * @param timeInput: epoch time + * @param time: the struct in which this function will return the datetime + * @param runIsDST: bool if it will run the IsDST function after this function completes + */ +void breakTime(uint32_t timeInput, ts *time, uint8_t runIsDST) +{ + 8001468: b580 push {r7, lr} + 800146a: b08a sub sp, #40 ; 0x28 + 800146c: af00 add r7, sp, #0 + 800146e: 60f8 str r0, [r7, #12] + 8001470: 60b9 str r1, [r7, #8] + 8001472: 4613 mov r3, r2 + 8001474: 71fb strb r3, [r7, #7] + // note that year is offset from 1970 !!! + + uint8_t year; + uint8_t month, monthLength; + unsigned long days; + uint8_t monthDays[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + 8001476: 4aa1 ldr r2, [pc, #644] ; (80016fc ) + 8001478: f107 0314 add.w r3, r7, #20 + 800147c: ca07 ldmia r2, {r0, r1, r2} + 800147e: e883 0007 stmia.w r3, {r0, r1, r2} + + time->unixtime = timeInput; + 8001482: 68bb ldr r3, [r7, #8] + 8001484: 68fa ldr r2, [r7, #12] + 8001486: 60da str r2, [r3, #12] + time->Second = timeInput % 60; + 8001488: 68f9 ldr r1, [r7, #12] + 800148a: 4b9d ldr r3, [pc, #628] ; (8001700 ) + 800148c: fba3 2301 umull r2, r3, r3, r1 + 8001490: 095a lsrs r2, r3, #5 + 8001492: 4613 mov r3, r2 + 8001494: 011b lsls r3, r3, #4 + 8001496: 1a9b subs r3, r3, r2 + 8001498: 009b lsls r3, r3, #2 + 800149a: 1aca subs r2, r1, r3 + 800149c: b2d2 uxtb r2, r2 + 800149e: 68bb ldr r3, [r7, #8] + 80014a0: 701a strb r2, [r3, #0] + timeInput /= 60; // now it is minutes + 80014a2: 68fb ldr r3, [r7, #12] + 80014a4: 4a96 ldr r2, [pc, #600] ; (8001700 ) + 80014a6: fba2 2303 umull r2, r3, r2, r3 + 80014aa: 095b lsrs r3, r3, #5 + 80014ac: 60fb str r3, [r7, #12] + time->Minute = timeInput % 60; + 80014ae: 68f9 ldr r1, [r7, #12] + 80014b0: 4b93 ldr r3, [pc, #588] ; (8001700 ) + 80014b2: fba3 2301 umull r2, r3, r3, r1 + 80014b6: 095a lsrs r2, r3, #5 + 80014b8: 4613 mov r3, r2 + 80014ba: 011b lsls r3, r3, #4 + 80014bc: 1a9b subs r3, r3, r2 + 80014be: 009b lsls r3, r3, #2 + 80014c0: 1aca subs r2, r1, r3 + 80014c2: b2d2 uxtb r2, r2 + 80014c4: 68bb ldr r3, [r7, #8] + 80014c6: 705a strb r2, [r3, #1] + timeInput /= 60; // now it is hours + 80014c8: 68fb ldr r3, [r7, #12] + 80014ca: 4a8d ldr r2, [pc, #564] ; (8001700 ) + 80014cc: fba2 2303 umull r2, r3, r2, r3 + 80014d0: 095b lsrs r3, r3, #5 + 80014d2: 60fb str r3, [r7, #12] + time->Hour = timeInput % 24; + 80014d4: 68f9 ldr r1, [r7, #12] + 80014d6: 4b8b ldr r3, [pc, #556] ; (8001704 ) + 80014d8: fba3 2301 umull r2, r3, r3, r1 + 80014dc: 091a lsrs r2, r3, #4 + 80014de: 4613 mov r3, r2 + 80014e0: 005b lsls r3, r3, #1 + 80014e2: 4413 add r3, r2 + 80014e4: 00db lsls r3, r3, #3 + 80014e6: 1aca subs r2, r1, r3 + 80014e8: b2d2 uxtb r2, r2 + 80014ea: 68bb ldr r3, [r7, #8] + 80014ec: 709a strb r2, [r3, #2] + timeInput /= 24; // now it is days + 80014ee: 68fb ldr r3, [r7, #12] + 80014f0: 4a84 ldr r2, [pc, #528] ; (8001704 ) + 80014f2: fba2 2303 umull r2, r3, r2, r3 + 80014f6: 091b lsrs r3, r3, #4 + 80014f8: 60fb str r3, [r7, #12] + time->Wday = ((timeInput + 4) % 7) + 1; // Sunday is day 1 + 80014fa: 68fb ldr r3, [r7, #12] + 80014fc: 1d1a adds r2, r3, #4 + 80014fe: 4b82 ldr r3, [pc, #520] ; (8001708 ) + 8001500: fba3 1302 umull r1, r3, r3, r2 + 8001504: 1ad1 subs r1, r2, r3 + 8001506: 0849 lsrs r1, r1, #1 + 8001508: 440b add r3, r1 + 800150a: 0899 lsrs r1, r3, #2 + 800150c: 460b mov r3, r1 + 800150e: 00db lsls r3, r3, #3 + 8001510: 1a5b subs r3, r3, r1 + 8001512: 1ad1 subs r1, r2, r3 + 8001514: b2cb uxtb r3, r1 + 8001516: 3301 adds r3, #1 + 8001518: b2da uxtb r2, r3 + 800151a: 68bb ldr r3, [r7, #8] + 800151c: 721a strb r2, [r3, #8] + + year = 0; + 800151e: 2300 movs r3, #0 + 8001520: f887 3027 strb.w r3, [r7, #39] ; 0x27 + days = 0; + 8001524: 2300 movs r3, #0 + 8001526: 623b str r3, [r7, #32] + while ((unsigned)(days += (LEAP_YEAR(year) ? 366 : 365)) <= timeInput) + 8001528: e004 b.n 8001534 + { + year++; + 800152a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800152e: 3301 adds r3, #1 + 8001530: f887 3027 strb.w r3, [r7, #39] ; 0x27 + while ((unsigned)(days += (LEAP_YEAR(year) ? 366 : 365)) <= timeInput) + 8001534: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001538: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 800153c: f003 0303 and.w r3, r3, #3 + 8001540: 2b00 cmp r3, #0 + 8001542: d123 bne.n 800158c + 8001544: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001548: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800154c: 4b6f ldr r3, [pc, #444] ; (800170c ) + 800154e: fb83 1302 smull r1, r3, r3, r2 + 8001552: 1159 asrs r1, r3, #5 + 8001554: 17d3 asrs r3, r2, #31 + 8001556: 1acb subs r3, r1, r3 + 8001558: 2164 movs r1, #100 ; 0x64 + 800155a: fb01 f303 mul.w r3, r1, r3 + 800155e: 1ad3 subs r3, r2, r3 + 8001560: 2b00 cmp r3, #0 + 8001562: d110 bne.n 8001586 + 8001564: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001568: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800156c: 4b67 ldr r3, [pc, #412] ; (800170c ) + 800156e: fb83 1302 smull r1, r3, r3, r2 + 8001572: 11d9 asrs r1, r3, #7 + 8001574: 17d3 asrs r3, r2, #31 + 8001576: 1acb subs r3, r1, r3 + 8001578: f44f 71c8 mov.w r1, #400 ; 0x190 + 800157c: fb01 f303 mul.w r3, r1, r3 + 8001580: 1ad3 subs r3, r2, r3 + 8001582: 2b00 cmp r3, #0 + 8001584: d102 bne.n 800158c + 8001586: f44f 73b7 mov.w r3, #366 ; 0x16e + 800158a: e001 b.n 8001590 + 800158c: f240 136d movw r3, #365 ; 0x16d + 8001590: 6a3a ldr r2, [r7, #32] + 8001592: 4413 add r3, r2 + 8001594: 623b str r3, [r7, #32] + 8001596: 6a3a ldr r2, [r7, #32] + 8001598: 68fb ldr r3, [r7, #12] + 800159a: 429a cmp r2, r3 + 800159c: d9c5 bls.n 800152a + } + time->Year = year; // year is offset from 1970 + 800159e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80015a2: b21a sxth r2, r3 + 80015a4: 68bb ldr r3, [r7, #8] + 80015a6: 80da strh r2, [r3, #6] + + days -= LEAP_YEAR(year) ? 366 : 365; + 80015a8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80015ac: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 80015b0: f003 0303 and.w r3, r3, #3 + 80015b4: 2b00 cmp r3, #0 + 80015b6: d123 bne.n 8001600 + 80015b8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80015bc: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 80015c0: 4b52 ldr r3, [pc, #328] ; (800170c ) + 80015c2: fb83 1302 smull r1, r3, r3, r2 + 80015c6: 1159 asrs r1, r3, #5 + 80015c8: 17d3 asrs r3, r2, #31 + 80015ca: 1acb subs r3, r1, r3 + 80015cc: 2164 movs r1, #100 ; 0x64 + 80015ce: fb01 f303 mul.w r3, r1, r3 + 80015d2: 1ad3 subs r3, r2, r3 + 80015d4: 2b00 cmp r3, #0 + 80015d6: d110 bne.n 80015fa + 80015d8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80015dc: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 80015e0: 4b4a ldr r3, [pc, #296] ; (800170c ) + 80015e2: fb83 1302 smull r1, r3, r3, r2 + 80015e6: 11d9 asrs r1, r3, #7 + 80015e8: 17d3 asrs r3, r2, #31 + 80015ea: 1acb subs r3, r1, r3 + 80015ec: f44f 71c8 mov.w r1, #400 ; 0x190 + 80015f0: fb01 f303 mul.w r3, r1, r3 + 80015f4: 1ad3 subs r3, r2, r3 + 80015f6: 2b00 cmp r3, #0 + 80015f8: d102 bne.n 8001600 + 80015fa: f44f 73b7 mov.w r3, #366 ; 0x16e + 80015fe: e001 b.n 8001604 + 8001600: f240 136d movw r3, #365 ; 0x16d + 8001604: 6a3a ldr r2, [r7, #32] + 8001606: 1ad3 subs r3, r2, r3 + 8001608: 623b str r3, [r7, #32] + timeInput -= days; // now it is days in this year, starting at 0 + 800160a: 68fa ldr r2, [r7, #12] + 800160c: 6a3b ldr r3, [r7, #32] + 800160e: 1ad3 subs r3, r2, r3 + 8001610: 60fb str r3, [r7, #12] + + days = 0; + 8001612: 2300 movs r3, #0 + 8001614: 623b str r3, [r7, #32] + month = 0; + 8001616: 2300 movs r3, #0 + 8001618: f887 3026 strb.w r3, [r7, #38] ; 0x26 + monthLength = 0; + 800161c: 2300 movs r3, #0 + 800161e: f887 3025 strb.w r3, [r7, #37] ; 0x25 + for (month = 0; month < 12; month++) + 8001622: 2300 movs r3, #0 + 8001624: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8001628: e04b b.n 80016c2 + { + if (month == 1) + 800162a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800162e: 2b01 cmp r3, #1 + 8001630: d130 bne.n 8001694 + { // february + if (LEAP_YEAR(year)) + 8001632: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001636: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 800163a: f003 0303 and.w r3, r3, #3 + 800163e: 2b00 cmp r3, #0 + 8001640: d124 bne.n 800168c + 8001642: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001646: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800164a: 4b30 ldr r3, [pc, #192] ; (800170c ) + 800164c: fb83 1302 smull r1, r3, r3, r2 + 8001650: 1159 asrs r1, r3, #5 + 8001652: 17d3 asrs r3, r2, #31 + 8001654: 1acb subs r3, r1, r3 + 8001656: 2164 movs r1, #100 ; 0x64 + 8001658: fb01 f303 mul.w r3, r1, r3 + 800165c: 1ad3 subs r3, r2, r3 + 800165e: 2b00 cmp r3, #0 + 8001660: d110 bne.n 8001684 + 8001662: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001666: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800166a: 4b28 ldr r3, [pc, #160] ; (800170c ) + 800166c: fb83 1302 smull r1, r3, r3, r2 + 8001670: 11d9 asrs r1, r3, #7 + 8001672: 17d3 asrs r3, r2, #31 + 8001674: 1acb subs r3, r1, r3 + 8001676: f44f 71c8 mov.w r1, #400 ; 0x190 + 800167a: fb01 f303 mul.w r3, r1, r3 + 800167e: 1ad3 subs r3, r2, r3 + 8001680: 2b00 cmp r3, #0 + 8001682: d103 bne.n 800168c + { + monthLength = 29; + 8001684: 231d movs r3, #29 + 8001686: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 800168a: e00b b.n 80016a4 + } + else + { + monthLength = 28; + 800168c: 231c movs r3, #28 + 800168e: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 8001692: e007 b.n 80016a4 + } + } + else + { + monthLength = monthDays[month]; + 8001694: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8001698: 3328 adds r3, #40 ; 0x28 + 800169a: 443b add r3, r7 + 800169c: f813 3c14 ldrb.w r3, [r3, #-20] + 80016a0: f887 3025 strb.w r3, [r7, #37] ; 0x25 + } + + if (timeInput >= monthLength) + 80016a4: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 + 80016a8: 68fa ldr r2, [r7, #12] + 80016aa: 429a cmp r2, r3 + 80016ac: d30e bcc.n 80016cc + { + timeInput -= monthLength; + 80016ae: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 + 80016b2: 68fa ldr r2, [r7, #12] + 80016b4: 1ad3 subs r3, r2, r3 + 80016b6: 60fb str r3, [r7, #12] + for (month = 0; month < 12; month++) + 80016b8: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80016bc: 3301 adds r3, #1 + 80016be: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 80016c2: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80016c6: 2b0b cmp r3, #11 + 80016c8: d9af bls.n 800162a + 80016ca: e000 b.n 80016ce + } + else + { + break; + 80016cc: bf00 nop + } + } + time->Month = month + 1; // jan is month 1 + 80016ce: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80016d2: 3301 adds r3, #1 + 80016d4: b2da uxtb r2, r3 + 80016d6: 68bb ldr r3, [r7, #8] + 80016d8: 711a strb r2, [r3, #4] + time->Day = timeInput + 1; // day of month + 80016da: 68fb ldr r3, [r7, #12] + 80016dc: b2db uxtb r3, r3 + 80016de: 3301 adds r3, #1 + 80016e0: b2da uxtb r2, r3 + 80016e2: 68bb ldr r3, [r7, #8] + 80016e4: 70da strb r2, [r3, #3] + + if (runIsDST) + 80016e6: 79fb ldrb r3, [r7, #7] + 80016e8: 2b00 cmp r3, #0 + 80016ea: d002 beq.n 80016f2 + IsDST(time); + 80016ec: 68b8 ldr r0, [r7, #8] + 80016ee: f7ff fded bl 80012cc +} + 80016f2: bf00 nop + 80016f4: 3728 adds r7, #40 ; 0x28 + 80016f6: 46bd mov sp, r7 + 80016f8: bd80 pop {r7, pc} + 80016fa: bf00 nop + 80016fc: 0801e674 .word 0x0801e674 + 8001700: 88888889 .word 0x88888889 + 8001704: aaaaaaab .word 0xaaaaaaab + 8001708: 24924925 .word 0x24924925 + 800170c: 51eb851f .word 0x51eb851f + +08001710 : + * @param time: our time struct to convert from + * @param runIsDST: bool if it will run the IsDST function after this function completes + * @return the epoch time + */ +uint32_t makeTime(ts *time, uint8_t runIsDST) +{ + 8001710: b580 push {r7, lr} + 8001712: b088 sub sp, #32 + 8001714: af00 add r7, sp, #0 + 8001716: 6078 str r0, [r7, #4] + 8001718: 460b mov r3, r1 + 800171a: 70fb strb r3, [r7, #3] + // note year argument is offset from 1970 (see macros in time.h to convert to other formats) + // previous version used full four digit year (or digits since 2000),i.e. 2009 was 2009 or 9 + + int i; + uint32_t seconds; + uint8_t monthDays[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + 800171c: 4a68 ldr r2, [pc, #416] ; (80018c0 ) + 800171e: f107 030c add.w r3, r7, #12 + 8001722: ca07 ldmia r2, {r0, r1, r2} + 8001724: e883 0007 stmia.w r3, {r0, r1, r2} + + // seconds from 1970 till 1 jan 00:00:00 of the given year + seconds = time->Year * (NUMBEROFSECONDSPERDAY * 365); + 8001728: 687b ldr r3, [r7, #4] + 800172a: f9b3 3006 ldrsh.w r3, [r3, #6] + 800172e: 461a mov r2, r3 + 8001730: 4b64 ldr r3, [pc, #400] ; (80018c4 ) + 8001732: fb02 f303 mul.w r3, r2, r3 + 8001736: 61bb str r3, [r7, #24] + for (i = 0; i < time->Year; i++) + 8001738: 2300 movs r3, #0 + 800173a: 61fb str r3, [r7, #28] + 800173c: e031 b.n 80017a2 + { + if (LEAP_YEAR(i)) + 800173e: 69fb ldr r3, [r7, #28] + 8001740: f46f 62f6 mvn.w r2, #1968 ; 0x7b0 + 8001744: 4293 cmp r3, r2 + 8001746: db29 blt.n 800179c + 8001748: 69fb ldr r3, [r7, #28] + 800174a: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 800174e: f003 0303 and.w r3, r3, #3 + 8001752: 2b00 cmp r3, #0 + 8001754: d122 bne.n 800179c + 8001756: 69fb ldr r3, [r7, #28] + 8001758: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800175c: 4b5a ldr r3, [pc, #360] ; (80018c8 ) + 800175e: fb83 1302 smull r1, r3, r3, r2 + 8001762: 1159 asrs r1, r3, #5 + 8001764: 17d3 asrs r3, r2, #31 + 8001766: 1acb subs r3, r1, r3 + 8001768: 2164 movs r1, #100 ; 0x64 + 800176a: fb01 f303 mul.w r3, r1, r3 + 800176e: 1ad3 subs r3, r2, r3 + 8001770: 2b00 cmp r3, #0 + 8001772: d10f bne.n 8001794 + 8001774: 69fb ldr r3, [r7, #28] + 8001776: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 800177a: 4b53 ldr r3, [pc, #332] ; (80018c8 ) + 800177c: fb83 1302 smull r1, r3, r3, r2 + 8001780: 11d9 asrs r1, r3, #7 + 8001782: 17d3 asrs r3, r2, #31 + 8001784: 1acb subs r3, r1, r3 + 8001786: f44f 71c8 mov.w r1, #400 ; 0x190 + 800178a: fb01 f303 mul.w r3, r1, r3 + 800178e: 1ad3 subs r3, r2, r3 + 8001790: 2b00 cmp r3, #0 + 8001792: d103 bne.n 800179c + { + seconds += NUMBEROFSECONDSPERDAY; // add extra days for leap years + 8001794: 69ba ldr r2, [r7, #24] + 8001796: 4b4d ldr r3, [pc, #308] ; (80018cc ) + 8001798: 4413 add r3, r2 + 800179a: 61bb str r3, [r7, #24] + for (i = 0; i < time->Year; i++) + 800179c: 69fb ldr r3, [r7, #28] + 800179e: 3301 adds r3, #1 + 80017a0: 61fb str r3, [r7, #28] + 80017a2: 687b ldr r3, [r7, #4] + 80017a4: f9b3 3006 ldrsh.w r3, [r3, #6] + 80017a8: 461a mov r2, r3 + 80017aa: 69fb ldr r3, [r7, #28] + 80017ac: 4293 cmp r3, r2 + 80017ae: dbc6 blt.n 800173e + } + } + + // add days for this year, months start from 1 + for (i = 1; i < time->Month; i++) + 80017b0: 2301 movs r3, #1 + 80017b2: 61fb str r3, [r7, #28] + 80017b4: e04a b.n 800184c + { + if ((i == 2) && LEAP_YEAR(time->Year)) + 80017b6: 69fb ldr r3, [r7, #28] + 80017b8: 2b02 cmp r3, #2 + 80017ba: d137 bne.n 800182c + 80017bc: 687b ldr r3, [r7, #4] + 80017be: f9b3 3006 ldrsh.w r3, [r3, #6] + 80017c2: f46f 62f6 mvn.w r2, #1968 ; 0x7b0 + 80017c6: 4293 cmp r3, r2 + 80017c8: db30 blt.n 800182c + 80017ca: 687b ldr r3, [r7, #4] + 80017cc: f9b3 3006 ldrsh.w r3, [r3, #6] + 80017d0: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 80017d4: f003 0303 and.w r3, r3, #3 + 80017d8: 2b00 cmp r3, #0 + 80017da: d127 bne.n 800182c + 80017dc: 687b ldr r3, [r7, #4] + 80017de: f9b3 3006 ldrsh.w r3, [r3, #6] + 80017e2: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 80017e6: 4b38 ldr r3, [pc, #224] ; (80018c8 ) + 80017e8: fb83 1302 smull r1, r3, r3, r2 + 80017ec: 1159 asrs r1, r3, #5 + 80017ee: 17d3 asrs r3, r2, #31 + 80017f0: 1acb subs r3, r1, r3 + 80017f2: 2164 movs r1, #100 ; 0x64 + 80017f4: fb01 f303 mul.w r3, r1, r3 + 80017f8: 1ad3 subs r3, r2, r3 + 80017fa: 2b00 cmp r3, #0 + 80017fc: d111 bne.n 8001822 + 80017fe: 687b ldr r3, [r7, #4] + 8001800: f9b3 3006 ldrsh.w r3, [r3, #6] + 8001804: f203 72b2 addw r2, r3, #1970 ; 0x7b2 + 8001808: 4b2f ldr r3, [pc, #188] ; (80018c8 ) + 800180a: fb83 1302 smull r1, r3, r3, r2 + 800180e: 11d9 asrs r1, r3, #7 + 8001810: 17d3 asrs r3, r2, #31 + 8001812: 1acb subs r3, r1, r3 + 8001814: f44f 71c8 mov.w r1, #400 ; 0x190 + 8001818: fb01 f303 mul.w r3, r1, r3 + 800181c: 1ad3 subs r3, r2, r3 + 800181e: 2b00 cmp r3, #0 + 8001820: d104 bne.n 800182c + { + seconds += NUMBEROFSECONDSPERDAY * 29; + 8001822: 69ba ldr r2, [r7, #24] + 8001824: 4b2a ldr r3, [pc, #168] ; (80018d0 ) + 8001826: 4413 add r3, r2 + 8001828: 61bb str r3, [r7, #24] + 800182a: e00c b.n 8001846 + } + else + { + seconds += NUMBEROFSECONDSPERDAY * monthDays[i - 1]; // monthDay array starts from 0 + 800182c: 69fb ldr r3, [r7, #28] + 800182e: 3b01 subs r3, #1 + 8001830: 3320 adds r3, #32 + 8001832: 443b add r3, r7 + 8001834: f813 3c14 ldrb.w r3, [r3, #-20] + 8001838: 461a mov r2, r3 + 800183a: 4b24 ldr r3, [pc, #144] ; (80018cc ) + 800183c: fb02 f303 mul.w r3, r2, r3 + 8001840: 69ba ldr r2, [r7, #24] + 8001842: 4413 add r3, r2 + 8001844: 61bb str r3, [r7, #24] + for (i = 1; i < time->Month; i++) + 8001846: 69fb ldr r3, [r7, #28] + 8001848: 3301 adds r3, #1 + 800184a: 61fb str r3, [r7, #28] + 800184c: 687b ldr r3, [r7, #4] + 800184e: 791b ldrb r3, [r3, #4] + 8001850: 461a mov r2, r3 + 8001852: 69fb ldr r3, [r7, #28] + 8001854: 4293 cmp r3, r2 + 8001856: dbae blt.n 80017b6 + } + } + seconds += (time->Day - 1) * NUMBEROFSECONDSPERDAY; + 8001858: 687b ldr r3, [r7, #4] + 800185a: 78db ldrb r3, [r3, #3] + 800185c: 3b01 subs r3, #1 + 800185e: 461a mov r2, r3 + 8001860: 4b1a ldr r3, [pc, #104] ; (80018cc ) + 8001862: fb02 f303 mul.w r3, r2, r3 + 8001866: 69ba ldr r2, [r7, #24] + 8001868: 4413 add r3, r2 + 800186a: 61bb str r3, [r7, #24] + seconds += time->Hour * NUMBEROFSECONDSPERHOUR; + 800186c: 687b ldr r3, [r7, #4] + 800186e: 789b ldrb r3, [r3, #2] + 8001870: 461a mov r2, r3 + 8001872: f44f 6361 mov.w r3, #3600 ; 0xe10 + 8001876: fb02 f303 mul.w r3, r2, r3 + 800187a: 69ba ldr r2, [r7, #24] + 800187c: 4413 add r3, r2 + 800187e: 61bb str r3, [r7, #24] + seconds += time->Minute * NUMBEROFSECONDSPERMINUTE; + 8001880: 687b ldr r3, [r7, #4] + 8001882: 785b ldrb r3, [r3, #1] + 8001884: 461a mov r2, r3 + 8001886: 4613 mov r3, r2 + 8001888: 011b lsls r3, r3, #4 + 800188a: 1a9b subs r3, r3, r2 + 800188c: 009b lsls r3, r3, #2 + 800188e: 461a mov r2, r3 + 8001890: 69bb ldr r3, [r7, #24] + 8001892: 4413 add r3, r2 + 8001894: 61bb str r3, [r7, #24] + seconds += time->Second; + 8001896: 687b ldr r3, [r7, #4] + 8001898: 781b ldrb r3, [r3, #0] + 800189a: 461a mov r2, r3 + 800189c: 69bb ldr r3, [r7, #24] + 800189e: 4413 add r3, r2 + 80018a0: 61bb str r3, [r7, #24] + + if (runIsDST) + 80018a2: 78fb ldrb r3, [r7, #3] + 80018a4: 2b00 cmp r3, #0 + 80018a6: d002 beq.n 80018ae + IsDST(time); + 80018a8: 6878 ldr r0, [r7, #4] + 80018aa: f7ff fd0f bl 80012cc + time->unixtime = seconds; + 80018ae: 687b ldr r3, [r7, #4] + 80018b0: 69ba ldr r2, [r7, #24] + 80018b2: 60da str r2, [r3, #12] + return seconds; + 80018b4: 69bb ldr r3, [r7, #24] +} + 80018b6: 4618 mov r0, r3 + 80018b8: 3720 adds r7, #32 + 80018ba: 46bd mov sp, r7 + 80018bc: bd80 pop {r7, pc} + 80018be: bf00 nop + 80018c0: 0801e674 .word 0x0801e674 + 80018c4: 01e13380 .word 0x01e13380 + 80018c8: 51eb851f .word 0x51eb851f + 80018cc: 00015180 .word 0x00015180 + 80018d0: 00263b80 .word 0x00263b80 + +080018d4 : + * @param local: the time struct in which we want to write our conversion + * @param timeZone: the offset from UTC ex. UTC+1 => timeZone = 1 + * @param IsDST: bool if we want to take DST in to account + */ +void toTimeZone(ts *utc, ts *local, int8_t timeZone, uint8_t IsDST) +{ + 80018d4: b580 push {r7, lr} + 80018d6: b086 sub sp, #24 + 80018d8: af00 add r7, sp, #0 + 80018da: 60f8 str r0, [r7, #12] + 80018dc: 60b9 str r1, [r7, #8] + 80018de: 4611 mov r1, r2 + 80018e0: 461a mov r2, r3 + 80018e2: 460b mov r3, r1 + 80018e4: 71fb strb r3, [r7, #7] + 80018e6: 4613 mov r3, r2 + 80018e8: 71bb strb r3, [r7, #6] + uint32_t localTime; + makeTime(utc, 1); + 80018ea: 2101 movs r1, #1 + 80018ec: 68f8 ldr r0, [r7, #12] + 80018ee: f7ff ff0f bl 8001710 + if (IsDST) + 80018f2: 79bb ldrb r3, [r7, #6] + 80018f4: 2b00 cmp r3, #0 + 80018f6: d00e beq.n 8001916 + { + localTime = utc->unixtime + (timeZone + utc->IsDST) * NUMBEROFSECONDSPERHOUR; + 80018f8: 68fb ldr r3, [r7, #12] + 80018fa: 68da ldr r2, [r3, #12] + 80018fc: f997 3007 ldrsb.w r3, [r7, #7] + 8001900: 68f9 ldr r1, [r7, #12] + 8001902: 7a89 ldrb r1, [r1, #10] + 8001904: 440b add r3, r1 + 8001906: 4619 mov r1, r3 + 8001908: f44f 6361 mov.w r3, #3600 ; 0xe10 + 800190c: fb01 f303 mul.w r3, r1, r3 + 8001910: 4413 add r3, r2 + 8001912: 617b str r3, [r7, #20] + 8001914: e009 b.n 800192a + } + else + { + localTime = utc->unixtime + timeZone * NUMBEROFSECONDSPERHOUR; + 8001916: 68fb ldr r3, [r7, #12] + 8001918: 68da ldr r2, [r3, #12] + 800191a: f997 3007 ldrsb.w r3, [r7, #7] + 800191e: f44f 6161 mov.w r1, #3600 ; 0xe10 + 8001922: fb01 f303 mul.w r3, r1, r3 + 8001926: 4413 add r3, r2 + 8001928: 617b str r3, [r7, #20] + } + + breakTime(localTime, local, 0); + 800192a: 2200 movs r2, #0 + 800192c: 68b9 ldr r1, [r7, #8] + 800192e: 6978 ldr r0, [r7, #20] + 8001930: f7ff fd9a bl 8001468 +} + 8001934: bf00 nop + 8001936: 3718 adds r7, #24 + 8001938: 46bd mov sp, r7 + 800193a: bd80 pop {r7, pc} + 800193c: 0000 movs r0, r0 + ... + +08001940 : +#include "debug.h" + +extern RTC_HandleTypeDef hrtc; + +void app_main(void *argument) +{ + 8001940: b580 push {r7, lr} + 8001942: b096 sub sp, #88 ; 0x58 + 8001944: af04 add r7, sp, #16 + 8001946: 6078 str r0, [r7, #4] + RTC_TimeTypeDef sTime; + RTC_DateTypeDef sDate; + uint8_t sBefore; + + /* init code for LWIP */ + MX_LWIP_Init(); + 8001948: f008 fe52 bl 800a5f0 + /* USER CODE BEGIN 5 */ + + debugln("LWIP is initialized"); + 800194c: 4872 ldr r0, [pc, #456] ; (8001b18 ) + 800194e: f01a fbe7 bl 801c120 + + // The stored time is always in UTC + breakTime(NTPToEpochUnix(), &utc, 0); + 8001952: f7ff fad5 bl 8000f00 + 8001956: f107 0334 add.w r3, r7, #52 ; 0x34 + 800195a: 2200 movs r2, #0 + 800195c: 4619 mov r1, r3 + 800195e: f7ff fd83 bl 8001468 + toTimeZone(&utc, &local, UTC_DELTA_HOURS, 1); + 8001962: f107 0124 add.w r1, r7, #36 ; 0x24 + 8001966: f107 0034 add.w r0, r7, #52 ; 0x34 + 800196a: 2301 movs r3, #1 + 800196c: 2201 movs r2, #1 + 800196e: f7ff ffb1 bl 80018d4 + debugln("Started: %02d:%02d:%02d", utc.Hour, utc.Minute, utc.Second); + 8001972: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8001976: 4619 mov r1, r3 + 8001978: f897 3035 ldrb.w r3, [r7, #53] ; 0x35 + 800197c: 461a mov r2, r3 + 800197e: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8001982: 4866 ldr r0, [pc, #408] ; (8001b1c ) + 8001984: f01a fb46 bl 801c014 + debugln(" \n"); // I don't know why, but my uart/Serial monitor doesn't show epoch and packet sent if I remove the spaces + 8001988: 4865 ldr r0, [pc, #404] ; (8001b20 ) + 800198a: f01a fbc9 bl 801c120 + Ts_To_RTC(&utc, &sTime, &sDate); + 800198e: f107 020c add.w r2, r7, #12 + 8001992: f107 0110 add.w r1, r7, #16 + 8001996: f107 0334 add.w r3, r7, #52 ; 0x34 + 800199a: 4618 mov r0, r3 + 800199c: f7ff fc4a bl 8001234 + Set_Time(sTime, sDate); + 80019a0: 68fb ldr r3, [r7, #12] + 80019a2: 9301 str r3, [sp, #4] + 80019a4: 6a3b ldr r3, [r7, #32] + 80019a6: 9300 str r3, [sp, #0] + 80019a8: f107 0310 add.w r3, r7, #16 + 80019ac: cb0f ldmia r3, {r0, r1, r2, r3} + 80019ae: f7ff fbf3 bl 8001198 + DS3231_SetTime(&utc); + 80019b2: f107 0334 add.w r3, r7, #52 ; 0x34 + 80019b6: 4618 mov r0, r3 + 80019b8: f000 fd52 bl 8002460 + + BSP_LCD_SelectLayer(0); + 80019bc: 2000 movs r0, #0 + 80019be: f001 ffdb bl 8003978 + BSP_LCD_Clear(LCD_COLOR_BLACK); + 80019c2: f04f 407f mov.w r0, #4278190080 ; 0xff000000 + 80019c6: f002 f833 bl 8003a30 + BSP_LCD_SetTextColor(LCD_COLOR_WHITE); + 80019ca: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 80019ce: f001 ffe3 bl 8003998 + BSP_LCD_SetBackColor(LCD_COLOR_BLACK); + 80019d2: f04f 407f mov.w r0, #4278190080 ; 0xff000000 + 80019d6: f001 fff7 bl 80039c8 + BSP_LCD_SetFont(&Font12); + 80019da: 4852 ldr r0, [pc, #328] ; (8001b24 ) + 80019dc: f002 f80e bl 80039fc + Clock_Draw_Outline(X_CENTER, Y_CENTER, Radius); + 80019e0: ed9f 0b4b vldr d0, [pc, #300] ; 8001b10 + 80019e4: 2187 movs r1, #135 ; 0x87 + 80019e6: 20f0 movs r0, #240 ; 0xf0 + 80019e8: f000 f8a6 bl 8001b38 + BSP_LCD_SelectLayer(1); + 80019ec: 2001 movs r0, #1 + 80019ee: f001 ffc3 bl 8003978 + + /* Infinite loop */ + for (;;) + { + Get_Time(&sDate, &sTime); + 80019f2: f107 0210 add.w r2, r7, #16 + 80019f6: f107 030c add.w r3, r7, #12 + 80019fa: 4611 mov r1, r2 + 80019fc: 4618 mov r0, r3 + 80019fe: f7ff fc03 bl 8001208 + //DS3231_GetTime(&utc); + if ((utc.Hour == 0) && (utc.Minute == 0) && (utc.Second == 0) && sBefore == 59) + 8001a02: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8001a06: 2b00 cmp r3, #0 + 8001a08: d12b bne.n 8001a62 + 8001a0a: f897 3035 ldrb.w r3, [r7, #53] ; 0x35 + 8001a0e: 2b00 cmp r3, #0 + 8001a10: d127 bne.n 8001a62 + 8001a12: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8001a16: 2b00 cmp r3, #0 + 8001a18: d123 bne.n 8001a62 + 8001a1a: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 + 8001a1e: 2b3b cmp r3, #59 ; 0x3b + 8001a20: d11f bne.n 8001a62 + { + debugln(" \nUpdating time"); + 8001a22: 4841 ldr r0, [pc, #260] ; (8001b28 ) + 8001a24: f01a fb7c bl 801c120 + breakTime(NTPToEpochUnix(), &utc, 0); + 8001a28: f7ff fa6a bl 8000f00 + 8001a2c: f107 0334 add.w r3, r7, #52 ; 0x34 + 8001a30: 2200 movs r2, #0 + 8001a32: 4619 mov r1, r3 + 8001a34: f7ff fd18 bl 8001468 + printf(" \n"); + 8001a38: 483c ldr r0, [pc, #240] ; (8001b2c ) + 8001a3a: f01a fb71 bl 801c120 + Ts_To_RTC(&utc, &sTime, &sDate); + 8001a3e: f107 020c add.w r2, r7, #12 + 8001a42: f107 0110 add.w r1, r7, #16 + 8001a46: f107 0334 add.w r3, r7, #52 ; 0x34 + 8001a4a: 4618 mov r0, r3 + 8001a4c: f7ff fbf2 bl 8001234 + Set_Time(sTime, sDate); + 8001a50: 68fb ldr r3, [r7, #12] + 8001a52: 9301 str r3, [sp, #4] + 8001a54: 6a3b ldr r3, [r7, #32] + 8001a56: 9300 str r3, [sp, #0] + 8001a58: f107 0310 add.w r3, r7, #16 + 8001a5c: cb0f ldmia r3, {r0, r1, r2, r3} + 8001a5e: f7ff fb9b bl 8001198 + //DS3231_SetTime(&utc); + } + + RTC_To_Ts(&sTime, &sDate, &utc); + 8001a62: f107 0234 add.w r2, r7, #52 ; 0x34 + 8001a66: f107 010c add.w r1, r7, #12 + 8001a6a: f107 0310 add.w r3, r7, #16 + 8001a6e: 4618 mov r0, r3 + 8001a70: f7ff fc06 bl 8001280 + toTimeZone(&utc, &local, UTC_DELTA_HOURS, 1); + 8001a74: f107 0124 add.w r1, r7, #36 ; 0x24 + 8001a78: f107 0034 add.w r0, r7, #52 ; 0x34 + 8001a7c: 2301 movs r3, #1 + 8001a7e: 2201 movs r2, #1 + 8001a80: f7ff ff28 bl 80018d4 + if (local.Second != sBefore) + 8001a84: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8001a88: f897 2047 ldrb.w r2, [r7, #71] ; 0x47 + 8001a8c: 429a cmp r2, r3 + 8001a8e: d034 beq.n 8001afa + { + printf(CURSOR_PREV_N_LINES(1) ERASE_FROM_CURSOR_TO_END); + 8001a90: 4827 ldr r0, [pc, #156] ; (8001b30 ) + 8001a92: f01a fabf bl 801c014 + //debugln("RTC : %02d:%02d:%02d", sTime.Hours, sTime.Minutes, sTime.Seconds); + debugln("DS3231: %02d:%02d:%02d", utc.Hour, utc.Minute, utc.Second); + 8001a96: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8001a9a: 4619 mov r1, r3 + 8001a9c: f897 3035 ldrb.w r3, [r7, #53] ; 0x35 + 8001aa0: 461a mov r2, r3 + 8001aa2: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8001aa6: 4823 ldr r0, [pc, #140] ; (8001b34 ) + 8001aa8: f01a fab4 bl 801c014 + //TimeDiff(&utc, &rtc, &diff); + //debugln("DIFF : %02d:%02d:%02d", diff.Hour, diff.Minute, diff.Second); + BSP_LCD_Clear(LCD_COLOR_TRANSPARENT); + 8001aac: 2000 movs r0, #0 + 8001aae: f001 ffbf bl 8003a30 + + Clock_Write_Date(0, 0, Y_CENTER, 40, local.Wday, local.Day, local.Month, local.Year + 1970); + 8001ab2: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 8001ab6: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 8001aba: f897 1028 ldrb.w r1, [r7, #40] ; 0x28 + 8001abe: f9b7 002a ldrsh.w r0, [r7, #42] ; 0x2a + 8001ac2: b280 uxth r0, r0 + 8001ac4: f200 70b2 addw r0, r0, #1970 ; 0x7b2 + 8001ac8: b280 uxth r0, r0 + 8001aca: 9003 str r0, [sp, #12] + 8001acc: 9102 str r1, [sp, #8] + 8001ace: 9201 str r2, [sp, #4] + 8001ad0: 9300 str r3, [sp, #0] + 8001ad2: 2328 movs r3, #40 ; 0x28 + 8001ad4: 2287 movs r2, #135 ; 0x87 + 8001ad6: 2100 movs r1, #0 + 8001ad8: 2000 movs r0, #0 + 8001ada: f000 fbb9 bl 8002250 + + Clock_Draw_Hands(X_CENTER, Y_CENTER, Radius, local.Hour, local.Minute, local.Second); + 8001ade: f897 2026 ldrb.w r2, [r7, #38] ; 0x26 + 8001ae2: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 8001ae6: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8001aea: 9300 str r3, [sp, #0] + 8001aec: 460b mov r3, r1 + 8001aee: ed9f 0b08 vldr d0, [pc, #32] ; 8001b10 + 8001af2: 2187 movs r1, #135 ; 0x87 + 8001af4: 20f0 movs r0, #240 ; 0xf0 + 8001af6: f000 fa0f bl 8001f18 + } + + sBefore = local.Second; + 8001afa: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8001afe: f887 3047 strb.w r3, [r7, #71] ; 0x47 + osDelay(10); + 8001b02: 200a movs r0, #10 + 8001b04: f009 fb26 bl 800b154 + Get_Time(&sDate, &sTime); + 8001b08: e773 b.n 80019f2 + 8001b0a: bf00 nop + 8001b0c: f3af 8000 nop.w + 8001b10: 00000000 .word 0x00000000 + 8001b14: 40602000 .word 0x40602000 + 8001b18: 0801e680 .word 0x0801e680 + 8001b1c: 0801e6a0 .word 0x0801e6a0 + 8001b20: 0801e6c4 .word 0x0801e6c4 + 8001b24: 20000088 .word 0x20000088 + 8001b28: 0801e6d0 .word 0x0801e6d0 + 8001b2c: 0801e6ec .word 0x0801e6ec + 8001b30: 0801e6f0 .word 0x0801e6f0 + 8001b34: 0801e6fc .word 0x0801e6fc + +08001b38 : + 0, 10, //8 + 0, 12 //7 +}; + +void Clock_Draw_Outline(uint16_t xCenter, uint16_t yCenter, double radius) +{ + 8001b38: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 8001b3c: b08a sub sp, #40 ; 0x28 + 8001b3e: af00 add r7, sp, #0 + 8001b40: 4603 mov r3, r0 + 8001b42: 460a mov r2, r1 + 8001b44: ed87 0b00 vstr d0, [r7] + 8001b48: 81fb strh r3, [r7, #14] + 8001b4a: 4613 mov r3, r2 + 8001b4c: 81bb strh r3, [r7, #12] + uint16_t x1, y1, x2, y2; + double angle; + // draw the outline of the clock + BSP_LCD_DrawCircle(xCenter, yCenter, 2); + 8001b4e: 89b9 ldrh r1, [r7, #12] + 8001b50: 89fb ldrh r3, [r7, #14] + 8001b52: 2202 movs r2, #2 + 8001b54: 4618 mov r0, r3 + 8001b56: f002 f96b bl 8003e30 + // draw minute's ticks (60 lines) + for (int j = 1; j <= 60; j++) + 8001b5a: 2301 movs r3, #1 + 8001b5c: 627b str r3, [r7, #36] ; 0x24 + 8001b5e: e0a0 b.n 8001ca2 + { + angle = j * 6; + 8001b60: 6a7a ldr r2, [r7, #36] ; 0x24 + 8001b62: 4613 mov r3, r2 + 8001b64: 005b lsls r3, r3, #1 + 8001b66: 4413 add r3, r2 + 8001b68: 005b lsls r3, r3, #1 + 8001b6a: 4618 mov r0, r3 + 8001b6c: f7fe fcfa bl 8000564 <__aeabi_i2d> + 8001b70: 4602 mov r2, r0 + 8001b72: 460b mov r3, r1 + 8001b74: e9c7 2306 strd r2, r3, [r7, #24] + angle = angle * M_PI / 180; + 8001b78: a34d add r3, pc, #308 ; (adr r3, 8001cb0 ) + 8001b7a: e9d3 2300 ldrd r2, r3, [r3] + 8001b7e: e9d7 0106 ldrd r0, r1, [r7, #24] + 8001b82: f7fe fd59 bl 8000638 <__aeabi_dmul> + 8001b86: 4602 mov r2, r0 + 8001b88: 460b mov r3, r1 + 8001b8a: 4610 mov r0, r2 + 8001b8c: 4619 mov r1, r3 + 8001b8e: f04f 0200 mov.w r2, #0 + 8001b92: 4b49 ldr r3, [pc, #292] ; (8001cb8 ) + 8001b94: f7fe fe7a bl 800088c <__aeabi_ddiv> + 8001b98: 4602 mov r2, r0 + 8001b9a: 460b mov r3, r1 + 8001b9c: e9c7 2306 strd r2, r3, [r7, #24] + + x1 = xCenter + (sin(angle) * radius); + 8001ba0: 89fb ldrh r3, [r7, #14] + 8001ba2: 4618 mov r0, r3 + 8001ba4: f7fe fcde bl 8000564 <__aeabi_i2d> + 8001ba8: 4604 mov r4, r0 + 8001baa: 460d mov r5, r1 + 8001bac: ed97 0b06 vldr d0, [r7, #24] + 8001bb0: f01b fbf2 bl 801d398 + 8001bb4: ec51 0b10 vmov r0, r1, d0 + 8001bb8: e9d7 2300 ldrd r2, r3, [r7] + 8001bbc: f7fe fd3c bl 8000638 <__aeabi_dmul> + 8001bc0: 4602 mov r2, r0 + 8001bc2: 460b mov r3, r1 + 8001bc4: 4620 mov r0, r4 + 8001bc6: 4629 mov r1, r5 + 8001bc8: f7fe fb80 bl 80002cc <__adddf3> + 8001bcc: 4602 mov r2, r0 + 8001bce: 460b mov r3, r1 + 8001bd0: 4610 mov r0, r2 + 8001bd2: 4619 mov r1, r3 + 8001bd4: f7fe fff2 bl 8000bbc <__aeabi_d2uiz> + 8001bd8: 4603 mov r3, r0 + 8001bda: 82fb strh r3, [r7, #22] + y1 = yCenter + (cos(angle) * radius); + 8001bdc: 89bb ldrh r3, [r7, #12] + 8001bde: 4618 mov r0, r3 + 8001be0: f7fe fcc0 bl 8000564 <__aeabi_i2d> + 8001be4: 4604 mov r4, r0 + 8001be6: 460d mov r5, r1 + 8001be8: ed97 0b06 vldr d0, [r7, #24] + 8001bec: f01b fb80 bl 801d2f0 + 8001bf0: ec51 0b10 vmov r0, r1, d0 + 8001bf4: e9d7 2300 ldrd r2, r3, [r7] + 8001bf8: f7fe fd1e bl 8000638 <__aeabi_dmul> + 8001bfc: 4602 mov r2, r0 + 8001bfe: 460b mov r3, r1 + 8001c00: 4620 mov r0, r4 + 8001c02: 4629 mov r1, r5 + 8001c04: f7fe fb62 bl 80002cc <__adddf3> + 8001c08: 4602 mov r2, r0 + 8001c0a: 460b mov r3, r1 + 8001c0c: 4610 mov r0, r2 + 8001c0e: 4619 mov r1, r3 + 8001c10: f7fe ffd4 bl 8000bbc <__aeabi_d2uiz> + 8001c14: 4603 mov r3, r0 + 8001c16: 82bb strh r3, [r7, #20] + x2 = xCenter + (sin(angle) * (radius)); + 8001c18: 89fb ldrh r3, [r7, #14] + 8001c1a: 4618 mov r0, r3 + 8001c1c: f7fe fca2 bl 8000564 <__aeabi_i2d> + 8001c20: 4604 mov r4, r0 + 8001c22: 460d mov r5, r1 + 8001c24: ed97 0b06 vldr d0, [r7, #24] + 8001c28: f01b fbb6 bl 801d398 + 8001c2c: ec51 0b10 vmov r0, r1, d0 + 8001c30: e9d7 2300 ldrd r2, r3, [r7] + 8001c34: f7fe fd00 bl 8000638 <__aeabi_dmul> + 8001c38: 4602 mov r2, r0 + 8001c3a: 460b mov r3, r1 + 8001c3c: 4620 mov r0, r4 + 8001c3e: 4629 mov r1, r5 + 8001c40: f7fe fb44 bl 80002cc <__adddf3> + 8001c44: 4602 mov r2, r0 + 8001c46: 460b mov r3, r1 + 8001c48: 4610 mov r0, r2 + 8001c4a: 4619 mov r1, r3 + 8001c4c: f7fe ffb6 bl 8000bbc <__aeabi_d2uiz> + 8001c50: 4603 mov r3, r0 + 8001c52: 827b strh r3, [r7, #18] + y2 = yCenter + (cos(angle) * (radius)); + 8001c54: 89bb ldrh r3, [r7, #12] + 8001c56: 4618 mov r0, r3 + 8001c58: f7fe fc84 bl 8000564 <__aeabi_i2d> + 8001c5c: 4604 mov r4, r0 + 8001c5e: 460d mov r5, r1 + 8001c60: ed97 0b06 vldr d0, [r7, #24] + 8001c64: f01b fb44 bl 801d2f0 + 8001c68: ec51 0b10 vmov r0, r1, d0 + 8001c6c: e9d7 2300 ldrd r2, r3, [r7] + 8001c70: f7fe fce2 bl 8000638 <__aeabi_dmul> + 8001c74: 4602 mov r2, r0 + 8001c76: 460b mov r3, r1 + 8001c78: 4620 mov r0, r4 + 8001c7a: 4629 mov r1, r5 + 8001c7c: f7fe fb26 bl 80002cc <__adddf3> + 8001c80: 4602 mov r2, r0 + 8001c82: 460b mov r3, r1 + 8001c84: 4610 mov r0, r2 + 8001c86: 4619 mov r1, r3 + 8001c88: f7fe ff98 bl 8000bbc <__aeabi_d2uiz> + 8001c8c: 4603 mov r3, r0 + 8001c8e: 823b strh r3, [r7, #16] + BSP_LCD_DrawLine(x1, y1, x2, y2); + 8001c90: 8a3b ldrh r3, [r7, #16] + 8001c92: 8a7a ldrh r2, [r7, #18] + 8001c94: 8ab9 ldrh r1, [r7, #20] + 8001c96: 8af8 ldrh r0, [r7, #22] + 8001c98: f001 fffe bl 8003c98 + for (int j = 1; j <= 60; j++) + 8001c9c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001c9e: 3301 adds r3, #1 + 8001ca0: 627b str r3, [r7, #36] ; 0x24 + 8001ca2: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001ca4: 2b3c cmp r3, #60 ; 0x3c + 8001ca6: f77f af5b ble.w 8001b60 + } + // draw hour's ticks (12 lines) + for (int j = 0; j < 12; j++) + 8001caa: 2300 movs r3, #0 + 8001cac: 623b str r3, [r7, #32] + 8001cae: e118 b.n 8001ee2 + 8001cb0: 54442d18 .word 0x54442d18 + 8001cb4: 400921fb .word 0x400921fb + 8001cb8: 40668000 .word 0x40668000 + { + angle = j * 30 * M_PI / 180; + 8001cbc: 6a3a ldr r2, [r7, #32] + 8001cbe: 4613 mov r3, r2 + 8001cc0: 011b lsls r3, r3, #4 + 8001cc2: 1a9b subs r3, r3, r2 + 8001cc4: 005b lsls r3, r3, #1 + 8001cc6: 4618 mov r0, r3 + 8001cc8: f7fe fc4c bl 8000564 <__aeabi_i2d> + 8001ccc: a38f add r3, pc, #572 ; (adr r3, 8001f0c ) + 8001cce: e9d3 2300 ldrd r2, r3, [r3] + 8001cd2: f7fe fcb1 bl 8000638 <__aeabi_dmul> + 8001cd6: 4602 mov r2, r0 + 8001cd8: 460b mov r3, r1 + 8001cda: 4610 mov r0, r2 + 8001cdc: 4619 mov r1, r3 + 8001cde: f04f 0200 mov.w r2, #0 + 8001ce2: 4b85 ldr r3, [pc, #532] ; (8001ef8 ) + 8001ce4: f7fe fdd2 bl 800088c <__aeabi_ddiv> + 8001ce8: 4602 mov r2, r0 + 8001cea: 460b mov r3, r1 + 8001cec: e9c7 2306 strd r2, r3, [r7, #24] + + x1 = xCenter + (sin(angle) * radius); + 8001cf0: 89fb ldrh r3, [r7, #14] + 8001cf2: 4618 mov r0, r3 + 8001cf4: f7fe fc36 bl 8000564 <__aeabi_i2d> + 8001cf8: 4604 mov r4, r0 + 8001cfa: 460d mov r5, r1 + 8001cfc: ed97 0b06 vldr d0, [r7, #24] + 8001d00: f01b fb4a bl 801d398 + 8001d04: ec51 0b10 vmov r0, r1, d0 + 8001d08: e9d7 2300 ldrd r2, r3, [r7] + 8001d0c: f7fe fc94 bl 8000638 <__aeabi_dmul> + 8001d10: 4602 mov r2, r0 + 8001d12: 460b mov r3, r1 + 8001d14: 4620 mov r0, r4 + 8001d16: 4629 mov r1, r5 + 8001d18: f7fe fad8 bl 80002cc <__adddf3> + 8001d1c: 4602 mov r2, r0 + 8001d1e: 460b mov r3, r1 + 8001d20: 4610 mov r0, r2 + 8001d22: 4619 mov r1, r3 + 8001d24: f7fe ff4a bl 8000bbc <__aeabi_d2uiz> + 8001d28: 4603 mov r3, r0 + 8001d2a: 82fb strh r3, [r7, #22] + y1 = yCenter + (cos(angle) * radius); + 8001d2c: 89bb ldrh r3, [r7, #12] + 8001d2e: 4618 mov r0, r3 + 8001d30: f7fe fc18 bl 8000564 <__aeabi_i2d> + 8001d34: 4604 mov r4, r0 + 8001d36: 460d mov r5, r1 + 8001d38: ed97 0b06 vldr d0, [r7, #24] + 8001d3c: f01b fad8 bl 801d2f0 + 8001d40: ec51 0b10 vmov r0, r1, d0 + 8001d44: e9d7 2300 ldrd r2, r3, [r7] + 8001d48: f7fe fc76 bl 8000638 <__aeabi_dmul> + 8001d4c: 4602 mov r2, r0 + 8001d4e: 460b mov r3, r1 + 8001d50: 4620 mov r0, r4 + 8001d52: 4629 mov r1, r5 + 8001d54: f7fe faba bl 80002cc <__adddf3> + 8001d58: 4602 mov r2, r0 + 8001d5a: 460b mov r3, r1 + 8001d5c: 4610 mov r0, r2 + 8001d5e: 4619 mov r1, r3 + 8001d60: f7fe ff2c bl 8000bbc <__aeabi_d2uiz> + 8001d64: 4603 mov r3, r0 + 8001d66: 82bb strh r3, [r7, #20] + x2 = xCenter + (sin(angle) * (radius - 4)); + 8001d68: 89fb ldrh r3, [r7, #14] + 8001d6a: 4618 mov r0, r3 + 8001d6c: f7fe fbfa bl 8000564 <__aeabi_i2d> + 8001d70: 4604 mov r4, r0 + 8001d72: 460d mov r5, r1 + 8001d74: ed97 0b06 vldr d0, [r7, #24] + 8001d78: f01b fb0e bl 801d398 + 8001d7c: ec59 8b10 vmov r8, r9, d0 + 8001d80: f04f 0200 mov.w r2, #0 + 8001d84: 4b5d ldr r3, [pc, #372] ; (8001efc ) + 8001d86: e9d7 0100 ldrd r0, r1, [r7] + 8001d8a: f7fe fa9d bl 80002c8 <__aeabi_dsub> + 8001d8e: 4602 mov r2, r0 + 8001d90: 460b mov r3, r1 + 8001d92: 4640 mov r0, r8 + 8001d94: 4649 mov r1, r9 + 8001d96: f7fe fc4f bl 8000638 <__aeabi_dmul> + 8001d9a: 4602 mov r2, r0 + 8001d9c: 460b mov r3, r1 + 8001d9e: 4620 mov r0, r4 + 8001da0: 4629 mov r1, r5 + 8001da2: f7fe fa93 bl 80002cc <__adddf3> + 8001da6: 4602 mov r2, r0 + 8001da8: 460b mov r3, r1 + 8001daa: 4610 mov r0, r2 + 8001dac: 4619 mov r1, r3 + 8001dae: f7fe ff05 bl 8000bbc <__aeabi_d2uiz> + 8001db2: 4603 mov r3, r0 + 8001db4: 827b strh r3, [r7, #18] + y2 = yCenter + (cos(angle) * (radius - 4)); + 8001db6: 89bb ldrh r3, [r7, #12] + 8001db8: 4618 mov r0, r3 + 8001dba: f7fe fbd3 bl 8000564 <__aeabi_i2d> + 8001dbe: 4604 mov r4, r0 + 8001dc0: 460d mov r5, r1 + 8001dc2: ed97 0b06 vldr d0, [r7, #24] + 8001dc6: f01b fa93 bl 801d2f0 + 8001dca: ec59 8b10 vmov r8, r9, d0 + 8001dce: f04f 0200 mov.w r2, #0 + 8001dd2: 4b4a ldr r3, [pc, #296] ; (8001efc ) + 8001dd4: e9d7 0100 ldrd r0, r1, [r7] + 8001dd8: f7fe fa76 bl 80002c8 <__aeabi_dsub> + 8001ddc: 4602 mov r2, r0 + 8001dde: 460b mov r3, r1 + 8001de0: 4640 mov r0, r8 + 8001de2: 4649 mov r1, r9 + 8001de4: f7fe fc28 bl 8000638 <__aeabi_dmul> + 8001de8: 4602 mov r2, r0 + 8001dea: 460b mov r3, r1 + 8001dec: 4620 mov r0, r4 + 8001dee: 4629 mov r1, r5 + 8001df0: f7fe fa6c bl 80002cc <__adddf3> + 8001df4: 4602 mov r2, r0 + 8001df6: 460b mov r3, r1 + 8001df8: 4610 mov r0, r2 + 8001dfa: 4619 mov r1, r3 + 8001dfc: f7fe fede bl 8000bbc <__aeabi_d2uiz> + 8001e00: 4603 mov r3, r0 + 8001e02: 823b strh r3, [r7, #16] + BSP_LCD_DrawLine(x1, y1, x2, y2); + 8001e04: 8a3b ldrh r3, [r7, #16] + 8001e06: 8a7a ldrh r2, [r7, #18] + 8001e08: 8ab9 ldrh r1, [r7, #20] + 8001e0a: 8af8 ldrh r0, [r7, #22] + 8001e0c: f001 ff44 bl 8003c98 + // draw hour digits(12 lines) + x2 = xCenter + (sin(angle) * (radius - 8)); + 8001e10: 89fb ldrh r3, [r7, #14] + 8001e12: 4618 mov r0, r3 + 8001e14: f7fe fba6 bl 8000564 <__aeabi_i2d> + 8001e18: 4604 mov r4, r0 + 8001e1a: 460d mov r5, r1 + 8001e1c: ed97 0b06 vldr d0, [r7, #24] + 8001e20: f01b faba bl 801d398 + 8001e24: ec59 8b10 vmov r8, r9, d0 + 8001e28: f04f 0200 mov.w r2, #0 + 8001e2c: 4b34 ldr r3, [pc, #208] ; (8001f00 ) + 8001e2e: e9d7 0100 ldrd r0, r1, [r7] + 8001e32: f7fe fa49 bl 80002c8 <__aeabi_dsub> + 8001e36: 4602 mov r2, r0 + 8001e38: 460b mov r3, r1 + 8001e3a: 4640 mov r0, r8 + 8001e3c: 4649 mov r1, r9 + 8001e3e: f7fe fbfb bl 8000638 <__aeabi_dmul> + 8001e42: 4602 mov r2, r0 + 8001e44: 460b mov r3, r1 + 8001e46: 4620 mov r0, r4 + 8001e48: 4629 mov r1, r5 + 8001e4a: f7fe fa3f bl 80002cc <__adddf3> + 8001e4e: 4602 mov r2, r0 + 8001e50: 460b mov r3, r1 + 8001e52: 4610 mov r0, r2 + 8001e54: 4619 mov r1, r3 + 8001e56: f7fe feb1 bl 8000bbc <__aeabi_d2uiz> + 8001e5a: 4603 mov r3, r0 + 8001e5c: 827b strh r3, [r7, #18] + y2 = yCenter + (cos(angle) * (radius - 8)); + 8001e5e: 89bb ldrh r3, [r7, #12] + 8001e60: 4618 mov r0, r3 + 8001e62: f7fe fb7f bl 8000564 <__aeabi_i2d> + 8001e66: 4604 mov r4, r0 + 8001e68: 460d mov r5, r1 + 8001e6a: ed97 0b06 vldr d0, [r7, #24] + 8001e6e: f01b fa3f bl 801d2f0 + 8001e72: ec59 8b10 vmov r8, r9, d0 + 8001e76: f04f 0200 mov.w r2, #0 + 8001e7a: 4b21 ldr r3, [pc, #132] ; (8001f00 ) + 8001e7c: e9d7 0100 ldrd r0, r1, [r7] + 8001e80: f7fe fa22 bl 80002c8 <__aeabi_dsub> + 8001e84: 4602 mov r2, r0 + 8001e86: 460b mov r3, r1 + 8001e88: 4640 mov r0, r8 + 8001e8a: 4649 mov r1, r9 + 8001e8c: f7fe fbd4 bl 8000638 <__aeabi_dmul> + 8001e90: 4602 mov r2, r0 + 8001e92: 460b mov r3, r1 + 8001e94: 4620 mov r0, r4 + 8001e96: 4629 mov r1, r5 + 8001e98: f7fe fa18 bl 80002cc <__adddf3> + 8001e9c: 4602 mov r2, r0 + 8001e9e: 460b mov r3, r1 + 8001ea0: 4610 mov r0, r2 + 8001ea2: 4619 mov r1, r3 + 8001ea4: f7fe fe8a bl 8000bbc <__aeabi_d2uiz> + 8001ea8: 4603 mov r3, r0 + 8001eaa: 823b strh r3, [r7, #16] + BSP_LCD_DisplayStringAt(x2 - offset[2*j], y2 - offset[2*j+1], (uint8_t*) number[j], LEFT_MODE); + 8001eac: 6a3b ldr r3, [r7, #32] + 8001eae: 005b lsls r3, r3, #1 + 8001eb0: 4a14 ldr r2, [pc, #80] ; (8001f04 ) + 8001eb2: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8001eb6: 8a7a ldrh r2, [r7, #18] + 8001eb8: 1ad3 subs r3, r2, r3 + 8001eba: b298 uxth r0, r3 + 8001ebc: 6a3b ldr r3, [r7, #32] + 8001ebe: 005b lsls r3, r3, #1 + 8001ec0: 3301 adds r3, #1 + 8001ec2: 4a10 ldr r2, [pc, #64] ; (8001f04 ) + 8001ec4: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8001ec8: 8a3a ldrh r2, [r7, #16] + 8001eca: 1ad3 subs r3, r2, r3 + 8001ecc: b299 uxth r1, r3 + 8001ece: 4a0e ldr r2, [pc, #56] ; (8001f08 ) + 8001ed0: 6a3b ldr r3, [r7, #32] + 8001ed2: f852 2023 ldr.w r2, [r2, r3, lsl #2] + 8001ed6: 2303 movs r3, #3 + 8001ed8: f001 fe16 bl 8003b08 + for (int j = 0; j < 12; j++) + 8001edc: 6a3b ldr r3, [r7, #32] + 8001ede: 3301 adds r3, #1 + 8001ee0: 623b str r3, [r7, #32] + 8001ee2: 6a3b ldr r3, [r7, #32] + 8001ee4: 2b0b cmp r3, #11 + 8001ee6: f77f aee9 ble.w 8001cbc + } +} + 8001eea: bf00 nop + 8001eec: bf00 nop + 8001eee: 3728 adds r7, #40 ; 0x28 + 8001ef0: 46bd mov sp, r7 + 8001ef2: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 8001ef6: bf00 nop + 8001ef8: 40668000 .word 0x40668000 + 8001efc: 40100000 .word 0x40100000 + 8001f00: 40200000 .word 0x40200000 + 8001f04: 08021854 .word 0x08021854 + 8001f08: 20000000 .word 0x20000000 + 8001f0c: 54442d18 .word 0x54442d18 + 8001f10: 400921fb .word 0x400921fb + 8001f14: 00000000 .word 0x00000000 + +08001f18 : + +void Clock_Draw_Hands(uint16_t xCenter, uint16_t yCenter, double radius, + uint8_t hours, uint8_t minutes, uint8_t seconds) +{ + 8001f18: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 8001f1c: b088 sub sp, #32 + 8001f1e: af00 add r7, sp, #0 + 8001f20: 4604 mov r4, r0 + 8001f22: 4608 mov r0, r1 + 8001f24: ed87 0b00 vstr d0, [r7] + 8001f28: 4611 mov r1, r2 + 8001f2a: 461a mov r2, r3 + 8001f2c: 4623 mov r3, r4 + 8001f2e: 81fb strh r3, [r7, #14] + 8001f30: 4603 mov r3, r0 + 8001f32: 81bb strh r3, [r7, #12] + 8001f34: 460b mov r3, r1 + 8001f36: 72fb strb r3, [r7, #11] + 8001f38: 4613 mov r3, r2 + 8001f3a: 72bb strb r3, [r7, #10] + uint16_t x2, y2; + double angle; + angle = seconds * 6; + 8001f3c: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 + 8001f40: 4613 mov r3, r2 + 8001f42: 005b lsls r3, r3, #1 + 8001f44: 4413 add r3, r2 + 8001f46: 005b lsls r3, r3, #1 + 8001f48: 4618 mov r0, r3 + 8001f4a: f7fe fb0b bl 8000564 <__aeabi_i2d> + 8001f4e: 4602 mov r2, r0 + 8001f50: 460b mov r3, r1 + 8001f52: e9c7 2306 strd r2, r3, [r7, #24] + angle = angle * M_PI / 180; + 8001f56: a3b6 add r3, pc, #728 ; (adr r3, 8002230 ) + 8001f58: e9d3 2300 ldrd r2, r3, [r3] + 8001f5c: e9d7 0106 ldrd r0, r1, [r7, #24] + 8001f60: f7fe fb6a bl 8000638 <__aeabi_dmul> + 8001f64: 4602 mov r2, r0 + 8001f66: 460b mov r3, r1 + 8001f68: 4610 mov r0, r2 + 8001f6a: 4619 mov r1, r3 + 8001f6c: f04f 0200 mov.w r2, #0 + 8001f70: 4bb1 ldr r3, [pc, #708] ; (8002238 ) + 8001f72: f7fe fc8b bl 800088c <__aeabi_ddiv> + 8001f76: 4602 mov r2, r0 + 8001f78: 460b mov r3, r1 + 8001f7a: e9c7 2306 strd r2, r3, [r7, #24] + x2 = xCenter + (sin(angle) * (radius - 30)); + 8001f7e: 89fb ldrh r3, [r7, #14] + 8001f80: 4618 mov r0, r3 + 8001f82: f7fe faef bl 8000564 <__aeabi_i2d> + 8001f86: 4604 mov r4, r0 + 8001f88: 460d mov r5, r1 + 8001f8a: ed97 0b06 vldr d0, [r7, #24] + 8001f8e: f01b fa03 bl 801d398 + 8001f92: ec59 8b10 vmov r8, r9, d0 + 8001f96: f04f 0200 mov.w r2, #0 + 8001f9a: 4ba8 ldr r3, [pc, #672] ; (800223c ) + 8001f9c: e9d7 0100 ldrd r0, r1, [r7] + 8001fa0: f7fe f992 bl 80002c8 <__aeabi_dsub> + 8001fa4: 4602 mov r2, r0 + 8001fa6: 460b mov r3, r1 + 8001fa8: 4640 mov r0, r8 + 8001faa: 4649 mov r1, r9 + 8001fac: f7fe fb44 bl 8000638 <__aeabi_dmul> + 8001fb0: 4602 mov r2, r0 + 8001fb2: 460b mov r3, r1 + 8001fb4: 4620 mov r0, r4 + 8001fb6: 4629 mov r1, r5 + 8001fb8: f7fe f988 bl 80002cc <__adddf3> + 8001fbc: 4602 mov r2, r0 + 8001fbe: 460b mov r3, r1 + 8001fc0: 4610 mov r0, r2 + 8001fc2: 4619 mov r1, r3 + 8001fc4: f7fe fdfa bl 8000bbc <__aeabi_d2uiz> + 8001fc8: 4603 mov r3, r0 + 8001fca: 82fb strh r3, [r7, #22] + y2 = yCenter - (cos(angle) * (radius - 30)); + 8001fcc: 89bb ldrh r3, [r7, #12] + 8001fce: 4618 mov r0, r3 + 8001fd0: f7fe fac8 bl 8000564 <__aeabi_i2d> + 8001fd4: 4604 mov r4, r0 + 8001fd6: 460d mov r5, r1 + 8001fd8: ed97 0b06 vldr d0, [r7, #24] + 8001fdc: f01b f988 bl 801d2f0 + 8001fe0: ec59 8b10 vmov r8, r9, d0 + 8001fe4: f04f 0200 mov.w r2, #0 + 8001fe8: 4b94 ldr r3, [pc, #592] ; (800223c ) + 8001fea: e9d7 0100 ldrd r0, r1, [r7] + 8001fee: f7fe f96b bl 80002c8 <__aeabi_dsub> + 8001ff2: 4602 mov r2, r0 + 8001ff4: 460b mov r3, r1 + 8001ff6: 4640 mov r0, r8 + 8001ff8: 4649 mov r1, r9 + 8001ffa: f7fe fb1d bl 8000638 <__aeabi_dmul> + 8001ffe: 4602 mov r2, r0 + 8002000: 460b mov r3, r1 + 8002002: 4620 mov r0, r4 + 8002004: 4629 mov r1, r5 + 8002006: f7fe f95f bl 80002c8 <__aeabi_dsub> + 800200a: 4602 mov r2, r0 + 800200c: 460b mov r3, r1 + 800200e: 4610 mov r0, r2 + 8002010: 4619 mov r1, r3 + 8002012: f7fe fdd3 bl 8000bbc <__aeabi_d2uiz> + 8002016: 4603 mov r3, r0 + 8002018: 82bb strh r3, [r7, #20] + BSP_LCD_DrawLine(xCenter, yCenter, x2, y2); + 800201a: 8abb ldrh r3, [r7, #20] + 800201c: 8afa ldrh r2, [r7, #22] + 800201e: 89b9 ldrh r1, [r7, #12] + 8002020: 89f8 ldrh r0, [r7, #14] + 8002022: f001 fe39 bl 8003c98 + + angle = minutes * 6 + (seconds / 10); + 8002026: 7aba ldrb r2, [r7, #10] + 8002028: 4613 mov r3, r2 + 800202a: 005b lsls r3, r3, #1 + 800202c: 4413 add r3, r2 + 800202e: 005b lsls r3, r3, #1 + 8002030: 4619 mov r1, r3 + 8002032: f897 3038 ldrb.w r3, [r7, #56] ; 0x38 + 8002036: 4a82 ldr r2, [pc, #520] ; (8002240 ) + 8002038: fba2 2303 umull r2, r3, r2, r3 + 800203c: 08db lsrs r3, r3, #3 + 800203e: b2db uxtb r3, r3 + 8002040: 440b add r3, r1 + 8002042: 4618 mov r0, r3 + 8002044: f7fe fa8e bl 8000564 <__aeabi_i2d> + 8002048: 4602 mov r2, r0 + 800204a: 460b mov r3, r1 + 800204c: e9c7 2306 strd r2, r3, [r7, #24] + angle = angle * M_PI / 180; + 8002050: a377 add r3, pc, #476 ; (adr r3, 8002230 ) + 8002052: e9d3 2300 ldrd r2, r3, [r3] + 8002056: e9d7 0106 ldrd r0, r1, [r7, #24] + 800205a: f7fe faed bl 8000638 <__aeabi_dmul> + 800205e: 4602 mov r2, r0 + 8002060: 460b mov r3, r1 + 8002062: 4610 mov r0, r2 + 8002064: 4619 mov r1, r3 + 8002066: f04f 0200 mov.w r2, #0 + 800206a: 4b73 ldr r3, [pc, #460] ; (8002238 ) + 800206c: f7fe fc0e bl 800088c <__aeabi_ddiv> + 8002070: 4602 mov r2, r0 + 8002072: 460b mov r3, r1 + 8002074: e9c7 2306 strd r2, r3, [r7, #24] + x2 = xCenter + (sin(angle) * (radius - 50)); + 8002078: 89fb ldrh r3, [r7, #14] + 800207a: 4618 mov r0, r3 + 800207c: f7fe fa72 bl 8000564 <__aeabi_i2d> + 8002080: 4604 mov r4, r0 + 8002082: 460d mov r5, r1 + 8002084: ed97 0b06 vldr d0, [r7, #24] + 8002088: f01b f986 bl 801d398 + 800208c: ec59 8b10 vmov r8, r9, d0 + 8002090: f04f 0200 mov.w r2, #0 + 8002094: 4b6b ldr r3, [pc, #428] ; (8002244 ) + 8002096: e9d7 0100 ldrd r0, r1, [r7] + 800209a: f7fe f915 bl 80002c8 <__aeabi_dsub> + 800209e: 4602 mov r2, r0 + 80020a0: 460b mov r3, r1 + 80020a2: 4640 mov r0, r8 + 80020a4: 4649 mov r1, r9 + 80020a6: f7fe fac7 bl 8000638 <__aeabi_dmul> + 80020aa: 4602 mov r2, r0 + 80020ac: 460b mov r3, r1 + 80020ae: 4620 mov r0, r4 + 80020b0: 4629 mov r1, r5 + 80020b2: f7fe f90b bl 80002cc <__adddf3> + 80020b6: 4602 mov r2, r0 + 80020b8: 460b mov r3, r1 + 80020ba: 4610 mov r0, r2 + 80020bc: 4619 mov r1, r3 + 80020be: f7fe fd7d bl 8000bbc <__aeabi_d2uiz> + 80020c2: 4603 mov r3, r0 + 80020c4: 82fb strh r3, [r7, #22] + y2 = yCenter - (cos(angle) * (radius - 50)); + 80020c6: 89bb ldrh r3, [r7, #12] + 80020c8: 4618 mov r0, r3 + 80020ca: f7fe fa4b bl 8000564 <__aeabi_i2d> + 80020ce: 4604 mov r4, r0 + 80020d0: 460d mov r5, r1 + 80020d2: ed97 0b06 vldr d0, [r7, #24] + 80020d6: f01b f90b bl 801d2f0 + 80020da: ec59 8b10 vmov r8, r9, d0 + 80020de: f04f 0200 mov.w r2, #0 + 80020e2: 4b58 ldr r3, [pc, #352] ; (8002244 ) + 80020e4: e9d7 0100 ldrd r0, r1, [r7] + 80020e8: f7fe f8ee bl 80002c8 <__aeabi_dsub> + 80020ec: 4602 mov r2, r0 + 80020ee: 460b mov r3, r1 + 80020f0: 4640 mov r0, r8 + 80020f2: 4649 mov r1, r9 + 80020f4: f7fe faa0 bl 8000638 <__aeabi_dmul> + 80020f8: 4602 mov r2, r0 + 80020fa: 460b mov r3, r1 + 80020fc: 4620 mov r0, r4 + 80020fe: 4629 mov r1, r5 + 8002100: f7fe f8e2 bl 80002c8 <__aeabi_dsub> + 8002104: 4602 mov r2, r0 + 8002106: 460b mov r3, r1 + 8002108: 4610 mov r0, r2 + 800210a: 4619 mov r1, r3 + 800210c: f7fe fd56 bl 8000bbc <__aeabi_d2uiz> + 8002110: 4603 mov r3, r0 + 8002112: 82bb strh r3, [r7, #20] + BSP_LCD_DrawLine(xCenter, yCenter, x2, y2); + 8002114: 8abb ldrh r3, [r7, #20] + 8002116: 8afa ldrh r2, [r7, #22] + 8002118: 89b9 ldrh r1, [r7, #12] + 800211a: 89f8 ldrh r0, [r7, #14] + 800211c: f001 fdbc bl 8003c98 + + angle = hours * 30 + ((minutes / 12) * 6); + 8002120: 7afa ldrb r2, [r7, #11] + 8002122: 4613 mov r3, r2 + 8002124: 011b lsls r3, r3, #4 + 8002126: 1a9b subs r3, r3, r2 + 8002128: 005b lsls r3, r3, #1 + 800212a: 4619 mov r1, r3 + 800212c: 7abb ldrb r3, [r7, #10] + 800212e: 4a46 ldr r2, [pc, #280] ; (8002248 ) + 8002130: fba2 2303 umull r2, r3, r2, r3 + 8002134: 08db lsrs r3, r3, #3 + 8002136: b2db uxtb r3, r3 + 8002138: 461a mov r2, r3 + 800213a: 4613 mov r3, r2 + 800213c: 005b lsls r3, r3, #1 + 800213e: 4413 add r3, r2 + 8002140: 005b lsls r3, r3, #1 + 8002142: 440b add r3, r1 + 8002144: 4618 mov r0, r3 + 8002146: f7fe fa0d bl 8000564 <__aeabi_i2d> + 800214a: 4602 mov r2, r0 + 800214c: 460b mov r3, r1 + 800214e: e9c7 2306 strd r2, r3, [r7, #24] + angle = angle * M_PI / 180; + 8002152: a337 add r3, pc, #220 ; (adr r3, 8002230 ) + 8002154: e9d3 2300 ldrd r2, r3, [r3] + 8002158: e9d7 0106 ldrd r0, r1, [r7, #24] + 800215c: f7fe fa6c bl 8000638 <__aeabi_dmul> + 8002160: 4602 mov r2, r0 + 8002162: 460b mov r3, r1 + 8002164: 4610 mov r0, r2 + 8002166: 4619 mov r1, r3 + 8002168: f04f 0200 mov.w r2, #0 + 800216c: 4b32 ldr r3, [pc, #200] ; (8002238 ) + 800216e: f7fe fb8d bl 800088c <__aeabi_ddiv> + 8002172: 4602 mov r2, r0 + 8002174: 460b mov r3, r1 + 8002176: e9c7 2306 strd r2, r3, [r7, #24] + x2 = xCenter + (sin(angle) * (radius / 4)); + 800217a: 89fb ldrh r3, [r7, #14] + 800217c: 4618 mov r0, r3 + 800217e: f7fe f9f1 bl 8000564 <__aeabi_i2d> + 8002182: 4604 mov r4, r0 + 8002184: 460d mov r5, r1 + 8002186: ed97 0b06 vldr d0, [r7, #24] + 800218a: f01b f905 bl 801d398 + 800218e: ec59 8b10 vmov r8, r9, d0 + 8002192: f04f 0200 mov.w r2, #0 + 8002196: 4b2d ldr r3, [pc, #180] ; (800224c ) + 8002198: e9d7 0100 ldrd r0, r1, [r7] + 800219c: f7fe fb76 bl 800088c <__aeabi_ddiv> + 80021a0: 4602 mov r2, r0 + 80021a2: 460b mov r3, r1 + 80021a4: 4640 mov r0, r8 + 80021a6: 4649 mov r1, r9 + 80021a8: f7fe fa46 bl 8000638 <__aeabi_dmul> + 80021ac: 4602 mov r2, r0 + 80021ae: 460b mov r3, r1 + 80021b0: 4620 mov r0, r4 + 80021b2: 4629 mov r1, r5 + 80021b4: f7fe f88a bl 80002cc <__adddf3> + 80021b8: 4602 mov r2, r0 + 80021ba: 460b mov r3, r1 + 80021bc: 4610 mov r0, r2 + 80021be: 4619 mov r1, r3 + 80021c0: f7fe fcfc bl 8000bbc <__aeabi_d2uiz> + 80021c4: 4603 mov r3, r0 + 80021c6: 82fb strh r3, [r7, #22] + y2 = yCenter - (cos(angle) * (radius / 4)); + 80021c8: 89bb ldrh r3, [r7, #12] + 80021ca: 4618 mov r0, r3 + 80021cc: f7fe f9ca bl 8000564 <__aeabi_i2d> + 80021d0: 4604 mov r4, r0 + 80021d2: 460d mov r5, r1 + 80021d4: ed97 0b06 vldr d0, [r7, #24] + 80021d8: f01b f88a bl 801d2f0 + 80021dc: ec59 8b10 vmov r8, r9, d0 + 80021e0: f04f 0200 mov.w r2, #0 + 80021e4: 4b19 ldr r3, [pc, #100] ; (800224c ) + 80021e6: e9d7 0100 ldrd r0, r1, [r7] + 80021ea: f7fe fb4f bl 800088c <__aeabi_ddiv> + 80021ee: 4602 mov r2, r0 + 80021f0: 460b mov r3, r1 + 80021f2: 4640 mov r0, r8 + 80021f4: 4649 mov r1, r9 + 80021f6: f7fe fa1f bl 8000638 <__aeabi_dmul> + 80021fa: 4602 mov r2, r0 + 80021fc: 460b mov r3, r1 + 80021fe: 4620 mov r0, r4 + 8002200: 4629 mov r1, r5 + 8002202: f7fe f861 bl 80002c8 <__aeabi_dsub> + 8002206: 4602 mov r2, r0 + 8002208: 460b mov r3, r1 + 800220a: 4610 mov r0, r2 + 800220c: 4619 mov r1, r3 + 800220e: f7fe fcd5 bl 8000bbc <__aeabi_d2uiz> + 8002212: 4603 mov r3, r0 + 8002214: 82bb strh r3, [r7, #20] + BSP_LCD_DrawLine(xCenter, yCenter, x2, y2); + 8002216: 8abb ldrh r3, [r7, #20] + 8002218: 8afa ldrh r2, [r7, #22] + 800221a: 89b9 ldrh r1, [r7, #12] + 800221c: 89f8 ldrh r0, [r7, #14] + 800221e: f001 fd3b bl 8003c98 +} + 8002222: bf00 nop + 8002224: 3720 adds r7, #32 + 8002226: 46bd mov sp, r7 + 8002228: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800222c: f3af 8000 nop.w + 8002230: 54442d18 .word 0x54442d18 + 8002234: 400921fb .word 0x400921fb + 8002238: 40668000 .word 0x40668000 + 800223c: 403e0000 .word 0x403e0000 + 8002240: cccccccd .word 0xcccccccd + 8002244: 40490000 .word 0x40490000 + 8002248: aaaaaaab .word 0xaaaaaaab + 800224c: 40100000 .word 0x40100000 + +08002250 : + +void Clock_Write_Date(uint16_t xCenter, uint16_t xOffset, uint16_t yCenter, uint16_t yOffset, uint8_t Wday, uint8_t Day, uint8_t Month, uint16_t Year) +{ + 8002250: b590 push {r4, r7, lr} + 8002252: b087 sub sp, #28 + 8002254: af00 add r7, sp, #0 + 8002256: 4604 mov r4, r0 + 8002258: 4608 mov r0, r1 + 800225a: 4611 mov r1, r2 + 800225c: 461a mov r2, r3 + 800225e: 4623 mov r3, r4 + 8002260: 80fb strh r3, [r7, #6] + 8002262: 4603 mov r3, r0 + 8002264: 80bb strh r3, [r7, #4] + 8002266: 460b mov r3, r1 + 8002268: 807b strh r3, [r7, #2] + 800226a: 4613 mov r3, r2 + 800226c: 803b strh r3, [r7, #0] + char buff[16]; + memset(buff, 0, 16); + 800226e: f107 0308 add.w r3, r7, #8 + 8002272: 2210 movs r2, #16 + 8002274: 2100 movs r1, #0 + 8002276: 4618 mov r0, r3 + 8002278: f019 fe2f bl 801beda + sprintf(buff, "%s %2u", days[Wday - 1], Day); + 800227c: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 8002280: 3b01 subs r3, #1 + 8002282: 4a1d ldr r2, [pc, #116] ; (80022f8 ) + 8002284: f852 2023 ldr.w r2, [r2, r3, lsl #2] + 8002288: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 800228c: f107 0008 add.w r0, r7, #8 + 8002290: 491a ldr r1, [pc, #104] ; (80022fc ) + 8002292: f01a f805 bl 801c2a0 + BSP_LCD_DisplayStringAt(xCenter - xOffset, yCenter - yOffset, (uint8_t*)buff, CENTER_MODE); + 8002296: 88fa ldrh r2, [r7, #6] + 8002298: 88bb ldrh r3, [r7, #4] + 800229a: 1ad3 subs r3, r2, r3 + 800229c: b298 uxth r0, r3 + 800229e: 887a ldrh r2, [r7, #2] + 80022a0: 883b ldrh r3, [r7, #0] + 80022a2: 1ad3 subs r3, r2, r3 + 80022a4: b299 uxth r1, r3 + 80022a6: f107 0208 add.w r2, r7, #8 + 80022aa: 2301 movs r3, #1 + 80022ac: f001 fc2c bl 8003b08 + memset(buff, 0, 16); + 80022b0: f107 0308 add.w r3, r7, #8 + 80022b4: 2210 movs r2, #16 + 80022b6: 2100 movs r1, #0 + 80022b8: 4618 mov r0, r3 + 80022ba: f019 fe0e bl 801beda + sprintf(buff, "%s %4u", months[Month - 1], Year); + 80022be: f897 3030 ldrb.w r3, [r7, #48] ; 0x30 + 80022c2: 3b01 subs r3, #1 + 80022c4: 4a0e ldr r2, [pc, #56] ; (8002300 ) + 80022c6: f852 2023 ldr.w r2, [r2, r3, lsl #2] + 80022ca: 8ebb ldrh r3, [r7, #52] ; 0x34 + 80022cc: f107 0008 add.w r0, r7, #8 + 80022d0: 490c ldr r1, [pc, #48] ; (8002304 ) + 80022d2: f019 ffe5 bl 801c2a0 + BSP_LCD_DisplayStringAt(xCenter + xOffset, yCenter + yOffset, (uint8_t*)buff, CENTER_MODE); + 80022d6: 88fa ldrh r2, [r7, #6] + 80022d8: 88bb ldrh r3, [r7, #4] + 80022da: 4413 add r3, r2 + 80022dc: b298 uxth r0, r3 + 80022de: 887a ldrh r2, [r7, #2] + 80022e0: 883b ldrh r3, [r7, #0] + 80022e2: 4413 add r3, r2 + 80022e4: b299 uxth r1, r3 + 80022e6: f107 0208 add.w r2, r7, #8 + 80022ea: 2301 movs r3, #1 + 80022ec: f001 fc0c bl 8003b08 +} + 80022f0: bf00 nop + 80022f2: 371c adds r7, #28 + 80022f4: 46bd mov sp, r7 + 80022f6: bd90 pop {r4, r7, pc} + 80022f8: 20000030 .word 0x20000030 + 80022fc: 0801e79c .word 0x0801e79c + 8002300: 2000004c .word 0x2000004c + 8002304: 0801e7a4 .word 0x0801e7a4 + +08002308 <_write>: + */ +#include "debug.h" + +extern UART_HandleTypeDef huart1; + +int _write(int file, char *ptr, int len) { + 8002308: b580 push {r7, lr} + 800230a: b086 sub sp, #24 + 800230c: af00 add r7, sp, #0 + 800230e: 60f8 str r0, [r7, #12] + 8002310: 60b9 str r1, [r7, #8] + 8002312: 607a str r2, [r7, #4] + HAL_StatusTypeDef xStatus; + switch (file) { + 8002314: 68fb ldr r3, [r7, #12] + 8002316: 2b01 cmp r3, #1 + 8002318: d003 beq.n 8002322 <_write+0x1a> + 800231a: 68fb ldr r3, [r7, #12] + 800231c: 2b02 cmp r3, #2 + 800231e: d013 beq.n 8002348 <_write+0x40> + 8002320: e025 b.n 800236e <_write+0x66> + case STDOUT_FILENO: /*stdout*/ + xStatus = HAL_UART_Transmit(&huart1, (uint8_t*)ptr, len, HAL_MAX_DELAY); + 8002322: 687b ldr r3, [r7, #4] + 8002324: b29a uxth r2, r3 + 8002326: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800232a: 68b9 ldr r1, [r7, #8] + 800232c: 4817 ldr r0, [pc, #92] ; (800238c <_write+0x84>) + 800232e: f007 fb11 bl 8009954 + 8002332: 4603 mov r3, r0 + 8002334: 75fb strb r3, [r7, #23] + if (xStatus != HAL_OK) { + 8002336: 7dfb ldrb r3, [r7, #23] + 8002338: 2b00 cmp r3, #0 + 800233a: d01e beq.n 800237a <_write+0x72> + errno = EIO; + 800233c: 4b14 ldr r3, [pc, #80] ; (8002390 <_write+0x88>) + 800233e: 2205 movs r2, #5 + 8002340: 601a str r2, [r3, #0] + return -1; + 8002342: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002346: e01c b.n 8002382 <_write+0x7a> + } + break; + case STDERR_FILENO: /* stderr */ + xStatus = HAL_UART_Transmit(&huart1, (uint8_t*)ptr, len, HAL_MAX_DELAY); + 8002348: 687b ldr r3, [r7, #4] + 800234a: b29a uxth r2, r3 + 800234c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002350: 68b9 ldr r1, [r7, #8] + 8002352: 480e ldr r0, [pc, #56] ; (800238c <_write+0x84>) + 8002354: f007 fafe bl 8009954 + 8002358: 4603 mov r3, r0 + 800235a: 75fb strb r3, [r7, #23] + if (xStatus != HAL_OK) { + 800235c: 7dfb ldrb r3, [r7, #23] + 800235e: 2b00 cmp r3, #0 + 8002360: d00d beq.n 800237e <_write+0x76> + errno = EIO; + 8002362: 4b0b ldr r3, [pc, #44] ; (8002390 <_write+0x88>) + 8002364: 2205 movs r2, #5 + 8002366: 601a str r2, [r3, #0] + return -1; + 8002368: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800236c: e009 b.n 8002382 <_write+0x7a> + } + break; + default: + errno = EBADF; + 800236e: 4b08 ldr r3, [pc, #32] ; (8002390 <_write+0x88>) + 8002370: 2209 movs r2, #9 + 8002372: 601a str r2, [r3, #0] + return -1; + 8002374: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002378: e003 b.n 8002382 <_write+0x7a> + break; + 800237a: bf00 nop + 800237c: e000 b.n 8002380 <_write+0x78> + break; + 800237e: bf00 nop + } + return len; + 8002380: 687b ldr r3, [r7, #4] +} + 8002382: 4618 mov r0, r3 + 8002384: 3718 adds r7, #24 + 8002386: 46bd mov sp, r7 + 8002388: bd80 pop {r7, pc} + 800238a: bf00 nop + 800238c: 20000648 .word 0x20000648 + 8002390: 2000d0ec .word 0x2000d0ec + +08002394 <_read>: + +int _read(int fd, char* ptr, int len) { + 8002394: b580 push {r7, lr} + 8002396: b086 sub sp, #24 + 8002398: af00 add r7, sp, #0 + 800239a: 60f8 str r0, [r7, #12] + 800239c: 60b9 str r1, [r7, #8] + 800239e: 607a str r2, [r7, #4] + HAL_StatusTypeDef hstatus; + + if (fd == STDIN_FILENO) { + 80023a0: 68fb ldr r3, [r7, #12] + 80023a2: 2b00 cmp r3, #0 + 80023a4: d10f bne.n 80023c6 <_read+0x32> + hstatus = HAL_UART_Receive(&huart1, (uint8_t *) ptr, 1, HAL_MAX_DELAY); + 80023a6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80023aa: 2201 movs r2, #1 + 80023ac: 68b9 ldr r1, [r7, #8] + 80023ae: 480a ldr r0, [pc, #40] ; (80023d8 <_read+0x44>) + 80023b0: f007 fb53 bl 8009a5a + 80023b4: 4603 mov r3, r0 + 80023b6: 75fb strb r3, [r7, #23] + if (hstatus == HAL_OK) + 80023b8: 7dfb ldrb r3, [r7, #23] + 80023ba: 2b00 cmp r3, #0 + 80023bc: d101 bne.n 80023c2 <_read+0x2e> + return 1; + 80023be: 2301 movs r3, #1 + 80023c0: e006 b.n 80023d0 <_read+0x3c> + else + return EIO; + 80023c2: 2305 movs r3, #5 + 80023c4: e004 b.n 80023d0 <_read+0x3c> + } + errno = EBADF; + 80023c6: 4b05 ldr r3, [pc, #20] ; (80023dc <_read+0x48>) + 80023c8: 2209 movs r2, #9 + 80023ca: 601a str r2, [r3, #0] + return -1; + 80023cc: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 80023d0: 4618 mov r0, r3 + 80023d2: 3718 adds r7, #24 + 80023d4: 46bd mov sp, r7 + 80023d6: bd80 pop {r7, pc} + 80023d8: 20000648 .word 0x20000648 + 80023dc: 2000d0ec .word 0x2000d0ec + +080023e0 : +/** + * @brief Set the byte in the designated DS3231 register to value. + * @param regAddr Register address to write. + * @param val Value to set, 0 to 255. + */ +void DS3231_SetRegByte(uint8_t regAddr, uint8_t val) { + 80023e0: b580 push {r7, lr} + 80023e2: b086 sub sp, #24 + 80023e4: af02 add r7, sp, #8 + 80023e6: 4603 mov r3, r0 + 80023e8: 460a mov r2, r1 + 80023ea: 71fb strb r3, [r7, #7] + 80023ec: 4613 mov r3, r2 + 80023ee: 71bb strb r3, [r7, #6] + uint8_t bytes[2] = { regAddr, val }; + 80023f0: 79fb ldrb r3, [r7, #7] + 80023f2: 733b strb r3, [r7, #12] + 80023f4: 79bb ldrb r3, [r7, #6] + 80023f6: 737b strb r3, [r7, #13] + HAL_I2C_Master_Transmit(_ds3231_ui2c, DS3231_I2C_ADDR << 1, bytes, 2, DS3231_TIMEOUT); + 80023f8: 4b07 ldr r3, [pc, #28] ; (8002418 ) + 80023fa: 6818 ldr r0, [r3, #0] + 80023fc: f107 020c add.w r2, r7, #12 + 8002400: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002404: 9300 str r3, [sp, #0] + 8002406: 2302 movs r3, #2 + 8002408: 21d0 movs r1, #208 ; 0xd0 + 800240a: f004 fba3 bl 8006b54 +} + 800240e: bf00 nop + 8002410: 3710 adds r7, #16 + 8002412: 46bd mov sp, r7 + 8002414: bd80 pop {r7, pc} + 8002416: bf00 nop + 8002418: 20000288 .word 0x20000288 + +0800241c : +/** + * @brief Gets the byte in the designated DS3231 register. + * @param regAddr Register address to read. + * @return Value stored in the register, 0 to 255. + */ +uint8_t DS3231_GetRegByte(uint8_t regAddr) { + 800241c: b580 push {r7, lr} + 800241e: b086 sub sp, #24 + 8002420: af02 add r7, sp, #8 + 8002422: 4603 mov r3, r0 + 8002424: 71fb strb r3, [r7, #7] + uint8_t val; + HAL_I2C_Master_Transmit(_ds3231_ui2c, DS3231_I2C_ADDR << 1, ®Addr, 1, DS3231_TIMEOUT); + 8002426: 4b0d ldr r3, [pc, #52] ; (800245c ) + 8002428: 6818 ldr r0, [r3, #0] + 800242a: 1dfa adds r2, r7, #7 + 800242c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002430: 9300 str r3, [sp, #0] + 8002432: 2301 movs r3, #1 + 8002434: 21d0 movs r1, #208 ; 0xd0 + 8002436: f004 fb8d bl 8006b54 + HAL_I2C_Master_Receive(_ds3231_ui2c, DS3231_I2C_ADDR << 1, &val, 1, DS3231_TIMEOUT); + 800243a: 4b08 ldr r3, [pc, #32] ; (800245c ) + 800243c: 6818 ldr r0, [r3, #0] + 800243e: f107 020f add.w r2, r7, #15 + 8002442: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002446: 9300 str r3, [sp, #0] + 8002448: 2301 movs r3, #1 + 800244a: 21d0 movs r1, #208 ; 0xd0 + 800244c: f004 fc76 bl 8006d3c + return val; + 8002450: 7bfb ldrb r3, [r7, #15] +} + 8002452: 4618 mov r0, r3 + 8002454: 3710 adds r7, #16 + 8002456: 46bd mov sp, r7 + 8002458: bd80 pop {r7, pc} + 800245a: bf00 nop + 800245c: 20000288 .word 0x20000288 + +08002460 : + * @brief Set the current time-> + * + * @param time Second, Minute, Hour, Day, Wday, Month, Year fields are used. + */ +void DS3231_SetTime(ts* time) +{ + 8002460: b580 push {r7, lr} + 8002462: b084 sub sp, #16 + 8002464: af00 add r7, sp, #0 + 8002466: 6078 str r0, [r7, #4] + uint8_t century; + uint8_t monthReg; + DS3231_SetRegByte(DS3231_REG_SECOND, DS3231_EncodeBCD(time->Second)); + 8002468: 687b ldr r3, [r7, #4] + 800246a: 781b ldrb r3, [r3, #0] + 800246c: 4618 mov r0, r3 + 800246e: f000 f883 bl 8002578 + 8002472: 4603 mov r3, r0 + 8002474: 4619 mov r1, r3 + 8002476: 2000 movs r0, #0 + 8002478: f7ff ffb2 bl 80023e0 + DS3231_SetRegByte(DS3231_REG_MINUTE, DS3231_EncodeBCD(time->Minute)); + 800247c: 687b ldr r3, [r7, #4] + 800247e: 785b ldrb r3, [r3, #1] + 8002480: 4618 mov r0, r3 + 8002482: f000 f879 bl 8002578 + 8002486: 4603 mov r3, r0 + 8002488: 4619 mov r1, r3 + 800248a: 2001 movs r0, #1 + 800248c: f7ff ffa8 bl 80023e0 + DS3231_SetRegByte(DS3231_REG_HOUR, DS3231_EncodeBCD(time->Hour)); + 8002490: 687b ldr r3, [r7, #4] + 8002492: 789b ldrb r3, [r3, #2] + 8002494: 4618 mov r0, r3 + 8002496: f000 f86f bl 8002578 + 800249a: 4603 mov r3, r0 + 800249c: 4619 mov r1, r3 + 800249e: 2002 movs r0, #2 + 80024a0: f7ff ff9e bl 80023e0 + DS3231_SetRegByte(DS3231_REG_DATE, DS3231_EncodeBCD(time->Day)); + 80024a4: 687b ldr r3, [r7, #4] + 80024a6: 78db ldrb r3, [r3, #3] + 80024a8: 4618 mov r0, r3 + 80024aa: f000 f865 bl 8002578 + 80024ae: 4603 mov r3, r0 + 80024b0: 4619 mov r1, r3 + 80024b2: 2004 movs r0, #4 + 80024b4: f7ff ff94 bl 80023e0 + DS3231_SetRegByte(DS3231_REG_DOW, DS3231_EncodeBCD(time->Wday)); + 80024b8: 687b ldr r3, [r7, #4] + 80024ba: 7a1b ldrb r3, [r3, #8] + 80024bc: 4618 mov r0, r3 + 80024be: f000 f85b bl 8002578 + 80024c2: 4603 mov r3, r0 + 80024c4: 4619 mov r1, r3 + 80024c6: 2003 movs r0, #3 + 80024c8: f7ff ff8a bl 80023e0 + DS3231_SetRegByte(DS3231_REG_MONTH, DS3231_EncodeBCD(time->Month)); + 80024cc: 687b ldr r3, [r7, #4] + 80024ce: 791b ldrb r3, [r3, #4] + 80024d0: 4618 mov r0, r3 + 80024d2: f000 f851 bl 8002578 + 80024d6: 4603 mov r3, r0 + 80024d8: 4619 mov r1, r3 + 80024da: 2005 movs r0, #5 + 80024dc: f7ff ff80 bl 80023e0 + century = ((time->Year + 1970) / 100) % 20; + 80024e0: 687b ldr r3, [r7, #4] + 80024e2: f9b3 3006 ldrsh.w r3, [r3, #6] + 80024e6: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 80024ea: 4a21 ldr r2, [pc, #132] ; (8002570 ) + 80024ec: fb82 1203 smull r1, r2, r2, r3 + 80024f0: 1152 asrs r2, r2, #5 + 80024f2: 17db asrs r3, r3, #31 + 80024f4: 1ad2 subs r2, r2, r3 + 80024f6: 4b1f ldr r3, [pc, #124] ; (8002574 ) + 80024f8: fb83 1302 smull r1, r3, r3, r2 + 80024fc: 10d9 asrs r1, r3, #3 + 80024fe: 17d3 asrs r3, r2, #31 + 8002500: 1ac9 subs r1, r1, r3 + 8002502: 460b mov r3, r1 + 8002504: 009b lsls r3, r3, #2 + 8002506: 440b add r3, r1 + 8002508: 009b lsls r3, r3, #2 + 800250a: 1ad1 subs r1, r2, r3 + 800250c: 460b mov r3, r1 + 800250e: 73fb strb r3, [r7, #15] + monthReg = (DS3231_GetRegByte(DS3231_REG_MONTH) & 0x7f) | (century << DS3231_CENTURY); + 8002510: 2005 movs r0, #5 + 8002512: f7ff ff83 bl 800241c + 8002516: 4603 mov r3, r0 + 8002518: b25b sxtb r3, r3 + 800251a: f003 037f and.w r3, r3, #127 ; 0x7f + 800251e: b25a sxtb r2, r3 + 8002520: 7bfb ldrb r3, [r7, #15] + 8002522: 01db lsls r3, r3, #7 + 8002524: b25b sxtb r3, r3 + 8002526: 4313 orrs r3, r2 + 8002528: b25b sxtb r3, r3 + 800252a: 73bb strb r3, [r7, #14] + DS3231_SetRegByte(DS3231_REG_MONTH, monthReg); + 800252c: 7bbb ldrb r3, [r7, #14] + 800252e: 4619 mov r1, r3 + 8002530: 2005 movs r0, #5 + 8002532: f7ff ff55 bl 80023e0 + DS3231_SetRegByte(DS3231_REG_YEAR, DS3231_EncodeBCD((time->Year + 1970) % 100)); + 8002536: 687b ldr r3, [r7, #4] + 8002538: f9b3 3006 ldrsh.w r3, [r3, #6] + 800253c: f203 73b2 addw r3, r3, #1970 ; 0x7b2 + 8002540: 4a0b ldr r2, [pc, #44] ; (8002570 ) + 8002542: fb82 1203 smull r1, r2, r2, r3 + 8002546: 1151 asrs r1, r2, #5 + 8002548: 17da asrs r2, r3, #31 + 800254a: 1a8a subs r2, r1, r2 + 800254c: 2164 movs r1, #100 ; 0x64 + 800254e: fb01 f202 mul.w r2, r1, r2 + 8002552: 1a9a subs r2, r3, r2 + 8002554: b2d3 uxtb r3, r2 + 8002556: 4618 mov r0, r3 + 8002558: f000 f80e bl 8002578 + 800255c: 4603 mov r3, r0 + 800255e: 4619 mov r1, r3 + 8002560: 2006 movs r0, #6 + 8002562: f7ff ff3d bl 80023e0 +} + 8002566: bf00 nop + 8002568: 3710 adds r7, #16 + 800256a: 46bd mov sp, r7 + 800256c: bd80 pop {r7, pc} + 800256e: bf00 nop + 8002570: 51eb851f .word 0x51eb851f + 8002574: 66666667 .word 0x66666667 + +08002578 : +/** + * @brief Encodes a decimal number to binaty-coded decimal for storage in registers. + * @param dec Decimal number to encode. + * @return Encoded binary-coded decimal value. + */ +uint8_t DS3231_EncodeBCD(uint8_t dec) { + 8002578: b480 push {r7} + 800257a: b083 sub sp, #12 + 800257c: af00 add r7, sp, #0 + 800257e: 4603 mov r3, r0 + 8002580: 71fb strb r3, [r7, #7] + return (dec % 10 + ((dec / 10) << 4)); + 8002582: 79fa ldrb r2, [r7, #7] + 8002584: 4b0c ldr r3, [pc, #48] ; (80025b8 ) + 8002586: fba3 1302 umull r1, r3, r3, r2 + 800258a: 08d9 lsrs r1, r3, #3 + 800258c: 460b mov r3, r1 + 800258e: 009b lsls r3, r3, #2 + 8002590: 440b add r3, r1 + 8002592: 005b lsls r3, r3, #1 + 8002594: 1ad3 subs r3, r2, r3 + 8002596: b2da uxtb r2, r3 + 8002598: 79fb ldrb r3, [r7, #7] + 800259a: 4907 ldr r1, [pc, #28] ; (80025b8 ) + 800259c: fba1 1303 umull r1, r3, r1, r3 + 80025a0: 08db lsrs r3, r3, #3 + 80025a2: b2db uxtb r3, r3 + 80025a4: 011b lsls r3, r3, #4 + 80025a6: b2db uxtb r3, r3 + 80025a8: 4413 add r3, r2 + 80025aa: b2db uxtb r3, r3 +} + 80025ac: 4618 mov r0, r3 + 80025ae: 370c adds r7, #12 + 80025b0: 46bd mov sp, r7 + 80025b2: f85d 7b04 ldr.w r7, [sp], #4 + 80025b6: 4770 bx lr + 80025b8: cccccccd .word 0xcccccccd + +080025bc : +/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ +static StaticTask_t xIdleTaskTCBBuffer; +static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; + +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ + 80025bc: b480 push {r7} + 80025be: b085 sub sp, #20 + 80025c0: af00 add r7, sp, #0 + 80025c2: 60f8 str r0, [r7, #12] + 80025c4: 60b9 str r1, [r7, #8] + 80025c6: 607a str r2, [r7, #4] + *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer; + 80025c8: 68fb ldr r3, [r7, #12] + 80025ca: 4a07 ldr r2, [pc, #28] ; (80025e8 ) + 80025cc: 601a str r2, [r3, #0] + *ppxIdleTaskStackBuffer = &xIdleStack[0]; + 80025ce: 68bb ldr r3, [r7, #8] + 80025d0: 4a06 ldr r2, [pc, #24] ; (80025ec ) + 80025d2: 601a str r2, [r3, #0] + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + 80025d4: 687b ldr r3, [r7, #4] + 80025d6: 2280 movs r2, #128 ; 0x80 + 80025d8: 601a str r2, [r3, #0] + /* place for user code */ +} + 80025da: bf00 nop + 80025dc: 3714 adds r7, #20 + 80025de: 46bd mov sp, r7 + 80025e0: f85d 7b04 ldr.w r7, [sp], #4 + 80025e4: 4770 bx lr + 80025e6: bf00 nop + 80025e8: 2000028c .word 0x2000028c + 80025ec: 20000340 .word 0x20000340 + +080025f0
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80025f0: b5b0 push {r4, r5, r7, lr} + 80025f2: b088 sub sp, #32 + 80025f4: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80025f6: f002 f91b bl 8004830 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80025fa: f000 f887 bl 800270c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80025fe: f000 fa8d bl 8002b1c + MX_LTDC_Init(); + 8002602: f000 f92d bl 8002860 + MX_USART1_UART_Init(); + 8002606: f000 fa0b bl 8002a20 + MX_DMA2D_Init(); + 800260a: f000 f8f7 bl 80027fc + MX_FMC_Init(); + 800260e: f000 fa37 bl 8002a80 + MX_RTC_Init(); + 8002612: f000 f9df bl 80029d4 + /* USER CODE BEGIN 2 */ + ip_addr_t ip; + /* set the default dns server for the NTP client*/ + debugln("Setting default dns server"); + 8002616: 4831 ldr r0, [pc, #196] ; (80026dc ) + 8002618: f019 fd82 bl 801c120 + IP4_ADDR(&ip, 8, 8, 8, 8); + 800261c: f04f 3308 mov.w r3, #134744072 ; 0x8080808 + 8002620: 61fb str r3, [r7, #28] + dns_setserver(0, &ip); + 8002622: f107 031c add.w r3, r7, #28 + 8002626: 4619 mov r1, r3 + 8002628: 2000 movs r0, #0 + 800262a: f00b fe71 bl 800e310 + + /* Backlight */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET); + 800262e: 2201 movs r2, #1 + 8002630: 2108 movs r1, #8 + 8002632: 482b ldr r0, [pc, #172] ; (80026e0 ) + 8002634: f004 fa74 bl 8006b20 + /* Assert display enable LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET); + 8002638: 2201 movs r2, #1 + 800263a: f44f 5180 mov.w r1, #4096 ; 0x1000 + 800263e: 4829 ldr r0, [pc, #164] ; (80026e4 ) + 8002640: f004 fa6e bl 8006b20 + + BSP_LCD_Init(); + 8002644: f001 f8a0 bl 8003788 + BSP_LCD_LayerDefaultInit(1, LCD_FB_START_ADDRESS); + 8002648: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000 + 800264c: 2001 movs r0, #1 + 800264e: f001 f933 bl 80038b8 + BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS + (480 * 272 * 4)); + 8002652: 4925 ldr r1, [pc, #148] ; (80026e8 ) + 8002654: 2000 movs r0, #0 + 8002656: f001 f92f bl 80038b8 + /* Enable the LCD */ + BSP_LCD_DisplayOn(); + 800265a: f001 fd1b bl 8004094 + /* Select the LCD Background Layer */ + BSP_LCD_SelectLayer(0); + 800265e: 2000 movs r0, #0 + 8002660: f001 f98a bl 8003978 + /* Clear the Background Layer */ + BSP_LCD_Clear(LCD_COLOR_BLACK); + 8002664: f04f 407f mov.w r0, #4278190080 ; 0xff000000 + 8002668: f001 f9e2 bl 8003a30 + BSP_LCD_SelectLayer(1); + 800266c: 2001 movs r0, #1 + 800266e: f001 f983 bl 8003978 + /* Clear the foreground Layer */ + BSP_LCD_Clear(LCD_COLOR_TRANSPARENT); + 8002672: 2000 movs r0, #0 + 8002674: f001 f9dc bl 8003a30 + /* Some sign */ + BSP_LCD_SetTextColor(LCD_COLOR_WHITE); + 8002678: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800267c: f001 f98c bl 8003998 + BSP_LCD_SetBackColor(LCD_COLOR_BLACK); + 8002680: f04f 407f mov.w r0, #4278190080 ; 0xff000000 + 8002684: f001 f9a0 bl 80039c8 + BSP_LCD_SetFont(&Font12); + 8002688: 4818 ldr r0, [pc, #96] ; (80026ec ) + 800268a: f001 f9b7 bl 80039fc + BSP_LCD_DisplayStringAt(0, 0, (uint8_t*) "Initializing...", CENTER_MODE); + 800268e: 2301 movs r3, #1 + 8002690: 4a17 ldr r2, [pc, #92] ; (80026f0 ) + 8002692: 2100 movs r1, #0 + 8002694: 2000 movs r0, #0 + 8002696: f001 fa37 bl 8003b08 + printf(CLEAR_SCREEN); + 800269a: 4816 ldr r0, [pc, #88] ; (80026f4 ) + 800269c: f019 fcba bl 801c014 + debugln("Display is initialized"); + 80026a0: 4815 ldr r0, [pc, #84] ; (80026f8 ) + 80026a2: f019 fd3d bl 801c120 + /* USER CODE END 2 */ + + /* USER CODE BEGIN RTOS_MUTEX */ + debugln("Kernel initialized"); + 80026a6: 4815 ldr r0, [pc, #84] ; (80026fc ) + 80026a8: f019 fd3a bl 801c120 + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* definition and creation of app */ + osThreadDef(app, app_main, osPriorityNormal, 0, 2048); + 80026ac: 4b14 ldr r3, [pc, #80] ; (8002700 ) + 80026ae: 463c mov r4, r7 + 80026b0: 461d mov r5, r3 + 80026b2: cd0f ldmia r5!, {r0, r1, r2, r3} + 80026b4: c40f stmia r4!, {r0, r1, r2, r3} + 80026b6: e895 0007 ldmia.w r5, {r0, r1, r2} + 80026ba: e884 0007 stmia.w r4, {r0, r1, r2} + appHandle = osThreadCreate(osThread(app), NULL); + 80026be: 463b mov r3, r7 + 80026c0: 2100 movs r1, #0 + 80026c2: 4618 mov r0, r3 + 80026c4: f008 fcfa bl 800b0bc + 80026c8: 4603 mov r3, r0 + 80026ca: 4a0e ldr r2, [pc, #56] ; (8002704 ) + 80026cc: 6013 str r3, [r2, #0] + + /* USER CODE BEGIN RTOS_THREADS */ + debugln("appHandle created"); + 80026ce: 480e ldr r0, [pc, #56] ; (8002708 ) + 80026d0: f019 fd26 bl 801c120 + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* Start scheduler */ + osKernelStart(); + 80026d4: f008 fcdb bl 800b08e + + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + 80026d8: e7fe b.n 80026d8 + 80026da: bf00 nop + 80026dc: 0801e7b0 .word 0x0801e7b0 + 80026e0: 40022800 .word 0x40022800 + 80026e4: 40022000 .word 0x40022000 + 80026e8: c007f800 .word 0xc007f800 + 80026ec: 20000088 .word 0x20000088 + 80026f0: 0801e7d4 .word 0x0801e7d4 + 80026f4: 0801e7e4 .word 0x0801e7e4 + 80026f8: 0801e7e8 .word 0x0801e7e8 + 80026fc: 0801e808 .word 0x0801e808 + 8002700: 0801e840 .word 0x0801e840 + 8002704: 20000704 .word 0x20000704 + 8002708: 0801e824 .word 0x0801e824 + +0800270c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800270c: b580 push {r7, lr} + 800270e: b094 sub sp, #80 ; 0x50 + 8002710: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8002712: f107 0320 add.w r3, r7, #32 + 8002716: 2230 movs r2, #48 ; 0x30 + 8002718: 2100 movs r1, #0 + 800271a: 4618 mov r0, r3 + 800271c: f019 fbdd bl 801beda + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8002720: f107 030c add.w r3, r7, #12 + 8002724: 2200 movs r2, #0 + 8002726: 601a str r2, [r3, #0] + 8002728: 605a str r2, [r3, #4] + 800272a: 609a str r2, [r3, #8] + 800272c: 60da str r2, [r3, #12] + 800272e: 611a str r2, [r3, #16] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 8002730: f005 f91c bl 800796c + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + 8002734: 4b2f ldr r3, [pc, #188] ; (80027f4 ) + 8002736: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002738: 4a2e ldr r2, [pc, #184] ; (80027f4 ) + 800273a: f023 0318 bic.w r3, r3, #24 + 800273e: 6713 str r3, [r2, #112] ; 0x70 + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8002740: 4b2c ldr r3, [pc, #176] ; (80027f4 ) + 8002742: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002744: 4a2b ldr r2, [pc, #172] ; (80027f4 ) + 8002746: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800274a: 6413 str r3, [r2, #64] ; 0x40 + 800274c: 4b29 ldr r3, [pc, #164] ; (80027f4 ) + 800274e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002750: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002754: 60bb str r3, [r7, #8] + 8002756: 68bb ldr r3, [r7, #8] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8002758: 4b27 ldr r3, [pc, #156] ; (80027f8 ) + 800275a: 681b ldr r3, [r3, #0] + 800275c: 4a26 ldr r2, [pc, #152] ; (80027f8 ) + 800275e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8002762: 6013 str r3, [r2, #0] + 8002764: 4b24 ldr r3, [pc, #144] ; (80027f8 ) + 8002766: 681b ldr r3, [r3, #0] + 8002768: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 800276c: 607b str r3, [r7, #4] + 800276e: 687b ldr r3, [r7, #4] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; + 8002770: 2305 movs r3, #5 + 8002772: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8002774: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8002778: 627b str r3, [r7, #36] ; 0x24 + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 800277a: 2301 movs r3, #1 + 800277c: 62bb str r3, [r7, #40] ; 0x28 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 800277e: 2302 movs r3, #2 + 8002780: 63bb str r3, [r7, #56] ; 0x38 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8002782: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 8002786: 63fb str r3, [r7, #60] ; 0x3c + RCC_OscInitStruct.PLL.PLLM = 25; + 8002788: 2319 movs r3, #25 + 800278a: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.PLL.PLLN = 400; + 800278c: f44f 73c8 mov.w r3, #400 ; 0x190 + 8002790: 647b str r3, [r7, #68] ; 0x44 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 8002792: 2302 movs r3, #2 + 8002794: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLQ = 2; + 8002796: 2302 movs r3, #2 + 8002798: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800279a: f107 0320 add.w r3, r7, #32 + 800279e: 4618 mov r0, r3 + 80027a0: f005 f944 bl 8007a2c + 80027a4: 4603 mov r3, r0 + 80027a6: 2b00 cmp r3, #0 + 80027a8: d001 beq.n 80027ae + { + Error_Handler(); + 80027aa: f000 fa97 bl 8002cdc + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + 80027ae: f005 f8ed bl 800798c + 80027b2: 4603 mov r3, r0 + 80027b4: 2b00 cmp r3, #0 + 80027b6: d001 beq.n 80027bc + { + Error_Handler(); + 80027b8: f000 fa90 bl 8002cdc + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80027bc: 230f movs r3, #15 + 80027be: 60fb str r3, [r7, #12] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 80027c0: 2302 movs r3, #2 + 80027c2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80027c4: 2300 movs r3, #0 + 80027c6: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 80027c8: f44f 53a0 mov.w r3, #5120 ; 0x1400 + 80027cc: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 80027ce: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80027d2: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) + 80027d4: f107 030c add.w r3, r7, #12 + 80027d8: 2106 movs r1, #6 + 80027da: 4618 mov r0, r3 + 80027dc: f005 fbca bl 8007f74 + 80027e0: 4603 mov r3, r0 + 80027e2: 2b00 cmp r3, #0 + 80027e4: d001 beq.n 80027ea + { + Error_Handler(); + 80027e6: f000 fa79 bl 8002cdc + } +} + 80027ea: bf00 nop + 80027ec: 3750 adds r7, #80 ; 0x50 + 80027ee: 46bd mov sp, r7 + 80027f0: bd80 pop {r7, pc} + 80027f2: bf00 nop + 80027f4: 40023800 .word 0x40023800 + 80027f8: 40007000 .word 0x40007000 + +080027fc : + * @brief DMA2D Initialization Function + * @param None + * @retval None + */ +static void MX_DMA2D_Init(void) +{ + 80027fc: b580 push {r7, lr} + 80027fe: af00 add r7, sp, #0 + /* USER CODE END DMA2D_Init 0 */ + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + hdma2d.Instance = DMA2D; + 8002800: 4b15 ldr r3, [pc, #84] ; (8002858 ) + 8002802: 4a16 ldr r2, [pc, #88] ; (800285c ) + 8002804: 601a str r2, [r3, #0] + hdma2d.Init.Mode = DMA2D_M2M; + 8002806: 4b14 ldr r3, [pc, #80] ; (8002858 ) + 8002808: 2200 movs r2, #0 + 800280a: 605a str r2, [r3, #4] + hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; + 800280c: 4b12 ldr r3, [pc, #72] ; (8002858 ) + 800280e: 2200 movs r2, #0 + 8002810: 609a str r2, [r3, #8] + hdma2d.Init.OutputOffset = 0; + 8002812: 4b11 ldr r3, [pc, #68] ; (8002858 ) + 8002814: 2200 movs r2, #0 + 8002816: 60da str r2, [r3, #12] + hdma2d.LayerCfg[1].InputOffset = 0; + 8002818: 4b0f ldr r3, [pc, #60] ; (8002858 ) + 800281a: 2200 movs r2, #0 + 800281c: 629a str r2, [r3, #40] ; 0x28 + hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + 800281e: 4b0e ldr r3, [pc, #56] ; (8002858 ) + 8002820: 2200 movs r2, #0 + 8002822: 62da str r2, [r3, #44] ; 0x2c + hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + 8002824: 4b0c ldr r3, [pc, #48] ; (8002858 ) + 8002826: 2200 movs r2, #0 + 8002828: 631a str r2, [r3, #48] ; 0x30 + hdma2d.LayerCfg[1].InputAlpha = 0; + 800282a: 4b0b ldr r3, [pc, #44] ; (8002858 ) + 800282c: 2200 movs r2, #0 + 800282e: 635a str r2, [r3, #52] ; 0x34 + if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) + 8002830: 4809 ldr r0, [pc, #36] ; (8002858 ) + 8002832: f002 faef bl 8004e14 + 8002836: 4603 mov r3, r0 + 8002838: 2b00 cmp r3, #0 + 800283a: d001 beq.n 8002840 + { + Error_Handler(); + 800283c: f000 fa4e bl 8002cdc + } + if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) + 8002840: 2101 movs r1, #1 + 8002842: 4805 ldr r0, [pc, #20] ; (8002858 ) + 8002844: f002 fc44 bl 80050d0 + 8002848: 4603 mov r3, r0 + 800284a: 2b00 cmp r3, #0 + 800284c: d001 beq.n 8002852 + { + Error_Handler(); + 800284e: f000 fa45 bl 8002cdc + } + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + 8002852: bf00 nop + 8002854: bd80 pop {r7, pc} + 8002856: bf00 nop + 8002858: 20000540 .word 0x20000540 + 800285c: 4002b000 .word 0x4002b000 + +08002860 : + * @brief LTDC Initialization Function + * @param None + * @retval None + */ +static void MX_LTDC_Init(void) +{ + 8002860: b580 push {r7, lr} + 8002862: b09a sub sp, #104 ; 0x68 + 8002864: af00 add r7, sp, #0 + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + 8002866: f107 0334 add.w r3, r7, #52 ; 0x34 + 800286a: 2234 movs r2, #52 ; 0x34 + 800286c: 2100 movs r1, #0 + 800286e: 4618 mov r0, r3 + 8002870: f019 fb33 bl 801beda + LTDC_LayerCfgTypeDef pLayerCfg1 = {0}; + 8002874: 463b mov r3, r7 + 8002876: 2234 movs r2, #52 ; 0x34 + 8002878: 2100 movs r1, #0 + 800287a: 4618 mov r0, r3 + 800287c: f019 fb2d bl 801beda + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + 8002880: 4b52 ldr r3, [pc, #328] ; (80029cc ) + 8002882: 4a53 ldr r2, [pc, #332] ; (80029d0 ) + 8002884: 601a str r2, [r3, #0] + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + 8002886: 4b51 ldr r3, [pc, #324] ; (80029cc ) + 8002888: 2200 movs r2, #0 + 800288a: 605a str r2, [r3, #4] + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + 800288c: 4b4f ldr r3, [pc, #316] ; (80029cc ) + 800288e: 2200 movs r2, #0 + 8002890: 609a str r2, [r3, #8] + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + 8002892: 4b4e ldr r3, [pc, #312] ; (80029cc ) + 8002894: 2200 movs r2, #0 + 8002896: 60da str r2, [r3, #12] + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + 8002898: 4b4c ldr r3, [pc, #304] ; (80029cc ) + 800289a: 2200 movs r2, #0 + 800289c: 611a str r2, [r3, #16] + hltdc.Init.HorizontalSync = 40; + 800289e: 4b4b ldr r3, [pc, #300] ; (80029cc ) + 80028a0: 2228 movs r2, #40 ; 0x28 + 80028a2: 615a str r2, [r3, #20] + hltdc.Init.VerticalSync = 9; + 80028a4: 4b49 ldr r3, [pc, #292] ; (80029cc ) + 80028a6: 2209 movs r2, #9 + 80028a8: 619a str r2, [r3, #24] + hltdc.Init.AccumulatedHBP = 53; + 80028aa: 4b48 ldr r3, [pc, #288] ; (80029cc ) + 80028ac: 2235 movs r2, #53 ; 0x35 + 80028ae: 61da str r2, [r3, #28] + hltdc.Init.AccumulatedVBP = 11; + 80028b0: 4b46 ldr r3, [pc, #280] ; (80029cc ) + 80028b2: 220b movs r2, #11 + 80028b4: 621a str r2, [r3, #32] + hltdc.Init.AccumulatedActiveW = 533; + 80028b6: 4b45 ldr r3, [pc, #276] ; (80029cc ) + 80028b8: f240 2215 movw r2, #533 ; 0x215 + 80028bc: 625a str r2, [r3, #36] ; 0x24 + hltdc.Init.AccumulatedActiveH = 283; + 80028be: 4b43 ldr r3, [pc, #268] ; (80029cc ) + 80028c0: f240 121b movw r2, #283 ; 0x11b + 80028c4: 629a str r2, [r3, #40] ; 0x28 + hltdc.Init.TotalWidth = 565; + 80028c6: 4b41 ldr r3, [pc, #260] ; (80029cc ) + 80028c8: f240 2235 movw r2, #565 ; 0x235 + 80028cc: 62da str r2, [r3, #44] ; 0x2c + hltdc.Init.TotalHeigh = 285; + 80028ce: 4b3f ldr r3, [pc, #252] ; (80029cc ) + 80028d0: f240 121d movw r2, #285 ; 0x11d + 80028d4: 631a str r2, [r3, #48] ; 0x30 + hltdc.Init.Backcolor.Blue = 0; + 80028d6: 4b3d ldr r3, [pc, #244] ; (80029cc ) + 80028d8: 2200 movs r2, #0 + 80028da: f883 2034 strb.w r2, [r3, #52] ; 0x34 + hltdc.Init.Backcolor.Green = 255; + 80028de: 4b3b ldr r3, [pc, #236] ; (80029cc ) + 80028e0: 22ff movs r2, #255 ; 0xff + 80028e2: f883 2035 strb.w r2, [r3, #53] ; 0x35 + hltdc.Init.Backcolor.Red = 0; + 80028e6: 4b39 ldr r3, [pc, #228] ; (80029cc ) + 80028e8: 2200 movs r2, #0 + 80028ea: f883 2036 strb.w r2, [r3, #54] ; 0x36 + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + 80028ee: 4837 ldr r0, [pc, #220] ; (80029cc ) + 80028f0: f004 fd86 bl 8007400 + 80028f4: 4603 mov r3, r0 + 80028f6: 2b00 cmp r3, #0 + 80028f8: d001 beq.n 80028fe + { + Error_Handler(); + 80028fa: f000 f9ef bl 8002cdc + } + pLayerCfg.WindowX0 = 0; + 80028fe: 2300 movs r3, #0 + 8002900: 637b str r3, [r7, #52] ; 0x34 + pLayerCfg.WindowX1 = 480; + 8002902: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 8002906: 63bb str r3, [r7, #56] ; 0x38 + pLayerCfg.WindowY0 = 0; + 8002908: 2300 movs r3, #0 + 800290a: 63fb str r3, [r7, #60] ; 0x3c + pLayerCfg.WindowY1 = 272; + 800290c: f44f 7388 mov.w r3, #272 ; 0x110 + 8002910: 643b str r3, [r7, #64] ; 0x40 + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB1555; + 8002912: 2303 movs r3, #3 + 8002914: 647b str r3, [r7, #68] ; 0x44 + pLayerCfg.Alpha = 255; + 8002916: 23ff movs r3, #255 ; 0xff + 8002918: 64bb str r3, [r7, #72] ; 0x48 + pLayerCfg.Alpha0 = 0; + 800291a: 2300 movs r3, #0 + 800291c: 64fb str r3, [r7, #76] ; 0x4c + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + 800291e: f44f 63c0 mov.w r3, #1536 ; 0x600 + 8002922: 653b str r3, [r7, #80] ; 0x50 + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + 8002924: 2307 movs r3, #7 + 8002926: 657b str r3, [r7, #84] ; 0x54 + pLayerCfg.FBStartAdress = 0; + 8002928: 2300 movs r3, #0 + 800292a: 65bb str r3, [r7, #88] ; 0x58 + pLayerCfg.ImageWidth = 480; + 800292c: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 8002930: 65fb str r3, [r7, #92] ; 0x5c + pLayerCfg.ImageHeight = 272; + 8002932: f44f 7388 mov.w r3, #272 ; 0x110 + 8002936: 663b str r3, [r7, #96] ; 0x60 + pLayerCfg.Backcolor.Blue = 0; + 8002938: 2300 movs r3, #0 + 800293a: f887 3064 strb.w r3, [r7, #100] ; 0x64 + pLayerCfg.Backcolor.Green = 0; + 800293e: 2300 movs r3, #0 + 8002940: f887 3065 strb.w r3, [r7, #101] ; 0x65 + pLayerCfg.Backcolor.Red = 0; + 8002944: 2300 movs r3, #0 + 8002946: f887 3066 strb.w r3, [r7, #102] ; 0x66 + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + 800294a: f107 0334 add.w r3, r7, #52 ; 0x34 + 800294e: 2200 movs r2, #0 + 8002950: 4619 mov r1, r3 + 8002952: 481e ldr r0, [pc, #120] ; (80029cc ) + 8002954: f004 fe24 bl 80075a0 + 8002958: 4603 mov r3, r0 + 800295a: 2b00 cmp r3, #0 + 800295c: d001 beq.n 8002962 + { + Error_Handler(); + 800295e: f000 f9bd bl 8002cdc + } + pLayerCfg1.WindowX0 = 0; + 8002962: 2300 movs r3, #0 + 8002964: 603b str r3, [r7, #0] + pLayerCfg1.WindowX1 = 480; + 8002966: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 800296a: 607b str r3, [r7, #4] + pLayerCfg1.WindowY0 = 0; + 800296c: 2300 movs r3, #0 + 800296e: 60bb str r3, [r7, #8] + pLayerCfg1.WindowY1 = 272; + 8002970: f44f 7388 mov.w r3, #272 ; 0x110 + 8002974: 60fb str r3, [r7, #12] + pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB1555; + 8002976: 2303 movs r3, #3 + 8002978: 613b str r3, [r7, #16] + pLayerCfg1.Alpha = 255; + 800297a: 23ff movs r3, #255 ; 0xff + 800297c: 617b str r3, [r7, #20] + pLayerCfg1.Alpha0 = 0; + 800297e: 2300 movs r3, #0 + 8002980: 61bb str r3, [r7, #24] + pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + 8002982: f44f 63c0 mov.w r3, #1536 ; 0x600 + 8002986: 61fb str r3, [r7, #28] + pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + 8002988: 2307 movs r3, #7 + 800298a: 623b str r3, [r7, #32] + pLayerCfg1.FBStartAdress = 0; + 800298c: 2300 movs r3, #0 + 800298e: 627b str r3, [r7, #36] ; 0x24 + pLayerCfg1.ImageWidth = 480; + 8002990: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 8002994: 62bb str r3, [r7, #40] ; 0x28 + pLayerCfg1.ImageHeight = 272; + 8002996: f44f 7388 mov.w r3, #272 ; 0x110 + 800299a: 62fb str r3, [r7, #44] ; 0x2c + pLayerCfg1.Backcolor.Blue = 0; + 800299c: 2300 movs r3, #0 + 800299e: f887 3030 strb.w r3, [r7, #48] ; 0x30 + pLayerCfg1.Backcolor.Green = 0; + 80029a2: 2300 movs r3, #0 + 80029a4: f887 3031 strb.w r3, [r7, #49] ; 0x31 + pLayerCfg1.Backcolor.Red = 0; + 80029a8: 2300 movs r3, #0 + 80029aa: f887 3032 strb.w r3, [r7, #50] ; 0x32 + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK) + 80029ae: 463b mov r3, r7 + 80029b0: 2201 movs r2, #1 + 80029b2: 4619 mov r1, r3 + 80029b4: 4805 ldr r0, [pc, #20] ; (80029cc ) + 80029b6: f004 fdf3 bl 80075a0 + 80029ba: 4603 mov r3, r0 + 80029bc: 2b00 cmp r3, #0 + 80029be: d001 beq.n 80029c4 + { + Error_Handler(); + 80029c0: f000 f98c bl 8002cdc + } + /* USER CODE BEGIN LTDC_Init 2 */ + + /* USER CODE END LTDC_Init 2 */ + +} + 80029c4: bf00 nop + 80029c6: 3768 adds r7, #104 ; 0x68 + 80029c8: 46bd mov sp, r7 + 80029ca: bd80 pop {r7, pc} + 80029cc: 20000580 .word 0x20000580 + 80029d0: 40016800 .word 0x40016800 + +080029d4 : + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + 80029d4: b580 push {r7, lr} + 80029d6: af00 add r7, sp, #0 + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 80029d8: 4b0f ldr r3, [pc, #60] ; (8002a18 ) + 80029da: 4a10 ldr r2, [pc, #64] ; (8002a1c ) + 80029dc: 601a str r2, [r3, #0] + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + 80029de: 4b0e ldr r3, [pc, #56] ; (8002a18 ) + 80029e0: 2200 movs r2, #0 + 80029e2: 605a str r2, [r3, #4] + hrtc.Init.AsynchPrediv = 127; + 80029e4: 4b0c ldr r3, [pc, #48] ; (8002a18 ) + 80029e6: 227f movs r2, #127 ; 0x7f + 80029e8: 609a str r2, [r3, #8] + hrtc.Init.SynchPrediv = 255; + 80029ea: 4b0b ldr r3, [pc, #44] ; (8002a18 ) + 80029ec: 22ff movs r2, #255 ; 0xff + 80029ee: 60da str r2, [r3, #12] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 80029f0: 4b09 ldr r3, [pc, #36] ; (8002a18 ) + 80029f2: 2200 movs r2, #0 + 80029f4: 611a str r2, [r3, #16] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 80029f6: 4b08 ldr r3, [pc, #32] ; (8002a18 ) + 80029f8: 2200 movs r2, #0 + 80029fa: 615a str r2, [r3, #20] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 80029fc: 4b06 ldr r3, [pc, #24] ; (8002a18 ) + 80029fe: 2200 movs r2, #0 + 8002a00: 619a str r2, [r3, #24] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 8002a02: 4805 ldr r0, [pc, #20] ; (8002a18 ) + 8002a04: f006 f8be bl 8008b84 + 8002a08: 4603 mov r3, r0 + 8002a0a: 2b00 cmp r3, #0 + 8002a0c: d001 beq.n 8002a12 + { + Error_Handler(); + 8002a0e: f000 f965 bl 8002cdc + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 8002a12: bf00 nop + 8002a14: bd80 pop {r7, pc} + 8002a16: bf00 nop + 8002a18: 20000628 .word 0x20000628 + 8002a1c: 40002800 .word 0x40002800 + +08002a20 : + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + 8002a20: b580 push {r7, lr} + 8002a22: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 8002a24: 4b14 ldr r3, [pc, #80] ; (8002a78 ) + 8002a26: 4a15 ldr r2, [pc, #84] ; (8002a7c ) + 8002a28: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 8002a2a: 4b13 ldr r3, [pc, #76] ; (8002a78 ) + 8002a2c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8002a30: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 8002a32: 4b11 ldr r3, [pc, #68] ; (8002a78 ) + 8002a34: 2200 movs r2, #0 + 8002a36: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 8002a38: 4b0f ldr r3, [pc, #60] ; (8002a78 ) + 8002a3a: 2200 movs r2, #0 + 8002a3c: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 8002a3e: 4b0e ldr r3, [pc, #56] ; (8002a78 ) + 8002a40: 2200 movs r2, #0 + 8002a42: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8002a44: 4b0c ldr r3, [pc, #48] ; (8002a78 ) + 8002a46: 220c movs r2, #12 + 8002a48: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8002a4a: 4b0b ldr r3, [pc, #44] ; (8002a78 ) + 8002a4c: 2200 movs r2, #0 + 8002a4e: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 8002a50: 4b09 ldr r3, [pc, #36] ; (8002a78 ) + 8002a52: 2200 movs r2, #0 + 8002a54: 61da str r2, [r3, #28] + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8002a56: 4b08 ldr r3, [pc, #32] ; (8002a78 ) + 8002a58: 2200 movs r2, #0 + 8002a5a: 621a str r2, [r3, #32] + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8002a5c: 4b06 ldr r3, [pc, #24] ; (8002a78 ) + 8002a5e: 2200 movs r2, #0 + 8002a60: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart1) != HAL_OK) + 8002a62: 4805 ldr r0, [pc, #20] ; (8002a78 ) + 8002a64: f006 ff28 bl 80098b8 + 8002a68: 4603 mov r3, r0 + 8002a6a: 2b00 cmp r3, #0 + 8002a6c: d001 beq.n 8002a72 + { + Error_Handler(); + 8002a6e: f000 f935 bl 8002cdc + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 8002a72: bf00 nop + 8002a74: bd80 pop {r7, pc} + 8002a76: bf00 nop + 8002a78: 20000648 .word 0x20000648 + 8002a7c: 40011000 .word 0x40011000 + +08002a80 : + +/* FMC initialization function */ +static void MX_FMC_Init(void) +{ + 8002a80: b580 push {r7, lr} + 8002a82: b088 sub sp, #32 + 8002a84: af00 add r7, sp, #0 + + /* USER CODE BEGIN FMC_Init 0 */ + + /* USER CODE END FMC_Init 0 */ + + FMC_SDRAM_TimingTypeDef SdramTiming = {0}; + 8002a86: 1d3b adds r3, r7, #4 + 8002a88: 2200 movs r2, #0 + 8002a8a: 601a str r2, [r3, #0] + 8002a8c: 605a str r2, [r3, #4] + 8002a8e: 609a str r2, [r3, #8] + 8002a90: 60da str r2, [r3, #12] + 8002a92: 611a str r2, [r3, #16] + 8002a94: 615a str r2, [r3, #20] + 8002a96: 619a str r2, [r3, #24] + + /* USER CODE END FMC_Init 1 */ + + /** Perform the SDRAM1 memory initialization sequence + */ + hsdram1.Instance = FMC_SDRAM_DEVICE; + 8002a98: 4b1e ldr r3, [pc, #120] ; (8002b14 ) + 8002a9a: 4a1f ldr r2, [pc, #124] ; (8002b18 ) + 8002a9c: 601a str r2, [r3, #0] + /* hsdram1.Init */ + hsdram1.Init.SDBank = FMC_SDRAM_BANK1; + 8002a9e: 4b1d ldr r3, [pc, #116] ; (8002b14 ) + 8002aa0: 2200 movs r2, #0 + 8002aa2: 605a str r2, [r3, #4] + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + 8002aa4: 4b1b ldr r3, [pc, #108] ; (8002b14 ) + 8002aa6: 2200 movs r2, #0 + 8002aa8: 609a str r2, [r3, #8] + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + 8002aaa: 4b1a ldr r3, [pc, #104] ; (8002b14 ) + 8002aac: 2204 movs r2, #4 + 8002aae: 60da str r2, [r3, #12] + hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; + 8002ab0: 4b18 ldr r3, [pc, #96] ; (8002b14 ) + 8002ab2: 2210 movs r2, #16 + 8002ab4: 611a str r2, [r3, #16] + hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + 8002ab6: 4b17 ldr r3, [pc, #92] ; (8002b14 ) + 8002ab8: 2240 movs r2, #64 ; 0x40 + 8002aba: 615a str r2, [r3, #20] + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; + 8002abc: 4b15 ldr r3, [pc, #84] ; (8002b14 ) + 8002abe: 2280 movs r2, #128 ; 0x80 + 8002ac0: 619a str r2, [r3, #24] + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + 8002ac2: 4b14 ldr r3, [pc, #80] ; (8002b14 ) + 8002ac4: 2200 movs r2, #0 + 8002ac6: 61da str r2, [r3, #28] + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; + 8002ac8: 4b12 ldr r3, [pc, #72] ; (8002b14 ) + 8002aca: 2200 movs r2, #0 + 8002acc: 621a str r2, [r3, #32] + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; + 8002ace: 4b11 ldr r3, [pc, #68] ; (8002b14 ) + 8002ad0: 2200 movs r2, #0 + 8002ad2: 625a str r2, [r3, #36] ; 0x24 + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + 8002ad4: 4b0f ldr r3, [pc, #60] ; (8002b14 ) + 8002ad6: 2200 movs r2, #0 + 8002ad8: 629a str r2, [r3, #40] ; 0x28 + /* SdramTiming */ + SdramTiming.LoadToActiveDelay = 16; + 8002ada: 2310 movs r3, #16 + 8002adc: 607b str r3, [r7, #4] + SdramTiming.ExitSelfRefreshDelay = 16; + 8002ade: 2310 movs r3, #16 + 8002ae0: 60bb str r3, [r7, #8] + SdramTiming.SelfRefreshTime = 16; + 8002ae2: 2310 movs r3, #16 + 8002ae4: 60fb str r3, [r7, #12] + SdramTiming.RowCycleDelay = 16; + 8002ae6: 2310 movs r3, #16 + 8002ae8: 613b str r3, [r7, #16] + SdramTiming.WriteRecoveryTime = 16; + 8002aea: 2310 movs r3, #16 + 8002aec: 617b str r3, [r7, #20] + SdramTiming.RPDelay = 16; + 8002aee: 2310 movs r3, #16 + 8002af0: 61bb str r3, [r7, #24] + SdramTiming.RCDDelay = 16; + 8002af2: 2310 movs r3, #16 + 8002af4: 61fb str r3, [r7, #28] + + if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + 8002af6: 1d3b adds r3, r7, #4 + 8002af8: 4619 mov r1, r3 + 8002afa: 4806 ldr r0, [pc, #24] ; (8002b14 ) + 8002afc: f006 fb6c bl 80091d8 + 8002b00: 4603 mov r3, r0 + 8002b02: 2b00 cmp r3, #0 + 8002b04: d001 beq.n 8002b0a + { + Error_Handler( ); + 8002b06: f000 f8e9 bl 8002cdc + } + + /* USER CODE BEGIN FMC_Init 2 */ + + /* USER CODE END FMC_Init 2 */ +} + 8002b0a: bf00 nop + 8002b0c: 3720 adds r7, #32 + 8002b0e: 46bd mov sp, r7 + 8002b10: bd80 pop {r7, pc} + 8002b12: bf00 nop + 8002b14: 200006d0 .word 0x200006d0 + 8002b18: a0000140 .word 0xa0000140 + +08002b1c : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8002b1c: b580 push {r7, lr} + 8002b1e: b090 sub sp, #64 ; 0x40 + 8002b20: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8002b22: f107 032c add.w r3, r7, #44 ; 0x2c + 8002b26: 2200 movs r2, #0 + 8002b28: 601a str r2, [r3, #0] + 8002b2a: 605a str r2, [r3, #4] + 8002b2c: 609a str r2, [r3, #8] + 8002b2e: 60da str r2, [r3, #12] + 8002b30: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8002b32: 4b5e ldr r3, [pc, #376] ; (8002cac ) + 8002b34: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b36: 4a5d ldr r2, [pc, #372] ; (8002cac ) + 8002b38: f043 0310 orr.w r3, r3, #16 + 8002b3c: 6313 str r3, [r2, #48] ; 0x30 + 8002b3e: 4b5b ldr r3, [pc, #364] ; (8002cac ) + 8002b40: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b42: f003 0310 and.w r3, r3, #16 + 8002b46: 62bb str r3, [r7, #40] ; 0x28 + 8002b48: 6abb ldr r3, [r7, #40] ; 0x28 + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8002b4a: 4b58 ldr r3, [pc, #352] ; (8002cac ) + 8002b4c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b4e: 4a57 ldr r2, [pc, #348] ; (8002cac ) + 8002b50: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002b54: 6313 str r3, [r2, #48] ; 0x30 + 8002b56: 4b55 ldr r3, [pc, #340] ; (8002cac ) + 8002b58: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b5a: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002b5e: 627b str r3, [r7, #36] ; 0x24 + 8002b60: 6a7b ldr r3, [r7, #36] ; 0x24 + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8002b62: 4b52 ldr r3, [pc, #328] ; (8002cac ) + 8002b64: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b66: 4a51 ldr r2, [pc, #324] ; (8002cac ) + 8002b68: f043 0302 orr.w r3, r3, #2 + 8002b6c: 6313 str r3, [r2, #48] ; 0x30 + 8002b6e: 4b4f ldr r3, [pc, #316] ; (8002cac ) + 8002b70: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b72: f003 0302 and.w r3, r3, #2 + 8002b76: 623b str r3, [r7, #32] + 8002b78: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8002b7a: 4b4c ldr r3, [pc, #304] ; (8002cac ) + 8002b7c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b7e: 4a4b ldr r2, [pc, #300] ; (8002cac ) + 8002b80: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002b84: 6313 str r3, [r2, #48] ; 0x30 + 8002b86: 4b49 ldr r3, [pc, #292] ; (8002cac ) + 8002b88: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b8a: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002b8e: 61fb str r3, [r7, #28] + 8002b90: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8002b92: 4b46 ldr r3, [pc, #280] ; (8002cac ) + 8002b94: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002b96: 4a45 ldr r2, [pc, #276] ; (8002cac ) + 8002b98: f043 0308 orr.w r3, r3, #8 + 8002b9c: 6313 str r3, [r2, #48] ; 0x30 + 8002b9e: 4b43 ldr r3, [pc, #268] ; (8002cac ) + 8002ba0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002ba2: f003 0308 and.w r3, r3, #8 + 8002ba6: 61bb str r3, [r7, #24] + 8002ba8: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 8002baa: 4b40 ldr r3, [pc, #256] ; (8002cac ) + 8002bac: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bae: 4a3f ldr r2, [pc, #252] ; (8002cac ) + 8002bb0: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002bb4: 6313 str r3, [r2, #48] ; 0x30 + 8002bb6: 4b3d ldr r3, [pc, #244] ; (8002cac ) + 8002bb8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bba: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002bbe: 617b str r3, [r7, #20] + 8002bc0: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8002bc2: 4b3a ldr r3, [pc, #232] ; (8002cac ) + 8002bc4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bc6: 4a39 ldr r2, [pc, #228] ; (8002cac ) + 8002bc8: f043 0320 orr.w r3, r3, #32 + 8002bcc: 6313 str r3, [r2, #48] ; 0x30 + 8002bce: 4b37 ldr r3, [pc, #220] ; (8002cac ) + 8002bd0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bd2: f003 0320 and.w r3, r3, #32 + 8002bd6: 613b str r3, [r7, #16] + 8002bd8: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8002bda: 4b34 ldr r3, [pc, #208] ; (8002cac ) + 8002bdc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bde: 4a33 ldr r2, [pc, #204] ; (8002cac ) + 8002be0: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002be4: 6313 str r3, [r2, #48] ; 0x30 + 8002be6: 4b31 ldr r3, [pc, #196] ; (8002cac ) + 8002be8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bea: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002bee: 60fb str r3, [r7, #12] + 8002bf0: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8002bf2: 4b2e ldr r3, [pc, #184] ; (8002cac ) + 8002bf4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002bf6: 4a2d ldr r2, [pc, #180] ; (8002cac ) + 8002bf8: f043 0304 orr.w r3, r3, #4 + 8002bfc: 6313 str r3, [r2, #48] ; 0x30 + 8002bfe: 4b2b ldr r3, [pc, #172] ; (8002cac ) + 8002c00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c02: f003 0304 and.w r3, r3, #4 + 8002c06: 60bb str r3, [r7, #8] + 8002c08: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8002c0a: 4b28 ldr r3, [pc, #160] ; (8002cac ) + 8002c0c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c0e: 4a27 ldr r2, [pc, #156] ; (8002cac ) + 8002c10: f043 0301 orr.w r3, r3, #1 + 8002c14: 6313 str r3, [r2, #48] ; 0x30 + 8002c16: 4b25 ldr r3, [pc, #148] ; (8002cac ) + 8002c18: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c1a: f003 0301 and.w r3, r3, #1 + 8002c1e: 607b str r3, [r7, #4] + 8002c20: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8002c22: 4b22 ldr r3, [pc, #136] ; (8002cac ) + 8002c24: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c26: 4a21 ldr r2, [pc, #132] ; (8002cac ) + 8002c28: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8002c2c: 6313 str r3, [r2, #48] ; 0x30 + 8002c2e: 4b1f ldr r3, [pc, #124] ; (8002cac ) + 8002c30: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c32: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002c36: 603b str r3, [r7, #0] + 8002c38: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_RESET); + 8002c3a: 2200 movs r2, #0 + 8002c3c: 2108 movs r1, #8 + 8002c3e: 481c ldr r0, [pc, #112] ; (8002cb0 ) + 8002c40: f003 ff6e bl 8006b20 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOI, LED_Pin|LCD_DISP_Pin, GPIO_PIN_RESET); + 8002c44: 2200 movs r2, #0 + 8002c46: f241 0102 movw r1, #4098 ; 0x1002 + 8002c4a: 481a ldr r0, [pc, #104] ; (8002cb4 ) + 8002c4c: f003 ff68 bl 8006b20 + + /*Configure GPIO pin : LCD_BL_CTRL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin; + 8002c50: 2308 movs r3, #8 + 8002c52: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8002c54: 2301 movs r3, #1 + 8002c56: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002c58: 2300 movs r3, #0 + 8002c5a: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002c5c: 2300 movs r3, #0 + 8002c5e: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct); + 8002c60: f107 032c add.w r3, r7, #44 ; 0x2c + 8002c64: 4619 mov r1, r3 + 8002c66: 4812 ldr r0, [pc, #72] ; (8002cb0 ) + 8002c68: f003 fdae bl 80067c8 + + /*Configure GPIO pins : LED_Pin LCD_DISP_Pin */ + GPIO_InitStruct.Pin = LED_Pin|LCD_DISP_Pin; + 8002c6c: f241 0302 movw r3, #4098 ; 0x1002 + 8002c70: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8002c72: 2301 movs r3, #1 + 8002c74: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002c76: 2300 movs r3, #0 + 8002c78: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002c7a: 2300 movs r3, #0 + 8002c7c: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8002c7e: f107 032c add.w r3, r7, #44 ; 0x2c + 8002c82: 4619 mov r1, r3 + 8002c84: 480b ldr r0, [pc, #44] ; (8002cb4 ) + 8002c86: f003 fd9f bl 80067c8 + + /*Configure GPIO pin : BUTTON_Pin */ + GPIO_InitStruct.Pin = BUTTON_Pin; + 8002c8a: f44f 6300 mov.w r3, #2048 ; 0x800 + 8002c8e: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8002c90: 2300 movs r3, #0 + 8002c92: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002c94: 2300 movs r3, #0 + 8002c96: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(BUTTON_GPIO_Port, &GPIO_InitStruct); + 8002c98: f107 032c add.w r3, r7, #44 ; 0x2c + 8002c9c: 4619 mov r1, r3 + 8002c9e: 4805 ldr r0, [pc, #20] ; (8002cb4 ) + 8002ca0: f003 fd92 bl 80067c8 + +} + 8002ca4: bf00 nop + 8002ca6: 3740 adds r7, #64 ; 0x40 + 8002ca8: 46bd mov sp, r7 + 8002caa: bd80 pop {r7, pc} + 8002cac: 40023800 .word 0x40023800 + 8002cb0: 40022800 .word 0x40022800 + 8002cb4: 40022000 .word 0x40022000 + +08002cb8 : + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8002cb8: b580 push {r7, lr} + 8002cba: b082 sub sp, #8 + 8002cbc: af00 add r7, sp, #0 + 8002cbe: 6078 str r0, [r7, #4] + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM1) { + 8002cc0: 687b ldr r3, [r7, #4] + 8002cc2: 681b ldr r3, [r3, #0] + 8002cc4: 4a04 ldr r2, [pc, #16] ; (8002cd8 ) + 8002cc6: 4293 cmp r3, r2 + 8002cc8: d101 bne.n 8002cce + HAL_IncTick(); + 8002cca: f001 fdbf bl 800484c + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + 8002cce: bf00 nop + 8002cd0: 3708 adds r7, #8 + 8002cd2: 46bd mov sp, r7 + 8002cd4: bd80 pop {r7, pc} + 8002cd6: bf00 nop + 8002cd8: 40010000 .word 0x40010000 + +08002cdc : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8002cdc: b480 push {r7} + 8002cde: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8002ce0: b672 cpsid i +} + 8002ce2: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8002ce4: e7fe b.n 8002ce4 + ... + +08002ce8 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8002ce8: b580 push {r7, lr} + 8002cea: b082 sub sp, #8 + 8002cec: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + 8002cee: 4b11 ldr r3, [pc, #68] ; (8002d34 ) + 8002cf0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002cf2: 4a10 ldr r2, [pc, #64] ; (8002d34 ) + 8002cf4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002cf8: 6413 str r3, [r2, #64] ; 0x40 + 8002cfa: 4b0e ldr r3, [pc, #56] ; (8002d34 ) + 8002cfc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002cfe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002d02: 607b str r3, [r7, #4] + 8002d04: 687b ldr r3, [r7, #4] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8002d06: 4b0b ldr r3, [pc, #44] ; (8002d34 ) + 8002d08: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002d0a: 4a0a ldr r2, [pc, #40] ; (8002d34 ) + 8002d0c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8002d10: 6453 str r3, [r2, #68] ; 0x44 + 8002d12: 4b08 ldr r3, [pc, #32] ; (8002d34 ) + 8002d14: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002d16: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8002d1a: 603b str r3, [r7, #0] + 8002d1c: 683b ldr r3, [r7, #0] + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + 8002d1e: 2200 movs r2, #0 + 8002d20: 210f movs r1, #15 + 8002d22: f06f 0001 mvn.w r0, #1 + 8002d26: f001 fe8d bl 8004a44 + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8002d2a: bf00 nop + 8002d2c: 3708 adds r7, #8 + 8002d2e: 46bd mov sp, r7 + 8002d30: bd80 pop {r7, pc} + 8002d32: bf00 nop + 8002d34: 40023800 .word 0x40023800 + +08002d38 : +* This function configures the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + 8002d38: b480 push {r7} + 8002d3a: b085 sub sp, #20 + 8002d3c: af00 add r7, sp, #0 + 8002d3e: 6078 str r0, [r7, #4] + if(hdma2d->Instance==DMA2D) + 8002d40: 687b ldr r3, [r7, #4] + 8002d42: 681b ldr r3, [r3, #0] + 8002d44: 4a0a ldr r2, [pc, #40] ; (8002d70 ) + 8002d46: 4293 cmp r3, r2 + 8002d48: d10b bne.n 8002d62 + { + /* USER CODE BEGIN DMA2D_MspInit 0 */ + + /* USER CODE END DMA2D_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DMA2D_CLK_ENABLE(); + 8002d4a: 4b0a ldr r3, [pc, #40] ; (8002d74 ) + 8002d4c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002d4e: 4a09 ldr r2, [pc, #36] ; (8002d74 ) + 8002d50: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8002d54: 6313 str r3, [r2, #48] ; 0x30 + 8002d56: 4b07 ldr r3, [pc, #28] ; (8002d74 ) + 8002d58: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002d5a: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8002d5e: 60fb str r3, [r7, #12] + 8002d60: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN DMA2D_MspInit 1 */ + + /* USER CODE END DMA2D_MspInit 1 */ + } + +} + 8002d62: bf00 nop + 8002d64: 3714 adds r7, #20 + 8002d66: 46bd mov sp, r7 + 8002d68: f85d 7b04 ldr.w r7, [sp], #4 + 8002d6c: 4770 bx lr + 8002d6e: bf00 nop + 8002d70: 4002b000 .word 0x4002b000 + 8002d74: 40023800 .word 0x40023800 + +08002d78 : +* This function configures the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + 8002d78: b580 push {r7, lr} + 8002d7a: b0ae sub sp, #184 ; 0xb8 + 8002d7c: af00 add r7, sp, #0 + 8002d7e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8002d80: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002d84: 2200 movs r2, #0 + 8002d86: 601a str r2, [r3, #0] + 8002d88: 605a str r2, [r3, #4] + 8002d8a: 609a str r2, [r3, #8] + 8002d8c: 60da str r2, [r3, #12] + 8002d8e: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8002d90: f107 0320 add.w r3, r7, #32 + 8002d94: 2284 movs r2, #132 ; 0x84 + 8002d96: 2100 movs r1, #0 + 8002d98: 4618 mov r0, r3 + 8002d9a: f019 f89e bl 801beda + if(hltdc->Instance==LTDC) + 8002d9e: 687b ldr r3, [r7, #4] + 8002da0: 681b ldr r3, [r3, #0] + 8002da2: 4a6a ldr r2, [pc, #424] ; (8002f4c ) + 8002da4: 4293 cmp r3, r2 + 8002da6: f040 80cd bne.w 8002f44 + + /* USER CODE END LTDC_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + 8002daa: 2308 movs r3, #8 + 8002dac: 623b str r3, [r7, #32] + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + 8002dae: 23c0 movs r3, #192 ; 0xc0 + 8002db0: 637b str r3, [r7, #52] ; 0x34 + PeriphClkInitStruct.PLLSAI.PLLSAIR = 5; + 8002db2: 2305 movs r3, #5 + 8002db4: 63fb str r3, [r7, #60] ; 0x3c + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + 8002db6: 2302 movs r3, #2 + 8002db8: 63bb str r3, [r7, #56] ; 0x38 + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; + 8002dba: 2300 movs r3, #0 + 8002dbc: 643b str r3, [r7, #64] ; 0x40 + PeriphClkInitStruct.PLLSAIDivQ = 1; + 8002dbe: 2301 movs r3, #1 + 8002dc0: 64bb str r3, [r7, #72] ; 0x48 + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_4; + 8002dc2: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8002dc6: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8002dc8: f107 0320 add.w r3, r7, #32 + 8002dcc: 4618 mov r0, r3 + 8002dce: f005 fae9 bl 80083a4 + 8002dd2: 4603 mov r3, r0 + 8002dd4: 2b00 cmp r3, #0 + 8002dd6: d001 beq.n 8002ddc + { + Error_Handler(); + 8002dd8: f7ff ff80 bl 8002cdc + } + + /* Peripheral clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + 8002ddc: 4b5c ldr r3, [pc, #368] ; (8002f50 ) + 8002dde: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002de0: 4a5b ldr r2, [pc, #364] ; (8002f50 ) + 8002de2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 8002de6: 6453 str r3, [r2, #68] ; 0x44 + 8002de8: 4b59 ldr r3, [pc, #356] ; (8002f50 ) + 8002dea: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002dec: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8002df0: 61fb str r3, [r7, #28] + 8002df2: 69fb ldr r3, [r7, #28] + + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8002df4: 4b56 ldr r3, [pc, #344] ; (8002f50 ) + 8002df6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002df8: 4a55 ldr r2, [pc, #340] ; (8002f50 ) + 8002dfa: f043 0310 orr.w r3, r3, #16 + 8002dfe: 6313 str r3, [r2, #48] ; 0x30 + 8002e00: 4b53 ldr r3, [pc, #332] ; (8002f50 ) + 8002e02: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e04: f003 0310 and.w r3, r3, #16 + 8002e08: 61bb str r3, [r7, #24] + 8002e0a: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8002e0c: 4b50 ldr r3, [pc, #320] ; (8002f50 ) + 8002e0e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e10: 4a4f ldr r2, [pc, #316] ; (8002f50 ) + 8002e12: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002e16: 6313 str r3, [r2, #48] ; 0x30 + 8002e18: 4b4d ldr r3, [pc, #308] ; (8002f50 ) + 8002e1a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e1c: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002e20: 617b str r3, [r7, #20] + 8002e22: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 8002e24: 4b4a ldr r3, [pc, #296] ; (8002f50 ) + 8002e26: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e28: 4a49 ldr r2, [pc, #292] ; (8002f50 ) + 8002e2a: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002e2e: 6313 str r3, [r2, #48] ; 0x30 + 8002e30: 4b47 ldr r3, [pc, #284] ; (8002f50 ) + 8002e32: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e34: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002e38: 613b str r3, [r7, #16] + 8002e3a: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8002e3c: 4b44 ldr r3, [pc, #272] ; (8002f50 ) + 8002e3e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e40: 4a43 ldr r2, [pc, #268] ; (8002f50 ) + 8002e42: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002e46: 6313 str r3, [r2, #48] ; 0x30 + 8002e48: 4b41 ldr r3, [pc, #260] ; (8002f50 ) + 8002e4a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e4c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002e50: 60fb str r3, [r7, #12] + 8002e52: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8002e54: 4b3e ldr r3, [pc, #248] ; (8002f50 ) + 8002e56: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e58: 4a3d ldr r2, [pc, #244] ; (8002f50 ) + 8002e5a: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002e5e: 6313 str r3, [r2, #48] ; 0x30 + 8002e60: 4b3b ldr r3, [pc, #236] ; (8002f50 ) + 8002e62: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e64: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002e68: 60bb str r3, [r7, #8] + 8002e6a: 68bb ldr r3, [r7, #8] + PJ3 ------> LTDC_R4 + PJ2 ------> LTDC_R3 + PJ0 ------> LTDC_R1 + PJ1 ------> LTDC_R2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8002e6c: 2310 movs r3, #16 + 8002e6e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002e72: 2302 movs r3, #2 + 8002e74: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002e78: 2300 movs r3, #0 + 8002e7a: f8c7 30ac str.w r3, [r7, #172] ; 0xac + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002e7e: 2300 movs r3, #0 + 8002e80: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8002e84: 230e movs r3, #14 + 8002e86: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8002e8a: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002e8e: 4619 mov r1, r3 + 8002e90: 4830 ldr r0, [pc, #192] ; (8002f54 ) + 8002e92: f003 fc99 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_11 + 8002e96: f64e 73ff movw r3, #61439 ; 0xefff + 8002e9a: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + |GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_7|GPIO_PIN_9 + |GPIO_PIN_6|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_3 + |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002e9e: 2302 movs r3, #2 + 8002ea0: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002ea4: 2300 movs r3, #0 + 8002ea6: f8c7 30ac str.w r3, [r7, #172] ; 0xac + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002eaa: 2300 movs r3, #0 + 8002eac: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8002eb0: 230e movs r3, #14 + 8002eb2: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); + 8002eb6: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002eba: 4619 mov r1, r3 + 8002ebc: 4826 ldr r0, [pc, #152] ; (8002f58 ) + 8002ebe: f003 fc83 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 + 8002ec2: 23f7 movs r3, #247 ; 0xf7 + 8002ec4: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002ec8: 2302 movs r3, #2 + 8002eca: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002ece: 2300 movs r3, #0 + 8002ed0: f8c7 30ac str.w r3, [r7, #172] ; 0xac + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002ed4: 2300 movs r3, #0 + 8002ed6: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8002eda: 230e movs r3, #14 + 8002edc: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); + 8002ee0: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002ee4: 4619 mov r1, r3 + 8002ee6: 481d ldr r0, [pc, #116] ; (8002f5c ) + 8002ee8: f003 fc6e bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_12; + 8002eec: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8002ef0: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002ef4: 2302 movs r3, #2 + 8002ef6: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002efa: 2300 movs r3, #0 + 8002efc: f8c7 30ac str.w r3, [r7, #172] ; 0xac + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002f00: 2300 movs r3, #0 + 8002f02: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + 8002f06: 2309 movs r3, #9 + 8002f08: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 8002f0c: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002f10: 4619 mov r1, r3 + 8002f12: 4813 ldr r0, [pc, #76] ; (8002f60 ) + 8002f14: f003 fc58 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15|GPIO_PIN_14; + 8002f18: f44f 4346 mov.w r3, #50688 ; 0xc600 + 8002f1c: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002f20: 2302 movs r3, #2 + 8002f22: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002f26: 2300 movs r3, #0 + 8002f28: f8c7 30ac str.w r3, [r7, #172] ; 0xac + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8002f2c: 2300 movs r3, #0 + 8002f2e: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8002f32: 230e movs r3, #14 + 8002f34: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8002f38: f107 03a4 add.w r3, r7, #164 ; 0xa4 + 8002f3c: 4619 mov r1, r3 + 8002f3e: 4809 ldr r0, [pc, #36] ; (8002f64 ) + 8002f40: f003 fc42 bl 80067c8 + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } + +} + 8002f44: bf00 nop + 8002f46: 37b8 adds r7, #184 ; 0xb8 + 8002f48: 46bd mov sp, r7 + 8002f4a: bd80 pop {r7, pc} + 8002f4c: 40016800 .word 0x40016800 + 8002f50: 40023800 .word 0x40023800 + 8002f54: 40021000 .word 0x40021000 + 8002f58: 40022400 .word 0x40022400 + 8002f5c: 40022800 .word 0x40022800 + 8002f60: 40021800 .word 0x40021800 + 8002f64: 40022000 .word 0x40022000 + +08002f68 : +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + 8002f68: b580 push {r7, lr} + 8002f6a: b0a4 sub sp, #144 ; 0x90 + 8002f6c: af00 add r7, sp, #0 + 8002f6e: 6078 str r0, [r7, #4] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8002f70: f107 030c add.w r3, r7, #12 + 8002f74: 2284 movs r2, #132 ; 0x84 + 8002f76: 2100 movs r1, #0 + 8002f78: 4618 mov r0, r3 + 8002f7a: f018 ffae bl 801beda + if(hrtc->Instance==RTC) + 8002f7e: 687b ldr r3, [r7, #4] + 8002f80: 681b ldr r3, [r3, #0] + 8002f82: 4a0e ldr r2, [pc, #56] ; (8002fbc ) + 8002f84: 4293 cmp r3, r2 + 8002f86: d114 bne.n 8002fb2 + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 8002f88: 2320 movs r3, #32 + 8002f8a: 60fb str r3, [r7, #12] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 8002f8c: f44f 7380 mov.w r3, #256 ; 0x100 + 8002f90: 63fb str r3, [r7, #60] ; 0x3c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8002f92: f107 030c add.w r3, r7, #12 + 8002f96: 4618 mov r0, r3 + 8002f98: f005 fa04 bl 80083a4 + 8002f9c: 4603 mov r3, r0 + 8002f9e: 2b00 cmp r3, #0 + 8002fa0: d001 beq.n 8002fa6 + { + Error_Handler(); + 8002fa2: f7ff fe9b bl 8002cdc + } + + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8002fa6: 4b06 ldr r3, [pc, #24] ; (8002fc0 ) + 8002fa8: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002faa: 4a05 ldr r2, [pc, #20] ; (8002fc0 ) + 8002fac: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8002fb0: 6713 str r3, [r2, #112] ; 0x70 + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + 8002fb2: bf00 nop + 8002fb4: 3790 adds r7, #144 ; 0x90 + 8002fb6: 46bd mov sp, r7 + 8002fb8: bd80 pop {r7, pc} + 8002fba: bf00 nop + 8002fbc: 40002800 .word 0x40002800 + 8002fc0: 40023800 .word 0x40023800 + +08002fc4 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 8002fc4: b580 push {r7, lr} + 8002fc6: b0ac sub sp, #176 ; 0xb0 + 8002fc8: af00 add r7, sp, #0 + 8002fca: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8002fcc: f107 039c add.w r3, r7, #156 ; 0x9c + 8002fd0: 2200 movs r2, #0 + 8002fd2: 601a str r2, [r3, #0] + 8002fd4: 605a str r2, [r3, #4] + 8002fd6: 609a str r2, [r3, #8] + 8002fd8: 60da str r2, [r3, #12] + 8002fda: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8002fdc: f107 0318 add.w r3, r7, #24 + 8002fe0: 2284 movs r2, #132 ; 0x84 + 8002fe2: 2100 movs r1, #0 + 8002fe4: 4618 mov r0, r3 + 8002fe6: f018 ff78 bl 801beda + if(huart->Instance==USART1) + 8002fea: 687b ldr r3, [r7, #4] + 8002fec: 681b ldr r3, [r3, #0] + 8002fee: 4a32 ldr r2, [pc, #200] ; (80030b8 ) + 8002ff0: 4293 cmp r3, r2 + 8002ff2: d15c bne.n 80030ae + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + 8002ff4: 2340 movs r3, #64 ; 0x40 + 8002ff6: 61bb str r3, [r7, #24] + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 8002ff8: 2300 movs r3, #0 + 8002ffa: 65fb str r3, [r7, #92] ; 0x5c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8002ffc: f107 0318 add.w r3, r7, #24 + 8003000: 4618 mov r0, r3 + 8003002: f005 f9cf bl 80083a4 + 8003006: 4603 mov r3, r0 + 8003008: 2b00 cmp r3, #0 + 800300a: d001 beq.n 8003010 + { + Error_Handler(); + 800300c: f7ff fe66 bl 8002cdc + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + 8003010: 4b2a ldr r3, [pc, #168] ; (80030bc ) + 8003012: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003014: 4a29 ldr r2, [pc, #164] ; (80030bc ) + 8003016: f043 0310 orr.w r3, r3, #16 + 800301a: 6453 str r3, [r2, #68] ; 0x44 + 800301c: 4b27 ldr r3, [pc, #156] ; (80030bc ) + 800301e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003020: f003 0310 and.w r3, r3, #16 + 8003024: 617b str r3, [r7, #20] + 8003026: 697b ldr r3, [r7, #20] + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8003028: 4b24 ldr r3, [pc, #144] ; (80030bc ) + 800302a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800302c: 4a23 ldr r2, [pc, #140] ; (80030bc ) + 800302e: f043 0302 orr.w r3, r3, #2 + 8003032: 6313 str r3, [r2, #48] ; 0x30 + 8003034: 4b21 ldr r3, [pc, #132] ; (80030bc ) + 8003036: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003038: f003 0302 and.w r3, r3, #2 + 800303c: 613b str r3, [r7, #16] + 800303e: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8003040: 4b1e ldr r3, [pc, #120] ; (80030bc ) + 8003042: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003044: 4a1d ldr r2, [pc, #116] ; (80030bc ) + 8003046: f043 0301 orr.w r3, r3, #1 + 800304a: 6313 str r3, [r2, #48] ; 0x30 + 800304c: 4b1b ldr r3, [pc, #108] ; (80030bc ) + 800304e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003050: f003 0301 and.w r3, r3, #1 + 8003054: 60fb str r3, [r7, #12] + 8003056: 68fb ldr r3, [r7, #12] + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + 8003058: 2380 movs r3, #128 ; 0x80 + 800305a: f8c7 309c str.w r3, [r7, #156] ; 0x9c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800305e: 2302 movs r3, #2 + 8003060: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003064: 2300 movs r3, #0 + 8003066: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800306a: 2303 movs r3, #3 + 800306c: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 8003070: 2307 movs r3, #7 + 8003072: f8c7 30ac str.w r3, [r7, #172] ; 0xac + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8003076: f107 039c add.w r3, r7, #156 ; 0x9c + 800307a: 4619 mov r1, r3 + 800307c: 4810 ldr r0, [pc, #64] ; (80030c0 ) + 800307e: f003 fba3 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_9; + 8003082: f44f 7300 mov.w r3, #512 ; 0x200 + 8003086: f8c7 309c str.w r3, [r7, #156] ; 0x9c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800308a: 2302 movs r3, #2 + 800308c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003090: 2300 movs r3, #0 + 8003092: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003096: 2303 movs r3, #3 + 8003098: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 800309c: 2307 movs r3, #7 + 800309e: f8c7 30ac str.w r3, [r7, #172] ; 0xac + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80030a2: f107 039c add.w r3, r7, #156 ; 0x9c + 80030a6: 4619 mov r1, r3 + 80030a8: 4806 ldr r0, [pc, #24] ; (80030c4 ) + 80030aa: f003 fb8d bl 80067c8 + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + 80030ae: bf00 nop + 80030b0: 37b0 adds r7, #176 ; 0xb0 + 80030b2: 46bd mov sp, r7 + 80030b4: bd80 pop {r7, pc} + 80030b6: bf00 nop + 80030b8: 40011000 .word 0x40011000 + 80030bc: 40023800 .word 0x40023800 + 80030c0: 40020400 .word 0x40020400 + 80030c4: 40020000 .word 0x40020000 + +080030c8 : + +} + +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + 80030c8: b580 push {r7, lr} + 80030ca: b086 sub sp, #24 + 80030cc: af00 add r7, sp, #0 + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + 80030ce: 1d3b adds r3, r7, #4 + 80030d0: 2200 movs r2, #0 + 80030d2: 601a str r2, [r3, #0] + 80030d4: 605a str r2, [r3, #4] + 80030d6: 609a str r2, [r3, #8] + 80030d8: 60da str r2, [r3, #12] + 80030da: 611a str r2, [r3, #16] + if (FMC_Initialized) { + 80030dc: 4b33 ldr r3, [pc, #204] ; (80031ac ) + 80030de: 681b ldr r3, [r3, #0] + 80030e0: 2b00 cmp r3, #0 + 80030e2: d15e bne.n 80031a2 + return; + } + FMC_Initialized = 1; + 80030e4: 4b31 ldr r3, [pc, #196] ; (80031ac ) + 80030e6: 2201 movs r2, #1 + 80030e8: 601a str r2, [r3, #0] + + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + 80030ea: 4b31 ldr r3, [pc, #196] ; (80031b0 ) + 80030ec: 6b9b ldr r3, [r3, #56] ; 0x38 + 80030ee: 4a30 ldr r2, [pc, #192] ; (80031b0 ) + 80030f0: f043 0301 orr.w r3, r3, #1 + 80030f4: 6393 str r3, [r2, #56] ; 0x38 + 80030f6: 4b2e ldr r3, [pc, #184] ; (80031b0 ) + 80030f8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80030fa: f003 0301 and.w r3, r3, #1 + 80030fe: 603b str r3, [r7, #0] + 8003100: 683b ldr r3, [r7, #0] + PE10 ------> FMC_D7 + PE12 ------> FMC_D9 + PE15 ------> FMC_D12 + PE13 ------> FMC_D10 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + 8003102: f64f 7383 movw r3, #65411 ; 0xff83 + 8003106: 607b str r3, [r7, #4] + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003108: 2302 movs r3, #2 + 800310a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800310c: 2300 movs r3, #0 + 800310e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003110: 2303 movs r3, #3 + 8003112: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8003114: 230c movs r3, #12 + 8003116: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8003118: 1d3b adds r3, r7, #4 + 800311a: 4619 mov r1, r3 + 800311c: 4825 ldr r0, [pc, #148] ; (80031b4 ) + 800311e: f003 fb53 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + 8003122: f248 1333 movw r3, #33075 ; 0x8133 + 8003126: 607b str r3, [r7, #4] + |GPIO_PIN_5|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003128: 2302 movs r3, #2 + 800312a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800312c: 2300 movs r3, #0 + 800312e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003130: 2303 movs r3, #3 + 8003132: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8003134: 230c movs r3, #12 + 8003136: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 8003138: 1d3b adds r3, r7, #4 + 800313a: 4619 mov r1, r3 + 800313c: 481e ldr r0, [pc, #120] ; (80031b8 ) + 800313e: f003 fb43 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + 8003142: f24c 7303 movw r3, #50947 ; 0xc703 + 8003146: 607b str r3, [r7, #4] + |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003148: 2302 movs r3, #2 + 800314a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800314c: 2300 movs r3, #0 + 800314e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003150: 2303 movs r3, #3 + 8003152: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8003154: 230c movs r3, #12 + 8003156: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8003158: 1d3b adds r3, r7, #4 + 800315a: 4619 mov r1, r3 + 800315c: 4817 ldr r0, [pc, #92] ; (80031bc ) + 800315e: f003 fb33 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + 8003162: f64f 033f movw r3, #63551 ; 0xf83f + 8003166: 607b str r3, [r7, #4] + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003168: 2302 movs r3, #2 + 800316a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800316c: 2300 movs r3, #0 + 800316e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003170: 2303 movs r3, #3 + 8003172: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8003174: 230c movs r3, #12 + 8003176: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 8003178: 1d3b adds r3, r7, #4 + 800317a: 4619 mov r1, r3 + 800317c: 4810 ldr r0, [pc, #64] ; (80031c0 ) + 800317e: f003 fb23 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3|GPIO_PIN_2; + 8003182: 232c movs r3, #44 ; 0x2c + 8003184: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003186: 2302 movs r3, #2 + 8003188: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800318a: 2300 movs r3, #0 + 800318c: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800318e: 2303 movs r3, #3 + 8003190: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8003192: 230c movs r3, #12 + 8003194: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8003196: 1d3b adds r3, r7, #4 + 8003198: 4619 mov r1, r3 + 800319a: 480a ldr r0, [pc, #40] ; (80031c4 ) + 800319c: f003 fb14 bl 80067c8 + 80031a0: e000 b.n 80031a4 + return; + 80031a2: bf00 nop + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + 80031a4: 3718 adds r7, #24 + 80031a6: 46bd mov sp, r7 + 80031a8: bd80 pop {r7, pc} + 80031aa: bf00 nop + 80031ac: 20000708 .word 0x20000708 + 80031b0: 40023800 .word 0x40023800 + 80031b4: 40021000 .word 0x40021000 + 80031b8: 40021800 .word 0x40021800 + 80031bc: 40020c00 .word 0x40020c00 + 80031c0: 40021400 .word 0x40021400 + 80031c4: 40021c00 .word 0x40021c00 + +080031c8 : + +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ + 80031c8: b580 push {r7, lr} + 80031ca: b082 sub sp, #8 + 80031cc: af00 add r7, sp, #0 + 80031ce: 6078 str r0, [r7, #4] + /* USER CODE BEGIN SDRAM_MspInit 0 */ + + /* USER CODE END SDRAM_MspInit 0 */ + HAL_FMC_MspInit(); + 80031d0: f7ff ff7a bl 80030c8 + /* USER CODE BEGIN SDRAM_MspInit 1 */ + + /* USER CODE END SDRAM_MspInit 1 */ +} + 80031d4: bf00 nop + 80031d6: 3708 adds r7, #8 + 80031d8: 46bd mov sp, r7 + 80031da: bd80 pop {r7, pc} + +080031dc : + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80031dc: b580 push {r7, lr} + 80031de: b08c sub sp, #48 ; 0x30 + 80031e0: af00 add r7, sp, #0 + 80031e2: 6078 str r0, [r7, #4] + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock = 0U; + 80031e4: 2300 movs r3, #0 + 80031e6: 62bb str r3, [r7, #40] ; 0x28 + + uint32_t uwPrescalerValue = 0U; + 80031e8: 2300 movs r3, #0 + 80031ea: 627b str r3, [r7, #36] ; 0x24 + uint32_t pFLatency; + HAL_StatusTypeDef status; + + /* Enable TIM1 clock */ + __HAL_RCC_TIM1_CLK_ENABLE(); + 80031ec: 4b2f ldr r3, [pc, #188] ; (80032ac ) + 80031ee: 6c5b ldr r3, [r3, #68] ; 0x44 + 80031f0: 4a2e ldr r2, [pc, #184] ; (80032ac ) + 80031f2: f043 0301 orr.w r3, r3, #1 + 80031f6: 6453 str r3, [r2, #68] ; 0x44 + 80031f8: 4b2c ldr r3, [pc, #176] ; (80032ac ) + 80031fa: 6c5b ldr r3, [r3, #68] ; 0x44 + 80031fc: f003 0301 and.w r3, r3, #1 + 8003200: 60bb str r3, [r7, #8] + 8003202: 68bb ldr r3, [r7, #8] + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + 8003204: f107 020c add.w r2, r7, #12 + 8003208: f107 0310 add.w r3, r7, #16 + 800320c: 4611 mov r1, r2 + 800320e: 4618 mov r0, r3 + 8003210: f005 f896 bl 8008340 + + /* Compute TIM1 clock */ + uwTimclock = 2*HAL_RCC_GetPCLK2Freq(); + 8003214: f005 f880 bl 8008318 + 8003218: 4603 mov r3, r0 + 800321a: 005b lsls r3, r3, #1 + 800321c: 62bb str r3, [r7, #40] ; 0x28 + + /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + 800321e: 6abb ldr r3, [r7, #40] ; 0x28 + 8003220: 4a23 ldr r2, [pc, #140] ; (80032b0 ) + 8003222: fba2 2303 umull r2, r3, r2, r3 + 8003226: 0c9b lsrs r3, r3, #18 + 8003228: 3b01 subs r3, #1 + 800322a: 627b str r3, [r7, #36] ; 0x24 + + /* Initialize TIM1 */ + htim1.Instance = TIM1; + 800322c: 4b21 ldr r3, [pc, #132] ; (80032b4 ) + 800322e: 4a22 ldr r2, [pc, #136] ; (80032b8 ) + 8003230: 601a str r2, [r3, #0] + + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim1.Init.Period = (1000000U / 1000U) - 1U; + 8003232: 4b20 ldr r3, [pc, #128] ; (80032b4 ) + 8003234: f240 32e7 movw r2, #999 ; 0x3e7 + 8003238: 60da str r2, [r3, #12] + htim1.Init.Prescaler = uwPrescalerValue; + 800323a: 4a1e ldr r2, [pc, #120] ; (80032b4 ) + 800323c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800323e: 6053 str r3, [r2, #4] + htim1.Init.ClockDivision = 0; + 8003240: 4b1c ldr r3, [pc, #112] ; (80032b4 ) + 8003242: 2200 movs r2, #0 + 8003244: 611a str r2, [r3, #16] + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + 8003246: 4b1b ldr r3, [pc, #108] ; (80032b4 ) + 8003248: 2200 movs r2, #0 + 800324a: 609a str r2, [r3, #8] + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800324c: 4b19 ldr r3, [pc, #100] ; (80032b4 ) + 800324e: 2200 movs r2, #0 + 8003250: 619a str r2, [r3, #24] + + status = HAL_TIM_Base_Init(&htim1); + 8003252: 4818 ldr r0, [pc, #96] ; (80032b4 ) + 8003254: f006 f851 bl 80092fa + 8003258: 4603 mov r3, r0 + 800325a: f887 302f strb.w r3, [r7, #47] ; 0x2f + if (status == HAL_OK) + 800325e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8003262: 2b00 cmp r3, #0 + 8003264: d11b bne.n 800329e + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim1); + 8003266: 4813 ldr r0, [pc, #76] ; (80032b4 ) + 8003268: f006 f8a8 bl 80093bc + 800326c: 4603 mov r3, r0 + 800326e: f887 302f strb.w r3, [r7, #47] ; 0x2f + if (status == HAL_OK) + 8003272: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8003276: 2b00 cmp r3, #0 + 8003278: d111 bne.n 800329e + { + /* Enable the TIM1 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); + 800327a: 2019 movs r0, #25 + 800327c: f001 fbfe bl 8004a7c + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8003280: 687b ldr r3, [r7, #4] + 8003282: 2b0f cmp r3, #15 + 8003284: d808 bhi.n 8003298 + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, TickPriority, 0U); + 8003286: 2200 movs r2, #0 + 8003288: 6879 ldr r1, [r7, #4] + 800328a: 2019 movs r0, #25 + 800328c: f001 fbda bl 8004a44 + uwTickPrio = TickPriority; + 8003290: 4a0a ldr r2, [pc, #40] ; (80032bc ) + 8003292: 687b ldr r3, [r7, #4] + 8003294: 6013 str r3, [r2, #0] + 8003296: e002 b.n 800329e + } + else + { + status = HAL_ERROR; + 8003298: 2301 movs r3, #1 + 800329a: f887 302f strb.w r3, [r7, #47] ; 0x2f + } + } + } + + /* Return function status */ + return status; + 800329e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f +} + 80032a2: 4618 mov r0, r3 + 80032a4: 3730 adds r7, #48 ; 0x30 + 80032a6: 46bd mov sp, r7 + 80032a8: bd80 pop {r7, pc} + 80032aa: bf00 nop + 80032ac: 40023800 .word 0x40023800 + 80032b0: 431bde83 .word 0x431bde83 + 80032b4: 2000070c .word 0x2000070c + 80032b8: 40010000 .word 0x40010000 + 80032bc: 20000094 .word 0x20000094 + +080032c0 : + +/** + * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. + */ +void TIM1_UP_TIM10_IRQHandler(void) +{ + 80032c0: b580 push {r7, lr} + 80032c2: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */ + + /* USER CODE END TIM1_UP_TIM10_IRQn 0 */ + HAL_TIM_IRQHandler(&htim1); + 80032c4: 4802 ldr r0, [pc, #8] ; (80032d0 ) + 80032c6: f006 f8f1 bl 80094ac + /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */ + + /* USER CODE END TIM1_UP_TIM10_IRQn 1 */ +} + 80032ca: bf00 nop + 80032cc: bd80 pop {r7, pc} + 80032ce: bf00 nop + 80032d0: 2000070c .word 0x2000070c + +080032d4 : + +/** + * @brief This function handles Ethernet global interrupt. + */ +void ETH_IRQHandler(void) +{ + 80032d4: b580 push {r7, lr} + 80032d6: af00 add r7, sp, #0 + /* USER CODE BEGIN ETH_IRQn 0 */ + + /* USER CODE END ETH_IRQn 0 */ + HAL_ETH_IRQHandler(&heth); + 80032d8: 4802 ldr r0, [pc, #8] ; (80032e4 ) + 80032da: f002 fba1 bl 8005a20 + /* USER CODE BEGIN ETH_IRQn 1 */ + + /* USER CODE END ETH_IRQn 1 */ +} + 80032de: bf00 nop + 80032e0: bd80 pop {r7, pc} + 80032e2: bf00 nop + 80032e4: 20005380 .word 0x20005380 + +080032e8 <_getpid>: +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + 80032e8: b480 push {r7} + 80032ea: af00 add r7, sp, #0 + return 1; + 80032ec: 2301 movs r3, #1 +} + 80032ee: 4618 mov r0, r3 + 80032f0: 46bd mov sp, r7 + 80032f2: f85d 7b04 ldr.w r7, [sp], #4 + 80032f6: 4770 bx lr + +080032f8 <_kill>: + +int _kill(int pid, int sig) +{ + 80032f8: b480 push {r7} + 80032fa: b083 sub sp, #12 + 80032fc: af00 add r7, sp, #0 + 80032fe: 6078 str r0, [r7, #4] + 8003300: 6039 str r1, [r7, #0] + errno = EINVAL; + 8003302: 4b05 ldr r3, [pc, #20] ; (8003318 <_kill+0x20>) + 8003304: 2216 movs r2, #22 + 8003306: 601a str r2, [r3, #0] + return -1; + 8003308: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 800330c: 4618 mov r0, r3 + 800330e: 370c adds r7, #12 + 8003310: 46bd mov sp, r7 + 8003312: f85d 7b04 ldr.w r7, [sp], #4 + 8003316: 4770 bx lr + 8003318: 2000d0ec .word 0x2000d0ec + +0800331c <_exit>: + +void _exit (int status) +{ + 800331c: b580 push {r7, lr} + 800331e: b082 sub sp, #8 + 8003320: af00 add r7, sp, #0 + 8003322: 6078 str r0, [r7, #4] + _kill(status, -1); + 8003324: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8003328: 6878 ldr r0, [r7, #4] + 800332a: f7ff ffe5 bl 80032f8 <_kill> + while (1) {} /* Make sure we hang here */ + 800332e: e7fe b.n 800332e <_exit+0x12> + +08003330 <_close>: + } + return len; +} + +int _close(int file) +{ + 8003330: b480 push {r7} + 8003332: b083 sub sp, #12 + 8003334: af00 add r7, sp, #0 + 8003336: 6078 str r0, [r7, #4] + return -1; + 8003338: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 800333c: 4618 mov r0, r3 + 800333e: 370c adds r7, #12 + 8003340: 46bd mov sp, r7 + 8003342: f85d 7b04 ldr.w r7, [sp], #4 + 8003346: 4770 bx lr + +08003348 <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 8003348: b480 push {r7} + 800334a: b083 sub sp, #12 + 800334c: af00 add r7, sp, #0 + 800334e: 6078 str r0, [r7, #4] + 8003350: 6039 str r1, [r7, #0] + st->st_mode = S_IFCHR; + 8003352: 683b ldr r3, [r7, #0] + 8003354: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8003358: 605a str r2, [r3, #4] + return 0; + 800335a: 2300 movs r3, #0 +} + 800335c: 4618 mov r0, r3 + 800335e: 370c adds r7, #12 + 8003360: 46bd mov sp, r7 + 8003362: f85d 7b04 ldr.w r7, [sp], #4 + 8003366: 4770 bx lr + +08003368 <_isatty>: + +int _isatty(int file) +{ + 8003368: b480 push {r7} + 800336a: b083 sub sp, #12 + 800336c: af00 add r7, sp, #0 + 800336e: 6078 str r0, [r7, #4] + return 1; + 8003370: 2301 movs r3, #1 +} + 8003372: 4618 mov r0, r3 + 8003374: 370c adds r7, #12 + 8003376: 46bd mov sp, r7 + 8003378: f85d 7b04 ldr.w r7, [sp], #4 + 800337c: 4770 bx lr + +0800337e <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 800337e: b480 push {r7} + 8003380: b085 sub sp, #20 + 8003382: af00 add r7, sp, #0 + 8003384: 60f8 str r0, [r7, #12] + 8003386: 60b9 str r1, [r7, #8] + 8003388: 607a str r2, [r7, #4] + return 0; + 800338a: 2300 movs r3, #0 +} + 800338c: 4618 mov r0, r3 + 800338e: 3714 adds r7, #20 + 8003390: 46bd mov sp, r7 + 8003392: f85d 7b04 ldr.w r7, [sp], #4 + 8003396: 4770 bx lr + +08003398 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8003398: b480 push {r7} + 800339a: b087 sub sp, #28 + 800339c: af00 add r7, sp, #0 + 800339e: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 80033a0: 4a14 ldr r2, [pc, #80] ; (80033f4 <_sbrk+0x5c>) + 80033a2: 4b15 ldr r3, [pc, #84] ; (80033f8 <_sbrk+0x60>) + 80033a4: 1ad3 subs r3, r2, r3 + 80033a6: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 80033a8: 697b ldr r3, [r7, #20] + 80033aa: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 80033ac: 4b13 ldr r3, [pc, #76] ; (80033fc <_sbrk+0x64>) + 80033ae: 681b ldr r3, [r3, #0] + 80033b0: 2b00 cmp r3, #0 + 80033b2: d102 bne.n 80033ba <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 80033b4: 4b11 ldr r3, [pc, #68] ; (80033fc <_sbrk+0x64>) + 80033b6: 4a12 ldr r2, [pc, #72] ; (8003400 <_sbrk+0x68>) + 80033b8: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 80033ba: 4b10 ldr r3, [pc, #64] ; (80033fc <_sbrk+0x64>) + 80033bc: 681a ldr r2, [r3, #0] + 80033be: 687b ldr r3, [r7, #4] + 80033c0: 4413 add r3, r2 + 80033c2: 693a ldr r2, [r7, #16] + 80033c4: 429a cmp r2, r3 + 80033c6: d205 bcs.n 80033d4 <_sbrk+0x3c> + { + errno = ENOMEM; + 80033c8: 4b0e ldr r3, [pc, #56] ; (8003404 <_sbrk+0x6c>) + 80033ca: 220c movs r2, #12 + 80033cc: 601a str r2, [r3, #0] + return (void *)-1; + 80033ce: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80033d2: e009 b.n 80033e8 <_sbrk+0x50> + } + + prev_heap_end = __sbrk_heap_end; + 80033d4: 4b09 ldr r3, [pc, #36] ; (80033fc <_sbrk+0x64>) + 80033d6: 681b ldr r3, [r3, #0] + 80033d8: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 80033da: 4b08 ldr r3, [pc, #32] ; (80033fc <_sbrk+0x64>) + 80033dc: 681a ldr r2, [r3, #0] + 80033de: 687b ldr r3, [r7, #4] + 80033e0: 4413 add r3, r2 + 80033e2: 4a06 ldr r2, [pc, #24] ; (80033fc <_sbrk+0x64>) + 80033e4: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 80033e6: 68fb ldr r3, [r7, #12] +} + 80033e8: 4618 mov r0, r3 + 80033ea: 371c adds r7, #28 + 80033ec: 46bd mov sp, r7 + 80033ee: f85d 7b04 ldr.w r7, [sp], #4 + 80033f2: 4770 bx lr + 80033f4: 20050000 .word 0x20050000 + 80033f8: 00000400 .word 0x00000400 + 80033fc: 20000758 .word 0x20000758 + 8003400: 2000d0f0 .word 0x2000d0f0 + 8003404: 2000d0ec .word 0x2000d0ec + +08003408 : + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8003408: b480 push {r7} + 800340a: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 800340c: 4b15 ldr r3, [pc, #84] ; (8003464 ) + 800340e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003412: 4a14 ldr r2, [pc, #80] ; (8003464 ) + 8003414: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8003418: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 800341c: 4b12 ldr r3, [pc, #72] ; (8003468 ) + 800341e: 681b ldr r3, [r3, #0] + 8003420: 4a11 ldr r2, [pc, #68] ; (8003468 ) + 8003422: f043 0301 orr.w r3, r3, #1 + 8003426: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8003428: 4b0f ldr r3, [pc, #60] ; (8003468 ) + 800342a: 2200 movs r2, #0 + 800342c: 609a str r2, [r3, #8] + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 800342e: 4b0e ldr r3, [pc, #56] ; (8003468 ) + 8003430: 681a ldr r2, [r3, #0] + 8003432: 490d ldr r1, [pc, #52] ; (8003468 ) + 8003434: 4b0d ldr r3, [pc, #52] ; (800346c ) + 8003436: 4013 ands r3, r2 + 8003438: 600b str r3, [r1, #0] + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + 800343a: 4b0b ldr r3, [pc, #44] ; (8003468 ) + 800343c: 4a0c ldr r2, [pc, #48] ; (8003470 ) + 800343e: 605a str r2, [r3, #4] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 8003440: 4b09 ldr r3, [pc, #36] ; (8003468 ) + 8003442: 681b ldr r3, [r3, #0] + 8003444: 4a08 ldr r2, [pc, #32] ; (8003468 ) + 8003446: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 800344a: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + 800344c: 4b06 ldr r3, [pc, #24] ; (8003468 ) + 800344e: 2200 movs r2, #0 + 8003450: 60da str r2, [r3, #12] + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8003452: 4b04 ldr r3, [pc, #16] ; (8003464 ) + 8003454: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8003458: 609a str r2, [r3, #8] +#endif +} + 800345a: bf00 nop + 800345c: 46bd mov sp, r7 + 800345e: f85d 7b04 ldr.w r7, [sp], #4 + 8003462: 4770 bx lr + 8003464: e000ed00 .word 0xe000ed00 + 8003468: 40023800 .word 0x40023800 + 800346c: fef6ffff .word 0xfef6ffff + 8003470: 24003010 .word 0x24003010 + +08003474 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8003474: f8df d034 ldr.w sp, [pc, #52] ; 80034ac + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8003478: 2100 movs r1, #0 + b LoopCopyDataInit + 800347a: e003 b.n 8003484 + +0800347c : + +CopyDataInit: + ldr r3, =_sidata + 800347c: 4b0c ldr r3, [pc, #48] ; (80034b0 ) + ldr r3, [r3, r1] + 800347e: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8003480: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 8003482: 3104 adds r1, #4 + +08003484 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8003484: 480b ldr r0, [pc, #44] ; (80034b4 ) + ldr r3, =_edata + 8003486: 4b0c ldr r3, [pc, #48] ; (80034b8 ) + adds r2, r0, r1 + 8003488: 1842 adds r2, r0, r1 + cmp r2, r3 + 800348a: 429a cmp r2, r3 + bcc CopyDataInit + 800348c: d3f6 bcc.n 800347c + ldr r2, =_sbss + 800348e: 4a0b ldr r2, [pc, #44] ; (80034bc ) + b LoopFillZerobss + 8003490: e002 b.n 8003498 + +08003492 : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 8003492: 2300 movs r3, #0 + str r3, [r2], #4 + 8003494: f842 3b04 str.w r3, [r2], #4 + +08003498 : + +LoopFillZerobss: + ldr r3, = _ebss + 8003498: 4b09 ldr r3, [pc, #36] ; (80034c0 ) + cmp r2, r3 + 800349a: 429a cmp r2, r3 + bcc FillZerobss + 800349c: d3f9 bcc.n 8003492 + +/* Call the clock system initialization function.*/ + bl SystemInit + 800349e: f7ff ffb3 bl 8003408 +/* Call static constructors */ + bl __libc_init_array + 80034a2: f018 fcbb bl 801be1c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80034a6: f7ff f8a3 bl 80025f0
+ bx lr + 80034aa: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 80034ac: 20050000 .word 0x20050000 + ldr r3, =_sidata + 80034b0: 08023d68 .word 0x08023d68 + ldr r0, =_sdata + 80034b4: 20000000 .word 0x20000000 + ldr r3, =_edata + 80034b8: 20000128 .word 0x20000128 + ldr r2, =_sbss + 80034bc: 20000268 .word 0x20000268 + ldr r3, = _ebss + 80034c0: 2000d0f0 .word 0x2000d0f0 + +080034c4 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80034c4: e7fe b.n 80034c4 + +080034c6 : + * @param ioctx: holds device IO functions. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_ERROR if missing mandatory function + */ +int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx) +{ + 80034c6: b480 push {r7} + 80034c8: b083 sub sp, #12 + 80034ca: af00 add r7, sp, #0 + 80034cc: 6078 str r0, [r7, #4] + 80034ce: 6039 str r1, [r7, #0] + if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick) + 80034d0: 687b ldr r3, [r7, #4] + 80034d2: 2b00 cmp r3, #0 + 80034d4: d00b beq.n 80034ee + 80034d6: 683b ldr r3, [r7, #0] + 80034d8: 68db ldr r3, [r3, #12] + 80034da: 2b00 cmp r3, #0 + 80034dc: d007 beq.n 80034ee + 80034de: 683b ldr r3, [r7, #0] + 80034e0: 689b ldr r3, [r3, #8] + 80034e2: 2b00 cmp r3, #0 + 80034e4: d003 beq.n 80034ee + 80034e6: 683b ldr r3, [r7, #0] + 80034e8: 691b ldr r3, [r3, #16] + 80034ea: 2b00 cmp r3, #0 + 80034ec: d102 bne.n 80034f4 + { + return LAN8742_STATUS_ERROR; + 80034ee: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80034f2: e014 b.n 800351e + } + + pObj->IO.Init = ioctx->Init; + 80034f4: 683b ldr r3, [r7, #0] + 80034f6: 681a ldr r2, [r3, #0] + 80034f8: 687b ldr r3, [r7, #4] + 80034fa: 609a str r2, [r3, #8] + pObj->IO.DeInit = ioctx->DeInit; + 80034fc: 683b ldr r3, [r7, #0] + 80034fe: 685a ldr r2, [r3, #4] + 8003500: 687b ldr r3, [r7, #4] + 8003502: 60da str r2, [r3, #12] + pObj->IO.ReadReg = ioctx->ReadReg; + 8003504: 683b ldr r3, [r7, #0] + 8003506: 68da ldr r2, [r3, #12] + 8003508: 687b ldr r3, [r7, #4] + 800350a: 615a str r2, [r3, #20] + pObj->IO.WriteReg = ioctx->WriteReg; + 800350c: 683b ldr r3, [r7, #0] + 800350e: 689a ldr r2, [r3, #8] + 8003510: 687b ldr r3, [r7, #4] + 8003512: 611a str r2, [r3, #16] + pObj->IO.GetTick = ioctx->GetTick; + 8003514: 683b ldr r3, [r7, #0] + 8003516: 691a ldr r2, [r3, #16] + 8003518: 687b ldr r3, [r7, #4] + 800351a: 619a str r2, [r3, #24] + + return LAN8742_STATUS_OK; + 800351c: 2300 movs r3, #0 +} + 800351e: 4618 mov r0, r3 + 8003520: 370c adds r7, #12 + 8003522: 46bd mov sp, r7 + 8003524: f85d 7b04 ldr.w r7, [sp], #4 + 8003528: 4770 bx lr + +0800352a : + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + * LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset + */ + int32_t LAN8742_Init(lan8742_Object_t *pObj) + { + 800352a: b580 push {r7, lr} + 800352c: b086 sub sp, #24 + 800352e: af00 add r7, sp, #0 + 8003530: 6078 str r0, [r7, #4] + uint32_t tickstart = 0, regvalue = 0, addr = 0; + 8003532: 2300 movs r3, #0 + 8003534: 60fb str r3, [r7, #12] + 8003536: 2300 movs r3, #0 + 8003538: 60bb str r3, [r7, #8] + 800353a: 2300 movs r3, #0 + 800353c: 617b str r3, [r7, #20] + int32_t status = LAN8742_STATUS_OK; + 800353e: 2300 movs r3, #0 + 8003540: 613b str r3, [r7, #16] + + if(pObj->Is_Initialized == 0) + 8003542: 687b ldr r3, [r7, #4] + 8003544: 685b ldr r3, [r3, #4] + 8003546: 2b00 cmp r3, #0 + 8003548: d17c bne.n 8003644 + { + if(pObj->IO.Init != 0) + 800354a: 687b ldr r3, [r7, #4] + 800354c: 689b ldr r3, [r3, #8] + 800354e: 2b00 cmp r3, #0 + 8003550: d002 beq.n 8003558 + { + /* GPIO and Clocks initialization */ + pObj->IO.Init(); + 8003552: 687b ldr r3, [r7, #4] + 8003554: 689b ldr r3, [r3, #8] + 8003556: 4798 blx r3 + } + + /* for later check */ + pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1; + 8003558: 687b ldr r3, [r7, #4] + 800355a: 2220 movs r2, #32 + 800355c: 601a str r2, [r3, #0] + + /* Get the device address from special mode register */ + for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) + 800355e: 2300 movs r3, #0 + 8003560: 617b str r3, [r7, #20] + 8003562: e01c b.n 800359e + { + if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0) + 8003564: 687b ldr r3, [r7, #4] + 8003566: 695b ldr r3, [r3, #20] + 8003568: f107 0208 add.w r2, r7, #8 + 800356c: 2112 movs r1, #18 + 800356e: 6978 ldr r0, [r7, #20] + 8003570: 4798 blx r3 + 8003572: 4603 mov r3, r0 + 8003574: 2b00 cmp r3, #0 + 8003576: da03 bge.n 8003580 + { + status = LAN8742_STATUS_READ_ERROR; + 8003578: f06f 0304 mvn.w r3, #4 + 800357c: 613b str r3, [r7, #16] + /* Can't read from this device address + continue with next address */ + continue; + 800357e: e00b b.n 8003598 + } + + if((regvalue & LAN8742_SMR_PHY_ADDR) == addr) + 8003580: 68bb ldr r3, [r7, #8] + 8003582: f003 031f and.w r3, r3, #31 + 8003586: 697a ldr r2, [r7, #20] + 8003588: 429a cmp r2, r3 + 800358a: d105 bne.n 8003598 + { + pObj->DevAddr = addr; + 800358c: 687b ldr r3, [r7, #4] + 800358e: 697a ldr r2, [r7, #20] + 8003590: 601a str r2, [r3, #0] + status = LAN8742_STATUS_OK; + 8003592: 2300 movs r3, #0 + 8003594: 613b str r3, [r7, #16] + break; + 8003596: e005 b.n 80035a4 + for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) + 8003598: 697b ldr r3, [r7, #20] + 800359a: 3301 adds r3, #1 + 800359c: 617b str r3, [r7, #20] + 800359e: 697b ldr r3, [r7, #20] + 80035a0: 2b1f cmp r3, #31 + 80035a2: d9df bls.n 8003564 + } + } + + if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR) + 80035a4: 687b ldr r3, [r7, #4] + 80035a6: 681b ldr r3, [r3, #0] + 80035a8: 2b1f cmp r3, #31 + 80035aa: d902 bls.n 80035b2 + { + status = LAN8742_STATUS_ADDRESS_ERROR; + 80035ac: f06f 0302 mvn.w r3, #2 + 80035b0: 613b str r3, [r7, #16] + } + + /* if device address is matched */ + if(status == LAN8742_STATUS_OK) + 80035b2: 693b ldr r3, [r7, #16] + 80035b4: 2b00 cmp r3, #0 + 80035b6: d145 bne.n 8003644 + { + /* set a software reset */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0) + 80035b8: 687b ldr r3, [r7, #4] + 80035ba: 691b ldr r3, [r3, #16] + 80035bc: 687a ldr r2, [r7, #4] + 80035be: 6810 ldr r0, [r2, #0] + 80035c0: f44f 4200 mov.w r2, #32768 ; 0x8000 + 80035c4: 2100 movs r1, #0 + 80035c6: 4798 blx r3 + 80035c8: 4603 mov r3, r0 + 80035ca: 2b00 cmp r3, #0 + 80035cc: db37 blt.n 800363e + { + /* get software reset status */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0) + 80035ce: 687b ldr r3, [r7, #4] + 80035d0: 695b ldr r3, [r3, #20] + 80035d2: 687a ldr r2, [r7, #4] + 80035d4: 6810 ldr r0, [r2, #0] + 80035d6: f107 0208 add.w r2, r7, #8 + 80035da: 2100 movs r1, #0 + 80035dc: 4798 blx r3 + 80035de: 4603 mov r3, r0 + 80035e0: 2b00 cmp r3, #0 + 80035e2: db28 blt.n 8003636 + { + tickstart = pObj->IO.GetTick(); + 80035e4: 687b ldr r3, [r7, #4] + 80035e6: 699b ldr r3, [r3, #24] + 80035e8: 4798 blx r3 + 80035ea: 4603 mov r3, r0 + 80035ec: 60fb str r3, [r7, #12] + + /* wait until software reset is done or timeout occured */ + while(regvalue & LAN8742_BCR_SOFT_RESET) + 80035ee: e01c b.n 800362a + { + if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO) + 80035f0: 687b ldr r3, [r7, #4] + 80035f2: 699b ldr r3, [r3, #24] + 80035f4: 4798 blx r3 + 80035f6: 4603 mov r3, r0 + 80035f8: 461a mov r2, r3 + 80035fa: 68fb ldr r3, [r7, #12] + 80035fc: 1ad3 subs r3, r2, r3 + 80035fe: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 8003602: d80e bhi.n 8003622 + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0) + 8003604: 687b ldr r3, [r7, #4] + 8003606: 695b ldr r3, [r3, #20] + 8003608: 687a ldr r2, [r7, #4] + 800360a: 6810 ldr r0, [r2, #0] + 800360c: f107 0208 add.w r2, r7, #8 + 8003610: 2100 movs r1, #0 + 8003612: 4798 blx r3 + 8003614: 4603 mov r3, r0 + 8003616: 2b00 cmp r3, #0 + 8003618: da07 bge.n 800362a + { + status = LAN8742_STATUS_READ_ERROR; + 800361a: f06f 0304 mvn.w r3, #4 + 800361e: 613b str r3, [r7, #16] + break; + 8003620: e010 b.n 8003644 + } + } + else + { + status = LAN8742_STATUS_RESET_TIMEOUT; + 8003622: f06f 0301 mvn.w r3, #1 + 8003626: 613b str r3, [r7, #16] + break; + 8003628: e00c b.n 8003644 + while(regvalue & LAN8742_BCR_SOFT_RESET) + 800362a: 68bb ldr r3, [r7, #8] + 800362c: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8003630: 2b00 cmp r3, #0 + 8003632: d1dd bne.n 80035f0 + 8003634: e006 b.n 8003644 + } + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + 8003636: f06f 0304 mvn.w r3, #4 + 800363a: 613b str r3, [r7, #16] + 800363c: e002 b.n 8003644 + } + } + else + { + status = LAN8742_STATUS_WRITE_ERROR; + 800363e: f06f 0303 mvn.w r3, #3 + 8003642: 613b str r3, [r7, #16] + } + } + } + + if(status == LAN8742_STATUS_OK) + 8003644: 693b ldr r3, [r7, #16] + 8003646: 2b00 cmp r3, #0 + 8003648: d112 bne.n 8003670 + { + tickstart = pObj->IO.GetTick(); + 800364a: 687b ldr r3, [r7, #4] + 800364c: 699b ldr r3, [r3, #24] + 800364e: 4798 blx r3 + 8003650: 4603 mov r3, r0 + 8003652: 60fb str r3, [r7, #12] + + /* Wait for 2s to perform initialization */ + while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO) + 8003654: bf00 nop + 8003656: 687b ldr r3, [r7, #4] + 8003658: 699b ldr r3, [r3, #24] + 800365a: 4798 blx r3 + 800365c: 4603 mov r3, r0 + 800365e: 461a mov r2, r3 + 8003660: 68fb ldr r3, [r7, #12] + 8003662: 1ad3 subs r3, r2, r3 + 8003664: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 + 8003668: d9f5 bls.n 8003656 + { + } + pObj->Is_Initialized = 1; + 800366a: 687b ldr r3, [r7, #4] + 800366c: 2201 movs r2, #1 + 800366e: 605a str r2, [r3, #4] + } + + return status; + 8003670: 693b ldr r3, [r7, #16] + } + 8003672: 4618 mov r0, r3 + 8003674: 3718 adds r7, #24 + 8003676: 46bd mov sp, r7 + 8003678: bd80 pop {r7, pc} + +0800367a : + * LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj) +{ + 800367a: b580 push {r7, lr} + 800367c: b084 sub sp, #16 + 800367e: af00 add r7, sp, #0 + 8003680: 6078 str r0, [r7, #4] + uint32_t readval = 0; + 8003682: 2300 movs r3, #0 + 8003684: 60fb str r3, [r7, #12] + + /* Read Status register */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + 8003686: 687b ldr r3, [r7, #4] + 8003688: 695b ldr r3, [r3, #20] + 800368a: 687a ldr r2, [r7, #4] + 800368c: 6810 ldr r0, [r2, #0] + 800368e: f107 020c add.w r2, r7, #12 + 8003692: 2101 movs r1, #1 + 8003694: 4798 blx r3 + 8003696: 4603 mov r3, r0 + 8003698: 2b00 cmp r3, #0 + 800369a: da02 bge.n 80036a2 + { + return LAN8742_STATUS_READ_ERROR; + 800369c: f06f 0304 mvn.w r3, #4 + 80036a0: e06e b.n 8003780 + } + + /* Read Status register again */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + 80036a2: 687b ldr r3, [r7, #4] + 80036a4: 695b ldr r3, [r3, #20] + 80036a6: 687a ldr r2, [r7, #4] + 80036a8: 6810 ldr r0, [r2, #0] + 80036aa: f107 020c add.w r2, r7, #12 + 80036ae: 2101 movs r1, #1 + 80036b0: 4798 blx r3 + 80036b2: 4603 mov r3, r0 + 80036b4: 2b00 cmp r3, #0 + 80036b6: da02 bge.n 80036be + { + return LAN8742_STATUS_READ_ERROR; + 80036b8: f06f 0304 mvn.w r3, #4 + 80036bc: e060 b.n 8003780 + } + + if((readval & LAN8742_BSR_LINK_STATUS) == 0) + 80036be: 68fb ldr r3, [r7, #12] + 80036c0: f003 0304 and.w r3, r3, #4 + 80036c4: 2b00 cmp r3, #0 + 80036c6: d101 bne.n 80036cc + { + /* Return Link Down status */ + return LAN8742_STATUS_LINK_DOWN; + 80036c8: 2301 movs r3, #1 + 80036ca: e059 b.n 8003780 + } + + /* Check Auto negotiaition */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0) + 80036cc: 687b ldr r3, [r7, #4] + 80036ce: 695b ldr r3, [r3, #20] + 80036d0: 687a ldr r2, [r7, #4] + 80036d2: 6810 ldr r0, [r2, #0] + 80036d4: f107 020c add.w r2, r7, #12 + 80036d8: 2100 movs r1, #0 + 80036da: 4798 blx r3 + 80036dc: 4603 mov r3, r0 + 80036de: 2b00 cmp r3, #0 + 80036e0: da02 bge.n 80036e8 + { + return LAN8742_STATUS_READ_ERROR; + 80036e2: f06f 0304 mvn.w r3, #4 + 80036e6: e04b b.n 8003780 + } + + if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN) + 80036e8: 68fb ldr r3, [r7, #12] + 80036ea: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 80036ee: 2b00 cmp r3, #0 + 80036f0: d11b bne.n 800372a + { + if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) + 80036f2: 68fb ldr r3, [r7, #12] + 80036f4: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 80036f8: 2b00 cmp r3, #0 + 80036fa: d006 beq.n 800370a + 80036fc: 68fb ldr r3, [r7, #12] + 80036fe: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003702: 2b00 cmp r3, #0 + 8003704: d001 beq.n 800370a + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + 8003706: 2302 movs r3, #2 + 8003708: e03a b.n 8003780 + } + else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) + 800370a: 68fb ldr r3, [r7, #12] + 800370c: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8003710: 2b00 cmp r3, #0 + 8003712: d001 beq.n 8003718 + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + 8003714: 2303 movs r3, #3 + 8003716: e033 b.n 8003780 + } + else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE) + 8003718: 68fb ldr r3, [r7, #12] + 800371a: f403 7380 and.w r3, r3, #256 ; 0x100 + 800371e: 2b00 cmp r3, #0 + 8003720: d001 beq.n 8003726 + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + 8003722: 2304 movs r3, #4 + 8003724: e02c b.n 8003780 + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + 8003726: 2305 movs r3, #5 + 8003728: e02a b.n 8003780 + } + } + else /* Auto Nego enabled */ + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0) + 800372a: 687b ldr r3, [r7, #4] + 800372c: 695b ldr r3, [r3, #20] + 800372e: 687a ldr r2, [r7, #4] + 8003730: 6810 ldr r0, [r2, #0] + 8003732: f107 020c add.w r2, r7, #12 + 8003736: 211f movs r1, #31 + 8003738: 4798 blx r3 + 800373a: 4603 mov r3, r0 + 800373c: 2b00 cmp r3, #0 + 800373e: da02 bge.n 8003746 + { + return LAN8742_STATUS_READ_ERROR; + 8003740: f06f 0304 mvn.w r3, #4 + 8003744: e01c b.n 8003780 + } + + /* Check if auto nego not done */ + if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0) + 8003746: 68fb ldr r3, [r7, #12] + 8003748: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 800374c: 2b00 cmp r3, #0 + 800374e: d101 bne.n 8003754 + { + return LAN8742_STATUS_AUTONEGO_NOTDONE; + 8003750: 2306 movs r3, #6 + 8003752: e015 b.n 8003780 + } + + if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD) + 8003754: 68fb ldr r3, [r7, #12] + 8003756: f003 031c and.w r3, r3, #28 + 800375a: 2b18 cmp r3, #24 + 800375c: d101 bne.n 8003762 + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + 800375e: 2302 movs r3, #2 + 8003760: e00e b.n 8003780 + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD) + 8003762: 68fb ldr r3, [r7, #12] + 8003764: f003 031c and.w r3, r3, #28 + 8003768: 2b08 cmp r3, #8 + 800376a: d101 bne.n 8003770 + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + 800376c: 2303 movs r3, #3 + 800376e: e007 b.n 8003780 + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD) + 8003770: 68fb ldr r3, [r7, #12] + 8003772: f003 031c and.w r3, r3, #28 + 8003776: 2b14 cmp r3, #20 + 8003778: d101 bne.n 800377e + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + 800377a: 2304 movs r3, #4 + 800377c: e000 b.n 8003780 + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + 800377e: 2305 movs r3, #5 + } + } +} + 8003780: 4618 mov r0, r3 + 8003782: 3710 adds r7, #16 + 8003784: 46bd mov sp, r7 + 8003786: bd80 pop {r7, pc} + +08003788 : +/** + * @brief Initializes the LCD. + * @retval LCD state + */ +uint8_t BSP_LCD_Init(void) +{ + 8003788: b580 push {r7, lr} + 800378a: af00 add r7, sp, #0 + /* Select the used LCD */ + + /* The RK043FN48H LCD 480x272 is selected */ + /* Timing Configuration */ + hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1); + 800378c: 4b31 ldr r3, [pc, #196] ; (8003854 ) + 800378e: 2228 movs r2, #40 ; 0x28 + 8003790: 615a str r2, [r3, #20] + hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1); + 8003792: 4b30 ldr r3, [pc, #192] ; (8003854 ) + 8003794: 2209 movs r2, #9 + 8003796: 619a str r2, [r3, #24] + hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + 8003798: 4b2e ldr r3, [pc, #184] ; (8003854 ) + 800379a: 2235 movs r2, #53 ; 0x35 + 800379c: 61da str r2, [r3, #28] + hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + 800379e: 4b2d ldr r3, [pc, #180] ; (8003854 ) + 80037a0: 220b movs r2, #11 + 80037a2: 621a str r2, [r3, #32] + hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + 80037a4: 4b2b ldr r3, [pc, #172] ; (8003854 ) + 80037a6: f240 121b movw r2, #283 ; 0x11b + 80037aa: 629a str r2, [r3, #40] ; 0x28 + hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + 80037ac: 4b29 ldr r3, [pc, #164] ; (8003854 ) + 80037ae: f240 2215 movw r2, #533 ; 0x215 + 80037b2: 625a str r2, [r3, #36] ; 0x24 + hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1); + 80037b4: 4b27 ldr r3, [pc, #156] ; (8003854 ) + 80037b6: f240 121d movw r2, #285 ; 0x11d + 80037ba: 631a str r2, [r3, #48] ; 0x30 + hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1); + 80037bc: 4b25 ldr r3, [pc, #148] ; (8003854 ) + 80037be: f240 2235 movw r2, #565 ; 0x235 + 80037c2: 62da str r2, [r3, #44] ; 0x2c + + /* LCD clock configuration */ + BSP_LCD_ClockConfig(&hLtdcHandler, NULL); + 80037c4: 2100 movs r1, #0 + 80037c6: 4823 ldr r0, [pc, #140] ; (8003854 ) + 80037c8: f000 fd5c bl 8004284 + + /* Initialize the LCD pixel width and pixel height */ + hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH; + 80037cc: 4b21 ldr r3, [pc, #132] ; (8003854 ) + 80037ce: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 80037d2: 661a str r2, [r3, #96] ; 0x60 + hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT; + 80037d4: 4b1f ldr r3, [pc, #124] ; (8003854 ) + 80037d6: f44f 7288 mov.w r2, #272 ; 0x110 + 80037da: 665a str r2, [r3, #100] ; 0x64 + + /* Background value */ + hLtdcHandler.Init.Backcolor.Blue = 0; + 80037dc: 4b1d ldr r3, [pc, #116] ; (8003854 ) + 80037de: 2200 movs r2, #0 + 80037e0: f883 2034 strb.w r2, [r3, #52] ; 0x34 + hLtdcHandler.Init.Backcolor.Green = 0; + 80037e4: 4b1b ldr r3, [pc, #108] ; (8003854 ) + 80037e6: 2200 movs r2, #0 + 80037e8: f883 2035 strb.w r2, [r3, #53] ; 0x35 + hLtdcHandler.Init.Backcolor.Red = 0; + 80037ec: 4b19 ldr r3, [pc, #100] ; (8003854 ) + 80037ee: 2200 movs r2, #0 + 80037f0: f883 2036 strb.w r2, [r3, #54] ; 0x36 + + /* Polarity */ + hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL; + 80037f4: 4b17 ldr r3, [pc, #92] ; (8003854 ) + 80037f6: 2200 movs r2, #0 + 80037f8: 605a str r2, [r3, #4] + hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL; + 80037fa: 4b16 ldr r3, [pc, #88] ; (8003854 ) + 80037fc: 2200 movs r2, #0 + 80037fe: 609a str r2, [r3, #8] + hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL; + 8003800: 4b14 ldr r3, [pc, #80] ; (8003854 ) + 8003802: 2200 movs r2, #0 + 8003804: 60da str r2, [r3, #12] + hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + 8003806: 4b13 ldr r3, [pc, #76] ; (8003854 ) + 8003808: 2200 movs r2, #0 + 800380a: 611a str r2, [r3, #16] + hLtdcHandler.Instance = LTDC; + 800380c: 4b11 ldr r3, [pc, #68] ; (8003854 ) + 800380e: 4a12 ldr r2, [pc, #72] ; (8003858 ) + 8003810: 601a str r2, [r3, #0] + + if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET) + 8003812: 4810 ldr r0, [pc, #64] ; (8003854 ) + 8003814: f003 ff02 bl 800761c + 8003818: 4603 mov r3, r0 + 800381a: 2b00 cmp r3, #0 + 800381c: d103 bne.n 8003826 + { + /* Initialize the LCD Msp: this __weak function can be rewritten by the application */ + BSP_LCD_MspInit(&hLtdcHandler, NULL); + 800381e: 2100 movs r1, #0 + 8003820: 480c ldr r0, [pc, #48] ; (8003854 ) + 8003822: f000 fc55 bl 80040d0 + } + HAL_LTDC_Init(&hLtdcHandler); + 8003826: 480b ldr r0, [pc, #44] ; (8003854 ) + 8003828: f003 fdea bl 8007400 + + /* Assert display enable LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); + 800382c: 2201 movs r2, #1 + 800382e: f44f 5180 mov.w r1, #4096 ; 0x1000 + 8003832: 480a ldr r0, [pc, #40] ; (800385c ) + 8003834: f003 f974 bl 8006b20 + + /* Assert backlight LCD_BL_CTRL pin */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); + 8003838: 2201 movs r2, #1 + 800383a: 2108 movs r1, #8 + 800383c: 4808 ldr r0, [pc, #32] ; (8003860 ) + 800383e: f003 f96f bl 8006b20 + +#if !defined(DATA_IN_ExtSDRAM) + /* Initialize the SDRAM */ + BSP_SDRAM_Init(); + 8003842: f000 fe3f bl 80044c4 +#endif + + /* Initialize the font */ + BSP_LCD_SetFont(&LCD_DEFAULT_FONT); + 8003846: 4807 ldr r0, [pc, #28] ; (8003864 ) + 8003848: f000 f8d8 bl 80039fc + + return LCD_OK; + 800384c: 2300 movs r3, #0 +} + 800384e: 4618 mov r0, r3 + 8003850: bd80 pop {r7, pc} + 8003852: bf00 nop + 8003854: 2000075c .word 0x2000075c + 8003858: 40016800 .word 0x40016800 + 800385c: 40022000 .word 0x40022000 + 8003860: 40022800 .word 0x40022800 + 8003864: 20000080 .word 0x20000080 + +08003868 : +/** + * @brief Gets the LCD X size. + * @retval Used LCD X size + */ +uint32_t BSP_LCD_GetXSize(void) +{ + 8003868: b480 push {r7} + 800386a: af00 add r7, sp, #0 + return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth; + 800386c: 4b06 ldr r3, [pc, #24] ; (8003888 ) + 800386e: 681b ldr r3, [r3, #0] + 8003870: 4a06 ldr r2, [pc, #24] ; (800388c ) + 8003872: 2134 movs r1, #52 ; 0x34 + 8003874: fb01 f303 mul.w r3, r1, r3 + 8003878: 4413 add r3, r2 + 800387a: 3360 adds r3, #96 ; 0x60 + 800387c: 681b ldr r3, [r3, #0] +} + 800387e: 4618 mov r0, r3 + 8003880: 46bd mov sp, r7 + 8003882: f85d 7b04 ldr.w r7, [sp], #4 + 8003886: 4770 bx lr + 8003888: 20000844 .word 0x20000844 + 800388c: 2000075c .word 0x2000075c + +08003890 : +/** + * @brief Gets the LCD Y size. + * @retval Used LCD Y size + */ +uint32_t BSP_LCD_GetYSize(void) +{ + 8003890: b480 push {r7} + 8003892: af00 add r7, sp, #0 + return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight; + 8003894: 4b06 ldr r3, [pc, #24] ; (80038b0 ) + 8003896: 681b ldr r3, [r3, #0] + 8003898: 4a06 ldr r2, [pc, #24] ; (80038b4 ) + 800389a: 2134 movs r1, #52 ; 0x34 + 800389c: fb01 f303 mul.w r3, r1, r3 + 80038a0: 4413 add r3, r2 + 80038a2: 3364 adds r3, #100 ; 0x64 + 80038a4: 681b ldr r3, [r3, #0] +} + 80038a6: 4618 mov r0, r3 + 80038a8: 46bd mov sp, r7 + 80038aa: f85d 7b04 ldr.w r7, [sp], #4 + 80038ae: 4770 bx lr + 80038b0: 20000844 .word 0x20000844 + 80038b4: 2000075c .word 0x2000075c + +080038b8 : + * @param LayerIndex: Layer foreground or background + * @param FB_Address: Layer frame buffer + * @retval None + */ +void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address) +{ + 80038b8: b580 push {r7, lr} + 80038ba: b090 sub sp, #64 ; 0x40 + 80038bc: af00 add r7, sp, #0 + 80038be: 4603 mov r3, r0 + 80038c0: 6039 str r1, [r7, #0] + 80038c2: 80fb strh r3, [r7, #6] + LCD_LayerCfgTypeDef layer_cfg; + + /* Layer Init */ + layer_cfg.WindowX0 = 0; + 80038c4: 2300 movs r3, #0 + 80038c6: 60fb str r3, [r7, #12] + layer_cfg.WindowX1 = BSP_LCD_GetXSize(); + 80038c8: f7ff ffce bl 8003868 + 80038cc: 4603 mov r3, r0 + 80038ce: 613b str r3, [r7, #16] + layer_cfg.WindowY0 = 0; + 80038d0: 2300 movs r3, #0 + 80038d2: 617b str r3, [r7, #20] + layer_cfg.WindowY1 = BSP_LCD_GetYSize(); + 80038d4: f7ff ffdc bl 8003890 + 80038d8: 4603 mov r3, r0 + 80038da: 61bb str r3, [r7, #24] + layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + 80038dc: 2300 movs r3, #0 + 80038de: 61fb str r3, [r7, #28] + layer_cfg.FBStartAdress = FB_Address; + 80038e0: 683b ldr r3, [r7, #0] + 80038e2: 633b str r3, [r7, #48] ; 0x30 + layer_cfg.Alpha = 255; + 80038e4: 23ff movs r3, #255 ; 0xff + 80038e6: 623b str r3, [r7, #32] + layer_cfg.Alpha0 = 0; + 80038e8: 2300 movs r3, #0 + 80038ea: 627b str r3, [r7, #36] ; 0x24 + layer_cfg.Backcolor.Blue = 0; + 80038ec: 2300 movs r3, #0 + 80038ee: f887 303c strb.w r3, [r7, #60] ; 0x3c + layer_cfg.Backcolor.Green = 0; + 80038f2: 2300 movs r3, #0 + 80038f4: f887 303d strb.w r3, [r7, #61] ; 0x3d + layer_cfg.Backcolor.Red = 0; + 80038f8: 2300 movs r3, #0 + 80038fa: f887 303e strb.w r3, [r7, #62] ; 0x3e + layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + 80038fe: f44f 63c0 mov.w r3, #1536 ; 0x600 + 8003902: 62bb str r3, [r7, #40] ; 0x28 + layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + 8003904: 2307 movs r3, #7 + 8003906: 62fb str r3, [r7, #44] ; 0x2c + layer_cfg.ImageWidth = BSP_LCD_GetXSize(); + 8003908: f7ff ffae bl 8003868 + 800390c: 4603 mov r3, r0 + 800390e: 637b str r3, [r7, #52] ; 0x34 + layer_cfg.ImageHeight = BSP_LCD_GetYSize(); + 8003910: f7ff ffbe bl 8003890 + 8003914: 4603 mov r3, r0 + 8003916: 63bb str r3, [r7, #56] ; 0x38 + + HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex); + 8003918: 88fa ldrh r2, [r7, #6] + 800391a: f107 030c add.w r3, r7, #12 + 800391e: 4619 mov r1, r3 + 8003920: 4812 ldr r0, [pc, #72] ; (800396c ) + 8003922: f003 fe3d bl 80075a0 + + DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE; + 8003926: 88fa ldrh r2, [r7, #6] + 8003928: 4911 ldr r1, [pc, #68] ; (8003970 ) + 800392a: 4613 mov r3, r2 + 800392c: 005b lsls r3, r3, #1 + 800392e: 4413 add r3, r2 + 8003930: 009b lsls r3, r3, #2 + 8003932: 440b add r3, r1 + 8003934: 3304 adds r3, #4 + 8003936: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800393a: 601a str r2, [r3, #0] + DrawProp[LayerIndex].pFont = &Font24; + 800393c: 88fa ldrh r2, [r7, #6] + 800393e: 490c ldr r1, [pc, #48] ; (8003970 ) + 8003940: 4613 mov r3, r2 + 8003942: 005b lsls r3, r3, #1 + 8003944: 4413 add r3, r2 + 8003946: 009b lsls r3, r3, #2 + 8003948: 440b add r3, r1 + 800394a: 3308 adds r3, #8 + 800394c: 4a09 ldr r2, [pc, #36] ; (8003974 ) + 800394e: 601a str r2, [r3, #0] + DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK; + 8003950: 88fa ldrh r2, [r7, #6] + 8003952: 4907 ldr r1, [pc, #28] ; (8003970 ) + 8003954: 4613 mov r3, r2 + 8003956: 005b lsls r3, r3, #1 + 8003958: 4413 add r3, r2 + 800395a: 009b lsls r3, r3, #2 + 800395c: 440b add r3, r1 + 800395e: f04f 427f mov.w r2, #4278190080 ; 0xff000000 + 8003962: 601a str r2, [r3, #0] +} + 8003964: bf00 nop + 8003966: 3740 adds r7, #64 ; 0x40 + 8003968: 46bd mov sp, r7 + 800396a: bd80 pop {r7, pc} + 800396c: 2000075c .word 0x2000075c + 8003970: 20000848 .word 0x20000848 + 8003974: 20000080 .word 0x20000080 + +08003978 : + * @brief Selects the LCD Layer. + * @param LayerIndex: Layer foreground or background + * @retval None + */ +void BSP_LCD_SelectLayer(uint32_t LayerIndex) +{ + 8003978: b480 push {r7} + 800397a: b083 sub sp, #12 + 800397c: af00 add r7, sp, #0 + 800397e: 6078 str r0, [r7, #4] + ActiveLayer = LayerIndex; + 8003980: 4a04 ldr r2, [pc, #16] ; (8003994 ) + 8003982: 687b ldr r3, [r7, #4] + 8003984: 6013 str r3, [r2, #0] +} + 8003986: bf00 nop + 8003988: 370c adds r7, #12 + 800398a: 46bd mov sp, r7 + 800398c: f85d 7b04 ldr.w r7, [sp], #4 + 8003990: 4770 bx lr + 8003992: bf00 nop + 8003994: 20000844 .word 0x20000844 + +08003998 : + * @brief Sets the LCD text color. + * @param Color: Text color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetTextColor(uint32_t Color) +{ + 8003998: b480 push {r7} + 800399a: b083 sub sp, #12 + 800399c: af00 add r7, sp, #0 + 800399e: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].TextColor = Color; + 80039a0: 4b07 ldr r3, [pc, #28] ; (80039c0 ) + 80039a2: 681a ldr r2, [r3, #0] + 80039a4: 4907 ldr r1, [pc, #28] ; (80039c4 ) + 80039a6: 4613 mov r3, r2 + 80039a8: 005b lsls r3, r3, #1 + 80039aa: 4413 add r3, r2 + 80039ac: 009b lsls r3, r3, #2 + 80039ae: 440b add r3, r1 + 80039b0: 687a ldr r2, [r7, #4] + 80039b2: 601a str r2, [r3, #0] +} + 80039b4: bf00 nop + 80039b6: 370c adds r7, #12 + 80039b8: 46bd mov sp, r7 + 80039ba: f85d 7b04 ldr.w r7, [sp], #4 + 80039be: 4770 bx lr + 80039c0: 20000844 .word 0x20000844 + 80039c4: 20000848 .word 0x20000848 + +080039c8 : + * @brief Sets the LCD background color. + * @param Color: Layer background color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetBackColor(uint32_t Color) +{ + 80039c8: b480 push {r7} + 80039ca: b083 sub sp, #12 + 80039cc: af00 add r7, sp, #0 + 80039ce: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].BackColor = Color; + 80039d0: 4b08 ldr r3, [pc, #32] ; (80039f4 ) + 80039d2: 681a ldr r2, [r3, #0] + 80039d4: 4908 ldr r1, [pc, #32] ; (80039f8 ) + 80039d6: 4613 mov r3, r2 + 80039d8: 005b lsls r3, r3, #1 + 80039da: 4413 add r3, r2 + 80039dc: 009b lsls r3, r3, #2 + 80039de: 440b add r3, r1 + 80039e0: 3304 adds r3, #4 + 80039e2: 687a ldr r2, [r7, #4] + 80039e4: 601a str r2, [r3, #0] +} + 80039e6: bf00 nop + 80039e8: 370c adds r7, #12 + 80039ea: 46bd mov sp, r7 + 80039ec: f85d 7b04 ldr.w r7, [sp], #4 + 80039f0: 4770 bx lr + 80039f2: bf00 nop + 80039f4: 20000844 .word 0x20000844 + 80039f8: 20000848 .word 0x20000848 + +080039fc : + * @brief Sets the LCD text font. + * @param fonts: Layer font to be used + * @retval None + */ +void BSP_LCD_SetFont(sFONT *fonts) +{ + 80039fc: b480 push {r7} + 80039fe: b083 sub sp, #12 + 8003a00: af00 add r7, sp, #0 + 8003a02: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].pFont = fonts; + 8003a04: 4b08 ldr r3, [pc, #32] ; (8003a28 ) + 8003a06: 681a ldr r2, [r3, #0] + 8003a08: 4908 ldr r1, [pc, #32] ; (8003a2c ) + 8003a0a: 4613 mov r3, r2 + 8003a0c: 005b lsls r3, r3, #1 + 8003a0e: 4413 add r3, r2 + 8003a10: 009b lsls r3, r3, #2 + 8003a12: 440b add r3, r1 + 8003a14: 3308 adds r3, #8 + 8003a16: 687a ldr r2, [r7, #4] + 8003a18: 601a str r2, [r3, #0] +} + 8003a1a: bf00 nop + 8003a1c: 370c adds r7, #12 + 8003a1e: 46bd mov sp, r7 + 8003a20: f85d 7b04 ldr.w r7, [sp], #4 + 8003a24: 4770 bx lr + 8003a26: bf00 nop + 8003a28: 20000844 .word 0x20000844 + 8003a2c: 20000848 .word 0x20000848 + +08003a30 : + * @brief Clears the hole LCD. + * @param Color: Color of the background + * @retval None + */ +void BSP_LCD_Clear(uint32_t Color) +{ + 8003a30: b5f0 push {r4, r5, r6, r7, lr} + 8003a32: b085 sub sp, #20 + 8003a34: af02 add r7, sp, #8 + 8003a36: 6078 str r0, [r7, #4] + /* Clear the LCD */ + LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color); + 8003a38: 4b0f ldr r3, [pc, #60] ; (8003a78 ) + 8003a3a: 681c ldr r4, [r3, #0] + 8003a3c: 4b0e ldr r3, [pc, #56] ; (8003a78 ) + 8003a3e: 681b ldr r3, [r3, #0] + 8003a40: 4a0e ldr r2, [pc, #56] ; (8003a7c ) + 8003a42: 2134 movs r1, #52 ; 0x34 + 8003a44: fb01 f303 mul.w r3, r1, r3 + 8003a48: 4413 add r3, r2 + 8003a4a: 335c adds r3, #92 ; 0x5c + 8003a4c: 681b ldr r3, [r3, #0] + 8003a4e: 461e mov r6, r3 + 8003a50: f7ff ff0a bl 8003868 + 8003a54: 4605 mov r5, r0 + 8003a56: f7ff ff1b bl 8003890 + 8003a5a: 4602 mov r2, r0 + 8003a5c: 687b ldr r3, [r7, #4] + 8003a5e: 9301 str r3, [sp, #4] + 8003a60: 2300 movs r3, #0 + 8003a62: 9300 str r3, [sp, #0] + 8003a64: 4613 mov r3, r2 + 8003a66: 462a mov r2, r5 + 8003a68: 4631 mov r1, r6 + 8003a6a: 4620 mov r0, r4 + 8003a6c: f000 fcde bl 800442c +} + 8003a70: bf00 nop + 8003a72: 370c adds r7, #12 + 8003a74: 46bd mov sp, r7 + 8003a76: bdf0 pop {r4, r5, r6, r7, pc} + 8003a78: 20000844 .word 0x20000844 + 8003a7c: 2000075c .word 0x2000075c + +08003a80 : + * @param Ascii: Character ascii code + * This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E + * @retval None + */ +void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii) +{ + 8003a80: b590 push {r4, r7, lr} + 8003a82: b083 sub sp, #12 + 8003a84: af00 add r7, sp, #0 + 8003a86: 4603 mov r3, r0 + 8003a88: 80fb strh r3, [r7, #6] + 8003a8a: 460b mov r3, r1 + 8003a8c: 80bb strh r3, [r7, #4] + 8003a8e: 4613 mov r3, r2 + 8003a90: 70fb strb r3, [r7, #3] + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 8003a92: 4b1b ldr r3, [pc, #108] ; (8003b00 ) + 8003a94: 681a ldr r2, [r3, #0] + 8003a96: 491b ldr r1, [pc, #108] ; (8003b04 ) + 8003a98: 4613 mov r3, r2 + 8003a9a: 005b lsls r3, r3, #1 + 8003a9c: 4413 add r3, r2 + 8003a9e: 009b lsls r3, r3, #2 + 8003aa0: 440b add r3, r1 + 8003aa2: 3308 adds r3, #8 + 8003aa4: 681b ldr r3, [r3, #0] + 8003aa6: 6819 ldr r1, [r3, #0] + 8003aa8: 78fb ldrb r3, [r7, #3] + 8003aaa: f1a3 0020 sub.w r0, r3, #32 + DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]); + 8003aae: 4b14 ldr r3, [pc, #80] ; (8003b00 ) + 8003ab0: 681a ldr r2, [r3, #0] + 8003ab2: 4c14 ldr r4, [pc, #80] ; (8003b04 ) + 8003ab4: 4613 mov r3, r2 + 8003ab6: 005b lsls r3, r3, #1 + 8003ab8: 4413 add r3, r2 + 8003aba: 009b lsls r3, r3, #2 + 8003abc: 4423 add r3, r4 + 8003abe: 3308 adds r3, #8 + 8003ac0: 681b ldr r3, [r3, #0] + 8003ac2: 88db ldrh r3, [r3, #6] + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 8003ac4: fb03 f000 mul.w r0, r3, r0 + DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]); + 8003ac8: 4b0d ldr r3, [pc, #52] ; (8003b00 ) + 8003aca: 681a ldr r2, [r3, #0] + 8003acc: 4c0d ldr r4, [pc, #52] ; (8003b04 ) + 8003ace: 4613 mov r3, r2 + 8003ad0: 005b lsls r3, r3, #1 + 8003ad2: 4413 add r3, r2 + 8003ad4: 009b lsls r3, r3, #2 + 8003ad6: 4423 add r3, r4 + 8003ad8: 3308 adds r3, #8 + 8003ada: 681b ldr r3, [r3, #0] + 8003adc: 889b ldrh r3, [r3, #4] + 8003ade: 3307 adds r3, #7 + 8003ae0: 2b00 cmp r3, #0 + 8003ae2: da00 bge.n 8003ae6 + 8003ae4: 3307 adds r3, #7 + 8003ae6: 10db asrs r3, r3, #3 + 8003ae8: fb00 f303 mul.w r3, r0, r3 + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 8003aec: 18ca adds r2, r1, r3 + 8003aee: 88b9 ldrh r1, [r7, #4] + 8003af0: 88fb ldrh r3, [r7, #6] + 8003af2: 4618 mov r0, r3 + 8003af4: f000 fbe2 bl 80042bc +} + 8003af8: bf00 nop + 8003afa: 370c adds r7, #12 + 8003afc: 46bd mov sp, r7 + 8003afe: bd90 pop {r4, r7, pc} + 8003b00: 20000844 .word 0x20000844 + 8003b04: 20000848 .word 0x20000848 + +08003b08 : + * @arg RIGHT_MODE + * @arg LEFT_MODE + * @retval None + */ +void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode) +{ + 8003b08: b5b0 push {r4, r5, r7, lr} + 8003b0a: b088 sub sp, #32 + 8003b0c: af00 add r7, sp, #0 + 8003b0e: 60ba str r2, [r7, #8] + 8003b10: 461a mov r2, r3 + 8003b12: 4603 mov r3, r0 + 8003b14: 81fb strh r3, [r7, #14] + 8003b16: 460b mov r3, r1 + 8003b18: 81bb strh r3, [r7, #12] + 8003b1a: 4613 mov r3, r2 + 8003b1c: 71fb strb r3, [r7, #7] + uint16_t ref_column = 1, i = 0; + 8003b1e: 2301 movs r3, #1 + 8003b20: 83fb strh r3, [r7, #30] + 8003b22: 2300 movs r3, #0 + 8003b24: 83bb strh r3, [r7, #28] + uint32_t size = 0, xsize = 0; + 8003b26: 2300 movs r3, #0 + 8003b28: 61bb str r3, [r7, #24] + 8003b2a: 2300 movs r3, #0 + 8003b2c: 613b str r3, [r7, #16] + uint8_t *ptr = Text; + 8003b2e: 68bb ldr r3, [r7, #8] + 8003b30: 617b str r3, [r7, #20] + + /* Get the text size */ + while (*ptr++) size ++ ; + 8003b32: e002 b.n 8003b3a + 8003b34: 69bb ldr r3, [r7, #24] + 8003b36: 3301 adds r3, #1 + 8003b38: 61bb str r3, [r7, #24] + 8003b3a: 697b ldr r3, [r7, #20] + 8003b3c: 1c5a adds r2, r3, #1 + 8003b3e: 617a str r2, [r7, #20] + 8003b40: 781b ldrb r3, [r3, #0] + 8003b42: 2b00 cmp r3, #0 + 8003b44: d1f6 bne.n 8003b34 + + /* Characters number per line */ + xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width); + 8003b46: f7ff fe8f bl 8003868 + 8003b4a: 4601 mov r1, r0 + 8003b4c: 4b50 ldr r3, [pc, #320] ; (8003c90 ) + 8003b4e: 681a ldr r2, [r3, #0] + 8003b50: 4850 ldr r0, [pc, #320] ; (8003c94 ) + 8003b52: 4613 mov r3, r2 + 8003b54: 005b lsls r3, r3, #1 + 8003b56: 4413 add r3, r2 + 8003b58: 009b lsls r3, r3, #2 + 8003b5a: 4403 add r3, r0 + 8003b5c: 3308 adds r3, #8 + 8003b5e: 681b ldr r3, [r3, #0] + 8003b60: 889b ldrh r3, [r3, #4] + 8003b62: fbb1 f3f3 udiv r3, r1, r3 + 8003b66: 613b str r3, [r7, #16] + + switch (Mode) + 8003b68: 79fb ldrb r3, [r7, #7] + 8003b6a: 2b03 cmp r3, #3 + 8003b6c: d01c beq.n 8003ba8 + 8003b6e: 2b03 cmp r3, #3 + 8003b70: dc33 bgt.n 8003bda + 8003b72: 2b01 cmp r3, #1 + 8003b74: d002 beq.n 8003b7c + 8003b76: 2b02 cmp r3, #2 + 8003b78: d019 beq.n 8003bae + 8003b7a: e02e b.n 8003bda + { + case CENTER_MODE: + { + ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2; + 8003b7c: 693a ldr r2, [r7, #16] + 8003b7e: 69bb ldr r3, [r7, #24] + 8003b80: 1ad1 subs r1, r2, r3 + 8003b82: 4b43 ldr r3, [pc, #268] ; (8003c90 ) + 8003b84: 681a ldr r2, [r3, #0] + 8003b86: 4843 ldr r0, [pc, #268] ; (8003c94 ) + 8003b88: 4613 mov r3, r2 + 8003b8a: 005b lsls r3, r3, #1 + 8003b8c: 4413 add r3, r2 + 8003b8e: 009b lsls r3, r3, #2 + 8003b90: 4403 add r3, r0 + 8003b92: 3308 adds r3, #8 + 8003b94: 681b ldr r3, [r3, #0] + 8003b96: 889b ldrh r3, [r3, #4] + 8003b98: fb01 f303 mul.w r3, r1, r3 + 8003b9c: 085b lsrs r3, r3, #1 + 8003b9e: b29a uxth r2, r3 + 8003ba0: 89fb ldrh r3, [r7, #14] + 8003ba2: 4413 add r3, r2 + 8003ba4: 83fb strh r3, [r7, #30] + break; + 8003ba6: e01b b.n 8003be0 + } + case LEFT_MODE: + { + ref_column = Xpos; + 8003ba8: 89fb ldrh r3, [r7, #14] + 8003baa: 83fb strh r3, [r7, #30] + break; + 8003bac: e018 b.n 8003be0 + } + case RIGHT_MODE: + { + ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width); + 8003bae: 693a ldr r2, [r7, #16] + 8003bb0: 69bb ldr r3, [r7, #24] + 8003bb2: 1ad3 subs r3, r2, r3 + 8003bb4: b299 uxth r1, r3 + 8003bb6: 4b36 ldr r3, [pc, #216] ; (8003c90 ) + 8003bb8: 681a ldr r2, [r3, #0] + 8003bba: 4836 ldr r0, [pc, #216] ; (8003c94 ) + 8003bbc: 4613 mov r3, r2 + 8003bbe: 005b lsls r3, r3, #1 + 8003bc0: 4413 add r3, r2 + 8003bc2: 009b lsls r3, r3, #2 + 8003bc4: 4403 add r3, r0 + 8003bc6: 3308 adds r3, #8 + 8003bc8: 681b ldr r3, [r3, #0] + 8003bca: 889b ldrh r3, [r3, #4] + 8003bcc: fb11 f303 smulbb r3, r1, r3 + 8003bd0: b29a uxth r2, r3 + 8003bd2: 89fb ldrh r3, [r7, #14] + 8003bd4: 1ad3 subs r3, r2, r3 + 8003bd6: 83fb strh r3, [r7, #30] + break; + 8003bd8: e002 b.n 8003be0 + } + default: + { + ref_column = Xpos; + 8003bda: 89fb ldrh r3, [r7, #14] + 8003bdc: 83fb strh r3, [r7, #30] + break; + 8003bde: bf00 nop + } + } + + /* Check that the Start column is located in the screen */ + if ((ref_column < 1) || (ref_column >= 0x8000)) + 8003be0: 8bfb ldrh r3, [r7, #30] + 8003be2: 2b00 cmp r3, #0 + 8003be4: d003 beq.n 8003bee + 8003be6: f9b7 301e ldrsh.w r3, [r7, #30] + 8003bea: 2b00 cmp r3, #0 + 8003bec: da1d bge.n 8003c2a + { + ref_column = 1; + 8003bee: 2301 movs r3, #1 + 8003bf0: 83fb strh r3, [r7, #30] + } + + /* Send the string character by character on LCD */ + while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width)) + 8003bf2: e01a b.n 8003c2a + { + /* Display one character on LCD */ + BSP_LCD_DisplayChar(ref_column, Ypos, *Text); + 8003bf4: 68bb ldr r3, [r7, #8] + 8003bf6: 781a ldrb r2, [r3, #0] + 8003bf8: 89b9 ldrh r1, [r7, #12] + 8003bfa: 8bfb ldrh r3, [r7, #30] + 8003bfc: 4618 mov r0, r3 + 8003bfe: f7ff ff3f bl 8003a80 + /* Decrement the column position by 16 */ + ref_column += DrawProp[ActiveLayer].pFont->Width; + 8003c02: 4b23 ldr r3, [pc, #140] ; (8003c90 ) + 8003c04: 681a ldr r2, [r3, #0] + 8003c06: 4923 ldr r1, [pc, #140] ; (8003c94 ) + 8003c08: 4613 mov r3, r2 + 8003c0a: 005b lsls r3, r3, #1 + 8003c0c: 4413 add r3, r2 + 8003c0e: 009b lsls r3, r3, #2 + 8003c10: 440b add r3, r1 + 8003c12: 3308 adds r3, #8 + 8003c14: 681b ldr r3, [r3, #0] + 8003c16: 889a ldrh r2, [r3, #4] + 8003c18: 8bfb ldrh r3, [r7, #30] + 8003c1a: 4413 add r3, r2 + 8003c1c: 83fb strh r3, [r7, #30] + /* Point on the next character */ + Text++; + 8003c1e: 68bb ldr r3, [r7, #8] + 8003c20: 3301 adds r3, #1 + 8003c22: 60bb str r3, [r7, #8] + i++; + 8003c24: 8bbb ldrh r3, [r7, #28] + 8003c26: 3301 adds r3, #1 + 8003c28: 83bb strh r3, [r7, #28] + while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width)) + 8003c2a: 68bb ldr r3, [r7, #8] + 8003c2c: 781b ldrb r3, [r3, #0] + 8003c2e: 2b00 cmp r3, #0 + 8003c30: bf14 ite ne + 8003c32: 2301 movne r3, #1 + 8003c34: 2300 moveq r3, #0 + 8003c36: b2dc uxtb r4, r3 + 8003c38: f7ff fe16 bl 8003868 + 8003c3c: 8bb9 ldrh r1, [r7, #28] + 8003c3e: 4b14 ldr r3, [pc, #80] ; (8003c90 ) + 8003c40: 681a ldr r2, [r3, #0] + 8003c42: 4d14 ldr r5, [pc, #80] ; (8003c94 ) + 8003c44: 4613 mov r3, r2 + 8003c46: 005b lsls r3, r3, #1 + 8003c48: 4413 add r3, r2 + 8003c4a: 009b lsls r3, r3, #2 + 8003c4c: 442b add r3, r5 + 8003c4e: 3308 adds r3, #8 + 8003c50: 681b ldr r3, [r3, #0] + 8003c52: 889b ldrh r3, [r3, #4] + 8003c54: fb01 f303 mul.w r3, r1, r3 + 8003c58: 1ac3 subs r3, r0, r3 + 8003c5a: b299 uxth r1, r3 + 8003c5c: 4b0c ldr r3, [pc, #48] ; (8003c90 ) + 8003c5e: 681a ldr r2, [r3, #0] + 8003c60: 480c ldr r0, [pc, #48] ; (8003c94 ) + 8003c62: 4613 mov r3, r2 + 8003c64: 005b lsls r3, r3, #1 + 8003c66: 4413 add r3, r2 + 8003c68: 009b lsls r3, r3, #2 + 8003c6a: 4403 add r3, r0 + 8003c6c: 3308 adds r3, #8 + 8003c6e: 681b ldr r3, [r3, #0] + 8003c70: 889b ldrh r3, [r3, #4] + 8003c72: 4299 cmp r1, r3 + 8003c74: bf2c ite cs + 8003c76: 2301 movcs r3, #1 + 8003c78: 2300 movcc r3, #0 + 8003c7a: b2db uxtb r3, r3 + 8003c7c: 4023 ands r3, r4 + 8003c7e: b2db uxtb r3, r3 + 8003c80: 2b00 cmp r3, #0 + 8003c82: d1b7 bne.n 8003bf4 + } +} + 8003c84: bf00 nop + 8003c86: bf00 nop + 8003c88: 3720 adds r7, #32 + 8003c8a: 46bd mov sp, r7 + 8003c8c: bdb0 pop {r4, r5, r7, pc} + 8003c8e: bf00 nop + 8003c90: 20000844 .word 0x20000844 + 8003c94: 20000848 .word 0x20000848 + +08003c98 : + * @param x2: Point 2 X position + * @param y2: Point 2 Y position + * @retval None + */ +void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + 8003c98: b590 push {r4, r7, lr} + 8003c9a: b08b sub sp, #44 ; 0x2c + 8003c9c: af00 add r7, sp, #0 + 8003c9e: 4604 mov r4, r0 + 8003ca0: 4608 mov r0, r1 + 8003ca2: 4611 mov r1, r2 + 8003ca4: 461a mov r2, r3 + 8003ca6: 4623 mov r3, r4 + 8003ca8: 80fb strh r3, [r7, #6] + 8003caa: 4603 mov r3, r0 + 8003cac: 80bb strh r3, [r7, #4] + 8003cae: 460b mov r3, r1 + 8003cb0: 807b strh r3, [r7, #2] + 8003cb2: 4613 mov r3, r2 + 8003cb4: 803b strh r3, [r7, #0] + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + 8003cb6: 2300 movs r3, #0 + 8003cb8: 823b strh r3, [r7, #16] + 8003cba: 2300 movs r3, #0 + 8003cbc: 81fb strh r3, [r7, #14] + 8003cbe: 2300 movs r3, #0 + 8003cc0: 84fb strh r3, [r7, #38] ; 0x26 + 8003cc2: 2300 movs r3, #0 + 8003cc4: 84bb strh r3, [r7, #36] ; 0x24 + 8003cc6: 2300 movs r3, #0 + 8003cc8: 847b strh r3, [r7, #34] ; 0x22 + 8003cca: 2300 movs r3, #0 + 8003ccc: 843b strh r3, [r7, #32] + yinc1 = 0, yinc2 = 0, den = 0, num = 0, num_add = 0, num_pixels = 0, + 8003cce: 2300 movs r3, #0 + 8003cd0: 83fb strh r3, [r7, #30] + 8003cd2: 2300 movs r3, #0 + 8003cd4: 83bb strh r3, [r7, #28] + 8003cd6: 2300 movs r3, #0 + 8003cd8: 837b strh r3, [r7, #26] + 8003cda: 2300 movs r3, #0 + 8003cdc: 833b strh r3, [r7, #24] + 8003cde: 2300 movs r3, #0 + 8003ce0: 82fb strh r3, [r7, #22] + 8003ce2: 2300 movs r3, #0 + 8003ce4: 82bb strh r3, [r7, #20] + curpixel = 0; + 8003ce6: 2300 movs r3, #0 + 8003ce8: 827b strh r3, [r7, #18] + + deltax = ABS(x2 - x1); /* The difference between the x's */ + 8003cea: 887a ldrh r2, [r7, #2] + 8003cec: 88fb ldrh r3, [r7, #6] + 8003cee: 1ad3 subs r3, r2, r3 + 8003cf0: 2b00 cmp r3, #0 + 8003cf2: bfb8 it lt + 8003cf4: 425b neglt r3, r3 + 8003cf6: 823b strh r3, [r7, #16] + deltay = ABS(y2 - y1); /* The difference between the y's */ + 8003cf8: 883a ldrh r2, [r7, #0] + 8003cfa: 88bb ldrh r3, [r7, #4] + 8003cfc: 1ad3 subs r3, r2, r3 + 8003cfe: 2b00 cmp r3, #0 + 8003d00: bfb8 it lt + 8003d02: 425b neglt r3, r3 + 8003d04: 81fb strh r3, [r7, #14] + x = x1; /* Start x off at the first pixel */ + 8003d06: 88fb ldrh r3, [r7, #6] + 8003d08: 84fb strh r3, [r7, #38] ; 0x26 + y = y1; /* Start y off at the first pixel */ + 8003d0a: 88bb ldrh r3, [r7, #4] + 8003d0c: 84bb strh r3, [r7, #36] ; 0x24 + + if (x2 >= x1) /* The x-values are increasing */ + 8003d0e: 887a ldrh r2, [r7, #2] + 8003d10: 88fb ldrh r3, [r7, #6] + 8003d12: 429a cmp r2, r3 + 8003d14: d304 bcc.n 8003d20 + { + xinc1 = 1; + 8003d16: 2301 movs r3, #1 + 8003d18: 847b strh r3, [r7, #34] ; 0x22 + xinc2 = 1; + 8003d1a: 2301 movs r3, #1 + 8003d1c: 843b strh r3, [r7, #32] + 8003d1e: e005 b.n 8003d2c + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + 8003d20: f64f 73ff movw r3, #65535 ; 0xffff + 8003d24: 847b strh r3, [r7, #34] ; 0x22 + xinc2 = -1; + 8003d26: f64f 73ff movw r3, #65535 ; 0xffff + 8003d2a: 843b strh r3, [r7, #32] + } + + if (y2 >= y1) /* The y-values are increasing */ + 8003d2c: 883a ldrh r2, [r7, #0] + 8003d2e: 88bb ldrh r3, [r7, #4] + 8003d30: 429a cmp r2, r3 + 8003d32: d304 bcc.n 8003d3e + { + yinc1 = 1; + 8003d34: 2301 movs r3, #1 + 8003d36: 83fb strh r3, [r7, #30] + yinc2 = 1; + 8003d38: 2301 movs r3, #1 + 8003d3a: 83bb strh r3, [r7, #28] + 8003d3c: e005 b.n 8003d4a + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + 8003d3e: f64f 73ff movw r3, #65535 ; 0xffff + 8003d42: 83fb strh r3, [r7, #30] + yinc2 = -1; + 8003d44: f64f 73ff movw r3, #65535 ; 0xffff + 8003d48: 83bb strh r3, [r7, #28] + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + 8003d4a: f9b7 2010 ldrsh.w r2, [r7, #16] + 8003d4e: f9b7 300e ldrsh.w r3, [r7, #14] + 8003d52: 429a cmp r2, r3 + 8003d54: db11 blt.n 8003d7a + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + 8003d56: 2300 movs r3, #0 + 8003d58: 847b strh r3, [r7, #34] ; 0x22 + yinc2 = 0; /* Don't change the y for every iteration */ + 8003d5a: 2300 movs r3, #0 + 8003d5c: 83bb strh r3, [r7, #28] + den = deltax; + 8003d5e: 8a3b ldrh r3, [r7, #16] + 8003d60: 837b strh r3, [r7, #26] + num = deltax / 2; + 8003d62: f9b7 3010 ldrsh.w r3, [r7, #16] + 8003d66: 2b00 cmp r3, #0 + 8003d68: da00 bge.n 8003d6c + 8003d6a: 3301 adds r3, #1 + 8003d6c: 105b asrs r3, r3, #1 + 8003d6e: 833b strh r3, [r7, #24] + num_add = deltay; + 8003d70: 89fb ldrh r3, [r7, #14] + 8003d72: 82fb strh r3, [r7, #22] + num_pixels = deltax; /* There are more x-values than y-values */ + 8003d74: 8a3b ldrh r3, [r7, #16] + 8003d76: 82bb strh r3, [r7, #20] + 8003d78: e010 b.n 8003d9c + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + 8003d7a: 2300 movs r3, #0 + 8003d7c: 843b strh r3, [r7, #32] + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + 8003d7e: 2300 movs r3, #0 + 8003d80: 83fb strh r3, [r7, #30] + den = deltay; + 8003d82: 89fb ldrh r3, [r7, #14] + 8003d84: 837b strh r3, [r7, #26] + num = deltay / 2; + 8003d86: f9b7 300e ldrsh.w r3, [r7, #14] + 8003d8a: 2b00 cmp r3, #0 + 8003d8c: da00 bge.n 8003d90 + 8003d8e: 3301 adds r3, #1 + 8003d90: 105b asrs r3, r3, #1 + 8003d92: 833b strh r3, [r7, #24] + num_add = deltax; + 8003d94: 8a3b ldrh r3, [r7, #16] + 8003d96: 82fb strh r3, [r7, #22] + num_pixels = deltay; /* There are more y-values than x-values */ + 8003d98: 89fb ldrh r3, [r7, #14] + 8003d9a: 82bb strh r3, [r7, #20] + } + + for (curpixel = 0; curpixel <= num_pixels; curpixel++) + 8003d9c: 2300 movs r3, #0 + 8003d9e: 827b strh r3, [r7, #18] + 8003da0: e037 b.n 8003e12 + { + BSP_LCD_DrawPixel(x, y, DrawProp[ActiveLayer].TextColor); /* Draw the current pixel */ + 8003da2: 8cf8 ldrh r0, [r7, #38] ; 0x26 + 8003da4: 8cb9 ldrh r1, [r7, #36] ; 0x24 + 8003da6: 4b20 ldr r3, [pc, #128] ; (8003e28 ) + 8003da8: 681a ldr r2, [r3, #0] + 8003daa: 4c20 ldr r4, [pc, #128] ; (8003e2c ) + 8003dac: 4613 mov r3, r2 + 8003dae: 005b lsls r3, r3, #1 + 8003db0: 4413 add r3, r2 + 8003db2: 009b lsls r3, r3, #2 + 8003db4: 4423 add r3, r4 + 8003db6: 681b ldr r3, [r3, #0] + 8003db8: 461a mov r2, r3 + 8003dba: f000 f923 bl 8004004 + num += num_add; /* Increase the numerator by the top of the fraction */ + 8003dbe: 8b3a ldrh r2, [r7, #24] + 8003dc0: 8afb ldrh r3, [r7, #22] + 8003dc2: 4413 add r3, r2 + 8003dc4: b29b uxth r3, r3 + 8003dc6: 833b strh r3, [r7, #24] + if (num >= den) /* Check if numerator >= denominator */ + 8003dc8: f9b7 2018 ldrsh.w r2, [r7, #24] + 8003dcc: f9b7 301a ldrsh.w r3, [r7, #26] + 8003dd0: 429a cmp r2, r3 + 8003dd2: db0e blt.n 8003df2 + { + num -= den; /* Calculate the new numerator value */ + 8003dd4: 8b3a ldrh r2, [r7, #24] + 8003dd6: 8b7b ldrh r3, [r7, #26] + 8003dd8: 1ad3 subs r3, r2, r3 + 8003dda: b29b uxth r3, r3 + 8003ddc: 833b strh r3, [r7, #24] + x += xinc1; /* Change the x as appropriate */ + 8003dde: 8cfa ldrh r2, [r7, #38] ; 0x26 + 8003de0: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8003de2: 4413 add r3, r2 + 8003de4: b29b uxth r3, r3 + 8003de6: 84fb strh r3, [r7, #38] ; 0x26 + y += yinc1; /* Change the y as appropriate */ + 8003de8: 8cba ldrh r2, [r7, #36] ; 0x24 + 8003dea: 8bfb ldrh r3, [r7, #30] + 8003dec: 4413 add r3, r2 + 8003dee: b29b uxth r3, r3 + 8003df0: 84bb strh r3, [r7, #36] ; 0x24 + } + x += xinc2; /* Change the x as appropriate */ + 8003df2: 8cfa ldrh r2, [r7, #38] ; 0x26 + 8003df4: 8c3b ldrh r3, [r7, #32] + 8003df6: 4413 add r3, r2 + 8003df8: b29b uxth r3, r3 + 8003dfa: 84fb strh r3, [r7, #38] ; 0x26 + y += yinc2; /* Change the y as appropriate */ + 8003dfc: 8cba ldrh r2, [r7, #36] ; 0x24 + 8003dfe: 8bbb ldrh r3, [r7, #28] + 8003e00: 4413 add r3, r2 + 8003e02: b29b uxth r3, r3 + 8003e04: 84bb strh r3, [r7, #36] ; 0x24 + for (curpixel = 0; curpixel <= num_pixels; curpixel++) + 8003e06: f9b7 3012 ldrsh.w r3, [r7, #18] + 8003e0a: b29b uxth r3, r3 + 8003e0c: 3301 adds r3, #1 + 8003e0e: b29b uxth r3, r3 + 8003e10: 827b strh r3, [r7, #18] + 8003e12: f9b7 2012 ldrsh.w r2, [r7, #18] + 8003e16: f9b7 3014 ldrsh.w r3, [r7, #20] + 8003e1a: 429a cmp r2, r3 + 8003e1c: ddc1 ble.n 8003da2 + } +} + 8003e1e: bf00 nop + 8003e20: bf00 nop + 8003e22: 372c adds r7, #44 ; 0x2c + 8003e24: 46bd mov sp, r7 + 8003e26: bd90 pop {r4, r7, pc} + 8003e28: 20000844 .word 0x20000844 + 8003e2c: 20000848 .word 0x20000848 + +08003e30 : + * @param Ypos: Y position + * @param Radius: Circle radius + * @retval None + */ +void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + 8003e30: b590 push {r4, r7, lr} + 8003e32: b087 sub sp, #28 + 8003e34: af00 add r7, sp, #0 + 8003e36: 4603 mov r3, r0 + 8003e38: 80fb strh r3, [r7, #6] + 8003e3a: 460b mov r3, r1 + 8003e3c: 80bb strh r3, [r7, #4] + 8003e3e: 4613 mov r3, r2 + 8003e40: 807b strh r3, [r7, #2] + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + decision = 3 - (Radius << 1); + 8003e42: 887b ldrh r3, [r7, #2] + 8003e44: 005b lsls r3, r3, #1 + 8003e46: f1c3 0303 rsb r3, r3, #3 + 8003e4a: 617b str r3, [r7, #20] + current_x = 0; + 8003e4c: 2300 movs r3, #0 + 8003e4e: 613b str r3, [r7, #16] + current_y = Radius; + 8003e50: 887b ldrh r3, [r7, #2] + 8003e52: 60fb str r3, [r7, #12] + + while (current_x <= current_y) + 8003e54: e0c7 b.n 8003fe6 + { + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + 8003e56: 693b ldr r3, [r7, #16] + 8003e58: b29a uxth r2, r3 + 8003e5a: 88fb ldrh r3, [r7, #6] + 8003e5c: 4413 add r3, r2 + 8003e5e: b298 uxth r0, r3 + 8003e60: 68fb ldr r3, [r7, #12] + 8003e62: b29b uxth r3, r3 + 8003e64: 88ba ldrh r2, [r7, #4] + 8003e66: 1ad3 subs r3, r2, r3 + 8003e68: b299 uxth r1, r3 + 8003e6a: 4b64 ldr r3, [pc, #400] ; (8003ffc ) + 8003e6c: 681a ldr r2, [r3, #0] + 8003e6e: 4c64 ldr r4, [pc, #400] ; (8004000 ) + 8003e70: 4613 mov r3, r2 + 8003e72: 005b lsls r3, r3, #1 + 8003e74: 4413 add r3, r2 + 8003e76: 009b lsls r3, r3, #2 + 8003e78: 4423 add r3, r4 + 8003e7a: 681b ldr r3, [r3, #0] + 8003e7c: 461a mov r2, r3 + 8003e7e: f000 f8c1 bl 8004004 + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + 8003e82: 693b ldr r3, [r7, #16] + 8003e84: b29b uxth r3, r3 + 8003e86: 88fa ldrh r2, [r7, #6] + 8003e88: 1ad3 subs r3, r2, r3 + 8003e8a: b298 uxth r0, r3 + 8003e8c: 68fb ldr r3, [r7, #12] + 8003e8e: b29b uxth r3, r3 + 8003e90: 88ba ldrh r2, [r7, #4] + 8003e92: 1ad3 subs r3, r2, r3 + 8003e94: b299 uxth r1, r3 + 8003e96: 4b59 ldr r3, [pc, #356] ; (8003ffc ) + 8003e98: 681a ldr r2, [r3, #0] + 8003e9a: 4c59 ldr r4, [pc, #356] ; (8004000 ) + 8003e9c: 4613 mov r3, r2 + 8003e9e: 005b lsls r3, r3, #1 + 8003ea0: 4413 add r3, r2 + 8003ea2: 009b lsls r3, r3, #2 + 8003ea4: 4423 add r3, r4 + 8003ea6: 681b ldr r3, [r3, #0] + 8003ea8: 461a mov r2, r3 + 8003eaa: f000 f8ab bl 8004004 + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + 8003eae: 68fb ldr r3, [r7, #12] + 8003eb0: b29a uxth r2, r3 + 8003eb2: 88fb ldrh r3, [r7, #6] + 8003eb4: 4413 add r3, r2 + 8003eb6: b298 uxth r0, r3 + 8003eb8: 693b ldr r3, [r7, #16] + 8003eba: b29b uxth r3, r3 + 8003ebc: 88ba ldrh r2, [r7, #4] + 8003ebe: 1ad3 subs r3, r2, r3 + 8003ec0: b299 uxth r1, r3 + 8003ec2: 4b4e ldr r3, [pc, #312] ; (8003ffc ) + 8003ec4: 681a ldr r2, [r3, #0] + 8003ec6: 4c4e ldr r4, [pc, #312] ; (8004000 ) + 8003ec8: 4613 mov r3, r2 + 8003eca: 005b lsls r3, r3, #1 + 8003ecc: 4413 add r3, r2 + 8003ece: 009b lsls r3, r3, #2 + 8003ed0: 4423 add r3, r4 + 8003ed2: 681b ldr r3, [r3, #0] + 8003ed4: 461a mov r2, r3 + 8003ed6: f000 f895 bl 8004004 + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + 8003eda: 68fb ldr r3, [r7, #12] + 8003edc: b29b uxth r3, r3 + 8003ede: 88fa ldrh r2, [r7, #6] + 8003ee0: 1ad3 subs r3, r2, r3 + 8003ee2: b298 uxth r0, r3 + 8003ee4: 693b ldr r3, [r7, #16] + 8003ee6: b29b uxth r3, r3 + 8003ee8: 88ba ldrh r2, [r7, #4] + 8003eea: 1ad3 subs r3, r2, r3 + 8003eec: b299 uxth r1, r3 + 8003eee: 4b43 ldr r3, [pc, #268] ; (8003ffc ) + 8003ef0: 681a ldr r2, [r3, #0] + 8003ef2: 4c43 ldr r4, [pc, #268] ; (8004000 ) + 8003ef4: 4613 mov r3, r2 + 8003ef6: 005b lsls r3, r3, #1 + 8003ef8: 4413 add r3, r2 + 8003efa: 009b lsls r3, r3, #2 + 8003efc: 4423 add r3, r4 + 8003efe: 681b ldr r3, [r3, #0] + 8003f00: 461a mov r2, r3 + 8003f02: f000 f87f bl 8004004 + + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + 8003f06: 693b ldr r3, [r7, #16] + 8003f08: b29a uxth r2, r3 + 8003f0a: 88fb ldrh r3, [r7, #6] + 8003f0c: 4413 add r3, r2 + 8003f0e: b298 uxth r0, r3 + 8003f10: 68fb ldr r3, [r7, #12] + 8003f12: b29a uxth r2, r3 + 8003f14: 88bb ldrh r3, [r7, #4] + 8003f16: 4413 add r3, r2 + 8003f18: b299 uxth r1, r3 + 8003f1a: 4b38 ldr r3, [pc, #224] ; (8003ffc ) + 8003f1c: 681a ldr r2, [r3, #0] + 8003f1e: 4c38 ldr r4, [pc, #224] ; (8004000 ) + 8003f20: 4613 mov r3, r2 + 8003f22: 005b lsls r3, r3, #1 + 8003f24: 4413 add r3, r2 + 8003f26: 009b lsls r3, r3, #2 + 8003f28: 4423 add r3, r4 + 8003f2a: 681b ldr r3, [r3, #0] + 8003f2c: 461a mov r2, r3 + 8003f2e: f000 f869 bl 8004004 + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + 8003f32: 693b ldr r3, [r7, #16] + 8003f34: b29b uxth r3, r3 + 8003f36: 88fa ldrh r2, [r7, #6] + 8003f38: 1ad3 subs r3, r2, r3 + 8003f3a: b298 uxth r0, r3 + 8003f3c: 68fb ldr r3, [r7, #12] + 8003f3e: b29a uxth r2, r3 + 8003f40: 88bb ldrh r3, [r7, #4] + 8003f42: 4413 add r3, r2 + 8003f44: b299 uxth r1, r3 + 8003f46: 4b2d ldr r3, [pc, #180] ; (8003ffc ) + 8003f48: 681a ldr r2, [r3, #0] + 8003f4a: 4c2d ldr r4, [pc, #180] ; (8004000 ) + 8003f4c: 4613 mov r3, r2 + 8003f4e: 005b lsls r3, r3, #1 + 8003f50: 4413 add r3, r2 + 8003f52: 009b lsls r3, r3, #2 + 8003f54: 4423 add r3, r4 + 8003f56: 681b ldr r3, [r3, #0] + 8003f58: 461a mov r2, r3 + 8003f5a: f000 f853 bl 8004004 + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + 8003f5e: 68fb ldr r3, [r7, #12] + 8003f60: b29a uxth r2, r3 + 8003f62: 88fb ldrh r3, [r7, #6] + 8003f64: 4413 add r3, r2 + 8003f66: b298 uxth r0, r3 + 8003f68: 693b ldr r3, [r7, #16] + 8003f6a: b29a uxth r2, r3 + 8003f6c: 88bb ldrh r3, [r7, #4] + 8003f6e: 4413 add r3, r2 + 8003f70: b299 uxth r1, r3 + 8003f72: 4b22 ldr r3, [pc, #136] ; (8003ffc ) + 8003f74: 681a ldr r2, [r3, #0] + 8003f76: 4c22 ldr r4, [pc, #136] ; (8004000 ) + 8003f78: 4613 mov r3, r2 + 8003f7a: 005b lsls r3, r3, #1 + 8003f7c: 4413 add r3, r2 + 8003f7e: 009b lsls r3, r3, #2 + 8003f80: 4423 add r3, r4 + 8003f82: 681b ldr r3, [r3, #0] + 8003f84: 461a mov r2, r3 + 8003f86: f000 f83d bl 8004004 + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + 8003f8a: 68fb ldr r3, [r7, #12] + 8003f8c: b29b uxth r3, r3 + 8003f8e: 88fa ldrh r2, [r7, #6] + 8003f90: 1ad3 subs r3, r2, r3 + 8003f92: b298 uxth r0, r3 + 8003f94: 693b ldr r3, [r7, #16] + 8003f96: b29a uxth r2, r3 + 8003f98: 88bb ldrh r3, [r7, #4] + 8003f9a: 4413 add r3, r2 + 8003f9c: b299 uxth r1, r3 + 8003f9e: 4b17 ldr r3, [pc, #92] ; (8003ffc ) + 8003fa0: 681a ldr r2, [r3, #0] + 8003fa2: 4c17 ldr r4, [pc, #92] ; (8004000 ) + 8003fa4: 4613 mov r3, r2 + 8003fa6: 005b lsls r3, r3, #1 + 8003fa8: 4413 add r3, r2 + 8003faa: 009b lsls r3, r3, #2 + 8003fac: 4423 add r3, r4 + 8003fae: 681b ldr r3, [r3, #0] + 8003fb0: 461a mov r2, r3 + 8003fb2: f000 f827 bl 8004004 + + if (decision < 0) + 8003fb6: 697b ldr r3, [r7, #20] + 8003fb8: 2b00 cmp r3, #0 + 8003fba: da06 bge.n 8003fca + { + decision += (current_x << 2) + 6; + 8003fbc: 693b ldr r3, [r7, #16] + 8003fbe: 009a lsls r2, r3, #2 + 8003fc0: 697b ldr r3, [r7, #20] + 8003fc2: 4413 add r3, r2 + 8003fc4: 3306 adds r3, #6 + 8003fc6: 617b str r3, [r7, #20] + 8003fc8: e00a b.n 8003fe0 + } + else + { + decision += ((current_x - current_y) << 2) + 10; + 8003fca: 693a ldr r2, [r7, #16] + 8003fcc: 68fb ldr r3, [r7, #12] + 8003fce: 1ad3 subs r3, r2, r3 + 8003fd0: 009a lsls r2, r3, #2 + 8003fd2: 697b ldr r3, [r7, #20] + 8003fd4: 4413 add r3, r2 + 8003fd6: 330a adds r3, #10 + 8003fd8: 617b str r3, [r7, #20] + current_y--; + 8003fda: 68fb ldr r3, [r7, #12] + 8003fdc: 3b01 subs r3, #1 + 8003fde: 60fb str r3, [r7, #12] + } + current_x++; + 8003fe0: 693b ldr r3, [r7, #16] + 8003fe2: 3301 adds r3, #1 + 8003fe4: 613b str r3, [r7, #16] + while (current_x <= current_y) + 8003fe6: 693a ldr r2, [r7, #16] + 8003fe8: 68fb ldr r3, [r7, #12] + 8003fea: 429a cmp r2, r3 + 8003fec: f67f af33 bls.w 8003e56 + } +} + 8003ff0: bf00 nop + 8003ff2: bf00 nop + 8003ff4: 371c adds r7, #28 + 8003ff6: 46bd mov sp, r7 + 8003ff8: bd90 pop {r4, r7, pc} + 8003ffa: bf00 nop + 8003ffc: 20000844 .word 0x20000844 + 8004000: 20000848 .word 0x20000848 + +08004004 : + * @param Ypos: Y position + * @param RGB_Code: Pixel color in ARGB mode (8-8-8-8) + * @retval None + */ +void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code) +{ + 8004004: b5b0 push {r4, r5, r7, lr} + 8004006: b082 sub sp, #8 + 8004008: af00 add r7, sp, #0 + 800400a: 4603 mov r3, r0 + 800400c: 603a str r2, [r7, #0] + 800400e: 80fb strh r3, [r7, #6] + 8004010: 460b mov r3, r1 + 8004012: 80bb strh r3, [r7, #4] + /* Write data value to all SDRAM memory */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + 8004014: 4b1d ldr r3, [pc, #116] ; (800408c ) + 8004016: 681b ldr r3, [r3, #0] + 8004018: 4a1d ldr r2, [pc, #116] ; (8004090 ) + 800401a: 2134 movs r1, #52 ; 0x34 + 800401c: fb01 f303 mul.w r3, r1, r3 + 8004020: 4413 add r3, r2 + 8004022: 3348 adds r3, #72 ; 0x48 + 8004024: 681b ldr r3, [r3, #0] + 8004026: 2b02 cmp r3, #2 + 8004028: d116 bne.n 8004058 + { /* RGB565 format */ + *(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code; + 800402a: 4b18 ldr r3, [pc, #96] ; (800408c ) + 800402c: 681b ldr r3, [r3, #0] + 800402e: 4a18 ldr r2, [pc, #96] ; (8004090 ) + 8004030: 2134 movs r1, #52 ; 0x34 + 8004032: fb01 f303 mul.w r3, r1, r3 + 8004036: 4413 add r3, r2 + 8004038: 335c adds r3, #92 ; 0x5c + 800403a: 681c ldr r4, [r3, #0] + 800403c: 88bd ldrh r5, [r7, #4] + 800403e: f7ff fc13 bl 8003868 + 8004042: 4603 mov r3, r0 + 8004044: fb03 f205 mul.w r2, r3, r5 + 8004048: 88fb ldrh r3, [r7, #6] + 800404a: 4413 add r3, r2 + 800404c: 005b lsls r3, r3, #1 + 800404e: 4423 add r3, r4 + 8004050: 683a ldr r2, [r7, #0] + 8004052: b292 uxth r2, r2 + 8004054: 801a strh r2, [r3, #0] + } + else + { /* ARGB8888 format */ + *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code; + } +} + 8004056: e015 b.n 8004084 + *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code; + 8004058: 4b0c ldr r3, [pc, #48] ; (800408c ) + 800405a: 681b ldr r3, [r3, #0] + 800405c: 4a0c ldr r2, [pc, #48] ; (8004090 ) + 800405e: 2134 movs r1, #52 ; 0x34 + 8004060: fb01 f303 mul.w r3, r1, r3 + 8004064: 4413 add r3, r2 + 8004066: 335c adds r3, #92 ; 0x5c + 8004068: 681c ldr r4, [r3, #0] + 800406a: 88bd ldrh r5, [r7, #4] + 800406c: f7ff fbfc bl 8003868 + 8004070: 4603 mov r3, r0 + 8004072: fb03 f205 mul.w r2, r3, r5 + 8004076: 88fb ldrh r3, [r7, #6] + 8004078: 4413 add r3, r2 + 800407a: 009b lsls r3, r3, #2 + 800407c: 4423 add r3, r4 + 800407e: 461a mov r2, r3 + 8004080: 683b ldr r3, [r7, #0] + 8004082: 6013 str r3, [r2, #0] +} + 8004084: bf00 nop + 8004086: 3708 adds r7, #8 + 8004088: 46bd mov sp, r7 + 800408a: bdb0 pop {r4, r5, r7, pc} + 800408c: 20000844 .word 0x20000844 + 8004090: 2000075c .word 0x2000075c + +08004094 : +/** + * @brief Enables the display. + * @retval None + */ +void BSP_LCD_DisplayOn(void) +{ + 8004094: b580 push {r7, lr} + 8004096: af00 add r7, sp, #0 + /* Display On */ + __HAL_LTDC_ENABLE(&hLtdcHandler); + 8004098: 4b0a ldr r3, [pc, #40] ; (80040c4 ) + 800409a: 681b ldr r3, [r3, #0] + 800409c: 699a ldr r2, [r3, #24] + 800409e: 4b09 ldr r3, [pc, #36] ; (80040c4 ) + 80040a0: 681b ldr r3, [r3, #0] + 80040a2: f042 0201 orr.w r2, r2, #1 + 80040a6: 619a str r2, [r3, #24] + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */ + 80040a8: 2201 movs r2, #1 + 80040aa: f44f 5180 mov.w r1, #4096 ; 0x1000 + 80040ae: 4806 ldr r0, [pc, #24] ; (80040c8 ) + 80040b0: f002 fd36 bl 8006b20 + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */ + 80040b4: 2201 movs r2, #1 + 80040b6: 2108 movs r1, #8 + 80040b8: 4804 ldr r0, [pc, #16] ; (80040cc ) + 80040ba: f002 fd31 bl 8006b20 +} + 80040be: bf00 nop + 80040c0: bd80 pop {r7, pc} + 80040c2: bf00 nop + 80040c4: 2000075c .word 0x2000075c + 80040c8: 40022000 .word 0x40022000 + 80040cc: 40022800 .word 0x40022800 + +080040d0 : + * @param hltdc: LTDC handle + * @param Params + * @retval None + */ +__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params) +{ + 80040d0: b580 push {r7, lr} + 80040d2: b090 sub sp, #64 ; 0x40 + 80040d4: af00 add r7, sp, #0 + 80040d6: 6078 str r0, [r7, #4] + 80040d8: 6039 str r1, [r7, #0] + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the LTDC and DMA2D clocks */ + __HAL_RCC_LTDC_CLK_ENABLE(); + 80040da: 4b64 ldr r3, [pc, #400] ; (800426c ) + 80040dc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80040de: 4a63 ldr r2, [pc, #396] ; (800426c ) + 80040e0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80040e4: 6453 str r3, [r2, #68] ; 0x44 + 80040e6: 4b61 ldr r3, [pc, #388] ; (800426c ) + 80040e8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80040ea: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 80040ee: 62bb str r3, [r7, #40] ; 0x28 + 80040f0: 6abb ldr r3, [r7, #40] ; 0x28 + __HAL_RCC_DMA2D_CLK_ENABLE(); + 80040f2: 4b5e ldr r3, [pc, #376] ; (800426c ) + 80040f4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80040f6: 4a5d ldr r2, [pc, #372] ; (800426c ) + 80040f8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 80040fc: 6313 str r3, [r2, #48] ; 0x30 + 80040fe: 4b5b ldr r3, [pc, #364] ; (800426c ) + 8004100: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004102: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8004106: 627b str r3, [r7, #36] ; 0x24 + 8004108: 6a7b ldr r3, [r7, #36] ; 0x24 + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 800410a: 4b58 ldr r3, [pc, #352] ; (800426c ) + 800410c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800410e: 4a57 ldr r2, [pc, #348] ; (800426c ) + 8004110: f043 0310 orr.w r3, r3, #16 + 8004114: 6313 str r3, [r2, #48] ; 0x30 + 8004116: 4b55 ldr r3, [pc, #340] ; (800426c ) + 8004118: 6b1b ldr r3, [r3, #48] ; 0x30 + 800411a: f003 0310 and.w r3, r3, #16 + 800411e: 623b str r3, [r7, #32] + 8004120: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8004122: 4b52 ldr r3, [pc, #328] ; (800426c ) + 8004124: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004126: 4a51 ldr r2, [pc, #324] ; (800426c ) + 8004128: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800412c: 6313 str r3, [r2, #48] ; 0x30 + 800412e: 4b4f ldr r3, [pc, #316] ; (800426c ) + 8004130: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004132: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004136: 61fb str r3, [r7, #28] + 8004138: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 800413a: 4b4c ldr r3, [pc, #304] ; (800426c ) + 800413c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800413e: 4a4b ldr r2, [pc, #300] ; (800426c ) + 8004140: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8004144: 6313 str r3, [r2, #48] ; 0x30 + 8004146: 4b49 ldr r3, [pc, #292] ; (800426c ) + 8004148: 6b1b ldr r3, [r3, #48] ; 0x30 + 800414a: f403 7380 and.w r3, r3, #256 ; 0x100 + 800414e: 61bb str r3, [r7, #24] + 8004150: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8004152: 4b46 ldr r3, [pc, #280] ; (800426c ) + 8004154: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004156: 4a45 ldr r2, [pc, #276] ; (800426c ) + 8004158: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800415c: 6313 str r3, [r2, #48] ; 0x30 + 800415e: 4b43 ldr r3, [pc, #268] ; (800426c ) + 8004160: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004162: f403 7300 and.w r3, r3, #512 ; 0x200 + 8004166: 617b str r3, [r7, #20] + 8004168: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 800416a: 4b40 ldr r3, [pc, #256] ; (800426c ) + 800416c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800416e: 4a3f ldr r2, [pc, #252] ; (800426c ) + 8004170: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8004174: 6313 str r3, [r2, #48] ; 0x30 + 8004176: 4b3d ldr r3, [pc, #244] ; (800426c ) + 8004178: 6b1b ldr r3, [r3, #48] ; 0x30 + 800417a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800417e: 613b str r3, [r7, #16] + 8004180: 693b ldr r3, [r7, #16] + LCD_DISP_GPIO_CLK_ENABLE(); + 8004182: 4b3a ldr r3, [pc, #232] ; (800426c ) + 8004184: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004186: 4a39 ldr r2, [pc, #228] ; (800426c ) + 8004188: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800418c: 6313 str r3, [r2, #48] ; 0x30 + 800418e: 4b37 ldr r3, [pc, #220] ; (800426c ) + 8004190: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004192: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004196: 60fb str r3, [r7, #12] + 8004198: 68fb ldr r3, [r7, #12] + LCD_BL_CTRL_GPIO_CLK_ENABLE(); + 800419a: 4b34 ldr r3, [pc, #208] ; (800426c ) + 800419c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800419e: 4a33 ldr r2, [pc, #204] ; (800426c ) + 80041a0: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 80041a4: 6313 str r3, [r2, #48] ; 0x30 + 80041a6: 4b31 ldr r3, [pc, #196] ; (800426c ) + 80041a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80041aa: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80041ae: 60bb str r3, [r7, #8] + 80041b0: 68bb ldr r3, [r7, #8] + + /*** LTDC Pins configuration ***/ + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_4; + 80041b2: 2310 movs r3, #16 + 80041b4: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 80041b6: 2302 movs r3, #2 + 80041b8: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Pull = GPIO_NOPULL; + 80041ba: 2300 movs r3, #0 + 80041bc: 637b str r3, [r7, #52] ; 0x34 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 80041be: 2302 movs r3, #2 + 80041c0: 63bb str r3, [r7, #56] ; 0x38 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 80041c2: 230e movs r3, #14 + 80041c4: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + 80041c6: f107 032c add.w r3, r7, #44 ; 0x2c + 80041ca: 4619 mov r1, r3 + 80041cc: 4828 ldr r0, [pc, #160] ; (8004270 ) + 80041ce: f002 fafb bl 80067c8 + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_12; + 80041d2: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80041d6: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 80041d8: 2302 movs r3, #2 + 80041da: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF9_LTDC; + 80041dc: 2309 movs r3, #9 + 80041de: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + 80041e0: f107 032c add.w r3, r7, #44 ; 0x2c + 80041e4: 4619 mov r1, r3 + 80041e6: 4823 ldr r0, [pc, #140] ; (8004274 ) + 80041e8: f002 faee bl 80067c8 + + /* GPIOI LTDC alternate configuration */ + gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \ + 80041ec: f44f 4346 mov.w r3, #50688 ; 0xc600 + 80041f0: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 80041f2: 2302 movs r3, #2 + 80041f4: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 80041f6: 230e movs r3, #14 + 80041f8: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + 80041fa: f107 032c add.w r3, r7, #44 ; 0x2c + 80041fe: 4619 mov r1, r3 + 8004200: 481d ldr r0, [pc, #116] ; (8004278 ) + 8004202: f002 fae1 bl 80067c8 + + /* GPIOJ configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \ + 8004206: f64e 73ff movw r3, #61439 ; 0xefff + 800420a: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 800420c: 2302 movs r3, #2 + 800420e: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8004210: 230e movs r3, #14 + 8004212: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOJ, &gpio_init_structure); + 8004214: f107 032c add.w r3, r7, #44 ; 0x2c + 8004218: 4619 mov r1, r3 + 800421a: 4818 ldr r0, [pc, #96] ; (800427c ) + 800421c: f002 fad4 bl 80067c8 + + /* GPIOK configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \ + 8004220: 23f7 movs r3, #247 ; 0xf7 + 8004222: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8004224: 2302 movs r3, #2 + 8004226: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8004228: 230e movs r3, #14 + 800422a: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOK, &gpio_init_structure); + 800422c: f107 032c add.w r3, r7, #44 ; 0x2c + 8004230: 4619 mov r1, r3 + 8004232: 4813 ldr r0, [pc, #76] ; (8004280 ) + 8004234: f002 fac8 bl 80067c8 + + /* LCD_DISP GPIO configuration */ + gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */ + 8004238: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800423c: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 800423e: 2301 movs r3, #1 + 8004240: 633b str r3, [r7, #48] ; 0x30 + HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure); + 8004242: f107 032c add.w r3, r7, #44 ; 0x2c + 8004246: 4619 mov r1, r3 + 8004248: 480b ldr r0, [pc, #44] ; (8004278 ) + 800424a: f002 fabd bl 80067c8 + + /* LCD_BL_CTRL GPIO configuration */ + gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */ + 800424e: 2308 movs r3, #8 + 8004250: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8004252: 2301 movs r3, #1 + 8004254: 633b str r3, [r7, #48] ; 0x30 + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure); + 8004256: f107 032c add.w r3, r7, #44 ; 0x2c + 800425a: 4619 mov r1, r3 + 800425c: 4808 ldr r0, [pc, #32] ; (8004280 ) + 800425e: f002 fab3 bl 80067c8 +} + 8004262: bf00 nop + 8004264: 3740 adds r7, #64 ; 0x40 + 8004266: 46bd mov sp, r7 + 8004268: bd80 pop {r7, pc} + 800426a: bf00 nop + 800426c: 40023800 .word 0x40023800 + 8004270: 40021000 .word 0x40021000 + 8004274: 40021800 .word 0x40021800 + 8004278: 40022000 .word 0x40022000 + 800427c: 40022400 .word 0x40022400 + 8004280: 40022800 .word 0x40022800 + +08004284 : + * @note This API is called by BSP_LCD_Init() + * Being __weak it can be overwritten by the application + * @retval None + */ +__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params) +{ + 8004284: b580 push {r7, lr} + 8004286: b082 sub sp, #8 + 8004288: af00 add r7, sp, #0 + 800428a: 6078 str r0, [r7, #4] + 800428c: 6039 str r1, [r7, #0] + /* RK043FN48H LCD clock configuration */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */ + /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */ + periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + 800428e: 4b0a ldr r3, [pc, #40] ; (80042b8 ) + 8004290: 2208 movs r2, #8 + 8004292: 601a str r2, [r3, #0] + periph_clk_init_struct.PLLSAI.PLLSAIN = 192; + 8004294: 4b08 ldr r3, [pc, #32] ; (80042b8 ) + 8004296: 22c0 movs r2, #192 ; 0xc0 + 8004298: 615a str r2, [r3, #20] + periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER; + 800429a: 4b07 ldr r3, [pc, #28] ; (80042b8 ) + 800429c: 2205 movs r2, #5 + 800429e: 61da str r2, [r3, #28] + periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4; + 80042a0: 4b05 ldr r3, [pc, #20] ; (80042b8 ) + 80042a2: f44f 3280 mov.w r2, #65536 ; 0x10000 + 80042a6: 62da str r2, [r3, #44] ; 0x2c + HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct); + 80042a8: 4803 ldr r0, [pc, #12] ; (80042b8 ) + 80042aa: f004 f87b bl 80083a4 +} + 80042ae: bf00 nop + 80042b0: 3708 adds r7, #8 + 80042b2: 46bd mov sp, r7 + 80042b4: bd80 pop {r7, pc} + 80042b6: bf00 nop + 80042b8: 20000860 .word 0x20000860 + +080042bc : + * @param Ypos: Start column address + * @param c: Pointer to the character data + * @retval None + */ +static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c) +{ + 80042bc: b580 push {r7, lr} + 80042be: b088 sub sp, #32 + 80042c0: af00 add r7, sp, #0 + 80042c2: 4603 mov r3, r0 + 80042c4: 603a str r2, [r7, #0] + 80042c6: 80fb strh r3, [r7, #6] + 80042c8: 460b mov r3, r1 + 80042ca: 80bb strh r3, [r7, #4] + uint32_t i = 0, j = 0; + 80042cc: 2300 movs r3, #0 + 80042ce: 61fb str r3, [r7, #28] + 80042d0: 2300 movs r3, #0 + 80042d2: 61bb str r3, [r7, #24] + uint16_t height, width; + uint8_t offset; + uint8_t *pchar; + uint32_t line; + + height = DrawProp[ActiveLayer].pFont->Height; + 80042d4: 4b53 ldr r3, [pc, #332] ; (8004424 ) + 80042d6: 681a ldr r2, [r3, #0] + 80042d8: 4953 ldr r1, [pc, #332] ; (8004428 ) + 80042da: 4613 mov r3, r2 + 80042dc: 005b lsls r3, r3, #1 + 80042de: 4413 add r3, r2 + 80042e0: 009b lsls r3, r3, #2 + 80042e2: 440b add r3, r1 + 80042e4: 3308 adds r3, #8 + 80042e6: 681b ldr r3, [r3, #0] + 80042e8: 88db ldrh r3, [r3, #6] + 80042ea: 827b strh r3, [r7, #18] + width = DrawProp[ActiveLayer].pFont->Width; + 80042ec: 4b4d ldr r3, [pc, #308] ; (8004424 ) + 80042ee: 681a ldr r2, [r3, #0] + 80042f0: 494d ldr r1, [pc, #308] ; (8004428 ) + 80042f2: 4613 mov r3, r2 + 80042f4: 005b lsls r3, r3, #1 + 80042f6: 4413 add r3, r2 + 80042f8: 009b lsls r3, r3, #2 + 80042fa: 440b add r3, r1 + 80042fc: 3308 adds r3, #8 + 80042fe: 681b ldr r3, [r3, #0] + 8004300: 889b ldrh r3, [r3, #4] + 8004302: 823b strh r3, [r7, #16] + + offset = 8 *((width + 7)/8) - width ; + 8004304: 8a3b ldrh r3, [r7, #16] + 8004306: 3307 adds r3, #7 + 8004308: 2b00 cmp r3, #0 + 800430a: da00 bge.n 800430e + 800430c: 3307 adds r3, #7 + 800430e: 10db asrs r3, r3, #3 + 8004310: b2db uxtb r3, r3 + 8004312: 00db lsls r3, r3, #3 + 8004314: b2da uxtb r2, r3 + 8004316: 8a3b ldrh r3, [r7, #16] + 8004318: b2db uxtb r3, r3 + 800431a: 1ad3 subs r3, r2, r3 + 800431c: 73fb strb r3, [r7, #15] + + for(i = 0; i < height; i++) + 800431e: 2300 movs r3, #0 + 8004320: 61fb str r3, [r7, #28] + 8004322: e076 b.n 8004412 + { + pchar = ((uint8_t *)c + (width + 7)/8 * i); + 8004324: 8a3b ldrh r3, [r7, #16] + 8004326: 3307 adds r3, #7 + 8004328: 2b00 cmp r3, #0 + 800432a: da00 bge.n 800432e + 800432c: 3307 adds r3, #7 + 800432e: 10db asrs r3, r3, #3 + 8004330: 461a mov r2, r3 + 8004332: 69fb ldr r3, [r7, #28] + 8004334: fb02 f303 mul.w r3, r2, r3 + 8004338: 683a ldr r2, [r7, #0] + 800433a: 4413 add r3, r2 + 800433c: 60bb str r3, [r7, #8] + + switch(((width + 7)/8)) + 800433e: 8a3b ldrh r3, [r7, #16] + 8004340: 3307 adds r3, #7 + 8004342: 2b00 cmp r3, #0 + 8004344: da00 bge.n 8004348 + 8004346: 3307 adds r3, #7 + 8004348: 10db asrs r3, r3, #3 + 800434a: 2b01 cmp r3, #1 + 800434c: d002 beq.n 8004354 + 800434e: 2b02 cmp r3, #2 + 8004350: d004 beq.n 800435c + 8004352: e00c b.n 800436e + { + + case 1: + line = pchar[0]; + 8004354: 68bb ldr r3, [r7, #8] + 8004356: 781b ldrb r3, [r3, #0] + 8004358: 617b str r3, [r7, #20] + break; + 800435a: e016 b.n 800438a + + case 2: + line = (pchar[0]<< 8) | pchar[1]; + 800435c: 68bb ldr r3, [r7, #8] + 800435e: 781b ldrb r3, [r3, #0] + 8004360: 021b lsls r3, r3, #8 + 8004362: 68ba ldr r2, [r7, #8] + 8004364: 3201 adds r2, #1 + 8004366: 7812 ldrb r2, [r2, #0] + 8004368: 4313 orrs r3, r2 + 800436a: 617b str r3, [r7, #20] + break; + 800436c: e00d b.n 800438a + + case 3: + default: + line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2]; + 800436e: 68bb ldr r3, [r7, #8] + 8004370: 781b ldrb r3, [r3, #0] + 8004372: 041a lsls r2, r3, #16 + 8004374: 68bb ldr r3, [r7, #8] + 8004376: 3301 adds r3, #1 + 8004378: 781b ldrb r3, [r3, #0] + 800437a: 021b lsls r3, r3, #8 + 800437c: 4313 orrs r3, r2 + 800437e: 68ba ldr r2, [r7, #8] + 8004380: 3202 adds r2, #2 + 8004382: 7812 ldrb r2, [r2, #0] + 8004384: 4313 orrs r3, r2 + 8004386: 617b str r3, [r7, #20] + break; + 8004388: bf00 nop + } + + for (j = 0; j < width; j++) + 800438a: 2300 movs r3, #0 + 800438c: 61bb str r3, [r7, #24] + 800438e: e036 b.n 80043fe + { + if(line & (1 << (width- j + offset- 1))) + 8004390: 8a3a ldrh r2, [r7, #16] + 8004392: 69bb ldr r3, [r7, #24] + 8004394: 1ad2 subs r2, r2, r3 + 8004396: 7bfb ldrb r3, [r7, #15] + 8004398: 4413 add r3, r2 + 800439a: 3b01 subs r3, #1 + 800439c: 2201 movs r2, #1 + 800439e: fa02 f303 lsl.w r3, r2, r3 + 80043a2: 461a mov r2, r3 + 80043a4: 697b ldr r3, [r7, #20] + 80043a6: 4013 ands r3, r2 + 80043a8: 2b00 cmp r3, #0 + 80043aa: d012 beq.n 80043d2 + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor); + 80043ac: 69bb ldr r3, [r7, #24] + 80043ae: b29a uxth r2, r3 + 80043b0: 88fb ldrh r3, [r7, #6] + 80043b2: 4413 add r3, r2 + 80043b4: b298 uxth r0, r3 + 80043b6: 4b1b ldr r3, [pc, #108] ; (8004424 ) + 80043b8: 681a ldr r2, [r3, #0] + 80043ba: 491b ldr r1, [pc, #108] ; (8004428 ) + 80043bc: 4613 mov r3, r2 + 80043be: 005b lsls r3, r3, #1 + 80043c0: 4413 add r3, r2 + 80043c2: 009b lsls r3, r3, #2 + 80043c4: 440b add r3, r1 + 80043c6: 681a ldr r2, [r3, #0] + 80043c8: 88bb ldrh r3, [r7, #4] + 80043ca: 4619 mov r1, r3 + 80043cc: f7ff fe1a bl 8004004 + 80043d0: e012 b.n 80043f8 + } + else + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor); + 80043d2: 69bb ldr r3, [r7, #24] + 80043d4: b29a uxth r2, r3 + 80043d6: 88fb ldrh r3, [r7, #6] + 80043d8: 4413 add r3, r2 + 80043da: b298 uxth r0, r3 + 80043dc: 4b11 ldr r3, [pc, #68] ; (8004424 ) + 80043de: 681a ldr r2, [r3, #0] + 80043e0: 4911 ldr r1, [pc, #68] ; (8004428 ) + 80043e2: 4613 mov r3, r2 + 80043e4: 005b lsls r3, r3, #1 + 80043e6: 4413 add r3, r2 + 80043e8: 009b lsls r3, r3, #2 + 80043ea: 440b add r3, r1 + 80043ec: 3304 adds r3, #4 + 80043ee: 681a ldr r2, [r3, #0] + 80043f0: 88bb ldrh r3, [r7, #4] + 80043f2: 4619 mov r1, r3 + 80043f4: f7ff fe06 bl 8004004 + for (j = 0; j < width; j++) + 80043f8: 69bb ldr r3, [r7, #24] + 80043fa: 3301 adds r3, #1 + 80043fc: 61bb str r3, [r7, #24] + 80043fe: 8a3b ldrh r3, [r7, #16] + 8004400: 69ba ldr r2, [r7, #24] + 8004402: 429a cmp r2, r3 + 8004404: d3c4 bcc.n 8004390 + } + } + Ypos++; + 8004406: 88bb ldrh r3, [r7, #4] + 8004408: 3301 adds r3, #1 + 800440a: 80bb strh r3, [r7, #4] + for(i = 0; i < height; i++) + 800440c: 69fb ldr r3, [r7, #28] + 800440e: 3301 adds r3, #1 + 8004410: 61fb str r3, [r7, #28] + 8004412: 8a7b ldrh r3, [r7, #18] + 8004414: 69fa ldr r2, [r7, #28] + 8004416: 429a cmp r2, r3 + 8004418: d384 bcc.n 8004324 + } +} + 800441a: bf00 nop + 800441c: bf00 nop + 800441e: 3720 adds r7, #32 + 8004420: 46bd mov sp, r7 + 8004422: bd80 pop {r7, pc} + 8004424: 20000844 .word 0x20000844 + 8004428: 20000848 .word 0x20000848 + +0800442c : + * @param OffLine: Offset + * @param ColorIndex: Color index + * @retval None + */ +static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex) +{ + 800442c: b580 push {r7, lr} + 800442e: b086 sub sp, #24 + 8004430: af02 add r7, sp, #8 + 8004432: 60f8 str r0, [r7, #12] + 8004434: 60b9 str r1, [r7, #8] + 8004436: 607a str r2, [r7, #4] + 8004438: 603b str r3, [r7, #0] + /* Register to memory mode with ARGB8888 as color Mode */ + hDma2dHandler.Init.Mode = DMA2D_R2M; + 800443a: 4b1e ldr r3, [pc, #120] ; (80044b4 ) + 800443c: f44f 3240 mov.w r2, #196608 ; 0x30000 + 8004440: 605a str r2, [r3, #4] + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + 8004442: 4b1d ldr r3, [pc, #116] ; (80044b8 ) + 8004444: 681b ldr r3, [r3, #0] + 8004446: 4a1d ldr r2, [pc, #116] ; (80044bc ) + 8004448: 2134 movs r1, #52 ; 0x34 + 800444a: fb01 f303 mul.w r3, r1, r3 + 800444e: 4413 add r3, r2 + 8004450: 3348 adds r3, #72 ; 0x48 + 8004452: 681b ldr r3, [r3, #0] + 8004454: 2b02 cmp r3, #2 + 8004456: d103 bne.n 8004460 + { /* RGB565 format */ + hDma2dHandler.Init.ColorMode = DMA2D_RGB565; + 8004458: 4b16 ldr r3, [pc, #88] ; (80044b4 ) + 800445a: 2202 movs r2, #2 + 800445c: 609a str r2, [r3, #8] + 800445e: e002 b.n 8004466 + } + else + { /* ARGB8888 format */ + hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888; + 8004460: 4b14 ldr r3, [pc, #80] ; (80044b4 ) + 8004462: 2200 movs r2, #0 + 8004464: 609a str r2, [r3, #8] + } + hDma2dHandler.Init.OutputOffset = OffLine; + 8004466: 4a13 ldr r2, [pc, #76] ; (80044b4 ) + 8004468: 69bb ldr r3, [r7, #24] + 800446a: 60d3 str r3, [r2, #12] + + hDma2dHandler.Instance = DMA2D; + 800446c: 4b11 ldr r3, [pc, #68] ; (80044b4 ) + 800446e: 4a14 ldr r2, [pc, #80] ; (80044c0 ) + 8004470: 601a str r2, [r3, #0] + + /* DMA2D Initialization */ + if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK) + 8004472: 4810 ldr r0, [pc, #64] ; (80044b4 ) + 8004474: f000 fcce bl 8004e14 + 8004478: 4603 mov r3, r0 + 800447a: 2b00 cmp r3, #0 + 800447c: d115 bne.n 80044aa + { + if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK) + 800447e: 68f9 ldr r1, [r7, #12] + 8004480: 480c ldr r0, [pc, #48] ; (80044b4 ) + 8004482: f000 fe25 bl 80050d0 + 8004486: 4603 mov r3, r0 + 8004488: 2b00 cmp r3, #0 + 800448a: d10e bne.n 80044aa + { + if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK) + 800448c: 68ba ldr r2, [r7, #8] + 800448e: 683b ldr r3, [r7, #0] + 8004490: 9300 str r3, [sp, #0] + 8004492: 687b ldr r3, [r7, #4] + 8004494: 69f9 ldr r1, [r7, #28] + 8004496: 4807 ldr r0, [pc, #28] ; (80044b4 ) + 8004498: f000 fd06 bl 8004ea8 + 800449c: 4603 mov r3, r0 + 800449e: 2b00 cmp r3, #0 + 80044a0: d103 bne.n 80044aa + { + /* Polling For DMA transfer */ + HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10); + 80044a2: 210a movs r1, #10 + 80044a4: 4803 ldr r0, [pc, #12] ; (80044b4 ) + 80044a6: f000 fd2a bl 8004efe + } + } + } +} + 80044aa: bf00 nop + 80044ac: 3710 adds r7, #16 + 80044ae: 46bd mov sp, r7 + 80044b0: bd80 pop {r7, pc} + 80044b2: bf00 nop + 80044b4: 20000804 .word 0x20000804 + 80044b8: 20000844 .word 0x20000844 + 80044bc: 2000075c .word 0x2000075c + 80044c0: 4002b000 .word 0x4002b000 + +080044c4 : +/** + * @brief Initializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Init(void) +{ + 80044c4: b580 push {r7, lr} + 80044c6: af00 add r7, sp, #0 + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device configuration */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + 80044c8: 4b29 ldr r3, [pc, #164] ; (8004570 ) + 80044ca: 4a2a ldr r2, [pc, #168] ; (8004574 ) + 80044cc: 601a str r2, [r3, #0] + + /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ + Timing.LoadToActiveDelay = 2; + 80044ce: 4b2a ldr r3, [pc, #168] ; (8004578 ) + 80044d0: 2202 movs r2, #2 + 80044d2: 601a str r2, [r3, #0] + Timing.ExitSelfRefreshDelay = 7; + 80044d4: 4b28 ldr r3, [pc, #160] ; (8004578 ) + 80044d6: 2207 movs r2, #7 + 80044d8: 605a str r2, [r3, #4] + Timing.SelfRefreshTime = 4; + 80044da: 4b27 ldr r3, [pc, #156] ; (8004578 ) + 80044dc: 2204 movs r2, #4 + 80044de: 609a str r2, [r3, #8] + Timing.RowCycleDelay = 7; + 80044e0: 4b25 ldr r3, [pc, #148] ; (8004578 ) + 80044e2: 2207 movs r2, #7 + 80044e4: 60da str r2, [r3, #12] + Timing.WriteRecoveryTime = 2; + 80044e6: 4b24 ldr r3, [pc, #144] ; (8004578 ) + 80044e8: 2202 movs r2, #2 + 80044ea: 611a str r2, [r3, #16] + Timing.RPDelay = 2; + 80044ec: 4b22 ldr r3, [pc, #136] ; (8004578 ) + 80044ee: 2202 movs r2, #2 + 80044f0: 615a str r2, [r3, #20] + Timing.RCDDelay = 2; + 80044f2: 4b21 ldr r3, [pc, #132] ; (8004578 ) + 80044f4: 2202 movs r2, #2 + 80044f6: 619a str r2, [r3, #24] + + sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; + 80044f8: 4b1d ldr r3, [pc, #116] ; (8004570 ) + 80044fa: 2200 movs r2, #0 + 80044fc: 605a str r2, [r3, #4] + sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + 80044fe: 4b1c ldr r3, [pc, #112] ; (8004570 ) + 8004500: 2200 movs r2, #0 + 8004502: 609a str r2, [r3, #8] + sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + 8004504: 4b1a ldr r3, [pc, #104] ; (8004570 ) + 8004506: 2204 movs r2, #4 + 8004508: 60da str r2, [r3, #12] + sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + 800450a: 4b19 ldr r3, [pc, #100] ; (8004570 ) + 800450c: 2210 movs r2, #16 + 800450e: 611a str r2, [r3, #16] + sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + 8004510: 4b17 ldr r3, [pc, #92] ; (8004570 ) + 8004512: 2240 movs r2, #64 ; 0x40 + 8004514: 615a str r2, [r3, #20] + sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + 8004516: 4b16 ldr r3, [pc, #88] ; (8004570 ) + 8004518: f44f 7280 mov.w r2, #256 ; 0x100 + 800451c: 619a str r2, [r3, #24] + sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + 800451e: 4b14 ldr r3, [pc, #80] ; (8004570 ) + 8004520: 2200 movs r2, #0 + 8004522: 61da str r2, [r3, #28] + sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + 8004524: 4b12 ldr r3, [pc, #72] ; (8004570 ) + 8004526: f44f 6200 mov.w r2, #2048 ; 0x800 + 800452a: 621a str r2, [r3, #32] + sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + 800452c: 4b10 ldr r3, [pc, #64] ; (8004570 ) + 800452e: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8004532: 625a str r2, [r3, #36] ; 0x24 + sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + 8004534: 4b0e ldr r3, [pc, #56] ; (8004570 ) + 8004536: 2200 movs r2, #0 + 8004538: 629a str r2, [r3, #40] ; 0x28 + + /* SDRAM controller initialization */ + + BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + 800453a: 2100 movs r1, #0 + 800453c: 480c ldr r0, [pc, #48] ; (8004570 ) + 800453e: f000 f87f bl 8004640 + + if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + 8004542: 490d ldr r1, [pc, #52] ; (8004578 ) + 8004544: 480a ldr r0, [pc, #40] ; (8004570 ) + 8004546: f004 fe47 bl 80091d8 + 800454a: 4603 mov r3, r0 + 800454c: 2b00 cmp r3, #0 + 800454e: d003 beq.n 8004558 + { + sdramstatus = SDRAM_ERROR; + 8004550: 4b0a ldr r3, [pc, #40] ; (800457c ) + 8004552: 2201 movs r2, #1 + 8004554: 701a strb r2, [r3, #0] + 8004556: e002 b.n 800455e + } + else + { + sdramstatus = SDRAM_OK; + 8004558: 4b08 ldr r3, [pc, #32] ; (800457c ) + 800455a: 2200 movs r2, #0 + 800455c: 701a strb r2, [r3, #0] + } + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + 800455e: f240 6003 movw r0, #1539 ; 0x603 + 8004562: f000 f80d bl 8004580 + + return sdramstatus; + 8004566: 4b05 ldr r3, [pc, #20] ; (800457c ) + 8004568: 781b ldrb r3, [r3, #0] +} + 800456a: 4618 mov r0, r3 + 800456c: bd80 pop {r7, pc} + 800456e: bf00 nop + 8004570: 200008e4 .word 0x200008e4 + 8004574: a0000140 .word 0xa0000140 + 8004578: 20000918 .word 0x20000918 + 800457c: 20000090 .word 0x20000090 + +08004580 : + * @brief Programs the SDRAM device. + * @param RefreshCount: SDRAM refresh counter value + * @retval None + */ +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +{ + 8004580: b580 push {r7, lr} + 8004582: b084 sub sp, #16 + 8004584: af00 add r7, sp, #0 + 8004586: 6078 str r0, [r7, #4] + __IO uint32_t tmpmrd = 0; + 8004588: 2300 movs r3, #0 + 800458a: 60fb str r3, [r7, #12] + + /* Step 1: Configure a clock configuration enable command */ + Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + 800458c: 4b2a ldr r3, [pc, #168] ; (8004638 ) + 800458e: 2201 movs r2, #1 + 8004590: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 8004592: 4b29 ldr r3, [pc, #164] ; (8004638 ) + 8004594: 2210 movs r2, #16 + 8004596: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 8004598: 4b27 ldr r3, [pc, #156] ; (8004638 ) + 800459a: 2201 movs r2, #1 + 800459c: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 800459e: 4b26 ldr r3, [pc, #152] ; (8004638 ) + 80045a0: 2200 movs r2, #0 + 80045a2: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 80045a4: f64f 72ff movw r2, #65535 ; 0xffff + 80045a8: 4923 ldr r1, [pc, #140] ; (8004638 ) + 80045aa: 4824 ldr r0, [pc, #144] ; (800463c ) + 80045ac: f004 fe48 bl 8009240 + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + 80045b0: 2001 movs r0, #1 + 80045b2: f000 f96b bl 800488c + + /* Step 3: Configure a PALL (precharge all) command */ + Command.CommandMode = FMC_SDRAM_CMD_PALL; + 80045b6: 4b20 ldr r3, [pc, #128] ; (8004638 ) + 80045b8: 2202 movs r2, #2 + 80045ba: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 80045bc: 4b1e ldr r3, [pc, #120] ; (8004638 ) + 80045be: 2210 movs r2, #16 + 80045c0: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 80045c2: 4b1d ldr r3, [pc, #116] ; (8004638 ) + 80045c4: 2201 movs r2, #1 + 80045c6: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 80045c8: 4b1b ldr r3, [pc, #108] ; (8004638 ) + 80045ca: 2200 movs r2, #0 + 80045cc: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 80045ce: f64f 72ff movw r2, #65535 ; 0xffff + 80045d2: 4919 ldr r1, [pc, #100] ; (8004638 ) + 80045d4: 4819 ldr r0, [pc, #100] ; (800463c ) + 80045d6: f004 fe33 bl 8009240 + + /* Step 4: Configure an Auto Refresh command */ + Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + 80045da: 4b17 ldr r3, [pc, #92] ; (8004638 ) + 80045dc: 2203 movs r2, #3 + 80045de: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 80045e0: 4b15 ldr r3, [pc, #84] ; (8004638 ) + 80045e2: 2210 movs r2, #16 + 80045e4: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 8; + 80045e6: 4b14 ldr r3, [pc, #80] ; (8004638 ) + 80045e8: 2208 movs r2, #8 + 80045ea: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 80045ec: 4b12 ldr r3, [pc, #72] ; (8004638 ) + 80045ee: 2200 movs r2, #0 + 80045f0: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 80045f2: f64f 72ff movw r2, #65535 ; 0xffff + 80045f6: 4910 ldr r1, [pc, #64] ; (8004638 ) + 80045f8: 4810 ldr r0, [pc, #64] ; (800463c ) + 80045fa: f004 fe21 bl 8009240 + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + 80045fe: f44f 7308 mov.w r3, #544 ; 0x220 + 8004602: 60fb str r3, [r7, #12] + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + 8004604: 4b0c ldr r3, [pc, #48] ; (8004638 ) + 8004606: 2204 movs r2, #4 + 8004608: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 800460a: 4b0b ldr r3, [pc, #44] ; (8004638 ) + 800460c: 2210 movs r2, #16 + 800460e: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 8004610: 4b09 ldr r3, [pc, #36] ; (8004638 ) + 8004612: 2201 movs r2, #1 + 8004614: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = tmpmrd; + 8004616: 68fb ldr r3, [r7, #12] + 8004618: 4a07 ldr r2, [pc, #28] ; (8004638 ) + 800461a: 60d3 str r3, [r2, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 800461c: f64f 72ff movw r2, #65535 ; 0xffff + 8004620: 4905 ldr r1, [pc, #20] ; (8004638 ) + 8004622: 4806 ldr r0, [pc, #24] ; (800463c ) + 8004624: f004 fe0c bl 8009240 + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); + 8004628: 6879 ldr r1, [r7, #4] + 800462a: 4804 ldr r0, [pc, #16] ; (800463c ) + 800462c: f004 fe3d bl 80092aa +} + 8004630: bf00 nop + 8004632: 3710 adds r7, #16 + 8004634: 46bd mov sp, r7 + 8004636: bd80 pop {r7, pc} + 8004638: 20000934 .word 0x20000934 + 800463c: 200008e4 .word 0x200008e4 + +08004640 : + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + 8004640: b580 push {r7, lr} + 8004642: b090 sub sp, #64 ; 0x40 + 8004644: af00 add r7, sp, #0 + 8004646: 6078 str r0, [r7, #4] + 8004648: 6039 str r1, [r7, #0] + static DMA_HandleTypeDef dma_handle; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + 800464a: 4b70 ldr r3, [pc, #448] ; (800480c ) + 800464c: 6b9b ldr r3, [r3, #56] ; 0x38 + 800464e: 4a6f ldr r2, [pc, #444] ; (800480c ) + 8004650: f043 0301 orr.w r3, r3, #1 + 8004654: 6393 str r3, [r2, #56] ; 0x38 + 8004656: 4b6d ldr r3, [pc, #436] ; (800480c ) + 8004658: 6b9b ldr r3, [r3, #56] ; 0x38 + 800465a: f003 0301 and.w r3, r3, #1 + 800465e: 62bb str r3, [r7, #40] ; 0x28 + 8004660: 6abb ldr r3, [r7, #40] ; 0x28 + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + 8004662: 4b6a ldr r3, [pc, #424] ; (800480c ) + 8004664: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004666: 4a69 ldr r2, [pc, #420] ; (800480c ) + 8004668: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 800466c: 6313 str r3, [r2, #48] ; 0x30 + 800466e: 4b67 ldr r3, [pc, #412] ; (800480c ) + 8004670: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004672: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8004676: 627b str r3, [r7, #36] ; 0x24 + 8004678: 6a7b ldr r3, [r7, #36] ; 0x24 + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800467a: 4b64 ldr r3, [pc, #400] ; (800480c ) + 800467c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800467e: 4a63 ldr r2, [pc, #396] ; (800480c ) + 8004680: f043 0304 orr.w r3, r3, #4 + 8004684: 6313 str r3, [r2, #48] ; 0x30 + 8004686: 4b61 ldr r3, [pc, #388] ; (800480c ) + 8004688: 6b1b ldr r3, [r3, #48] ; 0x30 + 800468a: f003 0304 and.w r3, r3, #4 + 800468e: 623b str r3, [r7, #32] + 8004690: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8004692: 4b5e ldr r3, [pc, #376] ; (800480c ) + 8004694: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004696: 4a5d ldr r2, [pc, #372] ; (800480c ) + 8004698: f043 0308 orr.w r3, r3, #8 + 800469c: 6313 str r3, [r2, #48] ; 0x30 + 800469e: 4b5b ldr r3, [pc, #364] ; (800480c ) + 80046a0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046a2: f003 0308 and.w r3, r3, #8 + 80046a6: 61fb str r3, [r7, #28] + 80046a8: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80046aa: 4b58 ldr r3, [pc, #352] ; (800480c ) + 80046ac: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046ae: 4a57 ldr r2, [pc, #348] ; (800480c ) + 80046b0: f043 0310 orr.w r3, r3, #16 + 80046b4: 6313 str r3, [r2, #48] ; 0x30 + 80046b6: 4b55 ldr r3, [pc, #340] ; (800480c ) + 80046b8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046ba: f003 0310 and.w r3, r3, #16 + 80046be: 61bb str r3, [r7, #24] + 80046c0: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 80046c2: 4b52 ldr r3, [pc, #328] ; (800480c ) + 80046c4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046c6: 4a51 ldr r2, [pc, #324] ; (800480c ) + 80046c8: f043 0320 orr.w r3, r3, #32 + 80046cc: 6313 str r3, [r2, #48] ; 0x30 + 80046ce: 4b4f ldr r3, [pc, #316] ; (800480c ) + 80046d0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046d2: f003 0320 and.w r3, r3, #32 + 80046d6: 617b str r3, [r7, #20] + 80046d8: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 80046da: 4b4c ldr r3, [pc, #304] ; (800480c ) + 80046dc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046de: 4a4b ldr r2, [pc, #300] ; (800480c ) + 80046e0: f043 0340 orr.w r3, r3, #64 ; 0x40 + 80046e4: 6313 str r3, [r2, #48] ; 0x30 + 80046e6: 4b49 ldr r3, [pc, #292] ; (800480c ) + 80046e8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046ea: f003 0340 and.w r3, r3, #64 ; 0x40 + 80046ee: 613b str r3, [r7, #16] + 80046f0: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 80046f2: 4b46 ldr r3, [pc, #280] ; (800480c ) + 80046f4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80046f6: 4a45 ldr r2, [pc, #276] ; (800480c ) + 80046f8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80046fc: 6313 str r3, [r2, #48] ; 0x30 + 80046fe: 4b43 ldr r3, [pc, #268] ; (800480c ) + 8004700: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004702: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004706: 60fb str r3, [r7, #12] + 8004708: 68fb ldr r3, [r7, #12] + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 800470a: 2302 movs r3, #2 + 800470c: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Pull = GPIO_PULLUP; + 800470e: 2301 movs r3, #1 + 8004710: 637b str r3, [r7, #52] ; 0x34 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 8004712: 2302 movs r3, #2 + 8004714: 63bb str r3, [r7, #56] ; 0x38 + gpio_init_structure.Alternate = GPIO_AF12_FMC; + 8004716: 230c movs r3, #12 + 8004718: 63fb str r3, [r7, #60] ; 0x3c + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + 800471a: 2308 movs r3, #8 + 800471c: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + 800471e: f107 032c add.w r3, r7, #44 ; 0x2c + 8004722: 4619 mov r1, r3 + 8004724: 483a ldr r0, [pc, #232] ; (8004810 ) + 8004726: f002 f84f bl 80067c8 + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | + 800472a: f24c 7303 movw r3, #50947 ; 0xc703 + 800472e: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + 8004730: f107 032c add.w r3, r7, #44 ; 0x2c + 8004734: 4619 mov r1, r3 + 8004736: 4837 ldr r0, [pc, #220] ; (8004814 ) + 8004738: f002 f846 bl 80067c8 + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + 800473c: f64f 7383 movw r3, #65411 ; 0xff83 + 8004740: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + 8004742: f107 032c add.w r3, r7, #44 ; 0x2c + 8004746: 4619 mov r1, r3 + 8004748: 4833 ldr r0, [pc, #204] ; (8004818 ) + 800474a: f002 f83d bl 80067c8 + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + 800474e: f64f 033f movw r3, #63551 ; 0xf83f + 8004752: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + 8004754: f107 032c add.w r3, r7, #44 ; 0x2c + 8004758: 4619 mov r1, r3 + 800475a: 4830 ldr r0, [pc, #192] ; (800481c ) + 800475c: f002 f834 bl 80067c8 + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + 8004760: f248 1333 movw r3, #33075 ; 0x8133 + 8004764: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + 8004766: f107 032c add.w r3, r7, #44 ; 0x2c + 800476a: 4619 mov r1, r3 + 800476c: 482c ldr r0, [pc, #176] ; (8004820 ) + 800476e: f002 f82b bl 80067c8 + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + 8004772: 2328 movs r3, #40 ; 0x28 + 8004774: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + 8004776: f107 032c add.w r3, r7, #44 ; 0x2c + 800477a: 4619 mov r1, r3 + 800477c: 4829 ldr r0, [pc, #164] ; (8004824 ) + 800477e: f002 f823 bl 80067c8 + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + 8004782: 4b29 ldr r3, [pc, #164] ; (8004828 ) + 8004784: 2200 movs r2, #0 + 8004786: 605a str r2, [r3, #4] + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + 8004788: 4b27 ldr r3, [pc, #156] ; (8004828 ) + 800478a: 2280 movs r2, #128 ; 0x80 + 800478c: 609a str r2, [r3, #8] + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + 800478e: 4b26 ldr r3, [pc, #152] ; (8004828 ) + 8004790: f44f 7200 mov.w r2, #512 ; 0x200 + 8004794: 60da str r2, [r3, #12] + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + 8004796: 4b24 ldr r3, [pc, #144] ; (8004828 ) + 8004798: f44f 6280 mov.w r2, #1024 ; 0x400 + 800479c: 611a str r2, [r3, #16] + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + 800479e: 4b22 ldr r3, [pc, #136] ; (8004828 ) + 80047a0: f44f 5280 mov.w r2, #4096 ; 0x1000 + 80047a4: 615a str r2, [r3, #20] + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + 80047a6: 4b20 ldr r3, [pc, #128] ; (8004828 ) + 80047a8: f44f 4280 mov.w r2, #16384 ; 0x4000 + 80047ac: 619a str r2, [r3, #24] + dma_handle.Init.Mode = DMA_NORMAL; + 80047ae: 4b1e ldr r3, [pc, #120] ; (8004828 ) + 80047b0: 2200 movs r2, #0 + 80047b2: 61da str r2, [r3, #28] + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + 80047b4: 4b1c ldr r3, [pc, #112] ; (8004828 ) + 80047b6: f44f 3200 mov.w r2, #131072 ; 0x20000 + 80047ba: 621a str r2, [r3, #32] + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 80047bc: 4b1a ldr r3, [pc, #104] ; (8004828 ) + 80047be: 2200 movs r2, #0 + 80047c0: 625a str r2, [r3, #36] ; 0x24 + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + 80047c2: 4b19 ldr r3, [pc, #100] ; (8004828 ) + 80047c4: 2203 movs r2, #3 + 80047c6: 629a str r2, [r3, #40] ; 0x28 + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + 80047c8: 4b17 ldr r3, [pc, #92] ; (8004828 ) + 80047ca: 2200 movs r2, #0 + 80047cc: 62da str r2, [r3, #44] ; 0x2c + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + 80047ce: 4b16 ldr r3, [pc, #88] ; (8004828 ) + 80047d0: 2200 movs r2, #0 + 80047d2: 631a str r2, [r3, #48] ; 0x30 + + dma_handle.Instance = SDRAM_DMAx_STREAM; + 80047d4: 4b14 ldr r3, [pc, #80] ; (8004828 ) + 80047d6: 4a15 ldr r2, [pc, #84] ; (800482c ) + 80047d8: 601a str r2, [r3, #0] + + /* Associate the DMA handle */ + __HAL_LINKDMA(hsdram, hdma, dma_handle); + 80047da: 687b ldr r3, [r7, #4] + 80047dc: 4a12 ldr r2, [pc, #72] ; (8004828 ) + 80047de: 631a str r2, [r3, #48] ; 0x30 + 80047e0: 4a11 ldr r2, [pc, #68] ; (8004828 ) + 80047e2: 687b ldr r3, [r7, #4] + 80047e4: 6393 str r3, [r2, #56] ; 0x38 + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + 80047e6: 4810 ldr r0, [pc, #64] ; (8004828 ) + 80047e8: f000 fa04 bl 8004bf4 + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + 80047ec: 480e ldr r0, [pc, #56] ; (8004828 ) + 80047ee: f000 f953 bl 8004a98 + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0); + 80047f2: 2200 movs r2, #0 + 80047f4: 210f movs r1, #15 + 80047f6: 2038 movs r0, #56 ; 0x38 + 80047f8: f000 f924 bl 8004a44 + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); + 80047fc: 2038 movs r0, #56 ; 0x38 + 80047fe: f000 f93d bl 8004a7c +} + 8004802: bf00 nop + 8004804: 3740 adds r7, #64 ; 0x40 + 8004806: 46bd mov sp, r7 + 8004808: bd80 pop {r7, pc} + 800480a: bf00 nop + 800480c: 40023800 .word 0x40023800 + 8004810: 40020800 .word 0x40020800 + 8004814: 40020c00 .word 0x40020c00 + 8004818: 40021000 .word 0x40021000 + 800481c: 40021400 .word 0x40021400 + 8004820: 40021800 .word 0x40021800 + 8004824: 40021c00 .word 0x40021c00 + 8004828: 20000944 .word 0x20000944 + 800482c: 40026410 .word 0x40026410 + +08004830 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8004830: b580 push {r7, lr} + 8004832: af00 add r7, sp, #0 +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8004834: 2003 movs r0, #3 + 8004836: f000 f8fa bl 8004a2e + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 800483a: 200f movs r0, #15 + 800483c: f7fe fcce bl 80031dc + + /* Init the low level hardware */ + HAL_MspInit(); + 8004840: f7fe fa52 bl 8002ce8 + + /* Return function status */ + return HAL_OK; + 8004844: 2300 movs r3, #0 +} + 8004846: 4618 mov r0, r3 + 8004848: bd80 pop {r7, pc} + ... + +0800484c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 800484c: b480 push {r7} + 800484e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8004850: 4b06 ldr r3, [pc, #24] ; (800486c ) + 8004852: 781b ldrb r3, [r3, #0] + 8004854: 461a mov r2, r3 + 8004856: 4b06 ldr r3, [pc, #24] ; (8004870 ) + 8004858: 681b ldr r3, [r3, #0] + 800485a: 4413 add r3, r2 + 800485c: 4a04 ldr r2, [pc, #16] ; (8004870 ) + 800485e: 6013 str r3, [r2, #0] +} + 8004860: bf00 nop + 8004862: 46bd mov sp, r7 + 8004864: f85d 7b04 ldr.w r7, [sp], #4 + 8004868: 4770 bx lr + 800486a: bf00 nop + 800486c: 20000098 .word 0x20000098 + 8004870: 200009a4 .word 0x200009a4 + +08004874 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8004874: b480 push {r7} + 8004876: af00 add r7, sp, #0 + return uwTick; + 8004878: 4b03 ldr r3, [pc, #12] ; (8004888 ) + 800487a: 681b ldr r3, [r3, #0] +} + 800487c: 4618 mov r0, r3 + 800487e: 46bd mov sp, r7 + 8004880: f85d 7b04 ldr.w r7, [sp], #4 + 8004884: 4770 bx lr + 8004886: bf00 nop + 8004888: 200009a4 .word 0x200009a4 + +0800488c : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 800488c: b580 push {r7, lr} + 800488e: b084 sub sp, #16 + 8004890: af00 add r7, sp, #0 + 8004892: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8004894: f7ff ffee bl 8004874 + 8004898: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800489a: 687b ldr r3, [r7, #4] + 800489c: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800489e: 68fb ldr r3, [r7, #12] + 80048a0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80048a4: d005 beq.n 80048b2 + { + wait += (uint32_t)(uwTickFreq); + 80048a6: 4b0a ldr r3, [pc, #40] ; (80048d0 ) + 80048a8: 781b ldrb r3, [r3, #0] + 80048aa: 461a mov r2, r3 + 80048ac: 68fb ldr r3, [r7, #12] + 80048ae: 4413 add r3, r2 + 80048b0: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 80048b2: bf00 nop + 80048b4: f7ff ffde bl 8004874 + 80048b8: 4602 mov r2, r0 + 80048ba: 68bb ldr r3, [r7, #8] + 80048bc: 1ad3 subs r3, r2, r3 + 80048be: 68fa ldr r2, [r7, #12] + 80048c0: 429a cmp r2, r3 + 80048c2: d8f7 bhi.n 80048b4 + { + } +} + 80048c4: bf00 nop + 80048c6: bf00 nop + 80048c8: 3710 adds r7, #16 + 80048ca: 46bd mov sp, r7 + 80048cc: bd80 pop {r7, pc} + 80048ce: bf00 nop + 80048d0: 20000098 .word 0x20000098 + +080048d4 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80048d4: b480 push {r7} + 80048d6: b085 sub sp, #20 + 80048d8: af00 add r7, sp, #0 + 80048da: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80048dc: 687b ldr r3, [r7, #4] + 80048de: f003 0307 and.w r3, r3, #7 + 80048e2: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80048e4: 4b0b ldr r3, [pc, #44] ; (8004914 <__NVIC_SetPriorityGrouping+0x40>) + 80048e6: 68db ldr r3, [r3, #12] + 80048e8: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 80048ea: 68ba ldr r2, [r7, #8] + 80048ec: f64f 03ff movw r3, #63743 ; 0xf8ff + 80048f0: 4013 ands r3, r2 + 80048f2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 80048f4: 68fb ldr r3, [r7, #12] + 80048f6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 80048f8: 68bb ldr r3, [r7, #8] + 80048fa: 431a orrs r2, r3 + reg_value = (reg_value | + 80048fc: 4b06 ldr r3, [pc, #24] ; (8004918 <__NVIC_SetPriorityGrouping+0x44>) + 80048fe: 4313 orrs r3, r2 + 8004900: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8004902: 4a04 ldr r2, [pc, #16] ; (8004914 <__NVIC_SetPriorityGrouping+0x40>) + 8004904: 68bb ldr r3, [r7, #8] + 8004906: 60d3 str r3, [r2, #12] +} + 8004908: bf00 nop + 800490a: 3714 adds r7, #20 + 800490c: 46bd mov sp, r7 + 800490e: f85d 7b04 ldr.w r7, [sp], #4 + 8004912: 4770 bx lr + 8004914: e000ed00 .word 0xe000ed00 + 8004918: 05fa0000 .word 0x05fa0000 + +0800491c <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 800491c: b480 push {r7} + 800491e: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8004920: 4b04 ldr r3, [pc, #16] ; (8004934 <__NVIC_GetPriorityGrouping+0x18>) + 8004922: 68db ldr r3, [r3, #12] + 8004924: 0a1b lsrs r3, r3, #8 + 8004926: f003 0307 and.w r3, r3, #7 +} + 800492a: 4618 mov r0, r3 + 800492c: 46bd mov sp, r7 + 800492e: f85d 7b04 ldr.w r7, [sp], #4 + 8004932: 4770 bx lr + 8004934: e000ed00 .word 0xe000ed00 + +08004938 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8004938: b480 push {r7} + 800493a: b083 sub sp, #12 + 800493c: af00 add r7, sp, #0 + 800493e: 4603 mov r3, r0 + 8004940: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8004942: f997 3007 ldrsb.w r3, [r7, #7] + 8004946: 2b00 cmp r3, #0 + 8004948: db0b blt.n 8004962 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800494a: 79fb ldrb r3, [r7, #7] + 800494c: f003 021f and.w r2, r3, #31 + 8004950: 4907 ldr r1, [pc, #28] ; (8004970 <__NVIC_EnableIRQ+0x38>) + 8004952: f997 3007 ldrsb.w r3, [r7, #7] + 8004956: 095b lsrs r3, r3, #5 + 8004958: 2001 movs r0, #1 + 800495a: fa00 f202 lsl.w r2, r0, r2 + 800495e: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8004962: bf00 nop + 8004964: 370c adds r7, #12 + 8004966: 46bd mov sp, r7 + 8004968: f85d 7b04 ldr.w r7, [sp], #4 + 800496c: 4770 bx lr + 800496e: bf00 nop + 8004970: e000e100 .word 0xe000e100 + +08004974 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8004974: b480 push {r7} + 8004976: b083 sub sp, #12 + 8004978: af00 add r7, sp, #0 + 800497a: 4603 mov r3, r0 + 800497c: 6039 str r1, [r7, #0] + 800497e: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8004980: f997 3007 ldrsb.w r3, [r7, #7] + 8004984: 2b00 cmp r3, #0 + 8004986: db0a blt.n 800499e <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8004988: 683b ldr r3, [r7, #0] + 800498a: b2da uxtb r2, r3 + 800498c: 490c ldr r1, [pc, #48] ; (80049c0 <__NVIC_SetPriority+0x4c>) + 800498e: f997 3007 ldrsb.w r3, [r7, #7] + 8004992: 0112 lsls r2, r2, #4 + 8004994: b2d2 uxtb r2, r2 + 8004996: 440b add r3, r1 + 8004998: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 800499c: e00a b.n 80049b4 <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 800499e: 683b ldr r3, [r7, #0] + 80049a0: b2da uxtb r2, r3 + 80049a2: 4908 ldr r1, [pc, #32] ; (80049c4 <__NVIC_SetPriority+0x50>) + 80049a4: 79fb ldrb r3, [r7, #7] + 80049a6: f003 030f and.w r3, r3, #15 + 80049aa: 3b04 subs r3, #4 + 80049ac: 0112 lsls r2, r2, #4 + 80049ae: b2d2 uxtb r2, r2 + 80049b0: 440b add r3, r1 + 80049b2: 761a strb r2, [r3, #24] +} + 80049b4: bf00 nop + 80049b6: 370c adds r7, #12 + 80049b8: 46bd mov sp, r7 + 80049ba: f85d 7b04 ldr.w r7, [sp], #4 + 80049be: 4770 bx lr + 80049c0: e000e100 .word 0xe000e100 + 80049c4: e000ed00 .word 0xe000ed00 + +080049c8 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80049c8: b480 push {r7} + 80049ca: b089 sub sp, #36 ; 0x24 + 80049cc: af00 add r7, sp, #0 + 80049ce: 60f8 str r0, [r7, #12] + 80049d0: 60b9 str r1, [r7, #8] + 80049d2: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80049d4: 68fb ldr r3, [r7, #12] + 80049d6: f003 0307 and.w r3, r3, #7 + 80049da: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80049dc: 69fb ldr r3, [r7, #28] + 80049de: f1c3 0307 rsb r3, r3, #7 + 80049e2: 2b04 cmp r3, #4 + 80049e4: bf28 it cs + 80049e6: 2304 movcs r3, #4 + 80049e8: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80049ea: 69fb ldr r3, [r7, #28] + 80049ec: 3304 adds r3, #4 + 80049ee: 2b06 cmp r3, #6 + 80049f0: d902 bls.n 80049f8 + 80049f2: 69fb ldr r3, [r7, #28] + 80049f4: 3b03 subs r3, #3 + 80049f6: e000 b.n 80049fa + 80049f8: 2300 movs r3, #0 + 80049fa: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80049fc: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8004a00: 69bb ldr r3, [r7, #24] + 8004a02: fa02 f303 lsl.w r3, r2, r3 + 8004a06: 43da mvns r2, r3 + 8004a08: 68bb ldr r3, [r7, #8] + 8004a0a: 401a ands r2, r3 + 8004a0c: 697b ldr r3, [r7, #20] + 8004a0e: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8004a10: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8004a14: 697b ldr r3, [r7, #20] + 8004a16: fa01 f303 lsl.w r3, r1, r3 + 8004a1a: 43d9 mvns r1, r3 + 8004a1c: 687b ldr r3, [r7, #4] + 8004a1e: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8004a20: 4313 orrs r3, r2 + ); +} + 8004a22: 4618 mov r0, r3 + 8004a24: 3724 adds r7, #36 ; 0x24 + 8004a26: 46bd mov sp, r7 + 8004a28: f85d 7b04 ldr.w r7, [sp], #4 + 8004a2c: 4770 bx lr + +08004a2e : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8004a2e: b580 push {r7, lr} + 8004a30: b082 sub sp, #8 + 8004a32: af00 add r7, sp, #0 + 8004a34: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8004a36: 6878 ldr r0, [r7, #4] + 8004a38: f7ff ff4c bl 80048d4 <__NVIC_SetPriorityGrouping> +} + 8004a3c: bf00 nop + 8004a3e: 3708 adds r7, #8 + 8004a40: 46bd mov sp, r7 + 8004a42: bd80 pop {r7, pc} + +08004a44 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8004a44: b580 push {r7, lr} + 8004a46: b086 sub sp, #24 + 8004a48: af00 add r7, sp, #0 + 8004a4a: 4603 mov r3, r0 + 8004a4c: 60b9 str r1, [r7, #8] + 8004a4e: 607a str r2, [r7, #4] + 8004a50: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8004a52: 2300 movs r3, #0 + 8004a54: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8004a56: f7ff ff61 bl 800491c <__NVIC_GetPriorityGrouping> + 8004a5a: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8004a5c: 687a ldr r2, [r7, #4] + 8004a5e: 68b9 ldr r1, [r7, #8] + 8004a60: 6978 ldr r0, [r7, #20] + 8004a62: f7ff ffb1 bl 80049c8 + 8004a66: 4602 mov r2, r0 + 8004a68: f997 300f ldrsb.w r3, [r7, #15] + 8004a6c: 4611 mov r1, r2 + 8004a6e: 4618 mov r0, r3 + 8004a70: f7ff ff80 bl 8004974 <__NVIC_SetPriority> +} + 8004a74: bf00 nop + 8004a76: 3718 adds r7, #24 + 8004a78: 46bd mov sp, r7 + 8004a7a: bd80 pop {r7, pc} + +08004a7c : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8004a7c: b580 push {r7, lr} + 8004a7e: b082 sub sp, #8 + 8004a80: af00 add r7, sp, #0 + 8004a82: 4603 mov r3, r0 + 8004a84: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8004a86: f997 3007 ldrsb.w r3, [r7, #7] + 8004a8a: 4618 mov r0, r3 + 8004a8c: f7ff ff54 bl 8004938 <__NVIC_EnableIRQ> +} + 8004a90: bf00 nop + 8004a92: 3708 adds r7, #8 + 8004a94: 46bd mov sp, r7 + 8004a96: bd80 pop {r7, pc} + +08004a98 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8004a98: b580 push {r7, lr} + 8004a9a: b086 sub sp, #24 + 8004a9c: af00 add r7, sp, #0 + 8004a9e: 6078 str r0, [r7, #4] + uint32_t tmp = 0U; + 8004aa0: 2300 movs r3, #0 + 8004aa2: 617b str r3, [r7, #20] + uint32_t tickstart = HAL_GetTick(); + 8004aa4: f7ff fee6 bl 8004874 + 8004aa8: 6138 str r0, [r7, #16] + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + 8004aaa: 687b ldr r3, [r7, #4] + 8004aac: 2b00 cmp r3, #0 + 8004aae: d101 bne.n 8004ab4 + { + return HAL_ERROR; + 8004ab0: 2301 movs r3, #1 + 8004ab2: e099 b.n 8004be8 + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8004ab4: 687b ldr r3, [r7, #4] + 8004ab6: 2202 movs r2, #2 + 8004ab8: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + 8004abc: 687b ldr r3, [r7, #4] + 8004abe: 2200 movs r2, #0 + 8004ac0: f883 2034 strb.w r2, [r3, #52] ; 0x34 + + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8004ac4: 687b ldr r3, [r7, #4] + 8004ac6: 681b ldr r3, [r3, #0] + 8004ac8: 681a ldr r2, [r3, #0] + 8004aca: 687b ldr r3, [r7, #4] + 8004acc: 681b ldr r3, [r3, #0] + 8004ace: f022 0201 bic.w r2, r2, #1 + 8004ad2: 601a str r2, [r3, #0] + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 8004ad4: e00f b.n 8004af6 + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 8004ad6: f7ff fecd bl 8004874 + 8004ada: 4602 mov r2, r0 + 8004adc: 693b ldr r3, [r7, #16] + 8004ade: 1ad3 subs r3, r2, r3 + 8004ae0: 2b05 cmp r3, #5 + 8004ae2: d908 bls.n 8004af6 + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 8004ae4: 687b ldr r3, [r7, #4] + 8004ae6: 2220 movs r2, #32 + 8004ae8: 655a str r2, [r3, #84] ; 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + 8004aea: 687b ldr r3, [r7, #4] + 8004aec: 2203 movs r2, #3 + 8004aee: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_TIMEOUT; + 8004af2: 2303 movs r3, #3 + 8004af4: e078 b.n 8004be8 + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 8004af6: 687b ldr r3, [r7, #4] + 8004af8: 681b ldr r3, [r3, #0] + 8004afa: 681b ldr r3, [r3, #0] + 8004afc: f003 0301 and.w r3, r3, #1 + 8004b00: 2b00 cmp r3, #0 + 8004b02: d1e8 bne.n 8004ad6 + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + 8004b04: 687b ldr r3, [r7, #4] + 8004b06: 681b ldr r3, [r3, #0] + 8004b08: 681b ldr r3, [r3, #0] + 8004b0a: 617b str r3, [r7, #20] + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + 8004b0c: 697a ldr r2, [r7, #20] + 8004b0e: 4b38 ldr r3, [pc, #224] ; (8004bf0 ) + 8004b10: 4013 ands r3, r2 + 8004b12: 617b str r3, [r7, #20] + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8004b14: 687b ldr r3, [r7, #4] + 8004b16: 685a ldr r2, [r3, #4] + 8004b18: 687b ldr r3, [r7, #4] + 8004b1a: 689b ldr r3, [r3, #8] + 8004b1c: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8004b1e: 687b ldr r3, [r7, #4] + 8004b20: 68db ldr r3, [r3, #12] + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8004b22: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8004b24: 687b ldr r3, [r7, #4] + 8004b26: 691b ldr r3, [r3, #16] + 8004b28: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8004b2a: 687b ldr r3, [r7, #4] + 8004b2c: 695b ldr r3, [r3, #20] + hdma->Init.PeriphInc | hdma->Init.MemInc | + 8004b2e: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8004b30: 687b ldr r3, [r7, #4] + 8004b32: 699b ldr r3, [r3, #24] + 8004b34: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8004b36: 687b ldr r3, [r7, #4] + 8004b38: 69db ldr r3, [r3, #28] + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8004b3a: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8004b3c: 687b ldr r3, [r7, #4] + 8004b3e: 6a1b ldr r3, [r3, #32] + 8004b40: 4313 orrs r3, r2 + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 8004b42: 697a ldr r2, [r7, #20] + 8004b44: 4313 orrs r3, r2 + 8004b46: 617b str r3, [r7, #20] + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 8004b48: 687b ldr r3, [r7, #4] + 8004b4a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004b4c: 2b04 cmp r3, #4 + 8004b4e: d107 bne.n 8004b60 + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + 8004b50: 687b ldr r3, [r7, #4] + 8004b52: 6ada ldr r2, [r3, #44] ; 0x2c + 8004b54: 687b ldr r3, [r7, #4] + 8004b56: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004b58: 4313 orrs r3, r2 + 8004b5a: 697a ldr r2, [r7, #20] + 8004b5c: 4313 orrs r3, r2 + 8004b5e: 617b str r3, [r7, #20] + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + 8004b60: 687b ldr r3, [r7, #4] + 8004b62: 681b ldr r3, [r3, #0] + 8004b64: 697a ldr r2, [r7, #20] + 8004b66: 601a str r2, [r3, #0] + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + 8004b68: 687b ldr r3, [r7, #4] + 8004b6a: 681b ldr r3, [r3, #0] + 8004b6c: 695b ldr r3, [r3, #20] + 8004b6e: 617b str r3, [r7, #20] + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + 8004b70: 697b ldr r3, [r7, #20] + 8004b72: f023 0307 bic.w r3, r3, #7 + 8004b76: 617b str r3, [r7, #20] + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + 8004b78: 687b ldr r3, [r7, #4] + 8004b7a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004b7c: 697a ldr r2, [r7, #20] + 8004b7e: 4313 orrs r3, r2 + 8004b80: 617b str r3, [r7, #20] + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 8004b82: 687b ldr r3, [r7, #4] + 8004b84: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004b86: 2b04 cmp r3, #4 + 8004b88: d117 bne.n 8004bba + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + 8004b8a: 687b ldr r3, [r7, #4] + 8004b8c: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004b8e: 697a ldr r2, [r7, #20] + 8004b90: 4313 orrs r3, r2 + 8004b92: 617b str r3, [r7, #20] + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + 8004b94: 687b ldr r3, [r7, #4] + 8004b96: 6adb ldr r3, [r3, #44] ; 0x2c + 8004b98: 2b00 cmp r3, #0 + 8004b9a: d00e beq.n 8004bba + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + 8004b9c: 6878 ldr r0, [r7, #4] + 8004b9e: f000 f8bd bl 8004d1c + 8004ba2: 4603 mov r3, r0 + 8004ba4: 2b00 cmp r3, #0 + 8004ba6: d008 beq.n 8004bba + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 8004ba8: 687b ldr r3, [r7, #4] + 8004baa: 2240 movs r2, #64 ; 0x40 + 8004bac: 655a str r2, [r3, #84] ; 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8004bae: 687b ldr r3, [r7, #4] + 8004bb0: 2201 movs r2, #1 + 8004bb2: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_ERROR; + 8004bb6: 2301 movs r3, #1 + 8004bb8: e016 b.n 8004be8 + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + 8004bba: 687b ldr r3, [r7, #4] + 8004bbc: 681b ldr r3, [r3, #0] + 8004bbe: 697a ldr r2, [r7, #20] + 8004bc0: 615a str r2, [r3, #20] + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 8004bc2: 6878 ldr r0, [r7, #4] + 8004bc4: f000 f874 bl 8004cb0 + 8004bc8: 4603 mov r3, r0 + 8004bca: 60fb str r3, [r7, #12] + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 8004bcc: 687b ldr r3, [r7, #4] + 8004bce: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004bd0: 223f movs r2, #63 ; 0x3f + 8004bd2: 409a lsls r2, r3 + 8004bd4: 68fb ldr r3, [r7, #12] + 8004bd6: 609a str r2, [r3, #8] + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8004bd8: 687b ldr r3, [r7, #4] + 8004bda: 2200 movs r2, #0 + 8004bdc: 655a str r2, [r3, #84] ; 0x54 + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8004bde: 687b ldr r3, [r7, #4] + 8004be0: 2201 movs r2, #1 + 8004be2: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_OK; + 8004be6: 2300 movs r3, #0 +} + 8004be8: 4618 mov r0, r3 + 8004bea: 3718 adds r7, #24 + 8004bec: 46bd mov sp, r7 + 8004bee: bd80 pop {r7, pc} + 8004bf0: f010803f .word 0xf010803f + +08004bf4 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + 8004bf4: b580 push {r7, lr} + 8004bf6: b084 sub sp, #16 + 8004bf8: af00 add r7, sp, #0 + 8004bfa: 6078 str r0, [r7, #4] + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + 8004bfc: 687b ldr r3, [r7, #4] + 8004bfe: 2b00 cmp r3, #0 + 8004c00: d101 bne.n 8004c06 + { + return HAL_ERROR; + 8004c02: 2301 movs r3, #1 + 8004c04: e050 b.n 8004ca8 + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + 8004c06: 687b ldr r3, [r7, #4] + 8004c08: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8004c0c: b2db uxtb r3, r3 + 8004c0e: 2b02 cmp r3, #2 + 8004c10: d101 bne.n 8004c16 + { + /* Return error status */ + return HAL_BUSY; + 8004c12: 2302 movs r3, #2 + 8004c14: e048 b.n 8004ca8 + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + 8004c16: 687b ldr r3, [r7, #4] + 8004c18: 681b ldr r3, [r3, #0] + 8004c1a: 681a ldr r2, [r3, #0] + 8004c1c: 687b ldr r3, [r7, #4] + 8004c1e: 681b ldr r3, [r3, #0] + 8004c20: f022 0201 bic.w r2, r2, #1 + 8004c24: 601a str r2, [r3, #0] + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + 8004c26: 687b ldr r3, [r7, #4] + 8004c28: 681b ldr r3, [r3, #0] + 8004c2a: 2200 movs r2, #0 + 8004c2c: 601a str r2, [r3, #0] + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + 8004c2e: 687b ldr r3, [r7, #4] + 8004c30: 681b ldr r3, [r3, #0] + 8004c32: 2200 movs r2, #0 + 8004c34: 605a str r2, [r3, #4] + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + 8004c36: 687b ldr r3, [r7, #4] + 8004c38: 681b ldr r3, [r3, #0] + 8004c3a: 2200 movs r2, #0 + 8004c3c: 609a str r2, [r3, #8] + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + 8004c3e: 687b ldr r3, [r7, #4] + 8004c40: 681b ldr r3, [r3, #0] + 8004c42: 2200 movs r2, #0 + 8004c44: 60da str r2, [r3, #12] + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + 8004c46: 687b ldr r3, [r7, #4] + 8004c48: 681b ldr r3, [r3, #0] + 8004c4a: 2200 movs r2, #0 + 8004c4c: 611a str r2, [r3, #16] + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021U; + 8004c4e: 687b ldr r3, [r7, #4] + 8004c50: 681b ldr r3, [r3, #0] + 8004c52: 2221 movs r2, #33 ; 0x21 + 8004c54: 615a str r2, [r3, #20] + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 8004c56: 6878 ldr r0, [r7, #4] + 8004c58: f000 f82a bl 8004cb0 + 8004c5c: 4603 mov r3, r0 + 8004c5e: 60fb str r3, [r7, #12] + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 8004c60: 687b ldr r3, [r7, #4] + 8004c62: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004c64: 223f movs r2, #63 ; 0x3f + 8004c66: 409a lsls r2, r3 + 8004c68: 68fb ldr r3, [r7, #12] + 8004c6a: 609a str r2, [r3, #8] + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + 8004c6c: 687b ldr r3, [r7, #4] + 8004c6e: 2200 movs r2, #0 + 8004c70: 63da str r2, [r3, #60] ; 0x3c + hdma->XferHalfCpltCallback = NULL; + 8004c72: 687b ldr r3, [r7, #4] + 8004c74: 2200 movs r2, #0 + 8004c76: 641a str r2, [r3, #64] ; 0x40 + hdma->XferM1CpltCallback = NULL; + 8004c78: 687b ldr r3, [r7, #4] + 8004c7a: 2200 movs r2, #0 + 8004c7c: 645a str r2, [r3, #68] ; 0x44 + hdma->XferM1HalfCpltCallback = NULL; + 8004c7e: 687b ldr r3, [r7, #4] + 8004c80: 2200 movs r2, #0 + 8004c82: 649a str r2, [r3, #72] ; 0x48 + hdma->XferErrorCallback = NULL; + 8004c84: 687b ldr r3, [r7, #4] + 8004c86: 2200 movs r2, #0 + 8004c88: 64da str r2, [r3, #76] ; 0x4c + hdma->XferAbortCallback = NULL; + 8004c8a: 687b ldr r3, [r7, #4] + 8004c8c: 2200 movs r2, #0 + 8004c8e: 651a str r2, [r3, #80] ; 0x50 + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8004c90: 687b ldr r3, [r7, #4] + 8004c92: 2200 movs r2, #0 + 8004c94: 655a str r2, [r3, #84] ; 0x54 + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + 8004c96: 687b ldr r3, [r7, #4] + 8004c98: 2200 movs r2, #0 + 8004c9a: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8004c9e: 687b ldr r3, [r7, #4] + 8004ca0: 2200 movs r2, #0 + 8004ca2: f883 2034 strb.w r2, [r3, #52] ; 0x34 + + return HAL_OK; + 8004ca6: 2300 movs r3, #0 +} + 8004ca8: 4618 mov r0, r3 + 8004caa: 3710 adds r7, #16 + 8004cac: 46bd mov sp, r7 + 8004cae: bd80 pop {r7, pc} + +08004cb0 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + 8004cb0: b480 push {r7} + 8004cb2: b085 sub sp, #20 + 8004cb4: af00 add r7, sp, #0 + 8004cb6: 6078 str r0, [r7, #4] + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + 8004cb8: 687b ldr r3, [r7, #4] + 8004cba: 681b ldr r3, [r3, #0] + 8004cbc: b2db uxtb r3, r3 + 8004cbe: 3b10 subs r3, #16 + 8004cc0: 4a13 ldr r2, [pc, #76] ; (8004d10 ) + 8004cc2: fba2 2303 umull r2, r3, r2, r3 + 8004cc6: 091b lsrs r3, r3, #4 + 8004cc8: 60fb str r3, [r7, #12] + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + 8004cca: 4a12 ldr r2, [pc, #72] ; (8004d14 ) + 8004ccc: 68fb ldr r3, [r7, #12] + 8004cce: 4413 add r3, r2 + 8004cd0: 781b ldrb r3, [r3, #0] + 8004cd2: 461a mov r2, r3 + 8004cd4: 687b ldr r3, [r7, #4] + 8004cd6: 65da str r2, [r3, #92] ; 0x5c + + if (stream_number > 3U) + 8004cd8: 68fb ldr r3, [r7, #12] + 8004cda: 2b03 cmp r3, #3 + 8004cdc: d908 bls.n 8004cf0 + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + 8004cde: 687b ldr r3, [r7, #4] + 8004ce0: 681b ldr r3, [r3, #0] + 8004ce2: 461a mov r2, r3 + 8004ce4: 4b0c ldr r3, [pc, #48] ; (8004d18 ) + 8004ce6: 4013 ands r3, r2 + 8004ce8: 1d1a adds r2, r3, #4 + 8004cea: 687b ldr r3, [r7, #4] + 8004cec: 659a str r2, [r3, #88] ; 0x58 + 8004cee: e006 b.n 8004cfe + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + 8004cf0: 687b ldr r3, [r7, #4] + 8004cf2: 681b ldr r3, [r3, #0] + 8004cf4: 461a mov r2, r3 + 8004cf6: 4b08 ldr r3, [pc, #32] ; (8004d18 ) + 8004cf8: 4013 ands r3, r2 + 8004cfa: 687a ldr r2, [r7, #4] + 8004cfc: 6593 str r3, [r2, #88] ; 0x58 + } + + return hdma->StreamBaseAddress; + 8004cfe: 687b ldr r3, [r7, #4] + 8004d00: 6d9b ldr r3, [r3, #88] ; 0x58 +} + 8004d02: 4618 mov r0, r3 + 8004d04: 3714 adds r7, #20 + 8004d06: 46bd mov sp, r7 + 8004d08: f85d 7b04 ldr.w r7, [sp], #4 + 8004d0c: 4770 bx lr + 8004d0e: bf00 nop + 8004d10: aaaaaaab .word 0xaaaaaaab + 8004d14: 080237c8 .word 0x080237c8 + 8004d18: fffffc00 .word 0xfffffc00 + +08004d1c : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + 8004d1c: b480 push {r7} + 8004d1e: b085 sub sp, #20 + 8004d20: af00 add r7, sp, #0 + 8004d22: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8004d24: 2300 movs r3, #0 + 8004d26: 73fb strb r3, [r7, #15] + uint32_t tmp = hdma->Init.FIFOThreshold; + 8004d28: 687b ldr r3, [r7, #4] + 8004d2a: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004d2c: 60bb str r3, [r7, #8] + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + 8004d2e: 687b ldr r3, [r7, #4] + 8004d30: 699b ldr r3, [r3, #24] + 8004d32: 2b00 cmp r3, #0 + 8004d34: d11f bne.n 8004d76 + { + switch (tmp) + 8004d36: 68bb ldr r3, [r7, #8] + 8004d38: 2b03 cmp r3, #3 + 8004d3a: d856 bhi.n 8004dea + 8004d3c: a201 add r2, pc, #4 ; (adr r2, 8004d44 ) + 8004d3e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004d42: bf00 nop + 8004d44: 08004d55 .word 0x08004d55 + 8004d48: 08004d67 .word 0x08004d67 + 8004d4c: 08004d55 .word 0x08004d55 + 8004d50: 08004deb .word 0x08004deb + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8004d54: 687b ldr r3, [r7, #4] + 8004d56: 6adb ldr r3, [r3, #44] ; 0x2c + 8004d58: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8004d5c: 2b00 cmp r3, #0 + 8004d5e: d046 beq.n 8004dee + { + status = HAL_ERROR; + 8004d60: 2301 movs r3, #1 + 8004d62: 73fb strb r3, [r7, #15] + } + break; + 8004d64: e043 b.n 8004dee + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 8004d66: 687b ldr r3, [r7, #4] + 8004d68: 6adb ldr r3, [r3, #44] ; 0x2c + 8004d6a: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 + 8004d6e: d140 bne.n 8004df2 + { + status = HAL_ERROR; + 8004d70: 2301 movs r3, #1 + 8004d72: 73fb strb r3, [r7, #15] + } + break; + 8004d74: e03d b.n 8004df2 + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 8004d76: 687b ldr r3, [r7, #4] + 8004d78: 699b ldr r3, [r3, #24] + 8004d7a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8004d7e: d121 bne.n 8004dc4 + { + switch (tmp) + 8004d80: 68bb ldr r3, [r7, #8] + 8004d82: 2b03 cmp r3, #3 + 8004d84: d837 bhi.n 8004df6 + 8004d86: a201 add r2, pc, #4 ; (adr r2, 8004d8c ) + 8004d88: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004d8c: 08004d9d .word 0x08004d9d + 8004d90: 08004da3 .word 0x08004da3 + 8004d94: 08004d9d .word 0x08004d9d + 8004d98: 08004db5 .word 0x08004db5 + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + 8004d9c: 2301 movs r3, #1 + 8004d9e: 73fb strb r3, [r7, #15] + break; + 8004da0: e030 b.n 8004e04 + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8004da2: 687b ldr r3, [r7, #4] + 8004da4: 6adb ldr r3, [r3, #44] ; 0x2c + 8004da6: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8004daa: 2b00 cmp r3, #0 + 8004dac: d025 beq.n 8004dfa + { + status = HAL_ERROR; + 8004dae: 2301 movs r3, #1 + 8004db0: 73fb strb r3, [r7, #15] + } + break; + 8004db2: e022 b.n 8004dfa + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 8004db4: 687b ldr r3, [r7, #4] + 8004db6: 6adb ldr r3, [r3, #44] ; 0x2c + 8004db8: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 + 8004dbc: d11f bne.n 8004dfe + { + status = HAL_ERROR; + 8004dbe: 2301 movs r3, #1 + 8004dc0: 73fb strb r3, [r7, #15] + } + break; + 8004dc2: e01c b.n 8004dfe + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + 8004dc4: 68bb ldr r3, [r7, #8] + 8004dc6: 2b02 cmp r3, #2 + 8004dc8: d903 bls.n 8004dd2 + 8004dca: 68bb ldr r3, [r7, #8] + 8004dcc: 2b03 cmp r3, #3 + 8004dce: d003 beq.n 8004dd8 + { + status = HAL_ERROR; + } + break; + default: + break; + 8004dd0: e018 b.n 8004e04 + status = HAL_ERROR; + 8004dd2: 2301 movs r3, #1 + 8004dd4: 73fb strb r3, [r7, #15] + break; + 8004dd6: e015 b.n 8004e04 + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 8004dd8: 687b ldr r3, [r7, #4] + 8004dda: 6adb ldr r3, [r3, #44] ; 0x2c + 8004ddc: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8004de0: 2b00 cmp r3, #0 + 8004de2: d00e beq.n 8004e02 + status = HAL_ERROR; + 8004de4: 2301 movs r3, #1 + 8004de6: 73fb strb r3, [r7, #15] + break; + 8004de8: e00b b.n 8004e02 + break; + 8004dea: bf00 nop + 8004dec: e00a b.n 8004e04 + break; + 8004dee: bf00 nop + 8004df0: e008 b.n 8004e04 + break; + 8004df2: bf00 nop + 8004df4: e006 b.n 8004e04 + break; + 8004df6: bf00 nop + 8004df8: e004 b.n 8004e04 + break; + 8004dfa: bf00 nop + 8004dfc: e002 b.n 8004e04 + break; + 8004dfe: bf00 nop + 8004e00: e000 b.n 8004e04 + break; + 8004e02: bf00 nop + } + } + + return status; + 8004e04: 7bfb ldrb r3, [r7, #15] +} + 8004e06: 4618 mov r0, r3 + 8004e08: 3714 adds r7, #20 + 8004e0a: 46bd mov sp, r7 + 8004e0c: f85d 7b04 ldr.w r7, [sp], #4 + 8004e10: 4770 bx lr + 8004e12: bf00 nop + +08004e14 : + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) +{ + 8004e14: b580 push {r7, lr} + 8004e16: b082 sub sp, #8 + 8004e18: af00 add r7, sp, #0 + 8004e1a: 6078 str r0, [r7, #4] + /* Check the DMA2D peripheral state */ + if (hdma2d == NULL) + 8004e1c: 687b ldr r3, [r7, #4] + 8004e1e: 2b00 cmp r3, #0 + 8004e20: d101 bne.n 8004e26 + { + return HAL_ERROR; + 8004e22: 2301 movs r3, #1 + 8004e24: e039 b.n 8004e9a + + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + 8004e26: 687b ldr r3, [r7, #4] + 8004e28: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 8004e2c: b2db uxtb r3, r3 + 8004e2e: 2b00 cmp r3, #0 + 8004e30: d106 bne.n 8004e40 + { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; + 8004e32: 687b ldr r3, [r7, #4] + 8004e34: 2200 movs r2, #0 + 8004e36: f883 2038 strb.w r2, [r3, #56] ; 0x38 + /* Init the low level hardware */ + HAL_DMA2D_MspInit(hdma2d); + 8004e3a: 6878 ldr r0, [r7, #4] + 8004e3c: f7fd ff7c bl 8002d38 + } +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 8004e40: 687b ldr r3, [r7, #4] + 8004e42: 2202 movs r2, #2 + 8004e44: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); + 8004e48: 687b ldr r3, [r7, #4] + 8004e4a: 681b ldr r3, [r3, #0] + 8004e4c: 681b ldr r3, [r3, #0] + 8004e4e: f423 3140 bic.w r1, r3, #196608 ; 0x30000 + 8004e52: 687b ldr r3, [r7, #4] + 8004e54: 685a ldr r2, [r3, #4] + 8004e56: 687b ldr r3, [r7, #4] + 8004e58: 681b ldr r3, [r3, #0] + 8004e5a: 430a orrs r2, r1 + 8004e5c: 601a str r2, [r3, #0] + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); + 8004e5e: 687b ldr r3, [r7, #4] + 8004e60: 681b ldr r3, [r3, #0] + 8004e62: 6b5b ldr r3, [r3, #52] ; 0x34 + 8004e64: f023 0107 bic.w r1, r3, #7 + 8004e68: 687b ldr r3, [r7, #4] + 8004e6a: 689a ldr r2, [r3, #8] + 8004e6c: 687b ldr r3, [r7, #4] + 8004e6e: 681b ldr r3, [r3, #0] + 8004e70: 430a orrs r2, r1 + 8004e72: 635a str r2, [r3, #52] ; 0x34 + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + 8004e74: 687b ldr r3, [r7, #4] + 8004e76: 681b ldr r3, [r3, #0] + 8004e78: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004e7a: 4b0a ldr r3, [pc, #40] ; (8004ea4 ) + 8004e7c: 4013 ands r3, r2 + 8004e7e: 687a ldr r2, [r7, #4] + 8004e80: 68d1 ldr r1, [r2, #12] + 8004e82: 687a ldr r2, [r7, #4] + 8004e84: 6812 ldr r2, [r2, #0] + 8004e86: 430b orrs r3, r1 + 8004e88: 6413 str r3, [r2, #64] ; 0x40 + (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + 8004e8a: 687b ldr r3, [r7, #4] + 8004e8c: 2200 movs r2, #0 + 8004e8e: 63da str r2, [r3, #60] ; 0x3c + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + 8004e90: 687b ldr r3, [r7, #4] + 8004e92: 2201 movs r2, #1 + 8004e94: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + return HAL_OK; + 8004e98: 2300 movs r3, #0 +} + 8004e9a: 4618 mov r0, r3 + 8004e9c: 3708 adds r7, #8 + 8004e9e: 46bd mov sp, r7 + 8004ea0: bd80 pop {r7, pc} + 8004ea2: bf00 nop + 8004ea4: ffffc000 .word 0xffffc000 + +08004ea8 : + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) +{ + 8004ea8: b580 push {r7, lr} + 8004eaa: b086 sub sp, #24 + 8004eac: af02 add r7, sp, #8 + 8004eae: 60f8 str r0, [r7, #12] + 8004eb0: 60b9 str r1, [r7, #8] + 8004eb2: 607a str r2, [r7, #4] + 8004eb4: 603b str r3, [r7, #0] + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + 8004eb6: 68fb ldr r3, [r7, #12] + 8004eb8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 8004ebc: 2b01 cmp r3, #1 + 8004ebe: d101 bne.n 8004ec4 + 8004ec0: 2302 movs r3, #2 + 8004ec2: e018 b.n 8004ef6 + 8004ec4: 68fb ldr r3, [r7, #12] + 8004ec6: 2201 movs r2, #1 + 8004ec8: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 8004ecc: 68fb ldr r3, [r7, #12] + 8004ece: 2202 movs r2, #2 + 8004ed0: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + 8004ed4: 69bb ldr r3, [r7, #24] + 8004ed6: 9300 str r3, [sp, #0] + 8004ed8: 683b ldr r3, [r7, #0] + 8004eda: 687a ldr r2, [r7, #4] + 8004edc: 68b9 ldr r1, [r7, #8] + 8004ede: 68f8 ldr r0, [r7, #12] + 8004ee0: f000 f988 bl 80051f4 + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + 8004ee4: 68fb ldr r3, [r7, #12] + 8004ee6: 681b ldr r3, [r3, #0] + 8004ee8: 681a ldr r2, [r3, #0] + 8004eea: 68fb ldr r3, [r7, #12] + 8004eec: 681b ldr r3, [r3, #0] + 8004eee: f042 0201 orr.w r2, r2, #1 + 8004ef2: 601a str r2, [r3, #0] + + return HAL_OK; + 8004ef4: 2300 movs r3, #0 +} + 8004ef6: 4618 mov r0, r3 + 8004ef8: 3710 adds r7, #16 + 8004efa: 46bd mov sp, r7 + 8004efc: bd80 pop {r7, pc} + +08004efe : + * the configuration information for the DMA2D. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + 8004efe: b580 push {r7, lr} + 8004f00: b086 sub sp, #24 + 8004f02: af00 add r7, sp, #0 + 8004f04: 6078 str r0, [r7, #4] + 8004f06: 6039 str r1, [r7, #0] + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; + 8004f08: 2300 movs r3, #0 + 8004f0a: 60fb str r3, [r7, #12] + + /* Polling for DMA2D transfer */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + 8004f0c: 687b ldr r3, [r7, #4] + 8004f0e: 681b ldr r3, [r3, #0] + 8004f10: 681b ldr r3, [r3, #0] + 8004f12: f003 0301 and.w r3, r3, #1 + 8004f16: 2b00 cmp r3, #0 + 8004f18: d056 beq.n 8004fc8 + { + /* Get tick */ + tickstart = HAL_GetTick(); + 8004f1a: f7ff fcab bl 8004874 + 8004f1e: 6178 str r0, [r7, #20] + + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + 8004f20: e04b b.n 8004fba + { + isrflags = READ_REG(hdma2d->Instance->ISR); + 8004f22: 687b ldr r3, [r7, #4] + 8004f24: 681b ldr r3, [r3, #0] + 8004f26: 685b ldr r3, [r3, #4] + 8004f28: 60fb str r3, [r7, #12] + if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) + 8004f2a: 68fb ldr r3, [r7, #12] + 8004f2c: f003 0321 and.w r3, r3, #33 ; 0x21 + 8004f30: 2b00 cmp r3, #0 + 8004f32: d023 beq.n 8004f7c + { + if ((isrflags & DMA2D_FLAG_CE) != 0U) + 8004f34: 68fb ldr r3, [r7, #12] + 8004f36: f003 0320 and.w r3, r3, #32 + 8004f3a: 2b00 cmp r3, #0 + 8004f3c: d005 beq.n 8004f4a + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + 8004f3e: 687b ldr r3, [r7, #4] + 8004f40: 6bdb ldr r3, [r3, #60] ; 0x3c + 8004f42: f043 0202 orr.w r2, r3, #2 + 8004f46: 687b ldr r3, [r7, #4] + 8004f48: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + 8004f4a: 68fb ldr r3, [r7, #12] + 8004f4c: f003 0301 and.w r3, r3, #1 + 8004f50: 2b00 cmp r3, #0 + 8004f52: d005 beq.n 8004f60 + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + 8004f54: 687b ldr r3, [r7, #4] + 8004f56: 6bdb ldr r3, [r3, #60] ; 0x3c + 8004f58: f043 0201 orr.w r2, r3, #1 + 8004f5c: 687b ldr r3, [r7, #4] + 8004f5e: 63da str r2, [r3, #60] ; 0x3c + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + 8004f60: 687b ldr r3, [r7, #4] + 8004f62: 681b ldr r3, [r3, #0] + 8004f64: 2221 movs r2, #33 ; 0x21 + 8004f66: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + 8004f68: 687b ldr r3, [r7, #4] + 8004f6a: 2204 movs r2, #4 + 8004f6c: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8004f70: 687b ldr r3, [r7, #4] + 8004f72: 2200 movs r2, #0 + 8004f74: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_ERROR; + 8004f78: 2301 movs r3, #1 + 8004f7a: e0a5 b.n 80050c8 + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004f7c: 683b ldr r3, [r7, #0] + 8004f7e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8004f82: d01a beq.n 8004fba + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 8004f84: f7ff fc76 bl 8004874 + 8004f88: 4602 mov r2, r0 + 8004f8a: 697b ldr r3, [r7, #20] + 8004f8c: 1ad3 subs r3, r2, r3 + 8004f8e: 683a ldr r2, [r7, #0] + 8004f90: 429a cmp r2, r3 + 8004f92: d302 bcc.n 8004f9a + 8004f94: 683b ldr r3, [r7, #0] + 8004f96: 2b00 cmp r3, #0 + 8004f98: d10f bne.n 8004fba + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + 8004f9a: 687b ldr r3, [r7, #4] + 8004f9c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8004f9e: f043 0220 orr.w r2, r3, #32 + 8004fa2: 687b ldr r3, [r7, #4] + 8004fa4: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + 8004fa6: 687b ldr r3, [r7, #4] + 8004fa8: 2203 movs r2, #3 + 8004faa: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8004fae: 687b ldr r3, [r7, #4] + 8004fb0: 2200 movs r2, #0 + 8004fb2: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 8004fb6: 2303 movs r3, #3 + 8004fb8: e086 b.n 80050c8 + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + 8004fba: 687b ldr r3, [r7, #4] + 8004fbc: 681b ldr r3, [r3, #0] + 8004fbe: 685b ldr r3, [r3, #4] + 8004fc0: f003 0302 and.w r3, r3, #2 + 8004fc4: 2b00 cmp r3, #0 + 8004fc6: d0ac beq.n 8004f22 + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + 8004fc8: 687b ldr r3, [r7, #4] + 8004fca: 681b ldr r3, [r3, #0] + 8004fcc: 69db ldr r3, [r3, #28] + 8004fce: f003 0320 and.w r3, r3, #32 + 8004fd2: 613b str r3, [r7, #16] + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + 8004fd4: 687b ldr r3, [r7, #4] + 8004fd6: 681b ldr r3, [r3, #0] + 8004fd8: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004fda: f003 0320 and.w r3, r3, #32 + 8004fde: 693a ldr r2, [r7, #16] + 8004fe0: 4313 orrs r3, r2 + 8004fe2: 613b str r3, [r7, #16] + if (layer_start != 0U) + 8004fe4: 693b ldr r3, [r7, #16] + 8004fe6: 2b00 cmp r3, #0 + 8004fe8: d061 beq.n 80050ae + { + /* Get tick */ + tickstart = HAL_GetTick(); + 8004fea: f7ff fc43 bl 8004874 + 8004fee: 6178 str r0, [r7, #20] + + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + 8004ff0: e056 b.n 80050a0 + { + isrflags = READ_REG(hdma2d->Instance->ISR); + 8004ff2: 687b ldr r3, [r7, #4] + 8004ff4: 681b ldr r3, [r3, #0] + 8004ff6: 685b ldr r3, [r3, #4] + 8004ff8: 60fb str r3, [r7, #12] + if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) + 8004ffa: 68fb ldr r3, [r7, #12] + 8004ffc: f003 0329 and.w r3, r3, #41 ; 0x29 + 8005000: 2b00 cmp r3, #0 + 8005002: d02e beq.n 8005062 + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + 8005004: 68fb ldr r3, [r7, #12] + 8005006: f003 0308 and.w r3, r3, #8 + 800500a: 2b00 cmp r3, #0 + 800500c: d005 beq.n 800501a + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + 800500e: 687b ldr r3, [r7, #4] + 8005010: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005012: f043 0204 orr.w r2, r3, #4 + 8005016: 687b ldr r3, [r7, #4] + 8005018: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_CE) != 0U) + 800501a: 68fb ldr r3, [r7, #12] + 800501c: f003 0320 and.w r3, r3, #32 + 8005020: 2b00 cmp r3, #0 + 8005022: d005 beq.n 8005030 + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + 8005024: 687b ldr r3, [r7, #4] + 8005026: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005028: f043 0202 orr.w r2, r3, #2 + 800502c: 687b ldr r3, [r7, #4] + 800502e: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + 8005030: 68fb ldr r3, [r7, #12] + 8005032: f003 0301 and.w r3, r3, #1 + 8005036: 2b00 cmp r3, #0 + 8005038: d005 beq.n 8005046 + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + 800503a: 687b ldr r3, [r7, #4] + 800503c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800503e: f043 0201 orr.w r2, r3, #1 + 8005042: 687b ldr r3, [r7, #4] + 8005044: 63da str r2, [r3, #60] ; 0x3c + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + 8005046: 687b ldr r3, [r7, #4] + 8005048: 681b ldr r3, [r3, #0] + 800504a: 2229 movs r2, #41 ; 0x29 + 800504c: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + 800504e: 687b ldr r3, [r7, #4] + 8005050: 2204 movs r2, #4 + 8005052: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005056: 687b ldr r3, [r7, #4] + 8005058: 2200 movs r2, #0 + 800505a: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_ERROR; + 800505e: 2301 movs r3, #1 + 8005060: e032 b.n 80050c8 + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8005062: 683b ldr r3, [r7, #0] + 8005064: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8005068: d01a beq.n 80050a0 + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 800506a: f7ff fc03 bl 8004874 + 800506e: 4602 mov r2, r0 + 8005070: 697b ldr r3, [r7, #20] + 8005072: 1ad3 subs r3, r2, r3 + 8005074: 683a ldr r2, [r7, #0] + 8005076: 429a cmp r2, r3 + 8005078: d302 bcc.n 8005080 + 800507a: 683b ldr r3, [r7, #0] + 800507c: 2b00 cmp r3, #0 + 800507e: d10f bne.n 80050a0 + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + 8005080: 687b ldr r3, [r7, #4] + 8005082: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005084: f043 0220 orr.w r2, r3, #32 + 8005088: 687b ldr r3, [r7, #4] + 800508a: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + 800508c: 687b ldr r3, [r7, #4] + 800508e: 2203 movs r2, #3 + 8005090: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005094: 687b ldr r3, [r7, #4] + 8005096: 2200 movs r2, #0 + 8005098: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 800509c: 2303 movs r3, #3 + 800509e: e013 b.n 80050c8 + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + 80050a0: 687b ldr r3, [r7, #4] + 80050a2: 681b ldr r3, [r3, #0] + 80050a4: 685b ldr r3, [r3, #4] + 80050a6: f003 0310 and.w r3, r3, #16 + 80050aa: 2b00 cmp r3, #0 + 80050ac: d0a1 beq.n 8004ff2 + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); + 80050ae: 687b ldr r3, [r7, #4] + 80050b0: 681b ldr r3, [r3, #0] + 80050b2: 2212 movs r2, #18 + 80050b4: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + 80050b6: 687b ldr r3, [r7, #4] + 80050b8: 2201 movs r2, #1 + 80050ba: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 80050be: 687b ldr r3, [r7, #4] + 80050c0: 2200 movs r2, #0 + 80050c2: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_OK; + 80050c6: 2300 movs r3, #0 +} + 80050c8: 4618 mov r0, r3 + 80050ca: 3718 adds r7, #24 + 80050cc: 46bd mov sp, r7 + 80050ce: bd80 pop {r7, pc} + +080050d0 : + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + 80050d0: b480 push {r7} + 80050d2: b087 sub sp, #28 + 80050d4: af00 add r7, sp, #0 + 80050d6: 6078 str r0, [r7, #4] + 80050d8: 6039 str r1, [r7, #0] + uint32_t regValue; + + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); + if (hdma2d->Init.Mode != DMA2D_R2M) + 80050da: 687b ldr r3, [r7, #4] + 80050dc: 685b ldr r3, [r3, #4] + 80050de: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* Process locked */ + __HAL_LOCK(hdma2d); + 80050e2: 687b ldr r3, [r7, #4] + 80050e4: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 80050e8: 2b01 cmp r3, #1 + 80050ea: d101 bne.n 80050f0 + 80050ec: 2302 movs r3, #2 + 80050ee: e079 b.n 80051e4 + 80050f0: 687b ldr r3, [r7, #4] + 80050f2: 2201 movs r2, #1 + 80050f4: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 80050f8: 687b ldr r3, [r7, #4] + 80050fa: 2202 movs r2, #2 + 80050fc: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + 8005100: 683b ldr r3, [r7, #0] + 8005102: 011b lsls r3, r3, #4 + 8005104: 3318 adds r3, #24 + 8005106: 687a ldr r2, [r7, #4] + 8005108: 4413 add r3, r2 + 800510a: 613b str r3, [r7, #16] +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); +#else + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); + 800510c: 693b ldr r3, [r7, #16] + 800510e: 685a ldr r2, [r3, #4] + 8005110: 693b ldr r3, [r7, #16] + 8005112: 689b ldr r3, [r3, #8] + 8005114: 041b lsls r3, r3, #16 + 8005116: 4313 orrs r3, r2 + 8005118: 617b str r3, [r7, #20] + regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; + 800511a: 4b35 ldr r3, [pc, #212] ; (80051f0 ) + 800511c: 60fb str r3, [r7, #12] +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 800511e: 693b ldr r3, [r7, #16] + 8005120: 685b ldr r3, [r3, #4] + 8005122: 2b0a cmp r3, #10 + 8005124: d003 beq.n 800512e + 8005126: 693b ldr r3, [r7, #16] + 8005128: 685b ldr r3, [r3, #4] + 800512a: 2b09 cmp r3, #9 + 800512c: d107 bne.n 800513e + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + 800512e: 693b ldr r3, [r7, #16] + 8005130: 68db ldr r3, [r3, #12] + 8005132: f003 437f and.w r3, r3, #4278190080 ; 0xff000000 + 8005136: 697a ldr r2, [r7, #20] + 8005138: 4313 orrs r3, r2 + 800513a: 617b str r3, [r7, #20] + 800513c: e005 b.n 800514a + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + 800513e: 693b ldr r3, [r7, #16] + 8005140: 68db ldr r3, [r3, #12] + 8005142: 061b lsls r3, r3, #24 + 8005144: 697a ldr r2, [r7, #20] + 8005146: 4313 orrs r3, r2 + 8005148: 617b str r3, [r7, #20] + } + + /* Configure the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + 800514a: 683b ldr r3, [r7, #0] + 800514c: 2b00 cmp r3, #0 + 800514e: d120 bne.n 8005192 + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + 8005150: 687b ldr r3, [r7, #4] + 8005152: 681b ldr r3, [r3, #0] + 8005154: 6a5a ldr r2, [r3, #36] ; 0x24 + 8005156: 68fb ldr r3, [r7, #12] + 8005158: 43db mvns r3, r3 + 800515a: ea02 0103 and.w r1, r2, r3 + 800515e: 687b ldr r3, [r7, #4] + 8005160: 681b ldr r3, [r3, #0] + 8005162: 697a ldr r2, [r7, #20] + 8005164: 430a orrs r2, r1 + 8005166: 625a str r2, [r3, #36] ; 0x24 + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + 8005168: 687b ldr r3, [r7, #4] + 800516a: 681b ldr r3, [r3, #0] + 800516c: 693a ldr r2, [r7, #16] + 800516e: 6812 ldr r2, [r2, #0] + 8005170: 619a str r2, [r3, #24] + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 8005172: 693b ldr r3, [r7, #16] + 8005174: 685b ldr r3, [r3, #4] + 8005176: 2b0a cmp r3, #10 + 8005178: d003 beq.n 8005182 + 800517a: 693b ldr r3, [r7, #16] + 800517c: 685b ldr r3, [r3, #4] + 800517e: 2b09 cmp r3, #9 + 8005180: d127 bne.n 80051d2 + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ + 8005182: 693b ldr r3, [r7, #16] + 8005184: 68da ldr r2, [r3, #12] + 8005186: 687b ldr r3, [r7, #4] + 8005188: 681b ldr r3, [r3, #0] + 800518a: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + 800518e: 629a str r2, [r3, #40] ; 0x28 + 8005190: e01f b.n 80051d2 + else + { + + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + 8005192: 687b ldr r3, [r7, #4] + 8005194: 681b ldr r3, [r3, #0] + 8005196: 69da ldr r2, [r3, #28] + 8005198: 68fb ldr r3, [r7, #12] + 800519a: 43db mvns r3, r3 + 800519c: ea02 0103 and.w r1, r2, r3 + 80051a0: 687b ldr r3, [r7, #4] + 80051a2: 681b ldr r3, [r3, #0] + 80051a4: 697a ldr r2, [r7, #20] + 80051a6: 430a orrs r2, r1 + 80051a8: 61da str r2, [r3, #28] + + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + 80051aa: 687b ldr r3, [r7, #4] + 80051ac: 681b ldr r3, [r3, #0] + 80051ae: 693a ldr r2, [r7, #16] + 80051b0: 6812 ldr r2, [r2, #0] + 80051b2: 611a str r2, [r3, #16] + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 80051b4: 693b ldr r3, [r7, #16] + 80051b6: 685b ldr r3, [r3, #4] + 80051b8: 2b0a cmp r3, #10 + 80051ba: d003 beq.n 80051c4 + 80051bc: 693b ldr r3, [r7, #16] + 80051be: 685b ldr r3, [r3, #4] + 80051c0: 2b09 cmp r3, #9 + 80051c2: d106 bne.n 80051d2 + { + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ + 80051c4: 693b ldr r3, [r7, #16] + 80051c6: 68da ldr r2, [r3, #12] + 80051c8: 687b ldr r3, [r7, #4] + 80051ca: 681b ldr r3, [r3, #0] + 80051cc: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + 80051d0: 621a str r2, [r3, #32] + DMA2D_FGCOLR_RED)); + } + } + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + 80051d2: 687b ldr r3, [r7, #4] + 80051d4: 2201 movs r2, #1 + 80051d6: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 80051da: 687b ldr r3, [r7, #4] + 80051dc: 2200 movs r2, #0 + 80051de: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_OK; + 80051e2: 2300 movs r3, #0 +} + 80051e4: 4618 mov r0, r3 + 80051e6: 371c adds r7, #28 + 80051e8: 46bd mov sp, r7 + 80051ea: f85d 7b04 ldr.w r7, [sp], #4 + 80051ee: 4770 bx lr + 80051f0: ff03000f .word 0xff03000f + +080051f4 : + * @param Height The height of data to be transferred from source to destination. + * @retval HAL status + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) +{ + 80051f4: b480 push {r7} + 80051f6: b08b sub sp, #44 ; 0x2c + 80051f8: af00 add r7, sp, #0 + 80051fa: 60f8 str r0, [r7, #12] + 80051fc: 60b9 str r1, [r7, #8] + 80051fe: 607a str r2, [r7, #4] + 8005200: 603b str r3, [r7, #0] + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + + /* Configure DMA2D data size */ + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos))); + 8005202: 68fb ldr r3, [r7, #12] + 8005204: 681b ldr r3, [r3, #0] + 8005206: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005208: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000 + 800520c: 683b ldr r3, [r7, #0] + 800520e: 041a lsls r2, r3, #16 + 8005210: 6b3b ldr r3, [r7, #48] ; 0x30 + 8005212: 431a orrs r2, r3 + 8005214: 68fb ldr r3, [r7, #12] + 8005216: 681b ldr r3, [r3, #0] + 8005218: 430a orrs r2, r1 + 800521a: 645a str r2, [r3, #68] ; 0x44 + + /* Configure DMA2D destination address */ + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); + 800521c: 68fb ldr r3, [r7, #12] + 800521e: 681b ldr r3, [r3, #0] + 8005220: 687a ldr r2, [r7, #4] + 8005222: 63da str r2, [r3, #60] ; 0x3c + + /* Register to memory DMA2D mode selected */ + if (hdma2d->Init.Mode == DMA2D_R2M) + 8005224: 68fb ldr r3, [r7, #12] + 8005226: 685b ldr r3, [r3, #4] + 8005228: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 + 800522c: d174 bne.n 8005318 + { + tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; + 800522e: 68bb ldr r3, [r7, #8] + 8005230: f003 437f and.w r3, r3, #4278190080 ; 0xff000000 + 8005234: 623b str r3, [r7, #32] + tmp2 = pdata & DMA2D_OCOLR_RED_1; + 8005236: 68bb ldr r3, [r7, #8] + 8005238: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 800523c: 61fb str r3, [r7, #28] + tmp3 = pdata & DMA2D_OCOLR_GREEN_1; + 800523e: 68bb ldr r3, [r7, #8] + 8005240: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8005244: 61bb str r3, [r7, #24] + tmp4 = pdata & DMA2D_OCOLR_BLUE_1; + 8005246: 68bb ldr r3, [r7, #8] + 8005248: b2db uxtb r3, r3 + 800524a: 617b str r3, [r7, #20] + + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) + 800524c: 68fb ldr r3, [r7, #12] + 800524e: 689b ldr r3, [r3, #8] + 8005250: 2b00 cmp r3, #0 + 8005252: d108 bne.n 8005266 + { + tmp = (tmp3 | tmp2 | tmp1 | tmp4); + 8005254: 69ba ldr r2, [r7, #24] + 8005256: 69fb ldr r3, [r7, #28] + 8005258: 431a orrs r2, r3 + 800525a: 6a3b ldr r3, [r7, #32] + 800525c: 4313 orrs r3, r2 + 800525e: 697a ldr r2, [r7, #20] + 8005260: 4313 orrs r3, r2 + 8005262: 627b str r3, [r7, #36] ; 0x24 + 8005264: e053 b.n 800530e + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) + 8005266: 68fb ldr r3, [r7, #12] + 8005268: 689b ldr r3, [r3, #8] + 800526a: 2b01 cmp r3, #1 + 800526c: d106 bne.n 800527c + { + tmp = (tmp3 | tmp2 | tmp4); + 800526e: 69ba ldr r2, [r7, #24] + 8005270: 69fb ldr r3, [r7, #28] + 8005272: 4313 orrs r3, r2 + 8005274: 697a ldr r2, [r7, #20] + 8005276: 4313 orrs r3, r2 + 8005278: 627b str r3, [r7, #36] ; 0x24 + 800527a: e048 b.n 800530e + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) + 800527c: 68fb ldr r3, [r7, #12] + 800527e: 689b ldr r3, [r3, #8] + 8005280: 2b02 cmp r3, #2 + 8005282: d111 bne.n 80052a8 + { + tmp2 = (tmp2 >> 19U); + 8005284: 69fb ldr r3, [r7, #28] + 8005286: 0cdb lsrs r3, r3, #19 + 8005288: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 10U); + 800528a: 69bb ldr r3, [r7, #24] + 800528c: 0a9b lsrs r3, r3, #10 + 800528e: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 3U); + 8005290: 697b ldr r3, [r7, #20] + 8005292: 08db lsrs r3, r3, #3 + 8005294: 617b str r3, [r7, #20] + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); + 8005296: 69bb ldr r3, [r7, #24] + 8005298: 015a lsls r2, r3, #5 + 800529a: 69fb ldr r3, [r7, #28] + 800529c: 02db lsls r3, r3, #11 + 800529e: 4313 orrs r3, r2 + 80052a0: 697a ldr r2, [r7, #20] + 80052a2: 4313 orrs r3, r2 + 80052a4: 627b str r3, [r7, #36] ; 0x24 + 80052a6: e032 b.n 800530e + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) + 80052a8: 68fb ldr r3, [r7, #12] + 80052aa: 689b ldr r3, [r3, #8] + 80052ac: 2b03 cmp r3, #3 + 80052ae: d117 bne.n 80052e0 + { + tmp1 = (tmp1 >> 31U); + 80052b0: 6a3b ldr r3, [r7, #32] + 80052b2: 0fdb lsrs r3, r3, #31 + 80052b4: 623b str r3, [r7, #32] + tmp2 = (tmp2 >> 19U); + 80052b6: 69fb ldr r3, [r7, #28] + 80052b8: 0cdb lsrs r3, r3, #19 + 80052ba: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 11U); + 80052bc: 69bb ldr r3, [r7, #24] + 80052be: 0adb lsrs r3, r3, #11 + 80052c0: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 3U); + 80052c2: 697b ldr r3, [r7, #20] + 80052c4: 08db lsrs r3, r3, #3 + 80052c6: 617b str r3, [r7, #20] + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + 80052c8: 69bb ldr r3, [r7, #24] + 80052ca: 015a lsls r2, r3, #5 + 80052cc: 69fb ldr r3, [r7, #28] + 80052ce: 029b lsls r3, r3, #10 + 80052d0: 431a orrs r2, r3 + 80052d2: 6a3b ldr r3, [r7, #32] + 80052d4: 03db lsls r3, r3, #15 + 80052d6: 4313 orrs r3, r2 + 80052d8: 697a ldr r2, [r7, #20] + 80052da: 4313 orrs r3, r2 + 80052dc: 627b str r3, [r7, #36] ; 0x24 + 80052de: e016 b.n 800530e + } + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ + { + tmp1 = (tmp1 >> 28U); + 80052e0: 6a3b ldr r3, [r7, #32] + 80052e2: 0f1b lsrs r3, r3, #28 + 80052e4: 623b str r3, [r7, #32] + tmp2 = (tmp2 >> 20U); + 80052e6: 69fb ldr r3, [r7, #28] + 80052e8: 0d1b lsrs r3, r3, #20 + 80052ea: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 12U); + 80052ec: 69bb ldr r3, [r7, #24] + 80052ee: 0b1b lsrs r3, r3, #12 + 80052f0: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 4U); + 80052f2: 697b ldr r3, [r7, #20] + 80052f4: 091b lsrs r3, r3, #4 + 80052f6: 617b str r3, [r7, #20] + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + 80052f8: 69bb ldr r3, [r7, #24] + 80052fa: 011a lsls r2, r3, #4 + 80052fc: 69fb ldr r3, [r7, #28] + 80052fe: 021b lsls r3, r3, #8 + 8005300: 431a orrs r2, r3 + 8005302: 6a3b ldr r3, [r7, #32] + 8005304: 031b lsls r3, r3, #12 + 8005306: 4313 orrs r3, r2 + 8005308: 697a ldr r2, [r7, #20] + 800530a: 4313 orrs r3, r2 + 800530c: 627b str r3, [r7, #36] ; 0x24 + } + /* Write to DMA2D OCOLR register */ + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + 800530e: 68fb ldr r3, [r7, #12] + 8005310: 681b ldr r3, [r3, #0] + 8005312: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005314: 639a str r2, [r3, #56] ; 0x38 + else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ + { + /* Configure DMA2D source address */ + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + } +} + 8005316: e003 b.n 8005320 + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + 8005318: 68fb ldr r3, [r7, #12] + 800531a: 681b ldr r3, [r3, #0] + 800531c: 68ba ldr r2, [r7, #8] + 800531e: 60da str r2, [r3, #12] +} + 8005320: bf00 nop + 8005322: 372c adds r7, #44 ; 0x2c + 8005324: 46bd mov sp, r7 + 8005326: f85d 7b04 ldr.w r7, [sp], #4 + 800532a: 4770 bx lr + +0800532c : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + 800532c: b580 push {r7, lr} + 800532e: b084 sub sp, #16 + 8005330: af00 add r7, sp, #0 + 8005332: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (heth == NULL) + 8005334: 687b ldr r3, [r7, #4] + 8005336: 2b00 cmp r3, #0 + 8005338: d101 bne.n 800533e + { + return HAL_ERROR; + 800533a: 2301 movs r3, #1 + 800533c: e06a b.n 8005414 + } + if (heth->gState == HAL_ETH_STATE_RESET) + 800533e: 687b ldr r3, [r7, #4] + 8005340: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8005344: 2b00 cmp r3, #0 + 8005346: d106 bne.n 8005356 + { + heth->gState = HAL_ETH_STATE_BUSY; + 8005348: 687b ldr r3, [r7, #4] + 800534a: 2223 movs r2, #35 ; 0x23 + 800534c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Init the low level hardware */ + heth->MspInitCallback(heth); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); + 8005350: 6878 ldr r0, [r7, #4] + 8005352: f005 fc77 bl 800ac44 + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8005356: 4b31 ldr r3, [pc, #196] ; (800541c ) + 8005358: 6c5b ldr r3, [r3, #68] ; 0x44 + 800535a: 4a30 ldr r2, [pc, #192] ; (800541c ) + 800535c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8005360: 6453 str r3, [r2, #68] ; 0x44 + 8005362: 4b2e ldr r3, [pc, #184] ; (800541c ) + 8005364: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005366: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800536a: 60bb str r3, [r7, #8] + 800536c: 68bb ldr r3, [r7, #8] + + /* Select MII or RMII Mode*/ + SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); + 800536e: 4b2c ldr r3, [pc, #176] ; (8005420 ) + 8005370: 685b ldr r3, [r3, #4] + 8005372: 4a2b ldr r2, [pc, #172] ; (8005420 ) + 8005374: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8005378: 6053 str r3, [r2, #4] + SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + 800537a: 4b29 ldr r3, [pc, #164] ; (8005420 ) + 800537c: 685a ldr r2, [r3, #4] + 800537e: 687b ldr r3, [r7, #4] + 8005380: 689b ldr r3, [r3, #8] + 8005382: 4927 ldr r1, [pc, #156] ; (8005420 ) + 8005384: 4313 orrs r3, r2 + 8005386: 604b str r3, [r1, #4] + /* Dummy read to sync SYSCFG with ETH */ + (void)SYSCFG->PMC; + 8005388: 4b25 ldr r3, [pc, #148] ; (8005420 ) + 800538a: 685b ldr r3, [r3, #4] + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); + 800538c: 687b ldr r3, [r7, #4] + 800538e: 681b ldr r3, [r3, #0] + 8005390: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005394: 681b ldr r3, [r3, #0] + 8005396: 687a ldr r2, [r7, #4] + 8005398: 6812 ldr r2, [r2, #0] + 800539a: f043 0301 orr.w r3, r3, #1 + 800539e: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80053a2: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80053a4: f7ff fa66 bl 8004874 + 80053a8: 60f8 str r0, [r7, #12] + + /* Wait for software reset */ + while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) + 80053aa: e011 b.n 80053d0 + { + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) + 80053ac: f7ff fa62 bl 8004874 + 80053b0: 4602 mov r2, r0 + 80053b2: 68fb ldr r3, [r7, #12] + 80053b4: 1ad3 subs r3, r2, r3 + 80053b6: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 80053ba: d909 bls.n 80053d0 + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + 80053bc: 687b ldr r3, [r7, #4] + 80053be: 2204 movs r2, #4 + 80053c0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + 80053c4: 687b ldr r3, [r7, #4] + 80053c6: 22e0 movs r2, #224 ; 0xe0 + 80053c8: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + /* Return Error */ + return HAL_ERROR; + 80053cc: 2301 movs r3, #1 + 80053ce: e021 b.n 8005414 + while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) + 80053d0: 687b ldr r3, [r7, #4] + 80053d2: 681b ldr r3, [r3, #0] + 80053d4: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80053d8: 681b ldr r3, [r3, #0] + 80053da: f003 0301 and.w r3, r3, #1 + 80053de: 2b00 cmp r3, #0 + 80053e0: d1e4 bne.n 80053ac + } + } + + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + 80053e2: 6878 ldr r0, [r7, #4] + 80053e4: f000 ff4c bl 8006280 + + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + 80053e8: 6878 ldr r0, [r7, #4] + 80053ea: f000 fff3 bl 80063d4 + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + 80053ee: 6878 ldr r0, [r7, #4] + 80053f0: f001 f849 bl 8006486 + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); + 80053f4: 687b ldr r3, [r7, #4] + 80053f6: 685b ldr r3, [r3, #4] + 80053f8: 461a mov r2, r3 + 80053fa: 2100 movs r1, #0 + 80053fc: 6878 ldr r0, [r7, #4] + 80053fe: f000 ffb1 bl 8006364 + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + 8005402: 687b ldr r3, [r7, #4] + 8005404: 2200 movs r2, #0 + 8005406: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + heth->gState = HAL_ETH_STATE_READY; + 800540a: 687b ldr r3, [r7, #4] + 800540c: 2210 movs r2, #16 + 800540e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8005412: 2300 movs r3, #0 +} + 8005414: 4618 mov r0, r3 + 8005416: 3710 adds r7, #16 + 8005418: 46bd mov sp, r7 + 800541a: bd80 pop {r7, pc} + 800541c: 40023800 .word 0x40023800 + 8005420: 40013800 .word 0x40013800 + +08005424 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) +{ + 8005424: b580 push {r7, lr} + 8005426: b084 sub sp, #16 + 8005428: af00 add r7, sp, #0 + 800542a: 6078 str r0, [r7, #4] + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_READY) + 800542c: 687b ldr r3, [r7, #4] + 800542e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8005432: 2b10 cmp r3, #16 + 8005434: d17b bne.n 800552e + { + heth->gState = HAL_ETH_STATE_BUSY; + 8005436: 687b ldr r3, [r7, #4] + 8005438: 2223 movs r2, #35 ; 0x23 + 800543a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* save IT mode to ETH Handle */ + heth->RxDescList.ItMode = 1U; + 800543e: 687b ldr r3, [r7, #4] + 8005440: 2201 movs r2, #1 + 8005442: 659a str r2, [r3, #88] ; 0x58 + /* Disable MMC Interrupts */ + SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); + 8005444: 687b ldr r3, [r7, #4] + 8005446: 681b ldr r3, [r3, #0] + 8005448: 6bda ldr r2, [r3, #60] ; 0x3c + 800544a: 687b ldr r3, [r7, #4] + 800544c: 681b ldr r3, [r3, #0] + 800544e: f442 7202 orr.w r2, r2, #520 ; 0x208 + 8005452: 63da str r2, [r3, #60] ; 0x3c + + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ + 8005454: 687b ldr r3, [r7, #4] + 8005456: 681b ldr r3, [r3, #0] + 8005458: f8d3 110c ldr.w r1, [r3, #268] ; 0x10c + 800545c: 687b ldr r3, [r7, #4] + 800545e: 681a ldr r2, [r3, #0] + 8005460: 4b35 ldr r3, [pc, #212] ; (8005538 ) + 8005462: 430b orrs r3, r1 + 8005464: f8c2 310c str.w r3, [r2, #268] ; 0x10c + ETH_MMCRIMR_RFCEM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ + 8005468: 687b ldr r3, [r7, #4] + 800546a: 681b ldr r3, [r3, #0] + 800546c: f8d3 2110 ldr.w r2, [r3, #272] ; 0x110 + 8005470: 687b ldr r3, [r7, #4] + 8005472: 681b ldr r3, [r3, #0] + 8005474: f442 1203 orr.w r2, r2, #2146304 ; 0x20c000 + 8005478: f8c3 2110 str.w r2, [r3, #272] ; 0x110 + ETH_MMCTIMR_TGFSCM); + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + 800547c: 687b ldr r3, [r7, #4] + 800547e: 2204 movs r2, #4 + 8005480: 66da str r2, [r3, #108] ; 0x6c + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + 8005482: 6878 ldr r0, [r7, #4] + 8005484: f000 f9fc bl 8005880 + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + 8005488: 687b ldr r3, [r7, #4] + 800548a: 681b ldr r3, [r3, #0] + 800548c: 681a ldr r2, [r3, #0] + 800548e: 687b ldr r3, [r7, #4] + 8005490: 681b ldr r3, [r3, #0] + 8005492: f042 0208 orr.w r2, r2, #8 + 8005496: 601a str r2, [r3, #0] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + 8005498: 687b ldr r3, [r7, #4] + 800549a: 681b ldr r3, [r3, #0] + 800549c: 681b ldr r3, [r3, #0] + 800549e: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 80054a0: 2001 movs r0, #1 + 80054a2: f7ff f9f3 bl 800488c + (heth->Instance)->MACCR = tmpreg1; + 80054a6: 687b ldr r3, [r7, #4] + 80054a8: 681b ldr r3, [r3, #0] + 80054aa: 68fa ldr r2, [r7, #12] + 80054ac: 601a str r2, [r3, #0] + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + 80054ae: 687b ldr r3, [r7, #4] + 80054b0: 681b ldr r3, [r3, #0] + 80054b2: 681a ldr r2, [r3, #0] + 80054b4: 687b ldr r3, [r7, #4] + 80054b6: 681b ldr r3, [r3, #0] + 80054b8: f042 0204 orr.w r2, r2, #4 + 80054bc: 601a str r2, [r3, #0] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + 80054be: 687b ldr r3, [r7, #4] + 80054c0: 681b ldr r3, [r3, #0] + 80054c2: 681b ldr r3, [r3, #0] + 80054c4: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 80054c6: 2001 movs r0, #1 + 80054c8: f7ff f9e0 bl 800488c + (heth->Instance)->MACCR = tmpreg1; + 80054cc: 687b ldr r3, [r7, #4] + 80054ce: 681b ldr r3, [r3, #0] + 80054d0: 68fa ldr r2, [r7, #12] + 80054d2: 601a str r2, [r3, #0] + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + 80054d4: 6878 ldr r0, [r7, #4] + 80054d6: f000 fd74 bl 8005fc2 + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + 80054da: 687b ldr r3, [r7, #4] + 80054dc: 681b ldr r3, [r3, #0] + 80054de: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80054e2: 699b ldr r3, [r3, #24] + 80054e4: 687a ldr r2, [r7, #4] + 80054e6: 6812 ldr r2, [r2, #0] + 80054e8: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 80054ec: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80054f0: 6193 str r3, [r2, #24] + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + 80054f2: 687b ldr r3, [r7, #4] + 80054f4: 681b ldr r3, [r3, #0] + 80054f6: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80054fa: 699b ldr r3, [r3, #24] + 80054fc: 687a ldr r2, [r7, #4] + 80054fe: 6812 ldr r2, [r2, #0] + 8005500: f043 0302 orr.w r3, r3, #2 + 8005504: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005508: 6193 str r3, [r2, #24] + /* Enable ETH DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + 800550a: 687b ldr r3, [r7, #4] + 800550c: 681b ldr r3, [r3, #0] + 800550e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005512: 69d9 ldr r1, [r3, #28] + 8005514: 687b ldr r3, [r7, #4] + 8005516: 681a ldr r2, [r3, #0] + 8005518: 4b08 ldr r3, [pc, #32] ; (800553c ) + 800551a: 430b orrs r3, r1 + 800551c: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005520: 61d3 str r3, [r2, #28] + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); + + heth->gState = HAL_ETH_STATE_STARTED; + 8005522: 687b ldr r3, [r7, #4] + 8005524: 2223 movs r2, #35 ; 0x23 + 8005526: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + return HAL_OK; + 800552a: 2300 movs r3, #0 + 800552c: e000 b.n 8005530 + } + else + { + return HAL_ERROR; + 800552e: 2301 movs r3, #1 + } +} + 8005530: 4618 mov r0, r3 + 8005532: 3710 adds r7, #16 + 8005534: 46bd mov sp, r7 + 8005536: bd80 pop {r7, pc} + 8005538: 00020060 .word 0x00020060 + 800553c: 0001a0c1 .word 0x0001a0c1 + +08005540 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + 8005540: b580 push {r7, lr} + 8005542: b086 sub sp, #24 + 8005544: af00 add r7, sp, #0 + 8005546: 6078 str r0, [r7, #4] + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_STARTED) + 8005548: 687b ldr r3, [r7, #4] + 800554a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800554e: 2b23 cmp r3, #35 ; 0x23 + 8005550: d16e bne.n 8005630 + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + 8005552: 687b ldr r3, [r7, #4] + 8005554: 2223 movs r2, #35 ; 0x23 + 8005556: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + 800555a: 687b ldr r3, [r7, #4] + 800555c: 681b ldr r3, [r3, #0] + 800555e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005562: 69d9 ldr r1, [r3, #28] + 8005564: 687b ldr r3, [r7, #4] + 8005566: 681a ldr r2, [r3, #0] + 8005568: 4b34 ldr r3, [pc, #208] ; (800563c ) + 800556a: 400b ands r3, r1 + 800556c: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005570: 61d3 str r3, [r2, #28] + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); + + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + 8005572: 687b ldr r3, [r7, #4] + 8005574: 681b ldr r3, [r3, #0] + 8005576: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800557a: 699b ldr r3, [r3, #24] + 800557c: 687a ldr r2, [r7, #4] + 800557e: 6812 ldr r2, [r2, #0] + 8005580: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 8005584: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005588: 6193 str r3, [r2, #24] + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + 800558a: 687b ldr r3, [r7, #4] + 800558c: 681b ldr r3, [r3, #0] + 800558e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005592: 699b ldr r3, [r3, #24] + 8005594: 687a ldr r2, [r7, #4] + 8005596: 6812 ldr r2, [r2, #0] + 8005598: f023 0302 bic.w r3, r3, #2 + 800559c: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80055a0: 6193 str r3, [r2, #24] + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + 80055a2: 687b ldr r3, [r7, #4] + 80055a4: 681b ldr r3, [r3, #0] + 80055a6: 681a ldr r2, [r3, #0] + 80055a8: 687b ldr r3, [r7, #4] + 80055aa: 681b ldr r3, [r3, #0] + 80055ac: f022 0204 bic.w r2, r2, #4 + 80055b0: 601a str r2, [r3, #0] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + 80055b2: 687b ldr r3, [r7, #4] + 80055b4: 681b ldr r3, [r3, #0] + 80055b6: 681b ldr r3, [r3, #0] + 80055b8: 613b str r3, [r7, #16] + HAL_Delay(ETH_REG_WRITE_DELAY); + 80055ba: 2001 movs r0, #1 + 80055bc: f7ff f966 bl 800488c + (heth->Instance)->MACCR = tmpreg1; + 80055c0: 687b ldr r3, [r7, #4] + 80055c2: 681b ldr r3, [r3, #0] + 80055c4: 693a ldr r2, [r7, #16] + 80055c6: 601a str r2, [r3, #0] + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + 80055c8: 6878 ldr r0, [r7, #4] + 80055ca: f000 fcfa bl 8005fc2 + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + 80055ce: 687b ldr r3, [r7, #4] + 80055d0: 681b ldr r3, [r3, #0] + 80055d2: 681a ldr r2, [r3, #0] + 80055d4: 687b ldr r3, [r7, #4] + 80055d6: 681b ldr r3, [r3, #0] + 80055d8: f022 0208 bic.w r2, r2, #8 + 80055dc: 601a str r2, [r3, #0] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + 80055de: 687b ldr r3, [r7, #4] + 80055e0: 681b ldr r3, [r3, #0] + 80055e2: 681b ldr r3, [r3, #0] + 80055e4: 613b str r3, [r7, #16] + HAL_Delay(ETH_REG_WRITE_DELAY); + 80055e6: 2001 movs r0, #1 + 80055e8: f7ff f950 bl 800488c + (heth->Instance)->MACCR = tmpreg1; + 80055ec: 687b ldr r3, [r7, #4] + 80055ee: 681b ldr r3, [r3, #0] + 80055f0: 693a ldr r2, [r7, #16] + 80055f2: 601a str r2, [r3, #0] + + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + 80055f4: 2300 movs r3, #0 + 80055f6: 617b str r3, [r7, #20] + 80055f8: e00e b.n 8005618 + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + 80055fa: 687b ldr r3, [r7, #4] + 80055fc: 697a ldr r2, [r7, #20] + 80055fe: 3212 adds r2, #18 + 8005600: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8005604: 60fb str r3, [r7, #12] + SET_BIT(dmarxdesc->DESC1, ETH_DMARXDESC_DIC); + 8005606: 68fb ldr r3, [r7, #12] + 8005608: 685b ldr r3, [r3, #4] + 800560a: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 800560e: 68fb ldr r3, [r7, #12] + 8005610: 605a str r2, [r3, #4] + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + 8005612: 697b ldr r3, [r7, #20] + 8005614: 3301 adds r3, #1 + 8005616: 617b str r3, [r7, #20] + 8005618: 697b ldr r3, [r7, #20] + 800561a: 2b03 cmp r3, #3 + 800561c: d9ed bls.n 80055fa + } + + heth->RxDescList.ItMode = 0U; + 800561e: 687b ldr r3, [r7, #4] + 8005620: 2200 movs r2, #0 + 8005622: 659a str r2, [r3, #88] ; 0x58 + + heth->gState = HAL_ETH_STATE_READY; + 8005624: 687b ldr r3, [r7, #4] + 8005626: 2210 movs r2, #16 + 8005628: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Return function status */ + return HAL_OK; + 800562c: 2300 movs r3, #0 + 800562e: e000 b.n 8005632 + } + else + { + return HAL_ERROR; + 8005630: 2301 movs r3, #1 + } +} + 8005632: 4618 mov r0, r3 + 8005634: 3718 adds r7, #24 + 8005636: 46bd mov sp, r7 + 8005638: bd80 pop {r7, pc} + 800563a: bf00 nop + 800563c: fffe5f3e .word 0xfffe5f3e + +08005640 : + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) +{ + 8005640: b580 push {r7, lr} + 8005642: b082 sub sp, #8 + 8005644: af00 add r7, sp, #0 + 8005646: 6078 str r0, [r7, #4] + 8005648: 6039 str r1, [r7, #0] + if (pTxConfig == NULL) + 800564a: 683b ldr r3, [r7, #0] + 800564c: 2b00 cmp r3, #0 + 800564e: d109 bne.n 8005664 + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + 8005650: 687b ldr r3, [r7, #4] + 8005652: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8005656: f043 0201 orr.w r2, r3, #1 + 800565a: 687b ldr r3, [r7, #4] + 800565c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 8005660: 2301 movs r3, #1 + 8005662: e045 b.n 80056f0 + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + 8005664: 687b ldr r3, [r7, #4] + 8005666: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800566a: 2b23 cmp r3, #35 ; 0x23 + 800566c: d13f bne.n 80056ee + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + 800566e: 683b ldr r3, [r7, #0] + 8005670: 6b5a ldr r2, [r3, #52] ; 0x34 + 8005672: 687b ldr r3, [r7, #4] + 8005674: 63da str r2, [r3, #60] ; 0x3c + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) + 8005676: 2201 movs r2, #1 + 8005678: 6839 ldr r1, [r7, #0] + 800567a: 6878 ldr r0, [r7, #4] + 800567c: f000 ff70 bl 8006560 + 8005680: 4603 mov r3, r0 + 8005682: 2b00 cmp r3, #0 + 8005684: d009 beq.n 800569a + { + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + 8005686: 687b ldr r3, [r7, #4] + 8005688: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800568c: f043 0202 orr.w r2, r3, #2 + 8005690: 687b ldr r3, [r7, #4] + 8005692: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 8005696: 2301 movs r3, #1 + 8005698: e02a b.n 80056f0 + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 800569a: f3bf 8f4f dsb sy +} + 800569e: bf00 nop + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + 80056a0: 687b ldr r3, [r7, #4] + 80056a2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80056a4: 1c5a adds r2, r3, #1 + 80056a6: 687b ldr r3, [r7, #4] + 80056a8: 629a str r2, [r3, #40] ; 0x28 + 80056aa: 687b ldr r3, [r7, #4] + 80056ac: 6a9b ldr r3, [r3, #40] ; 0x28 + 80056ae: 2b03 cmp r3, #3 + 80056b0: d904 bls.n 80056bc + 80056b2: 687b ldr r3, [r7, #4] + 80056b4: 6a9b ldr r3, [r3, #40] ; 0x28 + 80056b6: 1f1a subs r2, r3, #4 + 80056b8: 687b ldr r3, [r7, #4] + 80056ba: 629a str r2, [r3, #40] ; 0x28 + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + 80056bc: 687b ldr r3, [r7, #4] + 80056be: 681b ldr r3, [r3, #0] + 80056c0: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80056c4: 695b ldr r3, [r3, #20] + 80056c6: f003 0304 and.w r3, r3, #4 + 80056ca: 2b00 cmp r3, #0 + 80056cc: d00d beq.n 80056ea + { + /* Clear TBUS ETHERNET DMA flag */ + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + 80056ce: 687b ldr r3, [r7, #4] + 80056d0: 681b ldr r3, [r3, #0] + 80056d2: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80056d6: 461a mov r2, r3 + 80056d8: 2304 movs r3, #4 + 80056da: 6153 str r3, [r2, #20] + /* Resume DMA transmission*/ + (heth->Instance)->DMATPDR = 0U; + 80056dc: 687b ldr r3, [r7, #4] + 80056de: 681b ldr r3, [r3, #0] + 80056e0: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80056e4: 461a mov r2, r3 + 80056e6: 2300 movs r3, #0 + 80056e8: 6053 str r3, [r2, #4] + } + + return HAL_OK; + 80056ea: 2300 movs r3, #0 + 80056ec: e000 b.n 80056f0 + + } + else + { + return HAL_ERROR; + 80056ee: 2301 movs r3, #1 + } +} + 80056f0: 4618 mov r0, r3 + 80056f2: 3708 adds r7, #8 + 80056f4: 46bd mov sp, r7 + 80056f6: bd80 pop {r7, pc} + +080056f8 : + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + 80056f8: b580 push {r7, lr} + 80056fa: b088 sub sp, #32 + 80056fc: af00 add r7, sp, #0 + 80056fe: 6078 str r0, [r7, #4] + 8005700: 6039 str r1, [r7, #0] + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + 8005702: 2300 movs r3, #0 + 8005704: 617b str r3, [r7, #20] + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + 8005706: 2300 movs r3, #0 + 8005708: 73fb strb r3, [r7, #15] + + + if (pAppBuff == NULL) + 800570a: 683b ldr r3, [r7, #0] + 800570c: 2b00 cmp r3, #0 + 800570e: d109 bne.n 8005724 + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + 8005710: 687b ldr r3, [r7, #4] + 8005712: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8005716: f043 0201 orr.w r2, r3, #1 + 800571a: 687b ldr r3, [r7, #4] + 800571c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 8005720: 2301 movs r3, #1 + 8005722: e0a8 b.n 8005876 + } + + if (heth->gState != HAL_ETH_STATE_STARTED) + 8005724: 687b ldr r3, [r7, #4] + 8005726: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800572a: 2b23 cmp r3, #35 ; 0x23 + 800572c: d001 beq.n 8005732 + { + return HAL_ERROR; + 800572e: 2301 movs r3, #1 + 8005730: e0a1 b.n 8005876 + } + + descidx = heth->RxDescList.RxDescIdx; + 8005732: 687b ldr r3, [r7, #4] + 8005734: 6ddb ldr r3, [r3, #92] ; 0x5c + 8005736: 61fb str r3, [r7, #28] + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 8005738: 687b ldr r3, [r7, #4] + 800573a: 69fa ldr r2, [r7, #28] + 800573c: 3212 adds r2, #18 + 800573e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8005742: 61bb str r3, [r7, #24] + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + 8005744: 687b ldr r3, [r7, #4] + 8005746: 6edb ldr r3, [r3, #108] ; 0x6c + 8005748: f1c3 0304 rsb r3, r3, #4 + 800574c: 60bb str r3, [r7, #8] + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + 800574e: e06a b.n 8005826 + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) + 8005750: 69bb ldr r3, [r7, #24] + 8005752: 681b ldr r3, [r3, #0] + 8005754: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005758: 2b00 cmp r3, #0 + 800575a: d007 beq.n 800576c + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6; + 800575c: 69bb ldr r3, [r7, #24] + 800575e: 699a ldr r2, [r3, #24] + 8005760: 687b ldr r3, [r7, #4] + 8005762: 679a str r2, [r3, #120] ; 0x78 + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7; + 8005764: 69bb ldr r3, [r7, #24] + 8005766: 69da ldr r2, [r3, #28] + 8005768: 687b ldr r3, [r7, #4] + 800576a: 675a str r2, [r3, #116] ; 0x74 + } + if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + 800576c: 69bb ldr r3, [r7, #24] + 800576e: 681b ldr r3, [r3, #0] + 8005770: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005774: 2b00 cmp r3, #0 + 8005776: d103 bne.n 8005780 + 8005778: 687b ldr r3, [r7, #4] + 800577a: 6fdb ldr r3, [r3, #124] ; 0x7c + 800577c: 2b00 cmp r3, #0 + 800577e: d040 beq.n 8005802 + { + /* Check first descriptor */ + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) + 8005780: 69bb ldr r3, [r7, #24] + 8005782: 681b ldr r3, [r3, #0] + 8005784: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005788: 2b00 cmp r3, #0 + 800578a: d005 beq.n 8005798 + { + heth->RxDescList.RxDescCnt = 0; + 800578c: 687b ldr r3, [r7, #4] + 800578e: 2200 movs r2, #0 + 8005790: 661a str r2, [r3, #96] ; 0x60 + heth->RxDescList.RxDataLength = 0; + 8005792: 687b ldr r3, [r7, #4] + 8005794: 2200 movs r2, #0 + 8005796: 665a str r2, [r3, #100] ; 0x64 + } + + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + 8005798: 687b ldr r3, [r7, #4] + 800579a: 695b ldr r3, [r3, #20] + 800579c: 613b str r3, [r7, #16] + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) + 800579e: 69bb ldr r3, [r7, #24] + 80057a0: 681b ldr r3, [r3, #0] + 80057a2: f403 7380 and.w r3, r3, #256 ; 0x100 + 80057a6: 2b00 cmp r3, #0 + 80057a8: d00c beq.n 80057c4 + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + 80057aa: 69bb ldr r3, [r7, #24] + 80057ac: 681b ldr r3, [r3, #0] + 80057ae: 0c1b lsrs r3, r3, #16 + 80057b0: f3c3 030d ubfx r3, r3, #0, #14 + 80057b4: 3b04 subs r3, #4 + 80057b6: 613b str r3, [r7, #16] + + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0; + 80057b8: 69bb ldr r3, [r7, #24] + 80057ba: 681a ldr r2, [r3, #0] + 80057bc: 687b ldr r3, [r7, #4] + 80057be: 671a str r2, [r3, #112] ; 0x70 + + /* Packet ready */ + rxdataready = 1; + 80057c0: 2301 movs r3, #1 + 80057c2: 73fb strb r3, [r7, #15] + } + + /* Link data */ + WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); + 80057c4: 69bb ldr r3, [r7, #24] + 80057c6: 689a ldr r2, [r3, #8] + 80057c8: 69bb ldr r3, [r7, #24] + 80057ca: 621a str r2, [r3, #32] + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + 80057cc: 687b ldr r3, [r7, #4] + 80057ce: f103 007c add.w r0, r3, #124 ; 0x7c + 80057d2: 687b ldr r3, [r7, #4] + 80057d4: f103 0180 add.w r1, r3, #128 ; 0x80 + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); + 80057d8: 69bb ldr r3, [r7, #24] + 80057da: 6a1b ldr r3, [r3, #32] + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + 80057dc: 461a mov r2, r3 + 80057de: 693b ldr r3, [r7, #16] + 80057e0: b29b uxth r3, r3 + 80057e2: f005 fbdd bl 800afa0 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + 80057e6: 687b ldr r3, [r7, #4] + 80057e8: 6e1b ldr r3, [r3, #96] ; 0x60 + 80057ea: 1c5a adds r2, r3, #1 + 80057ec: 687b ldr r3, [r7, #4] + 80057ee: 661a str r2, [r3, #96] ; 0x60 + heth->RxDescList.RxDataLength += bufflength; + 80057f0: 687b ldr r3, [r7, #4] + 80057f2: 6e5a ldr r2, [r3, #100] ; 0x64 + 80057f4: 693b ldr r3, [r7, #16] + 80057f6: 441a add r2, r3 + 80057f8: 687b ldr r3, [r7, #4] + 80057fa: 665a str r2, [r3, #100] ; 0x64 + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + 80057fc: 69bb ldr r3, [r7, #24] + 80057fe: 2200 movs r2, #0 + 8005800: 621a str r2, [r3, #32] + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + 8005802: 69fb ldr r3, [r7, #28] + 8005804: 3301 adds r3, #1 + 8005806: 61fb str r3, [r7, #28] + 8005808: 69fb ldr r3, [r7, #28] + 800580a: 2b03 cmp r3, #3 + 800580c: d902 bls.n 8005814 + 800580e: 69fb ldr r3, [r7, #28] + 8005810: 3b04 subs r3, #4 + 8005812: 61fb str r3, [r7, #28] + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 8005814: 687b ldr r3, [r7, #4] + 8005816: 69fa ldr r2, [r7, #28] + 8005818: 3212 adds r2, #18 + 800581a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800581e: 61bb str r3, [r7, #24] + desccnt++; + 8005820: 697b ldr r3, [r7, #20] + 8005822: 3301 adds r3, #1 + 8005824: 617b str r3, [r7, #20] + while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + 8005826: 69bb ldr r3, [r7, #24] + 8005828: 681b ldr r3, [r3, #0] + 800582a: 2b00 cmp r3, #0 + 800582c: db06 blt.n 800583c + 800582e: 697a ldr r2, [r7, #20] + 8005830: 68bb ldr r3, [r7, #8] + 8005832: 429a cmp r2, r3 + 8005834: d202 bcs.n 800583c + && (rxdataready == 0U)) + 8005836: 7bfb ldrb r3, [r7, #15] + 8005838: 2b00 cmp r3, #0 + 800583a: d089 beq.n 8005750 + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + 800583c: 687b ldr r3, [r7, #4] + 800583e: 6eda ldr r2, [r3, #108] ; 0x6c + 8005840: 697b ldr r3, [r7, #20] + 8005842: 441a add r2, r3 + 8005844: 687b ldr r3, [r7, #4] + 8005846: 66da str r2, [r3, #108] ; 0x6c + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + 8005848: 687b ldr r3, [r7, #4] + 800584a: 6edb ldr r3, [r3, #108] ; 0x6c + 800584c: 2b00 cmp r3, #0 + 800584e: d002 beq.n 8005856 + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + 8005850: 6878 ldr r0, [r7, #4] + 8005852: f000 f815 bl 8005880 + } + + heth->RxDescList.RxDescIdx = descidx; + 8005856: 687b ldr r3, [r7, #4] + 8005858: 69fa ldr r2, [r7, #28] + 800585a: 65da str r2, [r3, #92] ; 0x5c + + if (rxdataready == 1U) + 800585c: 7bfb ldrb r3, [r7, #15] + 800585e: 2b01 cmp r3, #1 + 8005860: d108 bne.n 8005874 + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + 8005862: 687b ldr r3, [r7, #4] + 8005864: 6fda ldr r2, [r3, #124] ; 0x7c + 8005866: 683b ldr r3, [r7, #0] + 8005868: 601a str r2, [r3, #0] + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + 800586a: 687b ldr r3, [r7, #4] + 800586c: 2200 movs r2, #0 + 800586e: 67da str r2, [r3, #124] ; 0x7c + + return HAL_OK; + 8005870: 2300 movs r3, #0 + 8005872: e000 b.n 8005876 + } + + /* Packet not ready */ + return HAL_ERROR; + 8005874: 2301 movs r3, #1 +} + 8005876: 4618 mov r0, r3 + 8005878: 3720 adds r7, #32 + 800587a: 46bd mov sp, r7 + 800587c: bd80 pop {r7, pc} + ... + +08005880 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + 8005880: b580 push {r7, lr} + 8005882: b088 sub sp, #32 + 8005884: af00 add r7, sp, #0 + 8005886: 6078 str r0, [r7, #4] + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + 8005888: 2300 movs r3, #0 + 800588a: 60fb str r3, [r7, #12] + uint8_t allocStatus = 1U; + 800588c: 2301 movs r3, #1 + 800588e: 74fb strb r3, [r7, #19] + + descidx = heth->RxDescList.RxBuildDescIdx; + 8005890: 687b ldr r3, [r7, #4] + 8005892: 6e9b ldr r3, [r3, #104] ; 0x68 + 8005894: 61fb str r3, [r7, #28] + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 8005896: 687b ldr r3, [r7, #4] + 8005898: 69fa ldr r2, [r7, #28] + 800589a: 3212 adds r2, #18 + 800589c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80058a0: 617b str r3, [r7, #20] + desccount = heth->RxDescList.RxBuildDescCnt; + 80058a2: 687b ldr r3, [r7, #4] + 80058a4: 6edb ldr r3, [r3, #108] ; 0x6c + 80058a6: 61bb str r3, [r7, #24] + + while ((desccount > 0U) && (allocStatus != 0U)) + 80058a8: e040 b.n 800592c + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + 80058aa: 697b ldr r3, [r7, #20] + 80058ac: 6a1b ldr r3, [r3, #32] + 80058ae: 2b00 cmp r3, #0 + 80058b0: d112 bne.n 80058d8 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); + 80058b2: f107 030c add.w r3, r7, #12 + 80058b6: 4618 mov r0, r3 + 80058b8: f005 fb42 bl 800af40 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + 80058bc: 68fb ldr r3, [r7, #12] + 80058be: 2b00 cmp r3, #0 + 80058c0: d102 bne.n 80058c8 + { + allocStatus = 0U; + 80058c2: 2300 movs r3, #0 + 80058c4: 74fb strb r3, [r7, #19] + 80058c6: e007 b.n 80058d8 + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + 80058c8: 68fb ldr r3, [r7, #12] + 80058ca: 461a mov r2, r3 + 80058cc: 697b ldr r3, [r7, #20] + 80058ce: 621a str r2, [r3, #32] + WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); + 80058d0: 68fb ldr r3, [r7, #12] + 80058d2: 461a mov r2, r3 + 80058d4: 697b ldr r3, [r7, #20] + 80058d6: 609a str r2, [r3, #8] + } + } + + if (allocStatus != 0U) + 80058d8: 7cfb ldrb r3, [r7, #19] + 80058da: 2b00 cmp r3, #0 + 80058dc: d026 beq.n 800592c + { + if (heth->RxDescList.ItMode == 0U) + 80058de: 687b ldr r3, [r7, #4] + 80058e0: 6d9b ldr r3, [r3, #88] ; 0x58 + 80058e2: 2b00 cmp r3, #0 + 80058e4: d103 bne.n 80058ee + { + WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); + 80058e6: 697b ldr r3, [r7, #20] + 80058e8: 4a1e ldr r2, [pc, #120] ; (8005964 ) + 80058ea: 605a str r2, [r3, #4] + 80058ec: e003 b.n 80058f6 + } + else + { + WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); + 80058ee: 697b ldr r3, [r7, #20] + 80058f0: f44f 428c mov.w r2, #17920 ; 0x4600 + 80058f4: 605a str r2, [r3, #4] + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); + 80058f6: f3bf 8f5f dmb sy +} + 80058fa: bf00 nop + is fully performed. + The __DMB() instruction is added to avoid any potential compiler optimization that + may lead to abnormal behavior. */ + __DMB(); + + SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); + 80058fc: 697b ldr r3, [r7, #20] + 80058fe: 681b ldr r3, [r3, #0] + 8005900: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8005904: 697b ldr r3, [r7, #20] + 8005906: 601a str r2, [r3, #0] + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + 8005908: 69fb ldr r3, [r7, #28] + 800590a: 3301 adds r3, #1 + 800590c: 61fb str r3, [r7, #28] + 800590e: 69fb ldr r3, [r7, #28] + 8005910: 2b03 cmp r3, #3 + 8005912: d902 bls.n 800591a + 8005914: 69fb ldr r3, [r7, #28] + 8005916: 3b04 subs r3, #4 + 8005918: 61fb str r3, [r7, #28] + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 800591a: 687b ldr r3, [r7, #4] + 800591c: 69fa ldr r2, [r7, #28] + 800591e: 3212 adds r2, #18 + 8005920: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8005924: 617b str r3, [r7, #20] + desccount--; + 8005926: 69bb ldr r3, [r7, #24] + 8005928: 3b01 subs r3, #1 + 800592a: 61bb str r3, [r7, #24] + while ((desccount > 0U) && (allocStatus != 0U)) + 800592c: 69bb ldr r3, [r7, #24] + 800592e: 2b00 cmp r3, #0 + 8005930: d002 beq.n 8005938 + 8005932: 7cfb ldrb r3, [r7, #19] + 8005934: 2b00 cmp r3, #0 + 8005936: d1b8 bne.n 80058aa + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + 8005938: 687b ldr r3, [r7, #4] + 800593a: 6edb ldr r3, [r3, #108] ; 0x6c + 800593c: 69ba ldr r2, [r7, #24] + 800593e: 429a cmp r2, r3 + 8005940: d00c beq.n 800595c + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMARPDR, 0); + 8005942: 687b ldr r3, [r7, #4] + 8005944: 681b ldr r3, [r3, #0] + 8005946: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800594a: 461a mov r2, r3 + 800594c: 2300 movs r3, #0 + 800594e: 6093 str r3, [r2, #8] + + heth->RxDescList.RxBuildDescIdx = descidx; + 8005950: 687b ldr r3, [r7, #4] + 8005952: 69fa ldr r2, [r7, #28] + 8005954: 669a str r2, [r3, #104] ; 0x68 + heth->RxDescList.RxBuildDescCnt = desccount; + 8005956: 687b ldr r3, [r7, #4] + 8005958: 69ba ldr r2, [r7, #24] + 800595a: 66da str r2, [r3, #108] ; 0x6c + } +} + 800595c: bf00 nop + 800595e: 3720 adds r7, #32 + 8005960: 46bd mov sp, r7 + 8005962: bd80 pop {r7, pc} + 8005964: 80004600 .word 0x80004600 + +08005968 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + 8005968: b580 push {r7, lr} + 800596a: b086 sub sp, #24 + 800596c: af00 add r7, sp, #0 + 800596e: 6078 str r0, [r7, #4] + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + 8005970: 687b ldr r3, [r7, #4] + 8005972: 3318 adds r3, #24 + 8005974: 60bb str r3, [r7, #8] + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + 8005976: 68bb ldr r3, [r7, #8] + 8005978: 6a9b ldr r3, [r3, #40] ; 0x28 + 800597a: 617b str r3, [r7, #20] + uint32_t idx = dmatxdesclist->releaseIndex; + 800597c: 68bb ldr r3, [r7, #8] + 800597e: 6adb ldr r3, [r3, #44] ; 0x2c + 8005980: 613b str r3, [r7, #16] + uint8_t pktTxStatus = 1U; + 8005982: 2301 movs r3, #1 + 8005984: 73fb strb r3, [r7, #15] +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + 8005986: e03f b.n 8005a08 + { + pktInUse = 1U; + 8005988: 2301 movs r3, #1 + 800598a: 73bb strb r3, [r7, #14] + numOfBuf--; + 800598c: 697b ldr r3, [r7, #20] + 800598e: 3b01 subs r3, #1 + 8005990: 617b str r3, [r7, #20] + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) + 8005992: 68ba ldr r2, [r7, #8] + 8005994: 693b ldr r3, [r7, #16] + 8005996: 3304 adds r3, #4 + 8005998: 009b lsls r3, r3, #2 + 800599a: 4413 add r3, r2 + 800599c: 685b ldr r3, [r3, #4] + 800599e: 2b00 cmp r3, #0 + 80059a0: d106 bne.n 80059b0 + { + /* No packet in use, skip to next. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + 80059a2: 693b ldr r3, [r7, #16] + 80059a4: 3301 adds r3, #1 + 80059a6: f003 0303 and.w r3, r3, #3 + 80059aa: 613b str r3, [r7, #16] + pktInUse = 0U; + 80059ac: 2300 movs r3, #0 + 80059ae: 73bb strb r3, [r7, #14] + } + + if (pktInUse != 0U) + 80059b0: 7bbb ldrb r3, [r7, #14] + 80059b2: 2b00 cmp r3, #0 + 80059b4: d028 beq.n 8005a08 + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U) + 80059b6: 687b ldr r3, [r7, #4] + 80059b8: 68d9 ldr r1, [r3, #12] + 80059ba: 693a ldr r2, [r7, #16] + 80059bc: 4613 mov r3, r2 + 80059be: 009b lsls r3, r3, #2 + 80059c0: 4413 add r3, r2 + 80059c2: 00db lsls r3, r3, #3 + 80059c4: 440b add r3, r1 + 80059c6: 681b ldr r3, [r3, #0] + 80059c8: 2b00 cmp r3, #0 + 80059ca: db1b blt.n 8005a04 +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); + 80059cc: 68ba ldr r2, [r7, #8] + 80059ce: 693b ldr r3, [r7, #16] + 80059d0: 3304 adds r3, #4 + 80059d2: 009b lsls r3, r3, #2 + 80059d4: 4413 add r3, r2 + 80059d6: 685b ldr r3, [r3, #4] + 80059d8: 4618 mov r0, r3 + 80059da: f005 fb23 bl 800b024 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + 80059de: 68ba ldr r2, [r7, #8] + 80059e0: 693b ldr r3, [r7, #16] + 80059e2: 3304 adds r3, #4 + 80059e4: 009b lsls r3, r3, #2 + 80059e6: 4413 add r3, r2 + 80059e8: 2200 movs r2, #0 + 80059ea: 605a str r2, [r3, #4] + + /* Update the transmit relesae index and number of buffers in use. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + 80059ec: 693b ldr r3, [r7, #16] + 80059ee: 3301 adds r3, #1 + 80059f0: f003 0303 and.w r3, r3, #3 + 80059f4: 613b str r3, [r7, #16] + dmatxdesclist->BuffersInUse = numOfBuf; + 80059f6: 68bb ldr r3, [r7, #8] + 80059f8: 697a ldr r2, [r7, #20] + 80059fa: 629a str r2, [r3, #40] ; 0x28 + dmatxdesclist->releaseIndex = idx; + 80059fc: 68bb ldr r3, [r7, #8] + 80059fe: 693a ldr r2, [r7, #16] + 8005a00: 62da str r2, [r3, #44] ; 0x2c + 8005a02: e001 b.n 8005a08 + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + 8005a04: 2300 movs r3, #0 + 8005a06: 73fb strb r3, [r7, #15] + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + 8005a08: 697b ldr r3, [r7, #20] + 8005a0a: 2b00 cmp r3, #0 + 8005a0c: d002 beq.n 8005a14 + 8005a0e: 7bfb ldrb r3, [r7, #15] + 8005a10: 2b00 cmp r3, #0 + 8005a12: d1b9 bne.n 8005988 + } + } + } + return HAL_OK; + 8005a14: 2300 movs r3, #0 +} + 8005a16: 4618 mov r0, r3 + 8005a18: 3718 adds r7, #24 + 8005a1a: 46bd mov sp, r7 + 8005a1c: bd80 pop {r7, pc} + ... + +08005a20 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + 8005a20: b580 push {r7, lr} + 8005a22: b082 sub sp, #8 + 8005a24: af00 add r7, sp, #0 + 8005a26: 6078 str r0, [r7, #4] + /* Packet received */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_RS)) + 8005a28: 687b ldr r3, [r7, #4] + 8005a2a: 681b ldr r3, [r3, #0] + 8005a2c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a30: 695b ldr r3, [r3, #20] + 8005a32: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005a36: 2b40 cmp r3, #64 ; 0x40 + 8005a38: d112 bne.n 8005a60 + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_RIE)) + 8005a3a: 687b ldr r3, [r7, #4] + 8005a3c: 681b ldr r3, [r3, #0] + 8005a3e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a42: 69db ldr r3, [r3, #28] + 8005a44: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005a48: 2b40 cmp r3, #64 ; 0x40 + 8005a4a: d109 bne.n 8005a60 + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS); + 8005a4c: 687b ldr r3, [r7, #4] + 8005a4e: 681b ldr r3, [r3, #0] + 8005a50: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a54: 461a mov r2, r3 + 8005a56: 4b50 ldr r3, [pc, #320] ; (8005b98 ) + 8005a58: 6153 str r3, [r2, #20] +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); + 8005a5a: 6878 ldr r0, [r7, #4] + 8005a5c: f004 fe56 bl 800a70c +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Packet transmitted */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_TS)) + 8005a60: 687b ldr r3, [r7, #4] + 8005a62: 681b ldr r3, [r3, #0] + 8005a64: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a68: 695b ldr r3, [r3, #20] + 8005a6a: f003 0301 and.w r3, r3, #1 + 8005a6e: 2b01 cmp r3, #1 + 8005a70: d113 bne.n 8005a9a + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_TIE)) + 8005a72: 687b ldr r3, [r7, #4] + 8005a74: 681b ldr r3, [r3, #0] + 8005a76: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a7a: 69db ldr r3, [r3, #28] + 8005a7c: f003 0301 and.w r3, r3, #1 + 8005a80: 2b01 cmp r3, #1 + 8005a82: d10a bne.n 8005a9a + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS); + 8005a84: 687b ldr r3, [r7, #4] + 8005a86: 681b ldr r3, [r3, #0] + 8005a88: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005a8c: 461a mov r2, r3 + 8005a8e: f04f 1301 mov.w r3, #65537 ; 0x10001 + 8005a92: 6153 str r3, [r2, #20] +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); + 8005a94: 6878 ldr r0, [r7, #4] + 8005a96: f004 fe49 bl 800a72c + } + } + + + /* ETH DMA Error */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS)) + 8005a9a: 687b ldr r3, [r7, #4] + 8005a9c: 681b ldr r3, [r3, #0] + 8005a9e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005aa2: 695b ldr r3, [r3, #20] + 8005aa4: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8005aa8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8005aac: d14c bne.n 8005b48 + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE)) + 8005aae: 687b ldr r3, [r7, #4] + 8005ab0: 681b ldr r3, [r3, #0] + 8005ab2: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005ab6: 69db ldr r3, [r3, #28] + 8005ab8: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8005abc: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8005ac0: d142 bne.n 8005b48 + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + 8005ac2: 687b ldr r3, [r7, #4] + 8005ac4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8005ac8: f043 0208 orr.w r2, r3, #8 + 8005acc: 687b ldr r3, [r7, #4] + 8005ace: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* if fatal bus error occurred */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES)) + 8005ad2: 687b ldr r3, [r7, #4] + 8005ad4: 681b ldr r3, [r3, #0] + 8005ad6: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005ada: 695b ldr r3, [r3, #20] + 8005adc: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8005ae0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8005ae4: d11a bne.n 8005b1c + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS)); + 8005ae6: 687b ldr r3, [r7, #4] + 8005ae8: 681b ldr r3, [r3, #0] + 8005aea: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005aee: 695a ldr r2, [r3, #20] + 8005af0: 4b2a ldr r3, [pc, #168] ; (8005b9c ) + 8005af2: 4013 ands r3, r2 + 8005af4: 687a ldr r2, [r7, #4] + 8005af6: f8c2 308c str.w r3, [r2, #140] ; 0x8c + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE); + 8005afa: 687b ldr r3, [r7, #4] + 8005afc: 681b ldr r3, [r3, #0] + 8005afe: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005b02: 69db ldr r3, [r3, #28] + 8005b04: 687a ldr r2, [r7, #4] + 8005b06: 6812 ldr r2, [r2, #0] + 8005b08: f423 33c0 bic.w r3, r3, #98304 ; 0x18000 + 8005b0c: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005b10: 61d3 str r3, [r2, #28] + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + 8005b12: 687b ldr r3, [r7, #4] + 8005b14: 22e0 movs r2, #224 ; 0xe0 + 8005b16: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 8005b1a: e012 b.n 8005b42 + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + 8005b1c: 687b ldr r3, [r7, #4] + 8005b1e: 681b ldr r3, [r3, #0] + 8005b20: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005b24: 695a ldr r2, [r3, #20] + 8005b26: f248 6380 movw r3, #34432 ; 0x8680 + 8005b2a: 4013 ands r3, r2 + 8005b2c: 687a ldr r2, [r7, #4] + 8005b2e: f8c2 308c str.w r3, [r2, #140] ; 0x8c + ETH_DMASR_RBUS | ETH_DMASR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + 8005b32: 687b ldr r3, [r7, #4] + 8005b34: 681b ldr r3, [r3, #0] + 8005b36: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005b3a: 461a mov r2, r3 + 8005b3c: f248 6380 movw r3, #34432 ; 0x8680 + 8005b40: 6153 str r3, [r2, #20] +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); + 8005b42: 6878 ldr r0, [r7, #4] + 8005b44: f004 fe02 bl 800a74c + } + } + + + /* ETH PMT IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + 8005b48: 687b ldr r3, [r7, #4] + 8005b4a: 681b ldr r3, [r3, #0] + 8005b4c: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005b4e: f003 0308 and.w r3, r3, #8 + 8005b52: 2b08 cmp r3, #8 + 8005b54: d10e bne.n 8005b74 + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR)); + 8005b56: 687b ldr r3, [r7, #4] + 8005b58: 681b ldr r3, [r3, #0] + 8005b5a: 6adb ldr r3, [r3, #44] ; 0x2c + 8005b5c: f003 0260 and.w r2, r3, #96 ; 0x60 + 8005b60: 687b ldr r3, [r7, #4] + 8005b62: f8c3 2094 str.w r2, [r3, #148] ; 0x94 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); + 8005b66: 6878 ldr r0, [r7, #4] + 8005b68: f000 f81c bl 8005ba4 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + 8005b6c: 687b ldr r3, [r7, #4] + 8005b6e: 2200 movs r2, #0 + 8005b70: f8c3 2094 str.w r2, [r3, #148] ; 0x94 + } + + + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + 8005b74: 4b0a ldr r3, [pc, #40] ; (8005ba0 ) + 8005b76: 695b ldr r3, [r3, #20] + 8005b78: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8005b7c: 2b00 cmp r3, #0 + 8005b7e: d006 beq.n 8005b8e + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); + 8005b80: 4b07 ldr r3, [pc, #28] ; (8005ba0 ) + 8005b82: f44f 2200 mov.w r2, #524288 ; 0x80000 + 8005b86: 615a str r2, [r3, #20] +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); + 8005b88: 6878 ldr r0, [r7, #4] + 8005b8a: f000 f815 bl 8005bb8 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +} + 8005b8e: bf00 nop + 8005b90: 3708 adds r7, #8 + 8005b92: 46bd mov sp, r7 + 8005b94: bd80 pop {r7, pc} + 8005b96: bf00 nop + 8005b98: 00010040 .word 0x00010040 + 8005b9c: 007e2000 .word 0x007e2000 + 8005ba0: 40013c00 .word 0x40013c00 + +08005ba4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + 8005ba4: b480 push {r7} + 8005ba6: b083 sub sp, #12 + 8005ba8: af00 add r7, sp, #0 + 8005baa: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + 8005bac: bf00 nop + 8005bae: 370c adds r7, #12 + 8005bb0: 46bd mov sp, r7 + 8005bb2: f85d 7b04 ldr.w r7, [sp], #4 + 8005bb6: 4770 bx lr + +08005bb8 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + 8005bb8: b480 push {r7} + 8005bba: b083 sub sp, #12 + 8005bbc: af00 add r7, sp, #0 + 8005bbe: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + 8005bc0: bf00 nop + 8005bc2: 370c adds r7, #12 + 8005bc4: 46bd mov sp, r7 + 8005bc6: f85d 7b04 ldr.w r7, [sp], #4 + 8005bca: 4770 bx lr + +08005bcc : + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + 8005bcc: b580 push {r7, lr} + 8005bce: b086 sub sp, #24 + 8005bd0: af00 add r7, sp, #0 + 8005bd2: 60f8 str r0, [r7, #12] + 8005bd4: 60b9 str r1, [r7, #8] + 8005bd6: 607a str r2, [r7, #4] + 8005bd8: 603b str r3, [r7, #0] + uint32_t tmpreg1; + uint32_t tickstart; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + 8005bda: 68fb ldr r3, [r7, #12] + 8005bdc: 681b ldr r3, [r3, #0] + 8005bde: 691b ldr r3, [r3, #16] + 8005be0: 617b str r3, [r7, #20] + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + 8005be2: 697b ldr r3, [r7, #20] + 8005be4: f003 031c and.w r3, r3, #28 + 8005be8: 617b str r3, [r7, #20] + + /* Prepare the MII address register value */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + 8005bea: 68bb ldr r3, [r7, #8] + 8005bec: 02db lsls r3, r3, #11 + 8005bee: b29b uxth r3, r3 + 8005bf0: 697a ldr r2, [r7, #20] + 8005bf2: 4313 orrs r3, r2 + 8005bf4: 617b str r3, [r7, #20] + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + 8005bf6: 687b ldr r3, [r7, #4] + 8005bf8: 019b lsls r3, r3, #6 + 8005bfa: f403 63f8 and.w r3, r3, #1984 ; 0x7c0 + 8005bfe: 697a ldr r2, [r7, #20] + 8005c00: 4313 orrs r3, r2 + 8005c02: 617b str r3, [r7, #20] + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + 8005c04: 697b ldr r3, [r7, #20] + 8005c06: f023 0302 bic.w r3, r3, #2 + 8005c0a: 617b str r3, [r7, #20] + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + 8005c0c: 697b ldr r3, [r7, #20] + 8005c0e: f043 0301 orr.w r3, r3, #1 + 8005c12: 617b str r3, [r7, #20] + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + 8005c14: 68fb ldr r3, [r7, #12] + 8005c16: 681b ldr r3, [r3, #0] + 8005c18: 697a ldr r2, [r7, #20] + 8005c1a: 611a str r2, [r3, #16] + + + tickstart = HAL_GetTick(); + 8005c1c: f7fe fe2a bl 8004874 + 8005c20: 6138 str r0, [r7, #16] + + /* Check for the Busy flag */ + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + 8005c22: e00d b.n 8005c40 + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PHY_READ_TO) + 8005c24: f7fe fe26 bl 8004874 + 8005c28: 4602 mov r2, r0 + 8005c2a: 693b ldr r3, [r7, #16] + 8005c2c: 1ad3 subs r3, r2, r3 + 8005c2e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8005c32: d301 bcc.n 8005c38 + { + return HAL_ERROR; + 8005c34: 2301 movs r3, #1 + 8005c36: e010 b.n 8005c5a + } + + tmpreg1 = heth->Instance->MACMIIAR; + 8005c38: 68fb ldr r3, [r7, #12] + 8005c3a: 681b ldr r3, [r3, #0] + 8005c3c: 691b ldr r3, [r3, #16] + 8005c3e: 617b str r3, [r7, #20] + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + 8005c40: 697b ldr r3, [r7, #20] + 8005c42: f003 0301 and.w r3, r3, #1 + 8005c46: 2b00 cmp r3, #0 + 8005c48: d1ec bne.n 8005c24 + } + + /* Get MACMIIDR value */ + *pRegValue = (uint16_t)(heth->Instance->MACMIIDR); + 8005c4a: 68fb ldr r3, [r7, #12] + 8005c4c: 681b ldr r3, [r3, #0] + 8005c4e: 695b ldr r3, [r3, #20] + 8005c50: b29b uxth r3, r3 + 8005c52: 461a mov r2, r3 + 8005c54: 683b ldr r3, [r7, #0] + 8005c56: 601a str r2, [r3, #0] + + return HAL_OK; + 8005c58: 2300 movs r3, #0 +} + 8005c5a: 4618 mov r0, r3 + 8005c5c: 3718 adds r7, #24 + 8005c5e: 46bd mov sp, r7 + 8005c60: bd80 pop {r7, pc} + +08005c62 : + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + 8005c62: b580 push {r7, lr} + 8005c64: b086 sub sp, #24 + 8005c66: af00 add r7, sp, #0 + 8005c68: 60f8 str r0, [r7, #12] + 8005c6a: 60b9 str r1, [r7, #8] + 8005c6c: 607a str r2, [r7, #4] + 8005c6e: 603b str r3, [r7, #0] + uint32_t tmpreg1; + uint32_t tickstart; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + 8005c70: 68fb ldr r3, [r7, #12] + 8005c72: 681b ldr r3, [r3, #0] + 8005c74: 691b ldr r3, [r3, #16] + 8005c76: 617b str r3, [r7, #20] + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + 8005c78: 697b ldr r3, [r7, #20] + 8005c7a: f003 031c and.w r3, r3, #28 + 8005c7e: 617b str r3, [r7, #20] + + /* Prepare the MII register address value */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + 8005c80: 68bb ldr r3, [r7, #8] + 8005c82: 02db lsls r3, r3, #11 + 8005c84: b29b uxth r3, r3 + 8005c86: 697a ldr r2, [r7, #20] + 8005c88: 4313 orrs r3, r2 + 8005c8a: 617b str r3, [r7, #20] + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + 8005c8c: 687b ldr r3, [r7, #4] + 8005c8e: 019b lsls r3, r3, #6 + 8005c90: f403 63f8 and.w r3, r3, #1984 ; 0x7c0 + 8005c94: 697a ldr r2, [r7, #20] + 8005c96: 4313 orrs r3, r2 + 8005c98: 617b str r3, [r7, #20] + tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ + 8005c9a: 697b ldr r3, [r7, #20] + 8005c9c: f043 0302 orr.w r3, r3, #2 + 8005ca0: 617b str r3, [r7, #20] + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + 8005ca2: 697b ldr r3, [r7, #20] + 8005ca4: f043 0301 orr.w r3, r3, #1 + 8005ca8: 617b str r3, [r7, #20] + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = (uint16_t)RegValue; + 8005caa: 683b ldr r3, [r7, #0] + 8005cac: b29a uxth r2, r3 + 8005cae: 68fb ldr r3, [r7, #12] + 8005cb0: 681b ldr r3, [r3, #0] + 8005cb2: 615a str r2, [r3, #20] + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + 8005cb4: 68fb ldr r3, [r7, #12] + 8005cb6: 681b ldr r3, [r3, #0] + 8005cb8: 697a ldr r2, [r7, #20] + 8005cba: 611a str r2, [r3, #16] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8005cbc: f7fe fdda bl 8004874 + 8005cc0: 6138 str r0, [r7, #16] + + /* Check for the Busy flag */ + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + 8005cc2: e00d b.n 8005ce0 + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO) + 8005cc4: f7fe fdd6 bl 8004874 + 8005cc8: 4602 mov r2, r0 + 8005cca: 693b ldr r3, [r7, #16] + 8005ccc: 1ad3 subs r3, r2, r3 + 8005cce: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8005cd2: d301 bcc.n 8005cd8 + { + return HAL_ERROR; + 8005cd4: 2301 movs r3, #1 + 8005cd6: e009 b.n 8005cec + } + + tmpreg1 = heth->Instance->MACMIIAR; + 8005cd8: 68fb ldr r3, [r7, #12] + 8005cda: 681b ldr r3, [r3, #0] + 8005cdc: 691b ldr r3, [r3, #16] + 8005cde: 617b str r3, [r7, #20] + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + 8005ce0: 697b ldr r3, [r7, #20] + 8005ce2: f003 0301 and.w r3, r3, #1 + 8005ce6: 2b00 cmp r3, #0 + 8005ce8: d1ec bne.n 8005cc4 + } + + return HAL_OK; + 8005cea: 2300 movs r3, #0 +} + 8005cec: 4618 mov r0, r3 + 8005cee: 3718 adds r7, #24 + 8005cf0: 46bd mov sp, r7 + 8005cf2: bd80 pop {r7, pc} + +08005cf4 : + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 8005cf4: b480 push {r7} + 8005cf6: b083 sub sp, #12 + 8005cf8: af00 add r7, sp, #0 + 8005cfa: 6078 str r0, [r7, #4] + 8005cfc: 6039 str r1, [r7, #0] + if (macconf == NULL) + 8005cfe: 683b ldr r3, [r7, #0] + 8005d00: 2b00 cmp r3, #0 + 8005d02: d101 bne.n 8005d08 + { + return HAL_ERROR; + 8005d04: 2301 movs r3, #1 + 8005d06: e0d9 b.n 8005ebc + } + + /* Get MAC parameters */ + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + 8005d08: 687b ldr r3, [r7, #4] + 8005d0a: 681b ldr r3, [r3, #0] + 8005d0c: 681b ldr r3, [r3, #0] + 8005d0e: f003 0310 and.w r3, r3, #16 + 8005d12: 2b00 cmp r3, #0 + 8005d14: bf14 ite ne + 8005d16: 2301 movne r3, #1 + 8005d18: 2300 moveq r3, #0 + 8005d1a: b2db uxtb r3, r3 + 8005d1c: 461a mov r2, r3 + 8005d1e: 683b ldr r3, [r7, #0] + 8005d20: f883 2028 strb.w r2, [r3, #40] ; 0x28 + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + 8005d24: 687b ldr r3, [r7, #4] + 8005d26: 681b ldr r3, [r3, #0] + 8005d28: 681b ldr r3, [r3, #0] + 8005d2a: f003 0260 and.w r2, r3, #96 ; 0x60 + 8005d2e: 683b ldr r3, [r7, #0] + 8005d30: 625a str r2, [r3, #36] ; 0x24 + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_RD) >> 9) == 0U) ? ENABLE : DISABLE; + 8005d32: 687b ldr r3, [r7, #4] + 8005d34: 681b ldr r3, [r3, #0] + 8005d36: 681b ldr r3, [r3, #0] + 8005d38: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005d3c: 2b00 cmp r3, #0 + 8005d3e: bf0c ite eq + 8005d40: 2301 moveq r3, #1 + 8005d42: 2300 movne r3, #0 + 8005d44: b2db uxtb r3, r3 + 8005d46: 461a mov r2, r3 + 8005d48: 683b ldr r3, [r7, #0] + 8005d4a: f883 2020 strb.w r2, [r3, #32] + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U) + 8005d4e: 687b ldr r3, [r7, #4] + 8005d50: 681b ldr r3, [r3, #0] + 8005d52: 681b ldr r3, [r3, #0] + 8005d54: f403 3380 and.w r3, r3, #65536 ; 0x10000 + ? ENABLE : DISABLE; + 8005d58: 2b00 cmp r3, #0 + 8005d5a: bf14 ite ne + 8005d5c: 2301 movne r3, #1 + 8005d5e: 2300 moveq r3, #0 + 8005d60: b2db uxtb r3, r3 + 8005d62: 461a mov r2, r3 + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U) + 8005d64: 683b ldr r3, [r7, #0] + 8005d66: 77da strb r2, [r3, #31] + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ROD) >> 13) == 0U) ? ENABLE : DISABLE; + 8005d68: 687b ldr r3, [r7, #4] + 8005d6a: 681b ldr r3, [r3, #0] + 8005d6c: 681b ldr r3, [r3, #0] + 8005d6e: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8005d72: 2b00 cmp r3, #0 + 8005d74: bf0c ite eq + 8005d76: 2301 moveq r3, #1 + 8005d78: 2300 movne r3, #0 + 8005d7a: b2db uxtb r3, r3 + 8005d7c: 461a mov r2, r3 + 8005d7e: 683b ldr r3, [r7, #0] + 8005d80: 779a strb r2, [r3, #30] + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + 8005d82: 687b ldr r3, [r7, #4] + 8005d84: 681b ldr r3, [r3, #0] + 8005d86: 681b ldr r3, [r3, #0] + 8005d88: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8005d8c: 2b00 cmp r3, #0 + 8005d8e: bf14 ite ne + 8005d90: 2301 movne r3, #1 + 8005d92: 2300 moveq r3, #0 + 8005d94: b2db uxtb r3, r3 + 8005d96: 461a mov r2, r3 + 8005d98: 683b ldr r3, [r7, #0] + 8005d9a: 771a strb r2, [r3, #28] + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + 8005d9c: 687b ldr r3, [r7, #4] + 8005d9e: 681b ldr r3, [r3, #0] + 8005da0: 681b ldr r3, [r3, #0] + 8005da2: f403 6200 and.w r2, r3, #2048 ; 0x800 + 8005da6: 683b ldr r3, [r7, #0] + 8005da8: 619a str r2, [r3, #24] + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + 8005daa: 687b ldr r3, [r7, #4] + 8005dac: 681b ldr r3, [r3, #0] + 8005dae: 681b ldr r3, [r3, #0] + 8005db0: f403 4280 and.w r2, r3, #16384 ; 0x4000 + 8005db4: 683b ldr r3, [r7, #0] + 8005db6: 615a str r2, [r3, #20] + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 22) == 0U) ? ENABLE : DISABLE; + 8005db8: 687b ldr r3, [r7, #4] + 8005dba: 681b ldr r3, [r3, #0] + 8005dbc: 681b ldr r3, [r3, #0] + 8005dbe: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8005dc2: 2b00 cmp r3, #0 + 8005dc4: bf0c ite eq + 8005dc6: 2301 moveq r3, #1 + 8005dc8: 2300 movne r3, #0 + 8005dca: b2db uxtb r3, r3 + 8005dcc: 461a mov r2, r3 + 8005dce: 683b ldr r3, [r7, #0] + 8005dd0: 745a strb r2, [r3, #17] + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE; + 8005dd2: 687b ldr r3, [r7, #4] + 8005dd4: 681b ldr r3, [r3, #0] + 8005dd6: 681b ldr r3, [r3, #0] + 8005dd8: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8005ddc: 2b00 cmp r3, #0 + 8005dde: bf0c ite eq + 8005de0: 2301 moveq r3, #1 + 8005de2: 2300 movne r3, #0 + 8005de4: b2db uxtb r3, r3 + 8005de6: 461a mov r2, r3 + 8005de8: 683b ldr r3, [r7, #0] + 8005dea: 741a strb r2, [r3, #16] + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE; + 8005dec: 687b ldr r3, [r7, #4] + 8005dee: 681b ldr r3, [r3, #0] + 8005df0: 681b ldr r3, [r3, #0] + 8005df2: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005df6: 2b00 cmp r3, #0 + 8005df8: bf14 ite ne + 8005dfa: 2301 movne r3, #1 + 8005dfc: 2300 moveq r3, #0 + 8005dfe: b2db uxtb r3, r3 + 8005e00: 461a mov r2, r3 + 8005e02: 683b ldr r3, [r7, #0] + 8005e04: 73da strb r2, [r3, #15] + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG); + 8005e06: 687b ldr r3, [r7, #4] + 8005e08: 681b ldr r3, [r3, #0] + 8005e0a: 681b ldr r3, [r3, #0] + 8005e0c: f403 2260 and.w r2, r3, #917504 ; 0xe0000 + 8005e10: 683b ldr r3, [r7, #0] + 8005e12: 609a str r2, [r3, #8] + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE; + 8005e14: 687b ldr r3, [r7, #4] + 8005e16: 681b ldr r3, [r3, #0] + 8005e18: 681b ldr r3, [r3, #0] + 8005e1a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8005e1e: 2b00 cmp r3, #0 + 8005e20: bf14 ite ne + 8005e22: 2301 movne r3, #1 + 8005e24: 2300 moveq r3, #0 + 8005e26: b2db uxtb r3, r3 + 8005e28: 461a mov r2, r3 + 8005e2a: 683b ldr r3, [r7, #0] + 8005e2c: 711a strb r2, [r3, #4] + + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE; + 8005e2e: 687b ldr r3, [r7, #4] + 8005e30: 681b ldr r3, [r3, #0] + 8005e32: 699b ldr r3, [r3, #24] + 8005e34: f003 0302 and.w r3, r3, #2 + 8005e38: 2b00 cmp r3, #0 + 8005e3a: bf14 ite ne + 8005e3c: 2301 movne r3, #1 + 8005e3e: 2300 moveq r3, #0 + 8005e40: b2db uxtb r3, r3 + 8005e42: 461a mov r2, r3 + 8005e44: 683b ldr r3, [r7, #0] + 8005e46: f883 2054 strb.w r2, [r3, #84] ; 0x54 + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE; + 8005e4a: 687b ldr r3, [r7, #4] + 8005e4c: 681b ldr r3, [r3, #0] + 8005e4e: 699b ldr r3, [r3, #24] + 8005e50: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005e54: 2b00 cmp r3, #0 + 8005e56: bf0c ite eq + 8005e58: 2301 moveq r3, #1 + 8005e5a: 2300 movne r3, #0 + 8005e5c: b2db uxtb r3, r3 + 8005e5e: 461a mov r2, r3 + 8005e60: 683b ldr r3, [r7, #0] + 8005e62: f883 204c strb.w r2, [r3, #76] ; 0x4c + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT); + 8005e66: 687b ldr r3, [r7, #4] + 8005e68: 681b ldr r3, [r3, #0] + 8005e6a: 699b ldr r3, [r3, #24] + 8005e6c: f003 0230 and.w r2, r3, #48 ; 0x30 + 8005e70: 683b ldr r3, [r7, #0] + 8005e72: 651a str r2, [r3, #80] ; 0x50 + macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16); + 8005e74: 687b ldr r3, [r7, #4] + 8005e76: 681b ldr r3, [r3, #0] + 8005e78: 699b ldr r3, [r3, #24] + 8005e7a: 0c1b lsrs r3, r3, #16 + 8005e7c: b29a uxth r2, r3 + 8005e7e: 683b ldr r3, [r7, #0] + 8005e80: 649a str r2, [r3, #72] ; 0x48 + macconf->ReceiveFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) >> 2U) > 0U) ? ENABLE : DISABLE; + 8005e82: 687b ldr r3, [r7, #4] + 8005e84: 681b ldr r3, [r3, #0] + 8005e86: 699b ldr r3, [r3, #24] + 8005e88: f003 0304 and.w r3, r3, #4 + 8005e8c: 2b00 cmp r3, #0 + 8005e8e: bf14 ite ne + 8005e90: 2301 movne r3, #1 + 8005e92: 2300 moveq r3, #0 + 8005e94: b2db uxtb r3, r3 + 8005e96: 461a mov r2, r3 + 8005e98: 683b ldr r3, [r7, #0] + 8005e9a: f883 2056 strb.w r2, [r3, #86] ; 0x56 + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U) + 8005e9e: 687b ldr r3, [r7, #4] + 8005ea0: 681b ldr r3, [r3, #0] + 8005ea2: 699b ldr r3, [r3, #24] + 8005ea4: f003 0308 and.w r3, r3, #8 + ? ENABLE : DISABLE; + 8005ea8: 2b00 cmp r3, #0 + 8005eaa: bf14 ite ne + 8005eac: 2301 movne r3, #1 + 8005eae: 2300 moveq r3, #0 + 8005eb0: b2db uxtb r3, r3 + 8005eb2: 461a mov r2, r3 + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U) + 8005eb4: 683b ldr r3, [r7, #0] + 8005eb6: f883 2055 strb.w r2, [r3, #85] ; 0x55 + + return HAL_OK; + 8005eba: 2300 movs r3, #0 +} + 8005ebc: 4618 mov r0, r3 + 8005ebe: 370c adds r7, #12 + 8005ec0: 46bd mov sp, r7 + 8005ec2: f85d 7b04 ldr.w r7, [sp], #4 + 8005ec6: 4770 bx lr + +08005ec8 : + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 8005ec8: b580 push {r7, lr} + 8005eca: b082 sub sp, #8 + 8005ecc: af00 add r7, sp, #0 + 8005ece: 6078 str r0, [r7, #4] + 8005ed0: 6039 str r1, [r7, #0] + if (macconf == NULL) + 8005ed2: 683b ldr r3, [r7, #0] + 8005ed4: 2b00 cmp r3, #0 + 8005ed6: d101 bne.n 8005edc + { + return HAL_ERROR; + 8005ed8: 2301 movs r3, #1 + 8005eda: e00b b.n 8005ef4 + } + + if (heth->gState == HAL_ETH_STATE_READY) + 8005edc: 687b ldr r3, [r7, #4] + 8005ede: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8005ee2: 2b10 cmp r3, #16 + 8005ee4: d105 bne.n 8005ef2 + { + ETH_SetMACConfig(heth, macconf); + 8005ee6: 6839 ldr r1, [r7, #0] + 8005ee8: 6878 ldr r0, [r7, #4] + 8005eea: f000 f88f bl 800600c + + return HAL_OK; + 8005eee: 2300 movs r3, #0 + 8005ef0: e000 b.n 8005ef4 + } + else + { + return HAL_ERROR; + 8005ef2: 2301 movs r3, #1 + } +} + 8005ef4: 4618 mov r0, r3 + 8005ef6: 3708 adds r7, #8 + 8005ef8: 46bd mov sp, r7 + 8005efa: bd80 pop {r7, pc} + +08005efc : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) +{ + 8005efc: b580 push {r7, lr} + 8005efe: b084 sub sp, #16 + 8005f00: af00 add r7, sp, #0 + 8005f02: 6078 str r0, [r7, #4] + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = (heth->Instance)->MACMIIAR; + 8005f04: 687b ldr r3, [r7, #4] + 8005f06: 681b ldr r3, [r3, #0] + 8005f08: 691b ldr r3, [r3, #16] + 8005f0a: 60fb str r3, [r7, #12] + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= ETH_MACMIIAR_CR_MASK; + 8005f0c: 68fb ldr r3, [r7, #12] + 8005f0e: f023 031c bic.w r3, r3, #28 + 8005f12: 60fb str r3, [r7, #12] + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + 8005f14: f002 f9e0 bl 80082d8 + 8005f18: 60b8 str r0, [r7, #8] + + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) + 8005f1a: 68bb ldr r3, [r7, #8] + 8005f1c: 4a1d ldr r2, [pc, #116] ; (8005f94 ) + 8005f1e: 4293 cmp r3, r2 + 8005f20: d908 bls.n 8005f34 + 8005f22: 68bb ldr r3, [r7, #8] + 8005f24: 4a1c ldr r2, [pc, #112] ; (8005f98 ) + 8005f26: 4293 cmp r3, r2 + 8005f28: d804 bhi.n 8005f34 + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + 8005f2a: 68fb ldr r3, [r7, #12] + 8005f2c: f043 0308 orr.w r3, r3, #8 + 8005f30: 60fb str r3, [r7, #12] + 8005f32: e027 b.n 8005f84 + } + else if ((hclk >= 35000000U) && (hclk < 60000000U)) + 8005f34: 68bb ldr r3, [r7, #8] + 8005f36: 4a18 ldr r2, [pc, #96] ; (8005f98 ) + 8005f38: 4293 cmp r3, r2 + 8005f3a: d908 bls.n 8005f4e + 8005f3c: 68bb ldr r3, [r7, #8] + 8005f3e: 4a17 ldr r2, [pc, #92] ; (8005f9c ) + 8005f40: 4293 cmp r3, r2 + 8005f42: d204 bcs.n 8005f4e + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + 8005f44: 68fb ldr r3, [r7, #12] + 8005f46: f043 030c orr.w r3, r3, #12 + 8005f4a: 60fb str r3, [r7, #12] + 8005f4c: e01a b.n 8005f84 + } + else if ((hclk >= 60000000U) && (hclk < 100000000U)) + 8005f4e: 68bb ldr r3, [r7, #8] + 8005f50: 4a12 ldr r2, [pc, #72] ; (8005f9c ) + 8005f52: 4293 cmp r3, r2 + 8005f54: d303 bcc.n 8005f5e + 8005f56: 68bb ldr r3, [r7, #8] + 8005f58: 4a11 ldr r2, [pc, #68] ; (8005fa0 ) + 8005f5a: 4293 cmp r3, r2 + 8005f5c: d911 bls.n 8005f82 + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if ((hclk >= 100000000U) && (hclk < 150000000U)) + 8005f5e: 68bb ldr r3, [r7, #8] + 8005f60: 4a0f ldr r2, [pc, #60] ; (8005fa0 ) + 8005f62: 4293 cmp r3, r2 + 8005f64: d908 bls.n 8005f78 + 8005f66: 68bb ldr r3, [r7, #8] + 8005f68: 4a0e ldr r2, [pc, #56] ; (8005fa4 ) + 8005f6a: 4293 cmp r3, r2 + 8005f6c: d804 bhi.n 8005f78 + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + 8005f6e: 68fb ldr r3, [r7, #12] + 8005f70: f043 0304 orr.w r3, r3, #4 + 8005f74: 60fb str r3, [r7, #12] + 8005f76: e005 b.n 8005f84 + } + else /* ((hclk >= 150000000)&&(hclk <= 183000000))*/ + { + /* CSR Clock Range between 150-183 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + 8005f78: 68fb ldr r3, [r7, #12] + 8005f7a: f043 0310 orr.w r3, r3, #16 + 8005f7e: 60fb str r3, [r7, #12] + 8005f80: e000 b.n 8005f84 + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + 8005f82: bf00 nop + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg; + 8005f84: 687b ldr r3, [r7, #4] + 8005f86: 681b ldr r3, [r3, #0] + 8005f88: 68fa ldr r2, [r7, #12] + 8005f8a: 611a str r2, [r3, #16] +} + 8005f8c: bf00 nop + 8005f8e: 3710 adds r7, #16 + 8005f90: 46bd mov sp, r7 + 8005f92: bd80 pop {r7, pc} + 8005f94: 01312cff .word 0x01312cff + 8005f98: 02160ebf .word 0x02160ebf + 8005f9c: 03938700 .word 0x03938700 + 8005fa0: 05f5e0ff .word 0x05f5e0ff + 8005fa4: 08f0d17f .word 0x08f0d17f + +08005fa8 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH DMA Error Code + */ +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +{ + 8005fa8: b480 push {r7} + 8005faa: b083 sub sp, #12 + 8005fac: af00 add r7, sp, #0 + 8005fae: 6078 str r0, [r7, #4] + return heth->DMAErrorCode; + 8005fb0: 687b ldr r3, [r7, #4] + 8005fb2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c +} + 8005fb6: 4618 mov r0, r3 + 8005fb8: 370c adds r7, #12 + 8005fba: 46bd mov sp, r7 + 8005fbc: f85d 7b04 ldr.w r7, [sp], #4 + 8005fc0: 4770 bx lr + +08005fc2 : + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +{ + 8005fc2: b580 push {r7, lr} + 8005fc4: b084 sub sp, #16 + 8005fc6: af00 add r7, sp, #0 + 8005fc8: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg = 0; + 8005fca: 2300 movs r3, #0 + 8005fcc: 60fb str r3, [r7, #12] + + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + 8005fce: 687b ldr r3, [r7, #4] + 8005fd0: 681b ldr r3, [r3, #0] + 8005fd2: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005fd6: 699b ldr r3, [r3, #24] + 8005fd8: 687a ldr r2, [r7, #4] + 8005fda: 6812 ldr r2, [r2, #0] + 8005fdc: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8005fe0: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8005fe4: 6193 str r3, [r2, #24] + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = (heth->Instance)->DMAOMR; + 8005fe6: 687b ldr r3, [r7, #4] + 8005fe8: 681b ldr r3, [r3, #0] + 8005fea: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8005fee: 699b ldr r3, [r3, #24] + 8005ff0: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 8005ff2: 2001 movs r0, #1 + 8005ff4: f7fe fc4a bl 800488c + (heth->Instance)->DMAOMR = tmpreg; + 8005ff8: 687b ldr r3, [r7, #4] + 8005ffa: 681a ldr r2, [r3, #0] + 8005ffc: 68fb ldr r3, [r7, #12] + 8005ffe: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8006002: 6193 str r3, [r2, #24] +} + 8006004: bf00 nop + 8006006: 3710 adds r7, #16 + 8006008: 46bd mov sp, r7 + 800600a: bd80 pop {r7, pc} + +0800600c : + +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 800600c: b580 push {r7, lr} + 800600e: b084 sub sp, #16 + 8006010: af00 add r7, sp, #0 + 8006012: 6078 str r0, [r7, #4] + 8006014: 6039 str r1, [r7, #0] + uint32_t tmpreg1; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + 8006016: 687b ldr r3, [r7, #4] + 8006018: 681b ldr r3, [r3, #0] + 800601a: 681b ldr r3, [r3, #0] + 800601c: 60fb str r3, [r7, #12] + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg1 &= ETH_MACCR_CLEAR_MASK; + 800601e: 68fa ldr r2, [r7, #12] + 8006020: 4b51 ldr r3, [pc, #324] ; (8006168 ) + 8006022: 4013 ands r3, r2 + 8006024: 60fb str r3, [r7, #12] + + tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | + 8006026: 683b ldr r3, [r7, #0] + 8006028: 7c1b ldrb r3, [r3, #16] + 800602a: 2b00 cmp r3, #0 + 800602c: d102 bne.n 8006034 + 800602e: f44f 0200 mov.w r2, #8388608 ; 0x800000 + 8006032: e000 b.n 8006036 + 8006034: 2200 movs r2, #0 + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | + 8006036: 683b ldr r3, [r7, #0] + 8006038: 7c5b ldrb r3, [r3, #17] + 800603a: 2b00 cmp r3, #0 + 800603c: d102 bne.n 8006044 + 800603e: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 8006042: e000 b.n 8006046 + 8006044: 2300 movs r3, #0 + tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | + 8006046: 431a orrs r2, r3 + (uint32_t)macconf->InterPacketGapVal | + 8006048: 683b ldr r3, [r7, #0] + 800604a: 689b ldr r3, [r3, #8] + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | + 800604c: 431a orrs r2, r3 + ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | + 800604e: 683b ldr r3, [r7, #0] + 8006050: 7fdb ldrb r3, [r3, #31] + 8006052: 041b lsls r3, r3, #16 + (uint32_t)macconf->InterPacketGapVal | + 8006054: 431a orrs r2, r3 + macconf->Speed | + 8006056: 683b ldr r3, [r7, #0] + 8006058: 695b ldr r3, [r3, #20] + ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | + 800605a: 4313 orrs r3, r2 + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | + 800605c: 683a ldr r2, [r7, #0] + 800605e: 7f92 ldrb r2, [r2, #30] + 8006060: 2a00 cmp r2, #0 + 8006062: d102 bne.n 800606a + 8006064: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8006068: e000 b.n 800606c + 800606a: 2200 movs r2, #0 + macconf->Speed | + 800606c: 431a orrs r2, r3 + ((uint32_t)macconf->LoopbackMode << 12U) | + 800606e: 683b ldr r3, [r7, #0] + 8006070: 7f1b ldrb r3, [r3, #28] + 8006072: 031b lsls r3, r3, #12 + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | + 8006074: 431a orrs r2, r3 + macconf->DuplexMode | + 8006076: 683b ldr r3, [r7, #0] + 8006078: 699b ldr r3, [r3, #24] + ((uint32_t)macconf->LoopbackMode << 12U) | + 800607a: 431a orrs r2, r3 + ((uint32_t)macconf->ChecksumOffload << 10U) | + 800607c: 683b ldr r3, [r7, #0] + 800607e: 791b ldrb r3, [r3, #4] + 8006080: 029b lsls r3, r3, #10 + macconf->DuplexMode | + 8006082: 4313 orrs r3, r2 + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | + 8006084: 683a ldr r2, [r7, #0] + 8006086: f892 2020 ldrb.w r2, [r2, #32] + 800608a: 2a00 cmp r2, #0 + 800608c: d102 bne.n 8006094 + 800608e: f44f 7200 mov.w r2, #512 ; 0x200 + 8006092: e000 b.n 8006096 + 8006094: 2200 movs r2, #0 + ((uint32_t)macconf->ChecksumOffload << 10U) | + 8006096: 431a orrs r2, r3 + ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | + 8006098: 683b ldr r3, [r7, #0] + 800609a: 7bdb ldrb r3, [r3, #15] + 800609c: 01db lsls r3, r3, #7 + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | + 800609e: 431a orrs r2, r3 + macconf->BackOffLimit | + 80060a0: 683b ldr r3, [r7, #0] + 80060a2: 6a5b ldr r3, [r3, #36] ; 0x24 + ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | + 80060a4: 431a orrs r2, r3 + ((uint32_t)macconf->DeferralCheck << 4U)); + 80060a6: 683b ldr r3, [r7, #0] + 80060a8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80060ac: 011b lsls r3, r3, #4 + tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | + 80060ae: 4313 orrs r3, r2 + 80060b0: 68fa ldr r2, [r7, #12] + 80060b2: 4313 orrs r3, r2 + 80060b4: 60fb str r3, [r7, #12] + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + 80060b6: 687b ldr r3, [r7, #4] + 80060b8: 681b ldr r3, [r3, #0] + 80060ba: 68fa ldr r2, [r7, #12] + 80060bc: 601a str r2, [r3, #0] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + 80060be: 687b ldr r3, [r7, #4] + 80060c0: 681b ldr r3, [r3, #0] + 80060c2: 681b ldr r3, [r3, #0] + 80060c4: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 80060c6: 2001 movs r0, #1 + 80060c8: f7fe fbe0 bl 800488c + (heth->Instance)->MACCR = tmpreg1; + 80060cc: 687b ldr r3, [r7, #4] + 80060ce: 681b ldr r3, [r3, #0] + 80060d0: 68fa ldr r2, [r7, #12] + 80060d2: 601a str r2, [r3, #0] + + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + 80060d4: 687b ldr r3, [r7, #4] + 80060d6: 681b ldr r3, [r3, #0] + 80060d8: 699b ldr r3, [r3, #24] + 80060da: 60fb str r3, [r7, #12] + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + 80060dc: 68fa ldr r2, [r7, #12] + 80060de: f64f 7341 movw r3, #65345 ; 0xff41 + 80060e2: 4013 ands r3, r2 + 80060e4: 60fb str r3, [r7, #12] + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + 80060e6: 683b ldr r3, [r7, #0] + 80060e8: 6c9b ldr r3, [r3, #72] ; 0x48 + 80060ea: 041b lsls r3, r3, #16 + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | + 80060ec: 683a ldr r2, [r7, #0] + 80060ee: f892 204c ldrb.w r2, [r2, #76] ; 0x4c + 80060f2: 2a00 cmp r2, #0 + 80060f4: d101 bne.n 80060fa + 80060f6: 2280 movs r2, #128 ; 0x80 + 80060f8: e000 b.n 80060fc + 80060fa: 2200 movs r2, #0 + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + 80060fc: 431a orrs r2, r3 + macconf->PauseLowThreshold | + 80060fe: 683b ldr r3, [r7, #0] + 8006100: 6d1b ldr r3, [r3, #80] ; 0x50 + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | + 8006102: 4313 orrs r3, r2 + ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | + 8006104: 683a ldr r2, [r7, #0] + 8006106: f892 2055 ldrb.w r2, [r2, #85] ; 0x55 + 800610a: 2a01 cmp r2, #1 + 800610c: d101 bne.n 8006112 + 800610e: 2208 movs r2, #8 + 8006110: e000 b.n 8006114 + 8006112: 2200 movs r2, #0 + macconf->PauseLowThreshold | + 8006114: 4313 orrs r3, r2 + ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | + 8006116: 683a ldr r2, [r7, #0] + 8006118: f892 2056 ldrb.w r2, [r2, #86] ; 0x56 + 800611c: 2a01 cmp r2, #1 + 800611e: d101 bne.n 8006124 + 8006120: 2204 movs r2, #4 + 8006122: e000 b.n 8006126 + 8006124: 2200 movs r2, #0 + ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | + 8006126: 4313 orrs r3, r2 + ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); + 8006128: 683a ldr r2, [r7, #0] + 800612a: f892 2054 ldrb.w r2, [r2, #84] ; 0x54 + 800612e: 2a01 cmp r2, #1 + 8006130: d101 bne.n 8006136 + 8006132: 2202 movs r2, #2 + 8006134: e000 b.n 8006138 + 8006136: 2200 movs r2, #0 + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + 8006138: 4313 orrs r3, r2 + 800613a: 68fa ldr r2, [r7, #12] + 800613c: 4313 orrs r3, r2 + 800613e: 60fb str r3, [r7, #12] + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + 8006140: 687b ldr r3, [r7, #4] + 8006142: 681b ldr r3, [r3, #0] + 8006144: 68fa ldr r2, [r7, #12] + 8006146: 619a str r2, [r3, #24] + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + 8006148: 687b ldr r3, [r7, #4] + 800614a: 681b ldr r3, [r3, #0] + 800614c: 699b ldr r3, [r3, #24] + 800614e: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 8006150: 2001 movs r0, #1 + 8006152: f7fe fb9b bl 800488c + (heth->Instance)->MACFCR = tmpreg1; + 8006156: 687b ldr r3, [r7, #4] + 8006158: 681b ldr r3, [r3, #0] + 800615a: 68fa ldr r2, [r7, #12] + 800615c: 619a str r2, [r3, #24] +} + 800615e: bf00 nop + 8006160: 3710 adds r7, #16 + 8006162: 46bd mov sp, r7 + 8006164: bd80 pop {r7, pc} + 8006166: bf00 nop + 8006168: ff20810f .word 0xff20810f + +0800616c : + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + 800616c: b580 push {r7, lr} + 800616e: b084 sub sp, #16 + 8006170: af00 add r7, sp, #0 + 8006172: 6078 str r0, [r7, #4] + 8006174: 6039 str r1, [r7, #0] + uint32_t tmpreg1; + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + 8006176: 687b ldr r3, [r7, #4] + 8006178: 681b ldr r3, [r3, #0] + 800617a: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800617e: 699b ldr r3, [r3, #24] + 8006180: 60fb str r3, [r7, #12] + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + 8006182: 68fa ldr r2, [r7, #12] + 8006184: 4b3d ldr r3, [pc, #244] ; (800627c ) + 8006186: 4013 ands r3, r2 + 8006188: 60fb str r3, [r7, #12] + + tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | + 800618a: 683b ldr r3, [r7, #0] + 800618c: 7b1b ldrb r3, [r3, #12] + 800618e: 2b00 cmp r3, #0 + 8006190: d102 bne.n 8006198 + 8006192: f04f 6280 mov.w r2, #67108864 ; 0x4000000 + 8006196: e000 b.n 800619a + 8006198: 2200 movs r2, #0 + ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | + 800619a: 683b ldr r3, [r7, #0] + 800619c: 7b5b ldrb r3, [r3, #13] + 800619e: 065b lsls r3, r3, #25 + tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | + 80061a0: 4313 orrs r3, r2 + ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | + 80061a2: 683a ldr r2, [r7, #0] + 80061a4: 7f52 ldrb r2, [r2, #29] + 80061a6: 2a00 cmp r2, #0 + 80061a8: d102 bne.n 80061b0 + 80061aa: f44f 1280 mov.w r2, #1048576 ; 0x100000 + 80061ae: e000 b.n 80061b2 + 80061b0: 2200 movs r2, #0 + ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | + 80061b2: 431a orrs r2, r3 + ((uint32_t)dmaconf->TransmitStoreForward << 21U) | + 80061b4: 683b ldr r3, [r7, #0] + 80061b6: 7b9b ldrb r3, [r3, #14] + 80061b8: 055b lsls r3, r3, #21 + ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | + 80061ba: 431a orrs r2, r3 + dmaconf->TransmitThresholdControl | + 80061bc: 683b ldr r3, [r7, #0] + 80061be: 695b ldr r3, [r3, #20] + ((uint32_t)dmaconf->TransmitStoreForward << 21U) | + 80061c0: 431a orrs r2, r3 + ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | + 80061c2: 683b ldr r3, [r7, #0] + 80061c4: 7f1b ldrb r3, [r3, #28] + 80061c6: 01db lsls r3, r3, #7 + dmaconf->TransmitThresholdControl | + 80061c8: 431a orrs r2, r3 + ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | + 80061ca: 683b ldr r3, [r7, #0] + 80061cc: 7f9b ldrb r3, [r3, #30] + 80061ce: 019b lsls r3, r3, #6 + ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | + 80061d0: 431a orrs r2, r3 + dmaconf->ReceiveThresholdControl | + 80061d2: 683b ldr r3, [r7, #0] + 80061d4: 6a1b ldr r3, [r3, #32] + ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | + 80061d6: 431a orrs r2, r3 + ((uint32_t)dmaconf->SecondFrameOperate << 2U)); + 80061d8: 683b ldr r3, [r7, #0] + 80061da: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 80061de: 009b lsls r3, r3, #2 + tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | + 80061e0: 4313 orrs r3, r2 + 80061e2: 68fa ldr r2, [r7, #12] + 80061e4: 4313 orrs r3, r2 + 80061e6: 60fb str r3, [r7, #12] + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + 80061e8: 687b ldr r3, [r7, #4] + 80061ea: 681b ldr r3, [r3, #0] + 80061ec: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80061f0: 461a mov r2, r3 + 80061f2: 68fb ldr r3, [r7, #12] + 80061f4: 6193 str r3, [r2, #24] + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + 80061f6: 687b ldr r3, [r7, #4] + 80061f8: 681b ldr r3, [r3, #0] + 80061fa: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80061fe: 699b ldr r3, [r3, #24] + 8006200: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 8006202: 2001 movs r0, #1 + 8006204: f7fe fb42 bl 800488c + (heth->Instance)->DMAOMR = tmpreg1; + 8006208: 687b ldr r3, [r7, #4] + 800620a: 681b ldr r3, [r3, #0] + 800620c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8006210: 461a mov r2, r3 + 8006212: 68fb ldr r3, [r7, #12] + 8006214: 6193 str r3, [r2, #24] + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | + 8006216: 683b ldr r3, [r7, #0] + 8006218: 791b ldrb r3, [r3, #4] + 800621a: 065a lsls r2, r3, #25 + dmaconf->BurstMode | + 800621c: 683b ldr r3, [r7, #0] + 800621e: 689b ldr r3, [r3, #8] + (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | + 8006220: 431a orrs r2, r3 + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or + 8006222: 683b ldr r3, [r7, #0] + 8006224: 699b ldr r3, [r3, #24] + dmaconf->BurstMode | + 8006226: 431a orrs r2, r3 + Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + 8006228: 683b ldr r3, [r7, #0] + 800622a: 691b ldr r3, [r3, #16] + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or + 800622c: 431a orrs r2, r3 + ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | + 800622e: 683b ldr r3, [r7, #0] + 8006230: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8006234: 01db lsls r3, r3, #7 + dmaconf->TxDMABurstLength | + 8006236: 431a orrs r2, r3 + (dmaconf->DescriptorSkipLength << 2U) | + 8006238: 683b ldr r3, [r7, #0] + 800623a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800623c: 009b lsls r3, r3, #2 + ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | + 800623e: 431a orrs r2, r3 + dmaconf->DMAArbitration | + 8006240: 683b ldr r3, [r7, #0] + 8006242: 681b ldr r3, [r3, #0] + (dmaconf->DescriptorSkipLength << 2U) | + 8006244: 4313 orrs r3, r2 + (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | + 8006246: 687a ldr r2, [r7, #4] + 8006248: 6812 ldr r2, [r2, #0] + 800624a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 800624e: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8006252: 6013 str r3, [r2, #0] + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + 8006254: 687b ldr r3, [r7, #4] + 8006256: 681b ldr r3, [r3, #0] + 8006258: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800625c: 681b ldr r3, [r3, #0] + 800625e: 60fb str r3, [r7, #12] + HAL_Delay(ETH_REG_WRITE_DELAY); + 8006260: 2001 movs r0, #1 + 8006262: f7fe fb13 bl 800488c + (heth->Instance)->DMABMR = tmpreg1; + 8006266: 687b ldr r3, [r7, #4] + 8006268: 681b ldr r3, [r3, #0] + 800626a: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800626e: 461a mov r2, r3 + 8006270: 68fb ldr r3, [r7, #12] + 8006272: 6013 str r3, [r2, #0] +} + 8006274: bf00 nop + 8006276: 3710 adds r7, #16 + 8006278: 46bd mov sp, r7 + 800627a: bd80 pop {r7, pc} + 800627c: f8de3f23 .word 0xf8de3f23 + +08006280 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + 8006280: b580 push {r7, lr} + 8006282: b0a6 sub sp, #152 ; 0x98 + 8006284: af00 add r7, sp, #0 + 8006286: 6078 str r0, [r7, #4] + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.Watchdog = ENABLE; + 8006288: 2301 movs r3, #1 + 800628a: f887 3044 strb.w r3, [r7, #68] ; 0x44 + macDefaultConf.Jabber = ENABLE; + 800628e: 2301 movs r3, #1 + 8006290: f887 3045 strb.w r3, [r7, #69] ; 0x45 + macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; + 8006294: 2300 movs r3, #0 + 8006296: 63fb str r3, [r7, #60] ; 0x3c + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + 8006298: 2300 movs r3, #0 + 800629a: f887 3053 strb.w r3, [r7, #83] ; 0x53 + macDefaultConf.ReceiveOwn = ENABLE; + 800629e: 2301 movs r3, #1 + 80062a0: f887 3052 strb.w r3, [r7, #82] ; 0x52 + macDefaultConf.LoopbackMode = DISABLE; + 80062a4: 2300 movs r3, #0 + 80062a6: f887 3050 strb.w r3, [r7, #80] ; 0x50 + macDefaultConf.ChecksumOffload = ENABLE; + 80062aa: 2301 movs r3, #1 + 80062ac: f887 3038 strb.w r3, [r7, #56] ; 0x38 + macDefaultConf.RetryTransmission = DISABLE; + 80062b0: 2300 movs r3, #0 + 80062b2: f887 3054 strb.w r3, [r7, #84] ; 0x54 + macDefaultConf.AutomaticPadCRCStrip = DISABLE; + 80062b6: 2300 movs r3, #0 + 80062b8: f887 3043 strb.w r3, [r7, #67] ; 0x43 + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + 80062bc: 2300 movs r3, #0 + 80062be: 65bb str r3, [r7, #88] ; 0x58 + macDefaultConf.DeferralCheck = DISABLE; + 80062c0: 2300 movs r3, #0 + 80062c2: f887 305c strb.w r3, [r7, #92] ; 0x5c + macDefaultConf.PauseTime = 0x0U; + 80062c6: 2300 movs r3, #0 + 80062c8: 67fb str r3, [r7, #124] ; 0x7c + macDefaultConf.ZeroQuantaPause = DISABLE; + 80062ca: 2300 movs r3, #0 + 80062cc: f887 3080 strb.w r3, [r7, #128] ; 0x80 + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + 80062d0: 2300 movs r3, #0 + 80062d2: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + macDefaultConf.ReceiveFlowControl = DISABLE; + 80062d6: 2300 movs r3, #0 + 80062d8: f887 308a strb.w r3, [r7, #138] ; 0x8a + macDefaultConf.TransmitFlowControl = DISABLE; + 80062dc: 2300 movs r3, #0 + 80062de: f887 3088 strb.w r3, [r7, #136] ; 0x88 + macDefaultConf.Speed = ETH_SPEED_100M; + 80062e2: f44f 4380 mov.w r3, #16384 ; 0x4000 + 80062e6: 64bb str r3, [r7, #72] ; 0x48 + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + 80062e8: f44f 6300 mov.w r3, #2048 ; 0x800 + 80062ec: 64fb str r3, [r7, #76] ; 0x4c + macDefaultConf.UnicastPausePacketDetect = DISABLE; + 80062ee: 2300 movs r3, #0 + 80062f0: f887 3089 strb.w r3, [r7, #137] ; 0x89 + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + 80062f4: f107 0334 add.w r3, r7, #52 ; 0x34 + 80062f8: 4619 mov r1, r3 + 80062fa: 6878 ldr r0, [r7, #4] + 80062fc: f7ff fe86 bl 800600c + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; + 8006300: 2301 movs r3, #1 + 8006302: 753b strb r3, [r7, #20] + dmaDefaultConf.ReceiveStoreForward = ENABLE; + 8006304: 2301 movs r3, #1 + 8006306: 757b strb r3, [r7, #21] + dmaDefaultConf.FlushRxPacket = ENABLE; + 8006308: 2301 movs r3, #1 + 800630a: f887 3025 strb.w r3, [r7, #37] ; 0x25 + dmaDefaultConf.TransmitStoreForward = ENABLE; + 800630e: 2301 movs r3, #1 + 8006310: 75bb strb r3, [r7, #22] + dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + 8006312: 2300 movs r3, #0 + 8006314: 61fb str r3, [r7, #28] + dmaDefaultConf.ForwardErrorFrames = DISABLE; + 8006316: 2300 movs r3, #0 + 8006318: f887 3024 strb.w r3, [r7, #36] ; 0x24 + dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; + 800631c: 2300 movs r3, #0 + 800631e: f887 3026 strb.w r3, [r7, #38] ; 0x26 + dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + 8006322: 2300 movs r3, #0 + 8006324: 62bb str r3, [r7, #40] ; 0x28 + dmaDefaultConf.SecondFrameOperate = ENABLE; + 8006326: 2301 movs r3, #1 + 8006328: f887 302c strb.w r3, [r7, #44] ; 0x2c + dmaDefaultConf.AddressAlignedBeats = ENABLE; + 800632c: 2301 movs r3, #1 + 800632e: 733b strb r3, [r7, #12] + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + 8006330: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8006334: 613b str r3, [r7, #16] + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + 8006336: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 800633a: 623b str r3, [r7, #32] + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + 800633c: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8006340: 61bb str r3, [r7, #24] + dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; + 8006342: 2301 movs r3, #1 + 8006344: f887 302d strb.w r3, [r7, #45] ; 0x2d + dmaDefaultConf.DescriptorSkipLength = 0x0U; + 8006348: 2300 movs r3, #0 + 800634a: 633b str r3, [r7, #48] ; 0x30 + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + 800634c: 2300 movs r3, #0 + 800634e: 60bb str r3, [r7, #8] + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); + 8006350: f107 0308 add.w r3, r7, #8 + 8006354: 4619 mov r1, r3 + 8006356: 6878 ldr r0, [r7, #4] + 8006358: f7ff ff08 bl 800616c +} + 800635c: bf00 nop + 800635e: 3798 adds r7, #152 ; 0x98 + 8006360: 46bd mov sp, r7 + 8006362: bd80 pop {r7, pc} + +08006364 : + * @arg ETH_MAC_Address3: MAC Address3 + * @param Addr Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) +{ + 8006364: b480 push {r7} + 8006366: b087 sub sp, #28 + 8006368: af00 add r7, sp, #0 + 800636a: 60f8 str r0, [r7, #12] + 800636c: 60b9 str r1, [r7, #8] + 800636e: 607a str r2, [r7, #4] + + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + + /* Calculate the selected MAC address high register */ + tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; + 8006370: 687b ldr r3, [r7, #4] + 8006372: 3305 adds r3, #5 + 8006374: 781b ldrb r3, [r3, #0] + 8006376: 021b lsls r3, r3, #8 + 8006378: 687a ldr r2, [r7, #4] + 800637a: 3204 adds r2, #4 + 800637c: 7812 ldrb r2, [r2, #0] + 800637e: 4313 orrs r3, r2 + 8006380: 617b str r3, [r7, #20] + /* Load the selected MAC address high register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; + 8006382: 68ba ldr r2, [r7, #8] + 8006384: 4b11 ldr r3, [pc, #68] ; (80063cc ) + 8006386: 4413 add r3, r2 + 8006388: 461a mov r2, r3 + 800638a: 697b ldr r3, [r7, #20] + 800638c: 6013 str r3, [r2, #0] + /* Calculate the selected MAC address low register */ + tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; + 800638e: 687b ldr r3, [r7, #4] + 8006390: 3303 adds r3, #3 + 8006392: 781b ldrb r3, [r3, #0] + 8006394: 061a lsls r2, r3, #24 + 8006396: 687b ldr r3, [r7, #4] + 8006398: 3302 adds r3, #2 + 800639a: 781b ldrb r3, [r3, #0] + 800639c: 041b lsls r3, r3, #16 + 800639e: 431a orrs r2, r3 + 80063a0: 687b ldr r3, [r7, #4] + 80063a2: 3301 adds r3, #1 + 80063a4: 781b ldrb r3, [r3, #0] + 80063a6: 021b lsls r3, r3, #8 + 80063a8: 4313 orrs r3, r2 + 80063aa: 687a ldr r2, [r7, #4] + 80063ac: 7812 ldrb r2, [r2, #0] + 80063ae: 4313 orrs r3, r2 + 80063b0: 617b str r3, [r7, #20] + + /* Load the selected MAC address low register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; + 80063b2: 68ba ldr r2, [r7, #8] + 80063b4: 4b06 ldr r3, [pc, #24] ; (80063d0 ) + 80063b6: 4413 add r3, r2 + 80063b8: 461a mov r2, r3 + 80063ba: 697b ldr r3, [r7, #20] + 80063bc: 6013 str r3, [r2, #0] +} + 80063be: bf00 nop + 80063c0: 371c adds r7, #28 + 80063c2: 46bd mov sp, r7 + 80063c4: f85d 7b04 ldr.w r7, [sp], #4 + 80063c8: 4770 bx lr + 80063ca: bf00 nop + 80063cc: 40028040 .word 0x40028040 + 80063d0: 40028044 .word 0x40028044 + +080063d4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + 80063d4: b480 push {r7} + 80063d6: b085 sub sp, #20 + 80063d8: af00 add r7, sp, #0 + 80063da: 6078 str r0, [r7, #4] + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + 80063dc: 2300 movs r3, #0 + 80063de: 60fb str r3, [r7, #12] + 80063e0: e03e b.n 8006460 + { + dmatxdesc = heth->Init.TxDesc + i; + 80063e2: 687b ldr r3, [r7, #4] + 80063e4: 68d9 ldr r1, [r3, #12] + 80063e6: 68fa ldr r2, [r7, #12] + 80063e8: 4613 mov r3, r2 + 80063ea: 009b lsls r3, r3, #2 + 80063ec: 4413 add r3, r2 + 80063ee: 00db lsls r3, r3, #3 + 80063f0: 440b add r3, r1 + 80063f2: 60bb str r3, [r7, #8] + + WRITE_REG(dmatxdesc->DESC0, 0x0); + 80063f4: 68bb ldr r3, [r7, #8] + 80063f6: 2200 movs r2, #0 + 80063f8: 601a str r2, [r3, #0] + WRITE_REG(dmatxdesc->DESC1, 0x0); + 80063fa: 68bb ldr r3, [r7, #8] + 80063fc: 2200 movs r2, #0 + 80063fe: 605a str r2, [r3, #4] + WRITE_REG(dmatxdesc->DESC2, 0x0); + 8006400: 68bb ldr r3, [r7, #8] + 8006402: 2200 movs r2, #0 + 8006404: 609a str r2, [r3, #8] + WRITE_REG(dmatxdesc->DESC3, 0x0); + 8006406: 68bb ldr r3, [r7, #8] + 8006408: 2200 movs r2, #0 + 800640a: 60da str r2, [r3, #12] + + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + 800640c: 68b9 ldr r1, [r7, #8] + 800640e: 687b ldr r3, [r7, #4] + 8006410: 68fa ldr r2, [r7, #12] + 8006412: 3206 adds r2, #6 + 8006414: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Set Second Address Chained bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); + 8006418: 68bb ldr r3, [r7, #8] + 800641a: 681b ldr r3, [r3, #0] + 800641c: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 + 8006420: 68bb ldr r3, [r7, #8] + 8006422: 601a str r2, [r3, #0] + + if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) + 8006424: 68fb ldr r3, [r7, #12] + 8006426: 2b02 cmp r3, #2 + 8006428: d80c bhi.n 8006444 + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); + 800642a: 687b ldr r3, [r7, #4] + 800642c: 68d9 ldr r1, [r3, #12] + 800642e: 68fb ldr r3, [r7, #12] + 8006430: 1c5a adds r2, r3, #1 + 8006432: 4613 mov r3, r2 + 8006434: 009b lsls r3, r3, #2 + 8006436: 4413 add r3, r2 + 8006438: 00db lsls r3, r3, #3 + 800643a: 440b add r3, r1 + 800643c: 461a mov r2, r3 + 800643e: 68bb ldr r3, [r7, #8] + 8006440: 60da str r2, [r3, #12] + 8006442: e004 b.n 800644e + } + else + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); + 8006444: 687b ldr r3, [r7, #4] + 8006446: 68db ldr r3, [r3, #12] + 8006448: 461a mov r2, r3 + 800644a: 68bb ldr r3, [r7, #8] + 800644c: 60da str r2, [r3, #12] + } + + /* Set the DMA Tx descriptors checksum insertion */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); + 800644e: 68bb ldr r3, [r7, #8] + 8006450: 681b ldr r3, [r3, #0] + 8006452: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000 + 8006456: 68bb ldr r3, [r7, #8] + 8006458: 601a str r2, [r3, #0] + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + 800645a: 68fb ldr r3, [r7, #12] + 800645c: 3301 adds r3, #1 + 800645e: 60fb str r3, [r7, #12] + 8006460: 68fb ldr r3, [r7, #12] + 8006462: 2b03 cmp r3, #3 + 8006464: d9bd bls.n 80063e2 + } + + heth->TxDescList.CurTxDesc = 0; + 8006466: 687b ldr r3, [r7, #4] + 8006468: 2200 movs r2, #0 + 800646a: 629a str r2, [r3, #40] ; 0x28 + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); + 800646c: 687b ldr r3, [r7, #4] + 800646e: 68da ldr r2, [r3, #12] + 8006470: 687b ldr r3, [r7, #4] + 8006472: 681b ldr r3, [r3, #0] + 8006474: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8006478: 611a str r2, [r3, #16] +} + 800647a: bf00 nop + 800647c: 3714 adds r7, #20 + 800647e: 46bd mov sp, r7 + 8006480: f85d 7b04 ldr.w r7, [sp], #4 + 8006484: 4770 bx lr + +08006486 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + 8006486: b480 push {r7} + 8006488: b085 sub sp, #20 + 800648a: af00 add r7, sp, #0 + 800648c: 6078 str r0, [r7, #4] + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + 800648e: 2300 movs r3, #0 + 8006490: 60fb str r3, [r7, #12] + 8006492: e046 b.n 8006522 + { + dmarxdesc = heth->Init.RxDesc + i; + 8006494: 687b ldr r3, [r7, #4] + 8006496: 6919 ldr r1, [r3, #16] + 8006498: 68fa ldr r2, [r7, #12] + 800649a: 4613 mov r3, r2 + 800649c: 009b lsls r3, r3, #2 + 800649e: 4413 add r3, r2 + 80064a0: 00db lsls r3, r3, #3 + 80064a2: 440b add r3, r1 + 80064a4: 60bb str r3, [r7, #8] + + WRITE_REG(dmarxdesc->DESC0, 0x0); + 80064a6: 68bb ldr r3, [r7, #8] + 80064a8: 2200 movs r2, #0 + 80064aa: 601a str r2, [r3, #0] + WRITE_REG(dmarxdesc->DESC1, 0x0); + 80064ac: 68bb ldr r3, [r7, #8] + 80064ae: 2200 movs r2, #0 + 80064b0: 605a str r2, [r3, #4] + WRITE_REG(dmarxdesc->DESC2, 0x0); + 80064b2: 68bb ldr r3, [r7, #8] + 80064b4: 2200 movs r2, #0 + 80064b6: 609a str r2, [r3, #8] + WRITE_REG(dmarxdesc->DESC3, 0x0); + 80064b8: 68bb ldr r3, [r7, #8] + 80064ba: 2200 movs r2, #0 + 80064bc: 60da str r2, [r3, #12] + WRITE_REG(dmarxdesc->BackupAddr0, 0x0); + 80064be: 68bb ldr r3, [r7, #8] + 80064c0: 2200 movs r2, #0 + 80064c2: 621a str r2, [r3, #32] + WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + 80064c4: 68bb ldr r3, [r7, #8] + 80064c6: 2200 movs r2, #0 + 80064c8: 625a str r2, [r3, #36] ; 0x24 + + /* Set Own bit of the Rx descriptor Status */ + dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; + 80064ca: 68bb ldr r3, [r7, #8] + 80064cc: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 80064d0: 601a str r2, [r3, #0] + + /* Set Buffer1 size and Second Address Chained bit */ + dmarxdesc->DESC1 = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + 80064d2: 68bb ldr r3, [r7, #8] + 80064d4: f44f 428c mov.w r2, #17920 ; 0x4600 + 80064d8: 605a str r2, [r3, #4] + + /* Enable Ethernet DMA Rx Descriptor interrupt */ + dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; + 80064da: 68bb ldr r3, [r7, #8] + 80064dc: 685b ldr r3, [r3, #4] + 80064de: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 80064e2: 68bb ldr r3, [r7, #8] + 80064e4: 605a str r2, [r3, #4] + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + 80064e6: 68b9 ldr r1, [r7, #8] + 80064e8: 687b ldr r3, [r7, #4] + 80064ea: 68fa ldr r2, [r7, #12] + 80064ec: 3212 adds r2, #18 + 80064ee: f843 1022 str.w r1, [r3, r2, lsl #2] + + if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) + 80064f2: 68fb ldr r3, [r7, #12] + 80064f4: 2b02 cmp r3, #2 + 80064f6: d80c bhi.n 8006512 + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); + 80064f8: 687b ldr r3, [r7, #4] + 80064fa: 6919 ldr r1, [r3, #16] + 80064fc: 68fb ldr r3, [r7, #12] + 80064fe: 1c5a adds r2, r3, #1 + 8006500: 4613 mov r3, r2 + 8006502: 009b lsls r3, r3, #2 + 8006504: 4413 add r3, r2 + 8006506: 00db lsls r3, r3, #3 + 8006508: 440b add r3, r1 + 800650a: 461a mov r2, r3 + 800650c: 68bb ldr r3, [r7, #8] + 800650e: 60da str r2, [r3, #12] + 8006510: e004 b.n 800651c + } + else + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); + 8006512: 687b ldr r3, [r7, #4] + 8006514: 691b ldr r3, [r3, #16] + 8006516: 461a mov r2, r3 + 8006518: 68bb ldr r3, [r7, #8] + 800651a: 60da str r2, [r3, #12] + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + 800651c: 68fb ldr r3, [r7, #12] + 800651e: 3301 adds r3, #1 + 8006520: 60fb str r3, [r7, #12] + 8006522: 68fb ldr r3, [r7, #12] + 8006524: 2b03 cmp r3, #3 + 8006526: d9b5 bls.n 8006494 + } + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + 8006528: 687b ldr r3, [r7, #4] + 800652a: 2200 movs r2, #0 + 800652c: 65da str r2, [r3, #92] ; 0x5c + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + 800652e: 687b ldr r3, [r7, #4] + 8006530: 2200 movs r2, #0 + 8006532: 661a str r2, [r3, #96] ; 0x60 + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + 8006534: 687b ldr r3, [r7, #4] + 8006536: 2200 movs r2, #0 + 8006538: 669a str r2, [r3, #104] ; 0x68 + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); + 800653a: 687b ldr r3, [r7, #4] + 800653c: 2200 movs r2, #0 + 800653e: 66da str r2, [r3, #108] ; 0x6c + WRITE_REG(heth->RxDescList.ItMode, 0); + 8006540: 687b ldr r3, [r7, #4] + 8006542: 2200 movs r2, #0 + 8006544: 659a str r2, [r3, #88] ; 0x58 + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); + 8006546: 687b ldr r3, [r7, #4] + 8006548: 691a ldr r2, [r3, #16] + 800654a: 687b ldr r3, [r7, #4] + 800654c: 681b ldr r3, [r3, #0] + 800654e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8006552: 60da str r2, [r3, #12] +} + 8006554: bf00 nop + 8006556: 3714 adds r7, #20 + 8006558: 46bd mov sp, r7 + 800655a: f85d 7b04 ldr.w r7, [sp], #4 + 800655e: 4770 bx lr + +08006560 : + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status + */ +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) +{ + 8006560: b480 push {r7} + 8006562: b08d sub sp, #52 ; 0x34 + 8006564: af00 add r7, sp, #0 + 8006566: 60f8 str r0, [r7, #12] + 8006568: 60b9 str r1, [r7, #8] + 800656a: 607a str r2, [r7, #4] + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + 800656c: 68fb ldr r3, [r7, #12] + 800656e: 3318 adds r3, #24 + 8006570: 617b str r3, [r7, #20] + uint32_t descidx = dmatxdesclist->CurTxDesc; + 8006572: 697b ldr r3, [r7, #20] + 8006574: 691b ldr r3, [r3, #16] + 8006576: 62fb str r3, [r7, #44] ; 0x2c + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + 8006578: 697b ldr r3, [r7, #20] + 800657a: 691b ldr r3, [r3, #16] + 800657c: 613b str r3, [r7, #16] + uint32_t idx; + uint32_t descnbr = 0; + 800657e: 2300 movs r3, #0 + 8006580: 627b str r3, [r7, #36] ; 0x24 + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 8006582: 697b ldr r3, [r7, #20] + 8006584: 6afa ldr r2, [r7, #44] ; 0x2c + 8006586: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800658a: 623b str r3, [r7, #32] + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + 800658c: 68bb ldr r3, [r7, #8] + 800658e: 689b ldr r3, [r3, #8] + 8006590: 61fb str r3, [r7, #28] + uint32_t bd_count = 0; + 8006592: 2300 movs r3, #0 + 8006594: 61bb str r3, [r7, #24] + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + 8006596: 6a3b ldr r3, [r7, #32] + 8006598: 681b ldr r3, [r3, #0] + 800659a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 800659e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 80065a2: d007 beq.n 80065b4 + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + 80065a4: 697a ldr r2, [r7, #20] + 80065a6: 6afb ldr r3, [r7, #44] ; 0x2c + 80065a8: 3304 adds r3, #4 + 80065aa: 009b lsls r3, r3, #2 + 80065ac: 4413 add r3, r2 + 80065ae: 685b ldr r3, [r3, #4] + 80065b0: 2b00 cmp r3, #0 + 80065b2: d001 beq.n 80065b8 + { + return HAL_ETH_ERROR_BUSY; + 80065b4: 2302 movs r3, #2 + 80065b6: e0ff b.n 80067b8 + } + + + descnbr += 1U; + 80065b8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80065ba: 3301 adds r3, #1 + 80065bc: 627b str r3, [r7, #36] ; 0x24 + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + 80065be: 69fb ldr r3, [r7, #28] + 80065c0: 681b ldr r3, [r3, #0] + 80065c2: 461a mov r2, r3 + 80065c4: 6a3b ldr r3, [r7, #32] + 80065c6: 609a str r2, [r3, #8] + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + 80065c8: 6a3b ldr r3, [r7, #32] + 80065ca: 685a ldr r2, [r3, #4] + 80065cc: 4b7d ldr r3, [pc, #500] ; (80067c4 ) + 80065ce: 4013 ands r3, r2 + 80065d0: 69fa ldr r2, [r7, #28] + 80065d2: 6852 ldr r2, [r2, #4] + 80065d4: 431a orrs r2, r3 + 80065d6: 6a3b ldr r3, [r7, #32] + 80065d8: 605a str r2, [r3, #4] + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) + 80065da: 68bb ldr r3, [r7, #8] + 80065dc: 681b ldr r3, [r3, #0] + 80065de: f003 0301 and.w r3, r3, #1 + 80065e2: 2b00 cmp r3, #0 + 80065e4: d008 beq.n 80065f8 + { + MODIFY_REG(dmatxdesc->DESC0, ETH_DMATXDESC_CIC, pTxConfig->ChecksumCtrl); + 80065e6: 6a3b ldr r3, [r7, #32] + 80065e8: 681b ldr r3, [r3, #0] + 80065ea: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 80065ee: 68bb ldr r3, [r7, #8] + 80065f0: 695b ldr r3, [r3, #20] + 80065f2: 431a orrs r2, r3 + 80065f4: 6a3b ldr r3, [r7, #32] + 80065f6: 601a str r2, [r3, #0] + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U) + 80065f8: 68bb ldr r3, [r7, #8] + 80065fa: 681b ldr r3, [r3, #0] + 80065fc: f003 0320 and.w r3, r3, #32 + 8006600: 2b00 cmp r3, #0 + 8006602: d008 beq.n 8006616 + { + MODIFY_REG(dmatxdesc->DESC0, ETH_CRC_PAD_DISABLE, pTxConfig->CRCPadCtrl); + 8006604: 6a3b ldr r3, [r7, #32] + 8006606: 681b ldr r3, [r3, #0] + 8006608: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 + 800660c: 68bb ldr r3, [r7, #8] + 800660e: 691b ldr r3, [r3, #16] + 8006610: 431a orrs r2, r3 + 8006612: 6a3b ldr r3, [r7, #32] + 8006614: 601a str r2, [r3, #0] + } + + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) + 8006616: 68bb ldr r3, [r7, #8] + 8006618: 681b ldr r3, [r3, #0] + 800661a: f003 0304 and.w r3, r3, #4 + 800661e: 2b00 cmp r3, #0 + 8006620: d005 beq.n 800662e + { + /* Set Vlan Type */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_VF); + 8006622: 6a3b ldr r3, [r7, #32] + 8006624: 681b ldr r3, [r3, #0] + 8006626: f043 0280 orr.w r2, r3, #128 ; 0x80 + 800662a: 6a3b ldr r3, [r7, #32] + 800662c: 601a str r2, [r3, #0] + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + 800662e: 6a3b ldr r3, [r7, #32] + 8006630: 681b ldr r3, [r3, #0] + 8006632: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 + 8006636: 6a3b ldr r3, [r7, #32] + 8006638: 601a str r2, [r3, #0] + __ASM volatile ("dmb 0xF":::"memory"); + 800663a: f3bf 8f5f dmb sy +} + 800663e: bf00 nop + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + 8006640: 6a3b ldr r3, [r7, #32] + 8006642: 681b ldr r3, [r3, #0] + 8006644: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8006648: 6a3b ldr r3, [r7, #32] + 800664a: 601a str r2, [r3, #0] + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + 800664c: e082 b.n 8006754 + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + 800664e: 6a3b ldr r3, [r7, #32] + 8006650: 681b ldr r3, [r3, #0] + 8006652: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 8006656: 6a3b ldr r3, [r7, #32] + 8006658: 601a str r2, [r3, #0] + if (ItMode != ((uint32_t)RESET)) + 800665a: 687b ldr r3, [r7, #4] + 800665c: 2b00 cmp r3, #0 + 800665e: d006 beq.n 800666e + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + 8006660: 6a3b ldr r3, [r7, #32] + 8006662: 681b ldr r3, [r3, #0] + 8006664: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 + 8006668: 6a3b ldr r3, [r7, #32] + 800666a: 601a str r2, [r3, #0] + 800666c: e005 b.n 800667a + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + 800666e: 6a3b ldr r3, [r7, #32] + 8006670: 681b ldr r3, [r3, #0] + 8006672: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 + 8006676: 6a3b ldr r3, [r7, #32] + 8006678: 601a str r2, [r3, #0] + } + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + 800667a: 6afb ldr r3, [r7, #44] ; 0x2c + 800667c: 3301 adds r3, #1 + 800667e: 62fb str r3, [r7, #44] ; 0x2c + 8006680: 6afb ldr r3, [r7, #44] ; 0x2c + 8006682: 2b03 cmp r3, #3 + 8006684: d902 bls.n 800668c + 8006686: 6afb ldr r3, [r7, #44] ; 0x2c + 8006688: 3b04 subs r3, #4 + 800668a: 62fb str r3, [r7, #44] ; 0x2c + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 800668c: 697b ldr r3, [r7, #20] + 800668e: 6afa ldr r2, [r7, #44] ; 0x2c + 8006690: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8006694: 623b str r3, [r7, #32] + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + 8006696: 6a3b ldr r3, [r7, #32] + 8006698: 681b ldr r3, [r3, #0] + 800669a: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 800669e: 6a3b ldr r3, [r7, #32] + 80066a0: 601a str r2, [r3, #0] + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + 80066a2: 6a3b ldr r3, [r7, #32] + 80066a4: 681b ldr r3, [r3, #0] + 80066a6: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 80066aa: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 80066ae: d007 beq.n 80066c0 + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + 80066b0: 697a ldr r2, [r7, #20] + 80066b2: 6afb ldr r3, [r7, #44] ; 0x2c + 80066b4: 3304 adds r3, #4 + 80066b6: 009b lsls r3, r3, #2 + 80066b8: 4413 add r3, r2 + 80066ba: 685b ldr r3, [r3, #4] + 80066bc: 2b00 cmp r3, #0 + 80066be: d029 beq.n 8006714 + { + descidx = firstdescidx; + 80066c0: 693b ldr r3, [r7, #16] + 80066c2: 62fb str r3, [r7, #44] ; 0x2c + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 80066c4: 697b ldr r3, [r7, #20] + 80066c6: 6afa ldr r2, [r7, #44] ; 0x2c + 80066c8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80066cc: 623b str r3, [r7, #32] + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + 80066ce: 2300 movs r3, #0 + 80066d0: 62bb str r3, [r7, #40] ; 0x28 + 80066d2: e019 b.n 8006708 + __ASM volatile ("dmb 0xF":::"memory"); + 80066d4: f3bf 8f5f dmb sy +} + 80066d8: bf00 nop + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + 80066da: 6a3b ldr r3, [r7, #32] + 80066dc: 681b ldr r3, [r3, #0] + 80066de: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 80066e2: 6a3b ldr r3, [r7, #32] + 80066e4: 601a str r2, [r3, #0] + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + 80066e6: 6afb ldr r3, [r7, #44] ; 0x2c + 80066e8: 3301 adds r3, #1 + 80066ea: 62fb str r3, [r7, #44] ; 0x2c + 80066ec: 6afb ldr r3, [r7, #44] ; 0x2c + 80066ee: 2b03 cmp r3, #3 + 80066f0: d902 bls.n 80066f8 + 80066f2: 6afb ldr r3, [r7, #44] ; 0x2c + 80066f4: 3b04 subs r3, #4 + 80066f6: 62fb str r3, [r7, #44] ; 0x2c + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 80066f8: 697b ldr r3, [r7, #20] + 80066fa: 6afa ldr r2, [r7, #44] ; 0x2c + 80066fc: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8006700: 623b str r3, [r7, #32] + for (idx = 0; idx < descnbr; idx ++) + 8006702: 6abb ldr r3, [r7, #40] ; 0x28 + 8006704: 3301 adds r3, #1 + 8006706: 62bb str r3, [r7, #40] ; 0x28 + 8006708: 6aba ldr r2, [r7, #40] ; 0x28 + 800670a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800670c: 429a cmp r2, r3 + 800670e: d3e1 bcc.n 80066d4 + } + + return HAL_ETH_ERROR_BUSY; + 8006710: 2302 movs r3, #2 + 8006712: e051 b.n 80067b8 + } + + descnbr += 1U; + 8006714: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006716: 3301 adds r3, #1 + 8006718: 627b str r3, [r7, #36] ; 0x24 + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + 800671a: 69fb ldr r3, [r7, #28] + 800671c: 689b ldr r3, [r3, #8] + 800671e: 61fb str r3, [r7, #28] + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + 8006720: 69fb ldr r3, [r7, #28] + 8006722: 681b ldr r3, [r3, #0] + 8006724: 461a mov r2, r3 + 8006726: 6a3b ldr r3, [r7, #32] + 8006728: 609a str r2, [r3, #8] + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + 800672a: 6a3b ldr r3, [r7, #32] + 800672c: 685a ldr r2, [r3, #4] + 800672e: 4b25 ldr r3, [pc, #148] ; (80067c4 ) + 8006730: 4013 ands r3, r2 + 8006732: 69fa ldr r2, [r7, #28] + 8006734: 6852 ldr r2, [r2, #4] + 8006736: 431a orrs r2, r3 + 8006738: 6a3b ldr r3, [r7, #32] + 800673a: 605a str r2, [r3, #4] + + bd_count += 1U; + 800673c: 69bb ldr r3, [r7, #24] + 800673e: 3301 adds r3, #1 + 8006740: 61bb str r3, [r7, #24] + __ASM volatile ("dmb 0xF":::"memory"); + 8006742: f3bf 8f5f dmb sy +} + 8006746: bf00 nop + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + 8006748: 6a3b ldr r3, [r7, #32] + 800674a: 681b ldr r3, [r3, #0] + 800674c: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8006750: 6a3b ldr r3, [r7, #32] + 8006752: 601a str r2, [r3, #0] + while (txbuffer->next != NULL) + 8006754: 69fb ldr r3, [r7, #28] + 8006756: 689b ldr r3, [r3, #8] + 8006758: 2b00 cmp r3, #0 + 800675a: f47f af78 bne.w 800664e + } + + if (ItMode != ((uint32_t)RESET)) + 800675e: 687b ldr r3, [r7, #4] + 8006760: 2b00 cmp r3, #0 + 8006762: d006 beq.n 8006772 + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + 8006764: 6a3b ldr r3, [r7, #32] + 8006766: 681b ldr r3, [r3, #0] + 8006768: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 + 800676c: 6a3b ldr r3, [r7, #32] + 800676e: 601a str r2, [r3, #0] + 8006770: e005 b.n 800677e + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + 8006772: 6a3b ldr r3, [r7, #32] + 8006774: 681b ldr r3, [r3, #0] + 8006776: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 + 800677a: 6a3b ldr r3, [r7, #32] + 800677c: 601a str r2, [r3, #0] + } + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + 800677e: 6a3b ldr r3, [r7, #32] + 8006780: 681b ldr r3, [r3, #0] + 8006782: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 + 8006786: 6a3b ldr r3, [r7, #32] + 8006788: 601a str r2, [r3, #0] + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + 800678a: 697b ldr r3, [r7, #20] + 800678c: 6a5a ldr r2, [r3, #36] ; 0x24 + 800678e: 6979 ldr r1, [r7, #20] + 8006790: 6afb ldr r3, [r7, #44] ; 0x2c + 8006792: 3304 adds r3, #4 + 8006794: 009b lsls r3, r3, #2 + 8006796: 440b add r3, r1 + 8006798: 605a str r2, [r3, #4] + + dmatxdesclist->CurTxDesc = descidx; + 800679a: 697b ldr r3, [r7, #20] + 800679c: 6afa ldr r2, [r7, #44] ; 0x2c + 800679e: 611a str r2, [r3, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 80067a0: b672 cpsid i +} + 80067a2: bf00 nop + + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + 80067a4: 697b ldr r3, [r7, #20] + 80067a6: 6a9a ldr r2, [r3, #40] ; 0x28 + 80067a8: 69bb ldr r3, [r7, #24] + 80067aa: 4413 add r3, r2 + 80067ac: 1c5a adds r2, r3, #1 + 80067ae: 697b ldr r3, [r7, #20] + 80067b0: 629a str r2, [r3, #40] ; 0x28 + __ASM volatile ("cpsie i" : : : "memory"); + 80067b2: b662 cpsie i +} + 80067b4: bf00 nop + /* Enable interrupts back */ + __enable_irq(); + + + /* Return function status */ + return HAL_ETH_ERROR_NONE; + 80067b6: 2300 movs r3, #0 +} + 80067b8: 4618 mov r0, r3 + 80067ba: 3734 adds r7, #52 ; 0x34 + 80067bc: 46bd mov sp, r7 + 80067be: f85d 7b04 ldr.w r7, [sp], #4 + 80067c2: 4770 bx lr + 80067c4: ffffe000 .word 0xffffe000 + +080067c8 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80067c8: b480 push {r7} + 80067ca: b089 sub sp, #36 ; 0x24 + 80067cc: af00 add r7, sp, #0 + 80067ce: 6078 str r0, [r7, #4] + 80067d0: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 80067d2: 2300 movs r3, #0 + 80067d4: 61fb str r3, [r7, #28] + uint32_t ioposition = 0x00; + 80067d6: 2300 movs r3, #0 + 80067d8: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 80067da: 2300 movs r3, #0 + 80067dc: 613b str r3, [r7, #16] + uint32_t temp = 0x00; + 80067de: 2300 movs r3, #0 + 80067e0: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 80067e2: 2300 movs r3, #0 + 80067e4: 61fb str r3, [r7, #28] + 80067e6: e175 b.n 8006ad4 + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 80067e8: 2201 movs r2, #1 + 80067ea: 69fb ldr r3, [r7, #28] + 80067ec: fa02 f303 lsl.w r3, r2, r3 + 80067f0: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 80067f2: 683b ldr r3, [r7, #0] + 80067f4: 681b ldr r3, [r3, #0] + 80067f6: 697a ldr r2, [r7, #20] + 80067f8: 4013 ands r3, r2 + 80067fa: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 80067fc: 693a ldr r2, [r7, #16] + 80067fe: 697b ldr r3, [r7, #20] + 8006800: 429a cmp r2, r3 + 8006802: f040 8164 bne.w 8006ace + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8006806: 683b ldr r3, [r7, #0] + 8006808: 685b ldr r3, [r3, #4] + 800680a: f003 0303 and.w r3, r3, #3 + 800680e: 2b01 cmp r3, #1 + 8006810: d005 beq.n 800681e + 8006812: 683b ldr r3, [r7, #0] + 8006814: 685b ldr r3, [r3, #4] + 8006816: f003 0303 and.w r3, r3, #3 + 800681a: 2b02 cmp r3, #2 + 800681c: d130 bne.n 8006880 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 800681e: 687b ldr r3, [r7, #4] + 8006820: 689b ldr r3, [r3, #8] + 8006822: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8006824: 69fb ldr r3, [r7, #28] + 8006826: 005b lsls r3, r3, #1 + 8006828: 2203 movs r2, #3 + 800682a: fa02 f303 lsl.w r3, r2, r3 + 800682e: 43db mvns r3, r3 + 8006830: 69ba ldr r2, [r7, #24] + 8006832: 4013 ands r3, r2 + 8006834: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2)); + 8006836: 683b ldr r3, [r7, #0] + 8006838: 68da ldr r2, [r3, #12] + 800683a: 69fb ldr r3, [r7, #28] + 800683c: 005b lsls r3, r3, #1 + 800683e: fa02 f303 lsl.w r3, r2, r3 + 8006842: 69ba ldr r2, [r7, #24] + 8006844: 4313 orrs r3, r2 + 8006846: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8006848: 687b ldr r3, [r7, #4] + 800684a: 69ba ldr r2, [r7, #24] + 800684c: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 800684e: 687b ldr r3, [r7, #4] + 8006850: 685b ldr r3, [r3, #4] + 8006852: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8006854: 2201 movs r2, #1 + 8006856: 69fb ldr r3, [r7, #28] + 8006858: fa02 f303 lsl.w r3, r2, r3 + 800685c: 43db mvns r3, r3 + 800685e: 69ba ldr r2, [r7, #24] + 8006860: 4013 ands r3, r2 + 8006862: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8006864: 683b ldr r3, [r7, #0] + 8006866: 685b ldr r3, [r3, #4] + 8006868: 091b lsrs r3, r3, #4 + 800686a: f003 0201 and.w r2, r3, #1 + 800686e: 69fb ldr r3, [r7, #28] + 8006870: fa02 f303 lsl.w r3, r2, r3 + 8006874: 69ba ldr r2, [r7, #24] + 8006876: 4313 orrs r3, r2 + 8006878: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 800687a: 687b ldr r3, [r7, #4] + 800687c: 69ba ldr r2, [r7, #24] + 800687e: 605a str r2, [r3, #4] + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8006880: 683b ldr r3, [r7, #0] + 8006882: 685b ldr r3, [r3, #4] + 8006884: f003 0303 and.w r3, r3, #3 + 8006888: 2b03 cmp r3, #3 + 800688a: d017 beq.n 80068bc + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 800688c: 687b ldr r3, [r7, #4] + 800688e: 68db ldr r3, [r3, #12] + 8006890: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 8006892: 69fb ldr r3, [r7, #28] + 8006894: 005b lsls r3, r3, #1 + 8006896: 2203 movs r2, #3 + 8006898: fa02 f303 lsl.w r3, r2, r3 + 800689c: 43db mvns r3, r3 + 800689e: 69ba ldr r2, [r7, #24] + 80068a0: 4013 ands r3, r2 + 80068a2: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2)); + 80068a4: 683b ldr r3, [r7, #0] + 80068a6: 689a ldr r2, [r3, #8] + 80068a8: 69fb ldr r3, [r7, #28] + 80068aa: 005b lsls r3, r3, #1 + 80068ac: fa02 f303 lsl.w r3, r2, r3 + 80068b0: 69ba ldr r2, [r7, #24] + 80068b2: 4313 orrs r3, r2 + 80068b4: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 80068b6: 687b ldr r3, [r7, #4] + 80068b8: 69ba ldr r2, [r7, #24] + 80068ba: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80068bc: 683b ldr r3, [r7, #0] + 80068be: 685b ldr r3, [r3, #4] + 80068c0: f003 0303 and.w r3, r3, #3 + 80068c4: 2b02 cmp r3, #2 + 80068c6: d123 bne.n 8006910 + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + 80068c8: 69fb ldr r3, [r7, #28] + 80068ca: 08da lsrs r2, r3, #3 + 80068cc: 687b ldr r3, [r7, #4] + 80068ce: 3208 adds r2, #8 + 80068d0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80068d4: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 80068d6: 69fb ldr r3, [r7, #28] + 80068d8: f003 0307 and.w r3, r3, #7 + 80068dc: 009b lsls r3, r3, #2 + 80068de: 220f movs r2, #15 + 80068e0: fa02 f303 lsl.w r3, r2, r3 + 80068e4: 43db mvns r3, r3 + 80068e6: 69ba ldr r2, [r7, #24] + 80068e8: 4013 ands r3, r2 + 80068ea: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 80068ec: 683b ldr r3, [r7, #0] + 80068ee: 691a ldr r2, [r3, #16] + 80068f0: 69fb ldr r3, [r7, #28] + 80068f2: f003 0307 and.w r3, r3, #7 + 80068f6: 009b lsls r3, r3, #2 + 80068f8: fa02 f303 lsl.w r3, r2, r3 + 80068fc: 69ba ldr r2, [r7, #24] + 80068fe: 4313 orrs r3, r2 + 8006900: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3] = temp; + 8006902: 69fb ldr r3, [r7, #28] + 8006904: 08da lsrs r2, r3, #3 + 8006906: 687b ldr r3, [r7, #4] + 8006908: 3208 adds r2, #8 + 800690a: 69b9 ldr r1, [r7, #24] + 800690c: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8006910: 687b ldr r3, [r7, #4] + 8006912: 681b ldr r3, [r3, #0] + 8006914: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 8006916: 69fb ldr r3, [r7, #28] + 8006918: 005b lsls r3, r3, #1 + 800691a: 2203 movs r2, #3 + 800691c: fa02 f303 lsl.w r3, r2, r3 + 8006920: 43db mvns r3, r3 + 8006922: 69ba ldr r2, [r7, #24] + 8006924: 4013 ands r3, r2 + 8006926: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8006928: 683b ldr r3, [r7, #0] + 800692a: 685b ldr r3, [r3, #4] + 800692c: f003 0203 and.w r2, r3, #3 + 8006930: 69fb ldr r3, [r7, #28] + 8006932: 005b lsls r3, r3, #1 + 8006934: fa02 f303 lsl.w r3, r2, r3 + 8006938: 69ba ldr r2, [r7, #24] + 800693a: 4313 orrs r3, r2 + 800693c: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 800693e: 687b ldr r3, [r7, #4] + 8006940: 69ba ldr r2, [r7, #24] + 8006942: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 8006944: 683b ldr r3, [r7, #0] + 8006946: 685b ldr r3, [r3, #4] + 8006948: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 800694c: 2b00 cmp r3, #0 + 800694e: f000 80be beq.w 8006ace + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8006952: 4b66 ldr r3, [pc, #408] ; (8006aec ) + 8006954: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006956: 4a65 ldr r2, [pc, #404] ; (8006aec ) + 8006958: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 800695c: 6453 str r3, [r2, #68] ; 0x44 + 800695e: 4b63 ldr r3, [pc, #396] ; (8006aec ) + 8006960: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006962: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8006966: 60fb str r3, [r7, #12] + 8006968: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2]; + 800696a: 4a61 ldr r2, [pc, #388] ; (8006af0 ) + 800696c: 69fb ldr r3, [r7, #28] + 800696e: 089b lsrs r3, r3, #2 + 8006970: 3302 adds r3, #2 + 8006972: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8006976: 61bb str r3, [r7, #24] + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 8006978: 69fb ldr r3, [r7, #28] + 800697a: f003 0303 and.w r3, r3, #3 + 800697e: 009b lsls r3, r3, #2 + 8006980: 220f movs r2, #15 + 8006982: fa02 f303 lsl.w r3, r2, r3 + 8006986: 43db mvns r3, r3 + 8006988: 69ba ldr r2, [r7, #24] + 800698a: 4013 ands r3, r2 + 800698c: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 800698e: 687b ldr r3, [r7, #4] + 8006990: 4a58 ldr r2, [pc, #352] ; (8006af4 ) + 8006992: 4293 cmp r3, r2 + 8006994: d037 beq.n 8006a06 + 8006996: 687b ldr r3, [r7, #4] + 8006998: 4a57 ldr r2, [pc, #348] ; (8006af8 ) + 800699a: 4293 cmp r3, r2 + 800699c: d031 beq.n 8006a02 + 800699e: 687b ldr r3, [r7, #4] + 80069a0: 4a56 ldr r2, [pc, #344] ; (8006afc ) + 80069a2: 4293 cmp r3, r2 + 80069a4: d02b beq.n 80069fe + 80069a6: 687b ldr r3, [r7, #4] + 80069a8: 4a55 ldr r2, [pc, #340] ; (8006b00 ) + 80069aa: 4293 cmp r3, r2 + 80069ac: d025 beq.n 80069fa + 80069ae: 687b ldr r3, [r7, #4] + 80069b0: 4a54 ldr r2, [pc, #336] ; (8006b04 ) + 80069b2: 4293 cmp r3, r2 + 80069b4: d01f beq.n 80069f6 + 80069b6: 687b ldr r3, [r7, #4] + 80069b8: 4a53 ldr r2, [pc, #332] ; (8006b08 ) + 80069ba: 4293 cmp r3, r2 + 80069bc: d019 beq.n 80069f2 + 80069be: 687b ldr r3, [r7, #4] + 80069c0: 4a52 ldr r2, [pc, #328] ; (8006b0c ) + 80069c2: 4293 cmp r3, r2 + 80069c4: d013 beq.n 80069ee + 80069c6: 687b ldr r3, [r7, #4] + 80069c8: 4a51 ldr r2, [pc, #324] ; (8006b10 ) + 80069ca: 4293 cmp r3, r2 + 80069cc: d00d beq.n 80069ea + 80069ce: 687b ldr r3, [r7, #4] + 80069d0: 4a50 ldr r2, [pc, #320] ; (8006b14 ) + 80069d2: 4293 cmp r3, r2 + 80069d4: d007 beq.n 80069e6 + 80069d6: 687b ldr r3, [r7, #4] + 80069d8: 4a4f ldr r2, [pc, #316] ; (8006b18 ) + 80069da: 4293 cmp r3, r2 + 80069dc: d101 bne.n 80069e2 + 80069de: 2309 movs r3, #9 + 80069e0: e012 b.n 8006a08 + 80069e2: 230a movs r3, #10 + 80069e4: e010 b.n 8006a08 + 80069e6: 2308 movs r3, #8 + 80069e8: e00e b.n 8006a08 + 80069ea: 2307 movs r3, #7 + 80069ec: e00c b.n 8006a08 + 80069ee: 2306 movs r3, #6 + 80069f0: e00a b.n 8006a08 + 80069f2: 2305 movs r3, #5 + 80069f4: e008 b.n 8006a08 + 80069f6: 2304 movs r3, #4 + 80069f8: e006 b.n 8006a08 + 80069fa: 2303 movs r3, #3 + 80069fc: e004 b.n 8006a08 + 80069fe: 2302 movs r3, #2 + 8006a00: e002 b.n 8006a08 + 8006a02: 2301 movs r3, #1 + 8006a04: e000 b.n 8006a08 + 8006a06: 2300 movs r3, #0 + 8006a08: 69fa ldr r2, [r7, #28] + 8006a0a: f002 0203 and.w r2, r2, #3 + 8006a0e: 0092 lsls r2, r2, #2 + 8006a10: 4093 lsls r3, r2 + 8006a12: 69ba ldr r2, [r7, #24] + 8006a14: 4313 orrs r3, r2 + 8006a16: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2] = temp; + 8006a18: 4935 ldr r1, [pc, #212] ; (8006af0 ) + 8006a1a: 69fb ldr r3, [r7, #28] + 8006a1c: 089b lsrs r3, r3, #2 + 8006a1e: 3302 adds r3, #2 + 8006a20: 69ba ldr r2, [r7, #24] + 8006a22: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8006a26: 4b3d ldr r3, [pc, #244] ; (8006b1c ) + 8006a28: 689b ldr r3, [r3, #8] + 8006a2a: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8006a2c: 693b ldr r3, [r7, #16] + 8006a2e: 43db mvns r3, r3 + 8006a30: 69ba ldr r2, [r7, #24] + 8006a32: 4013 ands r3, r2 + 8006a34: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8006a36: 683b ldr r3, [r7, #0] + 8006a38: 685b ldr r3, [r3, #4] + 8006a3a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8006a3e: 2b00 cmp r3, #0 + 8006a40: d003 beq.n 8006a4a + { + temp |= iocurrent; + 8006a42: 69ba ldr r2, [r7, #24] + 8006a44: 693b ldr r3, [r7, #16] + 8006a46: 4313 orrs r3, r2 + 8006a48: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 8006a4a: 4a34 ldr r2, [pc, #208] ; (8006b1c ) + 8006a4c: 69bb ldr r3, [r7, #24] + 8006a4e: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8006a50: 4b32 ldr r3, [pc, #200] ; (8006b1c ) + 8006a52: 68db ldr r3, [r3, #12] + 8006a54: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8006a56: 693b ldr r3, [r7, #16] + 8006a58: 43db mvns r3, r3 + 8006a5a: 69ba ldr r2, [r7, #24] + 8006a5c: 4013 ands r3, r2 + 8006a5e: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8006a60: 683b ldr r3, [r7, #0] + 8006a62: 685b ldr r3, [r3, #4] + 8006a64: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8006a68: 2b00 cmp r3, #0 + 8006a6a: d003 beq.n 8006a74 + { + temp |= iocurrent; + 8006a6c: 69ba ldr r2, [r7, #24] + 8006a6e: 693b ldr r3, [r7, #16] + 8006a70: 4313 orrs r3, r2 + 8006a72: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8006a74: 4a29 ldr r2, [pc, #164] ; (8006b1c ) + 8006a76: 69bb ldr r3, [r7, #24] + 8006a78: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8006a7a: 4b28 ldr r3, [pc, #160] ; (8006b1c ) + 8006a7c: 685b ldr r3, [r3, #4] + 8006a7e: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8006a80: 693b ldr r3, [r7, #16] + 8006a82: 43db mvns r3, r3 + 8006a84: 69ba ldr r2, [r7, #24] + 8006a86: 4013 ands r3, r2 + 8006a88: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 8006a8a: 683b ldr r3, [r7, #0] + 8006a8c: 685b ldr r3, [r3, #4] + 8006a8e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8006a92: 2b00 cmp r3, #0 + 8006a94: d003 beq.n 8006a9e + { + temp |= iocurrent; + 8006a96: 69ba ldr r2, [r7, #24] + 8006a98: 693b ldr r3, [r7, #16] + 8006a9a: 4313 orrs r3, r2 + 8006a9c: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 8006a9e: 4a1f ldr r2, [pc, #124] ; (8006b1c ) + 8006aa0: 69bb ldr r3, [r7, #24] + 8006aa2: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8006aa4: 4b1d ldr r3, [pc, #116] ; (8006b1c ) + 8006aa6: 681b ldr r3, [r3, #0] + 8006aa8: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8006aaa: 693b ldr r3, [r7, #16] + 8006aac: 43db mvns r3, r3 + 8006aae: 69ba ldr r2, [r7, #24] + 8006ab0: 4013 ands r3, r2 + 8006ab2: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 8006ab4: 683b ldr r3, [r7, #0] + 8006ab6: 685b ldr r3, [r3, #4] + 8006ab8: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8006abc: 2b00 cmp r3, #0 + 8006abe: d003 beq.n 8006ac8 + { + temp |= iocurrent; + 8006ac0: 69ba ldr r2, [r7, #24] + 8006ac2: 693b ldr r3, [r7, #16] + 8006ac4: 4313 orrs r3, r2 + 8006ac6: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 8006ac8: 4a14 ldr r2, [pc, #80] ; (8006b1c ) + 8006aca: 69bb ldr r3, [r7, #24] + 8006acc: 6013 str r3, [r2, #0] + for(position = 0; position < GPIO_NUMBER; position++) + 8006ace: 69fb ldr r3, [r7, #28] + 8006ad0: 3301 adds r3, #1 + 8006ad2: 61fb str r3, [r7, #28] + 8006ad4: 69fb ldr r3, [r7, #28] + 8006ad6: 2b0f cmp r3, #15 + 8006ad8: f67f ae86 bls.w 80067e8 + } + } + } +} + 8006adc: bf00 nop + 8006ade: bf00 nop + 8006ae0: 3724 adds r7, #36 ; 0x24 + 8006ae2: 46bd mov sp, r7 + 8006ae4: f85d 7b04 ldr.w r7, [sp], #4 + 8006ae8: 4770 bx lr + 8006aea: bf00 nop + 8006aec: 40023800 .word 0x40023800 + 8006af0: 40013800 .word 0x40013800 + 8006af4: 40020000 .word 0x40020000 + 8006af8: 40020400 .word 0x40020400 + 8006afc: 40020800 .word 0x40020800 + 8006b00: 40020c00 .word 0x40020c00 + 8006b04: 40021000 .word 0x40021000 + 8006b08: 40021400 .word 0x40021400 + 8006b0c: 40021800 .word 0x40021800 + 8006b10: 40021c00 .word 0x40021c00 + 8006b14: 40022000 .word 0x40022000 + 8006b18: 40022400 .word 0x40022400 + 8006b1c: 40013c00 .word 0x40013c00 + +08006b20 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8006b20: b480 push {r7} + 8006b22: b083 sub sp, #12 + 8006b24: af00 add r7, sp, #0 + 8006b26: 6078 str r0, [r7, #4] + 8006b28: 460b mov r3, r1 + 8006b2a: 807b strh r3, [r7, #2] + 8006b2c: 4613 mov r3, r2 + 8006b2e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 8006b30: 787b ldrb r3, [r7, #1] + 8006b32: 2b00 cmp r3, #0 + 8006b34: d003 beq.n 8006b3e + { + GPIOx->BSRR = GPIO_Pin; + 8006b36: 887a ldrh r2, [r7, #2] + 8006b38: 687b ldr r3, [r7, #4] + 8006b3a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + 8006b3c: e003 b.n 8006b46 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 8006b3e: 887b ldrh r3, [r7, #2] + 8006b40: 041a lsls r2, r3, #16 + 8006b42: 687b ldr r3, [r7, #4] + 8006b44: 619a str r2, [r3, #24] +} + 8006b46: bf00 nop + 8006b48: 370c adds r7, #12 + 8006b4a: 46bd mov sp, r7 + 8006b4c: f85d 7b04 ldr.w r7, [sp], #4 + 8006b50: 4770 bx lr + ... + +08006b54 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 8006b54: b580 push {r7, lr} + 8006b56: b088 sub sp, #32 + 8006b58: af02 add r7, sp, #8 + 8006b5a: 60f8 str r0, [r7, #12] + 8006b5c: 607a str r2, [r7, #4] + 8006b5e: 461a mov r2, r3 + 8006b60: 460b mov r3, r1 + 8006b62: 817b strh r3, [r7, #10] + 8006b64: 4613 mov r3, r2 + 8006b66: 813b strh r3, [r7, #8] + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8006b68: 68fb ldr r3, [r7, #12] + 8006b6a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8006b6e: b2db uxtb r3, r3 + 8006b70: 2b20 cmp r3, #32 + 8006b72: f040 80da bne.w 8006d2a + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8006b76: 68fb ldr r3, [r7, #12] + 8006b78: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8006b7c: 2b01 cmp r3, #1 + 8006b7e: d101 bne.n 8006b84 + 8006b80: 2302 movs r3, #2 + 8006b82: e0d3 b.n 8006d2c + 8006b84: 68fb ldr r3, [r7, #12] + 8006b86: 2201 movs r2, #1 + 8006b88: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8006b8c: f7fd fe72 bl 8004874 + 8006b90: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8006b92: 697b ldr r3, [r7, #20] + 8006b94: 9300 str r3, [sp, #0] + 8006b96: 2319 movs r3, #25 + 8006b98: 2201 movs r2, #1 + 8006b9a: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8006b9e: 68f8 ldr r0, [r7, #12] + 8006ba0: f000 f9e6 bl 8006f70 + 8006ba4: 4603 mov r3, r0 + 8006ba6: 2b00 cmp r3, #0 + 8006ba8: d001 beq.n 8006bae + { + return HAL_ERROR; + 8006baa: 2301 movs r3, #1 + 8006bac: e0be b.n 8006d2c + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 8006bae: 68fb ldr r3, [r7, #12] + 8006bb0: 2221 movs r2, #33 ; 0x21 + 8006bb2: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8006bb6: 68fb ldr r3, [r7, #12] + 8006bb8: 2210 movs r2, #16 + 8006bba: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8006bbe: 68fb ldr r3, [r7, #12] + 8006bc0: 2200 movs r2, #0 + 8006bc2: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8006bc4: 68fb ldr r3, [r7, #12] + 8006bc6: 687a ldr r2, [r7, #4] + 8006bc8: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8006bca: 68fb ldr r3, [r7, #12] + 8006bcc: 893a ldrh r2, [r7, #8] + 8006bce: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8006bd0: 68fb ldr r3, [r7, #12] + 8006bd2: 2200 movs r2, #0 + 8006bd4: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8006bd6: 68fb ldr r3, [r7, #12] + 8006bd8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006bda: b29b uxth r3, r3 + 8006bdc: 2bff cmp r3, #255 ; 0xff + 8006bde: d90e bls.n 8006bfe + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8006be0: 68fb ldr r3, [r7, #12] + 8006be2: 22ff movs r2, #255 ; 0xff + 8006be4: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8006be6: 68fb ldr r3, [r7, #12] + 8006be8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006bea: b2da uxtb r2, r3 + 8006bec: 8979 ldrh r1, [r7, #10] + 8006bee: 4b51 ldr r3, [pc, #324] ; (8006d34 ) + 8006bf0: 9300 str r3, [sp, #0] + 8006bf2: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8006bf6: 68f8 ldr r0, [r7, #12] + 8006bf8: f000 fbd0 bl 800739c + 8006bfc: e06c b.n 8006cd8 + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006bfe: 68fb ldr r3, [r7, #12] + 8006c00: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006c02: b29a uxth r2, r3 + 8006c04: 68fb ldr r3, [r7, #12] + 8006c06: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8006c08: 68fb ldr r3, [r7, #12] + 8006c0a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006c0c: b2da uxtb r2, r3 + 8006c0e: 8979 ldrh r1, [r7, #10] + 8006c10: 4b48 ldr r3, [pc, #288] ; (8006d34 ) + 8006c12: 9300 str r3, [sp, #0] + 8006c14: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8006c18: 68f8 ldr r0, [r7, #12] + 8006c1a: f000 fbbf bl 800739c + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + 8006c1e: e05b b.n 8006cd8 + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8006c20: 697a ldr r2, [r7, #20] + 8006c22: 6a39 ldr r1, [r7, #32] + 8006c24: 68f8 ldr r0, [r7, #12] + 8006c26: f000 f9e3 bl 8006ff0 + 8006c2a: 4603 mov r3, r0 + 8006c2c: 2b00 cmp r3, #0 + 8006c2e: d001 beq.n 8006c34 + { + return HAL_ERROR; + 8006c30: 2301 movs r3, #1 + 8006c32: e07b b.n 8006d2c + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8006c34: 68fb ldr r3, [r7, #12] + 8006c36: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006c38: 781a ldrb r2, [r3, #0] + 8006c3a: 68fb ldr r3, [r7, #12] + 8006c3c: 681b ldr r3, [r3, #0] + 8006c3e: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8006c40: 68fb ldr r3, [r7, #12] + 8006c42: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006c44: 1c5a adds r2, r3, #1 + 8006c46: 68fb ldr r3, [r7, #12] + 8006c48: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 8006c4a: 68fb ldr r3, [r7, #12] + 8006c4c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006c4e: b29b uxth r3, r3 + 8006c50: 3b01 subs r3, #1 + 8006c52: b29a uxth r2, r3 + 8006c54: 68fb ldr r3, [r7, #12] + 8006c56: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8006c58: 68fb ldr r3, [r7, #12] + 8006c5a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006c5c: 3b01 subs r3, #1 + 8006c5e: b29a uxth r2, r3 + 8006c60: 68fb ldr r3, [r7, #12] + 8006c62: 851a strh r2, [r3, #40] ; 0x28 + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8006c64: 68fb ldr r3, [r7, #12] + 8006c66: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006c68: b29b uxth r3, r3 + 8006c6a: 2b00 cmp r3, #0 + 8006c6c: d034 beq.n 8006cd8 + 8006c6e: 68fb ldr r3, [r7, #12] + 8006c70: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006c72: 2b00 cmp r3, #0 + 8006c74: d130 bne.n 8006cd8 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8006c76: 697b ldr r3, [r7, #20] + 8006c78: 9300 str r3, [sp, #0] + 8006c7a: 6a3b ldr r3, [r7, #32] + 8006c7c: 2200 movs r2, #0 + 8006c7e: 2180 movs r1, #128 ; 0x80 + 8006c80: 68f8 ldr r0, [r7, #12] + 8006c82: f000 f975 bl 8006f70 + 8006c86: 4603 mov r3, r0 + 8006c88: 2b00 cmp r3, #0 + 8006c8a: d001 beq.n 8006c90 + { + return HAL_ERROR; + 8006c8c: 2301 movs r3, #1 + 8006c8e: e04d b.n 8006d2c + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8006c90: 68fb ldr r3, [r7, #12] + 8006c92: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006c94: b29b uxth r3, r3 + 8006c96: 2bff cmp r3, #255 ; 0xff + 8006c98: d90e bls.n 8006cb8 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8006c9a: 68fb ldr r3, [r7, #12] + 8006c9c: 22ff movs r2, #255 ; 0xff + 8006c9e: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8006ca0: 68fb ldr r3, [r7, #12] + 8006ca2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006ca4: b2da uxtb r2, r3 + 8006ca6: 8979 ldrh r1, [r7, #10] + 8006ca8: 2300 movs r3, #0 + 8006caa: 9300 str r3, [sp, #0] + 8006cac: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8006cb0: 68f8 ldr r0, [r7, #12] + 8006cb2: f000 fb73 bl 800739c + 8006cb6: e00f b.n 8006cd8 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006cb8: 68fb ldr r3, [r7, #12] + 8006cba: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006cbc: b29a uxth r2, r3 + 8006cbe: 68fb ldr r3, [r7, #12] + 8006cc0: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8006cc2: 68fb ldr r3, [r7, #12] + 8006cc4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006cc6: b2da uxtb r2, r3 + 8006cc8: 8979 ldrh r1, [r7, #10] + 8006cca: 2300 movs r3, #0 + 8006ccc: 9300 str r3, [sp, #0] + 8006cce: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8006cd2: 68f8 ldr r0, [r7, #12] + 8006cd4: f000 fb62 bl 800739c + while (hi2c->XferCount > 0U) + 8006cd8: 68fb ldr r3, [r7, #12] + 8006cda: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006cdc: b29b uxth r3, r3 + 8006cde: 2b00 cmp r3, #0 + 8006ce0: d19e bne.n 8006c20 + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8006ce2: 697a ldr r2, [r7, #20] + 8006ce4: 6a39 ldr r1, [r7, #32] + 8006ce6: 68f8 ldr r0, [r7, #12] + 8006ce8: f000 f9c2 bl 8007070 + 8006cec: 4603 mov r3, r0 + 8006cee: 2b00 cmp r3, #0 + 8006cf0: d001 beq.n 8006cf6 + { + return HAL_ERROR; + 8006cf2: 2301 movs r3, #1 + 8006cf4: e01a b.n 8006d2c + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8006cf6: 68fb ldr r3, [r7, #12] + 8006cf8: 681b ldr r3, [r3, #0] + 8006cfa: 2220 movs r2, #32 + 8006cfc: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8006cfe: 68fb ldr r3, [r7, #12] + 8006d00: 681b ldr r3, [r3, #0] + 8006d02: 6859 ldr r1, [r3, #4] + 8006d04: 68fb ldr r3, [r7, #12] + 8006d06: 681a ldr r2, [r3, #0] + 8006d08: 4b0b ldr r3, [pc, #44] ; (8006d38 ) + 8006d0a: 400b ands r3, r1 + 8006d0c: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8006d0e: 68fb ldr r3, [r7, #12] + 8006d10: 2220 movs r2, #32 + 8006d12: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006d16: 68fb ldr r3, [r7, #12] + 8006d18: 2200 movs r2, #0 + 8006d1a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006d1e: 68fb ldr r3, [r7, #12] + 8006d20: 2200 movs r2, #0 + 8006d22: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006d26: 2300 movs r3, #0 + 8006d28: e000 b.n 8006d2c + } + else + { + return HAL_BUSY; + 8006d2a: 2302 movs r3, #2 + } +} + 8006d2c: 4618 mov r0, r3 + 8006d2e: 3718 adds r7, #24 + 8006d30: 46bd mov sp, r7 + 8006d32: bd80 pop {r7, pc} + 8006d34: 80002000 .word 0x80002000 + 8006d38: fe00e800 .word 0xfe00e800 + +08006d3c : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 8006d3c: b580 push {r7, lr} + 8006d3e: b088 sub sp, #32 + 8006d40: af02 add r7, sp, #8 + 8006d42: 60f8 str r0, [r7, #12] + 8006d44: 607a str r2, [r7, #4] + 8006d46: 461a mov r2, r3 + 8006d48: 460b mov r3, r1 + 8006d4a: 817b strh r3, [r7, #10] + 8006d4c: 4613 mov r3, r2 + 8006d4e: 813b strh r3, [r7, #8] + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8006d50: 68fb ldr r3, [r7, #12] + 8006d52: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8006d56: b2db uxtb r3, r3 + 8006d58: 2b20 cmp r3, #32 + 8006d5a: f040 80db bne.w 8006f14 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8006d5e: 68fb ldr r3, [r7, #12] + 8006d60: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8006d64: 2b01 cmp r3, #1 + 8006d66: d101 bne.n 8006d6c + 8006d68: 2302 movs r3, #2 + 8006d6a: e0d4 b.n 8006f16 + 8006d6c: 68fb ldr r3, [r7, #12] + 8006d6e: 2201 movs r2, #1 + 8006d70: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8006d74: f7fd fd7e bl 8004874 + 8006d78: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8006d7a: 697b ldr r3, [r7, #20] + 8006d7c: 9300 str r3, [sp, #0] + 8006d7e: 2319 movs r3, #25 + 8006d80: 2201 movs r2, #1 + 8006d82: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8006d86: 68f8 ldr r0, [r7, #12] + 8006d88: f000 f8f2 bl 8006f70 + 8006d8c: 4603 mov r3, r0 + 8006d8e: 2b00 cmp r3, #0 + 8006d90: d001 beq.n 8006d96 + { + return HAL_ERROR; + 8006d92: 2301 movs r3, #1 + 8006d94: e0bf b.n 8006f16 + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 8006d96: 68fb ldr r3, [r7, #12] + 8006d98: 2222 movs r2, #34 ; 0x22 + 8006d9a: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8006d9e: 68fb ldr r3, [r7, #12] + 8006da0: 2210 movs r2, #16 + 8006da2: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8006da6: 68fb ldr r3, [r7, #12] + 8006da8: 2200 movs r2, #0 + 8006daa: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8006dac: 68fb ldr r3, [r7, #12] + 8006dae: 687a ldr r2, [r7, #4] + 8006db0: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8006db2: 68fb ldr r3, [r7, #12] + 8006db4: 893a ldrh r2, [r7, #8] + 8006db6: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8006db8: 68fb ldr r3, [r7, #12] + 8006dba: 2200 movs r2, #0 + 8006dbc: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8006dbe: 68fb ldr r3, [r7, #12] + 8006dc0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006dc2: b29b uxth r3, r3 + 8006dc4: 2bff cmp r3, #255 ; 0xff + 8006dc6: d90e bls.n 8006de6 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8006dc8: 68fb ldr r3, [r7, #12] + 8006dca: 22ff movs r2, #255 ; 0xff + 8006dcc: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8006dce: 68fb ldr r3, [r7, #12] + 8006dd0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006dd2: b2da uxtb r2, r3 + 8006dd4: 8979 ldrh r1, [r7, #10] + 8006dd6: 4b52 ldr r3, [pc, #328] ; (8006f20 ) + 8006dd8: 9300 str r3, [sp, #0] + 8006dda: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8006dde: 68f8 ldr r0, [r7, #12] + 8006de0: f000 fadc bl 800739c + 8006de4: e06d b.n 8006ec2 + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006de6: 68fb ldr r3, [r7, #12] + 8006de8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006dea: b29a uxth r2, r3 + 8006dec: 68fb ldr r3, [r7, #12] + 8006dee: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8006df0: 68fb ldr r3, [r7, #12] + 8006df2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006df4: b2da uxtb r2, r3 + 8006df6: 8979 ldrh r1, [r7, #10] + 8006df8: 4b49 ldr r3, [pc, #292] ; (8006f20 ) + 8006dfa: 9300 str r3, [sp, #0] + 8006dfc: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8006e00: 68f8 ldr r0, [r7, #12] + 8006e02: f000 facb bl 800739c + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + 8006e06: e05c b.n 8006ec2 + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8006e08: 697a ldr r2, [r7, #20] + 8006e0a: 6a39 ldr r1, [r7, #32] + 8006e0c: 68f8 ldr r0, [r7, #12] + 8006e0e: f000 f96b bl 80070e8 + 8006e12: 4603 mov r3, r0 + 8006e14: 2b00 cmp r3, #0 + 8006e16: d001 beq.n 8006e1c + { + return HAL_ERROR; + 8006e18: 2301 movs r3, #1 + 8006e1a: e07c b.n 8006f16 + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 8006e1c: 68fb ldr r3, [r7, #12] + 8006e1e: 681b ldr r3, [r3, #0] + 8006e20: 6a5a ldr r2, [r3, #36] ; 0x24 + 8006e22: 68fb ldr r3, [r7, #12] + 8006e24: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006e26: b2d2 uxtb r2, r2 + 8006e28: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8006e2a: 68fb ldr r3, [r7, #12] + 8006e2c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006e2e: 1c5a adds r2, r3, #1 + 8006e30: 68fb ldr r3, [r7, #12] + 8006e32: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 8006e34: 68fb ldr r3, [r7, #12] + 8006e36: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006e38: 3b01 subs r3, #1 + 8006e3a: b29a uxth r2, r3 + 8006e3c: 68fb ldr r3, [r7, #12] + 8006e3e: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8006e40: 68fb ldr r3, [r7, #12] + 8006e42: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006e44: b29b uxth r3, r3 + 8006e46: 3b01 subs r3, #1 + 8006e48: b29a uxth r2, r3 + 8006e4a: 68fb ldr r3, [r7, #12] + 8006e4c: 855a strh r2, [r3, #42] ; 0x2a + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8006e4e: 68fb ldr r3, [r7, #12] + 8006e50: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006e52: b29b uxth r3, r3 + 8006e54: 2b00 cmp r3, #0 + 8006e56: d034 beq.n 8006ec2 + 8006e58: 68fb ldr r3, [r7, #12] + 8006e5a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006e5c: 2b00 cmp r3, #0 + 8006e5e: d130 bne.n 8006ec2 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8006e60: 697b ldr r3, [r7, #20] + 8006e62: 9300 str r3, [sp, #0] + 8006e64: 6a3b ldr r3, [r7, #32] + 8006e66: 2200 movs r2, #0 + 8006e68: 2180 movs r1, #128 ; 0x80 + 8006e6a: 68f8 ldr r0, [r7, #12] + 8006e6c: f000 f880 bl 8006f70 + 8006e70: 4603 mov r3, r0 + 8006e72: 2b00 cmp r3, #0 + 8006e74: d001 beq.n 8006e7a + { + return HAL_ERROR; + 8006e76: 2301 movs r3, #1 + 8006e78: e04d b.n 8006f16 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8006e7a: 68fb ldr r3, [r7, #12] + 8006e7c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006e7e: b29b uxth r3, r3 + 8006e80: 2bff cmp r3, #255 ; 0xff + 8006e82: d90e bls.n 8006ea2 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8006e84: 68fb ldr r3, [r7, #12] + 8006e86: 22ff movs r2, #255 ; 0xff + 8006e88: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8006e8a: 68fb ldr r3, [r7, #12] + 8006e8c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006e8e: b2da uxtb r2, r3 + 8006e90: 8979 ldrh r1, [r7, #10] + 8006e92: 2300 movs r3, #0 + 8006e94: 9300 str r3, [sp, #0] + 8006e96: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8006e9a: 68f8 ldr r0, [r7, #12] + 8006e9c: f000 fa7e bl 800739c + 8006ea0: e00f b.n 8006ec2 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006ea2: 68fb ldr r3, [r7, #12] + 8006ea4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006ea6: b29a uxth r2, r3 + 8006ea8: 68fb ldr r3, [r7, #12] + 8006eaa: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8006eac: 68fb ldr r3, [r7, #12] + 8006eae: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006eb0: b2da uxtb r2, r3 + 8006eb2: 8979 ldrh r1, [r7, #10] + 8006eb4: 2300 movs r3, #0 + 8006eb6: 9300 str r3, [sp, #0] + 8006eb8: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8006ebc: 68f8 ldr r0, [r7, #12] + 8006ebe: f000 fa6d bl 800739c + while (hi2c->XferCount > 0U) + 8006ec2: 68fb ldr r3, [r7, #12] + 8006ec4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006ec6: b29b uxth r3, r3 + 8006ec8: 2b00 cmp r3, #0 + 8006eca: d19d bne.n 8006e08 + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8006ecc: 697a ldr r2, [r7, #20] + 8006ece: 6a39 ldr r1, [r7, #32] + 8006ed0: 68f8 ldr r0, [r7, #12] + 8006ed2: f000 f8cd bl 8007070 + 8006ed6: 4603 mov r3, r0 + 8006ed8: 2b00 cmp r3, #0 + 8006eda: d001 beq.n 8006ee0 + { + return HAL_ERROR; + 8006edc: 2301 movs r3, #1 + 8006ede: e01a b.n 8006f16 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8006ee0: 68fb ldr r3, [r7, #12] + 8006ee2: 681b ldr r3, [r3, #0] + 8006ee4: 2220 movs r2, #32 + 8006ee6: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8006ee8: 68fb ldr r3, [r7, #12] + 8006eea: 681b ldr r3, [r3, #0] + 8006eec: 6859 ldr r1, [r3, #4] + 8006eee: 68fb ldr r3, [r7, #12] + 8006ef0: 681a ldr r2, [r3, #0] + 8006ef2: 4b0c ldr r3, [pc, #48] ; (8006f24 ) + 8006ef4: 400b ands r3, r1 + 8006ef6: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8006ef8: 68fb ldr r3, [r7, #12] + 8006efa: 2220 movs r2, #32 + 8006efc: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006f00: 68fb ldr r3, [r7, #12] + 8006f02: 2200 movs r2, #0 + 8006f04: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006f08: 68fb ldr r3, [r7, #12] + 8006f0a: 2200 movs r2, #0 + 8006f0c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006f10: 2300 movs r3, #0 + 8006f12: e000 b.n 8006f16 + } + else + { + return HAL_BUSY; + 8006f14: 2302 movs r3, #2 + } +} + 8006f16: 4618 mov r0, r3 + 8006f18: 3718 adds r7, #24 + 8006f1a: 46bd mov sp, r7 + 8006f1c: bd80 pop {r7, pc} + 8006f1e: bf00 nop + 8006f20: 80002400 .word 0x80002400 + 8006f24: fe00e800 .word 0xfe00e800 + +08006f28 : + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + 8006f28: b480 push {r7} + 8006f2a: b083 sub sp, #12 + 8006f2c: af00 add r7, sp, #0 + 8006f2e: 6078 str r0, [r7, #4] + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 8006f30: 687b ldr r3, [r7, #4] + 8006f32: 681b ldr r3, [r3, #0] + 8006f34: 699b ldr r3, [r3, #24] + 8006f36: f003 0302 and.w r3, r3, #2 + 8006f3a: 2b02 cmp r3, #2 + 8006f3c: d103 bne.n 8006f46 + { + hi2c->Instance->TXDR = 0x00U; + 8006f3e: 687b ldr r3, [r7, #4] + 8006f40: 681b ldr r3, [r3, #0] + 8006f42: 2200 movs r2, #0 + 8006f44: 629a str r2, [r3, #40] ; 0x28 + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8006f46: 687b ldr r3, [r7, #4] + 8006f48: 681b ldr r3, [r3, #0] + 8006f4a: 699b ldr r3, [r3, #24] + 8006f4c: f003 0301 and.w r3, r3, #1 + 8006f50: 2b01 cmp r3, #1 + 8006f52: d007 beq.n 8006f64 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 8006f54: 687b ldr r3, [r7, #4] + 8006f56: 681b ldr r3, [r3, #0] + 8006f58: 699a ldr r2, [r3, #24] + 8006f5a: 687b ldr r3, [r7, #4] + 8006f5c: 681b ldr r3, [r3, #0] + 8006f5e: f042 0201 orr.w r2, r2, #1 + 8006f62: 619a str r2, [r3, #24] + } +} + 8006f64: bf00 nop + 8006f66: 370c adds r7, #12 + 8006f68: 46bd mov sp, r7 + 8006f6a: f85d 7b04 ldr.w r7, [sp], #4 + 8006f6e: 4770 bx lr + +08006f70 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + 8006f70: b580 push {r7, lr} + 8006f72: b084 sub sp, #16 + 8006f74: af00 add r7, sp, #0 + 8006f76: 60f8 str r0, [r7, #12] + 8006f78: 60b9 str r1, [r7, #8] + 8006f7a: 603b str r3, [r7, #0] + 8006f7c: 4613 mov r3, r2 + 8006f7e: 71fb strb r3, [r7, #7] + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8006f80: e022 b.n 8006fc8 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8006f82: 683b ldr r3, [r7, #0] + 8006f84: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8006f88: d01e beq.n 8006fc8 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8006f8a: f7fd fc73 bl 8004874 + 8006f8e: 4602 mov r2, r0 + 8006f90: 69bb ldr r3, [r7, #24] + 8006f92: 1ad3 subs r3, r2, r3 + 8006f94: 683a ldr r2, [r7, #0] + 8006f96: 429a cmp r2, r3 + 8006f98: d302 bcc.n 8006fa0 + 8006f9a: 683b ldr r3, [r7, #0] + 8006f9c: 2b00 cmp r3, #0 + 8006f9e: d113 bne.n 8006fc8 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8006fa0: 68fb ldr r3, [r7, #12] + 8006fa2: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006fa4: f043 0220 orr.w r2, r3, #32 + 8006fa8: 68fb ldr r3, [r7, #12] + 8006faa: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8006fac: 68fb ldr r3, [r7, #12] + 8006fae: 2220 movs r2, #32 + 8006fb0: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006fb4: 68fb ldr r3, [r7, #12] + 8006fb6: 2200 movs r2, #0 + 8006fb8: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006fbc: 68fb ldr r3, [r7, #12] + 8006fbe: 2200 movs r2, #0 + 8006fc0: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8006fc4: 2301 movs r3, #1 + 8006fc6: e00f b.n 8006fe8 + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8006fc8: 68fb ldr r3, [r7, #12] + 8006fca: 681b ldr r3, [r3, #0] + 8006fcc: 699a ldr r2, [r3, #24] + 8006fce: 68bb ldr r3, [r7, #8] + 8006fd0: 4013 ands r3, r2 + 8006fd2: 68ba ldr r2, [r7, #8] + 8006fd4: 429a cmp r2, r3 + 8006fd6: bf0c ite eq + 8006fd8: 2301 moveq r3, #1 + 8006fda: 2300 movne r3, #0 + 8006fdc: b2db uxtb r3, r3 + 8006fde: 461a mov r2, r3 + 8006fe0: 79fb ldrb r3, [r7, #7] + 8006fe2: 429a cmp r2, r3 + 8006fe4: d0cd beq.n 8006f82 + } + } + } + return HAL_OK; + 8006fe6: 2300 movs r3, #0 +} + 8006fe8: 4618 mov r0, r3 + 8006fea: 3710 adds r7, #16 + 8006fec: 46bd mov sp, r7 + 8006fee: bd80 pop {r7, pc} + +08006ff0 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 8006ff0: b580 push {r7, lr} + 8006ff2: b084 sub sp, #16 + 8006ff4: af00 add r7, sp, #0 + 8006ff6: 60f8 str r0, [r7, #12] + 8006ff8: 60b9 str r1, [r7, #8] + 8006ffa: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 8006ffc: e02c b.n 8007058 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 8006ffe: 687a ldr r2, [r7, #4] + 8007000: 68b9 ldr r1, [r7, #8] + 8007002: 68f8 ldr r0, [r7, #12] + 8007004: f000 f8ea bl 80071dc + 8007008: 4603 mov r3, r0 + 800700a: 2b00 cmp r3, #0 + 800700c: d001 beq.n 8007012 + { + return HAL_ERROR; + 800700e: 2301 movs r3, #1 + 8007010: e02a b.n 8007068 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8007012: 68bb ldr r3, [r7, #8] + 8007014: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8007018: d01e beq.n 8007058 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800701a: f7fd fc2b bl 8004874 + 800701e: 4602 mov r2, r0 + 8007020: 687b ldr r3, [r7, #4] + 8007022: 1ad3 subs r3, r2, r3 + 8007024: 68ba ldr r2, [r7, #8] + 8007026: 429a cmp r2, r3 + 8007028: d302 bcc.n 8007030 + 800702a: 68bb ldr r3, [r7, #8] + 800702c: 2b00 cmp r3, #0 + 800702e: d113 bne.n 8007058 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8007030: 68fb ldr r3, [r7, #12] + 8007032: 6c5b ldr r3, [r3, #68] ; 0x44 + 8007034: f043 0220 orr.w r2, r3, #32 + 8007038: 68fb ldr r3, [r7, #12] + 800703a: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 800703c: 68fb ldr r3, [r7, #12] + 800703e: 2220 movs r2, #32 + 8007040: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8007044: 68fb ldr r3, [r7, #12] + 8007046: 2200 movs r2, #0 + 8007048: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800704c: 68fb ldr r3, [r7, #12] + 800704e: 2200 movs r2, #0 + 8007050: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8007054: 2301 movs r3, #1 + 8007056: e007 b.n 8007068 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 8007058: 68fb ldr r3, [r7, #12] + 800705a: 681b ldr r3, [r3, #0] + 800705c: 699b ldr r3, [r3, #24] + 800705e: f003 0302 and.w r3, r3, #2 + 8007062: 2b02 cmp r3, #2 + 8007064: d1cb bne.n 8006ffe + } + } + } + return HAL_OK; + 8007066: 2300 movs r3, #0 +} + 8007068: 4618 mov r0, r3 + 800706a: 3710 adds r7, #16 + 800706c: 46bd mov sp, r7 + 800706e: bd80 pop {r7, pc} + +08007070 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 8007070: b580 push {r7, lr} + 8007072: b084 sub sp, #16 + 8007074: af00 add r7, sp, #0 + 8007076: 60f8 str r0, [r7, #12] + 8007078: 60b9 str r1, [r7, #8] + 800707a: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 800707c: e028 b.n 80070d0 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 800707e: 687a ldr r2, [r7, #4] + 8007080: 68b9 ldr r1, [r7, #8] + 8007082: 68f8 ldr r0, [r7, #12] + 8007084: f000 f8aa bl 80071dc + 8007088: 4603 mov r3, r0 + 800708a: 2b00 cmp r3, #0 + 800708c: d001 beq.n 8007092 + { + return HAL_ERROR; + 800708e: 2301 movs r3, #1 + 8007090: e026 b.n 80070e0 + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8007092: f7fd fbef bl 8004874 + 8007096: 4602 mov r2, r0 + 8007098: 687b ldr r3, [r7, #4] + 800709a: 1ad3 subs r3, r2, r3 + 800709c: 68ba ldr r2, [r7, #8] + 800709e: 429a cmp r2, r3 + 80070a0: d302 bcc.n 80070a8 + 80070a2: 68bb ldr r3, [r7, #8] + 80070a4: 2b00 cmp r3, #0 + 80070a6: d113 bne.n 80070d0 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 80070a8: 68fb ldr r3, [r7, #12] + 80070aa: 6c5b ldr r3, [r3, #68] ; 0x44 + 80070ac: f043 0220 orr.w r2, r3, #32 + 80070b0: 68fb ldr r3, [r7, #12] + 80070b2: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80070b4: 68fb ldr r3, [r7, #12] + 80070b6: 2220 movs r2, #32 + 80070b8: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80070bc: 68fb ldr r3, [r7, #12] + 80070be: 2200 movs r2, #0 + 80070c0: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80070c4: 68fb ldr r3, [r7, #12] + 80070c6: 2200 movs r2, #0 + 80070c8: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80070cc: 2301 movs r3, #1 + 80070ce: e007 b.n 80070e0 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 80070d0: 68fb ldr r3, [r7, #12] + 80070d2: 681b ldr r3, [r3, #0] + 80070d4: 699b ldr r3, [r3, #24] + 80070d6: f003 0320 and.w r3, r3, #32 + 80070da: 2b20 cmp r3, #32 + 80070dc: d1cf bne.n 800707e + } + } + return HAL_OK; + 80070de: 2300 movs r3, #0 +} + 80070e0: 4618 mov r0, r3 + 80070e2: 3710 adds r7, #16 + 80070e4: 46bd mov sp, r7 + 80070e6: bd80 pop {r7, pc} + +080070e8 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 80070e8: b580 push {r7, lr} + 80070ea: b084 sub sp, #16 + 80070ec: af00 add r7, sp, #0 + 80070ee: 60f8 str r0, [r7, #12] + 80070f0: 60b9 str r1, [r7, #8] + 80070f2: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 80070f4: e064 b.n 80071c0 + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 80070f6: 687a ldr r2, [r7, #4] + 80070f8: 68b9 ldr r1, [r7, #8] + 80070fa: 68f8 ldr r0, [r7, #12] + 80070fc: f000 f86e bl 80071dc + 8007100: 4603 mov r3, r0 + 8007102: 2b00 cmp r3, #0 + 8007104: d001 beq.n 800710a + { + return HAL_ERROR; + 8007106: 2301 movs r3, #1 + 8007108: e062 b.n 80071d0 + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 800710a: 68fb ldr r3, [r7, #12] + 800710c: 681b ldr r3, [r3, #0] + 800710e: 699b ldr r3, [r3, #24] + 8007110: f003 0320 and.w r3, r3, #32 + 8007114: 2b20 cmp r3, #32 + 8007116: d138 bne.n 800718a + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + 8007118: 68fb ldr r3, [r7, #12] + 800711a: 681b ldr r3, [r3, #0] + 800711c: 699b ldr r3, [r3, #24] + 800711e: f003 0304 and.w r3, r3, #4 + 8007122: 2b04 cmp r3, #4 + 8007124: d105 bne.n 8007132 + 8007126: 68fb ldr r3, [r7, #12] + 8007128: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800712a: 2b00 cmp r3, #0 + 800712c: d001 beq.n 8007132 + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + 800712e: 2300 movs r3, #0 + 8007130: e04e b.n 80071d0 + } + else + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 8007132: 68fb ldr r3, [r7, #12] + 8007134: 681b ldr r3, [r3, #0] + 8007136: 699b ldr r3, [r3, #24] + 8007138: f003 0310 and.w r3, r3, #16 + 800713c: 2b10 cmp r3, #16 + 800713e: d107 bne.n 8007150 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8007140: 68fb ldr r3, [r7, #12] + 8007142: 681b ldr r3, [r3, #0] + 8007144: 2210 movs r2, #16 + 8007146: 61da str r2, [r3, #28] + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + 8007148: 68fb ldr r3, [r7, #12] + 800714a: 2204 movs r2, #4 + 800714c: 645a str r2, [r3, #68] ; 0x44 + 800714e: e002 b.n 8007156 + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8007150: 68fb ldr r3, [r7, #12] + 8007152: 2200 movs r2, #0 + 8007154: 645a str r2, [r3, #68] ; 0x44 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8007156: 68fb ldr r3, [r7, #12] + 8007158: 681b ldr r3, [r3, #0] + 800715a: 2220 movs r2, #32 + 800715c: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 800715e: 68fb ldr r3, [r7, #12] + 8007160: 681b ldr r3, [r3, #0] + 8007162: 6859 ldr r1, [r3, #4] + 8007164: 68fb ldr r3, [r7, #12] + 8007166: 681a ldr r2, [r3, #0] + 8007168: 4b1b ldr r3, [pc, #108] ; (80071d8 ) + 800716a: 400b ands r3, r1 + 800716c: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 800716e: 68fb ldr r3, [r7, #12] + 8007170: 2220 movs r2, #32 + 8007172: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8007176: 68fb ldr r3, [r7, #12] + 8007178: 2200 movs r2, #0 + 800717a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800717e: 68fb ldr r3, [r7, #12] + 8007180: 2200 movs r2, #0 + 8007182: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8007186: 2301 movs r3, #1 + 8007188: e022 b.n 80071d0 + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800718a: f7fd fb73 bl 8004874 + 800718e: 4602 mov r2, r0 + 8007190: 687b ldr r3, [r7, #4] + 8007192: 1ad3 subs r3, r2, r3 + 8007194: 68ba ldr r2, [r7, #8] + 8007196: 429a cmp r2, r3 + 8007198: d302 bcc.n 80071a0 + 800719a: 68bb ldr r3, [r7, #8] + 800719c: 2b00 cmp r3, #0 + 800719e: d10f bne.n 80071c0 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 80071a0: 68fb ldr r3, [r7, #12] + 80071a2: 6c5b ldr r3, [r3, #68] ; 0x44 + 80071a4: f043 0220 orr.w r2, r3, #32 + 80071a8: 68fb ldr r3, [r7, #12] + 80071aa: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80071ac: 68fb ldr r3, [r7, #12] + 80071ae: 2220 movs r2, #32 + 80071b0: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80071b4: 68fb ldr r3, [r7, #12] + 80071b6: 2200 movs r2, #0 + 80071b8: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80071bc: 2301 movs r3, #1 + 80071be: e007 b.n 80071d0 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 80071c0: 68fb ldr r3, [r7, #12] + 80071c2: 681b ldr r3, [r3, #0] + 80071c4: 699b ldr r3, [r3, #24] + 80071c6: f003 0304 and.w r3, r3, #4 + 80071ca: 2b04 cmp r3, #4 + 80071cc: d193 bne.n 80070f6 + } + } + return HAL_OK; + 80071ce: 2300 movs r3, #0 +} + 80071d0: 4618 mov r0, r3 + 80071d2: 3710 adds r7, #16 + 80071d4: 46bd mov sp, r7 + 80071d6: bd80 pop {r7, pc} + 80071d8: fe00e800 .word 0xfe00e800 + +080071dc : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 80071dc: b580 push {r7, lr} + 80071de: b08a sub sp, #40 ; 0x28 + 80071e0: af00 add r7, sp, #0 + 80071e2: 60f8 str r0, [r7, #12] + 80071e4: 60b9 str r1, [r7, #8] + 80071e6: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80071e8: 2300 movs r3, #0 + 80071ea: f887 3027 strb.w r3, [r7, #39] ; 0x27 + uint32_t itflag = hi2c->Instance->ISR; + 80071ee: 68fb ldr r3, [r7, #12] + 80071f0: 681b ldr r3, [r3, #0] + 80071f2: 699b ldr r3, [r3, #24] + 80071f4: 61bb str r3, [r7, #24] + uint32_t error_code = 0; + 80071f6: 2300 movs r3, #0 + 80071f8: 623b str r3, [r7, #32] + uint32_t tickstart = Tickstart; + 80071fa: 687b ldr r3, [r7, #4] + 80071fc: 61fb str r3, [r7, #28] + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + 80071fe: 69bb ldr r3, [r7, #24] + 8007200: f003 0310 and.w r3, r3, #16 + 8007204: 2b00 cmp r3, #0 + 8007206: d068 beq.n 80072da + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8007208: 68fb ldr r3, [r7, #12] + 800720a: 681b ldr r3, [r3, #0] + 800720c: 2210 movs r2, #16 + 800720e: 61da str r2, [r3, #28] + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + 8007210: e049 b.n 80072a6 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8007212: 68bb ldr r3, [r7, #8] + 8007214: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8007218: d045 beq.n 80072a6 + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 800721a: f7fd fb2b bl 8004874 + 800721e: 4602 mov r2, r0 + 8007220: 69fb ldr r3, [r7, #28] + 8007222: 1ad3 subs r3, r2, r3 + 8007224: 68ba ldr r2, [r7, #8] + 8007226: 429a cmp r2, r3 + 8007228: d302 bcc.n 8007230 + 800722a: 68bb ldr r3, [r7, #8] + 800722c: 2b00 cmp r3, #0 + 800722e: d13a bne.n 80072a6 + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + 8007230: 68fb ldr r3, [r7, #12] + 8007232: 681b ldr r3, [r3, #0] + 8007234: 685b ldr r3, [r3, #4] + 8007236: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800723a: 617b str r3, [r7, #20] + tmp2 = hi2c->Mode; + 800723c: 68fb ldr r3, [r7, #12] + 800723e: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8007242: 74fb strb r3, [r7, #19] + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + 8007244: 68fb ldr r3, [r7, #12] + 8007246: 681b ldr r3, [r3, #0] + 8007248: 699b ldr r3, [r3, #24] + 800724a: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 800724e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8007252: d121 bne.n 8007298 + 8007254: 697b ldr r3, [r7, #20] + 8007256: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 800725a: d01d beq.n 8007298 + (tmp1 != I2C_CR2_STOP) && \ + 800725c: 7cfb ldrb r3, [r7, #19] + 800725e: 2b20 cmp r3, #32 + 8007260: d01a beq.n 8007298 + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + 8007262: 68fb ldr r3, [r7, #12] + 8007264: 681b ldr r3, [r3, #0] + 8007266: 685a ldr r2, [r3, #4] + 8007268: 68fb ldr r3, [r7, #12] + 800726a: 681b ldr r3, [r3, #0] + 800726c: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8007270: 605a str r2, [r3, #4] + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + 8007272: f7fd faff bl 8004874 + 8007276: 61f8 str r0, [r7, #28] + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8007278: e00e b.n 8007298 + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + 800727a: f7fd fafb bl 8004874 + 800727e: 4602 mov r2, r0 + 8007280: 69fb ldr r3, [r7, #28] + 8007282: 1ad3 subs r3, r2, r3 + 8007284: 2b19 cmp r3, #25 + 8007286: d907 bls.n 8007298 + { + error_code |=HAL_I2C_ERROR_TIMEOUT; + 8007288: 6a3b ldr r3, [r7, #32] + 800728a: f043 0320 orr.w r3, r3, #32 + 800728e: 623b str r3, [r7, #32] + + status = HAL_ERROR; + 8007290: 2301 movs r3, #1 + 8007292: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + break; + 8007296: e006 b.n 80072a6 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8007298: 68fb ldr r3, [r7, #12] + 800729a: 681b ldr r3, [r3, #0] + 800729c: 699b ldr r3, [r3, #24] + 800729e: f003 0320 and.w r3, r3, #32 + 80072a2: 2b20 cmp r3, #32 + 80072a4: d1e9 bne.n 800727a + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + 80072a6: 68fb ldr r3, [r7, #12] + 80072a8: 681b ldr r3, [r3, #0] + 80072aa: 699b ldr r3, [r3, #24] + 80072ac: f003 0320 and.w r3, r3, #32 + 80072b0: 2b20 cmp r3, #32 + 80072b2: d003 beq.n 80072bc + 80072b4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80072b8: 2b00 cmp r3, #0 + 80072ba: d0aa beq.n 8007212 + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + 80072bc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80072c0: 2b00 cmp r3, #0 + 80072c2: d103 bne.n 80072cc + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80072c4: 68fb ldr r3, [r7, #12] + 80072c6: 681b ldr r3, [r3, #0] + 80072c8: 2220 movs r2, #32 + 80072ca: 61da str r2, [r3, #28] + } + + error_code |= HAL_I2C_ERROR_AF; + 80072cc: 6a3b ldr r3, [r7, #32] + 80072ce: f043 0304 orr.w r3, r3, #4 + 80072d2: 623b str r3, [r7, #32] + + status = HAL_ERROR; + 80072d4: 2301 movs r3, #1 + 80072d6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + 80072da: 68fb ldr r3, [r7, #12] + 80072dc: 681b ldr r3, [r3, #0] + 80072de: 699b ldr r3, [r3, #24] + 80072e0: 61bb str r3, [r7, #24] + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + 80072e2: 69bb ldr r3, [r7, #24] + 80072e4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80072e8: 2b00 cmp r3, #0 + 80072ea: d00b beq.n 8007304 + { + error_code |= HAL_I2C_ERROR_BERR; + 80072ec: 6a3b ldr r3, [r7, #32] + 80072ee: f043 0301 orr.w r3, r3, #1 + 80072f2: 623b str r3, [r7, #32] + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + 80072f4: 68fb ldr r3, [r7, #12] + 80072f6: 681b ldr r3, [r3, #0] + 80072f8: f44f 7280 mov.w r2, #256 ; 0x100 + 80072fc: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 80072fe: 2301 movs r3, #1 + 8007300: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + 8007304: 69bb ldr r3, [r7, #24] + 8007306: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800730a: 2b00 cmp r3, #0 + 800730c: d00b beq.n 8007326 + { + error_code |= HAL_I2C_ERROR_OVR; + 800730e: 6a3b ldr r3, [r7, #32] + 8007310: f043 0308 orr.w r3, r3, #8 + 8007314: 623b str r3, [r7, #32] + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + 8007316: 68fb ldr r3, [r7, #12] + 8007318: 681b ldr r3, [r3, #0] + 800731a: f44f 6280 mov.w r2, #1024 ; 0x400 + 800731e: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 8007320: 2301 movs r3, #1 + 8007322: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + 8007326: 69bb ldr r3, [r7, #24] + 8007328: f403 7300 and.w r3, r3, #512 ; 0x200 + 800732c: 2b00 cmp r3, #0 + 800732e: d00b beq.n 8007348 + { + error_code |= HAL_I2C_ERROR_ARLO; + 8007330: 6a3b ldr r3, [r7, #32] + 8007332: f043 0302 orr.w r3, r3, #2 + 8007336: 623b str r3, [r7, #32] + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + 8007338: 68fb ldr r3, [r7, #12] + 800733a: 681b ldr r3, [r3, #0] + 800733c: f44f 7200 mov.w r2, #512 ; 0x200 + 8007340: 61da str r2, [r3, #28] + + status = HAL_ERROR; + 8007342: 2301 movs r3, #1 + 8007344: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + if (status != HAL_OK) + 8007348: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800734c: 2b00 cmp r3, #0 + 800734e: d01c beq.n 800738a + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8007350: 68f8 ldr r0, [r7, #12] + 8007352: f7ff fde9 bl 8006f28 + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8007356: 68fb ldr r3, [r7, #12] + 8007358: 681b ldr r3, [r3, #0] + 800735a: 6859 ldr r1, [r3, #4] + 800735c: 68fb ldr r3, [r7, #12] + 800735e: 681a ldr r2, [r3, #0] + 8007360: 4b0d ldr r3, [pc, #52] ; (8007398 ) + 8007362: 400b ands r3, r1 + 8007364: 6053 str r3, [r2, #4] + + hi2c->ErrorCode |= error_code; + 8007366: 68fb ldr r3, [r7, #12] + 8007368: 6c5a ldr r2, [r3, #68] ; 0x44 + 800736a: 6a3b ldr r3, [r7, #32] + 800736c: 431a orrs r2, r3 + 800736e: 68fb ldr r3, [r7, #12] + 8007370: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8007372: 68fb ldr r3, [r7, #12] + 8007374: 2220 movs r2, #32 + 8007376: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 800737a: 68fb ldr r3, [r7, #12] + 800737c: 2200 movs r2, #0 + 800737e: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8007382: 68fb ldr r3, [r7, #12] + 8007384: 2200 movs r2, #0 + 8007386: f883 2040 strb.w r2, [r3, #64] ; 0x40 + } + + return status; + 800738a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 +} + 800738e: 4618 mov r0, r3 + 8007390: 3728 adds r7, #40 ; 0x28 + 8007392: 46bd mov sp, r7 + 8007394: bd80 pop {r7, pc} + 8007396: bf00 nop + 8007398: fe00e800 .word 0xfe00e800 + +0800739c : + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + 800739c: b480 push {r7} + 800739e: b087 sub sp, #28 + 80073a0: af00 add r7, sp, #0 + 80073a2: 60f8 str r0, [r7, #12] + 80073a4: 607b str r3, [r7, #4] + 80073a6: 460b mov r3, r1 + 80073a8: 817b strh r3, [r7, #10] + 80073aa: 4613 mov r3, r2 + 80073ac: 727b strb r3, [r7, #9] + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 80073ae: 897b ldrh r3, [r7, #10] + 80073b0: f3c3 0209 ubfx r2, r3, #0, #10 + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 80073b4: 7a7b ldrb r3, [r7, #9] + 80073b6: 041b lsls r3, r3, #16 + 80073b8: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 80073bc: 431a orrs r2, r3 + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 80073be: 687b ldr r3, [r7, #4] + 80073c0: 431a orrs r2, r3 + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 80073c2: 6a3b ldr r3, [r7, #32] + 80073c4: 4313 orrs r3, r2 + 80073c6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 80073ca: 617b str r3, [r7, #20] + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + 80073cc: 68fb ldr r3, [r7, #12] + 80073ce: 681b ldr r3, [r3, #0] + 80073d0: 685a ldr r2, [r3, #4] + 80073d2: 6a3b ldr r3, [r7, #32] + 80073d4: 0d5b lsrs r3, r3, #21 + 80073d6: f403 6180 and.w r1, r3, #1024 ; 0x400 + 80073da: 4b08 ldr r3, [pc, #32] ; (80073fc ) + 80073dc: 430b orrs r3, r1 + 80073de: 43db mvns r3, r3 + 80073e0: ea02 0103 and.w r1, r2, r3 + 80073e4: 68fb ldr r3, [r7, #12] + 80073e6: 681b ldr r3, [r3, #0] + 80073e8: 697a ldr r2, [r7, #20] + 80073ea: 430a orrs r2, r1 + 80073ec: 605a str r2, [r3, #4] + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + 80073ee: bf00 nop + 80073f0: 371c adds r7, #28 + 80073f2: 46bd mov sp, r7 + 80073f4: f85d 7b04 ldr.w r7, [sp], #4 + 80073f8: 4770 bx lr + 80073fa: bf00 nop + 80073fc: 03ff63ff .word 0x03ff63ff + +08007400 : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + 8007400: b580 push {r7, lr} + 8007402: b084 sub sp, #16 + 8007404: af00 add r7, sp, #0 + 8007406: 6078 str r0, [r7, #4] + uint32_t tmp; + uint32_t tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + 8007408: 687b ldr r3, [r7, #4] + 800740a: 2b00 cmp r3, #0 + 800740c: d101 bne.n 8007412 + { + return HAL_ERROR; + 800740e: 2301 movs r3, #1 + 8007410: e0bf b.n 8007592 + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + 8007412: 687b ldr r3, [r7, #4] + 8007414: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1 + 8007418: b2db uxtb r3, r3 + 800741a: 2b00 cmp r3, #0 + 800741c: d106 bne.n 800742c + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + 800741e: 687b ldr r3, [r7, #4] + 8007420: 2200 movs r2, #0 + 8007422: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + 8007426: 6878 ldr r0, [r7, #4] + 8007428: f7fb fca6 bl 8002d78 + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + 800742c: 687b ldr r3, [r7, #4] + 800742e: 2202 movs r2, #2 + 8007430: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + 8007434: 687b ldr r3, [r7, #4] + 8007436: 681b ldr r3, [r3, #0] + 8007438: 699a ldr r2, [r3, #24] + 800743a: 687b ldr r3, [r7, #4] + 800743c: 681b ldr r3, [r3, #0] + 800743e: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000 + 8007442: 619a str r2, [r3, #24] + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8007444: 687b ldr r3, [r7, #4] + 8007446: 681b ldr r3, [r3, #0] + 8007448: 6999 ldr r1, [r3, #24] + 800744a: 687b ldr r3, [r7, #4] + 800744c: 685a ldr r2, [r3, #4] + 800744e: 687b ldr r3, [r7, #4] + 8007450: 689b ldr r3, [r3, #8] + 8007452: 431a orrs r2, r3 + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + 8007454: 687b ldr r3, [r7, #4] + 8007456: 68db ldr r3, [r3, #12] + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8007458: 431a orrs r2, r3 + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + 800745a: 687b ldr r3, [r7, #4] + 800745c: 691b ldr r3, [r3, #16] + 800745e: 431a orrs r2, r3 + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8007460: 687b ldr r3, [r7, #4] + 8007462: 681b ldr r3, [r3, #0] + 8007464: 430a orrs r2, r1 + 8007466: 619a str r2, [r3, #24] + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + 8007468: 687b ldr r3, [r7, #4] + 800746a: 681b ldr r3, [r3, #0] + 800746c: 6899 ldr r1, [r3, #8] + 800746e: 687b ldr r3, [r7, #4] + 8007470: 681a ldr r2, [r3, #0] + 8007472: 4b4a ldr r3, [pc, #296] ; (800759c ) + 8007474: 400b ands r3, r1 + 8007476: 6093 str r3, [r2, #8] + tmp = (hltdc->Init.HorizontalSync << 16U); + 8007478: 687b ldr r3, [r7, #4] + 800747a: 695b ldr r3, [r3, #20] + 800747c: 041b lsls r3, r3, #16 + 800747e: 60fb str r3, [r7, #12] + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + 8007480: 687b ldr r3, [r7, #4] + 8007482: 681b ldr r3, [r3, #0] + 8007484: 6899 ldr r1, [r3, #8] + 8007486: 687b ldr r3, [r7, #4] + 8007488: 699a ldr r2, [r3, #24] + 800748a: 68fb ldr r3, [r7, #12] + 800748c: 431a orrs r2, r3 + 800748e: 687b ldr r3, [r7, #4] + 8007490: 681b ldr r3, [r3, #0] + 8007492: 430a orrs r2, r1 + 8007494: 609a str r2, [r3, #8] + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + 8007496: 687b ldr r3, [r7, #4] + 8007498: 681b ldr r3, [r3, #0] + 800749a: 68d9 ldr r1, [r3, #12] + 800749c: 687b ldr r3, [r7, #4] + 800749e: 681a ldr r2, [r3, #0] + 80074a0: 4b3e ldr r3, [pc, #248] ; (800759c ) + 80074a2: 400b ands r3, r1 + 80074a4: 60d3 str r3, [r2, #12] + tmp = (hltdc->Init.AccumulatedHBP << 16U); + 80074a6: 687b ldr r3, [r7, #4] + 80074a8: 69db ldr r3, [r3, #28] + 80074aa: 041b lsls r3, r3, #16 + 80074ac: 60fb str r3, [r7, #12] + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + 80074ae: 687b ldr r3, [r7, #4] + 80074b0: 681b ldr r3, [r3, #0] + 80074b2: 68d9 ldr r1, [r3, #12] + 80074b4: 687b ldr r3, [r7, #4] + 80074b6: 6a1a ldr r2, [r3, #32] + 80074b8: 68fb ldr r3, [r7, #12] + 80074ba: 431a orrs r2, r3 + 80074bc: 687b ldr r3, [r7, #4] + 80074be: 681b ldr r3, [r3, #0] + 80074c0: 430a orrs r2, r1 + 80074c2: 60da str r2, [r3, #12] + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + 80074c4: 687b ldr r3, [r7, #4] + 80074c6: 681b ldr r3, [r3, #0] + 80074c8: 6919 ldr r1, [r3, #16] + 80074ca: 687b ldr r3, [r7, #4] + 80074cc: 681a ldr r2, [r3, #0] + 80074ce: 4b33 ldr r3, [pc, #204] ; (800759c ) + 80074d0: 400b ands r3, r1 + 80074d2: 6113 str r3, [r2, #16] + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + 80074d4: 687b ldr r3, [r7, #4] + 80074d6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80074d8: 041b lsls r3, r3, #16 + 80074da: 60fb str r3, [r7, #12] + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + 80074dc: 687b ldr r3, [r7, #4] + 80074de: 681b ldr r3, [r3, #0] + 80074e0: 6919 ldr r1, [r3, #16] + 80074e2: 687b ldr r3, [r7, #4] + 80074e4: 6a9a ldr r2, [r3, #40] ; 0x28 + 80074e6: 68fb ldr r3, [r7, #12] + 80074e8: 431a orrs r2, r3 + 80074ea: 687b ldr r3, [r7, #4] + 80074ec: 681b ldr r3, [r3, #0] + 80074ee: 430a orrs r2, r1 + 80074f0: 611a str r2, [r3, #16] + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + 80074f2: 687b ldr r3, [r7, #4] + 80074f4: 681b ldr r3, [r3, #0] + 80074f6: 6959 ldr r1, [r3, #20] + 80074f8: 687b ldr r3, [r7, #4] + 80074fa: 681a ldr r2, [r3, #0] + 80074fc: 4b27 ldr r3, [pc, #156] ; (800759c ) + 80074fe: 400b ands r3, r1 + 8007500: 6153 str r3, [r2, #20] + tmp = (hltdc->Init.TotalWidth << 16U); + 8007502: 687b ldr r3, [r7, #4] + 8007504: 6adb ldr r3, [r3, #44] ; 0x2c + 8007506: 041b lsls r3, r3, #16 + 8007508: 60fb str r3, [r7, #12] + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + 800750a: 687b ldr r3, [r7, #4] + 800750c: 681b ldr r3, [r3, #0] + 800750e: 6959 ldr r1, [r3, #20] + 8007510: 687b ldr r3, [r7, #4] + 8007512: 6b1a ldr r2, [r3, #48] ; 0x30 + 8007514: 68fb ldr r3, [r7, #12] + 8007516: 431a orrs r2, r3 + 8007518: 687b ldr r3, [r7, #4] + 800751a: 681b ldr r3, [r3, #0] + 800751c: 430a orrs r2, r1 + 800751e: 615a str r2, [r3, #20] + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + 8007520: 687b ldr r3, [r7, #4] + 8007522: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8007526: 021b lsls r3, r3, #8 + 8007528: 60fb str r3, [r7, #12] + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + 800752a: 687b ldr r3, [r7, #4] + 800752c: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8007530: 041b lsls r3, r3, #16 + 8007532: 60bb str r3, [r7, #8] + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + 8007534: 687b ldr r3, [r7, #4] + 8007536: 681b ldr r3, [r3, #0] + 8007538: 6ada ldr r2, [r3, #44] ; 0x2c + 800753a: 687b ldr r3, [r7, #4] + 800753c: 681b ldr r3, [r3, #0] + 800753e: f002 427f and.w r2, r2, #4278190080 ; 0xff000000 + 8007542: 62da str r2, [r3, #44] ; 0x2c + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + 8007544: 687b ldr r3, [r7, #4] + 8007546: 681b ldr r3, [r3, #0] + 8007548: 6ad9 ldr r1, [r3, #44] ; 0x2c + 800754a: 68ba ldr r2, [r7, #8] + 800754c: 68fb ldr r3, [r7, #12] + 800754e: 4313 orrs r3, r2 + 8007550: 687a ldr r2, [r7, #4] + 8007552: f892 2034 ldrb.w r2, [r2, #52] ; 0x34 + 8007556: 431a orrs r2, r3 + 8007558: 687b ldr r3, [r7, #4] + 800755a: 681b ldr r3, [r3, #0] + 800755c: 430a orrs r2, r1 + 800755e: 62da str r2, [r3, #44] ; 0x2c + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + 8007560: 687b ldr r3, [r7, #4] + 8007562: 681b ldr r3, [r3, #0] + 8007564: 6b5a ldr r2, [r3, #52] ; 0x34 + 8007566: 687b ldr r3, [r7, #4] + 8007568: 681b ldr r3, [r3, #0] + 800756a: f042 0206 orr.w r2, r2, #6 + 800756e: 635a str r2, [r3, #52] ; 0x34 + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + 8007570: 687b ldr r3, [r7, #4] + 8007572: 681b ldr r3, [r3, #0] + 8007574: 699a ldr r2, [r3, #24] + 8007576: 687b ldr r3, [r7, #4] + 8007578: 681b ldr r3, [r3, #0] + 800757a: f042 0201 orr.w r2, r2, #1 + 800757e: 619a str r2, [r3, #24] + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + 8007580: 687b ldr r3, [r7, #4] + 8007582: 2200 movs r2, #0 + 8007584: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + 8007588: 687b ldr r3, [r7, #4] + 800758a: 2201 movs r2, #1 + 800758c: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + return HAL_OK; + 8007590: 2300 movs r3, #0 +} + 8007592: 4618 mov r0, r3 + 8007594: 3710 adds r7, #16 + 8007596: 46bd mov sp, r7 + 8007598: bd80 pop {r7, pc} + 800759a: bf00 nop + 800759c: f000f800 .word 0xf000f800 + +080075a0 : + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + 80075a0: b5b0 push {r4, r5, r7, lr} + 80075a2: b084 sub sp, #16 + 80075a4: af00 add r7, sp, #0 + 80075a6: 60f8 str r0, [r7, #12] + 80075a8: 60b9 str r1, [r7, #8] + 80075aa: 607a str r2, [r7, #4] + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + 80075ac: 68fb ldr r3, [r7, #12] + 80075ae: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0 + 80075b2: 2b01 cmp r3, #1 + 80075b4: d101 bne.n 80075ba + 80075b6: 2302 movs r3, #2 + 80075b8: e02c b.n 8007614 + 80075ba: 68fb ldr r3, [r7, #12] + 80075bc: 2201 movs r2, #1 + 80075be: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + 80075c2: 68fb ldr r3, [r7, #12] + 80075c4: 2202 movs r2, #2 + 80075c6: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + 80075ca: 68fa ldr r2, [r7, #12] + 80075cc: 687b ldr r3, [r7, #4] + 80075ce: 2134 movs r1, #52 ; 0x34 + 80075d0: fb01 f303 mul.w r3, r1, r3 + 80075d4: 4413 add r3, r2 + 80075d6: f103 0238 add.w r2, r3, #56 ; 0x38 + 80075da: 68bb ldr r3, [r7, #8] + 80075dc: 4614 mov r4, r2 + 80075de: 461d mov r5, r3 + 80075e0: cd0f ldmia r5!, {r0, r1, r2, r3} + 80075e2: c40f stmia r4!, {r0, r1, r2, r3} + 80075e4: cd0f ldmia r5!, {r0, r1, r2, r3} + 80075e6: c40f stmia r4!, {r0, r1, r2, r3} + 80075e8: cd0f ldmia r5!, {r0, r1, r2, r3} + 80075ea: c40f stmia r4!, {r0, r1, r2, r3} + 80075ec: 682b ldr r3, [r5, #0] + 80075ee: 6023 str r3, [r4, #0] + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + 80075f0: 687a ldr r2, [r7, #4] + 80075f2: 68b9 ldr r1, [r7, #8] + 80075f4: 68f8 ldr r0, [r7, #12] + 80075f6: f000 f81f bl 8007638 + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + 80075fa: 68fb ldr r3, [r7, #12] + 80075fc: 681b ldr r3, [r3, #0] + 80075fe: 2201 movs r2, #1 + 8007600: 625a str r2, [r3, #36] ; 0x24 + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + 8007602: 68fb ldr r3, [r7, #12] + 8007604: 2201 movs r2, #1 + 8007606: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 800760a: 68fb ldr r3, [r7, #12] + 800760c: 2200 movs r2, #0 + 800760e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + + return HAL_OK; + 8007612: 2300 movs r3, #0 +} + 8007614: 4618 mov r0, r3 + 8007616: 3710 adds r7, #16 + 8007618: 46bd mov sp, r7 + 800761a: bdb0 pop {r4, r5, r7, pc} + +0800761c : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + 800761c: b480 push {r7} + 800761e: b083 sub sp, #12 + 8007620: af00 add r7, sp, #0 + 8007622: 6078 str r0, [r7, #4] + return hltdc->State; + 8007624: 687b ldr r3, [r7, #4] + 8007626: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1 + 800762a: b2db uxtb r3, r3 +} + 800762c: 4618 mov r0, r3 + 800762e: 370c adds r7, #12 + 8007630: 46bd mov sp, r7 + 8007632: f85d 7b04 ldr.w r7, [sp], #4 + 8007636: 4770 bx lr + +08007638 : + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + 8007638: b480 push {r7} + 800763a: b089 sub sp, #36 ; 0x24 + 800763c: af00 add r7, sp, #0 + 800763e: 60f8 str r0, [r7, #12] + 8007640: 60b9 str r1, [r7, #8] + 8007642: 607a str r2, [r7, #4] + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + 8007644: 68bb ldr r3, [r7, #8] + 8007646: 685a ldr r2, [r3, #4] + 8007648: 68fb ldr r3, [r7, #12] + 800764a: 681b ldr r3, [r3, #0] + 800764c: 68db ldr r3, [r3, #12] + 800764e: 0c1b lsrs r3, r3, #16 + 8007650: f3c3 030b ubfx r3, r3, #0, #12 + 8007654: 4413 add r3, r2 + 8007656: 041b lsls r3, r3, #16 + 8007658: 61fb str r3, [r7, #28] + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + 800765a: 68fb ldr r3, [r7, #12] + 800765c: 681b ldr r3, [r3, #0] + 800765e: 461a mov r2, r3 + 8007660: 687b ldr r3, [r7, #4] + 8007662: 01db lsls r3, r3, #7 + 8007664: 4413 add r3, r2 + 8007666: 3384 adds r3, #132 ; 0x84 + 8007668: 685b ldr r3, [r3, #4] + 800766a: 68fa ldr r2, [r7, #12] + 800766c: 6812 ldr r2, [r2, #0] + 800766e: 4611 mov r1, r2 + 8007670: 687a ldr r2, [r7, #4] + 8007672: 01d2 lsls r2, r2, #7 + 8007674: 440a add r2, r1 + 8007676: 3284 adds r2, #132 ; 0x84 + 8007678: f403 4370 and.w r3, r3, #61440 ; 0xf000 + 800767c: 6053 str r3, [r2, #4] + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + 800767e: 68bb ldr r3, [r7, #8] + 8007680: 681a ldr r2, [r3, #0] + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + 8007682: 68fb ldr r3, [r7, #12] + 8007684: 681b ldr r3, [r3, #0] + 8007686: 68db ldr r3, [r3, #12] + 8007688: 0c1b lsrs r3, r3, #16 + 800768a: f3c3 030b ubfx r3, r3, #0, #12 + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + 800768e: 4413 add r3, r2 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + 8007690: 1c5a adds r2, r3, #1 + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + 8007692: 68fb ldr r3, [r7, #12] + 8007694: 681b ldr r3, [r3, #0] + 8007696: 4619 mov r1, r3 + 8007698: 687b ldr r3, [r7, #4] + 800769a: 01db lsls r3, r3, #7 + 800769c: 440b add r3, r1 + 800769e: 3384 adds r3, #132 ; 0x84 + 80076a0: 4619 mov r1, r3 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + 80076a2: 69fb ldr r3, [r7, #28] + 80076a4: 4313 orrs r3, r2 + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + 80076a6: 604b str r3, [r1, #4] + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + 80076a8: 68bb ldr r3, [r7, #8] + 80076aa: 68da ldr r2, [r3, #12] + 80076ac: 68fb ldr r3, [r7, #12] + 80076ae: 681b ldr r3, [r3, #0] + 80076b0: 68db ldr r3, [r3, #12] + 80076b2: f3c3 030a ubfx r3, r3, #0, #11 + 80076b6: 4413 add r3, r2 + 80076b8: 041b lsls r3, r3, #16 + 80076ba: 61fb str r3, [r7, #28] + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + 80076bc: 68fb ldr r3, [r7, #12] + 80076be: 681b ldr r3, [r3, #0] + 80076c0: 461a mov r2, r3 + 80076c2: 687b ldr r3, [r7, #4] + 80076c4: 01db lsls r3, r3, #7 + 80076c6: 4413 add r3, r2 + 80076c8: 3384 adds r3, #132 ; 0x84 + 80076ca: 689b ldr r3, [r3, #8] + 80076cc: 68fa ldr r2, [r7, #12] + 80076ce: 6812 ldr r2, [r2, #0] + 80076d0: 4611 mov r1, r2 + 80076d2: 687a ldr r2, [r7, #4] + 80076d4: 01d2 lsls r2, r2, #7 + 80076d6: 440a add r2, r1 + 80076d8: 3284 adds r2, #132 ; 0x84 + 80076da: f403 4370 and.w r3, r3, #61440 ; 0xf000 + 80076de: 6093 str r3, [r2, #8] + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + 80076e0: 68bb ldr r3, [r7, #8] + 80076e2: 689a ldr r2, [r3, #8] + 80076e4: 68fb ldr r3, [r7, #12] + 80076e6: 681b ldr r3, [r3, #0] + 80076e8: 68db ldr r3, [r3, #12] + 80076ea: f3c3 030a ubfx r3, r3, #0, #11 + 80076ee: 4413 add r3, r2 + 80076f0: 1c5a adds r2, r3, #1 + 80076f2: 68fb ldr r3, [r7, #12] + 80076f4: 681b ldr r3, [r3, #0] + 80076f6: 4619 mov r1, r3 + 80076f8: 687b ldr r3, [r7, #4] + 80076fa: 01db lsls r3, r3, #7 + 80076fc: 440b add r3, r1 + 80076fe: 3384 adds r3, #132 ; 0x84 + 8007700: 4619 mov r1, r3 + 8007702: 69fb ldr r3, [r7, #28] + 8007704: 4313 orrs r3, r2 + 8007706: 608b str r3, [r1, #8] + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + 8007708: 68fb ldr r3, [r7, #12] + 800770a: 681b ldr r3, [r3, #0] + 800770c: 461a mov r2, r3 + 800770e: 687b ldr r3, [r7, #4] + 8007710: 01db lsls r3, r3, #7 + 8007712: 4413 add r3, r2 + 8007714: 3384 adds r3, #132 ; 0x84 + 8007716: 691b ldr r3, [r3, #16] + 8007718: 68fa ldr r2, [r7, #12] + 800771a: 6812 ldr r2, [r2, #0] + 800771c: 4611 mov r1, r2 + 800771e: 687a ldr r2, [r7, #4] + 8007720: 01d2 lsls r2, r2, #7 + 8007722: 440a add r2, r1 + 8007724: 3284 adds r2, #132 ; 0x84 + 8007726: f023 0307 bic.w r3, r3, #7 + 800772a: 6113 str r3, [r2, #16] + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + 800772c: 68fb ldr r3, [r7, #12] + 800772e: 681b ldr r3, [r3, #0] + 8007730: 461a mov r2, r3 + 8007732: 687b ldr r3, [r7, #4] + 8007734: 01db lsls r3, r3, #7 + 8007736: 4413 add r3, r2 + 8007738: 3384 adds r3, #132 ; 0x84 + 800773a: 461a mov r2, r3 + 800773c: 68bb ldr r3, [r7, #8] + 800773e: 691b ldr r3, [r3, #16] + 8007740: 6113 str r3, [r2, #16] + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + 8007742: 68bb ldr r3, [r7, #8] + 8007744: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8007748: 021b lsls r3, r3, #8 + 800774a: 61fb str r3, [r7, #28] + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + 800774c: 68bb ldr r3, [r7, #8] + 800774e: f893 3032 ldrb.w r3, [r3, #50] ; 0x32 + 8007752: 041b lsls r3, r3, #16 + 8007754: 61bb str r3, [r7, #24] + tmp2 = (pLayerCfg->Alpha0 << 24U); + 8007756: 68bb ldr r3, [r7, #8] + 8007758: 699b ldr r3, [r3, #24] + 800775a: 061b lsls r3, r3, #24 + 800775c: 617b str r3, [r7, #20] + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + 800775e: 68fb ldr r3, [r7, #12] + 8007760: 681b ldr r3, [r3, #0] + 8007762: 461a mov r2, r3 + 8007764: 687b ldr r3, [r7, #4] + 8007766: 01db lsls r3, r3, #7 + 8007768: 4413 add r3, r2 + 800776a: 3384 adds r3, #132 ; 0x84 + 800776c: 699b ldr r3, [r3, #24] + 800776e: 68fb ldr r3, [r7, #12] + 8007770: 681b ldr r3, [r3, #0] + 8007772: 461a mov r2, r3 + 8007774: 687b ldr r3, [r7, #4] + 8007776: 01db lsls r3, r3, #7 + 8007778: 4413 add r3, r2 + 800777a: 3384 adds r3, #132 ; 0x84 + 800777c: 461a mov r2, r3 + 800777e: 2300 movs r3, #0 + 8007780: 6193 str r3, [r2, #24] + LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + 8007782: 68bb ldr r3, [r7, #8] + 8007784: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8007788: 461a mov r2, r3 + 800778a: 69fb ldr r3, [r7, #28] + 800778c: 431a orrs r2, r3 + 800778e: 69bb ldr r3, [r7, #24] + 8007790: 431a orrs r2, r3 + 8007792: 68fb ldr r3, [r7, #12] + 8007794: 681b ldr r3, [r3, #0] + 8007796: 4619 mov r1, r3 + 8007798: 687b ldr r3, [r7, #4] + 800779a: 01db lsls r3, r3, #7 + 800779c: 440b add r3, r1 + 800779e: 3384 adds r3, #132 ; 0x84 + 80077a0: 4619 mov r1, r3 + 80077a2: 697b ldr r3, [r7, #20] + 80077a4: 4313 orrs r3, r2 + 80077a6: 618b str r3, [r1, #24] + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + 80077a8: 68fb ldr r3, [r7, #12] + 80077aa: 681b ldr r3, [r3, #0] + 80077ac: 461a mov r2, r3 + 80077ae: 687b ldr r3, [r7, #4] + 80077b0: 01db lsls r3, r3, #7 + 80077b2: 4413 add r3, r2 + 80077b4: 3384 adds r3, #132 ; 0x84 + 80077b6: 695b ldr r3, [r3, #20] + 80077b8: 68fa ldr r2, [r7, #12] + 80077ba: 6812 ldr r2, [r2, #0] + 80077bc: 4611 mov r1, r2 + 80077be: 687a ldr r2, [r7, #4] + 80077c0: 01d2 lsls r2, r2, #7 + 80077c2: 440a add r2, r1 + 80077c4: 3284 adds r2, #132 ; 0x84 + 80077c6: f023 03ff bic.w r3, r3, #255 ; 0xff + 80077ca: 6153 str r3, [r2, #20] + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + 80077cc: 68fb ldr r3, [r7, #12] + 80077ce: 681b ldr r3, [r3, #0] + 80077d0: 461a mov r2, r3 + 80077d2: 687b ldr r3, [r7, #4] + 80077d4: 01db lsls r3, r3, #7 + 80077d6: 4413 add r3, r2 + 80077d8: 3384 adds r3, #132 ; 0x84 + 80077da: 461a mov r2, r3 + 80077dc: 68bb ldr r3, [r7, #8] + 80077de: 695b ldr r3, [r3, #20] + 80077e0: 6153 str r3, [r2, #20] + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + 80077e2: 68fb ldr r3, [r7, #12] + 80077e4: 681b ldr r3, [r3, #0] + 80077e6: 461a mov r2, r3 + 80077e8: 687b ldr r3, [r7, #4] + 80077ea: 01db lsls r3, r3, #7 + 80077ec: 4413 add r3, r2 + 80077ee: 3384 adds r3, #132 ; 0x84 + 80077f0: 69da ldr r2, [r3, #28] + 80077f2: 68fb ldr r3, [r7, #12] + 80077f4: 681b ldr r3, [r3, #0] + 80077f6: 4619 mov r1, r3 + 80077f8: 687b ldr r3, [r7, #4] + 80077fa: 01db lsls r3, r3, #7 + 80077fc: 440b add r3, r1 + 80077fe: 3384 adds r3, #132 ; 0x84 + 8007800: 4619 mov r1, r3 + 8007802: 4b58 ldr r3, [pc, #352] ; (8007964 ) + 8007804: 4013 ands r3, r2 + 8007806: 61cb str r3, [r1, #28] + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + 8007808: 68bb ldr r3, [r7, #8] + 800780a: 69da ldr r2, [r3, #28] + 800780c: 68bb ldr r3, [r7, #8] + 800780e: 6a1b ldr r3, [r3, #32] + 8007810: 68f9 ldr r1, [r7, #12] + 8007812: 6809 ldr r1, [r1, #0] + 8007814: 4608 mov r0, r1 + 8007816: 6879 ldr r1, [r7, #4] + 8007818: 01c9 lsls r1, r1, #7 + 800781a: 4401 add r1, r0 + 800781c: 3184 adds r1, #132 ; 0x84 + 800781e: 4313 orrs r3, r2 + 8007820: 61cb str r3, [r1, #28] + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + 8007822: 68fb ldr r3, [r7, #12] + 8007824: 681b ldr r3, [r3, #0] + 8007826: 461a mov r2, r3 + 8007828: 687b ldr r3, [r7, #4] + 800782a: 01db lsls r3, r3, #7 + 800782c: 4413 add r3, r2 + 800782e: 3384 adds r3, #132 ; 0x84 + 8007830: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007832: 68fb ldr r3, [r7, #12] + 8007834: 681b ldr r3, [r3, #0] + 8007836: 461a mov r2, r3 + 8007838: 687b ldr r3, [r7, #4] + 800783a: 01db lsls r3, r3, #7 + 800783c: 4413 add r3, r2 + 800783e: 3384 adds r3, #132 ; 0x84 + 8007840: 461a mov r2, r3 + 8007842: 2300 movs r3, #0 + 8007844: 6293 str r3, [r2, #40] ; 0x28 + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + 8007846: 68fb ldr r3, [r7, #12] + 8007848: 681b ldr r3, [r3, #0] + 800784a: 461a mov r2, r3 + 800784c: 687b ldr r3, [r7, #4] + 800784e: 01db lsls r3, r3, #7 + 8007850: 4413 add r3, r2 + 8007852: 3384 adds r3, #132 ; 0x84 + 8007854: 461a mov r2, r3 + 8007856: 68bb ldr r3, [r7, #8] + 8007858: 6a5b ldr r3, [r3, #36] ; 0x24 + 800785a: 6293 str r3, [r2, #40] ; 0x28 + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + 800785c: 68bb ldr r3, [r7, #8] + 800785e: 691b ldr r3, [r3, #16] + 8007860: 2b00 cmp r3, #0 + 8007862: d102 bne.n 800786a + { + tmp = 4U; + 8007864: 2304 movs r3, #4 + 8007866: 61fb str r3, [r7, #28] + 8007868: e01b b.n 80078a2 + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + 800786a: 68bb ldr r3, [r7, #8] + 800786c: 691b ldr r3, [r3, #16] + 800786e: 2b01 cmp r3, #1 + 8007870: d102 bne.n 8007878 + { + tmp = 3U; + 8007872: 2303 movs r3, #3 + 8007874: 61fb str r3, [r7, #28] + 8007876: e014 b.n 80078a2 + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + 8007878: 68bb ldr r3, [r7, #8] + 800787a: 691b ldr r3, [r3, #16] + 800787c: 2b04 cmp r3, #4 + 800787e: d00b beq.n 8007898 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + 8007880: 68bb ldr r3, [r7, #8] + 8007882: 691b ldr r3, [r3, #16] + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + 8007884: 2b02 cmp r3, #2 + 8007886: d007 beq.n 8007898 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + 8007888: 68bb ldr r3, [r7, #8] + 800788a: 691b ldr r3, [r3, #16] + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + 800788c: 2b03 cmp r3, #3 + 800788e: d003 beq.n 8007898 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + 8007890: 68bb ldr r3, [r7, #8] + 8007892: 691b ldr r3, [r3, #16] + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + 8007894: 2b07 cmp r3, #7 + 8007896: d102 bne.n 800789e + { + tmp = 2U; + 8007898: 2302 movs r3, #2 + 800789a: 61fb str r3, [r7, #28] + 800789c: e001 b.n 80078a2 + } + else + { + tmp = 1U; + 800789e: 2301 movs r3, #1 + 80078a0: 61fb str r3, [r7, #28] + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + 80078a2: 68fb ldr r3, [r7, #12] + 80078a4: 681b ldr r3, [r3, #0] + 80078a6: 461a mov r2, r3 + 80078a8: 687b ldr r3, [r7, #4] + 80078aa: 01db lsls r3, r3, #7 + 80078ac: 4413 add r3, r2 + 80078ae: 3384 adds r3, #132 ; 0x84 + 80078b0: 6adb ldr r3, [r3, #44] ; 0x2c + 80078b2: 68fa ldr r2, [r7, #12] + 80078b4: 6812 ldr r2, [r2, #0] + 80078b6: 4611 mov r1, r2 + 80078b8: 687a ldr r2, [r7, #4] + 80078ba: 01d2 lsls r2, r2, #7 + 80078bc: 440a add r2, r1 + 80078be: 3284 adds r2, #132 ; 0x84 + 80078c0: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000 + 80078c4: 62d3 str r3, [r2, #44] ; 0x2c + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ + 80078c6: 68bb ldr r3, [r7, #8] + 80078c8: 6a9b ldr r3, [r3, #40] ; 0x28 + 80078ca: 69fa ldr r2, [r7, #28] + 80078cc: fb02 f303 mul.w r3, r2, r3 + 80078d0: 041a lsls r2, r3, #16 + (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + 80078d2: 68bb ldr r3, [r7, #8] + 80078d4: 6859 ldr r1, [r3, #4] + 80078d6: 68bb ldr r3, [r7, #8] + 80078d8: 681b ldr r3, [r3, #0] + 80078da: 1acb subs r3, r1, r3 + 80078dc: 69f9 ldr r1, [r7, #28] + 80078de: fb01 f303 mul.w r3, r1, r3 + 80078e2: 3303 adds r3, #3 + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ + 80078e4: 68f9 ldr r1, [r7, #12] + 80078e6: 6809 ldr r1, [r1, #0] + 80078e8: 4608 mov r0, r1 + 80078ea: 6879 ldr r1, [r7, #4] + 80078ec: 01c9 lsls r1, r1, #7 + 80078ee: 4401 add r1, r0 + 80078f0: 3184 adds r1, #132 ; 0x84 + 80078f2: 4313 orrs r3, r2 + 80078f4: 62cb str r3, [r1, #44] ; 0x2c + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + 80078f6: 68fb ldr r3, [r7, #12] + 80078f8: 681b ldr r3, [r3, #0] + 80078fa: 461a mov r2, r3 + 80078fc: 687b ldr r3, [r7, #4] + 80078fe: 01db lsls r3, r3, #7 + 8007900: 4413 add r3, r2 + 8007902: 3384 adds r3, #132 ; 0x84 + 8007904: 6b1a ldr r2, [r3, #48] ; 0x30 + 8007906: 68fb ldr r3, [r7, #12] + 8007908: 681b ldr r3, [r3, #0] + 800790a: 4619 mov r1, r3 + 800790c: 687b ldr r3, [r7, #4] + 800790e: 01db lsls r3, r3, #7 + 8007910: 440b add r3, r1 + 8007912: 3384 adds r3, #132 ; 0x84 + 8007914: 4619 mov r1, r3 + 8007916: 4b14 ldr r3, [pc, #80] ; (8007968 ) + 8007918: 4013 ands r3, r2 + 800791a: 630b str r3, [r1, #48] ; 0x30 + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + 800791c: 68fb ldr r3, [r7, #12] + 800791e: 681b ldr r3, [r3, #0] + 8007920: 461a mov r2, r3 + 8007922: 687b ldr r3, [r7, #4] + 8007924: 01db lsls r3, r3, #7 + 8007926: 4413 add r3, r2 + 8007928: 3384 adds r3, #132 ; 0x84 + 800792a: 461a mov r2, r3 + 800792c: 68bb ldr r3, [r7, #8] + 800792e: 6adb ldr r3, [r3, #44] ; 0x2c + 8007930: 6313 str r3, [r2, #48] ; 0x30 + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; + 8007932: 68fb ldr r3, [r7, #12] + 8007934: 681b ldr r3, [r3, #0] + 8007936: 461a mov r2, r3 + 8007938: 687b ldr r3, [r7, #4] + 800793a: 01db lsls r3, r3, #7 + 800793c: 4413 add r3, r2 + 800793e: 3384 adds r3, #132 ; 0x84 + 8007940: 681b ldr r3, [r3, #0] + 8007942: 68fa ldr r2, [r7, #12] + 8007944: 6812 ldr r2, [r2, #0] + 8007946: 4611 mov r1, r2 + 8007948: 687a ldr r2, [r7, #4] + 800794a: 01d2 lsls r2, r2, #7 + 800794c: 440a add r2, r1 + 800794e: 3284 adds r2, #132 ; 0x84 + 8007950: f043 0301 orr.w r3, r3, #1 + 8007954: 6013 str r3, [r2, #0] +} + 8007956: bf00 nop + 8007958: 3724 adds r7, #36 ; 0x24 + 800795a: 46bd mov sp, r7 + 800795c: f85d 7b04 ldr.w r7, [sp], #4 + 8007960: 4770 bx lr + 8007962: bf00 nop + 8007964: fffff8f8 .word 0xfffff8f8 + 8007968: fffff800 .word 0xfffff800 + +0800796c : + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 800796c: b480 push {r7} + 800796e: af00 add r7, sp, #0 + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8007970: 4b05 ldr r3, [pc, #20] ; (8007988 ) + 8007972: 681b ldr r3, [r3, #0] + 8007974: 4a04 ldr r2, [pc, #16] ; (8007988 ) + 8007976: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800797a: 6013 str r3, [r2, #0] +} + 800797c: bf00 nop + 800797e: 46bd mov sp, r7 + 8007980: f85d 7b04 ldr.w r7, [sp], #4 + 8007984: 4770 bx lr + 8007986: bf00 nop + 8007988: 40007000 .word 0x40007000 + +0800798c : + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + 800798c: b580 push {r7, lr} + 800798e: b082 sub sp, #8 + 8007990: af00 add r7, sp, #0 + uint32_t tickstart = 0; + 8007992: 2300 movs r3, #0 + 8007994: 607b str r3, [r7, #4] + + __HAL_RCC_PWR_CLK_ENABLE(); + 8007996: 4b23 ldr r3, [pc, #140] ; (8007a24 ) + 8007998: 6c1b ldr r3, [r3, #64] ; 0x40 + 800799a: 4a22 ldr r2, [pc, #136] ; (8007a24 ) + 800799c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80079a0: 6413 str r3, [r2, #64] ; 0x40 + 80079a2: 4b20 ldr r3, [pc, #128] ; (8007a24 ) + 80079a4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80079a6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80079aa: 603b str r3, [r7, #0] + 80079ac: 683b ldr r3, [r7, #0] + + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + 80079ae: 4b1e ldr r3, [pc, #120] ; (8007a28 ) + 80079b0: 681b ldr r3, [r3, #0] + 80079b2: 4a1d ldr r2, [pc, #116] ; (8007a28 ) + 80079b4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80079b8: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80079ba: f7fc ff5b bl 8004874 + 80079be: 6078 str r0, [r7, #4] + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 80079c0: e009 b.n 80079d6 + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 80079c2: f7fc ff57 bl 8004874 + 80079c6: 4602 mov r2, r0 + 80079c8: 687b ldr r3, [r7, #4] + 80079ca: 1ad3 subs r3, r2, r3 + 80079cc: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 80079d0: d901 bls.n 80079d6 + { + return HAL_TIMEOUT; + 80079d2: 2303 movs r3, #3 + 80079d4: e022 b.n 8007a1c + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 80079d6: 4b14 ldr r3, [pc, #80] ; (8007a28 ) + 80079d8: 685b ldr r3, [r3, #4] + 80079da: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80079de: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80079e2: d1ee bne.n 80079c2 + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + 80079e4: 4b10 ldr r3, [pc, #64] ; (8007a28 ) + 80079e6: 681b ldr r3, [r3, #0] + 80079e8: 4a0f ldr r2, [pc, #60] ; (8007a28 ) + 80079ea: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 80079ee: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80079f0: f7fc ff40 bl 8004874 + 80079f4: 6078 str r0, [r7, #4] + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 80079f6: e009 b.n 8007a0c + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 80079f8: f7fc ff3c bl 8004874 + 80079fc: 4602 mov r2, r0 + 80079fe: 687b ldr r3, [r7, #4] + 8007a00: 1ad3 subs r3, r2, r3 + 8007a02: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8007a06: d901 bls.n 8007a0c + { + return HAL_TIMEOUT; + 8007a08: 2303 movs r3, #3 + 8007a0a: e007 b.n 8007a1c + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 8007a0c: 4b06 ldr r3, [pc, #24] ; (8007a28 ) + 8007a0e: 685b ldr r3, [r3, #4] + 8007a10: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007a14: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 8007a18: d1ee bne.n 80079f8 + } + } + return HAL_OK; + 8007a1a: 2300 movs r3, #0 +} + 8007a1c: 4618 mov r0, r3 + 8007a1e: 3708 adds r7, #8 + 8007a20: 46bd mov sp, r7 + 8007a22: bd80 pop {r7, pc} + 8007a24: 40023800 .word 0x40023800 + 8007a28: 40007000 .word 0x40007000 + +08007a2c : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8007a2c: b580 push {r7, lr} + 8007a2e: b086 sub sp, #24 + 8007a30: af00 add r7, sp, #0 + 8007a32: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + FlagStatus pwrclkchanged = RESET; + 8007a34: 2300 movs r3, #0 + 8007a36: 75fb strb r3, [r7, #23] + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8007a38: 687b ldr r3, [r7, #4] + 8007a3a: 2b00 cmp r3, #0 + 8007a3c: d101 bne.n 8007a42 + { + return HAL_ERROR; + 8007a3e: 2301 movs r3, #1 + 8007a40: e291 b.n 8007f66 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8007a42: 687b ldr r3, [r7, #4] + 8007a44: 681b ldr r3, [r3, #0] + 8007a46: f003 0301 and.w r3, r3, #1 + 8007a4a: 2b00 cmp r3, #0 + 8007a4c: f000 8087 beq.w 8007b5e + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8007a50: 4b96 ldr r3, [pc, #600] ; (8007cac ) + 8007a52: 689b ldr r3, [r3, #8] + 8007a54: f003 030c and.w r3, r3, #12 + 8007a58: 2b04 cmp r3, #4 + 8007a5a: d00c beq.n 8007a76 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8007a5c: 4b93 ldr r3, [pc, #588] ; (8007cac ) + 8007a5e: 689b ldr r3, [r3, #8] + 8007a60: f003 030c and.w r3, r3, #12 + 8007a64: 2b08 cmp r3, #8 + 8007a66: d112 bne.n 8007a8e + 8007a68: 4b90 ldr r3, [pc, #576] ; (8007cac ) + 8007a6a: 685b ldr r3, [r3, #4] + 8007a6c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8007a70: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8007a74: d10b bne.n 8007a8e + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8007a76: 4b8d ldr r3, [pc, #564] ; (8007cac ) + 8007a78: 681b ldr r3, [r3, #0] + 8007a7a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007a7e: 2b00 cmp r3, #0 + 8007a80: d06c beq.n 8007b5c + 8007a82: 687b ldr r3, [r7, #4] + 8007a84: 685b ldr r3, [r3, #4] + 8007a86: 2b00 cmp r3, #0 + 8007a88: d168 bne.n 8007b5c + { + return HAL_ERROR; + 8007a8a: 2301 movs r3, #1 + 8007a8c: e26b b.n 8007f66 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8007a8e: 687b ldr r3, [r7, #4] + 8007a90: 685b ldr r3, [r3, #4] + 8007a92: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8007a96: d106 bne.n 8007aa6 + 8007a98: 4b84 ldr r3, [pc, #528] ; (8007cac ) + 8007a9a: 681b ldr r3, [r3, #0] + 8007a9c: 4a83 ldr r2, [pc, #524] ; (8007cac ) + 8007a9e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007aa2: 6013 str r3, [r2, #0] + 8007aa4: e02e b.n 8007b04 + 8007aa6: 687b ldr r3, [r7, #4] + 8007aa8: 685b ldr r3, [r3, #4] + 8007aaa: 2b00 cmp r3, #0 + 8007aac: d10c bne.n 8007ac8 + 8007aae: 4b7f ldr r3, [pc, #508] ; (8007cac ) + 8007ab0: 681b ldr r3, [r3, #0] + 8007ab2: 4a7e ldr r2, [pc, #504] ; (8007cac ) + 8007ab4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007ab8: 6013 str r3, [r2, #0] + 8007aba: 4b7c ldr r3, [pc, #496] ; (8007cac ) + 8007abc: 681b ldr r3, [r3, #0] + 8007abe: 4a7b ldr r2, [pc, #492] ; (8007cac ) + 8007ac0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8007ac4: 6013 str r3, [r2, #0] + 8007ac6: e01d b.n 8007b04 + 8007ac8: 687b ldr r3, [r7, #4] + 8007aca: 685b ldr r3, [r3, #4] + 8007acc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8007ad0: d10c bne.n 8007aec + 8007ad2: 4b76 ldr r3, [pc, #472] ; (8007cac ) + 8007ad4: 681b ldr r3, [r3, #0] + 8007ad6: 4a75 ldr r2, [pc, #468] ; (8007cac ) + 8007ad8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8007adc: 6013 str r3, [r2, #0] + 8007ade: 4b73 ldr r3, [pc, #460] ; (8007cac ) + 8007ae0: 681b ldr r3, [r3, #0] + 8007ae2: 4a72 ldr r2, [pc, #456] ; (8007cac ) + 8007ae4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007ae8: 6013 str r3, [r2, #0] + 8007aea: e00b b.n 8007b04 + 8007aec: 4b6f ldr r3, [pc, #444] ; (8007cac ) + 8007aee: 681b ldr r3, [r3, #0] + 8007af0: 4a6e ldr r2, [pc, #440] ; (8007cac ) + 8007af2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007af6: 6013 str r3, [r2, #0] + 8007af8: 4b6c ldr r3, [pc, #432] ; (8007cac ) + 8007afa: 681b ldr r3, [r3, #0] + 8007afc: 4a6b ldr r2, [pc, #428] ; (8007cac ) + 8007afe: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8007b02: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8007b04: 687b ldr r3, [r7, #4] + 8007b06: 685b ldr r3, [r3, #4] + 8007b08: 2b00 cmp r3, #0 + 8007b0a: d013 beq.n 8007b34 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007b0c: f7fc feb2 bl 8004874 + 8007b10: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8007b12: e008 b.n 8007b26 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8007b14: f7fc feae bl 8004874 + 8007b18: 4602 mov r2, r0 + 8007b1a: 693b ldr r3, [r7, #16] + 8007b1c: 1ad3 subs r3, r2, r3 + 8007b1e: 2b64 cmp r3, #100 ; 0x64 + 8007b20: d901 bls.n 8007b26 + { + return HAL_TIMEOUT; + 8007b22: 2303 movs r3, #3 + 8007b24: e21f b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8007b26: 4b61 ldr r3, [pc, #388] ; (8007cac ) + 8007b28: 681b ldr r3, [r3, #0] + 8007b2a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007b2e: 2b00 cmp r3, #0 + 8007b30: d0f0 beq.n 8007b14 + 8007b32: e014 b.n 8007b5e + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007b34: f7fc fe9e bl 8004874 + 8007b38: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8007b3a: e008 b.n 8007b4e + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8007b3c: f7fc fe9a bl 8004874 + 8007b40: 4602 mov r2, r0 + 8007b42: 693b ldr r3, [r7, #16] + 8007b44: 1ad3 subs r3, r2, r3 + 8007b46: 2b64 cmp r3, #100 ; 0x64 + 8007b48: d901 bls.n 8007b4e + { + return HAL_TIMEOUT; + 8007b4a: 2303 movs r3, #3 + 8007b4c: e20b b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8007b4e: 4b57 ldr r3, [pc, #348] ; (8007cac ) + 8007b50: 681b ldr r3, [r3, #0] + 8007b52: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007b56: 2b00 cmp r3, #0 + 8007b58: d1f0 bne.n 8007b3c + 8007b5a: e000 b.n 8007b5e + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8007b5c: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8007b5e: 687b ldr r3, [r7, #4] + 8007b60: 681b ldr r3, [r3, #0] + 8007b62: f003 0302 and.w r3, r3, #2 + 8007b66: 2b00 cmp r3, #0 + 8007b68: d069 beq.n 8007c3e + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 8007b6a: 4b50 ldr r3, [pc, #320] ; (8007cac ) + 8007b6c: 689b ldr r3, [r3, #8] + 8007b6e: f003 030c and.w r3, r3, #12 + 8007b72: 2b00 cmp r3, #0 + 8007b74: d00b beq.n 8007b8e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8007b76: 4b4d ldr r3, [pc, #308] ; (8007cac ) + 8007b78: 689b ldr r3, [r3, #8] + 8007b7a: f003 030c and.w r3, r3, #12 + 8007b7e: 2b08 cmp r3, #8 + 8007b80: d11c bne.n 8007bbc + 8007b82: 4b4a ldr r3, [pc, #296] ; (8007cac ) + 8007b84: 685b ldr r3, [r3, #4] + 8007b86: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8007b8a: 2b00 cmp r3, #0 + 8007b8c: d116 bne.n 8007bbc + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8007b8e: 4b47 ldr r3, [pc, #284] ; (8007cac ) + 8007b90: 681b ldr r3, [r3, #0] + 8007b92: f003 0302 and.w r3, r3, #2 + 8007b96: 2b00 cmp r3, #0 + 8007b98: d005 beq.n 8007ba6 + 8007b9a: 687b ldr r3, [r7, #4] + 8007b9c: 68db ldr r3, [r3, #12] + 8007b9e: 2b01 cmp r3, #1 + 8007ba0: d001 beq.n 8007ba6 + { + return HAL_ERROR; + 8007ba2: 2301 movs r3, #1 + 8007ba4: e1df b.n 8007f66 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8007ba6: 4b41 ldr r3, [pc, #260] ; (8007cac ) + 8007ba8: 681b ldr r3, [r3, #0] + 8007baa: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8007bae: 687b ldr r3, [r7, #4] + 8007bb0: 691b ldr r3, [r3, #16] + 8007bb2: 00db lsls r3, r3, #3 + 8007bb4: 493d ldr r1, [pc, #244] ; (8007cac ) + 8007bb6: 4313 orrs r3, r2 + 8007bb8: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8007bba: e040 b.n 8007c3e + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + 8007bbc: 687b ldr r3, [r7, #4] + 8007bbe: 68db ldr r3, [r3, #12] + 8007bc0: 2b00 cmp r3, #0 + 8007bc2: d023 beq.n 8007c0c + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8007bc4: 4b39 ldr r3, [pc, #228] ; (8007cac ) + 8007bc6: 681b ldr r3, [r3, #0] + 8007bc8: 4a38 ldr r2, [pc, #224] ; (8007cac ) + 8007bca: f043 0301 orr.w r3, r3, #1 + 8007bce: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007bd0: f7fc fe50 bl 8004874 + 8007bd4: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007bd6: e008 b.n 8007bea + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8007bd8: f7fc fe4c bl 8004874 + 8007bdc: 4602 mov r2, r0 + 8007bde: 693b ldr r3, [r7, #16] + 8007be0: 1ad3 subs r3, r2, r3 + 8007be2: 2b02 cmp r3, #2 + 8007be4: d901 bls.n 8007bea + { + return HAL_TIMEOUT; + 8007be6: 2303 movs r3, #3 + 8007be8: e1bd b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007bea: 4b30 ldr r3, [pc, #192] ; (8007cac ) + 8007bec: 681b ldr r3, [r3, #0] + 8007bee: f003 0302 and.w r3, r3, #2 + 8007bf2: 2b00 cmp r3, #0 + 8007bf4: d0f0 beq.n 8007bd8 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8007bf6: 4b2d ldr r3, [pc, #180] ; (8007cac ) + 8007bf8: 681b ldr r3, [r3, #0] + 8007bfa: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8007bfe: 687b ldr r3, [r7, #4] + 8007c00: 691b ldr r3, [r3, #16] + 8007c02: 00db lsls r3, r3, #3 + 8007c04: 4929 ldr r1, [pc, #164] ; (8007cac ) + 8007c06: 4313 orrs r3, r2 + 8007c08: 600b str r3, [r1, #0] + 8007c0a: e018 b.n 8007c3e + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8007c0c: 4b27 ldr r3, [pc, #156] ; (8007cac ) + 8007c0e: 681b ldr r3, [r3, #0] + 8007c10: 4a26 ldr r2, [pc, #152] ; (8007cac ) + 8007c12: f023 0301 bic.w r3, r3, #1 + 8007c16: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007c18: f7fc fe2c bl 8004874 + 8007c1c: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8007c1e: e008 b.n 8007c32 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8007c20: f7fc fe28 bl 8004874 + 8007c24: 4602 mov r2, r0 + 8007c26: 693b ldr r3, [r7, #16] + 8007c28: 1ad3 subs r3, r2, r3 + 8007c2a: 2b02 cmp r3, #2 + 8007c2c: d901 bls.n 8007c32 + { + return HAL_TIMEOUT; + 8007c2e: 2303 movs r3, #3 + 8007c30: e199 b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8007c32: 4b1e ldr r3, [pc, #120] ; (8007cac ) + 8007c34: 681b ldr r3, [r3, #0] + 8007c36: f003 0302 and.w r3, r3, #2 + 8007c3a: 2b00 cmp r3, #0 + 8007c3c: d1f0 bne.n 8007c20 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8007c3e: 687b ldr r3, [r7, #4] + 8007c40: 681b ldr r3, [r3, #0] + 8007c42: f003 0308 and.w r3, r3, #8 + 8007c46: 2b00 cmp r3, #0 + 8007c48: d038 beq.n 8007cbc + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + 8007c4a: 687b ldr r3, [r7, #4] + 8007c4c: 695b ldr r3, [r3, #20] + 8007c4e: 2b00 cmp r3, #0 + 8007c50: d019 beq.n 8007c86 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8007c52: 4b16 ldr r3, [pc, #88] ; (8007cac ) + 8007c54: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007c56: 4a15 ldr r2, [pc, #84] ; (8007cac ) + 8007c58: f043 0301 orr.w r3, r3, #1 + 8007c5c: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007c5e: f7fc fe09 bl 8004874 + 8007c62: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8007c64: e008 b.n 8007c78 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8007c66: f7fc fe05 bl 8004874 + 8007c6a: 4602 mov r2, r0 + 8007c6c: 693b ldr r3, [r7, #16] + 8007c6e: 1ad3 subs r3, r2, r3 + 8007c70: 2b02 cmp r3, #2 + 8007c72: d901 bls.n 8007c78 + { + return HAL_TIMEOUT; + 8007c74: 2303 movs r3, #3 + 8007c76: e176 b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8007c78: 4b0c ldr r3, [pc, #48] ; (8007cac ) + 8007c7a: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007c7c: f003 0302 and.w r3, r3, #2 + 8007c80: 2b00 cmp r3, #0 + 8007c82: d0f0 beq.n 8007c66 + 8007c84: e01a b.n 8007cbc + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8007c86: 4b09 ldr r3, [pc, #36] ; (8007cac ) + 8007c88: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007c8a: 4a08 ldr r2, [pc, #32] ; (8007cac ) + 8007c8c: f023 0301 bic.w r3, r3, #1 + 8007c90: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007c92: f7fc fdef bl 8004874 + 8007c96: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8007c98: e00a b.n 8007cb0 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8007c9a: f7fc fdeb bl 8004874 + 8007c9e: 4602 mov r2, r0 + 8007ca0: 693b ldr r3, [r7, #16] + 8007ca2: 1ad3 subs r3, r2, r3 + 8007ca4: 2b02 cmp r3, #2 + 8007ca6: d903 bls.n 8007cb0 + { + return HAL_TIMEOUT; + 8007ca8: 2303 movs r3, #3 + 8007caa: e15c b.n 8007f66 + 8007cac: 40023800 .word 0x40023800 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8007cb0: 4b91 ldr r3, [pc, #580] ; (8007ef8 ) + 8007cb2: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007cb4: f003 0302 and.w r3, r3, #2 + 8007cb8: 2b00 cmp r3, #0 + 8007cba: d1ee bne.n 8007c9a + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8007cbc: 687b ldr r3, [r7, #4] + 8007cbe: 681b ldr r3, [r3, #0] + 8007cc0: f003 0304 and.w r3, r3, #4 + 8007cc4: 2b00 cmp r3, #0 + 8007cc6: f000 80a4 beq.w 8007e12 + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8007cca: 4b8b ldr r3, [pc, #556] ; (8007ef8 ) + 8007ccc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007cce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8007cd2: 2b00 cmp r3, #0 + 8007cd4: d10d bne.n 8007cf2 + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8007cd6: 4b88 ldr r3, [pc, #544] ; (8007ef8 ) + 8007cd8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007cda: 4a87 ldr r2, [pc, #540] ; (8007ef8 ) + 8007cdc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8007ce0: 6413 str r3, [r2, #64] ; 0x40 + 8007ce2: 4b85 ldr r3, [pc, #532] ; (8007ef8 ) + 8007ce4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007ce6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8007cea: 60bb str r3, [r7, #8] + 8007cec: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8007cee: 2301 movs r3, #1 + 8007cf0: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8007cf2: 4b82 ldr r3, [pc, #520] ; (8007efc ) + 8007cf4: 681b ldr r3, [r3, #0] + 8007cf6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007cfa: 2b00 cmp r3, #0 + 8007cfc: d118 bne.n 8007d30 + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8007cfe: 4b7f ldr r3, [pc, #508] ; (8007efc ) + 8007d00: 681b ldr r3, [r3, #0] + 8007d02: 4a7e ldr r2, [pc, #504] ; (8007efc ) + 8007d04: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8007d08: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8007d0a: f7fc fdb3 bl 8004874 + 8007d0e: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8007d10: e008 b.n 8007d24 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8007d12: f7fc fdaf bl 8004874 + 8007d16: 4602 mov r2, r0 + 8007d18: 693b ldr r3, [r7, #16] + 8007d1a: 1ad3 subs r3, r2, r3 + 8007d1c: 2b64 cmp r3, #100 ; 0x64 + 8007d1e: d901 bls.n 8007d24 + { + return HAL_TIMEOUT; + 8007d20: 2303 movs r3, #3 + 8007d22: e120 b.n 8007f66 + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8007d24: 4b75 ldr r3, [pc, #468] ; (8007efc ) + 8007d26: 681b ldr r3, [r3, #0] + 8007d28: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007d2c: 2b00 cmp r3, #0 + 8007d2e: d0f0 beq.n 8007d12 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8007d30: 687b ldr r3, [r7, #4] + 8007d32: 689b ldr r3, [r3, #8] + 8007d34: 2b01 cmp r3, #1 + 8007d36: d106 bne.n 8007d46 + 8007d38: 4b6f ldr r3, [pc, #444] ; (8007ef8 ) + 8007d3a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d3c: 4a6e ldr r2, [pc, #440] ; (8007ef8 ) + 8007d3e: f043 0301 orr.w r3, r3, #1 + 8007d42: 6713 str r3, [r2, #112] ; 0x70 + 8007d44: e02d b.n 8007da2 + 8007d46: 687b ldr r3, [r7, #4] + 8007d48: 689b ldr r3, [r3, #8] + 8007d4a: 2b00 cmp r3, #0 + 8007d4c: d10c bne.n 8007d68 + 8007d4e: 4b6a ldr r3, [pc, #424] ; (8007ef8 ) + 8007d50: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d52: 4a69 ldr r2, [pc, #420] ; (8007ef8 ) + 8007d54: f023 0301 bic.w r3, r3, #1 + 8007d58: 6713 str r3, [r2, #112] ; 0x70 + 8007d5a: 4b67 ldr r3, [pc, #412] ; (8007ef8 ) + 8007d5c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d5e: 4a66 ldr r2, [pc, #408] ; (8007ef8 ) + 8007d60: f023 0304 bic.w r3, r3, #4 + 8007d64: 6713 str r3, [r2, #112] ; 0x70 + 8007d66: e01c b.n 8007da2 + 8007d68: 687b ldr r3, [r7, #4] + 8007d6a: 689b ldr r3, [r3, #8] + 8007d6c: 2b05 cmp r3, #5 + 8007d6e: d10c bne.n 8007d8a + 8007d70: 4b61 ldr r3, [pc, #388] ; (8007ef8 ) + 8007d72: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d74: 4a60 ldr r2, [pc, #384] ; (8007ef8 ) + 8007d76: f043 0304 orr.w r3, r3, #4 + 8007d7a: 6713 str r3, [r2, #112] ; 0x70 + 8007d7c: 4b5e ldr r3, [pc, #376] ; (8007ef8 ) + 8007d7e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d80: 4a5d ldr r2, [pc, #372] ; (8007ef8 ) + 8007d82: f043 0301 orr.w r3, r3, #1 + 8007d86: 6713 str r3, [r2, #112] ; 0x70 + 8007d88: e00b b.n 8007da2 + 8007d8a: 4b5b ldr r3, [pc, #364] ; (8007ef8 ) + 8007d8c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d8e: 4a5a ldr r2, [pc, #360] ; (8007ef8 ) + 8007d90: f023 0301 bic.w r3, r3, #1 + 8007d94: 6713 str r3, [r2, #112] ; 0x70 + 8007d96: 4b58 ldr r3, [pc, #352] ; (8007ef8 ) + 8007d98: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007d9a: 4a57 ldr r2, [pc, #348] ; (8007ef8 ) + 8007d9c: f023 0304 bic.w r3, r3, #4 + 8007da0: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8007da2: 687b ldr r3, [r7, #4] + 8007da4: 689b ldr r3, [r3, #8] + 8007da6: 2b00 cmp r3, #0 + 8007da8: d015 beq.n 8007dd6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007daa: f7fc fd63 bl 8004874 + 8007dae: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007db0: e00a b.n 8007dc8 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8007db2: f7fc fd5f bl 8004874 + 8007db6: 4602 mov r2, r0 + 8007db8: 693b ldr r3, [r7, #16] + 8007dba: 1ad3 subs r3, r2, r3 + 8007dbc: f241 3288 movw r2, #5000 ; 0x1388 + 8007dc0: 4293 cmp r3, r2 + 8007dc2: d901 bls.n 8007dc8 + { + return HAL_TIMEOUT; + 8007dc4: 2303 movs r3, #3 + 8007dc6: e0ce b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007dc8: 4b4b ldr r3, [pc, #300] ; (8007ef8 ) + 8007dca: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007dcc: f003 0302 and.w r3, r3, #2 + 8007dd0: 2b00 cmp r3, #0 + 8007dd2: d0ee beq.n 8007db2 + 8007dd4: e014 b.n 8007e00 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007dd6: f7fc fd4d bl 8004874 + 8007dda: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8007ddc: e00a b.n 8007df4 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8007dde: f7fc fd49 bl 8004874 + 8007de2: 4602 mov r2, r0 + 8007de4: 693b ldr r3, [r7, #16] + 8007de6: 1ad3 subs r3, r2, r3 + 8007de8: f241 3288 movw r2, #5000 ; 0x1388 + 8007dec: 4293 cmp r3, r2 + 8007dee: d901 bls.n 8007df4 + { + return HAL_TIMEOUT; + 8007df0: 2303 movs r3, #3 + 8007df2: e0b8 b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8007df4: 4b40 ldr r3, [pc, #256] ; (8007ef8 ) + 8007df6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007df8: f003 0302 and.w r3, r3, #2 + 8007dfc: 2b00 cmp r3, #0 + 8007dfe: d1ee bne.n 8007dde + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + 8007e00: 7dfb ldrb r3, [r7, #23] + 8007e02: 2b01 cmp r3, #1 + 8007e04: d105 bne.n 8007e12 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8007e06: 4b3c ldr r3, [pc, #240] ; (8007ef8 ) + 8007e08: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007e0a: 4a3b ldr r2, [pc, #236] ; (8007ef8 ) + 8007e0c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8007e10: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8007e12: 687b ldr r3, [r7, #4] + 8007e14: 699b ldr r3, [r3, #24] + 8007e16: 2b00 cmp r3, #0 + 8007e18: f000 80a4 beq.w 8007f64 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8007e1c: 4b36 ldr r3, [pc, #216] ; (8007ef8 ) + 8007e1e: 689b ldr r3, [r3, #8] + 8007e20: f003 030c and.w r3, r3, #12 + 8007e24: 2b08 cmp r3, #8 + 8007e26: d06b beq.n 8007f00 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8007e28: 687b ldr r3, [r7, #4] + 8007e2a: 699b ldr r3, [r3, #24] + 8007e2c: 2b02 cmp r3, #2 + 8007e2e: d149 bne.n 8007ec4 +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8007e30: 4b31 ldr r3, [pc, #196] ; (8007ef8 ) + 8007e32: 681b ldr r3, [r3, #0] + 8007e34: 4a30 ldr r2, [pc, #192] ; (8007ef8 ) + 8007e36: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8007e3a: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007e3c: f7fc fd1a bl 8004874 + 8007e40: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007e42: e008 b.n 8007e56 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8007e44: f7fc fd16 bl 8004874 + 8007e48: 4602 mov r2, r0 + 8007e4a: 693b ldr r3, [r7, #16] + 8007e4c: 1ad3 subs r3, r2, r3 + 8007e4e: 2b02 cmp r3, #2 + 8007e50: d901 bls.n 8007e56 + { + return HAL_TIMEOUT; + 8007e52: 2303 movs r3, #3 + 8007e54: e087 b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007e56: 4b28 ldr r3, [pc, #160] ; (8007ef8 ) + 8007e58: 681b ldr r3, [r3, #0] + 8007e5a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8007e5e: 2b00 cmp r3, #0 + 8007e60: d1f0 bne.n 8007e44 + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8007e62: 687b ldr r3, [r7, #4] + 8007e64: 69da ldr r2, [r3, #28] + 8007e66: 687b ldr r3, [r7, #4] + 8007e68: 6a1b ldr r3, [r3, #32] + 8007e6a: 431a orrs r2, r3 + 8007e6c: 687b ldr r3, [r7, #4] + 8007e6e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007e70: 019b lsls r3, r3, #6 + 8007e72: 431a orrs r2, r3 + 8007e74: 687b ldr r3, [r7, #4] + 8007e76: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007e78: 085b lsrs r3, r3, #1 + 8007e7a: 3b01 subs r3, #1 + 8007e7c: 041b lsls r3, r3, #16 + 8007e7e: 431a orrs r2, r3 + 8007e80: 687b ldr r3, [r7, #4] + 8007e82: 6adb ldr r3, [r3, #44] ; 0x2c + 8007e84: 061b lsls r3, r3, #24 + 8007e86: 4313 orrs r3, r2 + 8007e88: 4a1b ldr r2, [pc, #108] ; (8007ef8 ) + 8007e8a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 8007e8e: 6053 str r3, [r2, #4] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8007e90: 4b19 ldr r3, [pc, #100] ; (8007ef8 ) + 8007e92: 681b ldr r3, [r3, #0] + 8007e94: 4a18 ldr r2, [pc, #96] ; (8007ef8 ) + 8007e96: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8007e9a: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007e9c: f7fc fcea bl 8004874 + 8007ea0: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007ea2: e008 b.n 8007eb6 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8007ea4: f7fc fce6 bl 8004874 + 8007ea8: 4602 mov r2, r0 + 8007eaa: 693b ldr r3, [r7, #16] + 8007eac: 1ad3 subs r3, r2, r3 + 8007eae: 2b02 cmp r3, #2 + 8007eb0: d901 bls.n 8007eb6 + { + return HAL_TIMEOUT; + 8007eb2: 2303 movs r3, #3 + 8007eb4: e057 b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007eb6: 4b10 ldr r3, [pc, #64] ; (8007ef8 ) + 8007eb8: 681b ldr r3, [r3, #0] + 8007eba: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8007ebe: 2b00 cmp r3, #0 + 8007ec0: d0f0 beq.n 8007ea4 + 8007ec2: e04f b.n 8007f64 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8007ec4: 4b0c ldr r3, [pc, #48] ; (8007ef8 ) + 8007ec6: 681b ldr r3, [r3, #0] + 8007ec8: 4a0b ldr r2, [pc, #44] ; (8007ef8 ) + 8007eca: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8007ece: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007ed0: f7fc fcd0 bl 8004874 + 8007ed4: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007ed6: e008 b.n 8007eea + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8007ed8: f7fc fccc bl 8004874 + 8007edc: 4602 mov r2, r0 + 8007ede: 693b ldr r3, [r7, #16] + 8007ee0: 1ad3 subs r3, r2, r3 + 8007ee2: 2b02 cmp r3, #2 + 8007ee4: d901 bls.n 8007eea + { + return HAL_TIMEOUT; + 8007ee6: 2303 movs r3, #3 + 8007ee8: e03d b.n 8007f66 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007eea: 4b03 ldr r3, [pc, #12] ; (8007ef8 ) + 8007eec: 681b ldr r3, [r3, #0] + 8007eee: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8007ef2: 2b00 cmp r3, #0 + 8007ef4: d1f0 bne.n 8007ed8 + 8007ef6: e035 b.n 8007f64 + 8007ef8: 40023800 .word 0x40023800 + 8007efc: 40007000 .word 0x40007000 + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 8007f00: 4b1b ldr r3, [pc, #108] ; (8007f70 ) + 8007f02: 685b ldr r3, [r3, #4] + 8007f04: 60fb str r3, [r7, #12] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 8007f06: 687b ldr r3, [r7, #4] + 8007f08: 699b ldr r3, [r3, #24] + 8007f0a: 2b01 cmp r3, #1 + 8007f0c: d028 beq.n 8007f60 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8007f0e: 68fb ldr r3, [r7, #12] + 8007f10: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 8007f14: 687b ldr r3, [r7, #4] + 8007f16: 69db ldr r3, [r3, #28] + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 8007f18: 429a cmp r2, r3 + 8007f1a: d121 bne.n 8007f60 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8007f1c: 68fb ldr r3, [r7, #12] + 8007f1e: f003 023f and.w r2, r3, #63 ; 0x3f + 8007f22: 687b ldr r3, [r7, #4] + 8007f24: 6a1b ldr r3, [r3, #32] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8007f26: 429a cmp r2, r3 + 8007f28: d11a bne.n 8007f60 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 8007f2a: 68fa ldr r2, [r7, #12] + 8007f2c: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8007f30: 4013 ands r3, r2 + 8007f32: 687a ldr r2, [r7, #4] + 8007f34: 6a52 ldr r2, [r2, #36] ; 0x24 + 8007f36: 0192 lsls r2, r2, #6 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8007f38: 4293 cmp r3, r2 + 8007f3a: d111 bne.n 8007f60 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + 8007f3c: 68fb ldr r3, [r7, #12] + 8007f3e: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 8007f42: 687b ldr r3, [r7, #4] + 8007f44: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007f46: 085b lsrs r3, r3, #1 + 8007f48: 3b01 subs r3, #1 + 8007f4a: 041b lsls r3, r3, #16 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 8007f4c: 429a cmp r2, r3 + 8007f4e: d107 bne.n 8007f60 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) + 8007f50: 68fb ldr r3, [r7, #12] + 8007f52: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 8007f56: 687b ldr r3, [r7, #4] + 8007f58: 6adb ldr r3, [r3, #44] ; 0x2c + 8007f5a: 061b lsls r3, r3, #24 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + 8007f5c: 429a cmp r2, r3 + 8007f5e: d001 beq.n 8007f64 +#endif + { + return HAL_ERROR; + 8007f60: 2301 movs r3, #1 + 8007f62: e000 b.n 8007f66 + } + } + } + return HAL_OK; + 8007f64: 2300 movs r3, #0 +} + 8007f66: 4618 mov r0, r3 + 8007f68: 3718 adds r7, #24 + 8007f6a: 46bd mov sp, r7 + 8007f6c: bd80 pop {r7, pc} + 8007f6e: bf00 nop + 8007f70: 40023800 .word 0x40023800 + +08007f74 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8007f74: b580 push {r7, lr} + 8007f76: b084 sub sp, #16 + 8007f78: af00 add r7, sp, #0 + 8007f7a: 6078 str r0, [r7, #4] + 8007f7c: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 8007f7e: 2300 movs r3, #0 + 8007f80: 60fb str r3, [r7, #12] + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8007f82: 687b ldr r3, [r7, #4] + 8007f84: 2b00 cmp r3, #0 + 8007f86: d101 bne.n 8007f8c + { + return HAL_ERROR; + 8007f88: 2301 movs r3, #1 + 8007f8a: e0d0 b.n 800812e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8007f8c: 4b6a ldr r3, [pc, #424] ; (8008138 ) + 8007f8e: 681b ldr r3, [r3, #0] + 8007f90: f003 030f and.w r3, r3, #15 + 8007f94: 683a ldr r2, [r7, #0] + 8007f96: 429a cmp r2, r3 + 8007f98: d910 bls.n 8007fbc + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8007f9a: 4b67 ldr r3, [pc, #412] ; (8008138 ) + 8007f9c: 681b ldr r3, [r3, #0] + 8007f9e: f023 020f bic.w r2, r3, #15 + 8007fa2: 4965 ldr r1, [pc, #404] ; (8008138 ) + 8007fa4: 683b ldr r3, [r7, #0] + 8007fa6: 4313 orrs r3, r2 + 8007fa8: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8007faa: 4b63 ldr r3, [pc, #396] ; (8008138 ) + 8007fac: 681b ldr r3, [r3, #0] + 8007fae: f003 030f and.w r3, r3, #15 + 8007fb2: 683a ldr r2, [r7, #0] + 8007fb4: 429a cmp r2, r3 + 8007fb6: d001 beq.n 8007fbc + { + return HAL_ERROR; + 8007fb8: 2301 movs r3, #1 + 8007fba: e0b8 b.n 800812e + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8007fbc: 687b ldr r3, [r7, #4] + 8007fbe: 681b ldr r3, [r3, #0] + 8007fc0: f003 0302 and.w r3, r3, #2 + 8007fc4: 2b00 cmp r3, #0 + 8007fc6: d020 beq.n 800800a + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8007fc8: 687b ldr r3, [r7, #4] + 8007fca: 681b ldr r3, [r3, #0] + 8007fcc: f003 0304 and.w r3, r3, #4 + 8007fd0: 2b00 cmp r3, #0 + 8007fd2: d005 beq.n 8007fe0 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8007fd4: 4b59 ldr r3, [pc, #356] ; (800813c ) + 8007fd6: 689b ldr r3, [r3, #8] + 8007fd8: 4a58 ldr r2, [pc, #352] ; (800813c ) + 8007fda: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 8007fde: 6093 str r3, [r2, #8] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8007fe0: 687b ldr r3, [r7, #4] + 8007fe2: 681b ldr r3, [r3, #0] + 8007fe4: f003 0308 and.w r3, r3, #8 + 8007fe8: 2b00 cmp r3, #0 + 8007fea: d005 beq.n 8007ff8 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8007fec: 4b53 ldr r3, [pc, #332] ; (800813c ) + 8007fee: 689b ldr r3, [r3, #8] + 8007ff0: 4a52 ldr r2, [pc, #328] ; (800813c ) + 8007ff2: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8007ff6: 6093 str r3, [r2, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8007ff8: 4b50 ldr r3, [pc, #320] ; (800813c ) + 8007ffa: 689b ldr r3, [r3, #8] + 8007ffc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8008000: 687b ldr r3, [r7, #4] + 8008002: 689b ldr r3, [r3, #8] + 8008004: 494d ldr r1, [pc, #308] ; (800813c ) + 8008006: 4313 orrs r3, r2 + 8008008: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800800a: 687b ldr r3, [r7, #4] + 800800c: 681b ldr r3, [r3, #0] + 800800e: f003 0301 and.w r3, r3, #1 + 8008012: 2b00 cmp r3, #0 + 8008014: d040 beq.n 8008098 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8008016: 687b ldr r3, [r7, #4] + 8008018: 685b ldr r3, [r3, #4] + 800801a: 2b01 cmp r3, #1 + 800801c: d107 bne.n 800802e + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800801e: 4b47 ldr r3, [pc, #284] ; (800813c ) + 8008020: 681b ldr r3, [r3, #0] + 8008022: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8008026: 2b00 cmp r3, #0 + 8008028: d115 bne.n 8008056 + { + return HAL_ERROR; + 800802a: 2301 movs r3, #1 + 800802c: e07f b.n 800812e + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800802e: 687b ldr r3, [r7, #4] + 8008030: 685b ldr r3, [r3, #4] + 8008032: 2b02 cmp r3, #2 + 8008034: d107 bne.n 8008046 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8008036: 4b41 ldr r3, [pc, #260] ; (800813c ) + 8008038: 681b ldr r3, [r3, #0] + 800803a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800803e: 2b00 cmp r3, #0 + 8008040: d109 bne.n 8008056 + { + return HAL_ERROR; + 8008042: 2301 movs r3, #1 + 8008044: e073 b.n 800812e + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8008046: 4b3d ldr r3, [pc, #244] ; (800813c ) + 8008048: 681b ldr r3, [r3, #0] + 800804a: f003 0302 and.w r3, r3, #2 + 800804e: 2b00 cmp r3, #0 + 8008050: d101 bne.n 8008056 + { + return HAL_ERROR; + 8008052: 2301 movs r3, #1 + 8008054: e06b b.n 800812e + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8008056: 4b39 ldr r3, [pc, #228] ; (800813c ) + 8008058: 689b ldr r3, [r3, #8] + 800805a: f023 0203 bic.w r2, r3, #3 + 800805e: 687b ldr r3, [r7, #4] + 8008060: 685b ldr r3, [r3, #4] + 8008062: 4936 ldr r1, [pc, #216] ; (800813c ) + 8008064: 4313 orrs r3, r2 + 8008066: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8008068: f7fc fc04 bl 8004874 + 800806c: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800806e: e00a b.n 8008086 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8008070: f7fc fc00 bl 8004874 + 8008074: 4602 mov r2, r0 + 8008076: 68fb ldr r3, [r7, #12] + 8008078: 1ad3 subs r3, r2, r3 + 800807a: f241 3288 movw r2, #5000 ; 0x1388 + 800807e: 4293 cmp r3, r2 + 8008080: d901 bls.n 8008086 + { + return HAL_TIMEOUT; + 8008082: 2303 movs r3, #3 + 8008084: e053 b.n 800812e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8008086: 4b2d ldr r3, [pc, #180] ; (800813c ) + 8008088: 689b ldr r3, [r3, #8] + 800808a: f003 020c and.w r2, r3, #12 + 800808e: 687b ldr r3, [r7, #4] + 8008090: 685b ldr r3, [r3, #4] + 8008092: 009b lsls r3, r3, #2 + 8008094: 429a cmp r2, r3 + 8008096: d1eb bne.n 8008070 + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8008098: 4b27 ldr r3, [pc, #156] ; (8008138 ) + 800809a: 681b ldr r3, [r3, #0] + 800809c: f003 030f and.w r3, r3, #15 + 80080a0: 683a ldr r2, [r7, #0] + 80080a2: 429a cmp r2, r3 + 80080a4: d210 bcs.n 80080c8 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80080a6: 4b24 ldr r3, [pc, #144] ; (8008138 ) + 80080a8: 681b ldr r3, [r3, #0] + 80080aa: f023 020f bic.w r2, r3, #15 + 80080ae: 4922 ldr r1, [pc, #136] ; (8008138 ) + 80080b0: 683b ldr r3, [r7, #0] + 80080b2: 4313 orrs r3, r2 + 80080b4: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 80080b6: 4b20 ldr r3, [pc, #128] ; (8008138 ) + 80080b8: 681b ldr r3, [r3, #0] + 80080ba: f003 030f and.w r3, r3, #15 + 80080be: 683a ldr r2, [r7, #0] + 80080c0: 429a cmp r2, r3 + 80080c2: d001 beq.n 80080c8 + { + return HAL_ERROR; + 80080c4: 2301 movs r3, #1 + 80080c6: e032 b.n 800812e + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80080c8: 687b ldr r3, [r7, #4] + 80080ca: 681b ldr r3, [r3, #0] + 80080cc: f003 0304 and.w r3, r3, #4 + 80080d0: 2b00 cmp r3, #0 + 80080d2: d008 beq.n 80080e6 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80080d4: 4b19 ldr r3, [pc, #100] ; (800813c ) + 80080d6: 689b ldr r3, [r3, #8] + 80080d8: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 80080dc: 687b ldr r3, [r7, #4] + 80080de: 68db ldr r3, [r3, #12] + 80080e0: 4916 ldr r1, [pc, #88] ; (800813c ) + 80080e2: 4313 orrs r3, r2 + 80080e4: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80080e6: 687b ldr r3, [r7, #4] + 80080e8: 681b ldr r3, [r3, #0] + 80080ea: f003 0308 and.w r3, r3, #8 + 80080ee: 2b00 cmp r3, #0 + 80080f0: d009 beq.n 8008106 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 80080f2: 4b12 ldr r3, [pc, #72] ; (800813c ) + 80080f4: 689b ldr r3, [r3, #8] + 80080f6: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 80080fa: 687b ldr r3, [r7, #4] + 80080fc: 691b ldr r3, [r3, #16] + 80080fe: 00db lsls r3, r3, #3 + 8008100: 490e ldr r1, [pc, #56] ; (800813c ) + 8008102: 4313 orrs r3, r2 + 8008104: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 8008106: f000 f821 bl 800814c + 800810a: 4602 mov r2, r0 + 800810c: 4b0b ldr r3, [pc, #44] ; (800813c ) + 800810e: 689b ldr r3, [r3, #8] + 8008110: 091b lsrs r3, r3, #4 + 8008112: f003 030f and.w r3, r3, #15 + 8008116: 490a ldr r1, [pc, #40] ; (8008140 ) + 8008118: 5ccb ldrb r3, [r1, r3] + 800811a: fa22 f303 lsr.w r3, r2, r3 + 800811e: 4a09 ldr r2, [pc, #36] ; (8008144 ) + 8008120: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + 8008122: 4b09 ldr r3, [pc, #36] ; (8008148 ) + 8008124: 681b ldr r3, [r3, #0] + 8008126: 4618 mov r0, r3 + 8008128: f7fb f858 bl 80031dc + + return HAL_OK; + 800812c: 2300 movs r3, #0 +} + 800812e: 4618 mov r0, r3 + 8008130: 3710 adds r7, #16 + 8008132: 46bd mov sp, r7 + 8008134: bd80 pop {r7, pc} + 8008136: bf00 nop + 8008138: 40023c00 .word 0x40023c00 + 800813c: 40023800 .word 0x40023800 + 8008140: 08021884 .word 0x08021884 + 8008144: 2000007c .word 0x2000007c + 8008148: 20000094 .word 0x20000094 + +0800814c : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 800814c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8008150: b090 sub sp, #64 ; 0x40 + 8008152: af00 add r7, sp, #0 + uint32_t pllm = 0, pllvco = 0, pllp = 0; + 8008154: 2300 movs r3, #0 + 8008156: 637b str r3, [r7, #52] ; 0x34 + 8008158: 2300 movs r3, #0 + 800815a: 63fb str r3, [r7, #60] ; 0x3c + 800815c: 2300 movs r3, #0 + 800815e: 633b str r3, [r7, #48] ; 0x30 + uint32_t sysclockfreq = 0; + 8008160: 2300 movs r3, #0 + 8008162: 63bb str r3, [r7, #56] ; 0x38 + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8008164: 4b59 ldr r3, [pc, #356] ; (80082cc ) + 8008166: 689b ldr r3, [r3, #8] + 8008168: f003 030c and.w r3, r3, #12 + 800816c: 2b08 cmp r3, #8 + 800816e: d00d beq.n 800818c + 8008170: 2b08 cmp r3, #8 + 8008172: f200 80a1 bhi.w 80082b8 + 8008176: 2b00 cmp r3, #0 + 8008178: d002 beq.n 8008180 + 800817a: 2b04 cmp r3, #4 + 800817c: d003 beq.n 8008186 + 800817e: e09b b.n 80082b8 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8008180: 4b53 ldr r3, [pc, #332] ; (80082d0 ) + 8008182: 63bb str r3, [r7, #56] ; 0x38 + break; + 8008184: e09b b.n 80082be + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 8008186: 4b53 ldr r3, [pc, #332] ; (80082d4 ) + 8008188: 63bb str r3, [r7, #56] ; 0x38 + break; + 800818a: e098 b.n 80082be + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 800818c: 4b4f ldr r3, [pc, #316] ; (80082cc ) + 800818e: 685b ldr r3, [r3, #4] + 8008190: f003 033f and.w r3, r3, #63 ; 0x3f + 8008194: 637b str r3, [r7, #52] ; 0x34 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 8008196: 4b4d ldr r3, [pc, #308] ; (80082cc ) + 8008198: 685b ldr r3, [r3, #4] + 800819a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800819e: 2b00 cmp r3, #0 + 80081a0: d028 beq.n 80081f4 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 80081a2: 4b4a ldr r3, [pc, #296] ; (80082cc ) + 80081a4: 685b ldr r3, [r3, #4] + 80081a6: 099b lsrs r3, r3, #6 + 80081a8: 2200 movs r2, #0 + 80081aa: 623b str r3, [r7, #32] + 80081ac: 627a str r2, [r7, #36] ; 0x24 + 80081ae: 6a3b ldr r3, [r7, #32] + 80081b0: f3c3 0008 ubfx r0, r3, #0, #9 + 80081b4: 2100 movs r1, #0 + 80081b6: 4b47 ldr r3, [pc, #284] ; (80082d4 ) + 80081b8: fb03 f201 mul.w r2, r3, r1 + 80081bc: 2300 movs r3, #0 + 80081be: fb00 f303 mul.w r3, r0, r3 + 80081c2: 4413 add r3, r2 + 80081c4: 4a43 ldr r2, [pc, #268] ; (80082d4 ) + 80081c6: fba0 1202 umull r1, r2, r0, r2 + 80081ca: 62fa str r2, [r7, #44] ; 0x2c + 80081cc: 460a mov r2, r1 + 80081ce: 62ba str r2, [r7, #40] ; 0x28 + 80081d0: 6afa ldr r2, [r7, #44] ; 0x2c + 80081d2: 4413 add r3, r2 + 80081d4: 62fb str r3, [r7, #44] ; 0x2c + 80081d6: 6b7b ldr r3, [r7, #52] ; 0x34 + 80081d8: 2200 movs r2, #0 + 80081da: 61bb str r3, [r7, #24] + 80081dc: 61fa str r2, [r7, #28] + 80081de: e9d7 2306 ldrd r2, r3, [r7, #24] + 80081e2: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 80081e6: f7f8 fd09 bl 8000bfc <__aeabi_uldivmod> + 80081ea: 4602 mov r2, r0 + 80081ec: 460b mov r3, r1 + 80081ee: 4613 mov r3, r2 + 80081f0: 63fb str r3, [r7, #60] ; 0x3c + 80081f2: e053 b.n 800829c + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 80081f4: 4b35 ldr r3, [pc, #212] ; (80082cc ) + 80081f6: 685b ldr r3, [r3, #4] + 80081f8: 099b lsrs r3, r3, #6 + 80081fa: 2200 movs r2, #0 + 80081fc: 613b str r3, [r7, #16] + 80081fe: 617a str r2, [r7, #20] + 8008200: 693b ldr r3, [r7, #16] + 8008202: f3c3 0a08 ubfx sl, r3, #0, #9 + 8008206: f04f 0b00 mov.w fp, #0 + 800820a: 4652 mov r2, sl + 800820c: 465b mov r3, fp + 800820e: f04f 0000 mov.w r0, #0 + 8008212: f04f 0100 mov.w r1, #0 + 8008216: 0159 lsls r1, r3, #5 + 8008218: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 800821c: 0150 lsls r0, r2, #5 + 800821e: 4602 mov r2, r0 + 8008220: 460b mov r3, r1 + 8008222: ebb2 080a subs.w r8, r2, sl + 8008226: eb63 090b sbc.w r9, r3, fp + 800822a: f04f 0200 mov.w r2, #0 + 800822e: f04f 0300 mov.w r3, #0 + 8008232: ea4f 1389 mov.w r3, r9, lsl #6 + 8008236: ea43 6398 orr.w r3, r3, r8, lsr #26 + 800823a: ea4f 1288 mov.w r2, r8, lsl #6 + 800823e: ebb2 0408 subs.w r4, r2, r8 + 8008242: eb63 0509 sbc.w r5, r3, r9 + 8008246: f04f 0200 mov.w r2, #0 + 800824a: f04f 0300 mov.w r3, #0 + 800824e: 00eb lsls r3, r5, #3 + 8008250: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8008254: 00e2 lsls r2, r4, #3 + 8008256: 4614 mov r4, r2 + 8008258: 461d mov r5, r3 + 800825a: eb14 030a adds.w r3, r4, sl + 800825e: 603b str r3, [r7, #0] + 8008260: eb45 030b adc.w r3, r5, fp + 8008264: 607b str r3, [r7, #4] + 8008266: f04f 0200 mov.w r2, #0 + 800826a: f04f 0300 mov.w r3, #0 + 800826e: e9d7 4500 ldrd r4, r5, [r7] + 8008272: 4629 mov r1, r5 + 8008274: 028b lsls r3, r1, #10 + 8008276: 4621 mov r1, r4 + 8008278: ea43 5391 orr.w r3, r3, r1, lsr #22 + 800827c: 4621 mov r1, r4 + 800827e: 028a lsls r2, r1, #10 + 8008280: 4610 mov r0, r2 + 8008282: 4619 mov r1, r3 + 8008284: 6b7b ldr r3, [r7, #52] ; 0x34 + 8008286: 2200 movs r2, #0 + 8008288: 60bb str r3, [r7, #8] + 800828a: 60fa str r2, [r7, #12] + 800828c: e9d7 2302 ldrd r2, r3, [r7, #8] + 8008290: f7f8 fcb4 bl 8000bfc <__aeabi_uldivmod> + 8008294: 4602 mov r2, r0 + 8008296: 460b mov r3, r1 + 8008298: 4613 mov r3, r2 + 800829a: 63fb str r3, [r7, #60] ; 0x3c + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + 800829c: 4b0b ldr r3, [pc, #44] ; (80082cc ) + 800829e: 685b ldr r3, [r3, #4] + 80082a0: 0c1b lsrs r3, r3, #16 + 80082a2: f003 0303 and.w r3, r3, #3 + 80082a6: 3301 adds r3, #1 + 80082a8: 005b lsls r3, r3, #1 + 80082aa: 633b str r3, [r7, #48] ; 0x30 + + sysclockfreq = pllvco / pllp; + 80082ac: 6bfa ldr r2, [r7, #60] ; 0x3c + 80082ae: 6b3b ldr r3, [r7, #48] ; 0x30 + 80082b0: fbb2 f3f3 udiv r3, r2, r3 + 80082b4: 63bb str r3, [r7, #56] ; 0x38 + break; + 80082b6: e002 b.n 80082be + } + default: + { + sysclockfreq = HSI_VALUE; + 80082b8: 4b05 ldr r3, [pc, #20] ; (80082d0 ) + 80082ba: 63bb str r3, [r7, #56] ; 0x38 + break; + 80082bc: bf00 nop + } + } + return sysclockfreq; + 80082be: 6bbb ldr r3, [r7, #56] ; 0x38 +} + 80082c0: 4618 mov r0, r3 + 80082c2: 3740 adds r7, #64 ; 0x40 + 80082c4: 46bd mov sp, r7 + 80082c6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80082ca: bf00 nop + 80082cc: 40023800 .word 0x40023800 + 80082d0: 00f42400 .word 0x00f42400 + 80082d4: 017d7840 .word 0x017d7840 + +080082d8 : + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 80082d8: b480 push {r7} + 80082da: af00 add r7, sp, #0 + return SystemCoreClock; + 80082dc: 4b03 ldr r3, [pc, #12] ; (80082ec ) + 80082de: 681b ldr r3, [r3, #0] +} + 80082e0: 4618 mov r0, r3 + 80082e2: 46bd mov sp, r7 + 80082e4: f85d 7b04 ldr.w r7, [sp], #4 + 80082e8: 4770 bx lr + 80082ea: bf00 nop + 80082ec: 2000007c .word 0x2000007c + +080082f0 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 80082f0: b580 push {r7, lr} + 80082f2: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 80082f4: f7ff fff0 bl 80082d8 + 80082f8: 4602 mov r2, r0 + 80082fa: 4b05 ldr r3, [pc, #20] ; (8008310 ) + 80082fc: 689b ldr r3, [r3, #8] + 80082fe: 0a9b lsrs r3, r3, #10 + 8008300: f003 0307 and.w r3, r3, #7 + 8008304: 4903 ldr r1, [pc, #12] ; (8008314 ) + 8008306: 5ccb ldrb r3, [r1, r3] + 8008308: fa22 f303 lsr.w r3, r2, r3 +} + 800830c: 4618 mov r0, r3 + 800830e: bd80 pop {r7, pc} + 8008310: 40023800 .word 0x40023800 + 8008314: 08021894 .word 0x08021894 + +08008318 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8008318: b580 push {r7, lr} + 800831a: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + 800831c: f7ff ffdc bl 80082d8 + 8008320: 4602 mov r2, r0 + 8008322: 4b05 ldr r3, [pc, #20] ; (8008338 ) + 8008324: 689b ldr r3, [r3, #8] + 8008326: 0b5b lsrs r3, r3, #13 + 8008328: f003 0307 and.w r3, r3, #7 + 800832c: 4903 ldr r1, [pc, #12] ; (800833c ) + 800832e: 5ccb ldrb r3, [r1, r3] + 8008330: fa22 f303 lsr.w r3, r2, r3 +} + 8008334: 4618 mov r0, r3 + 8008336: bd80 pop {r7, pc} + 8008338: 40023800 .word 0x40023800 + 800833c: 08021894 .word 0x08021894 + +08008340 : + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + 8008340: b480 push {r7} + 8008342: b083 sub sp, #12 + 8008344: af00 add r7, sp, #0 + 8008346: 6078 str r0, [r7, #4] + 8008348: 6039 str r1, [r7, #0] + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + 800834a: 687b ldr r3, [r7, #4] + 800834c: 220f movs r2, #15 + 800834e: 601a str r2, [r3, #0] + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 8008350: 4b12 ldr r3, [pc, #72] ; (800839c ) + 8008352: 689b ldr r3, [r3, #8] + 8008354: f003 0203 and.w r2, r3, #3 + 8008358: 687b ldr r3, [r7, #4] + 800835a: 605a str r2, [r3, #4] + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 800835c: 4b0f ldr r3, [pc, #60] ; (800839c ) + 800835e: 689b ldr r3, [r3, #8] + 8008360: f003 02f0 and.w r2, r3, #240 ; 0xf0 + 8008364: 687b ldr r3, [r7, #4] + 8008366: 609a str r2, [r3, #8] + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 8008368: 4b0c ldr r3, [pc, #48] ; (800839c ) + 800836a: 689b ldr r3, [r3, #8] + 800836c: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 8008370: 687b ldr r3, [r7, #4] + 8008372: 60da str r2, [r3, #12] + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + 8008374: 4b09 ldr r3, [pc, #36] ; (800839c ) + 8008376: 689b ldr r3, [r3, #8] + 8008378: 08db lsrs r3, r3, #3 + 800837a: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 800837e: 687b ldr r3, [r7, #4] + 8008380: 611a str r2, [r3, #16] + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 8008382: 4b07 ldr r3, [pc, #28] ; (80083a0 ) + 8008384: 681b ldr r3, [r3, #0] + 8008386: f003 020f and.w r2, r3, #15 + 800838a: 683b ldr r3, [r7, #0] + 800838c: 601a str r2, [r3, #0] +} + 800838e: bf00 nop + 8008390: 370c adds r7, #12 + 8008392: 46bd mov sp, r7 + 8008394: f85d 7b04 ldr.w r7, [sp], #4 + 8008398: 4770 bx lr + 800839a: bf00 nop + 800839c: 40023800 .word 0x40023800 + 80083a0: 40023c00 .word 0x40023c00 + +080083a4 : + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 80083a4: b580 push {r7, lr} + 80083a6: b088 sub sp, #32 + 80083a8: af00 add r7, sp, #0 + 80083aa: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 80083ac: 2300 movs r3, #0 + 80083ae: 617b str r3, [r7, #20] + uint32_t tmpreg0 = 0; + 80083b0: 2300 movs r3, #0 + 80083b2: 613b str r3, [r7, #16] + uint32_t tmpreg1 = 0; + 80083b4: 2300 movs r3, #0 + 80083b6: 60fb str r3, [r7, #12] + uint32_t plli2sused = 0; + 80083b8: 2300 movs r3, #0 + 80083ba: 61fb str r3, [r7, #28] + uint32_t pllsaiused = 0; + 80083bc: 2300 movs r3, #0 + 80083be: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 80083c0: 687b ldr r3, [r7, #4] + 80083c2: 681b ldr r3, [r3, #0] + 80083c4: f003 0301 and.w r3, r3, #1 + 80083c8: 2b00 cmp r3, #0 + 80083ca: d012 beq.n 80083f2 + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 80083cc: 4b69 ldr r3, [pc, #420] ; (8008574 ) + 80083ce: 689b ldr r3, [r3, #8] + 80083d0: 4a68 ldr r2, [pc, #416] ; (8008574 ) + 80083d2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 80083d6: 6093 str r3, [r2, #8] + 80083d8: 4b66 ldr r3, [pc, #408] ; (8008574 ) + 80083da: 689a ldr r2, [r3, #8] + 80083dc: 687b ldr r3, [r7, #4] + 80083de: 6b5b ldr r3, [r3, #52] ; 0x34 + 80083e0: 4964 ldr r1, [pc, #400] ; (8008574 ) + 80083e2: 4313 orrs r3, r2 + 80083e4: 608b str r3, [r1, #8] + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 80083e6: 687b ldr r3, [r7, #4] + 80083e8: 6b5b ldr r3, [r3, #52] ; 0x34 + 80083ea: 2b00 cmp r3, #0 + 80083ec: d101 bne.n 80083f2 + { + plli2sused = 1; + 80083ee: 2301 movs r3, #1 + 80083f0: 61fb str r3, [r7, #28] + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 80083f2: 687b ldr r3, [r7, #4] + 80083f4: 681b ldr r3, [r3, #0] + 80083f6: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80083fa: 2b00 cmp r3, #0 + 80083fc: d017 beq.n 800842e + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 80083fe: 4b5d ldr r3, [pc, #372] ; (8008574 ) + 8008400: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008404: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8008408: 687b ldr r3, [r7, #4] + 800840a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800840c: 4959 ldr r1, [pc, #356] ; (8008574 ) + 800840e: 4313 orrs r3, r2 + 8008410: f8c1 308c str.w r3, [r1, #140] ; 0x8c + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 8008414: 687b ldr r3, [r7, #4] + 8008416: 6bdb ldr r3, [r3, #60] ; 0x3c + 8008418: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800841c: d101 bne.n 8008422 + { + plli2sused = 1; + 800841e: 2301 movs r3, #1 + 8008420: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 8008422: 687b ldr r3, [r7, #4] + 8008424: 6bdb ldr r3, [r3, #60] ; 0x3c + 8008426: 2b00 cmp r3, #0 + 8008428: d101 bne.n 800842e + { + pllsaiused = 1; + 800842a: 2301 movs r3, #1 + 800842c: 61bb str r3, [r7, #24] + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 800842e: 687b ldr r3, [r7, #4] + 8008430: 681b ldr r3, [r3, #0] + 8008432: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8008436: 2b00 cmp r3, #0 + 8008438: d017 beq.n 800846a + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 800843a: 4b4e ldr r3, [pc, #312] ; (8008574 ) + 800843c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008440: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8008444: 687b ldr r3, [r7, #4] + 8008446: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008448: 494a ldr r1, [pc, #296] ; (8008574 ) + 800844a: 4313 orrs r3, r2 + 800844c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 8008450: 687b ldr r3, [r7, #4] + 8008452: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008454: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8008458: d101 bne.n 800845e + { + plli2sused = 1; + 800845a: 2301 movs r3, #1 + 800845c: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 800845e: 687b ldr r3, [r7, #4] + 8008460: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008462: 2b00 cmp r3, #0 + 8008464: d101 bne.n 800846a + { + pllsaiused = 1; + 8008466: 2301 movs r3, #1 + 8008468: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 800846a: 687b ldr r3, [r7, #4] + 800846c: 681b ldr r3, [r3, #0] + 800846e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8008472: 2b00 cmp r3, #0 + 8008474: d001 beq.n 800847a + { + plli2sused = 1; + 8008476: 2301 movs r3, #1 + 8008478: 61fb str r3, [r7, #28] + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 800847a: 687b ldr r3, [r7, #4] + 800847c: 681b ldr r3, [r3, #0] + 800847e: f003 0320 and.w r3, r3, #32 + 8008482: 2b00 cmp r3, #0 + 8008484: f000 808b beq.w 800859e + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8008488: 4b3a ldr r3, [pc, #232] ; (8008574 ) + 800848a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800848c: 4a39 ldr r2, [pc, #228] ; (8008574 ) + 800848e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8008492: 6413 str r3, [r2, #64] ; 0x40 + 8008494: 4b37 ldr r3, [pc, #220] ; (8008574 ) + 8008496: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008498: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800849c: 60bb str r3, [r7, #8] + 800849e: 68bb ldr r3, [r7, #8] + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 80084a0: 4b35 ldr r3, [pc, #212] ; (8008578 ) + 80084a2: 681b ldr r3, [r3, #0] + 80084a4: 4a34 ldr r2, [pc, #208] ; (8008578 ) + 80084a6: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80084aa: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80084ac: f7fc f9e2 bl 8004874 + 80084b0: 6178 str r0, [r7, #20] + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 80084b2: e008 b.n 80084c6 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80084b4: f7fc f9de bl 8004874 + 80084b8: 4602 mov r2, r0 + 80084ba: 697b ldr r3, [r7, #20] + 80084bc: 1ad3 subs r3, r2, r3 + 80084be: 2b64 cmp r3, #100 ; 0x64 + 80084c0: d901 bls.n 80084c6 + { + return HAL_TIMEOUT; + 80084c2: 2303 movs r3, #3 + 80084c4: e357 b.n 8008b76 + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 80084c6: 4b2c ldr r3, [pc, #176] ; (8008578 ) + 80084c8: 681b ldr r3, [r3, #0] + 80084ca: f403 7380 and.w r3, r3, #256 ; 0x100 + 80084ce: 2b00 cmp r3, #0 + 80084d0: d0f0 beq.n 80084b4 + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 80084d2: 4b28 ldr r3, [pc, #160] ; (8008574 ) + 80084d4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80084d6: f403 7340 and.w r3, r3, #768 ; 0x300 + 80084da: 613b str r3, [r7, #16] + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 80084dc: 693b ldr r3, [r7, #16] + 80084de: 2b00 cmp r3, #0 + 80084e0: d035 beq.n 800854e + 80084e2: 687b ldr r3, [r7, #4] + 80084e4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80084e6: f403 7340 and.w r3, r3, #768 ; 0x300 + 80084ea: 693a ldr r2, [r7, #16] + 80084ec: 429a cmp r2, r3 + 80084ee: d02e beq.n 800854e + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80084f0: 4b20 ldr r3, [pc, #128] ; (8008574 ) + 80084f2: 6f1b ldr r3, [r3, #112] ; 0x70 + 80084f4: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80084f8: 613b str r3, [r7, #16] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 80084fa: 4b1e ldr r3, [pc, #120] ; (8008574 ) + 80084fc: 6f1b ldr r3, [r3, #112] ; 0x70 + 80084fe: 4a1d ldr r2, [pc, #116] ; (8008574 ) + 8008500: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8008504: 6713 str r3, [r2, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_RELEASE(); + 8008506: 4b1b ldr r3, [pc, #108] ; (8008574 ) + 8008508: 6f1b ldr r3, [r3, #112] ; 0x70 + 800850a: 4a1a ldr r2, [pc, #104] ; (8008574 ) + 800850c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8008510: 6713 str r3, [r2, #112] ; 0x70 + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + 8008512: 4a18 ldr r2, [pc, #96] ; (8008574 ) + 8008514: 693b ldr r3, [r7, #16] + 8008516: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8008518: 4b16 ldr r3, [pc, #88] ; (8008574 ) + 800851a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800851c: f003 0301 and.w r3, r3, #1 + 8008520: 2b01 cmp r3, #1 + 8008522: d114 bne.n 800854e + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8008524: f7fc f9a6 bl 8004874 + 8008528: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 800852a: e00a b.n 8008542 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800852c: f7fc f9a2 bl 8004874 + 8008530: 4602 mov r2, r0 + 8008532: 697b ldr r3, [r7, #20] + 8008534: 1ad3 subs r3, r2, r3 + 8008536: f241 3288 movw r2, #5000 ; 0x1388 + 800853a: 4293 cmp r3, r2 + 800853c: d901 bls.n 8008542 + { + return HAL_TIMEOUT; + 800853e: 2303 movs r3, #3 + 8008540: e319 b.n 8008b76 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8008542: 4b0c ldr r3, [pc, #48] ; (8008574 ) + 8008544: 6f1b ldr r3, [r3, #112] ; 0x70 + 8008546: f003 0302 and.w r3, r3, #2 + 800854a: 2b00 cmp r3, #0 + 800854c: d0ee beq.n 800852c + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800854e: 687b ldr r3, [r7, #4] + 8008550: 6b1b ldr r3, [r3, #48] ; 0x30 + 8008552: f403 7340 and.w r3, r3, #768 ; 0x300 + 8008556: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 800855a: d111 bne.n 8008580 + 800855c: 4b05 ldr r3, [pc, #20] ; (8008574 ) + 800855e: 689b ldr r3, [r3, #8] + 8008560: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8008564: 687b ldr r3, [r7, #4] + 8008566: 6b19 ldr r1, [r3, #48] ; 0x30 + 8008568: 4b04 ldr r3, [pc, #16] ; (800857c ) + 800856a: 400b ands r3, r1 + 800856c: 4901 ldr r1, [pc, #4] ; (8008574 ) + 800856e: 4313 orrs r3, r2 + 8008570: 608b str r3, [r1, #8] + 8008572: e00b b.n 800858c + 8008574: 40023800 .word 0x40023800 + 8008578: 40007000 .word 0x40007000 + 800857c: 0ffffcff .word 0x0ffffcff + 8008580: 4baa ldr r3, [pc, #680] ; (800882c ) + 8008582: 689b ldr r3, [r3, #8] + 8008584: 4aa9 ldr r2, [pc, #676] ; (800882c ) + 8008586: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 800858a: 6093 str r3, [r2, #8] + 800858c: 4ba7 ldr r3, [pc, #668] ; (800882c ) + 800858e: 6f1a ldr r2, [r3, #112] ; 0x70 + 8008590: 687b ldr r3, [r7, #4] + 8008592: 6b1b ldr r3, [r3, #48] ; 0x30 + 8008594: f3c3 030b ubfx r3, r3, #0, #12 + 8008598: 49a4 ldr r1, [pc, #656] ; (800882c ) + 800859a: 4313 orrs r3, r2 + 800859c: 670b str r3, [r1, #112] ; 0x70 + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 800859e: 687b ldr r3, [r7, #4] + 80085a0: 681b ldr r3, [r3, #0] + 80085a2: f003 0310 and.w r3, r3, #16 + 80085a6: 2b00 cmp r3, #0 + 80085a8: d010 beq.n 80085cc + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 80085aa: 4ba0 ldr r3, [pc, #640] ; (800882c ) + 80085ac: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80085b0: 4a9e ldr r2, [pc, #632] ; (800882c ) + 80085b2: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80085b6: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 80085ba: 4b9c ldr r3, [pc, #624] ; (800882c ) + 80085bc: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 80085c0: 687b ldr r3, [r7, #4] + 80085c2: 6b9b ldr r3, [r3, #56] ; 0x38 + 80085c4: 4999 ldr r1, [pc, #612] ; (800882c ) + 80085c6: 4313 orrs r3, r2 + 80085c8: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 80085cc: 687b ldr r3, [r7, #4] + 80085ce: 681b ldr r3, [r3, #0] + 80085d0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80085d4: 2b00 cmp r3, #0 + 80085d6: d00a beq.n 80085ee + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 80085d8: 4b94 ldr r3, [pc, #592] ; (800882c ) + 80085da: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80085de: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 80085e2: 687b ldr r3, [r7, #4] + 80085e4: 6e5b ldr r3, [r3, #100] ; 0x64 + 80085e6: 4991 ldr r1, [pc, #580] ; (800882c ) + 80085e8: 4313 orrs r3, r2 + 80085ea: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 80085ee: 687b ldr r3, [r7, #4] + 80085f0: 681b ldr r3, [r3, #0] + 80085f2: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 80085f6: 2b00 cmp r3, #0 + 80085f8: d00a beq.n 8008610 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 80085fa: 4b8c ldr r3, [pc, #560] ; (800882c ) + 80085fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008600: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8008604: 687b ldr r3, [r7, #4] + 8008606: 6e9b ldr r3, [r3, #104] ; 0x68 + 8008608: 4988 ldr r1, [pc, #544] ; (800882c ) + 800860a: 4313 orrs r3, r2 + 800860c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8008610: 687b ldr r3, [r7, #4] + 8008612: 681b ldr r3, [r3, #0] + 8008614: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8008618: 2b00 cmp r3, #0 + 800861a: d00a beq.n 8008632 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 800861c: 4b83 ldr r3, [pc, #524] ; (800882c ) + 800861e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008622: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8008626: 687b ldr r3, [r7, #4] + 8008628: 6edb ldr r3, [r3, #108] ; 0x6c + 800862a: 4980 ldr r1, [pc, #512] ; (800882c ) + 800862c: 4313 orrs r3, r2 + 800862e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 8008632: 687b ldr r3, [r7, #4] + 8008634: 681b ldr r3, [r3, #0] + 8008636: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800863a: 2b00 cmp r3, #0 + 800863c: d00a beq.n 8008654 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 800863e: 4b7b ldr r3, [pc, #492] ; (800882c ) + 8008640: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008644: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8008648: 687b ldr r3, [r7, #4] + 800864a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800864c: 4977 ldr r1, [pc, #476] ; (800882c ) + 800864e: 4313 orrs r3, r2 + 8008650: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8008654: 687b ldr r3, [r7, #4] + 8008656: 681b ldr r3, [r3, #0] + 8008658: f003 0340 and.w r3, r3, #64 ; 0x40 + 800865c: 2b00 cmp r3, #0 + 800865e: d00a beq.n 8008676 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8008660: 4b72 ldr r3, [pc, #456] ; (800882c ) + 8008662: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008666: f023 0203 bic.w r2, r3, #3 + 800866a: 687b ldr r3, [r7, #4] + 800866c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800866e: 496f ldr r1, [pc, #444] ; (800882c ) + 8008670: 4313 orrs r3, r2 + 8008672: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8008676: 687b ldr r3, [r7, #4] + 8008678: 681b ldr r3, [r3, #0] + 800867a: f003 0380 and.w r3, r3, #128 ; 0x80 + 800867e: 2b00 cmp r3, #0 + 8008680: d00a beq.n 8008698 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8008682: 4b6a ldr r3, [pc, #424] ; (800882c ) + 8008684: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008688: f023 020c bic.w r2, r3, #12 + 800868c: 687b ldr r3, [r7, #4] + 800868e: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008690: 4966 ldr r1, [pc, #408] ; (800882c ) + 8008692: 4313 orrs r3, r2 + 8008694: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8008698: 687b ldr r3, [r7, #4] + 800869a: 681b ldr r3, [r3, #0] + 800869c: f403 7380 and.w r3, r3, #256 ; 0x100 + 80086a0: 2b00 cmp r3, #0 + 80086a2: d00a beq.n 80086ba + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 80086a4: 4b61 ldr r3, [pc, #388] ; (800882c ) + 80086a6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80086aa: f023 0230 bic.w r2, r3, #48 ; 0x30 + 80086ae: 687b ldr r3, [r7, #4] + 80086b0: 6cdb ldr r3, [r3, #76] ; 0x4c + 80086b2: 495e ldr r1, [pc, #376] ; (800882c ) + 80086b4: 4313 orrs r3, r2 + 80086b6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 80086ba: 687b ldr r3, [r7, #4] + 80086bc: 681b ldr r3, [r3, #0] + 80086be: f403 7300 and.w r3, r3, #512 ; 0x200 + 80086c2: 2b00 cmp r3, #0 + 80086c4: d00a beq.n 80086dc + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 80086c6: 4b59 ldr r3, [pc, #356] ; (800882c ) + 80086c8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80086cc: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 80086d0: 687b ldr r3, [r7, #4] + 80086d2: 6d1b ldr r3, [r3, #80] ; 0x50 + 80086d4: 4955 ldr r1, [pc, #340] ; (800882c ) + 80086d6: 4313 orrs r3, r2 + 80086d8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 80086dc: 687b ldr r3, [r7, #4] + 80086de: 681b ldr r3, [r3, #0] + 80086e0: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80086e4: 2b00 cmp r3, #0 + 80086e6: d00a beq.n 80086fe + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 80086e8: 4b50 ldr r3, [pc, #320] ; (800882c ) + 80086ea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80086ee: f423 7240 bic.w r2, r3, #768 ; 0x300 + 80086f2: 687b ldr r3, [r7, #4] + 80086f4: 6d5b ldr r3, [r3, #84] ; 0x54 + 80086f6: 494d ldr r1, [pc, #308] ; (800882c ) + 80086f8: 4313 orrs r3, r2 + 80086fa: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 80086fe: 687b ldr r3, [r7, #4] + 8008700: 681b ldr r3, [r3, #0] + 8008702: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8008706: 2b00 cmp r3, #0 + 8008708: d00a beq.n 8008720 + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 800870a: 4b48 ldr r3, [pc, #288] ; (800882c ) + 800870c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008710: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8008714: 687b ldr r3, [r7, #4] + 8008716: 6d9b ldr r3, [r3, #88] ; 0x58 + 8008718: 4944 ldr r1, [pc, #272] ; (800882c ) + 800871a: 4313 orrs r3, r2 + 800871c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 8008720: 687b ldr r3, [r7, #4] + 8008722: 681b ldr r3, [r3, #0] + 8008724: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8008728: 2b00 cmp r3, #0 + 800872a: d00a beq.n 8008742 + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 800872c: 4b3f ldr r3, [pc, #252] ; (800882c ) + 800872e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008732: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 8008736: 687b ldr r3, [r7, #4] + 8008738: 6ddb ldr r3, [r3, #92] ; 0x5c + 800873a: 493c ldr r1, [pc, #240] ; (800882c ) + 800873c: 4313 orrs r3, r2 + 800873e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 8008742: 687b ldr r3, [r7, #4] + 8008744: 681b ldr r3, [r3, #0] + 8008746: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 800874a: 2b00 cmp r3, #0 + 800874c: d00a beq.n 8008764 + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 800874e: 4b37 ldr r3, [pc, #220] ; (800882c ) + 8008750: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008754: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8008758: 687b ldr r3, [r7, #4] + 800875a: 6e1b ldr r3, [r3, #96] ; 0x60 + 800875c: 4933 ldr r1, [pc, #204] ; (800882c ) + 800875e: 4313 orrs r3, r2 + 8008760: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 8008764: 687b ldr r3, [r7, #4] + 8008766: 681b ldr r3, [r3, #0] + 8008768: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800876c: 2b00 cmp r3, #0 + 800876e: d00a beq.n 8008786 + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 8008770: 4b2e ldr r3, [pc, #184] ; (800882c ) + 8008772: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008776: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 800877a: 687b ldr r3, [r7, #4] + 800877c: 6f9b ldr r3, [r3, #120] ; 0x78 + 800877e: 492b ldr r1, [pc, #172] ; (800882c ) + 8008780: 4313 orrs r3, r2 + 8008782: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 8008786: 687b ldr r3, [r7, #4] + 8008788: 681b ldr r3, [r3, #0] + 800878a: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800878e: 2b00 cmp r3, #0 + 8008790: d011 beq.n 80087b6 + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 8008792: 4b26 ldr r3, [pc, #152] ; (800882c ) + 8008794: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008798: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 800879c: 687b ldr r3, [r7, #4] + 800879e: 6fdb ldr r3, [r3, #124] ; 0x7c + 80087a0: 4922 ldr r1, [pc, #136] ; (800882c ) + 80087a2: 4313 orrs r3, r2 + 80087a4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 80087a8: 687b ldr r3, [r7, #4] + 80087aa: 6fdb ldr r3, [r3, #124] ; 0x7c + 80087ac: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80087b0: d101 bne.n 80087b6 + { + pllsaiused = 1; + 80087b2: 2301 movs r3, #1 + 80087b4: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 80087b6: 687b ldr r3, [r7, #4] + 80087b8: 681b ldr r3, [r3, #0] + 80087ba: f003 0308 and.w r3, r3, #8 + 80087be: 2b00 cmp r3, #0 + 80087c0: d001 beq.n 80087c6 + { + pllsaiused = 1; + 80087c2: 2301 movs r3, #1 + 80087c4: 61bb str r3, [r7, #24] + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 80087c6: 687b ldr r3, [r7, #4] + 80087c8: 681b ldr r3, [r3, #0] + 80087ca: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 80087ce: 2b00 cmp r3, #0 + 80087d0: d00a beq.n 80087e8 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 80087d2: 4b16 ldr r3, [pc, #88] ; (800882c ) + 80087d4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80087d8: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 80087dc: 687b ldr r3, [r7, #4] + 80087de: 6f5b ldr r3, [r3, #116] ; 0x74 + 80087e0: 4912 ldr r1, [pc, #72] ; (800882c ) + 80087e2: 4313 orrs r3, r2 + 80087e4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 80087e8: 687b ldr r3, [r7, #4] + 80087ea: 681b ldr r3, [r3, #0] + 80087ec: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80087f0: 2b00 cmp r3, #0 + 80087f2: d00b beq.n 800880c + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 80087f4: 4b0d ldr r3, [pc, #52] ; (800882c ) + 80087f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80087fa: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 80087fe: 687b ldr r3, [r7, #4] + 8008800: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8008804: 4909 ldr r1, [pc, #36] ; (800882c ) + 8008806: 4313 orrs r3, r2 + 8008808: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + 800880c: 69fb ldr r3, [r7, #28] + 800880e: 2b01 cmp r3, #1 + 8008810: d006 beq.n 8008820 + 8008812: 687b ldr r3, [r7, #4] + 8008814: 681b ldr r3, [r3, #0] + 8008816: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800881a: 2b00 cmp r3, #0 + 800881c: f000 80d9 beq.w 80089d2 + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 8008820: 4b02 ldr r3, [pc, #8] ; (800882c ) + 8008822: 681b ldr r3, [r3, #0] + 8008824: 4a01 ldr r2, [pc, #4] ; (800882c ) + 8008826: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 800882a: e001 b.n 8008830 + 800882c: 40023800 .word 0x40023800 + 8008830: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8008832: f7fc f81f bl 8004874 + 8008836: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8008838: e008 b.n 800884c + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 800883a: f7fc f81b bl 8004874 + 800883e: 4602 mov r2, r0 + 8008840: 697b ldr r3, [r7, #20] + 8008842: 1ad3 subs r3, r2, r3 + 8008844: 2b64 cmp r3, #100 ; 0x64 + 8008846: d901 bls.n 800884c + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8008848: 2303 movs r3, #3 + 800884a: e194 b.n 8008b76 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 800884c: 4b6c ldr r3, [pc, #432] ; (8008a00 ) + 800884e: 681b ldr r3, [r3, #0] + 8008850: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8008854: 2b00 cmp r3, #0 + 8008856: d1f0 bne.n 800883a + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + 8008858: 687b ldr r3, [r7, #4] + 800885a: 681b ldr r3, [r3, #0] + 800885c: f003 0301 and.w r3, r3, #1 + 8008860: 2b00 cmp r3, #0 + 8008862: d021 beq.n 80088a8 + 8008864: 687b ldr r3, [r7, #4] + 8008866: 6b5b ldr r3, [r3, #52] ; 0x34 + 8008868: 2b00 cmp r3, #0 + 800886a: d11d bne.n 80088a8 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 800886c: 4b64 ldr r3, [pc, #400] ; (8008a00 ) + 800886e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8008872: 0c1b lsrs r3, r3, #16 + 8008874: f003 0303 and.w r3, r3, #3 + 8008878: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 800887a: 4b61 ldr r3, [pc, #388] ; (8008a00 ) + 800887c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8008880: 0e1b lsrs r3, r3, #24 + 8008882: f003 030f and.w r3, r3, #15 + 8008886: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + 8008888: 687b ldr r3, [r7, #4] + 800888a: 685b ldr r3, [r3, #4] + 800888c: 019a lsls r2, r3, #6 + 800888e: 693b ldr r3, [r7, #16] + 8008890: 041b lsls r3, r3, #16 + 8008892: 431a orrs r2, r3 + 8008894: 68fb ldr r3, [r7, #12] + 8008896: 061b lsls r3, r3, #24 + 8008898: 431a orrs r2, r3 + 800889a: 687b ldr r3, [r7, #4] + 800889c: 689b ldr r3, [r3, #8] + 800889e: 071b lsls r3, r3, #28 + 80088a0: 4957 ldr r1, [pc, #348] ; (8008a00 ) + 80088a2: 4313 orrs r3, r2 + 80088a4: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80088a8: 687b ldr r3, [r7, #4] + 80088aa: 681b ldr r3, [r3, #0] + 80088ac: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80088b0: 2b00 cmp r3, #0 + 80088b2: d004 beq.n 80088be + 80088b4: 687b ldr r3, [r7, #4] + 80088b6: 6bdb ldr r3, [r3, #60] ; 0x3c + 80088b8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80088bc: d00a beq.n 80088d4 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 80088be: 687b ldr r3, [r7, #4] + 80088c0: 681b ldr r3, [r3, #0] + 80088c2: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80088c6: 2b00 cmp r3, #0 + 80088c8: d02e beq.n 8008928 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 80088ca: 687b ldr r3, [r7, #4] + 80088cc: 6c1b ldr r3, [r3, #64] ; 0x40 + 80088ce: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80088d2: d129 bne.n 8008928 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 80088d4: 4b4a ldr r3, [pc, #296] ; (8008a00 ) + 80088d6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80088da: 0c1b lsrs r3, r3, #16 + 80088dc: f003 0303 and.w r3, r3, #3 + 80088e0: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 80088e2: 4b47 ldr r3, [pc, #284] ; (8008a00 ) + 80088e4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80088e8: 0f1b lsrs r3, r3, #28 + 80088ea: f003 0307 and.w r3, r3, #7 + 80088ee: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + 80088f0: 687b ldr r3, [r7, #4] + 80088f2: 685b ldr r3, [r3, #4] + 80088f4: 019a lsls r2, r3, #6 + 80088f6: 693b ldr r3, [r7, #16] + 80088f8: 041b lsls r3, r3, #16 + 80088fa: 431a orrs r2, r3 + 80088fc: 687b ldr r3, [r7, #4] + 80088fe: 68db ldr r3, [r3, #12] + 8008900: 061b lsls r3, r3, #24 + 8008902: 431a orrs r2, r3 + 8008904: 68fb ldr r3, [r7, #12] + 8008906: 071b lsls r3, r3, #28 + 8008908: 493d ldr r1, [pc, #244] ; (8008a00 ) + 800890a: 4313 orrs r3, r2 + 800890c: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 8008910: 4b3b ldr r3, [pc, #236] ; (8008a00 ) + 8008912: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008916: f023 021f bic.w r2, r3, #31 + 800891a: 687b ldr r3, [r7, #4] + 800891c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800891e: 3b01 subs r3, #1 + 8008920: 4937 ldr r1, [pc, #220] ; (8008a00 ) + 8008922: 4313 orrs r3, r2 + 8008924: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8008928: 687b ldr r3, [r7, #4] + 800892a: 681b ldr r3, [r3, #0] + 800892c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8008930: 2b00 cmp r3, #0 + 8008932: d01d beq.n 8008970 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 8008934: 4b32 ldr r3, [pc, #200] ; (8008a00 ) + 8008936: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800893a: 0e1b lsrs r3, r3, #24 + 800893c: f003 030f and.w r3, r3, #15 + 8008940: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 8008942: 4b2f ldr r3, [pc, #188] ; (8008a00 ) + 8008944: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8008948: 0f1b lsrs r3, r3, #28 + 800894a: f003 0307 and.w r3, r3, #7 + 800894e: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + 8008950: 687b ldr r3, [r7, #4] + 8008952: 685b ldr r3, [r3, #4] + 8008954: 019a lsls r2, r3, #6 + 8008956: 687b ldr r3, [r7, #4] + 8008958: 691b ldr r3, [r3, #16] + 800895a: 041b lsls r3, r3, #16 + 800895c: 431a orrs r2, r3 + 800895e: 693b ldr r3, [r7, #16] + 8008960: 061b lsls r3, r3, #24 + 8008962: 431a orrs r2, r3 + 8008964: 68fb ldr r3, [r7, #12] + 8008966: 071b lsls r3, r3, #28 + 8008968: 4925 ldr r1, [pc, #148] ; (8008a00 ) + 800896a: 4313 orrs r3, r2 + 800896c: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 8008970: 687b ldr r3, [r7, #4] + 8008972: 681b ldr r3, [r3, #0] + 8008974: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8008978: 2b00 cmp r3, #0 + 800897a: d011 beq.n 80089a0 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + 800897c: 687b ldr r3, [r7, #4] + 800897e: 685b ldr r3, [r3, #4] + 8008980: 019a lsls r2, r3, #6 + 8008982: 687b ldr r3, [r7, #4] + 8008984: 691b ldr r3, [r3, #16] + 8008986: 041b lsls r3, r3, #16 + 8008988: 431a orrs r2, r3 + 800898a: 687b ldr r3, [r7, #4] + 800898c: 68db ldr r3, [r3, #12] + 800898e: 061b lsls r3, r3, #24 + 8008990: 431a orrs r2, r3 + 8008992: 687b ldr r3, [r7, #4] + 8008994: 689b ldr r3, [r3, #8] + 8008996: 071b lsls r3, r3, #28 + 8008998: 4919 ldr r1, [pc, #100] ; (8008a00 ) + 800899a: 4313 orrs r3, r2 + 800899c: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 80089a0: 4b17 ldr r3, [pc, #92] ; (8008a00 ) + 80089a2: 681b ldr r3, [r3, #0] + 80089a4: 4a16 ldr r2, [pc, #88] ; (8008a00 ) + 80089a6: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80089aa: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80089ac: f7fb ff62 bl 8004874 + 80089b0: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80089b2: e008 b.n 80089c6 + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 80089b4: f7fb ff5e bl 8004874 + 80089b8: 4602 mov r2, r0 + 80089ba: 697b ldr r3, [r7, #20] + 80089bc: 1ad3 subs r3, r2, r3 + 80089be: 2b64 cmp r3, #100 ; 0x64 + 80089c0: d901 bls.n 80089c6 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80089c2: 2303 movs r3, #3 + 80089c4: e0d7 b.n 8008b76 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80089c6: 4b0e ldr r3, [pc, #56] ; (8008a00 ) + 80089c8: 681b ldr r3, [r3, #0] + 80089ca: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80089ce: 2b00 cmp r3, #0 + 80089d0: d0f0 beq.n 80089b4 + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + 80089d2: 69bb ldr r3, [r7, #24] + 80089d4: 2b01 cmp r3, #1 + 80089d6: f040 80cd bne.w 8008b74 + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + 80089da: 4b09 ldr r3, [pc, #36] ; (8008a00 ) + 80089dc: 681b ldr r3, [r3, #0] + 80089de: 4a08 ldr r2, [pc, #32] ; (8008a00 ) + 80089e0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80089e4: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80089e6: f7fb ff45 bl 8004874 + 80089ea: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 80089ec: e00a b.n 8008a04 + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 80089ee: f7fb ff41 bl 8004874 + 80089f2: 4602 mov r2, r0 + 80089f4: 697b ldr r3, [r7, #20] + 80089f6: 1ad3 subs r3, r2, r3 + 80089f8: 2b64 cmp r3, #100 ; 0x64 + 80089fa: d903 bls.n 8008a04 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80089fc: 2303 movs r3, #3 + 80089fe: e0ba b.n 8008b76 + 8008a00: 40023800 .word 0x40023800 + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8008a04: 4b5e ldr r3, [pc, #376] ; (8008b80 ) + 8008a06: 681b ldr r3, [r3, #0] + 8008a08: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8008a0c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8008a10: d0ed beq.n 80089ee + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8008a12: 687b ldr r3, [r7, #4] + 8008a14: 681b ldr r3, [r3, #0] + 8008a16: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8008a1a: 2b00 cmp r3, #0 + 8008a1c: d003 beq.n 8008a26 + 8008a1e: 687b ldr r3, [r7, #4] + 8008a20: 6bdb ldr r3, [r3, #60] ; 0x3c + 8008a22: 2b00 cmp r3, #0 + 8008a24: d009 beq.n 8008a3a + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 8008a26: 687b ldr r3, [r7, #4] + 8008a28: 681b ldr r3, [r3, #0] + 8008a2a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8008a2e: 2b00 cmp r3, #0 + 8008a30: d02e beq.n 8008a90 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 8008a32: 687b ldr r3, [r7, #4] + 8008a34: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008a36: 2b00 cmp r3, #0 + 8008a38: d12a bne.n 8008a90 + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8008a3a: 4b51 ldr r3, [pc, #324] ; (8008b80 ) + 8008a3c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008a40: 0c1b lsrs r3, r3, #16 + 8008a42: f003 0303 and.w r3, r3, #3 + 8008a46: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 8008a48: 4b4d ldr r3, [pc, #308] ; (8008b80 ) + 8008a4a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008a4e: 0f1b lsrs r3, r3, #28 + 8008a50: f003 0307 and.w r3, r3, #7 + 8008a54: 60fb str r3, [r7, #12] + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + 8008a56: 687b ldr r3, [r7, #4] + 8008a58: 695b ldr r3, [r3, #20] + 8008a5a: 019a lsls r2, r3, #6 + 8008a5c: 693b ldr r3, [r7, #16] + 8008a5e: 041b lsls r3, r3, #16 + 8008a60: 431a orrs r2, r3 + 8008a62: 687b ldr r3, [r7, #4] + 8008a64: 699b ldr r3, [r3, #24] + 8008a66: 061b lsls r3, r3, #24 + 8008a68: 431a orrs r2, r3 + 8008a6a: 68fb ldr r3, [r7, #12] + 8008a6c: 071b lsls r3, r3, #28 + 8008a6e: 4944 ldr r1, [pc, #272] ; (8008b80 ) + 8008a70: 4313 orrs r3, r2 + 8008a72: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 8008a76: 4b42 ldr r3, [pc, #264] ; (8008b80 ) + 8008a78: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008a7c: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 8008a80: 687b ldr r3, [r7, #4] + 8008a82: 6a9b ldr r3, [r3, #40] ; 0x28 + 8008a84: 3b01 subs r3, #1 + 8008a86: 021b lsls r3, r3, #8 + 8008a88: 493d ldr r1, [pc, #244] ; (8008b80 ) + 8008a8a: 4313 orrs r3, r2 + 8008a8c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + 8008a90: 687b ldr r3, [r7, #4] + 8008a92: 681b ldr r3, [r3, #0] + 8008a94: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8008a98: 2b00 cmp r3, #0 + 8008a9a: d022 beq.n 8008ae2 + 8008a9c: 687b ldr r3, [r7, #4] + 8008a9e: 6fdb ldr r3, [r3, #124] ; 0x7c + 8008aa0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8008aa4: d11d bne.n 8008ae2 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8008aa6: 4b36 ldr r3, [pc, #216] ; (8008b80 ) + 8008aa8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008aac: 0e1b lsrs r3, r3, #24 + 8008aae: f003 030f and.w r3, r3, #15 + 8008ab2: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 8008ab4: 4b32 ldr r3, [pc, #200] ; (8008b80 ) + 8008ab6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008aba: 0f1b lsrs r3, r3, #28 + 8008abc: f003 0307 and.w r3, r3, #7 + 8008ac0: 60fb str r3, [r7, #12] + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + 8008ac2: 687b ldr r3, [r7, #4] + 8008ac4: 695b ldr r3, [r3, #20] + 8008ac6: 019a lsls r2, r3, #6 + 8008ac8: 687b ldr r3, [r7, #4] + 8008aca: 6a1b ldr r3, [r3, #32] + 8008acc: 041b lsls r3, r3, #16 + 8008ace: 431a orrs r2, r3 + 8008ad0: 693b ldr r3, [r7, #16] + 8008ad2: 061b lsls r3, r3, #24 + 8008ad4: 431a orrs r2, r3 + 8008ad6: 68fb ldr r3, [r7, #12] + 8008ad8: 071b lsls r3, r3, #28 + 8008ada: 4929 ldr r1, [pc, #164] ; (8008b80 ) + 8008adc: 4313 orrs r3, r2 + 8008ade: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 8008ae2: 687b ldr r3, [r7, #4] + 8008ae4: 681b ldr r3, [r3, #0] + 8008ae6: f003 0308 and.w r3, r3, #8 + 8008aea: 2b00 cmp r3, #0 + 8008aec: d028 beq.n 8008b40 + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8008aee: 4b24 ldr r3, [pc, #144] ; (8008b80 ) + 8008af0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008af4: 0e1b lsrs r3, r3, #24 + 8008af6: f003 030f and.w r3, r3, #15 + 8008afa: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8008afc: 4b20 ldr r3, [pc, #128] ; (8008b80 ) + 8008afe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008b02: 0c1b lsrs r3, r3, #16 + 8008b04: f003 0303 and.w r3, r3, #3 + 8008b08: 60fb str r3, [r7, #12] + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + 8008b0a: 687b ldr r3, [r7, #4] + 8008b0c: 695b ldr r3, [r3, #20] + 8008b0e: 019a lsls r2, r3, #6 + 8008b10: 68fb ldr r3, [r7, #12] + 8008b12: 041b lsls r3, r3, #16 + 8008b14: 431a orrs r2, r3 + 8008b16: 693b ldr r3, [r7, #16] + 8008b18: 061b lsls r3, r3, #24 + 8008b1a: 431a orrs r2, r3 + 8008b1c: 687b ldr r3, [r7, #4] + 8008b1e: 69db ldr r3, [r3, #28] + 8008b20: 071b lsls r3, r3, #28 + 8008b22: 4917 ldr r1, [pc, #92] ; (8008b80 ) + 8008b24: 4313 orrs r3, r2 + 8008b26: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 8008b2a: 4b15 ldr r3, [pc, #84] ; (8008b80 ) + 8008b2c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008b30: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8008b34: 687b ldr r3, [r7, #4] + 8008b36: 6adb ldr r3, [r3, #44] ; 0x2c + 8008b38: 4911 ldr r1, [pc, #68] ; (8008b80 ) + 8008b3a: 4313 orrs r3, r2 + 8008b3c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + 8008b40: 4b0f ldr r3, [pc, #60] ; (8008b80 ) + 8008b42: 681b ldr r3, [r3, #0] + 8008b44: 4a0e ldr r2, [pc, #56] ; (8008b80 ) + 8008b46: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8008b4a: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8008b4c: f7fb fe92 bl 8004874 + 8008b50: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 8008b52: e008 b.n 8008b66 + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8008b54: f7fb fe8e bl 8004874 + 8008b58: 4602 mov r2, r0 + 8008b5a: 697b ldr r3, [r7, #20] + 8008b5c: 1ad3 subs r3, r2, r3 + 8008b5e: 2b64 cmp r3, #100 ; 0x64 + 8008b60: d901 bls.n 8008b66 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8008b62: 2303 movs r3, #3 + 8008b64: e007 b.n 8008b76 + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 8008b66: 4b06 ldr r3, [pc, #24] ; (8008b80 ) + 8008b68: 681b ldr r3, [r3, #0] + 8008b6a: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8008b6e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8008b72: d1ef bne.n 8008b54 + } + } + } + return HAL_OK; + 8008b74: 2300 movs r3, #0 +} + 8008b76: 4618 mov r0, r3 + 8008b78: 3720 adds r7, #32 + 8008b7a: 46bd mov sp, r7 + 8008b7c: bd80 pop {r7, pc} + 8008b7e: bf00 nop + 8008b80: 40023800 .word 0x40023800 + +08008b84 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 8008b84: b580 push {r7, lr} + 8008b86: b084 sub sp, #16 + 8008b88: af00 add r7, sp, #0 + 8008b8a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_ERROR; + 8008b8c: 2301 movs r3, #1 + 8008b8e: 73fb strb r3, [r7, #15] + + /* Check RTC handler validity */ + if (hrtc == NULL) + 8008b90: 687b ldr r3, [r7, #4] + 8008b92: 2b00 cmp r3, #0 + 8008b94: d101 bne.n 8008b9a + { + return HAL_ERROR; + 8008b96: 2301 movs r3, #1 + 8008b98: e071 b.n 8008c7e + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + if (hrtc->State == HAL_RTC_STATE_RESET) + 8008b9a: 687b ldr r3, [r7, #4] + 8008b9c: 7f5b ldrb r3, [r3, #29] + 8008b9e: b2db uxtb r3, r3 + 8008ba0: 2b00 cmp r3, #0 + 8008ba2: d105 bne.n 8008bb0 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8008ba4: 687b ldr r3, [r7, #4] + 8008ba6: 2200 movs r2, #0 + 8008ba8: 771a strb r2, [r3, #28] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 8008baa: 6878 ldr r0, [r7, #4] + 8008bac: f7fa f9dc bl 8002f68 + } +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 8008bb0: 687b ldr r3, [r7, #4] + 8008bb2: 2202 movs r2, #2 + 8008bb4: 775a strb r2, [r3, #29] + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 8008bb6: 687b ldr r3, [r7, #4] + 8008bb8: 681b ldr r3, [r3, #0] + 8008bba: 68db ldr r3, [r3, #12] + 8008bbc: f003 0310 and.w r3, r3, #16 + 8008bc0: 2b10 cmp r3, #16 + 8008bc2: d053 beq.n 8008c6c + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008bc4: 687b ldr r3, [r7, #4] + 8008bc6: 681b ldr r3, [r3, #0] + 8008bc8: 22ca movs r2, #202 ; 0xca + 8008bca: 625a str r2, [r3, #36] ; 0x24 + 8008bcc: 687b ldr r3, [r7, #4] + 8008bce: 681b ldr r3, [r3, #0] + 8008bd0: 2253 movs r2, #83 ; 0x53 + 8008bd2: 625a str r2, [r3, #36] ; 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8008bd4: 6878 ldr r0, [r7, #4] + 8008bd6: f000 fa4d bl 8009074 + 8008bda: 4603 mov r3, r0 + 8008bdc: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 8008bde: 7bfb ldrb r3, [r7, #15] + 8008be0: 2b00 cmp r3, #0 + 8008be2: d12a bne.n 8008c3a + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + 8008be4: 687b ldr r3, [r7, #4] + 8008be6: 681b ldr r3, [r3, #0] + 8008be8: 6899 ldr r1, [r3, #8] + 8008bea: 687b ldr r3, [r7, #4] + 8008bec: 681a ldr r2, [r3, #0] + 8008bee: 4b26 ldr r3, [pc, #152] ; (8008c88 ) + 8008bf0: 400b ands r3, r1 + 8008bf2: 6093 str r3, [r2, #8] + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + 8008bf4: 687b ldr r3, [r7, #4] + 8008bf6: 681b ldr r3, [r3, #0] + 8008bf8: 6899 ldr r1, [r3, #8] + 8008bfa: 687b ldr r3, [r7, #4] + 8008bfc: 685a ldr r2, [r3, #4] + 8008bfe: 687b ldr r3, [r7, #4] + 8008c00: 691b ldr r3, [r3, #16] + 8008c02: 431a orrs r2, r3 + 8008c04: 687b ldr r3, [r7, #4] + 8008c06: 695b ldr r3, [r3, #20] + 8008c08: 431a orrs r2, r3 + 8008c0a: 687b ldr r3, [r7, #4] + 8008c0c: 681b ldr r3, [r3, #0] + 8008c0e: 430a orrs r2, r1 + 8008c10: 609a str r2, [r3, #8] + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + 8008c12: 687b ldr r3, [r7, #4] + 8008c14: 681b ldr r3, [r3, #0] + 8008c16: 687a ldr r2, [r7, #4] + 8008c18: 68d2 ldr r2, [r2, #12] + 8008c1a: 611a str r2, [r3, #16] + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + 8008c1c: 687b ldr r3, [r7, #4] + 8008c1e: 681b ldr r3, [r3, #0] + 8008c20: 6919 ldr r1, [r3, #16] + 8008c22: 687b ldr r3, [r7, #4] + 8008c24: 689b ldr r3, [r3, #8] + 8008c26: 041a lsls r2, r3, #16 + 8008c28: 687b ldr r3, [r7, #4] + 8008c2a: 681b ldr r3, [r3, #0] + 8008c2c: 430a orrs r2, r1 + 8008c2e: 611a str r2, [r3, #16] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8008c30: 6878 ldr r0, [r7, #4] + 8008c32: f000 fa56 bl 80090e2 + 8008c36: 4603 mov r3, r0 + 8008c38: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 8008c3a: 7bfb ldrb r3, [r7, #15] + 8008c3c: 2b00 cmp r3, #0 + 8008c3e: d110 bne.n 8008c62 + { + hrtc->Instance->OR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; + 8008c40: 687b ldr r3, [r7, #4] + 8008c42: 681b ldr r3, [r3, #0] + 8008c44: 6cda ldr r2, [r3, #76] ; 0x4c + 8008c46: 687b ldr r3, [r7, #4] + 8008c48: 681b ldr r3, [r3, #0] + 8008c4a: f022 0208 bic.w r2, r2, #8 + 8008c4e: 64da str r2, [r3, #76] ; 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); + 8008c50: 687b ldr r3, [r7, #4] + 8008c52: 681b ldr r3, [r3, #0] + 8008c54: 6cd9 ldr r1, [r3, #76] ; 0x4c + 8008c56: 687b ldr r3, [r7, #4] + 8008c58: 699a ldr r2, [r3, #24] + 8008c5a: 687b ldr r3, [r7, #4] + 8008c5c: 681b ldr r3, [r3, #0] + 8008c5e: 430a orrs r2, r1 + 8008c60: 64da str r2, [r3, #76] ; 0x4c + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008c62: 687b ldr r3, [r7, #4] + 8008c64: 681b ldr r3, [r3, #0] + 8008c66: 22ff movs r2, #255 ; 0xff + 8008c68: 625a str r2, [r3, #36] ; 0x24 + 8008c6a: e001 b.n 8008c70 + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + 8008c6c: 2300 movs r3, #0 + 8008c6e: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 8008c70: 7bfb ldrb r3, [r7, #15] + 8008c72: 2b00 cmp r3, #0 + 8008c74: d102 bne.n 8008c7c + { + hrtc->State = HAL_RTC_STATE_READY; + 8008c76: 687b ldr r3, [r7, #4] + 8008c78: 2201 movs r2, #1 + 8008c7a: 775a strb r2, [r3, #29] + } + + return status; + 8008c7c: 7bfb ldrb r3, [r7, #15] +} + 8008c7e: 4618 mov r0, r3 + 8008c80: 3710 adds r7, #16 + 8008c82: 46bd mov sp, r7 + 8008c84: bd80 pop {r7, pc} + 8008c86: bf00 nop + 8008c88: ff8fffbf .word 0xff8fffbf + +08008c8c : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 8008c8c: b590 push {r4, r7, lr} + 8008c8e: b087 sub sp, #28 + 8008c90: af00 add r7, sp, #0 + 8008c92: 60f8 str r0, [r7, #12] + 8008c94: 60b9 str r1, [r7, #8] + 8008c96: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 8008c98: 2300 movs r3, #0 + 8008c9a: 617b str r3, [r7, #20] + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8008c9c: 68fb ldr r3, [r7, #12] + 8008c9e: 7f1b ldrb r3, [r3, #28] + 8008ca0: 2b01 cmp r3, #1 + 8008ca2: d101 bne.n 8008ca8 + 8008ca4: 2302 movs r3, #2 + 8008ca6: e085 b.n 8008db4 + 8008ca8: 68fb ldr r3, [r7, #12] + 8008caa: 2201 movs r2, #1 + 8008cac: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8008cae: 68fb ldr r3, [r7, #12] + 8008cb0: 2202 movs r2, #2 + 8008cb2: 775a strb r2, [r3, #29] + + if (Format == RTC_FORMAT_BIN) + 8008cb4: 687b ldr r3, [r7, #4] + 8008cb6: 2b00 cmp r3, #0 + 8008cb8: d126 bne.n 8008d08 + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 8008cba: 68fb ldr r3, [r7, #12] + 8008cbc: 681b ldr r3, [r3, #0] + 8008cbe: 689b ldr r3, [r3, #8] + 8008cc0: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008cc4: 2b00 cmp r3, #0 + 8008cc6: d102 bne.n 8008cce + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 8008cc8: 68bb ldr r3, [r7, #8] + 8008cca: 2200 movs r2, #0 + 8008ccc: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008cce: 68bb ldr r3, [r7, #8] + 8008cd0: 781b ldrb r3, [r3, #0] + 8008cd2: 4618 mov r0, r3 + 8008cd4: f000 fa2a bl 800912c + 8008cd8: 4603 mov r3, r0 + 8008cda: 041c lsls r4, r3, #16 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8008cdc: 68bb ldr r3, [r7, #8] + 8008cde: 785b ldrb r3, [r3, #1] + 8008ce0: 4618 mov r0, r3 + 8008ce2: f000 fa23 bl 800912c + 8008ce6: 4603 mov r3, r0 + 8008ce8: 021b lsls r3, r3, #8 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008cea: 431c orrs r4, r3 + ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 8008cec: 68bb ldr r3, [r7, #8] + 8008cee: 789b ldrb r3, [r3, #2] + 8008cf0: 4618 mov r0, r3 + 8008cf2: f000 fa1b bl 800912c + 8008cf6: 4603 mov r3, r0 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8008cf8: ea44 0203 orr.w r2, r4, r3 + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + 8008cfc: 68bb ldr r3, [r7, #8] + 8008cfe: 78db ldrb r3, [r3, #3] + 8008d00: 059b lsls r3, r3, #22 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008d02: 4313 orrs r3, r2 + 8008d04: 617b str r3, [r7, #20] + 8008d06: e018 b.n 8008d3a + } + else + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 8008d08: 68fb ldr r3, [r7, #12] + 8008d0a: 681b ldr r3, [r3, #0] + 8008d0c: 689b ldr r3, [r3, #8] + 8008d0e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008d12: 2b00 cmp r3, #0 + 8008d14: d102 bne.n 8008d1c + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 8008d16: 68bb ldr r3, [r7, #8] + 8008d18: 2200 movs r2, #0 + 8008d1a: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008d1c: 68bb ldr r3, [r7, #8] + 8008d1e: 781b ldrb r3, [r3, #0] + 8008d20: 041a lsls r2, r3, #16 + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8008d22: 68bb ldr r3, [r7, #8] + 8008d24: 785b ldrb r3, [r3, #1] + 8008d26: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008d28: 4313 orrs r3, r2 + ((uint32_t) sTime->Seconds) | \ + 8008d2a: 68ba ldr r2, [r7, #8] + 8008d2c: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8008d2e: 431a orrs r2, r3 + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + 8008d30: 68bb ldr r3, [r7, #8] + 8008d32: 78db ldrb r3, [r3, #3] + 8008d34: 059b lsls r3, r3, #22 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8008d36: 4313 orrs r3, r2 + 8008d38: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008d3a: 68fb ldr r3, [r7, #12] + 8008d3c: 681b ldr r3, [r3, #0] + 8008d3e: 22ca movs r2, #202 ; 0xca + 8008d40: 625a str r2, [r3, #36] ; 0x24 + 8008d42: 68fb ldr r3, [r7, #12] + 8008d44: 681b ldr r3, [r3, #0] + 8008d46: 2253 movs r2, #83 ; 0x53 + 8008d48: 625a str r2, [r3, #36] ; 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8008d4a: 68f8 ldr r0, [r7, #12] + 8008d4c: f000 f992 bl 8009074 + 8008d50: 4603 mov r3, r0 + 8008d52: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 8008d54: 7cfb ldrb r3, [r7, #19] + 8008d56: 2b00 cmp r3, #0 + 8008d58: d11e bne.n 8008d98 + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + 8008d5a: 68fb ldr r3, [r7, #12] + 8008d5c: 681a ldr r2, [r3, #0] + 8008d5e: 6979 ldr r1, [r7, #20] + 8008d60: 4b16 ldr r3, [pc, #88] ; (8008dbc ) + 8008d62: 400b ands r3, r1 + 8008d64: 6013 str r3, [r2, #0] + + /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; + 8008d66: 68fb ldr r3, [r7, #12] + 8008d68: 681b ldr r3, [r3, #0] + 8008d6a: 689a ldr r2, [r3, #8] + 8008d6c: 68fb ldr r3, [r7, #12] + 8008d6e: 681b ldr r3, [r3, #0] + 8008d70: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 8008d74: 609a str r2, [r3, #8] + + /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + 8008d76: 68fb ldr r3, [r7, #12] + 8008d78: 681b ldr r3, [r3, #0] + 8008d7a: 6899 ldr r1, [r3, #8] + 8008d7c: 68bb ldr r3, [r7, #8] + 8008d7e: 68da ldr r2, [r3, #12] + 8008d80: 68bb ldr r3, [r7, #8] + 8008d82: 691b ldr r3, [r3, #16] + 8008d84: 431a orrs r2, r3 + 8008d86: 68fb ldr r3, [r7, #12] + 8008d88: 681b ldr r3, [r3, #0] + 8008d8a: 430a orrs r2, r1 + 8008d8c: 609a str r2, [r3, #8] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8008d8e: 68f8 ldr r0, [r7, #12] + 8008d90: f000 f9a7 bl 80090e2 + 8008d94: 4603 mov r3, r0 + 8008d96: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8008d98: 7cfb ldrb r3, [r7, #19] + 8008d9a: 2b00 cmp r3, #0 + 8008d9c: d102 bne.n 8008da4 + { + hrtc->State = HAL_RTC_STATE_READY; + 8008d9e: 68fb ldr r3, [r7, #12] + 8008da0: 2201 movs r2, #1 + 8008da2: 775a strb r2, [r3, #29] + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008da4: 68fb ldr r3, [r7, #12] + 8008da6: 681b ldr r3, [r3, #0] + 8008da8: 22ff movs r2, #255 ; 0xff + 8008daa: 625a str r2, [r3, #36] ; 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008dac: 68fb ldr r3, [r7, #12] + 8008dae: 2200 movs r2, #0 + 8008db0: 771a strb r2, [r3, #28] + + return status; + 8008db2: 7cfb ldrb r3, [r7, #19] +} + 8008db4: 4618 mov r0, r3 + 8008db6: 371c adds r7, #28 + 8008db8: 46bd mov sp, r7 + 8008dba: bd90 pop {r4, r7, pc} + 8008dbc: 007f7f7f .word 0x007f7f7f + +08008dc0 : + * until current date is read to ensure consistency between the time and + * date values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 8008dc0: b580 push {r7, lr} + 8008dc2: b086 sub sp, #24 + 8008dc4: af00 add r7, sp, #0 + 8008dc6: 60f8 str r0, [r7, #12] + 8008dc8: 60b9 str r1, [r7, #8] + 8008dca: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 8008dcc: 2300 movs r3, #0 + 8008dce: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get subseconds value from the corresponding register */ + sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + 8008dd0: 68fb ldr r3, [r7, #12] + 8008dd2: 681b ldr r3, [r3, #0] + 8008dd4: 6a9a ldr r2, [r3, #40] ; 0x28 + 8008dd6: 68bb ldr r3, [r7, #8] + 8008dd8: 605a str r2, [r3, #4] + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + 8008dda: 68fb ldr r3, [r7, #12] + 8008ddc: 681b ldr r3, [r3, #0] + 8008dde: 691b ldr r3, [r3, #16] + 8008de0: f3c3 020e ubfx r2, r3, #0, #15 + 8008de4: 68bb ldr r3, [r7, #8] + 8008de6: 609a str r2, [r3, #8] + + /* Get the TR register */ + tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + 8008de8: 68fb ldr r3, [r7, #12] + 8008dea: 681b ldr r3, [r3, #0] + 8008dec: 681a ldr r2, [r3, #0] + 8008dee: 4b22 ldr r3, [pc, #136] ; (8008e78 ) + 8008df0: 4013 ands r3, r2 + 8008df2: 617b str r3, [r7, #20] + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + 8008df4: 697b ldr r3, [r7, #20] + 8008df6: 0c1b lsrs r3, r3, #16 + 8008df8: b2db uxtb r3, r3 + 8008dfa: f003 033f and.w r3, r3, #63 ; 0x3f + 8008dfe: b2da uxtb r2, r3 + 8008e00: 68bb ldr r3, [r7, #8] + 8008e02: 701a strb r2, [r3, #0] + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + 8008e04: 697b ldr r3, [r7, #20] + 8008e06: 0a1b lsrs r3, r3, #8 + 8008e08: b2db uxtb r3, r3 + 8008e0a: f003 037f and.w r3, r3, #127 ; 0x7f + 8008e0e: b2da uxtb r2, r3 + 8008e10: 68bb ldr r3, [r7, #8] + 8008e12: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU)); + 8008e14: 697b ldr r3, [r7, #20] + 8008e16: b2db uxtb r3, r3 + 8008e18: f003 037f and.w r3, r3, #127 ; 0x7f + 8008e1c: b2da uxtb r2, r3 + 8008e1e: 68bb ldr r3, [r7, #8] + 8008e20: 709a strb r2, [r3, #2] + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + 8008e22: 697b ldr r3, [r7, #20] + 8008e24: 0d9b lsrs r3, r3, #22 + 8008e26: b2db uxtb r3, r3 + 8008e28: f003 0301 and.w r3, r3, #1 + 8008e2c: b2da uxtb r2, r3 + 8008e2e: 68bb ldr r3, [r7, #8] + 8008e30: 70da strb r2, [r3, #3] + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + 8008e32: 687b ldr r3, [r7, #4] + 8008e34: 2b00 cmp r3, #0 + 8008e36: d11a bne.n 8008e6e + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + 8008e38: 68bb ldr r3, [r7, #8] + 8008e3a: 781b ldrb r3, [r3, #0] + 8008e3c: 4618 mov r0, r3 + 8008e3e: f000 f993 bl 8009168 + 8008e42: 4603 mov r3, r0 + 8008e44: 461a mov r2, r3 + 8008e46: 68bb ldr r3, [r7, #8] + 8008e48: 701a strb r2, [r3, #0] + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + 8008e4a: 68bb ldr r3, [r7, #8] + 8008e4c: 785b ldrb r3, [r3, #1] + 8008e4e: 4618 mov r0, r3 + 8008e50: f000 f98a bl 8009168 + 8008e54: 4603 mov r3, r0 + 8008e56: 461a mov r2, r3 + 8008e58: 68bb ldr r3, [r7, #8] + 8008e5a: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + 8008e5c: 68bb ldr r3, [r7, #8] + 8008e5e: 789b ldrb r3, [r3, #2] + 8008e60: 4618 mov r0, r3 + 8008e62: f000 f981 bl 8009168 + 8008e66: 4603 mov r3, r0 + 8008e68: 461a mov r2, r3 + 8008e6a: 68bb ldr r3, [r7, #8] + 8008e6c: 709a strb r2, [r3, #2] + } + + return HAL_OK; + 8008e6e: 2300 movs r3, #0 +} + 8008e70: 4618 mov r0, r3 + 8008e72: 3718 adds r7, #24 + 8008e74: 46bd mov sp, r7 + 8008e76: bd80 pop {r7, pc} + 8008e78: 007f7f7f .word 0x007f7f7f + +08008e7c : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 8008e7c: b590 push {r4, r7, lr} + 8008e7e: b087 sub sp, #28 + 8008e80: af00 add r7, sp, #0 + 8008e82: 60f8 str r0, [r7, #12] + 8008e84: 60b9 str r1, [r7, #8] + 8008e86: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8008e88: 2300 movs r3, #0 + 8008e8a: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8008e8c: 68fb ldr r3, [r7, #12] + 8008e8e: 7f1b ldrb r3, [r3, #28] + 8008e90: 2b01 cmp r3, #1 + 8008e92: d101 bne.n 8008e98 + 8008e94: 2302 movs r3, #2 + 8008e96: e06f b.n 8008f78 + 8008e98: 68fb ldr r3, [r7, #12] + 8008e9a: 2201 movs r2, #1 + 8008e9c: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8008e9e: 68fb ldr r3, [r7, #12] + 8008ea0: 2202 movs r2, #2 + 8008ea2: 775a strb r2, [r3, #29] + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 8008ea4: 687b ldr r3, [r7, #4] + 8008ea6: 2b00 cmp r3, #0 + 8008ea8: d10e bne.n 8008ec8 + 8008eaa: 68bb ldr r3, [r7, #8] + 8008eac: 785b ldrb r3, [r3, #1] + 8008eae: f003 0310 and.w r3, r3, #16 + 8008eb2: 2b00 cmp r3, #0 + 8008eb4: d008 beq.n 8008ec8 + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + 8008eb6: 68bb ldr r3, [r7, #8] + 8008eb8: 785b ldrb r3, [r3, #1] + 8008eba: f023 0310 bic.w r3, r3, #16 + 8008ebe: b2db uxtb r3, r3 + 8008ec0: 330a adds r3, #10 + 8008ec2: b2da uxtb r2, r3 + 8008ec4: 68bb ldr r3, [r7, #8] + 8008ec6: 705a strb r2, [r3, #1] + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + 8008ec8: 687b ldr r3, [r7, #4] + 8008eca: 2b00 cmp r3, #0 + 8008ecc: d11c bne.n 8008f08 + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8008ece: 68bb ldr r3, [r7, #8] + 8008ed0: 78db ldrb r3, [r3, #3] + 8008ed2: 4618 mov r0, r3 + 8008ed4: f000 f92a bl 800912c + 8008ed8: 4603 mov r3, r0 + 8008eda: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8008edc: 68bb ldr r3, [r7, #8] + 8008ede: 785b ldrb r3, [r3, #1] + 8008ee0: 4618 mov r0, r3 + 8008ee2: f000 f923 bl 800912c + 8008ee6: 4603 mov r3, r0 + 8008ee8: 021b lsls r3, r3, #8 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8008eea: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 8008eec: 68bb ldr r3, [r7, #8] + 8008eee: 789b ldrb r3, [r3, #2] + 8008ef0: 4618 mov r0, r3 + 8008ef2: f000 f91b bl 800912c + 8008ef6: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8008ef8: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + 8008efc: 68bb ldr r3, [r7, #8] + 8008efe: 781b ldrb r3, [r3, #0] + 8008f00: 035b lsls r3, r3, #13 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8008f02: 4313 orrs r3, r2 + 8008f04: 617b str r3, [r7, #20] + 8008f06: e00e b.n 8008f26 + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8008f08: 68bb ldr r3, [r7, #8] + 8008f0a: 78db ldrb r3, [r3, #3] + 8008f0c: 041a lsls r2, r3, #16 + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8008f0e: 68bb ldr r3, [r7, #8] + 8008f10: 785b ldrb r3, [r3, #1] + 8008f12: 021b lsls r3, r3, #8 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8008f14: 4313 orrs r3, r2 + ((uint32_t) sDate->Date) | \ + 8008f16: 68ba ldr r2, [r7, #8] + 8008f18: 7892 ldrb r2, [r2, #2] + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8008f1a: 431a orrs r2, r3 + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + 8008f1c: 68bb ldr r3, [r7, #8] + 8008f1e: 781b ldrb r3, [r3, #0] + 8008f20: 035b lsls r3, r3, #13 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8008f22: 4313 orrs r3, r2 + 8008f24: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008f26: 68fb ldr r3, [r7, #12] + 8008f28: 681b ldr r3, [r3, #0] + 8008f2a: 22ca movs r2, #202 ; 0xca + 8008f2c: 625a str r2, [r3, #36] ; 0x24 + 8008f2e: 68fb ldr r3, [r7, #12] + 8008f30: 681b ldr r3, [r3, #0] + 8008f32: 2253 movs r2, #83 ; 0x53 + 8008f34: 625a str r2, [r3, #36] ; 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8008f36: 68f8 ldr r0, [r7, #12] + 8008f38: f000 f89c bl 8009074 + 8008f3c: 4603 mov r3, r0 + 8008f3e: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 8008f40: 7cfb ldrb r3, [r7, #19] + 8008f42: 2b00 cmp r3, #0 + 8008f44: d10a bne.n 8008f5c + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + 8008f46: 68fb ldr r3, [r7, #12] + 8008f48: 681a ldr r2, [r3, #0] + 8008f4a: 6979 ldr r1, [r7, #20] + 8008f4c: 4b0c ldr r3, [pc, #48] ; (8008f80 ) + 8008f4e: 400b ands r3, r1 + 8008f50: 6053 str r3, [r2, #4] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8008f52: 68f8 ldr r0, [r7, #12] + 8008f54: f000 f8c5 bl 80090e2 + 8008f58: 4603 mov r3, r0 + 8008f5a: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8008f5c: 7cfb ldrb r3, [r7, #19] + 8008f5e: 2b00 cmp r3, #0 + 8008f60: d102 bne.n 8008f68 + { + hrtc->State = HAL_RTC_STATE_READY; + 8008f62: 68fb ldr r3, [r7, #12] + 8008f64: 2201 movs r2, #1 + 8008f66: 775a strb r2, [r3, #29] + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008f68: 68fb ldr r3, [r7, #12] + 8008f6a: 681b ldr r3, [r3, #0] + 8008f6c: 22ff movs r2, #255 ; 0xff + 8008f6e: 625a str r2, [r3, #36] ; 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008f70: 68fb ldr r3, [r7, #12] + 8008f72: 2200 movs r2, #0 + 8008f74: 771a strb r2, [r3, #28] + + return status; + 8008f76: 7cfb ldrb r3, [r7, #19] +} + 8008f78: 4618 mov r0, r3 + 8008f7a: 371c adds r7, #28 + 8008f7c: 46bd mov sp, r7 + 8008f7e: bd90 pop {r4, r7, pc} + 8008f80: 00ffff3f .word 0x00ffff3f + +08008f84 : + * until current date is read to ensure consistency between the time and + * date values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 8008f84: b580 push {r7, lr} + 8008f86: b086 sub sp, #24 + 8008f88: af00 add r7, sp, #0 + 8008f8a: 60f8 str r0, [r7, #12] + 8008f8c: 60b9 str r1, [r7, #8] + 8008f8e: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8008f90: 2300 movs r3, #0 + 8008f92: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + 8008f94: 68fb ldr r3, [r7, #12] + 8008f96: 681b ldr r3, [r3, #0] + 8008f98: 685a ldr r2, [r3, #4] + 8008f9a: 4b21 ldr r3, [pc, #132] ; (8009020 ) + 8008f9c: 4013 ands r3, r2 + 8008f9e: 617b str r3, [r7, #20] + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + 8008fa0: 697b ldr r3, [r7, #20] + 8008fa2: 0c1b lsrs r3, r3, #16 + 8008fa4: b2da uxtb r2, r3 + 8008fa6: 68bb ldr r3, [r7, #8] + 8008fa8: 70da strb r2, [r3, #3] + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + 8008faa: 697b ldr r3, [r7, #20] + 8008fac: 0a1b lsrs r3, r3, #8 + 8008fae: b2db uxtb r3, r3 + 8008fb0: f003 031f and.w r3, r3, #31 + 8008fb4: b2da uxtb r2, r3 + 8008fb6: 68bb ldr r3, [r7, #8] + 8008fb8: 705a strb r2, [r3, #1] + sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + 8008fba: 697b ldr r3, [r7, #20] + 8008fbc: b2db uxtb r3, r3 + 8008fbe: f003 033f and.w r3, r3, #63 ; 0x3f + 8008fc2: b2da uxtb r2, r3 + 8008fc4: 68bb ldr r3, [r7, #8] + 8008fc6: 709a strb r2, [r3, #2] + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + 8008fc8: 697b ldr r3, [r7, #20] + 8008fca: 0b5b lsrs r3, r3, #13 + 8008fcc: b2db uxtb r3, r3 + 8008fce: f003 0307 and.w r3, r3, #7 + 8008fd2: b2da uxtb r2, r3 + 8008fd4: 68bb ldr r3, [r7, #8] + 8008fd6: 701a strb r2, [r3, #0] + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + 8008fd8: 687b ldr r3, [r7, #4] + 8008fda: 2b00 cmp r3, #0 + 8008fdc: d11a bne.n 8009014 + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + 8008fde: 68bb ldr r3, [r7, #8] + 8008fe0: 78db ldrb r3, [r3, #3] + 8008fe2: 4618 mov r0, r3 + 8008fe4: f000 f8c0 bl 8009168 + 8008fe8: 4603 mov r3, r0 + 8008fea: 461a mov r2, r3 + 8008fec: 68bb ldr r3, [r7, #8] + 8008fee: 70da strb r2, [r3, #3] + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + 8008ff0: 68bb ldr r3, [r7, #8] + 8008ff2: 785b ldrb r3, [r3, #1] + 8008ff4: 4618 mov r0, r3 + 8008ff6: f000 f8b7 bl 8009168 + 8008ffa: 4603 mov r3, r0 + 8008ffc: 461a mov r2, r3 + 8008ffe: 68bb ldr r3, [r7, #8] + 8009000: 705a strb r2, [r3, #1] + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + 8009002: 68bb ldr r3, [r7, #8] + 8009004: 789b ldrb r3, [r3, #2] + 8009006: 4618 mov r0, r3 + 8009008: f000 f8ae bl 8009168 + 800900c: 4603 mov r3, r0 + 800900e: 461a mov r2, r3 + 8009010: 68bb ldr r3, [r7, #8] + 8009012: 709a strb r2, [r3, #2] + } + return HAL_OK; + 8009014: 2300 movs r3, #0 +} + 8009016: 4618 mov r0, r3 + 8009018: 3718 adds r7, #24 + 800901a: 46bd mov sp, r7 + 800901c: bd80 pop {r7, pc} + 800901e: bf00 nop + 8009020: 00ffff3f .word 0x00ffff3f + +08009024 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 8009024: b580 push {r7, lr} + 8009026: b084 sub sp, #16 + 8009028: af00 add r7, sp, #0 + 800902a: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800902c: 2300 movs r3, #0 + 800902e: 60fb str r3, [r7, #12] + + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + 8009030: 687b ldr r3, [r7, #4] + 8009032: 681b ldr r3, [r3, #0] + 8009034: 68da ldr r2, [r3, #12] + 8009036: 687b ldr r3, [r7, #4] + 8009038: 681b ldr r3, [r3, #0] + 800903a: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 800903e: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8009040: f7fb fc18 bl 8004874 + 8009044: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 8009046: e009 b.n 800905c + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8009048: f7fb fc14 bl 8004874 + 800904c: 4602 mov r2, r0 + 800904e: 68fb ldr r3, [r7, #12] + 8009050: 1ad3 subs r3, r2, r3 + 8009052: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8009056: d901 bls.n 800905c + { + return HAL_TIMEOUT; + 8009058: 2303 movs r3, #3 + 800905a: e007 b.n 800906c + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 800905c: 687b ldr r3, [r7, #4] + 800905e: 681b ldr r3, [r3, #0] + 8009060: 68db ldr r3, [r3, #12] + 8009062: f003 0320 and.w r3, r3, #32 + 8009066: 2b00 cmp r3, #0 + 8009068: d0ee beq.n 8009048 + } + } + + return HAL_OK; + 800906a: 2300 movs r3, #0 +} + 800906c: 4618 mov r0, r3 + 800906e: 3710 adds r7, #16 + 8009070: 46bd mov sp, r7 + 8009072: bd80 pop {r7, pc} + +08009074 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 8009074: b580 push {r7, lr} + 8009076: b084 sub sp, #16 + 8009078: af00 add r7, sp, #0 + 800907a: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800907c: 2300 movs r3, #0 + 800907e: 60bb str r3, [r7, #8] + HAL_StatusTypeDef status = HAL_OK; + 8009080: 2300 movs r3, #0 + 8009082: 73fb strb r3, [r7, #15] + + /* Check that Initialization mode is not already set */ + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) + 8009084: 687b ldr r3, [r7, #4] + 8009086: 681b ldr r3, [r3, #0] + 8009088: 68db ldr r3, [r3, #12] + 800908a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800908e: 2b00 cmp r3, #0 + 8009090: d122 bne.n 80090d8 + { + /* Set INIT bit to enter Initialization mode */ + SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 8009092: 687b ldr r3, [r7, #4] + 8009094: 681b ldr r3, [r3, #0] + 8009096: 68da ldr r2, [r3, #12] + 8009098: 687b ldr r3, [r7, #4] + 800909a: 681b ldr r3, [r3, #0] + 800909c: f042 0280 orr.w r2, r2, #128 ; 0x80 + 80090a0: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80090a2: f7fb fbe7 bl 8004874 + 80090a6: 60b8 str r0, [r7, #8] + + /* Wait till RTC is in INIT state and if timeout is reached exit */ + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 80090a8: e00c b.n 80090c4 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80090aa: f7fb fbe3 bl 8004874 + 80090ae: 4602 mov r2, r0 + 80090b0: 68bb ldr r3, [r7, #8] + 80090b2: 1ad3 subs r3, r2, r3 + 80090b4: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 80090b8: d904 bls.n 80090c4 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80090ba: 687b ldr r3, [r7, #4] + 80090bc: 2204 movs r2, #4 + 80090be: 775a strb r2, [r3, #29] + status = HAL_ERROR; + 80090c0: 2301 movs r3, #1 + 80090c2: 73fb strb r3, [r7, #15] + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 80090c4: 687b ldr r3, [r7, #4] + 80090c6: 681b ldr r3, [r3, #0] + 80090c8: 68db ldr r3, [r3, #12] + 80090ca: f003 0340 and.w r3, r3, #64 ; 0x40 + 80090ce: 2b00 cmp r3, #0 + 80090d0: d102 bne.n 80090d8 + 80090d2: 7bfb ldrb r3, [r7, #15] + 80090d4: 2b01 cmp r3, #1 + 80090d6: d1e8 bne.n 80090aa + } + } + } + + return status; + 80090d8: 7bfb ldrb r3, [r7, #15] +} + 80090da: 4618 mov r0, r3 + 80090dc: 3710 adds r7, #16 + 80090de: 46bd mov sp, r7 + 80090e0: bd80 pop {r7, pc} + +080090e2 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 80090e2: b580 push {r7, lr} + 80090e4: b084 sub sp, #16 + 80090e6: af00 add r7, sp, #0 + 80090e8: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80090ea: 2300 movs r3, #0 + 80090ec: 73fb strb r3, [r7, #15] + + /* Clear INIT bit to exit Initialization mode */ + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 80090ee: 687b ldr r3, [r7, #4] + 80090f0: 681b ldr r3, [r3, #0] + 80090f2: 68da ldr r2, [r3, #12] + 80090f4: 687b ldr r3, [r7, #4] + 80090f6: 681b ldr r3, [r3, #0] + 80090f8: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80090fc: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) + 80090fe: 687b ldr r3, [r7, #4] + 8009100: 681b ldr r3, [r3, #0] + 8009102: 689b ldr r3, [r3, #8] + 8009104: f003 0320 and.w r3, r3, #32 + 8009108: 2b00 cmp r3, #0 + 800910a: d10a bne.n 8009122 + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 800910c: 6878 ldr r0, [r7, #4] + 800910e: f7ff ff89 bl 8009024 + 8009112: 4603 mov r3, r0 + 8009114: 2b00 cmp r3, #0 + 8009116: d004 beq.n 8009122 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8009118: 687b ldr r3, [r7, #4] + 800911a: 2204 movs r2, #4 + 800911c: 775a strb r2, [r3, #29] + status = HAL_ERROR; + 800911e: 2301 movs r3, #1 + 8009120: 73fb strb r3, [r7, #15] + } + } + + return status; + 8009122: 7bfb ldrb r3, [r7, #15] +} + 8009124: 4618 mov r0, r3 + 8009126: 3710 adds r7, #16 + 8009128: 46bd mov sp, r7 + 800912a: bd80 pop {r7, pc} + +0800912c : + * @brief Converts a 2-digit number from decimal to BCD format. + * @param number decimal-formatted number (from 0 to 99) to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t number) +{ + 800912c: b480 push {r7} + 800912e: b085 sub sp, #20 + 8009130: af00 add r7, sp, #0 + 8009132: 4603 mov r3, r0 + 8009134: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 8009136: 2300 movs r3, #0 + 8009138: 60fb str r3, [r7, #12] + + while (number >= 10U) + 800913a: e005 b.n 8009148 + { + bcdhigh++; + 800913c: 68fb ldr r3, [r7, #12] + 800913e: 3301 adds r3, #1 + 8009140: 60fb str r3, [r7, #12] + number -= 10U; + 8009142: 79fb ldrb r3, [r7, #7] + 8009144: 3b0a subs r3, #10 + 8009146: 71fb strb r3, [r7, #7] + while (number >= 10U) + 8009148: 79fb ldrb r3, [r7, #7] + 800914a: 2b09 cmp r3, #9 + 800914c: d8f6 bhi.n 800913c + } + + return ((uint8_t)(bcdhigh << 4U) | number); + 800914e: 68fb ldr r3, [r7, #12] + 8009150: b2db uxtb r3, r3 + 8009152: 011b lsls r3, r3, #4 + 8009154: b2da uxtb r2, r3 + 8009156: 79fb ldrb r3, [r7, #7] + 8009158: 4313 orrs r3, r2 + 800915a: b2db uxtb r3, r3 +} + 800915c: 4618 mov r0, r3 + 800915e: 3714 adds r7, #20 + 8009160: 46bd mov sp, r7 + 8009162: f85d 7b04 ldr.w r7, [sp], #4 + 8009166: 4770 bx lr + +08009168 : + * @brief Converts a 2-digit number from BCD to decimal format. + * @param number BCD-formatted number (from 00 to 99) to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t number) +{ + 8009168: b480 push {r7} + 800916a: b085 sub sp, #20 + 800916c: af00 add r7, sp, #0 + 800916e: 4603 mov r3, r0 + 8009170: 71fb strb r3, [r7, #7] + uint32_t tens = 0U; + 8009172: 2300 movs r3, #0 + 8009174: 60fb str r3, [r7, #12] + tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U; + 8009176: 79fb ldrb r3, [r7, #7] + 8009178: 091b lsrs r3, r3, #4 + 800917a: b2db uxtb r3, r3 + 800917c: 461a mov r2, r3 + 800917e: 4613 mov r3, r2 + 8009180: 009b lsls r3, r3, #2 + 8009182: 4413 add r3, r2 + 8009184: 005b lsls r3, r3, #1 + 8009186: 60fb str r3, [r7, #12] + return (uint8_t)(tens + ((uint32_t)number & 0x0FU)); + 8009188: 68fb ldr r3, [r7, #12] + 800918a: b2da uxtb r2, r3 + 800918c: 79fb ldrb r3, [r7, #7] + 800918e: f003 030f and.w r3, r3, #15 + 8009192: b2db uxtb r3, r3 + 8009194: 4413 add r3, r2 + 8009196: b2db uxtb r3, r3 +} + 8009198: 4618 mov r0, r3 + 800919a: 3714 adds r7, #20 + 800919c: 46bd mov sp, r7 + 800919e: f85d 7b04 ldr.w r7, [sp], #4 + 80091a2: 4770 bx lr + +080091a4 : + * to specify the register. + * @param Data Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + 80091a4: b480 push {r7} + 80091a6: b087 sub sp, #28 + 80091a8: af00 add r7, sp, #0 + 80091aa: 60f8 str r0, [r7, #12] + 80091ac: 60b9 str r1, [r7, #8] + 80091ae: 607a str r2, [r7, #4] + uint32_t tmp = 0U; + 80091b0: 2300 movs r3, #0 + 80091b2: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (hrtc->Instance->BKP0R); + 80091b4: 68fb ldr r3, [r7, #12] + 80091b6: 681b ldr r3, [r3, #0] + 80091b8: 3350 adds r3, #80 ; 0x50 + 80091ba: 617b str r3, [r7, #20] + tmp += (BackupRegister * 4U); + 80091bc: 68bb ldr r3, [r7, #8] + 80091be: 009b lsls r3, r3, #2 + 80091c0: 697a ldr r2, [r7, #20] + 80091c2: 4413 add r3, r2 + 80091c4: 617b str r3, [r7, #20] + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; + 80091c6: 697b ldr r3, [r7, #20] + 80091c8: 687a ldr r2, [r7, #4] + 80091ca: 601a str r2, [r3, #0] +} + 80091cc: bf00 nop + 80091ce: 371c adds r7, #28 + 80091d0: 46bd mov sp, r7 + 80091d2: f85d 7b04 ldr.w r7, [sp], #4 + 80091d6: 4770 bx lr + +080091d8 : + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + 80091d8: b580 push {r7, lr} + 80091da: b082 sub sp, #8 + 80091dc: af00 add r7, sp, #0 + 80091de: 6078 str r0, [r7, #4] + 80091e0: 6039 str r1, [r7, #0] + /* Check the SDRAM handle parameter */ + if (hsdram == NULL) + 80091e2: 687b ldr r3, [r7, #4] + 80091e4: 2b00 cmp r3, #0 + 80091e6: d101 bne.n 80091ec + { + return HAL_ERROR; + 80091e8: 2301 movs r3, #1 + 80091ea: e025 b.n 8009238 + } + + if (hsdram->State == HAL_SDRAM_STATE_RESET) + 80091ec: 687b ldr r3, [r7, #4] + 80091ee: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 80091f2: b2db uxtb r3, r3 + 80091f4: 2b00 cmp r3, #0 + 80091f6: d106 bne.n 8009206 + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; + 80091f8: 687b ldr r3, [r7, #4] + 80091fa: 2200 movs r2, #0 + 80091fc: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); + 8009200: 6878 ldr r0, [r7, #4] + 8009202: f7f9 ffe1 bl 80031c8 +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 8009206: 687b ldr r3, [r7, #4] + 8009208: 2202 movs r2, #2 + 800920a: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Initialize SDRAM control Interface */ + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + 800920e: 687b ldr r3, [r7, #4] + 8009210: 681a ldr r2, [r3, #0] + 8009212: 687b ldr r3, [r7, #4] + 8009214: 3304 adds r3, #4 + 8009216: 4619 mov r1, r3 + 8009218: 4610 mov r0, r2 + 800921a: f001 f8e7 bl 800a3ec + + /* Initialize SDRAM timing Interface */ + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + 800921e: 687b ldr r3, [r7, #4] + 8009220: 6818 ldr r0, [r3, #0] + 8009222: 687b ldr r3, [r7, #4] + 8009224: 685b ldr r3, [r3, #4] + 8009226: 461a mov r2, r3 + 8009228: 6839 ldr r1, [r7, #0] + 800922a: f001 f93b bl 800a4a4 + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + 800922e: 687b ldr r3, [r7, #4] + 8009230: 2201 movs r2, #1 + 8009232: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8009236: 2300 movs r3, #0 +} + 8009238: 4618 mov r0, r3 + 800923a: 3708 adds r7, #8 + 800923c: 46bd mov sp, r7 + 800923e: bd80 pop {r7, pc} + +08009240 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) +{ + 8009240: b580 push {r7, lr} + 8009242: b086 sub sp, #24 + 8009244: af00 add r7, sp, #0 + 8009246: 60f8 str r0, [r7, #12] + 8009248: 60b9 str r1, [r7, #8] + 800924a: 607a str r2, [r7, #4] + HAL_SDRAM_StateTypeDef state = hsdram->State; + 800924c: 68fb ldr r3, [r7, #12] + 800924e: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8009252: 75fb strb r3, [r7, #23] + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + 8009254: 7dfb ldrb r3, [r7, #23] + 8009256: 2b02 cmp r3, #2 + 8009258: d101 bne.n 800925e + { + return HAL_BUSY; + 800925a: 2302 movs r3, #2 + 800925c: e021 b.n 80092a2 + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + 800925e: 7dfb ldrb r3, [r7, #23] + 8009260: 2b01 cmp r3, #1 + 8009262: d002 beq.n 800926a + 8009264: 7dfb ldrb r3, [r7, #23] + 8009266: 2b05 cmp r3, #5 + 8009268: d118 bne.n 800929c + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 800926a: 68fb ldr r3, [r7, #12] + 800926c: 2202 movs r2, #2 + 800926e: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + 8009272: 68fb ldr r3, [r7, #12] + 8009274: 681b ldr r3, [r3, #0] + 8009276: 687a ldr r2, [r7, #4] + 8009278: 68b9 ldr r1, [r7, #8] + 800927a: 4618 mov r0, r3 + 800927c: f001 f97c bl 800a578 + + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + 8009280: 68bb ldr r3, [r7, #8] + 8009282: 681b ldr r3, [r3, #0] + 8009284: 2b02 cmp r3, #2 + 8009286: d104 bne.n 8009292 + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + 8009288: 68fb ldr r3, [r7, #12] + 800928a: 2205 movs r2, #5 + 800928c: f883 202c strb.w r2, [r3, #44] ; 0x2c + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + 8009290: e006 b.n 80092a0 + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + 8009292: 68fb ldr r3, [r7, #12] + 8009294: 2201 movs r2, #1 + 8009296: f883 202c strb.w r2, [r3, #44] ; 0x2c + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + 800929a: e001 b.n 80092a0 + } + } + else + { + return HAL_ERROR; + 800929c: 2301 movs r3, #1 + 800929e: e000 b.n 80092a2 + } + + return HAL_OK; + 80092a0: 2300 movs r3, #0 +} + 80092a2: 4618 mov r0, r3 + 80092a4: 3718 adds r7, #24 + 80092a6: 46bd mov sp, r7 + 80092a8: bd80 pop {r7, pc} + +080092aa : + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + 80092aa: b580 push {r7, lr} + 80092ac: b082 sub sp, #8 + 80092ae: af00 add r7, sp, #0 + 80092b0: 6078 str r0, [r7, #4] + 80092b2: 6039 str r1, [r7, #0] + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + 80092b4: 687b ldr r3, [r7, #4] + 80092b6: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 80092ba: b2db uxtb r3, r3 + 80092bc: 2b02 cmp r3, #2 + 80092be: d101 bne.n 80092c4 + { + return HAL_BUSY; + 80092c0: 2302 movs r3, #2 + 80092c2: e016 b.n 80092f2 + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + 80092c4: 687b ldr r3, [r7, #4] + 80092c6: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 80092ca: b2db uxtb r3, r3 + 80092cc: 2b01 cmp r3, #1 + 80092ce: d10f bne.n 80092f0 + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 80092d0: 687b ldr r3, [r7, #4] + 80092d2: 2202 movs r2, #2 + 80092d4: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); + 80092d8: 687b ldr r3, [r7, #4] + 80092da: 681b ldr r3, [r3, #0] + 80092dc: 6839 ldr r1, [r7, #0] + 80092de: 4618 mov r0, r3 + 80092e0: f001 f96e bl 800a5c0 + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + 80092e4: 687b ldr r3, [r7, #4] + 80092e6: 2201 movs r2, #1 + 80092e8: f883 202c strb.w r2, [r3, #44] ; 0x2c + else + { + return HAL_ERROR; + } + + return HAL_OK; + 80092ec: 2300 movs r3, #0 + 80092ee: e000 b.n 80092f2 + return HAL_ERROR; + 80092f0: 2301 movs r3, #1 +} + 80092f2: 4618 mov r0, r3 + 80092f4: 3708 adds r7, #8 + 80092f6: 46bd mov sp, r7 + 80092f8: bd80 pop {r7, pc} + +080092fa : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80092fa: b580 push {r7, lr} + 80092fc: b082 sub sp, #8 + 80092fe: af00 add r7, sp, #0 + 8009300: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8009302: 687b ldr r3, [r7, #4] + 8009304: 2b00 cmp r3, #0 + 8009306: d101 bne.n 800930c + { + return HAL_ERROR; + 8009308: 2301 movs r3, #1 + 800930a: e049 b.n 80093a0 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800930c: 687b ldr r3, [r7, #4] + 800930e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8009312: b2db uxtb r3, r3 + 8009314: 2b00 cmp r3, #0 + 8009316: d106 bne.n 8009326 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8009318: 687b ldr r3, [r7, #4] + 800931a: 2200 movs r2, #0 + 800931c: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8009320: 6878 ldr r0, [r7, #4] + 8009322: f000 f841 bl 80093a8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8009326: 687b ldr r3, [r7, #4] + 8009328: 2202 movs r2, #2 + 800932a: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800932e: 687b ldr r3, [r7, #4] + 8009330: 681a ldr r2, [r3, #0] + 8009332: 687b ldr r3, [r7, #4] + 8009334: 3304 adds r3, #4 + 8009336: 4619 mov r1, r3 + 8009338: 4610 mov r0, r2 + 800933a: f000 f9ff bl 800973c + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 800933e: 687b ldr r3, [r7, #4] + 8009340: 2201 movs r2, #1 + 8009342: f883 2048 strb.w r2, [r3, #72] ; 0x48 + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8009346: 687b ldr r3, [r7, #4] + 8009348: 2201 movs r2, #1 + 800934a: f883 203e strb.w r2, [r3, #62] ; 0x3e + 800934e: 687b ldr r3, [r7, #4] + 8009350: 2201 movs r2, #1 + 8009352: f883 203f strb.w r2, [r3, #63] ; 0x3f + 8009356: 687b ldr r3, [r7, #4] + 8009358: 2201 movs r2, #1 + 800935a: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 800935e: 687b ldr r3, [r7, #4] + 8009360: 2201 movs r2, #1 + 8009362: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8009366: 687b ldr r3, [r7, #4] + 8009368: 2201 movs r2, #1 + 800936a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 800936e: 687b ldr r3, [r7, #4] + 8009370: 2201 movs r2, #1 + 8009372: f883 2043 strb.w r2, [r3, #67] ; 0x43 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8009376: 687b ldr r3, [r7, #4] + 8009378: 2201 movs r2, #1 + 800937a: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800937e: 687b ldr r3, [r7, #4] + 8009380: 2201 movs r2, #1 + 8009382: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8009386: 687b ldr r3, [r7, #4] + 8009388: 2201 movs r2, #1 + 800938a: f883 2046 strb.w r2, [r3, #70] ; 0x46 + 800938e: 687b ldr r3, [r7, #4] + 8009390: 2201 movs r2, #1 + 8009392: f883 2047 strb.w r2, [r3, #71] ; 0x47 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8009396: 687b ldr r3, [r7, #4] + 8009398: 2201 movs r2, #1 + 800939a: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 800939e: 2300 movs r3, #0 +} + 80093a0: 4618 mov r0, r3 + 80093a2: 3708 adds r7, #8 + 80093a4: 46bd mov sp, r7 + 80093a6: bd80 pop {r7, pc} + +080093a8 : + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + 80093a8: b480 push {r7} + 80093aa: b083 sub sp, #12 + 80093ac: af00 add r7, sp, #0 + 80093ae: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + 80093b0: bf00 nop + 80093b2: 370c adds r7, #12 + 80093b4: 46bd mov sp, r7 + 80093b6: f85d 7b04 ldr.w r7, [sp], #4 + 80093ba: 4770 bx lr + +080093bc : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 80093bc: b480 push {r7} + 80093be: b085 sub sp, #20 + 80093c0: af00 add r7, sp, #0 + 80093c2: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 80093c4: 687b ldr r3, [r7, #4] + 80093c6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80093ca: b2db uxtb r3, r3 + 80093cc: 2b01 cmp r3, #1 + 80093ce: d001 beq.n 80093d4 + { + return HAL_ERROR; + 80093d0: 2301 movs r3, #1 + 80093d2: e054 b.n 800947e + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80093d4: 687b ldr r3, [r7, #4] + 80093d6: 2202 movs r2, #2 + 80093d8: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 80093dc: 687b ldr r3, [r7, #4] + 80093de: 681b ldr r3, [r3, #0] + 80093e0: 68da ldr r2, [r3, #12] + 80093e2: 687b ldr r3, [r7, #4] + 80093e4: 681b ldr r3, [r3, #0] + 80093e6: f042 0201 orr.w r2, r2, #1 + 80093ea: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 80093ec: 687b ldr r3, [r7, #4] + 80093ee: 681b ldr r3, [r3, #0] + 80093f0: 4a26 ldr r2, [pc, #152] ; (800948c ) + 80093f2: 4293 cmp r3, r2 + 80093f4: d022 beq.n 800943c + 80093f6: 687b ldr r3, [r7, #4] + 80093f8: 681b ldr r3, [r3, #0] + 80093fa: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 80093fe: d01d beq.n 800943c + 8009400: 687b ldr r3, [r7, #4] + 8009402: 681b ldr r3, [r3, #0] + 8009404: 4a22 ldr r2, [pc, #136] ; (8009490 ) + 8009406: 4293 cmp r3, r2 + 8009408: d018 beq.n 800943c + 800940a: 687b ldr r3, [r7, #4] + 800940c: 681b ldr r3, [r3, #0] + 800940e: 4a21 ldr r2, [pc, #132] ; (8009494 ) + 8009410: 4293 cmp r3, r2 + 8009412: d013 beq.n 800943c + 8009414: 687b ldr r3, [r7, #4] + 8009416: 681b ldr r3, [r3, #0] + 8009418: 4a1f ldr r2, [pc, #124] ; (8009498 ) + 800941a: 4293 cmp r3, r2 + 800941c: d00e beq.n 800943c + 800941e: 687b ldr r3, [r7, #4] + 8009420: 681b ldr r3, [r3, #0] + 8009422: 4a1e ldr r2, [pc, #120] ; (800949c ) + 8009424: 4293 cmp r3, r2 + 8009426: d009 beq.n 800943c + 8009428: 687b ldr r3, [r7, #4] + 800942a: 681b ldr r3, [r3, #0] + 800942c: 4a1c ldr r2, [pc, #112] ; (80094a0 ) + 800942e: 4293 cmp r3, r2 + 8009430: d004 beq.n 800943c + 8009432: 687b ldr r3, [r7, #4] + 8009434: 681b ldr r3, [r3, #0] + 8009436: 4a1b ldr r2, [pc, #108] ; (80094a4 ) + 8009438: 4293 cmp r3, r2 + 800943a: d115 bne.n 8009468 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 800943c: 687b ldr r3, [r7, #4] + 800943e: 681b ldr r3, [r3, #0] + 8009440: 689a ldr r2, [r3, #8] + 8009442: 4b19 ldr r3, [pc, #100] ; (80094a8 ) + 8009444: 4013 ands r3, r2 + 8009446: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8009448: 68fb ldr r3, [r7, #12] + 800944a: 2b06 cmp r3, #6 + 800944c: d015 beq.n 800947a + 800944e: 68fb ldr r3, [r7, #12] + 8009450: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8009454: d011 beq.n 800947a + { + __HAL_TIM_ENABLE(htim); + 8009456: 687b ldr r3, [r7, #4] + 8009458: 681b ldr r3, [r3, #0] + 800945a: 681a ldr r2, [r3, #0] + 800945c: 687b ldr r3, [r7, #4] + 800945e: 681b ldr r3, [r3, #0] + 8009460: f042 0201 orr.w r2, r2, #1 + 8009464: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8009466: e008 b.n 800947a + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8009468: 687b ldr r3, [r7, #4] + 800946a: 681b ldr r3, [r3, #0] + 800946c: 681a ldr r2, [r3, #0] + 800946e: 687b ldr r3, [r7, #4] + 8009470: 681b ldr r3, [r3, #0] + 8009472: f042 0201 orr.w r2, r2, #1 + 8009476: 601a str r2, [r3, #0] + 8009478: e000 b.n 800947c + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800947a: bf00 nop + } + + /* Return function status */ + return HAL_OK; + 800947c: 2300 movs r3, #0 +} + 800947e: 4618 mov r0, r3 + 8009480: 3714 adds r7, #20 + 8009482: 46bd mov sp, r7 + 8009484: f85d 7b04 ldr.w r7, [sp], #4 + 8009488: 4770 bx lr + 800948a: bf00 nop + 800948c: 40010000 .word 0x40010000 + 8009490: 40000400 .word 0x40000400 + 8009494: 40000800 .word 0x40000800 + 8009498: 40000c00 .word 0x40000c00 + 800949c: 40010400 .word 0x40010400 + 80094a0: 40014000 .word 0x40014000 + 80094a4: 40001800 .word 0x40001800 + 80094a8: 00010007 .word 0x00010007 + +080094ac : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 80094ac: b580 push {r7, lr} + 80094ae: b082 sub sp, #8 + 80094b0: af00 add r7, sp, #0 + 80094b2: 6078 str r0, [r7, #4] + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 80094b4: 687b ldr r3, [r7, #4] + 80094b6: 681b ldr r3, [r3, #0] + 80094b8: 691b ldr r3, [r3, #16] + 80094ba: f003 0302 and.w r3, r3, #2 + 80094be: 2b02 cmp r3, #2 + 80094c0: d122 bne.n 8009508 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 80094c2: 687b ldr r3, [r7, #4] + 80094c4: 681b ldr r3, [r3, #0] + 80094c6: 68db ldr r3, [r3, #12] + 80094c8: f003 0302 and.w r3, r3, #2 + 80094cc: 2b02 cmp r3, #2 + 80094ce: d11b bne.n 8009508 + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 80094d0: 687b ldr r3, [r7, #4] + 80094d2: 681b ldr r3, [r3, #0] + 80094d4: f06f 0202 mvn.w r2, #2 + 80094d8: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 80094da: 687b ldr r3, [r7, #4] + 80094dc: 2201 movs r2, #1 + 80094de: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 80094e0: 687b ldr r3, [r7, #4] + 80094e2: 681b ldr r3, [r3, #0] + 80094e4: 699b ldr r3, [r3, #24] + 80094e6: f003 0303 and.w r3, r3, #3 + 80094ea: 2b00 cmp r3, #0 + 80094ec: d003 beq.n 80094f6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80094ee: 6878 ldr r0, [r7, #4] + 80094f0: f000 f905 bl 80096fe + 80094f4: e005 b.n 8009502 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80094f6: 6878 ldr r0, [r7, #4] + 80094f8: f000 f8f7 bl 80096ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80094fc: 6878 ldr r0, [r7, #4] + 80094fe: f000 f908 bl 8009712 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8009502: 687b ldr r3, [r7, #4] + 8009504: 2200 movs r2, #0 + 8009506: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 8009508: 687b ldr r3, [r7, #4] + 800950a: 681b ldr r3, [r3, #0] + 800950c: 691b ldr r3, [r3, #16] + 800950e: f003 0304 and.w r3, r3, #4 + 8009512: 2b04 cmp r3, #4 + 8009514: d122 bne.n 800955c + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 8009516: 687b ldr r3, [r7, #4] + 8009518: 681b ldr r3, [r3, #0] + 800951a: 68db ldr r3, [r3, #12] + 800951c: f003 0304 and.w r3, r3, #4 + 8009520: 2b04 cmp r3, #4 + 8009522: d11b bne.n 800955c + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 8009524: 687b ldr r3, [r7, #4] + 8009526: 681b ldr r3, [r3, #0] + 8009528: f06f 0204 mvn.w r2, #4 + 800952c: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 800952e: 687b ldr r3, [r7, #4] + 8009530: 2202 movs r2, #2 + 8009532: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8009534: 687b ldr r3, [r7, #4] + 8009536: 681b ldr r3, [r3, #0] + 8009538: 699b ldr r3, [r3, #24] + 800953a: f403 7340 and.w r3, r3, #768 ; 0x300 + 800953e: 2b00 cmp r3, #0 + 8009540: d003 beq.n 800954a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8009542: 6878 ldr r0, [r7, #4] + 8009544: f000 f8db bl 80096fe + 8009548: e005 b.n 8009556 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800954a: 6878 ldr r0, [r7, #4] + 800954c: f000 f8cd bl 80096ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8009550: 6878 ldr r0, [r7, #4] + 8009552: f000 f8de bl 8009712 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8009556: 687b ldr r3, [r7, #4] + 8009558: 2200 movs r2, #0 + 800955a: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 800955c: 687b ldr r3, [r7, #4] + 800955e: 681b ldr r3, [r3, #0] + 8009560: 691b ldr r3, [r3, #16] + 8009562: f003 0308 and.w r3, r3, #8 + 8009566: 2b08 cmp r3, #8 + 8009568: d122 bne.n 80095b0 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 800956a: 687b ldr r3, [r7, #4] + 800956c: 681b ldr r3, [r3, #0] + 800956e: 68db ldr r3, [r3, #12] + 8009570: f003 0308 and.w r3, r3, #8 + 8009574: 2b08 cmp r3, #8 + 8009576: d11b bne.n 80095b0 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 8009578: 687b ldr r3, [r7, #4] + 800957a: 681b ldr r3, [r3, #0] + 800957c: f06f 0208 mvn.w r2, #8 + 8009580: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8009582: 687b ldr r3, [r7, #4] + 8009584: 2204 movs r2, #4 + 8009586: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8009588: 687b ldr r3, [r7, #4] + 800958a: 681b ldr r3, [r3, #0] + 800958c: 69db ldr r3, [r3, #28] + 800958e: f003 0303 and.w r3, r3, #3 + 8009592: 2b00 cmp r3, #0 + 8009594: d003 beq.n 800959e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8009596: 6878 ldr r0, [r7, #4] + 8009598: f000 f8b1 bl 80096fe + 800959c: e005 b.n 80095aa + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800959e: 6878 ldr r0, [r7, #4] + 80095a0: f000 f8a3 bl 80096ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80095a4: 6878 ldr r0, [r7, #4] + 80095a6: f000 f8b4 bl 8009712 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80095aa: 687b ldr r3, [r7, #4] + 80095ac: 2200 movs r2, #0 + 80095ae: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 80095b0: 687b ldr r3, [r7, #4] + 80095b2: 681b ldr r3, [r3, #0] + 80095b4: 691b ldr r3, [r3, #16] + 80095b6: f003 0310 and.w r3, r3, #16 + 80095ba: 2b10 cmp r3, #16 + 80095bc: d122 bne.n 8009604 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 80095be: 687b ldr r3, [r7, #4] + 80095c0: 681b ldr r3, [r3, #0] + 80095c2: 68db ldr r3, [r3, #12] + 80095c4: f003 0310 and.w r3, r3, #16 + 80095c8: 2b10 cmp r3, #16 + 80095ca: d11b bne.n 8009604 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 80095cc: 687b ldr r3, [r7, #4] + 80095ce: 681b ldr r3, [r3, #0] + 80095d0: f06f 0210 mvn.w r2, #16 + 80095d4: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 80095d6: 687b ldr r3, [r7, #4] + 80095d8: 2208 movs r2, #8 + 80095da: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 80095dc: 687b ldr r3, [r7, #4] + 80095de: 681b ldr r3, [r3, #0] + 80095e0: 69db ldr r3, [r3, #28] + 80095e2: f403 7340 and.w r3, r3, #768 ; 0x300 + 80095e6: 2b00 cmp r3, #0 + 80095e8: d003 beq.n 80095f2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80095ea: 6878 ldr r0, [r7, #4] + 80095ec: f000 f887 bl 80096fe + 80095f0: e005 b.n 80095fe + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80095f2: 6878 ldr r0, [r7, #4] + 80095f4: f000 f879 bl 80096ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80095f8: 6878 ldr r0, [r7, #4] + 80095fa: f000 f88a bl 8009712 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80095fe: 687b ldr r3, [r7, #4] + 8009600: 2200 movs r2, #0 + 8009602: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8009604: 687b ldr r3, [r7, #4] + 8009606: 681b ldr r3, [r3, #0] + 8009608: 691b ldr r3, [r3, #16] + 800960a: f003 0301 and.w r3, r3, #1 + 800960e: 2b01 cmp r3, #1 + 8009610: d10e bne.n 8009630 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 8009612: 687b ldr r3, [r7, #4] + 8009614: 681b ldr r3, [r3, #0] + 8009616: 68db ldr r3, [r3, #12] + 8009618: f003 0301 and.w r3, r3, #1 + 800961c: 2b01 cmp r3, #1 + 800961e: d107 bne.n 8009630 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 8009620: 687b ldr r3, [r7, #4] + 8009622: 681b ldr r3, [r3, #0] + 8009624: f06f 0201 mvn.w r2, #1 + 8009628: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 800962a: 6878 ldr r0, [r7, #4] + 800962c: f7f9 fb44 bl 8002cb8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 8009630: 687b ldr r3, [r7, #4] + 8009632: 681b ldr r3, [r3, #0] + 8009634: 691b ldr r3, [r3, #16] + 8009636: f003 0380 and.w r3, r3, #128 ; 0x80 + 800963a: 2b80 cmp r3, #128 ; 0x80 + 800963c: d10e bne.n 800965c + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 800963e: 687b ldr r3, [r7, #4] + 8009640: 681b ldr r3, [r3, #0] + 8009642: 68db ldr r3, [r3, #12] + 8009644: f003 0380 and.w r3, r3, #128 ; 0x80 + 8009648: 2b80 cmp r3, #128 ; 0x80 + 800964a: d107 bne.n 800965c + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 800964c: 687b ldr r3, [r7, #4] + 800964e: 681b ldr r3, [r3, #0] + 8009650: f06f 0280 mvn.w r2, #128 ; 0x80 + 8009654: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 8009656: 6878 ldr r0, [r7, #4] + 8009658: f000 f91a bl 8009890 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 800965c: 687b ldr r3, [r7, #4] + 800965e: 681b ldr r3, [r3, #0] + 8009660: 691b ldr r3, [r3, #16] + 8009662: f403 7380 and.w r3, r3, #256 ; 0x100 + 8009666: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800966a: d10e bne.n 800968a + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 800966c: 687b ldr r3, [r7, #4] + 800966e: 681b ldr r3, [r3, #0] + 8009670: 68db ldr r3, [r3, #12] + 8009672: f003 0380 and.w r3, r3, #128 ; 0x80 + 8009676: 2b80 cmp r3, #128 ; 0x80 + 8009678: d107 bne.n 800968a + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + 800967a: 687b ldr r3, [r7, #4] + 800967c: 681b ldr r3, [r3, #0] + 800967e: f46f 7280 mvn.w r2, #256 ; 0x100 + 8009682: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); + 8009684: 6878 ldr r0, [r7, #4] + 8009686: f000 f90d bl 80098a4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 800968a: 687b ldr r3, [r7, #4] + 800968c: 681b ldr r3, [r3, #0] + 800968e: 691b ldr r3, [r3, #16] + 8009690: f003 0340 and.w r3, r3, #64 ; 0x40 + 8009694: 2b40 cmp r3, #64 ; 0x40 + 8009696: d10e bne.n 80096b6 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 8009698: 687b ldr r3, [r7, #4] + 800969a: 681b ldr r3, [r3, #0] + 800969c: 68db ldr r3, [r3, #12] + 800969e: f003 0340 and.w r3, r3, #64 ; 0x40 + 80096a2: 2b40 cmp r3, #64 ; 0x40 + 80096a4: d107 bne.n 80096b6 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 80096a6: 687b ldr r3, [r7, #4] + 80096a8: 681b ldr r3, [r3, #0] + 80096aa: f06f 0240 mvn.w r2, #64 ; 0x40 + 80096ae: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 80096b0: 6878 ldr r0, [r7, #4] + 80096b2: f000 f838 bl 8009726 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 80096b6: 687b ldr r3, [r7, #4] + 80096b8: 681b ldr r3, [r3, #0] + 80096ba: 691b ldr r3, [r3, #16] + 80096bc: f003 0320 and.w r3, r3, #32 + 80096c0: 2b20 cmp r3, #32 + 80096c2: d10e bne.n 80096e2 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 80096c4: 687b ldr r3, [r7, #4] + 80096c6: 681b ldr r3, [r3, #0] + 80096c8: 68db ldr r3, [r3, #12] + 80096ca: f003 0320 and.w r3, r3, #32 + 80096ce: 2b20 cmp r3, #32 + 80096d0: d107 bne.n 80096e2 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 80096d2: 687b ldr r3, [r7, #4] + 80096d4: 681b ldr r3, [r3, #0] + 80096d6: f06f 0220 mvn.w r2, #32 + 80096da: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 80096dc: 6878 ldr r0, [r7, #4] + 80096de: f000 f8cd bl 800987c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 80096e2: bf00 nop + 80096e4: 3708 adds r7, #8 + 80096e6: 46bd mov sp, r7 + 80096e8: bd80 pop {r7, pc} + +080096ea : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 80096ea: b480 push {r7} + 80096ec: b083 sub sp, #12 + 80096ee: af00 add r7, sp, #0 + 80096f0: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 80096f2: bf00 nop + 80096f4: 370c adds r7, #12 + 80096f6: 46bd mov sp, r7 + 80096f8: f85d 7b04 ldr.w r7, [sp], #4 + 80096fc: 4770 bx lr + +080096fe : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 80096fe: b480 push {r7} + 8009700: b083 sub sp, #12 + 8009702: af00 add r7, sp, #0 + 8009704: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8009706: bf00 nop + 8009708: 370c adds r7, #12 + 800970a: 46bd mov sp, r7 + 800970c: f85d 7b04 ldr.w r7, [sp], #4 + 8009710: 4770 bx lr + +08009712 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8009712: b480 push {r7} + 8009714: b083 sub sp, #12 + 8009716: af00 add r7, sp, #0 + 8009718: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 800971a: bf00 nop + 800971c: 370c adds r7, #12 + 800971e: 46bd mov sp, r7 + 8009720: f85d 7b04 ldr.w r7, [sp], #4 + 8009724: 4770 bx lr + +08009726 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8009726: b480 push {r7} + 8009728: b083 sub sp, #12 + 800972a: af00 add r7, sp, #0 + 800972c: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 800972e: bf00 nop + 8009730: 370c adds r7, #12 + 8009732: 46bd mov sp, r7 + 8009734: f85d 7b04 ldr.w r7, [sp], #4 + 8009738: 4770 bx lr + ... + +0800973c : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 800973c: b480 push {r7} + 800973e: b085 sub sp, #20 + 8009740: af00 add r7, sp, #0 + 8009742: 6078 str r0, [r7, #4] + 8009744: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8009746: 687b ldr r3, [r7, #4] + 8009748: 681b ldr r3, [r3, #0] + 800974a: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 800974c: 687b ldr r3, [r7, #4] + 800974e: 4a40 ldr r2, [pc, #256] ; (8009850 ) + 8009750: 4293 cmp r3, r2 + 8009752: d013 beq.n 800977c + 8009754: 687b ldr r3, [r7, #4] + 8009756: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800975a: d00f beq.n 800977c + 800975c: 687b ldr r3, [r7, #4] + 800975e: 4a3d ldr r2, [pc, #244] ; (8009854 ) + 8009760: 4293 cmp r3, r2 + 8009762: d00b beq.n 800977c + 8009764: 687b ldr r3, [r7, #4] + 8009766: 4a3c ldr r2, [pc, #240] ; (8009858 ) + 8009768: 4293 cmp r3, r2 + 800976a: d007 beq.n 800977c + 800976c: 687b ldr r3, [r7, #4] + 800976e: 4a3b ldr r2, [pc, #236] ; (800985c ) + 8009770: 4293 cmp r3, r2 + 8009772: d003 beq.n 800977c + 8009774: 687b ldr r3, [r7, #4] + 8009776: 4a3a ldr r2, [pc, #232] ; (8009860 ) + 8009778: 4293 cmp r3, r2 + 800977a: d108 bne.n 800978e + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 800977c: 68fb ldr r3, [r7, #12] + 800977e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8009782: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8009784: 683b ldr r3, [r7, #0] + 8009786: 685b ldr r3, [r3, #4] + 8009788: 68fa ldr r2, [r7, #12] + 800978a: 4313 orrs r3, r2 + 800978c: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 800978e: 687b ldr r3, [r7, #4] + 8009790: 4a2f ldr r2, [pc, #188] ; (8009850 ) + 8009792: 4293 cmp r3, r2 + 8009794: d02b beq.n 80097ee + 8009796: 687b ldr r3, [r7, #4] + 8009798: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800979c: d027 beq.n 80097ee + 800979e: 687b ldr r3, [r7, #4] + 80097a0: 4a2c ldr r2, [pc, #176] ; (8009854 ) + 80097a2: 4293 cmp r3, r2 + 80097a4: d023 beq.n 80097ee + 80097a6: 687b ldr r3, [r7, #4] + 80097a8: 4a2b ldr r2, [pc, #172] ; (8009858 ) + 80097aa: 4293 cmp r3, r2 + 80097ac: d01f beq.n 80097ee + 80097ae: 687b ldr r3, [r7, #4] + 80097b0: 4a2a ldr r2, [pc, #168] ; (800985c ) + 80097b2: 4293 cmp r3, r2 + 80097b4: d01b beq.n 80097ee + 80097b6: 687b ldr r3, [r7, #4] + 80097b8: 4a29 ldr r2, [pc, #164] ; (8009860 ) + 80097ba: 4293 cmp r3, r2 + 80097bc: d017 beq.n 80097ee + 80097be: 687b ldr r3, [r7, #4] + 80097c0: 4a28 ldr r2, [pc, #160] ; (8009864 ) + 80097c2: 4293 cmp r3, r2 + 80097c4: d013 beq.n 80097ee + 80097c6: 687b ldr r3, [r7, #4] + 80097c8: 4a27 ldr r2, [pc, #156] ; (8009868 ) + 80097ca: 4293 cmp r3, r2 + 80097cc: d00f beq.n 80097ee + 80097ce: 687b ldr r3, [r7, #4] + 80097d0: 4a26 ldr r2, [pc, #152] ; (800986c ) + 80097d2: 4293 cmp r3, r2 + 80097d4: d00b beq.n 80097ee + 80097d6: 687b ldr r3, [r7, #4] + 80097d8: 4a25 ldr r2, [pc, #148] ; (8009870 ) + 80097da: 4293 cmp r3, r2 + 80097dc: d007 beq.n 80097ee + 80097de: 687b ldr r3, [r7, #4] + 80097e0: 4a24 ldr r2, [pc, #144] ; (8009874 ) + 80097e2: 4293 cmp r3, r2 + 80097e4: d003 beq.n 80097ee + 80097e6: 687b ldr r3, [r7, #4] + 80097e8: 4a23 ldr r2, [pc, #140] ; (8009878 ) + 80097ea: 4293 cmp r3, r2 + 80097ec: d108 bne.n 8009800 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 80097ee: 68fb ldr r3, [r7, #12] + 80097f0: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80097f4: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 80097f6: 683b ldr r3, [r7, #0] + 80097f8: 68db ldr r3, [r3, #12] + 80097fa: 68fa ldr r2, [r7, #12] + 80097fc: 4313 orrs r3, r2 + 80097fe: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8009800: 68fb ldr r3, [r7, #12] + 8009802: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8009806: 683b ldr r3, [r7, #0] + 8009808: 695b ldr r3, [r3, #20] + 800980a: 4313 orrs r3, r2 + 800980c: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 800980e: 687b ldr r3, [r7, #4] + 8009810: 68fa ldr r2, [r7, #12] + 8009812: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8009814: 683b ldr r3, [r7, #0] + 8009816: 689a ldr r2, [r3, #8] + 8009818: 687b ldr r3, [r7, #4] + 800981a: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 800981c: 683b ldr r3, [r7, #0] + 800981e: 681a ldr r2, [r3, #0] + 8009820: 687b ldr r3, [r7, #4] + 8009822: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8009824: 687b ldr r3, [r7, #4] + 8009826: 4a0a ldr r2, [pc, #40] ; (8009850 ) + 8009828: 4293 cmp r3, r2 + 800982a: d003 beq.n 8009834 + 800982c: 687b ldr r3, [r7, #4] + 800982e: 4a0c ldr r2, [pc, #48] ; (8009860 ) + 8009830: 4293 cmp r3, r2 + 8009832: d103 bne.n 800983c + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8009834: 683b ldr r3, [r7, #0] + 8009836: 691a ldr r2, [r3, #16] + 8009838: 687b ldr r3, [r7, #4] + 800983a: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 800983c: 687b ldr r3, [r7, #4] + 800983e: 2201 movs r2, #1 + 8009840: 615a str r2, [r3, #20] +} + 8009842: bf00 nop + 8009844: 3714 adds r7, #20 + 8009846: 46bd mov sp, r7 + 8009848: f85d 7b04 ldr.w r7, [sp], #4 + 800984c: 4770 bx lr + 800984e: bf00 nop + 8009850: 40010000 .word 0x40010000 + 8009854: 40000400 .word 0x40000400 + 8009858: 40000800 .word 0x40000800 + 800985c: 40000c00 .word 0x40000c00 + 8009860: 40010400 .word 0x40010400 + 8009864: 40014000 .word 0x40014000 + 8009868: 40014400 .word 0x40014400 + 800986c: 40014800 .word 0x40014800 + 8009870: 40001800 .word 0x40001800 + 8009874: 40001c00 .word 0x40001c00 + 8009878: 40002000 .word 0x40002000 + +0800987c : + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 800987c: b480 push {r7} + 800987e: b083 sub sp, #12 + 8009880: af00 add r7, sp, #0 + 8009882: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 8009884: bf00 nop + 8009886: 370c adds r7, #12 + 8009888: 46bd mov sp, r7 + 800988a: f85d 7b04 ldr.w r7, [sp], #4 + 800988e: 4770 bx lr + +08009890 : + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8009890: b480 push {r7} + 8009892: b083 sub sp, #12 + 8009894: af00 add r7, sp, #0 + 8009896: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 8009898: bf00 nop + 800989a: 370c adds r7, #12 + 800989c: 46bd mov sp, r7 + 800989e: f85d 7b04 ldr.w r7, [sp], #4 + 80098a2: 4770 bx lr + +080098a4 : + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + 80098a4: b480 push {r7} + 80098a6: b083 sub sp, #12 + 80098a8: af00 add r7, sp, #0 + 80098aa: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + 80098ac: bf00 nop + 80098ae: 370c adds r7, #12 + 80098b0: 46bd mov sp, r7 + 80098b2: f85d 7b04 ldr.w r7, [sp], #4 + 80098b6: 4770 bx lr + +080098b8 : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 80098b8: b580 push {r7, lr} + 80098ba: b082 sub sp, #8 + 80098bc: af00 add r7, sp, #0 + 80098be: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 80098c0: 687b ldr r3, [r7, #4] + 80098c2: 2b00 cmp r3, #0 + 80098c4: d101 bne.n 80098ca + { + return HAL_ERROR; + 80098c6: 2301 movs r3, #1 + 80098c8: e040 b.n 800994c + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 80098ca: 687b ldr r3, [r7, #4] + 80098cc: 6fdb ldr r3, [r3, #124] ; 0x7c + 80098ce: 2b00 cmp r3, #0 + 80098d0: d106 bne.n 80098e0 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 80098d2: 687b ldr r3, [r7, #4] + 80098d4: 2200 movs r2, #0 + 80098d6: f883 2078 strb.w r2, [r3, #120] ; 0x78 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 80098da: 6878 ldr r0, [r7, #4] + 80098dc: f7f9 fb72 bl 8002fc4 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 80098e0: 687b ldr r3, [r7, #4] + 80098e2: 2224 movs r2, #36 ; 0x24 + 80098e4: 67da str r2, [r3, #124] ; 0x7c + + __HAL_UART_DISABLE(huart); + 80098e6: 687b ldr r3, [r7, #4] + 80098e8: 681b ldr r3, [r3, #0] + 80098ea: 681a ldr r2, [r3, #0] + 80098ec: 687b ldr r3, [r7, #4] + 80098ee: 681b ldr r3, [r3, #0] + 80098f0: f022 0201 bic.w r2, r2, #1 + 80098f4: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 80098f6: 6878 ldr r0, [r7, #4] + 80098f8: f000 f974 bl 8009be4 + 80098fc: 4603 mov r3, r0 + 80098fe: 2b01 cmp r3, #1 + 8009900: d101 bne.n 8009906 + { + return HAL_ERROR; + 8009902: 2301 movs r3, #1 + 8009904: e022 b.n 800994c + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 8009906: 687b ldr r3, [r7, #4] + 8009908: 6a5b ldr r3, [r3, #36] ; 0x24 + 800990a: 2b00 cmp r3, #0 + 800990c: d002 beq.n 8009914 + { + UART_AdvFeatureConfig(huart); + 800990e: 6878 ldr r0, [r7, #4] + 8009910: f000 fbcc bl 800a0ac + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8009914: 687b ldr r3, [r7, #4] + 8009916: 681b ldr r3, [r3, #0] + 8009918: 685a ldr r2, [r3, #4] + 800991a: 687b ldr r3, [r7, #4] + 800991c: 681b ldr r3, [r3, #0] + 800991e: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8009922: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8009924: 687b ldr r3, [r7, #4] + 8009926: 681b ldr r3, [r3, #0] + 8009928: 689a ldr r2, [r3, #8] + 800992a: 687b ldr r3, [r7, #4] + 800992c: 681b ldr r3, [r3, #0] + 800992e: f022 022a bic.w r2, r2, #42 ; 0x2a + 8009932: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 8009934: 687b ldr r3, [r7, #4] + 8009936: 681b ldr r3, [r3, #0] + 8009938: 681a ldr r2, [r3, #0] + 800993a: 687b ldr r3, [r7, #4] + 800993c: 681b ldr r3, [r3, #0] + 800993e: f042 0201 orr.w r2, r2, #1 + 8009942: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 8009944: 6878 ldr r0, [r7, #4] + 8009946: f000 fc53 bl 800a1f0 + 800994a: 4603 mov r3, r0 +} + 800994c: 4618 mov r0, r3 + 800994e: 3708 adds r7, #8 + 8009950: 46bd mov sp, r7 + 8009952: bd80 pop {r7, pc} + +08009954 : + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8009954: b580 push {r7, lr} + 8009956: b08a sub sp, #40 ; 0x28 + 8009958: af02 add r7, sp, #8 + 800995a: 60f8 str r0, [r7, #12] + 800995c: 60b9 str r1, [r7, #8] + 800995e: 603b str r3, [r7, #0] + 8009960: 4613 mov r3, r2 + 8009962: 80fb strh r3, [r7, #6] + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8009964: 68fb ldr r3, [r7, #12] + 8009966: 6fdb ldr r3, [r3, #124] ; 0x7c + 8009968: 2b20 cmp r3, #32 + 800996a: d171 bne.n 8009a50 + { + if ((pData == NULL) || (Size == 0U)) + 800996c: 68bb ldr r3, [r7, #8] + 800996e: 2b00 cmp r3, #0 + 8009970: d002 beq.n 8009978 + 8009972: 88fb ldrh r3, [r7, #6] + 8009974: 2b00 cmp r3, #0 + 8009976: d101 bne.n 800997c + { + return HAL_ERROR; + 8009978: 2301 movs r3, #1 + 800997a: e06a b.n 8009a52 + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800997c: 68fb ldr r3, [r7, #12] + 800997e: 2200 movs r2, #0 + 8009980: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + huart->gState = HAL_UART_STATE_BUSY_TX; + 8009984: 68fb ldr r3, [r7, #12] + 8009986: 2221 movs r2, #33 ; 0x21 + 8009988: 67da str r2, [r3, #124] ; 0x7c + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 800998a: f7fa ff73 bl 8004874 + 800998e: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 8009990: 68fb ldr r3, [r7, #12] + 8009992: 88fa ldrh r2, [r7, #6] + 8009994: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + huart->TxXferCount = Size; + 8009998: 68fb ldr r3, [r7, #12] + 800999a: 88fa ldrh r2, [r7, #6] + 800999c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 80099a0: 68fb ldr r3, [r7, #12] + 80099a2: 689b ldr r3, [r3, #8] + 80099a4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80099a8: d108 bne.n 80099bc + 80099aa: 68fb ldr r3, [r7, #12] + 80099ac: 691b ldr r3, [r3, #16] + 80099ae: 2b00 cmp r3, #0 + 80099b0: d104 bne.n 80099bc + { + pdata8bits = NULL; + 80099b2: 2300 movs r3, #0 + 80099b4: 61fb str r3, [r7, #28] + pdata16bits = (const uint16_t *) pData; + 80099b6: 68bb ldr r3, [r7, #8] + 80099b8: 61bb str r3, [r7, #24] + 80099ba: e003 b.n 80099c4 + } + else + { + pdata8bits = pData; + 80099bc: 68bb ldr r3, [r7, #8] + 80099be: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 80099c0: 2300 movs r3, #0 + 80099c2: 61bb str r3, [r7, #24] + } + + while (huart->TxXferCount > 0U) + 80099c4: e02c b.n 8009a20 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 80099c6: 683b ldr r3, [r7, #0] + 80099c8: 9300 str r3, [sp, #0] + 80099ca: 697b ldr r3, [r7, #20] + 80099cc: 2200 movs r2, #0 + 80099ce: 2180 movs r1, #128 ; 0x80 + 80099d0: 68f8 ldr r0, [r7, #12] + 80099d2: f000 fc44 bl 800a25e + 80099d6: 4603 mov r3, r0 + 80099d8: 2b00 cmp r3, #0 + 80099da: d001 beq.n 80099e0 + { + return HAL_TIMEOUT; + 80099dc: 2303 movs r3, #3 + 80099de: e038 b.n 8009a52 + } + if (pdata8bits == NULL) + 80099e0: 69fb ldr r3, [r7, #28] + 80099e2: 2b00 cmp r3, #0 + 80099e4: d10b bne.n 80099fe + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + 80099e6: 69bb ldr r3, [r7, #24] + 80099e8: 881b ldrh r3, [r3, #0] + 80099ea: 461a mov r2, r3 + 80099ec: 68fb ldr r3, [r7, #12] + 80099ee: 681b ldr r3, [r3, #0] + 80099f0: f3c2 0208 ubfx r2, r2, #0, #9 + 80099f4: 629a str r2, [r3, #40] ; 0x28 + pdata16bits++; + 80099f6: 69bb ldr r3, [r7, #24] + 80099f8: 3302 adds r3, #2 + 80099fa: 61bb str r3, [r7, #24] + 80099fc: e007 b.n 8009a0e + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + 80099fe: 69fb ldr r3, [r7, #28] + 8009a00: 781a ldrb r2, [r3, #0] + 8009a02: 68fb ldr r3, [r7, #12] + 8009a04: 681b ldr r3, [r3, #0] + 8009a06: 629a str r2, [r3, #40] ; 0x28 + pdata8bits++; + 8009a08: 69fb ldr r3, [r7, #28] + 8009a0a: 3301 adds r3, #1 + 8009a0c: 61fb str r3, [r7, #28] + } + huart->TxXferCount--; + 8009a0e: 68fb ldr r3, [r7, #12] + 8009a10: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8009a14: b29b uxth r3, r3 + 8009a16: 3b01 subs r3, #1 + 8009a18: b29a uxth r2, r3 + 8009a1a: 68fb ldr r3, [r7, #12] + 8009a1c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + while (huart->TxXferCount > 0U) + 8009a20: 68fb ldr r3, [r7, #12] + 8009a22: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8009a26: b29b uxth r3, r3 + 8009a28: 2b00 cmp r3, #0 + 8009a2a: d1cc bne.n 80099c6 + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 8009a2c: 683b ldr r3, [r7, #0] + 8009a2e: 9300 str r3, [sp, #0] + 8009a30: 697b ldr r3, [r7, #20] + 8009a32: 2200 movs r2, #0 + 8009a34: 2140 movs r1, #64 ; 0x40 + 8009a36: 68f8 ldr r0, [r7, #12] + 8009a38: f000 fc11 bl 800a25e + 8009a3c: 4603 mov r3, r0 + 8009a3e: 2b00 cmp r3, #0 + 8009a40: d001 beq.n 8009a46 + { + return HAL_TIMEOUT; + 8009a42: 2303 movs r3, #3 + 8009a44: e005 b.n 8009a52 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8009a46: 68fb ldr r3, [r7, #12] + 8009a48: 2220 movs r2, #32 + 8009a4a: 67da str r2, [r3, #124] ; 0x7c + + return HAL_OK; + 8009a4c: 2300 movs r3, #0 + 8009a4e: e000 b.n 8009a52 + } + else + { + return HAL_BUSY; + 8009a50: 2302 movs r3, #2 + } +} + 8009a52: 4618 mov r0, r3 + 8009a54: 3720 adds r7, #32 + 8009a56: 46bd mov sp, r7 + 8009a58: bd80 pop {r7, pc} + +08009a5a : + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8009a5a: b580 push {r7, lr} + 8009a5c: b08a sub sp, #40 ; 0x28 + 8009a5e: af02 add r7, sp, #8 + 8009a60: 60f8 str r0, [r7, #12] + 8009a62: 60b9 str r1, [r7, #8] + 8009a64: 603b str r3, [r7, #0] + 8009a66: 4613 mov r3, r2 + 8009a68: 80fb strh r3, [r7, #6] + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8009a6a: 68fb ldr r3, [r7, #12] + 8009a6c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8009a70: 2b20 cmp r3, #32 + 8009a72: f040 80b1 bne.w 8009bd8 + { + if ((pData == NULL) || (Size == 0U)) + 8009a76: 68bb ldr r3, [r7, #8] + 8009a78: 2b00 cmp r3, #0 + 8009a7a: d002 beq.n 8009a82 + 8009a7c: 88fb ldrh r3, [r7, #6] + 8009a7e: 2b00 cmp r3, #0 + 8009a80: d101 bne.n 8009a86 + { + return HAL_ERROR; + 8009a82: 2301 movs r3, #1 + 8009a84: e0a9 b.n 8009bda + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8009a86: 68fb ldr r3, [r7, #12] + 8009a88: 2200 movs r2, #0 + 8009a8a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8009a8e: 68fb ldr r3, [r7, #12] + 8009a90: 2222 movs r2, #34 ; 0x22 + 8009a92: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8009a96: 68fb ldr r3, [r7, #12] + 8009a98: 2200 movs r2, #0 + 8009a9a: 661a str r2, [r3, #96] ; 0x60 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8009a9c: f7fa feea bl 8004874 + 8009aa0: 6178 str r0, [r7, #20] + + huart->RxXferSize = Size; + 8009aa2: 68fb ldr r3, [r7, #12] + 8009aa4: 88fa ldrh r2, [r7, #6] + 8009aa6: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + huart->RxXferCount = Size; + 8009aaa: 68fb ldr r3, [r7, #12] + 8009aac: 88fa ldrh r2, [r7, #6] + 8009aae: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 8009ab2: 68fb ldr r3, [r7, #12] + 8009ab4: 689b ldr r3, [r3, #8] + 8009ab6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8009aba: d10e bne.n 8009ada + 8009abc: 68fb ldr r3, [r7, #12] + 8009abe: 691b ldr r3, [r3, #16] + 8009ac0: 2b00 cmp r3, #0 + 8009ac2: d105 bne.n 8009ad0 + 8009ac4: 68fb ldr r3, [r7, #12] + 8009ac6: f240 12ff movw r2, #511 ; 0x1ff + 8009aca: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009ace: e02d b.n 8009b2c + 8009ad0: 68fb ldr r3, [r7, #12] + 8009ad2: 22ff movs r2, #255 ; 0xff + 8009ad4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009ad8: e028 b.n 8009b2c + 8009ada: 68fb ldr r3, [r7, #12] + 8009adc: 689b ldr r3, [r3, #8] + 8009ade: 2b00 cmp r3, #0 + 8009ae0: d10d bne.n 8009afe + 8009ae2: 68fb ldr r3, [r7, #12] + 8009ae4: 691b ldr r3, [r3, #16] + 8009ae6: 2b00 cmp r3, #0 + 8009ae8: d104 bne.n 8009af4 + 8009aea: 68fb ldr r3, [r7, #12] + 8009aec: 22ff movs r2, #255 ; 0xff + 8009aee: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009af2: e01b b.n 8009b2c + 8009af4: 68fb ldr r3, [r7, #12] + 8009af6: 227f movs r2, #127 ; 0x7f + 8009af8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009afc: e016 b.n 8009b2c + 8009afe: 68fb ldr r3, [r7, #12] + 8009b00: 689b ldr r3, [r3, #8] + 8009b02: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8009b06: d10d bne.n 8009b24 + 8009b08: 68fb ldr r3, [r7, #12] + 8009b0a: 691b ldr r3, [r3, #16] + 8009b0c: 2b00 cmp r3, #0 + 8009b0e: d104 bne.n 8009b1a + 8009b10: 68fb ldr r3, [r7, #12] + 8009b12: 227f movs r2, #127 ; 0x7f + 8009b14: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009b18: e008 b.n 8009b2c + 8009b1a: 68fb ldr r3, [r7, #12] + 8009b1c: 223f movs r2, #63 ; 0x3f + 8009b1e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8009b22: e003 b.n 8009b2c + 8009b24: 68fb ldr r3, [r7, #12] + 8009b26: 2200 movs r2, #0 + 8009b28: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + uhMask = huart->Mask; + 8009b2c: 68fb ldr r3, [r7, #12] + 8009b2e: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8009b32: 827b strh r3, [r7, #18] + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8009b34: 68fb ldr r3, [r7, #12] + 8009b36: 689b ldr r3, [r3, #8] + 8009b38: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8009b3c: d108 bne.n 8009b50 + 8009b3e: 68fb ldr r3, [r7, #12] + 8009b40: 691b ldr r3, [r3, #16] + 8009b42: 2b00 cmp r3, #0 + 8009b44: d104 bne.n 8009b50 + { + pdata8bits = NULL; + 8009b46: 2300 movs r3, #0 + 8009b48: 61fb str r3, [r7, #28] + pdata16bits = (uint16_t *) pData; + 8009b4a: 68bb ldr r3, [r7, #8] + 8009b4c: 61bb str r3, [r7, #24] + 8009b4e: e003 b.n 8009b58 + } + else + { + pdata8bits = pData; + 8009b50: 68bb ldr r3, [r7, #8] + 8009b52: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 8009b54: 2300 movs r3, #0 + 8009b56: 61bb str r3, [r7, #24] + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + 8009b58: e032 b.n 8009bc0 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + 8009b5a: 683b ldr r3, [r7, #0] + 8009b5c: 9300 str r3, [sp, #0] + 8009b5e: 697b ldr r3, [r7, #20] + 8009b60: 2200 movs r2, #0 + 8009b62: 2120 movs r1, #32 + 8009b64: 68f8 ldr r0, [r7, #12] + 8009b66: f000 fb7a bl 800a25e + 8009b6a: 4603 mov r3, r0 + 8009b6c: 2b00 cmp r3, #0 + 8009b6e: d001 beq.n 8009b74 + { + return HAL_TIMEOUT; + 8009b70: 2303 movs r3, #3 + 8009b72: e032 b.n 8009bda + } + if (pdata8bits == NULL) + 8009b74: 69fb ldr r3, [r7, #28] + 8009b76: 2b00 cmp r3, #0 + 8009b78: d10c bne.n 8009b94 + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + 8009b7a: 68fb ldr r3, [r7, #12] + 8009b7c: 681b ldr r3, [r3, #0] + 8009b7e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009b80: b29a uxth r2, r3 + 8009b82: 8a7b ldrh r3, [r7, #18] + 8009b84: 4013 ands r3, r2 + 8009b86: b29a uxth r2, r3 + 8009b88: 69bb ldr r3, [r7, #24] + 8009b8a: 801a strh r2, [r3, #0] + pdata16bits++; + 8009b8c: 69bb ldr r3, [r7, #24] + 8009b8e: 3302 adds r3, #2 + 8009b90: 61bb str r3, [r7, #24] + 8009b92: e00c b.n 8009bae + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + 8009b94: 68fb ldr r3, [r7, #12] + 8009b96: 681b ldr r3, [r3, #0] + 8009b98: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009b9a: b2da uxtb r2, r3 + 8009b9c: 8a7b ldrh r3, [r7, #18] + 8009b9e: b2db uxtb r3, r3 + 8009ba0: 4013 ands r3, r2 + 8009ba2: b2da uxtb r2, r3 + 8009ba4: 69fb ldr r3, [r7, #28] + 8009ba6: 701a strb r2, [r3, #0] + pdata8bits++; + 8009ba8: 69fb ldr r3, [r7, #28] + 8009baa: 3301 adds r3, #1 + 8009bac: 61fb str r3, [r7, #28] + } + huart->RxXferCount--; + 8009bae: 68fb ldr r3, [r7, #12] + 8009bb0: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8009bb4: b29b uxth r3, r3 + 8009bb6: 3b01 subs r3, #1 + 8009bb8: b29a uxth r2, r3 + 8009bba: 68fb ldr r3, [r7, #12] + 8009bbc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + while (huart->RxXferCount > 0U) + 8009bc0: 68fb ldr r3, [r7, #12] + 8009bc2: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8009bc6: b29b uxth r3, r3 + 8009bc8: 2b00 cmp r3, #0 + 8009bca: d1c6 bne.n 8009b5a + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8009bcc: 68fb ldr r3, [r7, #12] + 8009bce: 2220 movs r2, #32 + 8009bd0: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + + return HAL_OK; + 8009bd4: 2300 movs r3, #0 + 8009bd6: e000 b.n 8009bda + } + else + { + return HAL_BUSY; + 8009bd8: 2302 movs r3, #2 + } +} + 8009bda: 4618 mov r0, r3 + 8009bdc: 3720 adds r7, #32 + 8009bde: 46bd mov sp, r7 + 8009be0: bd80 pop {r7, pc} + ... + +08009be4 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8009be4: b580 push {r7, lr} + 8009be6: b088 sub sp, #32 + 8009be8: af00 add r7, sp, #0 + 8009bea: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 8009bec: 2300 movs r3, #0 + 8009bee: 77bb strb r3, [r7, #30] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8009bf0: 687b ldr r3, [r7, #4] + 8009bf2: 689a ldr r2, [r3, #8] + 8009bf4: 687b ldr r3, [r7, #4] + 8009bf6: 691b ldr r3, [r3, #16] + 8009bf8: 431a orrs r2, r3 + 8009bfa: 687b ldr r3, [r7, #4] + 8009bfc: 695b ldr r3, [r3, #20] + 8009bfe: 431a orrs r2, r3 + 8009c00: 687b ldr r3, [r7, #4] + 8009c02: 69db ldr r3, [r3, #28] + 8009c04: 4313 orrs r3, r2 + 8009c06: 617b str r3, [r7, #20] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8009c08: 687b ldr r3, [r7, #4] + 8009c0a: 681b ldr r3, [r3, #0] + 8009c0c: 681a ldr r2, [r3, #0] + 8009c0e: 4ba6 ldr r3, [pc, #664] ; (8009ea8 ) + 8009c10: 4013 ands r3, r2 + 8009c12: 687a ldr r2, [r7, #4] + 8009c14: 6812 ldr r2, [r2, #0] + 8009c16: 6979 ldr r1, [r7, #20] + 8009c18: 430b orrs r3, r1 + 8009c1a: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8009c1c: 687b ldr r3, [r7, #4] + 8009c1e: 681b ldr r3, [r3, #0] + 8009c20: 685b ldr r3, [r3, #4] + 8009c22: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8009c26: 687b ldr r3, [r7, #4] + 8009c28: 68da ldr r2, [r3, #12] + 8009c2a: 687b ldr r3, [r7, #4] + 8009c2c: 681b ldr r3, [r3, #0] + 8009c2e: 430a orrs r2, r1 + 8009c30: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8009c32: 687b ldr r3, [r7, #4] + 8009c34: 699b ldr r3, [r3, #24] + 8009c36: 617b str r3, [r7, #20] + + tmpreg |= huart->Init.OneBitSampling; + 8009c38: 687b ldr r3, [r7, #4] + 8009c3a: 6a1b ldr r3, [r3, #32] + 8009c3c: 697a ldr r2, [r7, #20] + 8009c3e: 4313 orrs r3, r2 + 8009c40: 617b str r3, [r7, #20] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8009c42: 687b ldr r3, [r7, #4] + 8009c44: 681b ldr r3, [r3, #0] + 8009c46: 689b ldr r3, [r3, #8] + 8009c48: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 8009c4c: 687b ldr r3, [r7, #4] + 8009c4e: 681b ldr r3, [r3, #0] + 8009c50: 697a ldr r2, [r7, #20] + 8009c52: 430a orrs r2, r1 + 8009c54: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8009c56: 687b ldr r3, [r7, #4] + 8009c58: 681b ldr r3, [r3, #0] + 8009c5a: 4a94 ldr r2, [pc, #592] ; (8009eac ) + 8009c5c: 4293 cmp r3, r2 + 8009c5e: d120 bne.n 8009ca2 + 8009c60: 4b93 ldr r3, [pc, #588] ; (8009eb0 ) + 8009c62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009c66: f003 0303 and.w r3, r3, #3 + 8009c6a: 2b03 cmp r3, #3 + 8009c6c: d816 bhi.n 8009c9c + 8009c6e: a201 add r2, pc, #4 ; (adr r2, 8009c74 ) + 8009c70: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009c74: 08009c85 .word 0x08009c85 + 8009c78: 08009c91 .word 0x08009c91 + 8009c7c: 08009c8b .word 0x08009c8b + 8009c80: 08009c97 .word 0x08009c97 + 8009c84: 2301 movs r3, #1 + 8009c86: 77fb strb r3, [r7, #31] + 8009c88: e150 b.n 8009f2c + 8009c8a: 2302 movs r3, #2 + 8009c8c: 77fb strb r3, [r7, #31] + 8009c8e: e14d b.n 8009f2c + 8009c90: 2304 movs r3, #4 + 8009c92: 77fb strb r3, [r7, #31] + 8009c94: e14a b.n 8009f2c + 8009c96: 2308 movs r3, #8 + 8009c98: 77fb strb r3, [r7, #31] + 8009c9a: e147 b.n 8009f2c + 8009c9c: 2310 movs r3, #16 + 8009c9e: 77fb strb r3, [r7, #31] + 8009ca0: e144 b.n 8009f2c + 8009ca2: 687b ldr r3, [r7, #4] + 8009ca4: 681b ldr r3, [r3, #0] + 8009ca6: 4a83 ldr r2, [pc, #524] ; (8009eb4 ) + 8009ca8: 4293 cmp r3, r2 + 8009caa: d132 bne.n 8009d12 + 8009cac: 4b80 ldr r3, [pc, #512] ; (8009eb0 ) + 8009cae: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009cb2: f003 030c and.w r3, r3, #12 + 8009cb6: 2b0c cmp r3, #12 + 8009cb8: d828 bhi.n 8009d0c + 8009cba: a201 add r2, pc, #4 ; (adr r2, 8009cc0 ) + 8009cbc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009cc0: 08009cf5 .word 0x08009cf5 + 8009cc4: 08009d0d .word 0x08009d0d + 8009cc8: 08009d0d .word 0x08009d0d + 8009ccc: 08009d0d .word 0x08009d0d + 8009cd0: 08009d01 .word 0x08009d01 + 8009cd4: 08009d0d .word 0x08009d0d + 8009cd8: 08009d0d .word 0x08009d0d + 8009cdc: 08009d0d .word 0x08009d0d + 8009ce0: 08009cfb .word 0x08009cfb + 8009ce4: 08009d0d .word 0x08009d0d + 8009ce8: 08009d0d .word 0x08009d0d + 8009cec: 08009d0d .word 0x08009d0d + 8009cf0: 08009d07 .word 0x08009d07 + 8009cf4: 2300 movs r3, #0 + 8009cf6: 77fb strb r3, [r7, #31] + 8009cf8: e118 b.n 8009f2c + 8009cfa: 2302 movs r3, #2 + 8009cfc: 77fb strb r3, [r7, #31] + 8009cfe: e115 b.n 8009f2c + 8009d00: 2304 movs r3, #4 + 8009d02: 77fb strb r3, [r7, #31] + 8009d04: e112 b.n 8009f2c + 8009d06: 2308 movs r3, #8 + 8009d08: 77fb strb r3, [r7, #31] + 8009d0a: e10f b.n 8009f2c + 8009d0c: 2310 movs r3, #16 + 8009d0e: 77fb strb r3, [r7, #31] + 8009d10: e10c b.n 8009f2c + 8009d12: 687b ldr r3, [r7, #4] + 8009d14: 681b ldr r3, [r3, #0] + 8009d16: 4a68 ldr r2, [pc, #416] ; (8009eb8 ) + 8009d18: 4293 cmp r3, r2 + 8009d1a: d120 bne.n 8009d5e + 8009d1c: 4b64 ldr r3, [pc, #400] ; (8009eb0 ) + 8009d1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009d22: f003 0330 and.w r3, r3, #48 ; 0x30 + 8009d26: 2b30 cmp r3, #48 ; 0x30 + 8009d28: d013 beq.n 8009d52 + 8009d2a: 2b30 cmp r3, #48 ; 0x30 + 8009d2c: d814 bhi.n 8009d58 + 8009d2e: 2b20 cmp r3, #32 + 8009d30: d009 beq.n 8009d46 + 8009d32: 2b20 cmp r3, #32 + 8009d34: d810 bhi.n 8009d58 + 8009d36: 2b00 cmp r3, #0 + 8009d38: d002 beq.n 8009d40 + 8009d3a: 2b10 cmp r3, #16 + 8009d3c: d006 beq.n 8009d4c + 8009d3e: e00b b.n 8009d58 + 8009d40: 2300 movs r3, #0 + 8009d42: 77fb strb r3, [r7, #31] + 8009d44: e0f2 b.n 8009f2c + 8009d46: 2302 movs r3, #2 + 8009d48: 77fb strb r3, [r7, #31] + 8009d4a: e0ef b.n 8009f2c + 8009d4c: 2304 movs r3, #4 + 8009d4e: 77fb strb r3, [r7, #31] + 8009d50: e0ec b.n 8009f2c + 8009d52: 2308 movs r3, #8 + 8009d54: 77fb strb r3, [r7, #31] + 8009d56: e0e9 b.n 8009f2c + 8009d58: 2310 movs r3, #16 + 8009d5a: 77fb strb r3, [r7, #31] + 8009d5c: e0e6 b.n 8009f2c + 8009d5e: 687b ldr r3, [r7, #4] + 8009d60: 681b ldr r3, [r3, #0] + 8009d62: 4a56 ldr r2, [pc, #344] ; (8009ebc ) + 8009d64: 4293 cmp r3, r2 + 8009d66: d120 bne.n 8009daa + 8009d68: 4b51 ldr r3, [pc, #324] ; (8009eb0 ) + 8009d6a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009d6e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8009d72: 2bc0 cmp r3, #192 ; 0xc0 + 8009d74: d013 beq.n 8009d9e + 8009d76: 2bc0 cmp r3, #192 ; 0xc0 + 8009d78: d814 bhi.n 8009da4 + 8009d7a: 2b80 cmp r3, #128 ; 0x80 + 8009d7c: d009 beq.n 8009d92 + 8009d7e: 2b80 cmp r3, #128 ; 0x80 + 8009d80: d810 bhi.n 8009da4 + 8009d82: 2b00 cmp r3, #0 + 8009d84: d002 beq.n 8009d8c + 8009d86: 2b40 cmp r3, #64 ; 0x40 + 8009d88: d006 beq.n 8009d98 + 8009d8a: e00b b.n 8009da4 + 8009d8c: 2300 movs r3, #0 + 8009d8e: 77fb strb r3, [r7, #31] + 8009d90: e0cc b.n 8009f2c + 8009d92: 2302 movs r3, #2 + 8009d94: 77fb strb r3, [r7, #31] + 8009d96: e0c9 b.n 8009f2c + 8009d98: 2304 movs r3, #4 + 8009d9a: 77fb strb r3, [r7, #31] + 8009d9c: e0c6 b.n 8009f2c + 8009d9e: 2308 movs r3, #8 + 8009da0: 77fb strb r3, [r7, #31] + 8009da2: e0c3 b.n 8009f2c + 8009da4: 2310 movs r3, #16 + 8009da6: 77fb strb r3, [r7, #31] + 8009da8: e0c0 b.n 8009f2c + 8009daa: 687b ldr r3, [r7, #4] + 8009dac: 681b ldr r3, [r3, #0] + 8009dae: 4a44 ldr r2, [pc, #272] ; (8009ec0 ) + 8009db0: 4293 cmp r3, r2 + 8009db2: d125 bne.n 8009e00 + 8009db4: 4b3e ldr r3, [pc, #248] ; (8009eb0 ) + 8009db6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009dba: f403 7340 and.w r3, r3, #768 ; 0x300 + 8009dbe: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8009dc2: d017 beq.n 8009df4 + 8009dc4: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8009dc8: d817 bhi.n 8009dfa + 8009dca: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8009dce: d00b beq.n 8009de8 + 8009dd0: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8009dd4: d811 bhi.n 8009dfa + 8009dd6: 2b00 cmp r3, #0 + 8009dd8: d003 beq.n 8009de2 + 8009dda: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8009dde: d006 beq.n 8009dee + 8009de0: e00b b.n 8009dfa + 8009de2: 2300 movs r3, #0 + 8009de4: 77fb strb r3, [r7, #31] + 8009de6: e0a1 b.n 8009f2c + 8009de8: 2302 movs r3, #2 + 8009dea: 77fb strb r3, [r7, #31] + 8009dec: e09e b.n 8009f2c + 8009dee: 2304 movs r3, #4 + 8009df0: 77fb strb r3, [r7, #31] + 8009df2: e09b b.n 8009f2c + 8009df4: 2308 movs r3, #8 + 8009df6: 77fb strb r3, [r7, #31] + 8009df8: e098 b.n 8009f2c + 8009dfa: 2310 movs r3, #16 + 8009dfc: 77fb strb r3, [r7, #31] + 8009dfe: e095 b.n 8009f2c + 8009e00: 687b ldr r3, [r7, #4] + 8009e02: 681b ldr r3, [r3, #0] + 8009e04: 4a2f ldr r2, [pc, #188] ; (8009ec4 ) + 8009e06: 4293 cmp r3, r2 + 8009e08: d125 bne.n 8009e56 + 8009e0a: 4b29 ldr r3, [pc, #164] ; (8009eb0 ) + 8009e0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009e10: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 8009e14: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8009e18: d017 beq.n 8009e4a + 8009e1a: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8009e1e: d817 bhi.n 8009e50 + 8009e20: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8009e24: d00b beq.n 8009e3e + 8009e26: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8009e2a: d811 bhi.n 8009e50 + 8009e2c: 2b00 cmp r3, #0 + 8009e2e: d003 beq.n 8009e38 + 8009e30: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8009e34: d006 beq.n 8009e44 + 8009e36: e00b b.n 8009e50 + 8009e38: 2301 movs r3, #1 + 8009e3a: 77fb strb r3, [r7, #31] + 8009e3c: e076 b.n 8009f2c + 8009e3e: 2302 movs r3, #2 + 8009e40: 77fb strb r3, [r7, #31] + 8009e42: e073 b.n 8009f2c + 8009e44: 2304 movs r3, #4 + 8009e46: 77fb strb r3, [r7, #31] + 8009e48: e070 b.n 8009f2c + 8009e4a: 2308 movs r3, #8 + 8009e4c: 77fb strb r3, [r7, #31] + 8009e4e: e06d b.n 8009f2c + 8009e50: 2310 movs r3, #16 + 8009e52: 77fb strb r3, [r7, #31] + 8009e54: e06a b.n 8009f2c + 8009e56: 687b ldr r3, [r7, #4] + 8009e58: 681b ldr r3, [r3, #0] + 8009e5a: 4a1b ldr r2, [pc, #108] ; (8009ec8 ) + 8009e5c: 4293 cmp r3, r2 + 8009e5e: d138 bne.n 8009ed2 + 8009e60: 4b13 ldr r3, [pc, #76] ; (8009eb0 ) + 8009e62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009e66: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 8009e6a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8009e6e: d017 beq.n 8009ea0 + 8009e70: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8009e74: d82a bhi.n 8009ecc + 8009e76: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8009e7a: d00b beq.n 8009e94 + 8009e7c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8009e80: d824 bhi.n 8009ecc + 8009e82: 2b00 cmp r3, #0 + 8009e84: d003 beq.n 8009e8e + 8009e86: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8009e8a: d006 beq.n 8009e9a + 8009e8c: e01e b.n 8009ecc + 8009e8e: 2300 movs r3, #0 + 8009e90: 77fb strb r3, [r7, #31] + 8009e92: e04b b.n 8009f2c + 8009e94: 2302 movs r3, #2 + 8009e96: 77fb strb r3, [r7, #31] + 8009e98: e048 b.n 8009f2c + 8009e9a: 2304 movs r3, #4 + 8009e9c: 77fb strb r3, [r7, #31] + 8009e9e: e045 b.n 8009f2c + 8009ea0: 2308 movs r3, #8 + 8009ea2: 77fb strb r3, [r7, #31] + 8009ea4: e042 b.n 8009f2c + 8009ea6: bf00 nop + 8009ea8: efff69f3 .word 0xefff69f3 + 8009eac: 40011000 .word 0x40011000 + 8009eb0: 40023800 .word 0x40023800 + 8009eb4: 40004400 .word 0x40004400 + 8009eb8: 40004800 .word 0x40004800 + 8009ebc: 40004c00 .word 0x40004c00 + 8009ec0: 40005000 .word 0x40005000 + 8009ec4: 40011400 .word 0x40011400 + 8009ec8: 40007800 .word 0x40007800 + 8009ecc: 2310 movs r3, #16 + 8009ece: 77fb strb r3, [r7, #31] + 8009ed0: e02c b.n 8009f2c + 8009ed2: 687b ldr r3, [r7, #4] + 8009ed4: 681b ldr r3, [r3, #0] + 8009ed6: 4a72 ldr r2, [pc, #456] ; (800a0a0 ) + 8009ed8: 4293 cmp r3, r2 + 8009eda: d125 bne.n 8009f28 + 8009edc: 4b71 ldr r3, [pc, #452] ; (800a0a4 ) + 8009ede: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009ee2: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8009ee6: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8009eea: d017 beq.n 8009f1c + 8009eec: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8009ef0: d817 bhi.n 8009f22 + 8009ef2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8009ef6: d00b beq.n 8009f10 + 8009ef8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8009efc: d811 bhi.n 8009f22 + 8009efe: 2b00 cmp r3, #0 + 8009f00: d003 beq.n 8009f0a + 8009f02: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8009f06: d006 beq.n 8009f16 + 8009f08: e00b b.n 8009f22 + 8009f0a: 2300 movs r3, #0 + 8009f0c: 77fb strb r3, [r7, #31] + 8009f0e: e00d b.n 8009f2c + 8009f10: 2302 movs r3, #2 + 8009f12: 77fb strb r3, [r7, #31] + 8009f14: e00a b.n 8009f2c + 8009f16: 2304 movs r3, #4 + 8009f18: 77fb strb r3, [r7, #31] + 8009f1a: e007 b.n 8009f2c + 8009f1c: 2308 movs r3, #8 + 8009f1e: 77fb strb r3, [r7, #31] + 8009f20: e004 b.n 8009f2c + 8009f22: 2310 movs r3, #16 + 8009f24: 77fb strb r3, [r7, #31] + 8009f26: e001 b.n 8009f2c + 8009f28: 2310 movs r3, #16 + 8009f2a: 77fb strb r3, [r7, #31] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8009f2c: 687b ldr r3, [r7, #4] + 8009f2e: 69db ldr r3, [r3, #28] + 8009f30: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8009f34: d15b bne.n 8009fee + { + switch (clocksource) + 8009f36: 7ffb ldrb r3, [r7, #31] + 8009f38: 2b08 cmp r3, #8 + 8009f3a: d828 bhi.n 8009f8e + 8009f3c: a201 add r2, pc, #4 ; (adr r2, 8009f44 ) + 8009f3e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009f42: bf00 nop + 8009f44: 08009f69 .word 0x08009f69 + 8009f48: 08009f71 .word 0x08009f71 + 8009f4c: 08009f79 .word 0x08009f79 + 8009f50: 08009f8f .word 0x08009f8f + 8009f54: 08009f7f .word 0x08009f7f + 8009f58: 08009f8f .word 0x08009f8f + 8009f5c: 08009f8f .word 0x08009f8f + 8009f60: 08009f8f .word 0x08009f8f + 8009f64: 08009f87 .word 0x08009f87 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8009f68: f7fe f9c2 bl 80082f0 + 8009f6c: 61b8 str r0, [r7, #24] + break; + 8009f6e: e013 b.n 8009f98 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8009f70: f7fe f9d2 bl 8008318 + 8009f74: 61b8 str r0, [r7, #24] + break; + 8009f76: e00f b.n 8009f98 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8009f78: 4b4b ldr r3, [pc, #300] ; (800a0a8 ) + 8009f7a: 61bb str r3, [r7, #24] + break; + 8009f7c: e00c b.n 8009f98 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8009f7e: f7fe f8e5 bl 800814c + 8009f82: 61b8 str r0, [r7, #24] + break; + 8009f84: e008 b.n 8009f98 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8009f86: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8009f8a: 61bb str r3, [r7, #24] + break; + 8009f8c: e004 b.n 8009f98 + default: + pclk = 0U; + 8009f8e: 2300 movs r3, #0 + 8009f90: 61bb str r3, [r7, #24] + ret = HAL_ERROR; + 8009f92: 2301 movs r3, #1 + 8009f94: 77bb strb r3, [r7, #30] + break; + 8009f96: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 8009f98: 69bb ldr r3, [r7, #24] + 8009f9a: 2b00 cmp r3, #0 + 8009f9c: d074 beq.n 800a088 + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 8009f9e: 69bb ldr r3, [r7, #24] + 8009fa0: 005a lsls r2, r3, #1 + 8009fa2: 687b ldr r3, [r7, #4] + 8009fa4: 685b ldr r3, [r3, #4] + 8009fa6: 085b lsrs r3, r3, #1 + 8009fa8: 441a add r2, r3 + 8009faa: 687b ldr r3, [r7, #4] + 8009fac: 685b ldr r3, [r3, #4] + 8009fae: fbb2 f3f3 udiv r3, r2, r3 + 8009fb2: 613b str r3, [r7, #16] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8009fb4: 693b ldr r3, [r7, #16] + 8009fb6: 2b0f cmp r3, #15 + 8009fb8: d916 bls.n 8009fe8 + 8009fba: 693b ldr r3, [r7, #16] + 8009fbc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8009fc0: d212 bcs.n 8009fe8 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 8009fc2: 693b ldr r3, [r7, #16] + 8009fc4: b29b uxth r3, r3 + 8009fc6: f023 030f bic.w r3, r3, #15 + 8009fca: 81fb strh r3, [r7, #14] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8009fcc: 693b ldr r3, [r7, #16] + 8009fce: 085b lsrs r3, r3, #1 + 8009fd0: b29b uxth r3, r3 + 8009fd2: f003 0307 and.w r3, r3, #7 + 8009fd6: b29a uxth r2, r3 + 8009fd8: 89fb ldrh r3, [r7, #14] + 8009fda: 4313 orrs r3, r2 + 8009fdc: 81fb strh r3, [r7, #14] + huart->Instance->BRR = brrtemp; + 8009fde: 687b ldr r3, [r7, #4] + 8009fe0: 681b ldr r3, [r3, #0] + 8009fe2: 89fa ldrh r2, [r7, #14] + 8009fe4: 60da str r2, [r3, #12] + 8009fe6: e04f b.n 800a088 + } + else + { + ret = HAL_ERROR; + 8009fe8: 2301 movs r3, #1 + 8009fea: 77bb strb r3, [r7, #30] + 8009fec: e04c b.n 800a088 + } + } + } + else + { + switch (clocksource) + 8009fee: 7ffb ldrb r3, [r7, #31] + 8009ff0: 2b08 cmp r3, #8 + 8009ff2: d828 bhi.n 800a046 + 8009ff4: a201 add r2, pc, #4 ; (adr r2, 8009ffc ) + 8009ff6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009ffa: bf00 nop + 8009ffc: 0800a021 .word 0x0800a021 + 800a000: 0800a029 .word 0x0800a029 + 800a004: 0800a031 .word 0x0800a031 + 800a008: 0800a047 .word 0x0800a047 + 800a00c: 0800a037 .word 0x0800a037 + 800a010: 0800a047 .word 0x0800a047 + 800a014: 0800a047 .word 0x0800a047 + 800a018: 0800a047 .word 0x0800a047 + 800a01c: 0800a03f .word 0x0800a03f + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 800a020: f7fe f966 bl 80082f0 + 800a024: 61b8 str r0, [r7, #24] + break; + 800a026: e013 b.n 800a050 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 800a028: f7fe f976 bl 8008318 + 800a02c: 61b8 str r0, [r7, #24] + break; + 800a02e: e00f b.n 800a050 + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 800a030: 4b1d ldr r3, [pc, #116] ; (800a0a8 ) + 800a032: 61bb str r3, [r7, #24] + break; + 800a034: e00c b.n 800a050 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800a036: f7fe f889 bl 800814c + 800a03a: 61b8 str r0, [r7, #24] + break; + 800a03c: e008 b.n 800a050 + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 800a03e: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800a042: 61bb str r3, [r7, #24] + break; + 800a044: e004 b.n 800a050 + default: + pclk = 0U; + 800a046: 2300 movs r3, #0 + 800a048: 61bb str r3, [r7, #24] + ret = HAL_ERROR; + 800a04a: 2301 movs r3, #1 + 800a04c: 77bb strb r3, [r7, #30] + break; + 800a04e: bf00 nop + } + + if (pclk != 0U) + 800a050: 69bb ldr r3, [r7, #24] + 800a052: 2b00 cmp r3, #0 + 800a054: d018 beq.n 800a088 + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 800a056: 687b ldr r3, [r7, #4] + 800a058: 685b ldr r3, [r3, #4] + 800a05a: 085a lsrs r2, r3, #1 + 800a05c: 69bb ldr r3, [r7, #24] + 800a05e: 441a add r2, r3 + 800a060: 687b ldr r3, [r7, #4] + 800a062: 685b ldr r3, [r3, #4] + 800a064: fbb2 f3f3 udiv r3, r2, r3 + 800a068: 613b str r3, [r7, #16] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800a06a: 693b ldr r3, [r7, #16] + 800a06c: 2b0f cmp r3, #15 + 800a06e: d909 bls.n 800a084 + 800a070: 693b ldr r3, [r7, #16] + 800a072: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800a076: d205 bcs.n 800a084 + { + huart->Instance->BRR = (uint16_t)usartdiv; + 800a078: 693b ldr r3, [r7, #16] + 800a07a: b29a uxth r2, r3 + 800a07c: 687b ldr r3, [r7, #4] + 800a07e: 681b ldr r3, [r3, #0] + 800a080: 60da str r2, [r3, #12] + 800a082: e001 b.n 800a088 + } + else + { + ret = HAL_ERROR; + 800a084: 2301 movs r3, #1 + 800a086: 77bb strb r3, [r7, #30] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 800a088: 687b ldr r3, [r7, #4] + 800a08a: 2200 movs r2, #0 + 800a08c: 669a str r2, [r3, #104] ; 0x68 + huart->TxISR = NULL; + 800a08e: 687b ldr r3, [r7, #4] + 800a090: 2200 movs r2, #0 + 800a092: 66da str r2, [r3, #108] ; 0x6c + + return ret; + 800a094: 7fbb ldrb r3, [r7, #30] +} + 800a096: 4618 mov r0, r3 + 800a098: 3720 adds r7, #32 + 800a09a: 46bd mov sp, r7 + 800a09c: bd80 pop {r7, pc} + 800a09e: bf00 nop + 800a0a0: 40007c00 .word 0x40007c00 + 800a0a4: 40023800 .word 0x40023800 + 800a0a8: 00f42400 .word 0x00f42400 + +0800a0ac : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 800a0ac: b480 push {r7} + 800a0ae: b083 sub sp, #12 + 800a0b0: af00 add r7, sp, #0 + 800a0b2: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 800a0b4: 687b ldr r3, [r7, #4] + 800a0b6: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a0b8: f003 0301 and.w r3, r3, #1 + 800a0bc: 2b00 cmp r3, #0 + 800a0be: d00a beq.n 800a0d6 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800a0c0: 687b ldr r3, [r7, #4] + 800a0c2: 681b ldr r3, [r3, #0] + 800a0c4: 685b ldr r3, [r3, #4] + 800a0c6: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 800a0ca: 687b ldr r3, [r7, #4] + 800a0cc: 6a9a ldr r2, [r3, #40] ; 0x28 + 800a0ce: 687b ldr r3, [r7, #4] + 800a0d0: 681b ldr r3, [r3, #0] + 800a0d2: 430a orrs r2, r1 + 800a0d4: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 800a0d6: 687b ldr r3, [r7, #4] + 800a0d8: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a0da: f003 0302 and.w r3, r3, #2 + 800a0de: 2b00 cmp r3, #0 + 800a0e0: d00a beq.n 800a0f8 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 800a0e2: 687b ldr r3, [r7, #4] + 800a0e4: 681b ldr r3, [r3, #0] + 800a0e6: 685b ldr r3, [r3, #4] + 800a0e8: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 800a0ec: 687b ldr r3, [r7, #4] + 800a0ee: 6ada ldr r2, [r3, #44] ; 0x2c + 800a0f0: 687b ldr r3, [r7, #4] + 800a0f2: 681b ldr r3, [r3, #0] + 800a0f4: 430a orrs r2, r1 + 800a0f6: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 800a0f8: 687b ldr r3, [r7, #4] + 800a0fa: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a0fc: f003 0304 and.w r3, r3, #4 + 800a100: 2b00 cmp r3, #0 + 800a102: d00a beq.n 800a11a + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 800a104: 687b ldr r3, [r7, #4] + 800a106: 681b ldr r3, [r3, #0] + 800a108: 685b ldr r3, [r3, #4] + 800a10a: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800a10e: 687b ldr r3, [r7, #4] + 800a110: 6b1a ldr r2, [r3, #48] ; 0x30 + 800a112: 687b ldr r3, [r7, #4] + 800a114: 681b ldr r3, [r3, #0] + 800a116: 430a orrs r2, r1 + 800a118: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 800a11a: 687b ldr r3, [r7, #4] + 800a11c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a11e: f003 0308 and.w r3, r3, #8 + 800a122: 2b00 cmp r3, #0 + 800a124: d00a beq.n 800a13c + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 800a126: 687b ldr r3, [r7, #4] + 800a128: 681b ldr r3, [r3, #0] + 800a12a: 685b ldr r3, [r3, #4] + 800a12c: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 800a130: 687b ldr r3, [r7, #4] + 800a132: 6b5a ldr r2, [r3, #52] ; 0x34 + 800a134: 687b ldr r3, [r7, #4] + 800a136: 681b ldr r3, [r3, #0] + 800a138: 430a orrs r2, r1 + 800a13a: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 800a13c: 687b ldr r3, [r7, #4] + 800a13e: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a140: f003 0310 and.w r3, r3, #16 + 800a144: 2b00 cmp r3, #0 + 800a146: d00a beq.n 800a15e + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 800a148: 687b ldr r3, [r7, #4] + 800a14a: 681b ldr r3, [r3, #0] + 800a14c: 689b ldr r3, [r3, #8] + 800a14e: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 800a152: 687b ldr r3, [r7, #4] + 800a154: 6b9a ldr r2, [r3, #56] ; 0x38 + 800a156: 687b ldr r3, [r7, #4] + 800a158: 681b ldr r3, [r3, #0] + 800a15a: 430a orrs r2, r1 + 800a15c: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 800a15e: 687b ldr r3, [r7, #4] + 800a160: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a162: f003 0320 and.w r3, r3, #32 + 800a166: 2b00 cmp r3, #0 + 800a168: d00a beq.n 800a180 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 800a16a: 687b ldr r3, [r7, #4] + 800a16c: 681b ldr r3, [r3, #0] + 800a16e: 689b ldr r3, [r3, #8] + 800a170: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 800a174: 687b ldr r3, [r7, #4] + 800a176: 6bda ldr r2, [r3, #60] ; 0x3c + 800a178: 687b ldr r3, [r7, #4] + 800a17a: 681b ldr r3, [r3, #0] + 800a17c: 430a orrs r2, r1 + 800a17e: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 800a180: 687b ldr r3, [r7, #4] + 800a182: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a184: f003 0340 and.w r3, r3, #64 ; 0x40 + 800a188: 2b00 cmp r3, #0 + 800a18a: d01a beq.n 800a1c2 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 800a18c: 687b ldr r3, [r7, #4] + 800a18e: 681b ldr r3, [r3, #0] + 800a190: 685b ldr r3, [r3, #4] + 800a192: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 800a196: 687b ldr r3, [r7, #4] + 800a198: 6c1a ldr r2, [r3, #64] ; 0x40 + 800a19a: 687b ldr r3, [r7, #4] + 800a19c: 681b ldr r3, [r3, #0] + 800a19e: 430a orrs r2, r1 + 800a1a0: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 800a1a2: 687b ldr r3, [r7, #4] + 800a1a4: 6c1b ldr r3, [r3, #64] ; 0x40 + 800a1a6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800a1aa: d10a bne.n 800a1c2 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 800a1ac: 687b ldr r3, [r7, #4] + 800a1ae: 681b ldr r3, [r3, #0] + 800a1b0: 685b ldr r3, [r3, #4] + 800a1b2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 800a1b6: 687b ldr r3, [r7, #4] + 800a1b8: 6c5a ldr r2, [r3, #68] ; 0x44 + 800a1ba: 687b ldr r3, [r7, #4] + 800a1bc: 681b ldr r3, [r3, #0] + 800a1be: 430a orrs r2, r1 + 800a1c0: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 800a1c2: 687b ldr r3, [r7, #4] + 800a1c4: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a1c6: f003 0380 and.w r3, r3, #128 ; 0x80 + 800a1ca: 2b00 cmp r3, #0 + 800a1cc: d00a beq.n 800a1e4 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 800a1ce: 687b ldr r3, [r7, #4] + 800a1d0: 681b ldr r3, [r3, #0] + 800a1d2: 685b ldr r3, [r3, #4] + 800a1d4: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 800a1d8: 687b ldr r3, [r7, #4] + 800a1da: 6c9a ldr r2, [r3, #72] ; 0x48 + 800a1dc: 687b ldr r3, [r7, #4] + 800a1de: 681b ldr r3, [r3, #0] + 800a1e0: 430a orrs r2, r1 + 800a1e2: 605a str r2, [r3, #4] + } +} + 800a1e4: bf00 nop + 800a1e6: 370c adds r7, #12 + 800a1e8: 46bd mov sp, r7 + 800a1ea: f85d 7b04 ldr.w r7, [sp], #4 + 800a1ee: 4770 bx lr + +0800a1f0 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 800a1f0: b580 push {r7, lr} + 800a1f2: b086 sub sp, #24 + 800a1f4: af02 add r7, sp, #8 + 800a1f6: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800a1f8: 687b ldr r3, [r7, #4] + 800a1fa: 2200 movs r2, #0 + 800a1fc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 800a200: f7fa fb38 bl 8004874 + 800a204: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 800a206: 687b ldr r3, [r7, #4] + 800a208: 681b ldr r3, [r3, #0] + 800a20a: 681b ldr r3, [r3, #0] + 800a20c: f003 0308 and.w r3, r3, #8 + 800a210: 2b08 cmp r3, #8 + 800a212: d10e bne.n 800a232 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 800a214: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 800a218: 9300 str r3, [sp, #0] + 800a21a: 68fb ldr r3, [r7, #12] + 800a21c: 2200 movs r2, #0 + 800a21e: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 800a222: 6878 ldr r0, [r7, #4] + 800a224: f000 f81b bl 800a25e + 800a228: 4603 mov r3, r0 + 800a22a: 2b00 cmp r3, #0 + 800a22c: d001 beq.n 800a232 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 800a22e: 2303 movs r3, #3 + 800a230: e011 b.n 800a256 + } + } +#endif /* USART_ISR_REACK */ + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 800a232: 687b ldr r3, [r7, #4] + 800a234: 2220 movs r2, #32 + 800a236: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_READY; + 800a238: 687b ldr r3, [r7, #4] + 800a23a: 2220 movs r2, #32 + 800a23c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 800a240: 687b ldr r3, [r7, #4] + 800a242: 2200 movs r2, #0 + 800a244: 661a str r2, [r3, #96] ; 0x60 + huart->RxEventType = HAL_UART_RXEVENT_TC; + 800a246: 687b ldr r3, [r7, #4] + 800a248: 2200 movs r2, #0 + 800a24a: 665a str r2, [r3, #100] ; 0x64 + + __HAL_UNLOCK(huart); + 800a24c: 687b ldr r3, [r7, #4] + 800a24e: 2200 movs r2, #0 + 800a250: f883 2078 strb.w r2, [r3, #120] ; 0x78 + + return HAL_OK; + 800a254: 2300 movs r3, #0 +} + 800a256: 4618 mov r0, r3 + 800a258: 3710 adds r7, #16 + 800a25a: 46bd mov sp, r7 + 800a25c: bd80 pop {r7, pc} + +0800a25e : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 800a25e: b580 push {r7, lr} + 800a260: b09c sub sp, #112 ; 0x70 + 800a262: af00 add r7, sp, #0 + 800a264: 60f8 str r0, [r7, #12] + 800a266: 60b9 str r1, [r7, #8] + 800a268: 603b str r3, [r7, #0] + 800a26a: 4613 mov r3, r2 + 800a26c: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 800a26e: e0a7 b.n 800a3c0 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 800a270: 6fbb ldr r3, [r7, #120] ; 0x78 + 800a272: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800a276: f000 80a3 beq.w 800a3c0 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800a27a: f7fa fafb bl 8004874 + 800a27e: 4602 mov r2, r0 + 800a280: 683b ldr r3, [r7, #0] + 800a282: 1ad3 subs r3, r2, r3 + 800a284: 6fba ldr r2, [r7, #120] ; 0x78 + 800a286: 429a cmp r2, r3 + 800a288: d302 bcc.n 800a290 + 800a28a: 6fbb ldr r3, [r7, #120] ; 0x78 + 800a28c: 2b00 cmp r3, #0 + 800a28e: d13f bne.n 800a310 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800a290: 68fb ldr r3, [r7, #12] + 800a292: 681b ldr r3, [r3, #0] + 800a294: 653b str r3, [r7, #80] ; 0x50 + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800a296: 6d3b ldr r3, [r7, #80] ; 0x50 + 800a298: e853 3f00 ldrex r3, [r3] + 800a29c: 64fb str r3, [r7, #76] ; 0x4c + return(result); + 800a29e: 6cfb ldr r3, [r7, #76] ; 0x4c + 800a2a0: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 800a2a4: 667b str r3, [r7, #100] ; 0x64 + 800a2a6: 68fb ldr r3, [r7, #12] + 800a2a8: 681b ldr r3, [r3, #0] + 800a2aa: 461a mov r2, r3 + 800a2ac: 6e7b ldr r3, [r7, #100] ; 0x64 + 800a2ae: 65fb str r3, [r7, #92] ; 0x5c + 800a2b0: 65ba str r2, [r7, #88] ; 0x58 + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800a2b2: 6db9 ldr r1, [r7, #88] ; 0x58 + 800a2b4: 6dfa ldr r2, [r7, #92] ; 0x5c + 800a2b6: e841 2300 strex r3, r2, [r1] + 800a2ba: 657b str r3, [r7, #84] ; 0x54 + return(result); + 800a2bc: 6d7b ldr r3, [r7, #84] ; 0x54 + 800a2be: 2b00 cmp r3, #0 + 800a2c0: d1e6 bne.n 800a290 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800a2c2: 68fb ldr r3, [r7, #12] + 800a2c4: 681b ldr r3, [r3, #0] + 800a2c6: 3308 adds r3, #8 + 800a2c8: 63fb str r3, [r7, #60] ; 0x3c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800a2ca: 6bfb ldr r3, [r7, #60] ; 0x3c + 800a2cc: e853 3f00 ldrex r3, [r3] + 800a2d0: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 800a2d2: 6bbb ldr r3, [r7, #56] ; 0x38 + 800a2d4: f023 0301 bic.w r3, r3, #1 + 800a2d8: 663b str r3, [r7, #96] ; 0x60 + 800a2da: 68fb ldr r3, [r7, #12] + 800a2dc: 681b ldr r3, [r3, #0] + 800a2de: 3308 adds r3, #8 + 800a2e0: 6e3a ldr r2, [r7, #96] ; 0x60 + 800a2e2: 64ba str r2, [r7, #72] ; 0x48 + 800a2e4: 647b str r3, [r7, #68] ; 0x44 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800a2e6: 6c79 ldr r1, [r7, #68] ; 0x44 + 800a2e8: 6cba ldr r2, [r7, #72] ; 0x48 + 800a2ea: e841 2300 strex r3, r2, [r1] + 800a2ee: 643b str r3, [r7, #64] ; 0x40 + return(result); + 800a2f0: 6c3b ldr r3, [r7, #64] ; 0x40 + 800a2f2: 2b00 cmp r3, #0 + 800a2f4: d1e5 bne.n 800a2c2 + + huart->gState = HAL_UART_STATE_READY; + 800a2f6: 68fb ldr r3, [r7, #12] + 800a2f8: 2220 movs r2, #32 + 800a2fa: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_READY; + 800a2fc: 68fb ldr r3, [r7, #12] + 800a2fe: 2220 movs r2, #32 + 800a300: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + + __HAL_UNLOCK(huart); + 800a304: 68fb ldr r3, [r7, #12] + 800a306: 2200 movs r2, #0 + 800a308: f883 2078 strb.w r2, [r3, #120] ; 0x78 + + return HAL_TIMEOUT; + 800a30c: 2303 movs r3, #3 + 800a30e: e068 b.n 800a3e2 + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + 800a310: 68fb ldr r3, [r7, #12] + 800a312: 681b ldr r3, [r3, #0] + 800a314: 681b ldr r3, [r3, #0] + 800a316: f003 0304 and.w r3, r3, #4 + 800a31a: 2b00 cmp r3, #0 + 800a31c: d050 beq.n 800a3c0 + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 800a31e: 68fb ldr r3, [r7, #12] + 800a320: 681b ldr r3, [r3, #0] + 800a322: 69db ldr r3, [r3, #28] + 800a324: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800a328: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800a32c: d148 bne.n 800a3c0 + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 800a32e: 68fb ldr r3, [r7, #12] + 800a330: 681b ldr r3, [r3, #0] + 800a332: f44f 6200 mov.w r2, #2048 ; 0x800 + 800a336: 621a str r2, [r3, #32] + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800a338: 68fb ldr r3, [r7, #12] + 800a33a: 681b ldr r3, [r3, #0] + 800a33c: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800a33e: 6abb ldr r3, [r7, #40] ; 0x28 + 800a340: e853 3f00 ldrex r3, [r3] + 800a344: 627b str r3, [r7, #36] ; 0x24 + return(result); + 800a346: 6a7b ldr r3, [r7, #36] ; 0x24 + 800a348: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 800a34c: 66fb str r3, [r7, #108] ; 0x6c + 800a34e: 68fb ldr r3, [r7, #12] + 800a350: 681b ldr r3, [r3, #0] + 800a352: 461a mov r2, r3 + 800a354: 6efb ldr r3, [r7, #108] ; 0x6c + 800a356: 637b str r3, [r7, #52] ; 0x34 + 800a358: 633a str r2, [r7, #48] ; 0x30 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800a35a: 6b39 ldr r1, [r7, #48] ; 0x30 + 800a35c: 6b7a ldr r2, [r7, #52] ; 0x34 + 800a35e: e841 2300 strex r3, r2, [r1] + 800a362: 62fb str r3, [r7, #44] ; 0x2c + return(result); + 800a364: 6afb ldr r3, [r7, #44] ; 0x2c + 800a366: 2b00 cmp r3, #0 + 800a368: d1e6 bne.n 800a338 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800a36a: 68fb ldr r3, [r7, #12] + 800a36c: 681b ldr r3, [r3, #0] + 800a36e: 3308 adds r3, #8 + 800a370: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800a372: 697b ldr r3, [r7, #20] + 800a374: e853 3f00 ldrex r3, [r3] + 800a378: 613b str r3, [r7, #16] + return(result); + 800a37a: 693b ldr r3, [r7, #16] + 800a37c: f023 0301 bic.w r3, r3, #1 + 800a380: 66bb str r3, [r7, #104] ; 0x68 + 800a382: 68fb ldr r3, [r7, #12] + 800a384: 681b ldr r3, [r3, #0] + 800a386: 3308 adds r3, #8 + 800a388: 6eba ldr r2, [r7, #104] ; 0x68 + 800a38a: 623a str r2, [r7, #32] + 800a38c: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800a38e: 69f9 ldr r1, [r7, #28] + 800a390: 6a3a ldr r2, [r7, #32] + 800a392: e841 2300 strex r3, r2, [r1] + 800a396: 61bb str r3, [r7, #24] + return(result); + 800a398: 69bb ldr r3, [r7, #24] + 800a39a: 2b00 cmp r3, #0 + 800a39c: d1e5 bne.n 800a36a + + huart->gState = HAL_UART_STATE_READY; + 800a39e: 68fb ldr r3, [r7, #12] + 800a3a0: 2220 movs r2, #32 + 800a3a2: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_READY; + 800a3a4: 68fb ldr r3, [r7, #12] + 800a3a6: 2220 movs r2, #32 + 800a3a8: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + huart->ErrorCode = HAL_UART_ERROR_RTO; + 800a3ac: 68fb ldr r3, [r7, #12] + 800a3ae: 2220 movs r2, #32 + 800a3b0: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800a3b4: 68fb ldr r3, [r7, #12] + 800a3b6: 2200 movs r2, #0 + 800a3b8: f883 2078 strb.w r2, [r3, #120] ; 0x78 + + return HAL_TIMEOUT; + 800a3bc: 2303 movs r3, #3 + 800a3be: e010 b.n 800a3e2 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 800a3c0: 68fb ldr r3, [r7, #12] + 800a3c2: 681b ldr r3, [r3, #0] + 800a3c4: 69da ldr r2, [r3, #28] + 800a3c6: 68bb ldr r3, [r7, #8] + 800a3c8: 4013 ands r3, r2 + 800a3ca: 68ba ldr r2, [r7, #8] + 800a3cc: 429a cmp r2, r3 + 800a3ce: bf0c ite eq + 800a3d0: 2301 moveq r3, #1 + 800a3d2: 2300 movne r3, #0 + 800a3d4: b2db uxtb r3, r3 + 800a3d6: 461a mov r2, r3 + 800a3d8: 79fb ldrb r3, [r7, #7] + 800a3da: 429a cmp r2, r3 + 800a3dc: f43f af48 beq.w 800a270 + } + } + } + } + return HAL_OK; + 800a3e0: 2300 movs r3, #0 +} + 800a3e2: 4618 mov r0, r3 + 800a3e4: 3770 adds r7, #112 ; 0x70 + 800a3e6: 46bd mov sp, r7 + 800a3e8: bd80 pop {r7, pc} + ... + +0800a3ec : + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + 800a3ec: b480 push {r7} + 800a3ee: b083 sub sp, #12 + 800a3f0: af00 add r7, sp, #0 + 800a3f2: 6078 str r0, [r7, #4] + 800a3f4: 6039 str r1, [r7, #0] + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank == FMC_SDRAM_BANK1) + 800a3f6: 683b ldr r3, [r7, #0] + 800a3f8: 681b ldr r3, [r3, #0] + 800a3fa: 2b00 cmp r3, #0 + 800a3fc: d121 bne.n 800a442 + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + 800a3fe: 687b ldr r3, [r7, #4] + 800a400: 681a ldr r2, [r3, #0] + 800a402: 4b27 ldr r3, [pc, #156] ; (800a4a0 ) + 800a404: 4013 ands r3, r2 + 800a406: 683a ldr r2, [r7, #0] + 800a408: 6851 ldr r1, [r2, #4] + 800a40a: 683a ldr r2, [r7, #0] + 800a40c: 6892 ldr r2, [r2, #8] + 800a40e: 4311 orrs r1, r2 + 800a410: 683a ldr r2, [r7, #0] + 800a412: 68d2 ldr r2, [r2, #12] + 800a414: 4311 orrs r1, r2 + 800a416: 683a ldr r2, [r7, #0] + 800a418: 6912 ldr r2, [r2, #16] + 800a41a: 4311 orrs r1, r2 + 800a41c: 683a ldr r2, [r7, #0] + 800a41e: 6952 ldr r2, [r2, #20] + 800a420: 4311 orrs r1, r2 + 800a422: 683a ldr r2, [r7, #0] + 800a424: 6992 ldr r2, [r2, #24] + 800a426: 4311 orrs r1, r2 + 800a428: 683a ldr r2, [r7, #0] + 800a42a: 69d2 ldr r2, [r2, #28] + 800a42c: 4311 orrs r1, r2 + 800a42e: 683a ldr r2, [r7, #0] + 800a430: 6a12 ldr r2, [r2, #32] + 800a432: 4311 orrs r1, r2 + 800a434: 683a ldr r2, [r7, #0] + 800a436: 6a52 ldr r2, [r2, #36] ; 0x24 + 800a438: 430a orrs r2, r1 + 800a43a: 431a orrs r2, r3 + 800a43c: 687b ldr r3, [r7, #4] + 800a43e: 601a str r2, [r3, #0] + 800a440: e026 b.n 800a490 + Init->ReadBurst | + Init->ReadPipeDelay)); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + 800a442: 687b ldr r3, [r7, #4] + 800a444: 681b ldr r3, [r3, #0] + 800a446: f423 42f8 bic.w r2, r3, #31744 ; 0x7c00 + 800a44a: 683b ldr r3, [r7, #0] + 800a44c: 69d9 ldr r1, [r3, #28] + 800a44e: 683b ldr r3, [r7, #0] + 800a450: 6a1b ldr r3, [r3, #32] + 800a452: 4319 orrs r1, r3 + 800a454: 683b ldr r3, [r7, #0] + 800a456: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a458: 430b orrs r3, r1 + 800a45a: 431a orrs r2, r3 + 800a45c: 687b ldr r3, [r7, #4] + 800a45e: 601a str r2, [r3, #0] + FMC_SDCR1_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + 800a460: 687b ldr r3, [r7, #4] + 800a462: 685a ldr r2, [r3, #4] + 800a464: 4b0e ldr r3, [pc, #56] ; (800a4a0 ) + 800a466: 4013 ands r3, r2 + 800a468: 683a ldr r2, [r7, #0] + 800a46a: 6851 ldr r1, [r2, #4] + 800a46c: 683a ldr r2, [r7, #0] + 800a46e: 6892 ldr r2, [r2, #8] + 800a470: 4311 orrs r1, r2 + 800a472: 683a ldr r2, [r7, #0] + 800a474: 68d2 ldr r2, [r2, #12] + 800a476: 4311 orrs r1, r2 + 800a478: 683a ldr r2, [r7, #0] + 800a47a: 6912 ldr r2, [r2, #16] + 800a47c: 4311 orrs r1, r2 + 800a47e: 683a ldr r2, [r7, #0] + 800a480: 6952 ldr r2, [r2, #20] + 800a482: 4311 orrs r1, r2 + 800a484: 683a ldr r2, [r7, #0] + 800a486: 6992 ldr r2, [r2, #24] + 800a488: 430a orrs r2, r1 + 800a48a: 431a orrs r2, r3 + 800a48c: 687b ldr r3, [r7, #4] + 800a48e: 605a str r2, [r3, #4] + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); + } + + return HAL_OK; + 800a490: 2300 movs r3, #0 +} + 800a492: 4618 mov r0, r3 + 800a494: 370c adds r7, #12 + 800a496: 46bd mov sp, r7 + 800a498: f85d 7b04 ldr.w r7, [sp], #4 + 800a49c: 4770 bx lr + 800a49e: bf00 nop + 800a4a0: ffff8000 .word 0xffff8000 + +0800a4a4 : + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + 800a4a4: b480 push {r7} + 800a4a6: b085 sub sp, #20 + 800a4a8: af00 add r7, sp, #0 + 800a4aa: 60f8 str r0, [r7, #12] + 800a4ac: 60b9 str r1, [r7, #8] + 800a4ae: 607a str r2, [r7, #4] + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + 800a4b0: 687b ldr r3, [r7, #4] + 800a4b2: 2b00 cmp r3, #0 + 800a4b4: d128 bne.n 800a508 + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + 800a4b6: 68fb ldr r3, [r7, #12] + 800a4b8: 689b ldr r3, [r3, #8] + 800a4ba: f003 4270 and.w r2, r3, #4026531840 ; 0xf0000000 + 800a4be: 68bb ldr r3, [r7, #8] + 800a4c0: 681b ldr r3, [r3, #0] + 800a4c2: 1e59 subs r1, r3, #1 + 800a4c4: 68bb ldr r3, [r7, #8] + 800a4c6: 685b ldr r3, [r3, #4] + 800a4c8: 3b01 subs r3, #1 + 800a4ca: 011b lsls r3, r3, #4 + 800a4cc: 4319 orrs r1, r3 + 800a4ce: 68bb ldr r3, [r7, #8] + 800a4d0: 689b ldr r3, [r3, #8] + 800a4d2: 3b01 subs r3, #1 + 800a4d4: 021b lsls r3, r3, #8 + 800a4d6: 4319 orrs r1, r3 + 800a4d8: 68bb ldr r3, [r7, #8] + 800a4da: 68db ldr r3, [r3, #12] + 800a4dc: 3b01 subs r3, #1 + 800a4de: 031b lsls r3, r3, #12 + 800a4e0: 4319 orrs r1, r3 + 800a4e2: 68bb ldr r3, [r7, #8] + 800a4e4: 691b ldr r3, [r3, #16] + 800a4e6: 3b01 subs r3, #1 + 800a4e8: 041b lsls r3, r3, #16 + 800a4ea: 4319 orrs r1, r3 + 800a4ec: 68bb ldr r3, [r7, #8] + 800a4ee: 695b ldr r3, [r3, #20] + 800a4f0: 3b01 subs r3, #1 + 800a4f2: 051b lsls r3, r3, #20 + 800a4f4: 4319 orrs r1, r3 + 800a4f6: 68bb ldr r3, [r7, #8] + 800a4f8: 699b ldr r3, [r3, #24] + 800a4fa: 3b01 subs r3, #1 + 800a4fc: 061b lsls r3, r3, #24 + 800a4fe: 430b orrs r3, r1 + 800a500: 431a orrs r2, r3 + 800a502: 68fb ldr r3, [r7, #12] + 800a504: 609a str r2, [r3, #8] + 800a506: e02d b.n 800a564 + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + 800a508: 68fb ldr r3, [r7, #12] + 800a50a: 689a ldr r2, [r3, #8] + 800a50c: 4b19 ldr r3, [pc, #100] ; (800a574 ) + 800a50e: 4013 ands r3, r2 + 800a510: 68ba ldr r2, [r7, #8] + 800a512: 68d2 ldr r2, [r2, #12] + 800a514: 3a01 subs r2, #1 + 800a516: 0311 lsls r1, r2, #12 + 800a518: 68ba ldr r2, [r7, #8] + 800a51a: 6952 ldr r2, [r2, #20] + 800a51c: 3a01 subs r2, #1 + 800a51e: 0512 lsls r2, r2, #20 + 800a520: 430a orrs r2, r1 + 800a522: 431a orrs r2, r3 + 800a524: 68fb ldr r3, [r7, #12] + 800a526: 609a str r2, [r3, #8] + FMC_SDTR1_TRC | + FMC_SDTR1_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + 800a528: 68fb ldr r3, [r7, #12] + 800a52a: 68db ldr r3, [r3, #12] + 800a52c: f003 4270 and.w r2, r3, #4026531840 ; 0xf0000000 + 800a530: 68bb ldr r3, [r7, #8] + 800a532: 681b ldr r3, [r3, #0] + 800a534: 1e59 subs r1, r3, #1 + 800a536: 68bb ldr r3, [r7, #8] + 800a538: 685b ldr r3, [r3, #4] + 800a53a: 3b01 subs r3, #1 + 800a53c: 011b lsls r3, r3, #4 + 800a53e: 4319 orrs r1, r3 + 800a540: 68bb ldr r3, [r7, #8] + 800a542: 689b ldr r3, [r3, #8] + 800a544: 3b01 subs r3, #1 + 800a546: 021b lsls r3, r3, #8 + 800a548: 4319 orrs r1, r3 + 800a54a: 68bb ldr r3, [r7, #8] + 800a54c: 691b ldr r3, [r3, #16] + 800a54e: 3b01 subs r3, #1 + 800a550: 041b lsls r3, r3, #16 + 800a552: 4319 orrs r1, r3 + 800a554: 68bb ldr r3, [r7, #8] + 800a556: 699b ldr r3, [r3, #24] + 800a558: 3b01 subs r3, #1 + 800a55a: 061b lsls r3, r3, #24 + 800a55c: 430b orrs r3, r1 + 800a55e: 431a orrs r2, r3 + 800a560: 68fb ldr r3, [r7, #12] + 800a562: 60da str r2, [r3, #12] + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); + } + + return HAL_OK; + 800a564: 2300 movs r3, #0 +} + 800a566: 4618 mov r0, r3 + 800a568: 3714 adds r7, #20 + 800a56a: 46bd mov sp, r7 + 800a56c: f85d 7b04 ldr.w r7, [sp], #4 + 800a570: 4770 bx lr + 800a572: bf00 nop + 800a574: ff0f0fff .word 0xff0f0fff + +0800a578 : + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + 800a578: b480 push {r7} + 800a57a: b085 sub sp, #20 + 800a57c: af00 add r7, sp, #0 + 800a57e: 60f8 str r0, [r7, #12] + 800a580: 60b9 str r1, [r7, #8] + 800a582: 607a str r2, [r7, #4] + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + 800a584: 68fb ldr r3, [r7, #12] + 800a586: 691a ldr r2, [r3, #16] + 800a588: 4b0c ldr r3, [pc, #48] ; (800a5bc ) + 800a58a: 4013 ands r3, r2 + 800a58c: 68ba ldr r2, [r7, #8] + 800a58e: 6811 ldr r1, [r2, #0] + 800a590: 68ba ldr r2, [r7, #8] + 800a592: 6852 ldr r2, [r2, #4] + 800a594: 4311 orrs r1, r2 + 800a596: 68ba ldr r2, [r7, #8] + 800a598: 6892 ldr r2, [r2, #8] + 800a59a: 3a01 subs r2, #1 + 800a59c: 0152 lsls r2, r2, #5 + 800a59e: 4311 orrs r1, r2 + 800a5a0: 68ba ldr r2, [r7, #8] + 800a5a2: 68d2 ldr r2, [r2, #12] + 800a5a4: 0252 lsls r2, r2, #9 + 800a5a6: 430a orrs r2, r1 + 800a5a8: 431a orrs r2, r3 + 800a5aa: 68fb ldr r3, [r7, #12] + 800a5ac: 611a str r2, [r3, #16] + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + return HAL_OK; + 800a5ae: 2300 movs r3, #0 +} + 800a5b0: 4618 mov r0, r3 + 800a5b2: 3714 adds r7, #20 + 800a5b4: 46bd mov sp, r7 + 800a5b6: f85d 7b04 ldr.w r7, [sp], #4 + 800a5ba: 4770 bx lr + 800a5bc: ffc00000 .word 0xffc00000 + +0800a5c0 : + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + 800a5c0: b480 push {r7} + 800a5c2: b083 sub sp, #12 + 800a5c4: af00 add r7, sp, #0 + 800a5c6: 6078 str r0, [r7, #4] + 800a5c8: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); + 800a5ca: 687b ldr r3, [r7, #4] + 800a5cc: 695a ldr r2, [r3, #20] + 800a5ce: 4b07 ldr r3, [pc, #28] ; (800a5ec ) + 800a5d0: 4013 ands r3, r2 + 800a5d2: 683a ldr r2, [r7, #0] + 800a5d4: 0052 lsls r2, r2, #1 + 800a5d6: 431a orrs r2, r3 + 800a5d8: 687b ldr r3, [r7, #4] + 800a5da: 615a str r2, [r3, #20] + + return HAL_OK; + 800a5dc: 2300 movs r3, #0 +} + 800a5de: 4618 mov r0, r3 + 800a5e0: 370c adds r7, #12 + 800a5e2: 46bd mov sp, r7 + 800a5e4: f85d 7b04 ldr.w r7, [sp], #4 + 800a5e8: 4770 bx lr + 800a5ea: bf00 nop + 800a5ec: ffffc001 .word 0xffffc001 + +0800a5f0 : + +/** + * LwIP initialization function + */ +void MX_LWIP_Init(void) +{ + 800a5f0: b5b0 push {r4, r5, r7, lr} + 800a5f2: b08c sub sp, #48 ; 0x30 + 800a5f4: af04 add r7, sp, #16 + /* Initilialize the LwIP stack with RTOS */ + tcpip_init( NULL, NULL ); + 800a5f6: 2100 movs r1, #0 + 800a5f8: 2000 movs r0, #0 + 800a5fa: f003 fdcf bl 800e19c + + /* IP addresses initialization with DHCP (IPv4) */ + ipaddr.addr = 0; + 800a5fe: 4b20 ldr r3, [pc, #128] ; (800a680 ) + 800a600: 2200 movs r2, #0 + 800a602: 601a str r2, [r3, #0] + netmask.addr = 0; + 800a604: 4b1f ldr r3, [pc, #124] ; (800a684 ) + 800a606: 2200 movs r2, #0 + 800a608: 601a str r2, [r3, #0] + gw.addr = 0; + 800a60a: 4b1f ldr r3, [pc, #124] ; (800a688 ) + 800a60c: 2200 movs r2, #0 + 800a60e: 601a str r2, [r3, #0] + + /* add the network interface (IPv4/IPv6) with RTOS */ + netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, &tcpip_input); + 800a610: 4b1e ldr r3, [pc, #120] ; (800a68c ) + 800a612: 9302 str r3, [sp, #8] + 800a614: 4b1e ldr r3, [pc, #120] ; (800a690 ) + 800a616: 9301 str r3, [sp, #4] + 800a618: 2300 movs r3, #0 + 800a61a: 9300 str r3, [sp, #0] + 800a61c: 4b1a ldr r3, [pc, #104] ; (800a688 ) + 800a61e: 4a19 ldr r2, [pc, #100] ; (800a684 ) + 800a620: 4917 ldr r1, [pc, #92] ; (800a680 ) + 800a622: 481c ldr r0, [pc, #112] ; (800a694 ) + 800a624: f005 fb6e bl 800fd04 + + /* Registers the default network interface */ + netif_set_default(&gnetif); + 800a628: 481a ldr r0, [pc, #104] ; (800a694 ) + 800a62a: f005 fd25 bl 8010078 + + if (netif_is_link_up(&gnetif)) + 800a62e: 4b19 ldr r3, [pc, #100] ; (800a694 ) + 800a630: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 800a634: 089b lsrs r3, r3, #2 + 800a636: f003 0301 and.w r3, r3, #1 + 800a63a: b2db uxtb r3, r3 + 800a63c: 2b00 cmp r3, #0 + 800a63e: d003 beq.n 800a648 + { + /* When the netif is fully configured this function must be called */ + netif_set_up(&gnetif); + 800a640: 4814 ldr r0, [pc, #80] ; (800a694 ) + 800a642: f005 fd29 bl 8010098 + 800a646: e002 b.n 800a64e + } + else + { + /* When the netif link is down this function must be called */ + netif_set_down(&gnetif); + 800a648: 4812 ldr r0, [pc, #72] ; (800a694 ) + 800a64a: f005 fd91 bl 8010170 + } + + /* Set the link callback function, this function is called on change of link status*/ + netif_set_link_callback(&gnetif, ethernet_link_status_updated); + 800a64e: 4912 ldr r1, [pc, #72] ; (800a698 ) + 800a650: 4810 ldr r0, [pc, #64] ; (800a694 ) + 800a652: f005 fe27 bl 80102a4 + + /* Create the Ethernet link handler thread */ +/* USER CODE BEGIN H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ + osThreadDef(EthLink, ethernet_link_thread, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE *2); + 800a656: 4b11 ldr r3, [pc, #68] ; (800a69c ) + 800a658: 1d3c adds r4, r7, #4 + 800a65a: 461d mov r5, r3 + 800a65c: cd0f ldmia r5!, {r0, r1, r2, r3} + 800a65e: c40f stmia r4!, {r0, r1, r2, r3} + 800a660: e895 0007 ldmia.w r5, {r0, r1, r2} + 800a664: e884 0007 stmia.w r4, {r0, r1, r2} + osThreadCreate (osThread(EthLink), &gnetif); + 800a668: 1d3b adds r3, r7, #4 + 800a66a: 490a ldr r1, [pc, #40] ; (800a694 ) + 800a66c: 4618 mov r0, r3 + 800a66e: f000 fd25 bl 800b0bc +/* USER CODE END H7_OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ + + /* Start DHCP negotiation for a network interface (IPv4) */ + dhcp_start(&gnetif); + 800a672: 4808 ldr r0, [pc, #32] ; (800a694 ) + 800a674: f00d f9de bl 8017a34 + +/* USER CODE BEGIN 3 */ + +/* USER CODE END 3 */ +} + 800a678: bf00 nop + 800a67a: 3720 adds r7, #32 + 800a67c: 46bd mov sp, r7 + 800a67e: bdb0 pop {r4, r5, r7, pc} + 800a680: 200009e0 .word 0x200009e0 + 800a684: 200009e4 .word 0x200009e4 + 800a688: 200009e8 .word 0x200009e8 + 800a68c: 0800e0d9 .word 0x0800e0d9 + 800a690: 0800ab99 .word 0x0800ab99 + 800a694: 200009a8 .word 0x200009a8 + 800a698: 0800a6a1 .word 0x0800a6a1 + 800a69c: 0801e864 .word 0x0801e864 + +0800a6a0 : + * @brief Notify the User about the network interface config status + * @param netif: the network interface + * @retval None + */ +static void ethernet_link_status_updated(struct netif *netif) +{ + 800a6a0: b480 push {r7} + 800a6a2: b083 sub sp, #12 + 800a6a4: af00 add r7, sp, #0 + 800a6a6: 6078 str r0, [r7, #4] + else /* netif is down */ + { +/* USER CODE BEGIN 6 */ +/* USER CODE END 6 */ + } +} + 800a6a8: bf00 nop + 800a6aa: 370c adds r7, #12 + 800a6ac: 46bd mov sp, r7 + 800a6ae: f85d 7b04 ldr.w r7, [sp], #4 + 800a6b2: 4770 bx lr + +0800a6b4 : + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + 800a6b4: b480 push {r7} + 800a6b6: b087 sub sp, #28 + 800a6b8: af00 add r7, sp, #0 + 800a6ba: 6078 str r0, [r7, #4] + 800a6bc: 6039 str r1, [r7, #0] + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + 800a6be: 683b ldr r3, [r7, #0] + 800a6c0: 617b str r3, [r7, #20] + uint32_t op_addr = (uint32_t)addr; + 800a6c2: 687b ldr r3, [r7, #4] + 800a6c4: 613b str r3, [r7, #16] + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + 800a6c6: 2320 movs r3, #32 + 800a6c8: 60fb str r3, [r7, #12] + __ASM volatile ("dsb 0xF":::"memory"); + 800a6ca: f3bf 8f4f dsb sy +} + 800a6ce: bf00 nop + + __DSB(); + + while (op_size > 0) { + 800a6d0: e00b b.n 800a6ea + SCB->DCIMVAC = op_addr; + 800a6d2: 4a0d ldr r2, [pc, #52] ; (800a708 ) + 800a6d4: 693b ldr r3, [r7, #16] + 800a6d6: f8c2 325c str.w r3, [r2, #604] ; 0x25c + op_addr += (uint32_t)linesize; + 800a6da: 68fb ldr r3, [r7, #12] + 800a6dc: 693a ldr r2, [r7, #16] + 800a6de: 4413 add r3, r2 + 800a6e0: 613b str r3, [r7, #16] + op_size -= linesize; + 800a6e2: 697a ldr r2, [r7, #20] + 800a6e4: 68fb ldr r3, [r7, #12] + 800a6e6: 1ad3 subs r3, r2, r3 + 800a6e8: 617b str r3, [r7, #20] + while (op_size > 0) { + 800a6ea: 697b ldr r3, [r7, #20] + 800a6ec: 2b00 cmp r3, #0 + 800a6ee: dcf0 bgt.n 800a6d2 + __ASM volatile ("dsb 0xF":::"memory"); + 800a6f0: f3bf 8f4f dsb sy +} + 800a6f4: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 800a6f6: f3bf 8f6f isb sy +} + 800a6fa: bf00 nop + } + + __DSB(); + __ISB(); + #endif +} + 800a6fc: bf00 nop + 800a6fe: 371c adds r7, #28 + 800a700: 46bd mov sp, r7 + 800a702: f85d 7b04 ldr.w r7, [sp], #4 + 800a706: 4770 bx lr + 800a708: e000ed00 .word 0xe000ed00 + +0800a70c : + * @brief Ethernet Rx Transfer completed callback + * @param handlerEth: ETH handler + * @retval None + */ +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth) +{ + 800a70c: b580 push {r7, lr} + 800a70e: b082 sub sp, #8 + 800a710: af00 add r7, sp, #0 + 800a712: 6078 str r0, [r7, #4] + osSemaphoreRelease(RxPktSemaphore); + 800a714: 4b04 ldr r3, [pc, #16] ; (800a728 ) + 800a716: 681b ldr r3, [r3, #0] + 800a718: 4618 mov r0, r3 + 800a71a: f000 fe19 bl 800b350 +} + 800a71e: bf00 nop + 800a720: 3708 adds r7, #8 + 800a722: 46bd mov sp, r7 + 800a724: bd80 pop {r7, pc} + 800a726: bf00 nop + 800a728: 20005378 .word 0x20005378 + +0800a72c : + * @brief Ethernet Tx Transfer completed callback + * @param handlerEth: ETH handler + * @retval None + */ +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *handlerEth) +{ + 800a72c: b580 push {r7, lr} + 800a72e: b082 sub sp, #8 + 800a730: af00 add r7, sp, #0 + 800a732: 6078 str r0, [r7, #4] + osSemaphoreRelease(TxPktSemaphore); + 800a734: 4b04 ldr r3, [pc, #16] ; (800a748 ) + 800a736: 681b ldr r3, [r3, #0] + 800a738: 4618 mov r0, r3 + 800a73a: f000 fe09 bl 800b350 +} + 800a73e: bf00 nop + 800a740: 3708 adds r7, #8 + 800a742: 46bd mov sp, r7 + 800a744: bd80 pop {r7, pc} + 800a746: bf00 nop + 800a748: 2000537c .word 0x2000537c + +0800a74c : + * @brief Ethernet DMA transfer error callback + * @param handlerEth: ETH handler + * @retval None + */ +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *handlerEth) +{ + 800a74c: b580 push {r7, lr} + 800a74e: b082 sub sp, #8 + 800a750: af00 add r7, sp, #0 + 800a752: 6078 str r0, [r7, #4] + if((HAL_ETH_GetDMAError(handlerEth) & ETH_DMASR_RBUS) == ETH_DMASR_RBUS) + 800a754: 6878 ldr r0, [r7, #4] + 800a756: f7fb fc27 bl 8005fa8 + 800a75a: 4603 mov r3, r0 + 800a75c: f003 0380 and.w r3, r3, #128 ; 0x80 + 800a760: 2b80 cmp r3, #128 ; 0x80 + 800a762: d104 bne.n 800a76e + { + osSemaphoreRelease(RxPktSemaphore); + 800a764: 4b04 ldr r3, [pc, #16] ; (800a778 ) + 800a766: 681b ldr r3, [r3, #0] + 800a768: 4618 mov r0, r3 + 800a76a: f000 fdf1 bl 800b350 + } +} + 800a76e: bf00 nop + 800a770: 3708 adds r7, #8 + 800a772: 46bd mov sp, r7 + 800a774: bd80 pop {r7, pc} + 800a776: bf00 nop + 800a778: 20005378 .word 0x20005378 + +0800a77c : + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static void low_level_init(struct netif *netif) +{ + 800a77c: b5b0 push {r4, r5, r7, lr} + 800a77e: b0a8 sub sp, #160 ; 0xa0 + 800a780: af00 add r7, sp, #0 + 800a782: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_eth_init_status = HAL_OK; + 800a784: 2300 movs r3, #0 + 800a786: f887 3097 strb.w r3, [r7, #151] ; 0x97 + uint32_t duplex, speed = 0; + 800a78a: 2300 movs r3, #0 + 800a78c: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + int32_t PHYLinkState = 0; + 800a790: 2300 movs r3, #0 + 800a792: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + ETH_MACConfigTypeDef MACConf = {0}; + 800a796: f107 032c add.w r3, r7, #44 ; 0x2c + 800a79a: 2264 movs r2, #100 ; 0x64 + 800a79c: 2100 movs r1, #0 + 800a79e: 4618 mov r0, r3 + 800a7a0: f011 fb9b bl 801beda + /* Start ETH HAL Init */ + + uint8_t MACAddr[6] ; + heth.Instance = ETH; + 800a7a4: 4b85 ldr r3, [pc, #532] ; (800a9bc ) + 800a7a6: 4a86 ldr r2, [pc, #536] ; (800a9c0 ) + 800a7a8: 601a str r2, [r3, #0] + MACAddr[0] = 0x00; + 800a7aa: 2300 movs r3, #0 + 800a7ac: f887 3024 strb.w r3, [r7, #36] ; 0x24 + MACAddr[1] = 0x80; + 800a7b0: 2380 movs r3, #128 ; 0x80 + 800a7b2: f887 3025 strb.w r3, [r7, #37] ; 0x25 + MACAddr[2] = 0xE1; + 800a7b6: 23e1 movs r3, #225 ; 0xe1 + 800a7b8: f887 3026 strb.w r3, [r7, #38] ; 0x26 + MACAddr[3] = 0x00; + 800a7bc: 2300 movs r3, #0 + 800a7be: f887 3027 strb.w r3, [r7, #39] ; 0x27 + MACAddr[4] = 0x00; + 800a7c2: 2300 movs r3, #0 + 800a7c4: f887 3028 strb.w r3, [r7, #40] ; 0x28 + MACAddr[5] = 0x44; + 800a7c8: 2344 movs r3, #68 ; 0x44 + 800a7ca: f887 3029 strb.w r3, [r7, #41] ; 0x29 + heth.Init.MACAddr = &MACAddr[0]; + 800a7ce: 4a7b ldr r2, [pc, #492] ; (800a9bc ) + 800a7d0: f107 0324 add.w r3, r7, #36 ; 0x24 + 800a7d4: 6053 str r3, [r2, #4] + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + 800a7d6: 4b79 ldr r3, [pc, #484] ; (800a9bc ) + 800a7d8: f44f 0200 mov.w r2, #8388608 ; 0x800000 + 800a7dc: 609a str r2, [r3, #8] + heth.Init.TxDesc = DMATxDscrTab; + 800a7de: 4b77 ldr r3, [pc, #476] ; (800a9bc ) + 800a7e0: 4a78 ldr r2, [pc, #480] ; (800a9c4 ) + 800a7e2: 60da str r2, [r3, #12] + heth.Init.RxDesc = DMARxDscrTab; + 800a7e4: 4b75 ldr r3, [pc, #468] ; (800a9bc ) + 800a7e6: 4a78 ldr r2, [pc, #480] ; (800a9c8 ) + 800a7e8: 611a str r2, [r3, #16] + heth.Init.RxBuffLen = 1536; + 800a7ea: 4b74 ldr r3, [pc, #464] ; (800a9bc ) + 800a7ec: f44f 62c0 mov.w r2, #1536 ; 0x600 + 800a7f0: 615a str r2, [r3, #20] + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + hal_eth_init_status = HAL_ETH_Init(&heth); + 800a7f2: 4872 ldr r0, [pc, #456] ; (800a9bc ) + 800a7f4: f7fa fd9a bl 800532c + 800a7f8: 4603 mov r3, r0 + 800a7fa: f887 3097 strb.w r3, [r7, #151] ; 0x97 + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + 800a7fe: 2238 movs r2, #56 ; 0x38 + 800a800: 2100 movs r1, #0 + 800a802: 4872 ldr r0, [pc, #456] ; (800a9cc ) + 800a804: f011 fb69 bl 801beda + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + 800a808: 4b70 ldr r3, [pc, #448] ; (800a9cc ) + 800a80a: 2221 movs r2, #33 ; 0x21 + 800a80c: 601a str r2, [r3, #0] + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + 800a80e: 4b6f ldr r3, [pc, #444] ; (800a9cc ) + 800a810: f44f 0240 mov.w r2, #12582912 ; 0xc00000 + 800a814: 615a str r2, [r3, #20] + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + 800a816: 4b6d ldr r3, [pc, #436] ; (800a9cc ) + 800a818: 2200 movs r2, #0 + 800a81a: 611a str r2, [r3, #16] + + /* End ETH HAL Init */ + + /* Initialize the RX POOL */ + LWIP_MEMPOOL_INIT(RX_POOL); + 800a81c: 486c ldr r0, [pc, #432] ; (800a9d0 ) + 800a81e: f005 f92b bl 800fa78 + +#if LWIP_ARP || LWIP_ETHERNET + + /* set MAC hardware address length */ + netif->hwaddr_len = ETH_HWADDR_LEN; + 800a822: 687b ldr r3, [r7, #4] + 800a824: 2206 movs r2, #6 + 800a826: f883 2030 strb.w r2, [r3, #48] ; 0x30 + + /* set MAC hardware address */ + netif->hwaddr[0] = heth.Init.MACAddr[0]; + 800a82a: 4b64 ldr r3, [pc, #400] ; (800a9bc ) + 800a82c: 685b ldr r3, [r3, #4] + 800a82e: 781a ldrb r2, [r3, #0] + 800a830: 687b ldr r3, [r7, #4] + 800a832: f883 202a strb.w r2, [r3, #42] ; 0x2a + netif->hwaddr[1] = heth.Init.MACAddr[1]; + 800a836: 4b61 ldr r3, [pc, #388] ; (800a9bc ) + 800a838: 685b ldr r3, [r3, #4] + 800a83a: 785a ldrb r2, [r3, #1] + 800a83c: 687b ldr r3, [r7, #4] + 800a83e: f883 202b strb.w r2, [r3, #43] ; 0x2b + netif->hwaddr[2] = heth.Init.MACAddr[2]; + 800a842: 4b5e ldr r3, [pc, #376] ; (800a9bc ) + 800a844: 685b ldr r3, [r3, #4] + 800a846: 789a ldrb r2, [r3, #2] + 800a848: 687b ldr r3, [r7, #4] + 800a84a: f883 202c strb.w r2, [r3, #44] ; 0x2c + netif->hwaddr[3] = heth.Init.MACAddr[3]; + 800a84e: 4b5b ldr r3, [pc, #364] ; (800a9bc ) + 800a850: 685b ldr r3, [r3, #4] + 800a852: 78da ldrb r2, [r3, #3] + 800a854: 687b ldr r3, [r7, #4] + 800a856: f883 202d strb.w r2, [r3, #45] ; 0x2d + netif->hwaddr[4] = heth.Init.MACAddr[4]; + 800a85a: 4b58 ldr r3, [pc, #352] ; (800a9bc ) + 800a85c: 685b ldr r3, [r3, #4] + 800a85e: 791a ldrb r2, [r3, #4] + 800a860: 687b ldr r3, [r7, #4] + 800a862: f883 202e strb.w r2, [r3, #46] ; 0x2e + netif->hwaddr[5] = heth.Init.MACAddr[5]; + 800a866: 4b55 ldr r3, [pc, #340] ; (800a9bc ) + 800a868: 685b ldr r3, [r3, #4] + 800a86a: 795a ldrb r2, [r3, #5] + 800a86c: 687b ldr r3, [r7, #4] + 800a86e: f883 202f strb.w r2, [r3, #47] ; 0x2f + + /* maximum transfer unit */ + netif->mtu = ETH_MAX_PAYLOAD; + 800a872: 687b ldr r3, [r7, #4] + 800a874: f240 52dc movw r2, #1500 ; 0x5dc + 800a878: 851a strh r2, [r3, #40] ; 0x28 + + /* Accept broadcast address and ARP traffic */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + #if LWIP_ARP + netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; + 800a87a: 687b ldr r3, [r7, #4] + 800a87c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 800a880: f043 030a orr.w r3, r3, #10 + 800a884: b2da uxtb r2, r3 + 800a886: 687b ldr r3, [r7, #4] + 800a888: f883 2031 strb.w r2, [r3, #49] ; 0x31 + #else + netif->flags |= NETIF_FLAG_BROADCAST; + #endif /* LWIP_ARP */ + + /* create a binary semaphore used for informing ethernetif of frame reception */ + RxPktSemaphore = xSemaphoreCreateBinary(); + 800a88c: 2203 movs r2, #3 + 800a88e: 2100 movs r1, #0 + 800a890: 2001 movs r0, #1 + 800a892: f001 f80f bl 800b8b4 + 800a896: 4603 mov r3, r0 + 800a898: 4a4e ldr r2, [pc, #312] ; (800a9d4 ) + 800a89a: 6013 str r3, [r2, #0] + + /* create a binary semaphore used for informing ethernetif of frame transmission */ + TxPktSemaphore = xSemaphoreCreateBinary(); + 800a89c: 2203 movs r2, #3 + 800a89e: 2100 movs r1, #0 + 800a8a0: 2001 movs r0, #1 + 800a8a2: f001 f807 bl 800b8b4 + 800a8a6: 4603 mov r3, r0 + 800a8a8: 4a4b ldr r2, [pc, #300] ; (800a9d8 ) + 800a8aa: 6013 str r3, [r2, #0] + + /* create the task that handles the ETH_MAC */ +/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */ + osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE); + 800a8ac: 4b4b ldr r3, [pc, #300] ; (800a9dc ) + 800a8ae: f107 0408 add.w r4, r7, #8 + 800a8b2: 461d mov r5, r3 + 800a8b4: cd0f ldmia r5!, {r0, r1, r2, r3} + 800a8b6: c40f stmia r4!, {r0, r1, r2, r3} + 800a8b8: e895 0007 ldmia.w r5, {r0, r1, r2} + 800a8bc: e884 0007 stmia.w r4, {r0, r1, r2} + osThreadCreate (osThread(EthIf), netif); + 800a8c0: f107 0308 add.w r3, r7, #8 + 800a8c4: 6879 ldr r1, [r7, #4] + 800a8c6: 4618 mov r0, r3 + 800a8c8: f000 fbf8 bl 800b0bc + +/* USER CODE BEGIN PHY_PRE_CONFIG */ + +/* USER CODE END PHY_PRE_CONFIG */ + /* Set PHY IO functions */ + LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx); + 800a8cc: 4944 ldr r1, [pc, #272] ; (800a9e0 ) + 800a8ce: 4845 ldr r0, [pc, #276] ; (800a9e4 ) + 800a8d0: f7f8 fdf9 bl 80034c6 + + /* Initialize the LAN8742 ETH PHY */ + LAN8742_Init(&LAN8742); + 800a8d4: 4843 ldr r0, [pc, #268] ; (800a9e4 ) + 800a8d6: f7f8 fe28 bl 800352a + + if (hal_eth_init_status == HAL_OK) + 800a8da: f897 3097 ldrb.w r3, [r7, #151] ; 0x97 + 800a8de: 2b00 cmp r3, #0 + 800a8e0: d165 bne.n 800a9ae + { + PHYLinkState = LAN8742_GetLinkState(&LAN8742); + 800a8e2: 4840 ldr r0, [pc, #256] ; (800a9e4 ) + 800a8e4: f7f8 fec9 bl 800367a + 800a8e8: f8c7 0090 str.w r0, [r7, #144] ; 0x90 + + /* Get link state */ + if(PHYLinkState <= LAN8742_STATUS_LINK_DOWN) + 800a8ec: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 800a8f0: 2b01 cmp r3, #1 + 800a8f2: dc06 bgt.n 800a902 + { + netif_set_link_down(netif); + 800a8f4: 6878 ldr r0, [r7, #4] + 800a8f6: f005 fca5 bl 8010244 + netif_set_down(netif); + 800a8fa: 6878 ldr r0, [r7, #4] + 800a8fc: f005 fc38 bl 8010170 +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +/* USER CODE BEGIN LOW_LEVEL_INIT */ + +/* USER CODE END LOW_LEVEL_INIT */ +} + 800a900: e057 b.n 800a9b2 + switch (PHYLinkState) + 800a902: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 800a906: 3b02 subs r3, #2 + 800a908: 2b03 cmp r3, #3 + 800a90a: d82b bhi.n 800a964 + 800a90c: a201 add r2, pc, #4 ; (adr r2, 800a914 ) + 800a90e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a912: bf00 nop + 800a914: 0800a925 .word 0x0800a925 + 800a918: 0800a937 .word 0x0800a937 + 800a91c: 0800a947 .word 0x0800a947 + 800a920: 0800a957 .word 0x0800a957 + duplex = ETH_FULLDUPLEX_MODE; + 800a924: f44f 6300 mov.w r3, #2048 ; 0x800 + 800a928: f8c7 309c str.w r3, [r7, #156] ; 0x9c + speed = ETH_SPEED_100M; + 800a92c: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800a930: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + break; + 800a934: e01f b.n 800a976 + duplex = ETH_HALFDUPLEX_MODE; + 800a936: 2300 movs r3, #0 + 800a938: f8c7 309c str.w r3, [r7, #156] ; 0x9c + speed = ETH_SPEED_100M; + 800a93c: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800a940: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + break; + 800a944: e017 b.n 800a976 + duplex = ETH_FULLDUPLEX_MODE; + 800a946: f44f 6300 mov.w r3, #2048 ; 0x800 + 800a94a: f8c7 309c str.w r3, [r7, #156] ; 0x9c + speed = ETH_SPEED_10M; + 800a94e: 2300 movs r3, #0 + 800a950: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + break; + 800a954: e00f b.n 800a976 + duplex = ETH_HALFDUPLEX_MODE; + 800a956: 2300 movs r3, #0 + 800a958: f8c7 309c str.w r3, [r7, #156] ; 0x9c + speed = ETH_SPEED_10M; + 800a95c: 2300 movs r3, #0 + 800a95e: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + break; + 800a962: e008 b.n 800a976 + duplex = ETH_FULLDUPLEX_MODE; + 800a964: f44f 6300 mov.w r3, #2048 ; 0x800 + 800a968: f8c7 309c str.w r3, [r7, #156] ; 0x9c + speed = ETH_SPEED_100M; + 800a96c: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800a970: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + break; + 800a974: bf00 nop + HAL_ETH_GetMACConfig(&heth, &MACConf); + 800a976: f107 032c add.w r3, r7, #44 ; 0x2c + 800a97a: 4619 mov r1, r3 + 800a97c: 480f ldr r0, [pc, #60] ; (800a9bc ) + 800a97e: f7fb f9b9 bl 8005cf4 + MACConf.DuplexMode = duplex; + 800a982: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 800a986: 647b str r3, [r7, #68] ; 0x44 + MACConf.Speed = speed; + 800a988: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800a98c: 643b str r3, [r7, #64] ; 0x40 + HAL_ETH_SetMACConfig(&heth, &MACConf); + 800a98e: f107 032c add.w r3, r7, #44 ; 0x2c + 800a992: 4619 mov r1, r3 + 800a994: 4809 ldr r0, [pc, #36] ; (800a9bc ) + 800a996: f7fb fa97 bl 8005ec8 + HAL_ETH_Start_IT(&heth); + 800a99a: 4808 ldr r0, [pc, #32] ; (800a9bc ) + 800a99c: f7fa fd42 bl 8005424 + netif_set_up(netif); + 800a9a0: 6878 ldr r0, [r7, #4] + 800a9a2: f005 fb79 bl 8010098 + netif_set_link_up(netif); + 800a9a6: 6878 ldr r0, [r7, #4] + 800a9a8: f005 fc14 bl 80101d4 +} + 800a9ac: e001 b.n 800a9b2 + Error_Handler(); + 800a9ae: f7f8 f995 bl 8002cdc +} + 800a9b2: bf00 nop + 800a9b4: 37a0 adds r7, #160 ; 0xa0 + 800a9b6: 46bd mov sp, r7 + 800a9b8: bdb0 pop {r4, r5, r7, pc} + 800a9ba: bf00 nop + 800a9bc: 20005380 .word 0x20005380 + 800a9c0: 40028000 .word 0x40028000 + 800a9c4: 200001c8 .word 0x200001c8 + 800a9c8: 20000128 .word 0x20000128 + 800a9cc: 20005430 .word 0x20005430 + 800a9d0: 080237d0 .word 0x080237d0 + 800a9d4: 20005378 .word 0x20005378 + 800a9d8: 2000537c .word 0x2000537c + 800a9dc: 0801e888 .word 0x0801e888 + 800a9e0: 2000009c .word 0x2000009c + 800a9e4: 20005468 .word 0x20005468 + +0800a9e8 : + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + 800a9e8: b580 push {r7, lr} + 800a9ea: b092 sub sp, #72 ; 0x48 + 800a9ec: af00 add r7, sp, #0 + 800a9ee: 6078 str r0, [r7, #4] + 800a9f0: 6039 str r1, [r7, #0] + uint32_t i = 0U; + 800a9f2: 2300 movs r3, #0 + 800a9f4: 647b str r3, [r7, #68] ; 0x44 + struct pbuf *q = NULL; + 800a9f6: 2300 movs r3, #0 + 800a9f8: 643b str r3, [r7, #64] ; 0x40 + err_t errval = ERR_OK; + 800a9fa: 2300 movs r3, #0 + 800a9fc: f887 303f strb.w r3, [r7, #63] ; 0x3f + ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0}; + 800aa00: f107 030c add.w r3, r7, #12 + 800aa04: 2230 movs r2, #48 ; 0x30 + 800aa06: 2100 movs r1, #0 + 800aa08: 4618 mov r0, r3 + 800aa0a: f011 fa66 bl 801beda + + memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef)); + 800aa0e: f107 030c add.w r3, r7, #12 + 800aa12: 2230 movs r2, #48 ; 0x30 + 800aa14: 2100 movs r1, #0 + 800aa16: 4618 mov r0, r3 + 800aa18: f011 fa5f bl 801beda + + for(q = p; q != NULL; q = q->next) + 800aa1c: 683b ldr r3, [r7, #0] + 800aa1e: 643b str r3, [r7, #64] ; 0x40 + 800aa20: e045 b.n 800aaae + { + if(i >= ETH_TX_DESC_CNT) + 800aa22: 6c7b ldr r3, [r7, #68] ; 0x44 + 800aa24: 2b03 cmp r3, #3 + 800aa26: d902 bls.n 800aa2e + return ERR_IF; + 800aa28: f06f 030b mvn.w r3, #11 + 800aa2c: e065 b.n 800aafa + + Txbuffer[i].buffer = q->payload; + 800aa2e: 6c3b ldr r3, [r7, #64] ; 0x40 + 800aa30: 6859 ldr r1, [r3, #4] + 800aa32: 6c7a ldr r2, [r7, #68] ; 0x44 + 800aa34: 4613 mov r3, r2 + 800aa36: 005b lsls r3, r3, #1 + 800aa38: 4413 add r3, r2 + 800aa3a: 009b lsls r3, r3, #2 + 800aa3c: 3348 adds r3, #72 ; 0x48 + 800aa3e: 443b add r3, r7 + 800aa40: 3b3c subs r3, #60 ; 0x3c + 800aa42: 6019 str r1, [r3, #0] + Txbuffer[i].len = q->len; + 800aa44: 6c3b ldr r3, [r7, #64] ; 0x40 + 800aa46: 895b ldrh r3, [r3, #10] + 800aa48: 4619 mov r1, r3 + 800aa4a: 6c7a ldr r2, [r7, #68] ; 0x44 + 800aa4c: 4613 mov r3, r2 + 800aa4e: 005b lsls r3, r3, #1 + 800aa50: 4413 add r3, r2 + 800aa52: 009b lsls r3, r3, #2 + 800aa54: 3348 adds r3, #72 ; 0x48 + 800aa56: 443b add r3, r7 + 800aa58: 3b38 subs r3, #56 ; 0x38 + 800aa5a: 6019 str r1, [r3, #0] + + if(i>0) + 800aa5c: 6c7b ldr r3, [r7, #68] ; 0x44 + 800aa5e: 2b00 cmp r3, #0 + 800aa60: d011 beq.n 800aa86 + { + Txbuffer[i-1].next = &Txbuffer[i]; + 800aa62: 6c7b ldr r3, [r7, #68] ; 0x44 + 800aa64: 1e5a subs r2, r3, #1 + 800aa66: f107 000c add.w r0, r7, #12 + 800aa6a: 6c79 ldr r1, [r7, #68] ; 0x44 + 800aa6c: 460b mov r3, r1 + 800aa6e: 005b lsls r3, r3, #1 + 800aa70: 440b add r3, r1 + 800aa72: 009b lsls r3, r3, #2 + 800aa74: 18c1 adds r1, r0, r3 + 800aa76: 4613 mov r3, r2 + 800aa78: 005b lsls r3, r3, #1 + 800aa7a: 4413 add r3, r2 + 800aa7c: 009b lsls r3, r3, #2 + 800aa7e: 3348 adds r3, #72 ; 0x48 + 800aa80: 443b add r3, r7 + 800aa82: 3b34 subs r3, #52 ; 0x34 + 800aa84: 6019 str r1, [r3, #0] + } + + if(q->next == NULL) + 800aa86: 6c3b ldr r3, [r7, #64] ; 0x40 + 800aa88: 681b ldr r3, [r3, #0] + 800aa8a: 2b00 cmp r3, #0 + 800aa8c: d109 bne.n 800aaa2 + { + Txbuffer[i].next = NULL; + 800aa8e: 6c7a ldr r2, [r7, #68] ; 0x44 + 800aa90: 4613 mov r3, r2 + 800aa92: 005b lsls r3, r3, #1 + 800aa94: 4413 add r3, r2 + 800aa96: 009b lsls r3, r3, #2 + 800aa98: 3348 adds r3, #72 ; 0x48 + 800aa9a: 443b add r3, r7 + 800aa9c: 3b34 subs r3, #52 ; 0x34 + 800aa9e: 2200 movs r2, #0 + 800aaa0: 601a str r2, [r3, #0] + } + + i++; + 800aaa2: 6c7b ldr r3, [r7, #68] ; 0x44 + 800aaa4: 3301 adds r3, #1 + 800aaa6: 647b str r3, [r7, #68] ; 0x44 + for(q = p; q != NULL; q = q->next) + 800aaa8: 6c3b ldr r3, [r7, #64] ; 0x40 + 800aaaa: 681b ldr r3, [r3, #0] + 800aaac: 643b str r3, [r7, #64] ; 0x40 + 800aaae: 6c3b ldr r3, [r7, #64] ; 0x40 + 800aab0: 2b00 cmp r3, #0 + 800aab2: d1b6 bne.n 800aa22 + } + + TxConfig.Length = p->tot_len; + 800aab4: 683b ldr r3, [r7, #0] + 800aab6: 891b ldrh r3, [r3, #8] + 800aab8: 461a mov r2, r3 + 800aaba: 4b12 ldr r3, [pc, #72] ; (800ab04 ) + 800aabc: 605a str r2, [r3, #4] + TxConfig.TxBuffer = Txbuffer; + 800aabe: 4a11 ldr r2, [pc, #68] ; (800ab04 ) + 800aac0: f107 030c add.w r3, r7, #12 + 800aac4: 6093 str r3, [r2, #8] + TxConfig.pData = p; + 800aac6: 4a0f ldr r2, [pc, #60] ; (800ab04 ) + 800aac8: 683b ldr r3, [r7, #0] + 800aaca: 6353 str r3, [r2, #52] ; 0x34 + + pbuf_ref(p); + 800aacc: 6838 ldr r0, [r7, #0] + 800aace: f006 f83d bl 8010b4c + + HAL_ETH_Transmit_IT(&heth, &TxConfig); + 800aad2: 490c ldr r1, [pc, #48] ; (800ab04 ) + 800aad4: 480c ldr r0, [pc, #48] ; (800ab08 ) + 800aad6: f7fa fdb3 bl 8005640 + while(osSemaphoreWait(TxPktSemaphore, TIME_WAITING_FOR_INPUT)!=osOK) + 800aada: bf00 nop + 800aadc: 4b0b ldr r3, [pc, #44] ; (800ab0c ) + 800aade: 681b ldr r3, [r3, #0] + 800aae0: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 800aae4: 4618 mov r0, r3 + 800aae6: f000 fbe5 bl 800b2b4 + 800aaea: 4603 mov r3, r0 + 800aaec: 2b00 cmp r3, #0 + 800aaee: d1f5 bne.n 800aadc + + { + } + + HAL_ETH_ReleaseTxPacket(&heth); + 800aaf0: 4805 ldr r0, [pc, #20] ; (800ab08 ) + 800aaf2: f7fa ff39 bl 8005968 + + return errval; + 800aaf6: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f +} + 800aafa: 4618 mov r0, r3 + 800aafc: 3748 adds r7, #72 ; 0x48 + 800aafe: 46bd mov sp, r7 + 800ab00: bd80 pop {r7, pc} + 800ab02: bf00 nop + 800ab04: 20005430 .word 0x20005430 + 800ab08: 20005380 .word 0x20005380 + 800ab0c: 2000537c .word 0x2000537c + +0800ab10 : + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * low_level_input(struct netif *netif) +{ + 800ab10: b580 push {r7, lr} + 800ab12: b084 sub sp, #16 + 800ab14: af00 add r7, sp, #0 + 800ab16: 6078 str r0, [r7, #4] + struct pbuf *p = NULL; + 800ab18: 2300 movs r3, #0 + 800ab1a: 60fb str r3, [r7, #12] + + if(RxAllocStatus == RX_ALLOC_OK) + 800ab1c: 4b07 ldr r3, [pc, #28] ; (800ab3c ) + 800ab1e: 781b ldrb r3, [r3, #0] + 800ab20: 2b00 cmp r3, #0 + 800ab22: d105 bne.n 800ab30 + { + HAL_ETH_ReadData(&heth, (void **)&p); + 800ab24: f107 030c add.w r3, r7, #12 + 800ab28: 4619 mov r1, r3 + 800ab2a: 4805 ldr r0, [pc, #20] ; (800ab40 ) + 800ab2c: f7fa fde4 bl 80056f8 + } + + return p; + 800ab30: 68fb ldr r3, [r7, #12] +} + 800ab32: 4618 mov r0, r3 + 800ab34: 3710 adds r7, #16 + 800ab36: 46bd mov sp, r7 + 800ab38: bd80 pop {r7, pc} + 800ab3a: bf00 nop + 800ab3c: 20005374 .word 0x20005374 + 800ab40: 20005380 .word 0x20005380 + +0800ab44 : + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +static void ethernetif_input(void const * argument) +{ + 800ab44: b580 push {r7, lr} + 800ab46: b084 sub sp, #16 + 800ab48: af00 add r7, sp, #0 + 800ab4a: 6078 str r0, [r7, #4] + struct pbuf *p = NULL; + 800ab4c: 2300 movs r3, #0 + 800ab4e: 60fb str r3, [r7, #12] + struct netif *netif = (struct netif *) argument; + 800ab50: 687b ldr r3, [r7, #4] + 800ab52: 60bb str r3, [r7, #8] + + for( ;; ) + { + if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK) + 800ab54: 4b0f ldr r3, [pc, #60] ; (800ab94 ) + 800ab56: 681b ldr r3, [r3, #0] + 800ab58: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 800ab5c: 4618 mov r0, r3 + 800ab5e: f000 fba9 bl 800b2b4 + 800ab62: 4603 mov r3, r0 + 800ab64: 2b00 cmp r3, #0 + 800ab66: d1f5 bne.n 800ab54 + { + do + { + p = low_level_input( netif ); + 800ab68: 68b8 ldr r0, [r7, #8] + 800ab6a: f7ff ffd1 bl 800ab10 + 800ab6e: 60f8 str r0, [r7, #12] + if (p != NULL) + 800ab70: 68fb ldr r3, [r7, #12] + 800ab72: 2b00 cmp r3, #0 + 800ab74: d00a beq.n 800ab8c + { + if (netif->input( p, netif) != ERR_OK ) + 800ab76: 68bb ldr r3, [r7, #8] + 800ab78: 691b ldr r3, [r3, #16] + 800ab7a: 68b9 ldr r1, [r7, #8] + 800ab7c: 68f8 ldr r0, [r7, #12] + 800ab7e: 4798 blx r3 + 800ab80: 4603 mov r3, r0 + 800ab82: 2b00 cmp r3, #0 + 800ab84: d002 beq.n 800ab8c + { + pbuf_free(p); + 800ab86: 68f8 ldr r0, [r7, #12] + 800ab88: f005 ff3a bl 8010a00 + } + } + } while(p!=NULL); + 800ab8c: 68fb ldr r3, [r7, #12] + 800ab8e: 2b00 cmp r3, #0 + 800ab90: d1ea bne.n 800ab68 + if (osSemaphoreWait(RxPktSemaphore, TIME_WAITING_FOR_INPUT) == osOK) + 800ab92: e7df b.n 800ab54 + 800ab94: 20005378 .word 0x20005378 + +0800ab98 : + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif_init(struct netif *netif) +{ + 800ab98: b580 push {r7, lr} + 800ab9a: b082 sub sp, #8 + 800ab9c: af00 add r7, sp, #0 + 800ab9e: 6078 str r0, [r7, #4] + LWIP_ASSERT("netif != NULL", (netif != NULL)); + 800aba0: 687b ldr r3, [r7, #4] + 800aba2: 2b00 cmp r3, #0 + 800aba4: d106 bne.n 800abb4 + 800aba6: 4b0e ldr r3, [pc, #56] ; (800abe0 ) + 800aba8: f240 12ef movw r2, #495 ; 0x1ef + 800abac: 490d ldr r1, [pc, #52] ; (800abe4 ) + 800abae: 480e ldr r0, [pc, #56] ; (800abe8 ) + 800abb0: f011 fa30 bl 801c014 + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); + + netif->name[0] = IFNAME0; + 800abb4: 687b ldr r3, [r7, #4] + 800abb6: 2273 movs r2, #115 ; 0x73 + 800abb8: f883 2032 strb.w r2, [r3, #50] ; 0x32 + netif->name[1] = IFNAME1; + 800abbc: 687b ldr r3, [r7, #4] + 800abbe: 2274 movs r2, #116 ; 0x74 + 800abc0: f883 2033 strb.w r2, [r3, #51] ; 0x33 + * is available...) */ + +#if LWIP_IPV4 +#if LWIP_ARP || LWIP_ETHERNET +#if LWIP_ARP + netif->output = etharp_output; + 800abc4: 687b ldr r3, [r7, #4] + 800abc6: 4a09 ldr r2, [pc, #36] ; (800abec ) + 800abc8: 615a str r2, [r3, #20] + +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + + netif->linkoutput = low_level_output; + 800abca: 687b ldr r3, [r7, #4] + 800abcc: 4a08 ldr r2, [pc, #32] ; (800abf0 ) + 800abce: 619a str r2, [r3, #24] + + /* initialize the hardware */ + low_level_init(netif); + 800abd0: 6878 ldr r0, [r7, #4] + 800abd2: f7ff fdd3 bl 800a77c + + return ERR_OK; + 800abd6: 2300 movs r3, #0 +} + 800abd8: 4618 mov r0, r3 + 800abda: 3708 adds r7, #8 + 800abdc: 46bd mov sp, r7 + 800abde: bd80 pop {r7, pc} + 800abe0: 0801e8a4 .word 0x0801e8a4 + 800abe4: 0801e8c0 .word 0x0801e8c0 + 800abe8: 0801e8d0 .word 0x0801e8d0 + 800abec: 08019961 .word 0x08019961 + 800abf0: 0800a9e9 .word 0x0800a9e9 + +0800abf4 : + * @brief Custom Rx pbuf free callback + * @param pbuf: pbuf to be freed + * @retval None + */ +void pbuf_free_custom(struct pbuf *p) +{ + 800abf4: b580 push {r7, lr} + 800abf6: b084 sub sp, #16 + 800abf8: af00 add r7, sp, #0 + 800abfa: 6078 str r0, [r7, #4] + struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p; + 800abfc: 687b ldr r3, [r7, #4] + 800abfe: 60fb str r3, [r7, #12] + LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); + 800ac00: 68f9 ldr r1, [r7, #12] + 800ac02: 4809 ldr r0, [pc, #36] ; (800ac28 ) + 800ac04: f005 f828 bl 800fc58 + + /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to + * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */ + + if (RxAllocStatus == RX_ALLOC_ERROR) + 800ac08: 4b08 ldr r3, [pc, #32] ; (800ac2c ) + 800ac0a: 781b ldrb r3, [r3, #0] + 800ac0c: 2b01 cmp r3, #1 + 800ac0e: d107 bne.n 800ac20 + { + RxAllocStatus = RX_ALLOC_OK; + 800ac10: 4b06 ldr r3, [pc, #24] ; (800ac2c ) + 800ac12: 2200 movs r2, #0 + 800ac14: 701a strb r2, [r3, #0] + osSemaphoreRelease(RxPktSemaphore); + 800ac16: 4b06 ldr r3, [pc, #24] ; (800ac30 ) + 800ac18: 681b ldr r3, [r3, #0] + 800ac1a: 4618 mov r0, r3 + 800ac1c: f000 fb98 bl 800b350 + } +} + 800ac20: bf00 nop + 800ac22: 3710 adds r7, #16 + 800ac24: 46bd mov sp, r7 + 800ac26: bd80 pop {r7, pc} + 800ac28: 080237d0 .word 0x080237d0 + 800ac2c: 20005374 .word 0x20005374 + 800ac30: 20005378 .word 0x20005378 + +0800ac34 : +* when LWIP_TIMERS == 1 and NO_SYS == 1 +* @param None +* @retval Time +*/ +u32_t sys_now(void) +{ + 800ac34: b580 push {r7, lr} + 800ac36: af00 add r7, sp, #0 + return HAL_GetTick(); + 800ac38: f7f9 fe1c bl 8004874 + 800ac3c: 4603 mov r3, r0 +} + 800ac3e: 4618 mov r0, r3 + 800ac40: bd80 pop {r7, pc} + ... + +0800ac44 : + * @param ethHandle: ETH handle + * @retval None + */ + +void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle) +{ + 800ac44: b580 push {r7, lr} + 800ac46: b08e sub sp, #56 ; 0x38 + 800ac48: af00 add r7, sp, #0 + 800ac4a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800ac4c: f107 0324 add.w r3, r7, #36 ; 0x24 + 800ac50: 2200 movs r2, #0 + 800ac52: 601a str r2, [r3, #0] + 800ac54: 605a str r2, [r3, #4] + 800ac56: 609a str r2, [r3, #8] + 800ac58: 60da str r2, [r3, #12] + 800ac5a: 611a str r2, [r3, #16] + if(ethHandle->Instance==ETH) + 800ac5c: 687b ldr r3, [r7, #4] + 800ac5e: 681b ldr r3, [r3, #0] + 800ac60: 4a44 ldr r2, [pc, #272] ; (800ad74 ) + 800ac62: 4293 cmp r3, r2 + 800ac64: f040 8081 bne.w 800ad6a + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Enable Peripheral clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + 800ac68: 4b43 ldr r3, [pc, #268] ; (800ad78 ) + 800ac6a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ac6c: 4a42 ldr r2, [pc, #264] ; (800ad78 ) + 800ac6e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 800ac72: 6313 str r3, [r2, #48] ; 0x30 + 800ac74: 4b40 ldr r3, [pc, #256] ; (800ad78 ) + 800ac76: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ac78: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800ac7c: 623b str r3, [r7, #32] + 800ac7e: 6a3b ldr r3, [r7, #32] + 800ac80: 4b3d ldr r3, [pc, #244] ; (800ad78 ) + 800ac82: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ac84: 4a3c ldr r2, [pc, #240] ; (800ad78 ) + 800ac86: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 800ac8a: 6313 str r3, [r2, #48] ; 0x30 + 800ac8c: 4b3a ldr r3, [pc, #232] ; (800ad78 ) + 800ac8e: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ac90: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 800ac94: 61fb str r3, [r7, #28] + 800ac96: 69fb ldr r3, [r7, #28] + 800ac98: 4b37 ldr r3, [pc, #220] ; (800ad78 ) + 800ac9a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ac9c: 4a36 ldr r2, [pc, #216] ; (800ad78 ) + 800ac9e: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 + 800aca2: 6313 str r3, [r2, #48] ; 0x30 + 800aca4: 4b34 ldr r3, [pc, #208] ; (800ad78 ) + 800aca6: 6b1b ldr r3, [r3, #48] ; 0x30 + 800aca8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800acac: 61bb str r3, [r7, #24] + 800acae: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOG_CLK_ENABLE(); + 800acb0: 4b31 ldr r3, [pc, #196] ; (800ad78 ) + 800acb2: 6b1b ldr r3, [r3, #48] ; 0x30 + 800acb4: 4a30 ldr r2, [pc, #192] ; (800ad78 ) + 800acb6: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800acba: 6313 str r3, [r2, #48] ; 0x30 + 800acbc: 4b2e ldr r3, [pc, #184] ; (800ad78 ) + 800acbe: 6b1b ldr r3, [r3, #48] ; 0x30 + 800acc0: f003 0340 and.w r3, r3, #64 ; 0x40 + 800acc4: 617b str r3, [r7, #20] + 800acc6: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800acc8: 4b2b ldr r3, [pc, #172] ; (800ad78 ) + 800acca: 6b1b ldr r3, [r3, #48] ; 0x30 + 800accc: 4a2a ldr r2, [pc, #168] ; (800ad78 ) + 800acce: f043 0304 orr.w r3, r3, #4 + 800acd2: 6313 str r3, [r2, #48] ; 0x30 + 800acd4: 4b28 ldr r3, [pc, #160] ; (800ad78 ) + 800acd6: 6b1b ldr r3, [r3, #48] ; 0x30 + 800acd8: f003 0304 and.w r3, r3, #4 + 800acdc: 613b str r3, [r7, #16] + 800acde: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800ace0: 4b25 ldr r3, [pc, #148] ; (800ad78 ) + 800ace2: 6b1b ldr r3, [r3, #48] ; 0x30 + 800ace4: 4a24 ldr r2, [pc, #144] ; (800ad78 ) + 800ace6: f043 0301 orr.w r3, r3, #1 + 800acea: 6313 str r3, [r2, #48] ; 0x30 + 800acec: 4b22 ldr r3, [pc, #136] ; (800ad78 ) + 800acee: 6b1b ldr r3, [r3, #48] ; 0x30 + 800acf0: f003 0301 and.w r3, r3, #1 + 800acf4: 60fb str r3, [r7, #12] + 800acf6: 68fb ldr r3, [r7, #12] + PC4 ------> ETH_RXD0 + PA2 ------> ETH_MDIO + PC5 ------> ETH_RXD1 + PA7 ------> ETH_CRS_DV + */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11; + 800acf8: f44f 43d0 mov.w r3, #26624 ; 0x6800 + 800acfc: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800acfe: 2302 movs r3, #2 + 800ad00: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800ad02: 2300 movs r3, #0 + 800ad04: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800ad06: 2303 movs r3, #3 + 800ad08: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 800ad0a: 230b movs r3, #11 + 800ad0c: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 800ad0e: f107 0324 add.w r3, r7, #36 ; 0x24 + 800ad12: 4619 mov r1, r3 + 800ad14: 4819 ldr r0, [pc, #100] ; (800ad7c ) + 800ad16: f7fb fd57 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + 800ad1a: 2332 movs r3, #50 ; 0x32 + 800ad1c: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800ad1e: 2302 movs r3, #2 + 800ad20: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800ad22: 2300 movs r3, #0 + 800ad24: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800ad26: 2303 movs r3, #3 + 800ad28: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 800ad2a: 230b movs r3, #11 + 800ad2c: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800ad2e: f107 0324 add.w r3, r7, #36 ; 0x24 + 800ad32: 4619 mov r1, r3 + 800ad34: 4812 ldr r0, [pc, #72] ; (800ad80 ) + 800ad36: f7fb fd47 bl 80067c8 + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + 800ad3a: 2386 movs r3, #134 ; 0x86 + 800ad3c: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800ad3e: 2302 movs r3, #2 + 800ad40: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800ad42: 2300 movs r3, #0 + 800ad44: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800ad46: 2303 movs r3, #3 + 800ad48: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 800ad4a: 230b movs r3, #11 + 800ad4c: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800ad4e: f107 0324 add.w r3, r7, #36 ; 0x24 + 800ad52: 4619 mov r1, r3 + 800ad54: 480b ldr r0, [pc, #44] ; (800ad84 ) + 800ad56: f7fb fd37 bl 80067c8 + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(ETH_IRQn, 5, 0); + 800ad5a: 2200 movs r2, #0 + 800ad5c: 2105 movs r1, #5 + 800ad5e: 203d movs r0, #61 ; 0x3d + 800ad60: f7f9 fe70 bl 8004a44 + HAL_NVIC_EnableIRQ(ETH_IRQn); + 800ad64: 203d movs r0, #61 ; 0x3d + 800ad66: f7f9 fe89 bl 8004a7c + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } +} + 800ad6a: bf00 nop + 800ad6c: 3738 adds r7, #56 ; 0x38 + 800ad6e: 46bd mov sp, r7 + 800ad70: bd80 pop {r7, pc} + 800ad72: bf00 nop + 800ad74: 40028000 .word 0x40028000 + 800ad78: 40023800 .word 0x40023800 + 800ad7c: 40021800 .word 0x40021800 + 800ad80: 40020800 .word 0x40020800 + 800ad84: 40020000 .word 0x40020000 + +0800ad88 : + * @brief Initializes the MDIO interface GPIO and clocks. + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_Init(void) +{ + 800ad88: b580 push {r7, lr} + 800ad8a: af00 add r7, sp, #0 + /* We assume that MDIO GPIO configuration is already done + in the ETH_MspInit() else it should be done here + */ + + /* Configure the MDIO Clock */ + HAL_ETH_SetMDIOClockRange(&heth); + 800ad8c: 4802 ldr r0, [pc, #8] ; (800ad98 ) + 800ad8e: f7fb f8b5 bl 8005efc + + return 0; + 800ad92: 2300 movs r3, #0 +} + 800ad94: 4618 mov r0, r3 + 800ad96: bd80 pop {r7, pc} + 800ad98: 20005380 .word 0x20005380 + +0800ad9c : + * @brief De-Initializes the MDIO interface . + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_DeInit (void) +{ + 800ad9c: b480 push {r7} + 800ad9e: af00 add r7, sp, #0 + return 0; + 800ada0: 2300 movs r3, #0 +} + 800ada2: 4618 mov r0, r3 + 800ada4: 46bd mov sp, r7 + 800ada6: f85d 7b04 ldr.w r7, [sp], #4 + 800adaa: 4770 bx lr + +0800adac : + * @param RegAddr: PHY register address + * @param pRegVal: pointer to hold the register value + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal) +{ + 800adac: b580 push {r7, lr} + 800adae: b084 sub sp, #16 + 800adb0: af00 add r7, sp, #0 + 800adb2: 60f8 str r0, [r7, #12] + 800adb4: 60b9 str r1, [r7, #8] + 800adb6: 607a str r2, [r7, #4] + if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK) + 800adb8: 687b ldr r3, [r7, #4] + 800adba: 68ba ldr r2, [r7, #8] + 800adbc: 68f9 ldr r1, [r7, #12] + 800adbe: 4807 ldr r0, [pc, #28] ; (800addc ) + 800adc0: f7fa ff04 bl 8005bcc + 800adc4: 4603 mov r3, r0 + 800adc6: 2b00 cmp r3, #0 + 800adc8: d002 beq.n 800add0 + { + return -1; + 800adca: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800adce: e000 b.n 800add2 + } + + return 0; + 800add0: 2300 movs r3, #0 +} + 800add2: 4618 mov r0, r3 + 800add4: 3710 adds r7, #16 + 800add6: 46bd mov sp, r7 + 800add8: bd80 pop {r7, pc} + 800adda: bf00 nop + 800addc: 20005380 .word 0x20005380 + +0800ade0 : + * @param RegAddr: PHY register address + * @param RegVal: Value to be written + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal) +{ + 800ade0: b580 push {r7, lr} + 800ade2: b084 sub sp, #16 + 800ade4: af00 add r7, sp, #0 + 800ade6: 60f8 str r0, [r7, #12] + 800ade8: 60b9 str r1, [r7, #8] + 800adea: 607a str r2, [r7, #4] + if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK) + 800adec: 687b ldr r3, [r7, #4] + 800adee: 68ba ldr r2, [r7, #8] + 800adf0: 68f9 ldr r1, [r7, #12] + 800adf2: 4807 ldr r0, [pc, #28] ; (800ae10 ) + 800adf4: f7fa ff35 bl 8005c62 + 800adf8: 4603 mov r3, r0 + 800adfa: 2b00 cmp r3, #0 + 800adfc: d002 beq.n 800ae04 + { + return -1; + 800adfe: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800ae02: e000 b.n 800ae06 + } + + return 0; + 800ae04: 2300 movs r3, #0 +} + 800ae06: 4618 mov r0, r3 + 800ae08: 3710 adds r7, #16 + 800ae0a: 46bd mov sp, r7 + 800ae0c: bd80 pop {r7, pc} + 800ae0e: bf00 nop + 800ae10: 20005380 .word 0x20005380 + +0800ae14 : +/** + * @brief Get the time in millisecons used for internal PHY driver process. + * @retval Time value + */ +int32_t ETH_PHY_IO_GetTick(void) +{ + 800ae14: b580 push {r7, lr} + 800ae16: af00 add r7, sp, #0 + return HAL_GetTick(); + 800ae18: f7f9 fd2c bl 8004874 + 800ae1c: 4603 mov r3, r0 +} + 800ae1e: 4618 mov r0, r3 + 800ae20: bd80 pop {r7, pc} + ... + +0800ae24 : + * @brief Check the ETH link state then update ETH driver and netif link accordingly. + * @retval None + */ + +void ethernet_link_thread(void const * argument) +{ + 800ae24: b580 push {r7, lr} + 800ae26: b0a0 sub sp, #128 ; 0x80 + 800ae28: af00 add r7, sp, #0 + 800ae2a: 6078 str r0, [r7, #4] + ETH_MACConfigTypeDef MACConf = {0}; + 800ae2c: f107 0308 add.w r3, r7, #8 + 800ae30: 2264 movs r2, #100 ; 0x64 + 800ae32: 2100 movs r1, #0 + 800ae34: 4618 mov r0, r3 + 800ae36: f011 f850 bl 801beda + int32_t PHYLinkState = 0; + 800ae3a: 2300 movs r3, #0 + 800ae3c: 673b str r3, [r7, #112] ; 0x70 + uint32_t linkchanged = 0U, speed = 0U, duplex = 0U; + 800ae3e: 2300 movs r3, #0 + 800ae40: 67fb str r3, [r7, #124] ; 0x7c + 800ae42: 2300 movs r3, #0 + 800ae44: 67bb str r3, [r7, #120] ; 0x78 + 800ae46: 2300 movs r3, #0 + 800ae48: 677b str r3, [r7, #116] ; 0x74 + + struct netif *netif = (struct netif *) argument; + 800ae4a: 687b ldr r3, [r7, #4] + 800ae4c: 66fb str r3, [r7, #108] ; 0x6c + +/* USER CODE END ETH link init */ + + for(;;) + { + PHYLinkState = LAN8742_GetLinkState(&LAN8742); + 800ae4e: 483a ldr r0, [pc, #232] ; (800af38 ) + 800ae50: f7f8 fc13 bl 800367a + 800ae54: 6738 str r0, [r7, #112] ; 0x70 + + if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN)) + 800ae56: 6efb ldr r3, [r7, #108] ; 0x6c + 800ae58: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 800ae5c: 089b lsrs r3, r3, #2 + 800ae5e: f003 0301 and.w r3, r3, #1 + 800ae62: b2db uxtb r3, r3 + 800ae64: 2b00 cmp r3, #0 + 800ae66: d00c beq.n 800ae82 + 800ae68: 6f3b ldr r3, [r7, #112] ; 0x70 + 800ae6a: 2b01 cmp r3, #1 + 800ae6c: dc09 bgt.n 800ae82 + { + HAL_ETH_Stop_IT(&heth); + 800ae6e: 4833 ldr r0, [pc, #204] ; (800af3c ) + 800ae70: f7fa fb66 bl 8005540 + netif_set_down(netif); + 800ae74: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800ae76: f005 f97b bl 8010170 + netif_set_link_down(netif); + 800ae7a: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800ae7c: f005 f9e2 bl 8010244 + 800ae80: e055 b.n 800af2e + } + else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN)) + 800ae82: 6efb ldr r3, [r7, #108] ; 0x6c + 800ae84: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 800ae88: f003 0304 and.w r3, r3, #4 + 800ae8c: 2b00 cmp r3, #0 + 800ae8e: d14e bne.n 800af2e + 800ae90: 6f3b ldr r3, [r7, #112] ; 0x70 + 800ae92: 2b01 cmp r3, #1 + 800ae94: dd4b ble.n 800af2e + { + switch (PHYLinkState) + 800ae96: 6f3b ldr r3, [r7, #112] ; 0x70 + 800ae98: 3b02 subs r3, #2 + 800ae9a: 2b03 cmp r3, #3 + 800ae9c: d82a bhi.n 800aef4 + 800ae9e: a201 add r2, pc, #4 ; (adr r2, 800aea4 ) + 800aea0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800aea4: 0800aeb5 .word 0x0800aeb5 + 800aea8: 0800aec7 .word 0x0800aec7 + 800aeac: 0800aed7 .word 0x0800aed7 + 800aeb0: 0800aee7 .word 0x0800aee7 + { + case LAN8742_STATUS_100MBITS_FULLDUPLEX: + duplex = ETH_FULLDUPLEX_MODE; + 800aeb4: f44f 6300 mov.w r3, #2048 ; 0x800 + 800aeb8: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_100M; + 800aeba: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800aebe: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800aec0: 2301 movs r3, #1 + 800aec2: 67fb str r3, [r7, #124] ; 0x7c + break; + 800aec4: e017 b.n 800aef6 + case LAN8742_STATUS_100MBITS_HALFDUPLEX: + duplex = ETH_HALFDUPLEX_MODE; + 800aec6: 2300 movs r3, #0 + 800aec8: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_100M; + 800aeca: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800aece: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800aed0: 2301 movs r3, #1 + 800aed2: 67fb str r3, [r7, #124] ; 0x7c + break; + 800aed4: e00f b.n 800aef6 + case LAN8742_STATUS_10MBITS_FULLDUPLEX: + duplex = ETH_FULLDUPLEX_MODE; + 800aed6: f44f 6300 mov.w r3, #2048 ; 0x800 + 800aeda: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_10M; + 800aedc: 2300 movs r3, #0 + 800aede: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800aee0: 2301 movs r3, #1 + 800aee2: 67fb str r3, [r7, #124] ; 0x7c + break; + 800aee4: e007 b.n 800aef6 + case LAN8742_STATUS_10MBITS_HALFDUPLEX: + duplex = ETH_HALFDUPLEX_MODE; + 800aee6: 2300 movs r3, #0 + 800aee8: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_10M; + 800aeea: 2300 movs r3, #0 + 800aeec: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800aeee: 2301 movs r3, #1 + 800aef0: 67fb str r3, [r7, #124] ; 0x7c + break; + 800aef2: e000 b.n 800aef6 + default: + break; + 800aef4: bf00 nop + } + + if(linkchanged) + 800aef6: 6ffb ldr r3, [r7, #124] ; 0x7c + 800aef8: 2b00 cmp r3, #0 + 800aefa: d018 beq.n 800af2e + { + /* Get MAC Config MAC */ + HAL_ETH_GetMACConfig(&heth, &MACConf); + 800aefc: f107 0308 add.w r3, r7, #8 + 800af00: 4619 mov r1, r3 + 800af02: 480e ldr r0, [pc, #56] ; (800af3c ) + 800af04: f7fa fef6 bl 8005cf4 + MACConf.DuplexMode = duplex; + 800af08: 6f7b ldr r3, [r7, #116] ; 0x74 + 800af0a: 623b str r3, [r7, #32] + MACConf.Speed = speed; + 800af0c: 6fbb ldr r3, [r7, #120] ; 0x78 + 800af0e: 61fb str r3, [r7, #28] + HAL_ETH_SetMACConfig(&heth, &MACConf); + 800af10: f107 0308 add.w r3, r7, #8 + 800af14: 4619 mov r1, r3 + 800af16: 4809 ldr r0, [pc, #36] ; (800af3c ) + 800af18: f7fa ffd6 bl 8005ec8 + HAL_ETH_Start_IT(&heth); + 800af1c: 4807 ldr r0, [pc, #28] ; (800af3c ) + 800af1e: f7fa fa81 bl 8005424 + netif_set_up(netif); + 800af22: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800af24: f005 f8b8 bl 8010098 + netif_set_link_up(netif); + 800af28: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800af2a: f005 f953 bl 80101d4 + +/* USER CODE BEGIN ETH link Thread core code for User BSP */ + +/* USER CODE END ETH link Thread core code for User BSP */ + + osDelay(100); + 800af2e: 2064 movs r0, #100 ; 0x64 + 800af30: f000 f910 bl 800b154 + PHYLinkState = LAN8742_GetLinkState(&LAN8742); + 800af34: e78b b.n 800ae4e + 800af36: bf00 nop + 800af38: 20005468 .word 0x20005468 + 800af3c: 20005380 .word 0x20005380 + +0800af40 : + } +} + +void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + 800af40: b580 push {r7, lr} + 800af42: b086 sub sp, #24 + 800af44: af02 add r7, sp, #8 + 800af46: 6078 str r0, [r7, #4] +/* USER CODE BEGIN HAL ETH RxAllocateCallback */ + struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL); + 800af48: 4812 ldr r0, [pc, #72] ; (800af94 ) + 800af4a: f004 fe11 bl 800fb70 + 800af4e: 60f8 str r0, [r7, #12] + if (p) + 800af50: 68fb ldr r3, [r7, #12] + 800af52: 2b00 cmp r3, #0 + 800af54: d014 beq.n 800af80 + { + /* Get the buff from the struct pbuf address. */ + *buff = (uint8_t *)p + offsetof(RxBuff_t, buff); + 800af56: 68fb ldr r3, [r7, #12] + 800af58: f103 0220 add.w r2, r3, #32 + 800af5c: 687b ldr r3, [r7, #4] + 800af5e: 601a str r2, [r3, #0] + p->custom_free_function = pbuf_free_custom; + 800af60: 68fb ldr r3, [r7, #12] + 800af62: 4a0d ldr r2, [pc, #52] ; (800af98 ) + 800af64: 611a str r2, [r3, #16] + /* Initialize the struct pbuf. + * This must be performed whenever a buffer's allocated because it may be + * changed by lwIP or the app, e.g., pbuf_free decrements ref. */ + pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUF_SIZE); + 800af66: 687b ldr r3, [r7, #4] + 800af68: 681b ldr r3, [r3, #0] + 800af6a: f44f 62c0 mov.w r2, #1536 ; 0x600 + 800af6e: 9201 str r2, [sp, #4] + 800af70: 9300 str r3, [sp, #0] + 800af72: 68fb ldr r3, [r7, #12] + 800af74: 2241 movs r2, #65 ; 0x41 + 800af76: 2100 movs r1, #0 + 800af78: 2000 movs r0, #0 + 800af7a: f005 fb87 bl 801068c + { + RxAllocStatus = RX_ALLOC_ERROR; + *buff = NULL; + } +/* USER CODE END HAL ETH RxAllocateCallback */ +} + 800af7e: e005 b.n 800af8c + RxAllocStatus = RX_ALLOC_ERROR; + 800af80: 4b06 ldr r3, [pc, #24] ; (800af9c ) + 800af82: 2201 movs r2, #1 + 800af84: 701a strb r2, [r3, #0] + *buff = NULL; + 800af86: 687b ldr r3, [r7, #4] + 800af88: 2200 movs r2, #0 + 800af8a: 601a str r2, [r3, #0] +} + 800af8c: bf00 nop + 800af8e: 3710 adds r7, #16 + 800af90: 46bd mov sp, r7 + 800af92: bd80 pop {r7, pc} + 800af94: 080237d0 .word 0x080237d0 + 800af98: 0800abf5 .word 0x0800abf5 + 800af9c: 20005374 .word 0x20005374 + +0800afa0 : + +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + 800afa0: b580 push {r7, lr} + 800afa2: b088 sub sp, #32 + 800afa4: af00 add r7, sp, #0 + 800afa6: 60f8 str r0, [r7, #12] + 800afa8: 60b9 str r1, [r7, #8] + 800afaa: 607a str r2, [r7, #4] + 800afac: 807b strh r3, [r7, #2] +/* USER CODE BEGIN HAL ETH RxLinkCallback */ + + struct pbuf **ppStart = (struct pbuf **)pStart; + 800afae: 68fb ldr r3, [r7, #12] + 800afb0: 61bb str r3, [r7, #24] + struct pbuf **ppEnd = (struct pbuf **)pEnd; + 800afb2: 68bb ldr r3, [r7, #8] + 800afb4: 617b str r3, [r7, #20] + struct pbuf *p = NULL; + 800afb6: 2300 movs r3, #0 + 800afb8: 61fb str r3, [r7, #28] + + /* Get the struct pbuf from the buff address. */ + p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff)); + 800afba: 687b ldr r3, [r7, #4] + 800afbc: 3b20 subs r3, #32 + 800afbe: 61fb str r3, [r7, #28] + p->next = NULL; + 800afc0: 69fb ldr r3, [r7, #28] + 800afc2: 2200 movs r2, #0 + 800afc4: 601a str r2, [r3, #0] + p->tot_len = 0; + 800afc6: 69fb ldr r3, [r7, #28] + 800afc8: 2200 movs r2, #0 + 800afca: 811a strh r2, [r3, #8] + p->len = Length; + 800afcc: 69fb ldr r3, [r7, #28] + 800afce: 887a ldrh r2, [r7, #2] + 800afd0: 815a strh r2, [r3, #10] + + /* Chain the buffer. */ + if (!*ppStart) + 800afd2: 69bb ldr r3, [r7, #24] + 800afd4: 681b ldr r3, [r3, #0] + 800afd6: 2b00 cmp r3, #0 + 800afd8: d103 bne.n 800afe2 + { + /* The first buffer of the packet. */ + *ppStart = p; + 800afda: 69bb ldr r3, [r7, #24] + 800afdc: 69fa ldr r2, [r7, #28] + 800afde: 601a str r2, [r3, #0] + 800afe0: e003 b.n 800afea + } + else + { + /* Chain the buffer to the end of the packet. */ + (*ppEnd)->next = p; + 800afe2: 697b ldr r3, [r7, #20] + 800afe4: 681b ldr r3, [r3, #0] + 800afe6: 69fa ldr r2, [r7, #28] + 800afe8: 601a str r2, [r3, #0] + } + *ppEnd = p; + 800afea: 697b ldr r3, [r7, #20] + 800afec: 69fa ldr r2, [r7, #28] + 800afee: 601a str r2, [r3, #0] + + /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len + * set to its own length, plus the length of all the following pbufs in the chain. */ + for (p = *ppStart; p != NULL; p = p->next) + 800aff0: 69bb ldr r3, [r7, #24] + 800aff2: 681b ldr r3, [r3, #0] + 800aff4: 61fb str r3, [r7, #28] + 800aff6: e009 b.n 800b00c + { + p->tot_len += Length; + 800aff8: 69fb ldr r3, [r7, #28] + 800affa: 891a ldrh r2, [r3, #8] + 800affc: 887b ldrh r3, [r7, #2] + 800affe: 4413 add r3, r2 + 800b000: b29a uxth r2, r3 + 800b002: 69fb ldr r3, [r7, #28] + 800b004: 811a strh r2, [r3, #8] + for (p = *ppStart; p != NULL; p = p->next) + 800b006: 69fb ldr r3, [r7, #28] + 800b008: 681b ldr r3, [r3, #0] + 800b00a: 61fb str r3, [r7, #28] + 800b00c: 69fb ldr r3, [r7, #28] + 800b00e: 2b00 cmp r3, #0 + 800b010: d1f2 bne.n 800aff8 + } + + /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */ + SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length); + 800b012: 887b ldrh r3, [r7, #2] + 800b014: 4619 mov r1, r3 + 800b016: 6878 ldr r0, [r7, #4] + 800b018: f7ff fb4c bl 800a6b4 + +/* USER CODE END HAL ETH RxLinkCallback */ +} + 800b01c: bf00 nop + 800b01e: 3720 adds r7, #32 + 800b020: 46bd mov sp, r7 + 800b022: bd80 pop {r7, pc} + +0800b024 : + +void HAL_ETH_TxFreeCallback(uint32_t * buff) +{ + 800b024: b580 push {r7, lr} + 800b026: b082 sub sp, #8 + 800b028: af00 add r7, sp, #0 + 800b02a: 6078 str r0, [r7, #4] +/* USER CODE BEGIN HAL ETH TxFreeCallback */ + + pbuf_free((struct pbuf *)buff); + 800b02c: 6878 ldr r0, [r7, #4] + 800b02e: f005 fce7 bl 8010a00 + +/* USER CODE END HAL ETH TxFreeCallback */ +} + 800b032: bf00 nop + 800b034: 3708 adds r7, #8 + 800b036: 46bd mov sp, r7 + 800b038: bd80 pop {r7, pc} + +0800b03a : + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + 800b03a: b480 push {r7} + 800b03c: b085 sub sp, #20 + 800b03e: af00 add r7, sp, #0 + 800b040: 4603 mov r3, r0 + 800b042: 80fb strh r3, [r7, #6] + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + 800b044: 2300 movs r3, #0 + 800b046: 60fb str r3, [r7, #12] + + if (priority != osPriorityError) { + 800b048: f9b7 3006 ldrsh.w r3, [r7, #6] + 800b04c: 2b84 cmp r3, #132 ; 0x84 + 800b04e: d005 beq.n 800b05c + fpriority += (priority - osPriorityIdle); + 800b050: f9b7 2006 ldrsh.w r2, [r7, #6] + 800b054: 68fb ldr r3, [r7, #12] + 800b056: 4413 add r3, r2 + 800b058: 3303 adds r3, #3 + 800b05a: 60fb str r3, [r7, #12] + } + + return fpriority; + 800b05c: 68fb ldr r3, [r7, #12] +} + 800b05e: 4618 mov r0, r3 + 800b060: 3714 adds r7, #20 + 800b062: 46bd mov sp, r7 + 800b064: f85d 7b04 ldr.w r7, [sp], #4 + 800b068: 4770 bx lr + +0800b06a : +#endif + + +/* Determine whether we are in thread mode or handler mode. */ +static int inHandlerMode (void) +{ + 800b06a: b480 push {r7} + 800b06c: b083 sub sp, #12 + 800b06e: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 800b070: f3ef 8305 mrs r3, IPSR + 800b074: 607b str r3, [r7, #4] + return(result); + 800b076: 687b ldr r3, [r7, #4] + return __get_IPSR() != 0; + 800b078: 2b00 cmp r3, #0 + 800b07a: bf14 ite ne + 800b07c: 2301 movne r3, #1 + 800b07e: 2300 moveq r3, #0 + 800b080: b2db uxtb r3, r3 +} + 800b082: 4618 mov r0, r3 + 800b084: 370c adds r7, #12 + 800b086: 46bd mov sp, r7 + 800b088: f85d 7b04 ldr.w r7, [sp], #4 + 800b08c: 4770 bx lr + +0800b08e : +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + 800b08e: b580 push {r7, lr} + 800b090: af00 add r7, sp, #0 + vTaskStartScheduler(); + 800b092: f001 fc89 bl 800c9a8 + + return osOK; + 800b096: 2300 movs r3, #0 +} + 800b098: 4618 mov r0, r3 + 800b09a: bd80 pop {r7, pc} + +0800b09c : +* @param None +* @retval None +* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +*/ +uint32_t osKernelSysTick(void) +{ + 800b09c: b580 push {r7, lr} + 800b09e: af00 add r7, sp, #0 + if (inHandlerMode()) { + 800b0a0: f7ff ffe3 bl 800b06a + 800b0a4: 4603 mov r3, r0 + 800b0a6: 2b00 cmp r3, #0 + 800b0a8: d003 beq.n 800b0b2 + return xTaskGetTickCountFromISR(); + 800b0aa: f001 fda7 bl 800cbfc + 800b0ae: 4603 mov r3, r0 + 800b0b0: e002 b.n 800b0b8 + } + else { + return xTaskGetTickCount(); + 800b0b2: f001 fd93 bl 800cbdc + 800b0b6: 4603 mov r3, r0 + } +} + 800b0b8: 4618 mov r0, r3 + 800b0ba: bd80 pop {r7, pc} + +0800b0bc : +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + 800b0bc: b5f0 push {r4, r5, r6, r7, lr} + 800b0be: b089 sub sp, #36 ; 0x24 + 800b0c0: af04 add r7, sp, #16 + 800b0c2: 6078 str r0, [r7, #4] + 800b0c4: 6039 str r1, [r7, #0] + TaskHandle_t handle; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { + 800b0c6: 687b ldr r3, [r7, #4] + 800b0c8: 695b ldr r3, [r3, #20] + 800b0ca: 2b00 cmp r3, #0 + 800b0cc: d020 beq.n 800b110 + 800b0ce: 687b ldr r3, [r7, #4] + 800b0d0: 699b ldr r3, [r3, #24] + 800b0d2: 2b00 cmp r3, #0 + 800b0d4: d01c beq.n 800b110 + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800b0d6: 687b ldr r3, [r7, #4] + 800b0d8: 685c ldr r4, [r3, #4] + 800b0da: 687b ldr r3, [r7, #4] + 800b0dc: 681d ldr r5, [r3, #0] + 800b0de: 687b ldr r3, [r7, #4] + 800b0e0: 691e ldr r6, [r3, #16] + 800b0e2: 687b ldr r3, [r7, #4] + 800b0e4: f9b3 3008 ldrsh.w r3, [r3, #8] + 800b0e8: 4618 mov r0, r3 + 800b0ea: f7ff ffa6 bl 800b03a + 800b0ee: 4601 mov r1, r0 + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); + 800b0f0: 687b ldr r3, [r7, #4] + 800b0f2: 695b ldr r3, [r3, #20] + 800b0f4: 687a ldr r2, [r7, #4] + 800b0f6: 6992 ldr r2, [r2, #24] + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800b0f8: 9202 str r2, [sp, #8] + 800b0fa: 9301 str r3, [sp, #4] + 800b0fc: 9100 str r1, [sp, #0] + 800b0fe: 683b ldr r3, [r7, #0] + 800b100: 4632 mov r2, r6 + 800b102: 4629 mov r1, r5 + 800b104: 4620 mov r0, r4 + 800b106: f001 fa67 bl 800c5d8 + 800b10a: 4603 mov r3, r0 + 800b10c: 60fb str r3, [r7, #12] + 800b10e: e01c b.n 800b14a + } + else { + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800b110: 687b ldr r3, [r7, #4] + 800b112: 685c ldr r4, [r3, #4] + 800b114: 687b ldr r3, [r7, #4] + 800b116: 681d ldr r5, [r3, #0] + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + 800b118: 687b ldr r3, [r7, #4] + 800b11a: 691b ldr r3, [r3, #16] + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800b11c: b29e uxth r6, r3 + 800b11e: 687b ldr r3, [r7, #4] + 800b120: f9b3 3008 ldrsh.w r3, [r3, #8] + 800b124: 4618 mov r0, r3 + 800b126: f7ff ff88 bl 800b03a + 800b12a: 4602 mov r2, r0 + 800b12c: f107 030c add.w r3, r7, #12 + 800b130: 9301 str r3, [sp, #4] + 800b132: 9200 str r2, [sp, #0] + 800b134: 683b ldr r3, [r7, #0] + 800b136: 4632 mov r2, r6 + 800b138: 4629 mov r1, r5 + 800b13a: 4620 mov r0, r4 + 800b13c: f001 faaf bl 800c69e + 800b140: 4603 mov r3, r0 + 800b142: 2b01 cmp r3, #1 + 800b144: d001 beq.n 800b14a + &handle) != pdPASS) { + return NULL; + 800b146: 2300 movs r3, #0 + 800b148: e000 b.n 800b14c + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; + 800b14a: 68fb ldr r3, [r7, #12] +} + 800b14c: 4618 mov r0, r3 + 800b14e: 3714 adds r7, #20 + 800b150: 46bd mov sp, r7 + 800b152: bdf0 pop {r4, r5, r6, r7, pc} + +0800b154 : +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ + 800b154: b580 push {r7, lr} + 800b156: b084 sub sp, #16 + 800b158: af00 add r7, sp, #0 + 800b15a: 6078 str r0, [r7, #4] +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + 800b15c: 687b ldr r3, [r7, #4] + 800b15e: 60fb str r3, [r7, #12] + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + 800b160: 68fb ldr r3, [r7, #12] + 800b162: 2b00 cmp r3, #0 + 800b164: d001 beq.n 800b16a + 800b166: 68fb ldr r3, [r7, #12] + 800b168: e000 b.n 800b16c + 800b16a: 2301 movs r3, #1 + 800b16c: 4618 mov r0, r3 + 800b16e: f001 fbe5 bl 800c93c + + return osOK; + 800b172: 2300 movs r3, #0 +#else + (void) millisec; + + return osErrorResource; +#endif +} + 800b174: 4618 mov r0, r3 + 800b176: 3710 adds r7, #16 + 800b178: 46bd mov sp, r7 + 800b17a: bd80 pop {r7, pc} + +0800b17c : +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +*/ +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) +{ + 800b17c: b580 push {r7, lr} + 800b17e: b082 sub sp, #8 + 800b180: af00 add r7, sp, #0 + 800b182: 6078 str r0, [r7, #4] +#if ( configUSE_MUTEXES == 1) + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL) { + 800b184: 687b ldr r3, [r7, #4] + 800b186: 685b ldr r3, [r3, #4] + 800b188: 2b00 cmp r3, #0 + 800b18a: d007 beq.n 800b19c + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); + 800b18c: 687b ldr r3, [r7, #4] + 800b18e: 685b ldr r3, [r3, #4] + 800b190: 4619 mov r1, r3 + 800b192: 2001 movs r0, #1 + 800b194: f000 fc21 bl 800b9da + 800b198: 4603 mov r3, r0 + 800b19a: e003 b.n 800b1a4 + } + else { + return xSemaphoreCreateMutex(); + 800b19c: 2001 movs r0, #1 + 800b19e: f000 fc04 bl 800b9aa + 800b1a2: 4603 mov r3, r0 + return xSemaphoreCreateMutex(); +#endif +#else + return NULL; +#endif +} + 800b1a4: 4618 mov r0, r3 + 800b1a6: 3708 adds r7, #8 + 800b1a8: 46bd mov sp, r7 + 800b1aa: bd80 pop {r7, pc} + +0800b1ac : +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) +{ + 800b1ac: b580 push {r7, lr} + 800b1ae: b084 sub sp, #16 + 800b1b0: af00 add r7, sp, #0 + 800b1b2: 6078 str r0, [r7, #4] + 800b1b4: 6039 str r1, [r7, #0] + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + 800b1b6: 2300 movs r3, #0 + 800b1b8: 60bb str r3, [r7, #8] + + + if (mutex_id == NULL) { + 800b1ba: 687b ldr r3, [r7, #4] + 800b1bc: 2b00 cmp r3, #0 + 800b1be: d101 bne.n 800b1c4 + return osErrorParameter; + 800b1c0: 2380 movs r3, #128 ; 0x80 + 800b1c2: e03a b.n 800b23a + } + + ticks = 0; + 800b1c4: 2300 movs r3, #0 + 800b1c6: 60fb str r3, [r7, #12] + if (millisec == osWaitForever) { + 800b1c8: 683b ldr r3, [r7, #0] + 800b1ca: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b1ce: d103 bne.n 800b1d8 + ticks = portMAX_DELAY; + 800b1d0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800b1d4: 60fb str r3, [r7, #12] + 800b1d6: e009 b.n 800b1ec + } + else if (millisec != 0) { + 800b1d8: 683b ldr r3, [r7, #0] + 800b1da: 2b00 cmp r3, #0 + 800b1dc: d006 beq.n 800b1ec + ticks = millisec / portTICK_PERIOD_MS; + 800b1de: 683b ldr r3, [r7, #0] + 800b1e0: 60fb str r3, [r7, #12] + if (ticks == 0) { + 800b1e2: 68fb ldr r3, [r7, #12] + 800b1e4: 2b00 cmp r3, #0 + 800b1e6: d101 bne.n 800b1ec + ticks = 1; + 800b1e8: 2301 movs r3, #1 + 800b1ea: 60fb str r3, [r7, #12] + } + } + + if (inHandlerMode()) { + 800b1ec: f7ff ff3d bl 800b06a + 800b1f0: 4603 mov r3, r0 + 800b1f2: 2b00 cmp r3, #0 + 800b1f4: d017 beq.n 800b226 + if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) { + 800b1f6: f107 0308 add.w r3, r7, #8 + 800b1fa: 461a mov r2, r3 + 800b1fc: 2100 movs r1, #0 + 800b1fe: 6878 ldr r0, [r7, #4] + 800b200: f001 f83c bl 800c27c + 800b204: 4603 mov r3, r0 + 800b206: 2b01 cmp r3, #1 + 800b208: d001 beq.n 800b20e + return osErrorOS; + 800b20a: 23ff movs r3, #255 ; 0xff + 800b20c: e015 b.n 800b23a + } + portEND_SWITCHING_ISR(taskWoken); + 800b20e: 68bb ldr r3, [r7, #8] + 800b210: 2b00 cmp r3, #0 + 800b212: d011 beq.n 800b238 + 800b214: 4b0b ldr r3, [pc, #44] ; (800b244 ) + 800b216: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b21a: 601a str r2, [r3, #0] + 800b21c: f3bf 8f4f dsb sy + 800b220: f3bf 8f6f isb sy + 800b224: e008 b.n 800b238 + } + else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) { + 800b226: 68f9 ldr r1, [r7, #12] + 800b228: 6878 ldr r0, [r7, #4] + 800b22a: f000 ff13 bl 800c054 + 800b22e: 4603 mov r3, r0 + 800b230: 2b01 cmp r3, #1 + 800b232: d001 beq.n 800b238 + return osErrorOS; + 800b234: 23ff movs r3, #255 ; 0xff + 800b236: e000 b.n 800b23a + } + + return osOK; + 800b238: 2300 movs r3, #0 +} + 800b23a: 4618 mov r0, r3 + 800b23c: 3710 adds r7, #16 + 800b23e: 46bd mov sp, r7 + 800b240: bd80 pop {r7, pc} + 800b242: bf00 nop + 800b244: e000ed04 .word 0xe000ed04 + +0800b248 : +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexRelease (osMutexId mutex_id) +{ + 800b248: b580 push {r7, lr} + 800b24a: b084 sub sp, #16 + 800b24c: af00 add r7, sp, #0 + 800b24e: 6078 str r0, [r7, #4] + osStatus result = osOK; + 800b250: 2300 movs r3, #0 + 800b252: 60fb str r3, [r7, #12] + portBASE_TYPE taskWoken = pdFALSE; + 800b254: 2300 movs r3, #0 + 800b256: 60bb str r3, [r7, #8] + + if (inHandlerMode()) { + 800b258: f7ff ff07 bl 800b06a + 800b25c: 4603 mov r3, r0 + 800b25e: 2b00 cmp r3, #0 + 800b260: d016 beq.n 800b290 + if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) { + 800b262: f107 0308 add.w r3, r7, #8 + 800b266: 4619 mov r1, r3 + 800b268: 6878 ldr r0, [r7, #4] + 800b26a: f000 fd77 bl 800bd5c + 800b26e: 4603 mov r3, r0 + 800b270: 2b01 cmp r3, #1 + 800b272: d001 beq.n 800b278 + return osErrorOS; + 800b274: 23ff movs r3, #255 ; 0xff + 800b276: e017 b.n 800b2a8 + } + portEND_SWITCHING_ISR(taskWoken); + 800b278: 68bb ldr r3, [r7, #8] + 800b27a: 2b00 cmp r3, #0 + 800b27c: d013 beq.n 800b2a6 + 800b27e: 4b0c ldr r3, [pc, #48] ; (800b2b0 ) + 800b280: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b284: 601a str r2, [r3, #0] + 800b286: f3bf 8f4f dsb sy + 800b28a: f3bf 8f6f isb sy + 800b28e: e00a b.n 800b2a6 + } + else if (xSemaphoreGive(mutex_id) != pdTRUE) + 800b290: 2300 movs r3, #0 + 800b292: 2200 movs r2, #0 + 800b294: 2100 movs r1, #0 + 800b296: 6878 ldr r0, [r7, #4] + 800b298: f000 fbba bl 800ba10 + 800b29c: 4603 mov r3, r0 + 800b29e: 2b01 cmp r3, #1 + 800b2a0: d001 beq.n 800b2a6 + { + result = osErrorOS; + 800b2a2: 23ff movs r3, #255 ; 0xff + 800b2a4: 60fb str r3, [r7, #12] + } + return result; + 800b2a6: 68fb ldr r3, [r7, #12] +} + 800b2a8: 4618 mov r0, r3 + 800b2aa: 3710 adds r7, #16 + 800b2ac: 46bd mov sp, r7 + 800b2ae: bd80 pop {r7, pc} + 800b2b0: e000ed04 .word 0xe000ed04 + +0800b2b4 : +* @param millisec timeout value or 0 in case of no time-out. +* @retval number of available tokens, or -1 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +{ + 800b2b4: b580 push {r7, lr} + 800b2b6: b084 sub sp, #16 + 800b2b8: af00 add r7, sp, #0 + 800b2ba: 6078 str r0, [r7, #4] + 800b2bc: 6039 str r1, [r7, #0] + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + 800b2be: 2300 movs r3, #0 + 800b2c0: 60bb str r3, [r7, #8] + + + if (semaphore_id == NULL) { + 800b2c2: 687b ldr r3, [r7, #4] + 800b2c4: 2b00 cmp r3, #0 + 800b2c6: d101 bne.n 800b2cc + return osErrorParameter; + 800b2c8: 2380 movs r3, #128 ; 0x80 + 800b2ca: e03a b.n 800b342 + } + + ticks = 0; + 800b2cc: 2300 movs r3, #0 + 800b2ce: 60fb str r3, [r7, #12] + if (millisec == osWaitForever) { + 800b2d0: 683b ldr r3, [r7, #0] + 800b2d2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b2d6: d103 bne.n 800b2e0 + ticks = portMAX_DELAY; + 800b2d8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800b2dc: 60fb str r3, [r7, #12] + 800b2de: e009 b.n 800b2f4 + } + else if (millisec != 0) { + 800b2e0: 683b ldr r3, [r7, #0] + 800b2e2: 2b00 cmp r3, #0 + 800b2e4: d006 beq.n 800b2f4 + ticks = millisec / portTICK_PERIOD_MS; + 800b2e6: 683b ldr r3, [r7, #0] + 800b2e8: 60fb str r3, [r7, #12] + if (ticks == 0) { + 800b2ea: 68fb ldr r3, [r7, #12] + 800b2ec: 2b00 cmp r3, #0 + 800b2ee: d101 bne.n 800b2f4 + ticks = 1; + 800b2f0: 2301 movs r3, #1 + 800b2f2: 60fb str r3, [r7, #12] + } + } + + if (inHandlerMode()) { + 800b2f4: f7ff feb9 bl 800b06a + 800b2f8: 4603 mov r3, r0 + 800b2fa: 2b00 cmp r3, #0 + 800b2fc: d017 beq.n 800b32e + if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) { + 800b2fe: f107 0308 add.w r3, r7, #8 + 800b302: 461a mov r2, r3 + 800b304: 2100 movs r1, #0 + 800b306: 6878 ldr r0, [r7, #4] + 800b308: f000 ffb8 bl 800c27c + 800b30c: 4603 mov r3, r0 + 800b30e: 2b01 cmp r3, #1 + 800b310: d001 beq.n 800b316 + return osErrorOS; + 800b312: 23ff movs r3, #255 ; 0xff + 800b314: e015 b.n 800b342 + } + portEND_SWITCHING_ISR(taskWoken); + 800b316: 68bb ldr r3, [r7, #8] + 800b318: 2b00 cmp r3, #0 + 800b31a: d011 beq.n 800b340 + 800b31c: 4b0b ldr r3, [pc, #44] ; (800b34c ) + 800b31e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b322: 601a str r2, [r3, #0] + 800b324: f3bf 8f4f dsb sy + 800b328: f3bf 8f6f isb sy + 800b32c: e008 b.n 800b340 + } + else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) { + 800b32e: 68f9 ldr r1, [r7, #12] + 800b330: 6878 ldr r0, [r7, #4] + 800b332: f000 fe8f bl 800c054 + 800b336: 4603 mov r3, r0 + 800b338: 2b01 cmp r3, #1 + 800b33a: d001 beq.n 800b340 + return osErrorOS; + 800b33c: 23ff movs r3, #255 ; 0xff + 800b33e: e000 b.n 800b342 + } + + return osOK; + 800b340: 2300 movs r3, #0 +} + 800b342: 4618 mov r0, r3 + 800b344: 3710 adds r7, #16 + 800b346: 46bd mov sp, r7 + 800b348: bd80 pop {r7, pc} + 800b34a: bf00 nop + 800b34c: e000ed04 .word 0xe000ed04 + +0800b350 : +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) +{ + 800b350: b580 push {r7, lr} + 800b352: b084 sub sp, #16 + 800b354: af00 add r7, sp, #0 + 800b356: 6078 str r0, [r7, #4] + osStatus result = osOK; + 800b358: 2300 movs r3, #0 + 800b35a: 60fb str r3, [r7, #12] + portBASE_TYPE taskWoken = pdFALSE; + 800b35c: 2300 movs r3, #0 + 800b35e: 60bb str r3, [r7, #8] + + + if (inHandlerMode()) { + 800b360: f7ff fe83 bl 800b06a + 800b364: 4603 mov r3, r0 + 800b366: 2b00 cmp r3, #0 + 800b368: d016 beq.n 800b398 + if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) { + 800b36a: f107 0308 add.w r3, r7, #8 + 800b36e: 4619 mov r1, r3 + 800b370: 6878 ldr r0, [r7, #4] + 800b372: f000 fcf3 bl 800bd5c + 800b376: 4603 mov r3, r0 + 800b378: 2b01 cmp r3, #1 + 800b37a: d001 beq.n 800b380 + return osErrorOS; + 800b37c: 23ff movs r3, #255 ; 0xff + 800b37e: e017 b.n 800b3b0 + } + portEND_SWITCHING_ISR(taskWoken); + 800b380: 68bb ldr r3, [r7, #8] + 800b382: 2b00 cmp r3, #0 + 800b384: d013 beq.n 800b3ae + 800b386: 4b0c ldr r3, [pc, #48] ; (800b3b8 ) + 800b388: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b38c: 601a str r2, [r3, #0] + 800b38e: f3bf 8f4f dsb sy + 800b392: f3bf 8f6f isb sy + 800b396: e00a b.n 800b3ae + } + else { + if (xSemaphoreGive(semaphore_id) != pdTRUE) { + 800b398: 2300 movs r3, #0 + 800b39a: 2200 movs r2, #0 + 800b39c: 2100 movs r1, #0 + 800b39e: 6878 ldr r0, [r7, #4] + 800b3a0: f000 fb36 bl 800ba10 + 800b3a4: 4603 mov r3, r0 + 800b3a6: 2b01 cmp r3, #1 + 800b3a8: d001 beq.n 800b3ae + result = osErrorOS; + 800b3aa: 23ff movs r3, #255 ; 0xff + 800b3ac: 60fb str r3, [r7, #12] + } + } + + return result; + 800b3ae: 68fb ldr r3, [r7, #12] +} + 800b3b0: 4618 mov r0, r3 + 800b3b2: 3710 adds r7, #16 + 800b3b4: 46bd mov sp, r7 + 800b3b6: bd80 pop {r7, pc} + 800b3b8: e000ed04 .word 0xe000ed04 + +0800b3bc : +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval message queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +*/ +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) +{ + 800b3bc: b590 push {r4, r7, lr} + 800b3be: b085 sub sp, #20 + 800b3c0: af02 add r7, sp, #8 + 800b3c2: 6078 str r0, [r7, #4] + 800b3c4: 6039 str r1, [r7, #0] + (void) thread_id; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) { + 800b3c6: 687b ldr r3, [r7, #4] + 800b3c8: 689b ldr r3, [r3, #8] + 800b3ca: 2b00 cmp r3, #0 + 800b3cc: d011 beq.n 800b3f2 + 800b3ce: 687b ldr r3, [r7, #4] + 800b3d0: 68db ldr r3, [r3, #12] + 800b3d2: 2b00 cmp r3, #0 + 800b3d4: d00d beq.n 800b3f2 + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); + 800b3d6: 687b ldr r3, [r7, #4] + 800b3d8: 6818 ldr r0, [r3, #0] + 800b3da: 687b ldr r3, [r7, #4] + 800b3dc: 6859 ldr r1, [r3, #4] + 800b3de: 687b ldr r3, [r7, #4] + 800b3e0: 689a ldr r2, [r3, #8] + 800b3e2: 687b ldr r3, [r7, #4] + 800b3e4: 68db ldr r3, [r3, #12] + 800b3e6: 2400 movs r4, #0 + 800b3e8: 9400 str r4, [sp, #0] + 800b3ea: f000 f9e1 bl 800b7b0 + 800b3ee: 4603 mov r3, r0 + 800b3f0: e008 b.n 800b404 + } + else { + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); + 800b3f2: 687b ldr r3, [r7, #4] + 800b3f4: 6818 ldr r0, [r3, #0] + 800b3f6: 687b ldr r3, [r7, #4] + 800b3f8: 685b ldr r3, [r3, #4] + 800b3fa: 2200 movs r2, #0 + 800b3fc: 4619 mov r1, r3 + 800b3fe: f000 fa59 bl 800b8b4 + 800b402: 4603 mov r3, r0 +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); +#else + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); +#endif +} + 800b404: 4618 mov r0, r3 + 800b406: 370c adds r7, #12 + 800b408: 46bd mov sp, r7 + 800b40a: bd90 pop {r4, r7, pc} + +0800b40c : +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) +{ + 800b40c: b580 push {r7, lr} + 800b40e: b086 sub sp, #24 + 800b410: af00 add r7, sp, #0 + 800b412: 60f8 str r0, [r7, #12] + 800b414: 60b9 str r1, [r7, #8] + 800b416: 607a str r2, [r7, #4] + portBASE_TYPE taskWoken = pdFALSE; + 800b418: 2300 movs r3, #0 + 800b41a: 613b str r3, [r7, #16] + TickType_t ticks; + + ticks = millisec / portTICK_PERIOD_MS; + 800b41c: 687b ldr r3, [r7, #4] + 800b41e: 617b str r3, [r7, #20] + if (ticks == 0) { + 800b420: 697b ldr r3, [r7, #20] + 800b422: 2b00 cmp r3, #0 + 800b424: d101 bne.n 800b42a + ticks = 1; + 800b426: 2301 movs r3, #1 + 800b428: 617b str r3, [r7, #20] + } + + if (inHandlerMode()) { + 800b42a: f7ff fe1e bl 800b06a + 800b42e: 4603 mov r3, r0 + 800b430: 2b00 cmp r3, #0 + 800b432: d018 beq.n 800b466 + if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { + 800b434: f107 0210 add.w r2, r7, #16 + 800b438: f107 0108 add.w r1, r7, #8 + 800b43c: 2300 movs r3, #0 + 800b43e: 68f8 ldr r0, [r7, #12] + 800b440: f000 fbec bl 800bc1c + 800b444: 4603 mov r3, r0 + 800b446: 2b01 cmp r3, #1 + 800b448: d001 beq.n 800b44e + return osErrorOS; + 800b44a: 23ff movs r3, #255 ; 0xff + 800b44c: e018 b.n 800b480 + } + portEND_SWITCHING_ISR(taskWoken); + 800b44e: 693b ldr r3, [r7, #16] + 800b450: 2b00 cmp r3, #0 + 800b452: d014 beq.n 800b47e + 800b454: 4b0c ldr r3, [pc, #48] ; (800b488 ) + 800b456: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b45a: 601a str r2, [r3, #0] + 800b45c: f3bf 8f4f dsb sy + 800b460: f3bf 8f6f isb sy + 800b464: e00b b.n 800b47e + } + else { + if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { + 800b466: f107 0108 add.w r1, r7, #8 + 800b46a: 2300 movs r3, #0 + 800b46c: 697a ldr r2, [r7, #20] + 800b46e: 68f8 ldr r0, [r7, #12] + 800b470: f000 face bl 800ba10 + 800b474: 4603 mov r3, r0 + 800b476: 2b01 cmp r3, #1 + 800b478: d001 beq.n 800b47e + return osErrorOS; + 800b47a: 23ff movs r3, #255 ; 0xff + 800b47c: e000 b.n 800b480 + } + } + + return osOK; + 800b47e: 2300 movs r3, #0 +} + 800b480: 4618 mov r0, r3 + 800b482: 3718 adds r7, #24 + 800b484: 46bd mov sp, r7 + 800b486: bd80 pop {r7, pc} + 800b488: e000ed04 .word 0xe000ed04 + +0800b48c : +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) +{ + 800b48c: b590 push {r4, r7, lr} + 800b48e: b08b sub sp, #44 ; 0x2c + 800b490: af00 add r7, sp, #0 + 800b492: 60f8 str r0, [r7, #12] + 800b494: 60b9 str r1, [r7, #8] + 800b496: 607a str r2, [r7, #4] + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + 800b498: 68bb ldr r3, [r7, #8] + 800b49a: 61fb str r3, [r7, #28] + event.value.v = 0; + 800b49c: 2300 movs r3, #0 + 800b49e: 61bb str r3, [r7, #24] + + if (queue_id == NULL) { + 800b4a0: 68bb ldr r3, [r7, #8] + 800b4a2: 2b00 cmp r3, #0 + 800b4a4: d10a bne.n 800b4bc + event.status = osErrorParameter; + 800b4a6: 2380 movs r3, #128 ; 0x80 + 800b4a8: 617b str r3, [r7, #20] + return event; + 800b4aa: 68fb ldr r3, [r7, #12] + 800b4ac: 461c mov r4, r3 + 800b4ae: f107 0314 add.w r3, r7, #20 + 800b4b2: e893 0007 ldmia.w r3, {r0, r1, r2} + 800b4b6: e884 0007 stmia.w r4, {r0, r1, r2} + 800b4ba: e054 b.n 800b566 + } + + taskWoken = pdFALSE; + 800b4bc: 2300 movs r3, #0 + 800b4be: 623b str r3, [r7, #32] + + ticks = 0; + 800b4c0: 2300 movs r3, #0 + 800b4c2: 627b str r3, [r7, #36] ; 0x24 + if (millisec == osWaitForever) { + 800b4c4: 687b ldr r3, [r7, #4] + 800b4c6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b4ca: d103 bne.n 800b4d4 + ticks = portMAX_DELAY; + 800b4cc: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800b4d0: 627b str r3, [r7, #36] ; 0x24 + 800b4d2: e009 b.n 800b4e8 + } + else if (millisec != 0) { + 800b4d4: 687b ldr r3, [r7, #4] + 800b4d6: 2b00 cmp r3, #0 + 800b4d8: d006 beq.n 800b4e8 + ticks = millisec / portTICK_PERIOD_MS; + 800b4da: 687b ldr r3, [r7, #4] + 800b4dc: 627b str r3, [r7, #36] ; 0x24 + if (ticks == 0) { + 800b4de: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b4e0: 2b00 cmp r3, #0 + 800b4e2: d101 bne.n 800b4e8 + ticks = 1; + 800b4e4: 2301 movs r3, #1 + 800b4e6: 627b str r3, [r7, #36] ; 0x24 + } + } + + if (inHandlerMode()) { + 800b4e8: f7ff fdbf bl 800b06a + 800b4ec: 4603 mov r3, r0 + 800b4ee: 2b00 cmp r3, #0 + 800b4f0: d01c beq.n 800b52c + if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) { + 800b4f2: f107 0220 add.w r2, r7, #32 + 800b4f6: f107 0314 add.w r3, r7, #20 + 800b4fa: 3304 adds r3, #4 + 800b4fc: 4619 mov r1, r3 + 800b4fe: 68b8 ldr r0, [r7, #8] + 800b500: f000 febc bl 800c27c + 800b504: 4603 mov r3, r0 + 800b506: 2b01 cmp r3, #1 + 800b508: d102 bne.n 800b510 + /* We have mail */ + event.status = osEventMessage; + 800b50a: 2310 movs r3, #16 + 800b50c: 617b str r3, [r7, #20] + 800b50e: e001 b.n 800b514 + } + else { + event.status = osOK; + 800b510: 2300 movs r3, #0 + 800b512: 617b str r3, [r7, #20] + } + portEND_SWITCHING_ISR(taskWoken); + 800b514: 6a3b ldr r3, [r7, #32] + 800b516: 2b00 cmp r3, #0 + 800b518: d01d beq.n 800b556 + 800b51a: 4b15 ldr r3, [pc, #84] ; (800b570 ) + 800b51c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b520: 601a str r2, [r3, #0] + 800b522: f3bf 8f4f dsb sy + 800b526: f3bf 8f6f isb sy + 800b52a: e014 b.n 800b556 + } + else { + if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) { + 800b52c: f107 0314 add.w r3, r7, #20 + 800b530: 3304 adds r3, #4 + 800b532: 6a7a ldr r2, [r7, #36] ; 0x24 + 800b534: 4619 mov r1, r3 + 800b536: 68b8 ldr r0, [r7, #8] + 800b538: f000 fca6 bl 800be88 + 800b53c: 4603 mov r3, r0 + 800b53e: 2b01 cmp r3, #1 + 800b540: d102 bne.n 800b548 + /* We have mail */ + event.status = osEventMessage; + 800b542: 2310 movs r3, #16 + 800b544: 617b str r3, [r7, #20] + 800b546: e006 b.n 800b556 + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + 800b548: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b54a: 2b00 cmp r3, #0 + 800b54c: d101 bne.n 800b552 + 800b54e: 2300 movs r3, #0 + 800b550: e000 b.n 800b554 + 800b552: 2340 movs r3, #64 ; 0x40 + 800b554: 617b str r3, [r7, #20] + } + } + + return event; + 800b556: 68fb ldr r3, [r7, #12] + 800b558: 461c mov r4, r3 + 800b55a: f107 0314 add.w r3, r7, #20 + 800b55e: e893 0007 ldmia.w r3, {r0, r1, r2} + 800b562: e884 0007 stmia.w r4, {r0, r1, r2} +} + 800b566: 68f8 ldr r0, [r7, #12] + 800b568: 372c adds r7, #44 ; 0x2c + 800b56a: 46bd mov sp, r7 + 800b56c: bd90 pop {r4, r7, pc} + 800b56e: bf00 nop + 800b570: e000ed04 .word 0xe000ed04 + +0800b574 : +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + 800b574: b480 push {r7} + 800b576: b083 sub sp, #12 + 800b578: af00 add r7, sp, #0 + 800b57a: 6078 str r0, [r7, #4] + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800b57c: 687b ldr r3, [r7, #4] + 800b57e: f103 0208 add.w r2, r3, #8 + 800b582: 687b ldr r3, [r7, #4] + 800b584: 605a str r2, [r3, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 800b586: 687b ldr r3, [r7, #4] + 800b588: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800b58c: 609a str r2, [r3, #8] + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800b58e: 687b ldr r3, [r7, #4] + 800b590: f103 0208 add.w r2, r3, #8 + 800b594: 687b ldr r3, [r7, #4] + 800b596: 60da str r2, [r3, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800b598: 687b ldr r3, [r7, #4] + 800b59a: f103 0208 add.w r2, r3, #8 + 800b59e: 687b ldr r3, [r7, #4] + 800b5a0: 611a str r2, [r3, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 800b5a2: 687b ldr r3, [r7, #4] + 800b5a4: 2200 movs r2, #0 + 800b5a6: 601a str r2, [r3, #0] + + /* Write known values into the list if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} + 800b5a8: bf00 nop + 800b5aa: 370c adds r7, #12 + 800b5ac: 46bd mov sp, r7 + 800b5ae: f85d 7b04 ldr.w r7, [sp], #4 + 800b5b2: 4770 bx lr + +0800b5b4 : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + 800b5b4: b480 push {r7} + 800b5b6: b083 sub sp, #12 + 800b5b8: af00 add r7, sp, #0 + 800b5ba: 6078 str r0, [r7, #4] + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + 800b5bc: 687b ldr r3, [r7, #4] + 800b5be: 2200 movs r2, #0 + 800b5c0: 611a str r2, [r3, #16] + + /* Write known values into the list item if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} + 800b5c2: bf00 nop + 800b5c4: 370c adds r7, #12 + 800b5c6: 46bd mov sp, r7 + 800b5c8: f85d 7b04 ldr.w r7, [sp], #4 + 800b5cc: 4770 bx lr + +0800b5ce : +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800b5ce: b480 push {r7} + 800b5d0: b085 sub sp, #20 + 800b5d2: af00 add r7, sp, #0 + 800b5d4: 6078 str r0, [r7, #4] + 800b5d6: 6039 str r1, [r7, #0] +ListItem_t * const pxIndex = pxList->pxIndex; + 800b5d8: 687b ldr r3, [r7, #4] + 800b5da: 685b ldr r3, [r3, #4] + 800b5dc: 60fb str r3, [r7, #12] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 800b5de: 683b ldr r3, [r7, #0] + 800b5e0: 68fa ldr r2, [r7, #12] + 800b5e2: 605a str r2, [r3, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 800b5e4: 68fb ldr r3, [r7, #12] + 800b5e6: 689a ldr r2, [r3, #8] + 800b5e8: 683b ldr r3, [r7, #0] + 800b5ea: 609a str r2, [r3, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 800b5ec: 68fb ldr r3, [r7, #12] + 800b5ee: 689b ldr r3, [r3, #8] + 800b5f0: 683a ldr r2, [r7, #0] + 800b5f2: 605a str r2, [r3, #4] + pxIndex->pxPrevious = pxNewListItem; + 800b5f4: 68fb ldr r3, [r7, #12] + 800b5f6: 683a ldr r2, [r7, #0] + 800b5f8: 609a str r2, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + 800b5fa: 683b ldr r3, [r7, #0] + 800b5fc: 687a ldr r2, [r7, #4] + 800b5fe: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 800b600: 687b ldr r3, [r7, #4] + 800b602: 681b ldr r3, [r3, #0] + 800b604: 1c5a adds r2, r3, #1 + 800b606: 687b ldr r3, [r7, #4] + 800b608: 601a str r2, [r3, #0] +} + 800b60a: bf00 nop + 800b60c: 3714 adds r7, #20 + 800b60e: 46bd mov sp, r7 + 800b610: f85d 7b04 ldr.w r7, [sp], #4 + 800b614: 4770 bx lr + +0800b616 : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800b616: b480 push {r7} + 800b618: b085 sub sp, #20 + 800b61a: af00 add r7, sp, #0 + 800b61c: 6078 str r0, [r7, #4] + 800b61e: 6039 str r1, [r7, #0] +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 800b620: 683b ldr r3, [r7, #0] + 800b622: 681b ldr r3, [r3, #0] + 800b624: 60bb str r3, [r7, #8] + new list item should be placed after it. This ensures that TCBs which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 800b626: 68bb ldr r3, [r7, #8] + 800b628: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b62c: d103 bne.n 800b636 + { + pxIterator = pxList->xListEnd.pxPrevious; + 800b62e: 687b ldr r3, [r7, #4] + 800b630: 691b ldr r3, [r3, #16] + 800b632: 60fb str r3, [r7, #12] + 800b634: e00c b.n 800b650 + 4) Using a queue or semaphore before it has been initialised or + before the scheduler has been started (are interrupts firing + before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + 800b636: 687b ldr r3, [r7, #4] + 800b638: 3308 adds r3, #8 + 800b63a: 60fb str r3, [r7, #12] + 800b63c: e002 b.n 800b644 + 800b63e: 68fb ldr r3, [r7, #12] + 800b640: 685b ldr r3, [r3, #4] + 800b642: 60fb str r3, [r7, #12] + 800b644: 68fb ldr r3, [r7, #12] + 800b646: 685b ldr r3, [r3, #4] + 800b648: 681b ldr r3, [r3, #0] + 800b64a: 68ba ldr r2, [r7, #8] + 800b64c: 429a cmp r2, r3 + 800b64e: d2f6 bcs.n 800b63e + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 800b650: 68fb ldr r3, [r7, #12] + 800b652: 685a ldr r2, [r3, #4] + 800b654: 683b ldr r3, [r7, #0] + 800b656: 605a str r2, [r3, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 800b658: 683b ldr r3, [r7, #0] + 800b65a: 685b ldr r3, [r3, #4] + 800b65c: 683a ldr r2, [r7, #0] + 800b65e: 609a str r2, [r3, #8] + pxNewListItem->pxPrevious = pxIterator; + 800b660: 683b ldr r3, [r7, #0] + 800b662: 68fa ldr r2, [r7, #12] + 800b664: 609a str r2, [r3, #8] + pxIterator->pxNext = pxNewListItem; + 800b666: 68fb ldr r3, [r7, #12] + 800b668: 683a ldr r2, [r7, #0] + 800b66a: 605a str r2, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pxContainer = pxList; + 800b66c: 683b ldr r3, [r7, #0] + 800b66e: 687a ldr r2, [r7, #4] + 800b670: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 800b672: 687b ldr r3, [r7, #4] + 800b674: 681b ldr r3, [r3, #0] + 800b676: 1c5a adds r2, r3, #1 + 800b678: 687b ldr r3, [r7, #4] + 800b67a: 601a str r2, [r3, #0] +} + 800b67c: bf00 nop + 800b67e: 3714 adds r7, #20 + 800b680: 46bd mov sp, r7 + 800b682: f85d 7b04 ldr.w r7, [sp], #4 + 800b686: 4770 bx lr + +0800b688 : +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + 800b688: b480 push {r7} + 800b68a: b085 sub sp, #20 + 800b68c: af00 add r7, sp, #0 + 800b68e: 6078 str r0, [r7, #4] +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = pxItemToRemove->pxContainer; + 800b690: 687b ldr r3, [r7, #4] + 800b692: 691b ldr r3, [r3, #16] + 800b694: 60fb str r3, [r7, #12] + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 800b696: 687b ldr r3, [r7, #4] + 800b698: 685b ldr r3, [r3, #4] + 800b69a: 687a ldr r2, [r7, #4] + 800b69c: 6892 ldr r2, [r2, #8] + 800b69e: 609a str r2, [r3, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 800b6a0: 687b ldr r3, [r7, #4] + 800b6a2: 689b ldr r3, [r3, #8] + 800b6a4: 687a ldr r2, [r7, #4] + 800b6a6: 6852 ldr r2, [r2, #4] + 800b6a8: 605a str r2, [r3, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 800b6aa: 68fb ldr r3, [r7, #12] + 800b6ac: 685b ldr r3, [r3, #4] + 800b6ae: 687a ldr r2, [r7, #4] + 800b6b0: 429a cmp r2, r3 + 800b6b2: d103 bne.n 800b6bc + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 800b6b4: 687b ldr r3, [r7, #4] + 800b6b6: 689a ldr r2, [r3, #8] + 800b6b8: 68fb ldr r3, [r7, #12] + 800b6ba: 605a str r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + 800b6bc: 687b ldr r3, [r7, #4] + 800b6be: 2200 movs r2, #0 + 800b6c0: 611a str r2, [r3, #16] + ( pxList->uxNumberOfItems )--; + 800b6c2: 68fb ldr r3, [r7, #12] + 800b6c4: 681b ldr r3, [r3, #0] + 800b6c6: 1e5a subs r2, r3, #1 + 800b6c8: 68fb ldr r3, [r7, #12] + 800b6ca: 601a str r2, [r3, #0] + + return pxList->uxNumberOfItems; + 800b6cc: 68fb ldr r3, [r7, #12] + 800b6ce: 681b ldr r3, [r3, #0] +} + 800b6d0: 4618 mov r0, r3 + 800b6d2: 3714 adds r7, #20 + 800b6d4: 46bd mov sp, r7 + 800b6d6: f85d 7b04 ldr.w r7, [sp], #4 + 800b6da: 4770 bx lr + +0800b6dc : + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) +{ + 800b6dc: b580 push {r7, lr} + 800b6de: b084 sub sp, #16 + 800b6e0: af00 add r7, sp, #0 + 800b6e2: 6078 str r0, [r7, #4] + 800b6e4: 6039 str r1, [r7, #0] +Queue_t * const pxQueue = xQueue; + 800b6e6: 687b ldr r3, [r7, #4] + 800b6e8: 60fb str r3, [r7, #12] + + configASSERT( pxQueue ); + 800b6ea: 68fb ldr r3, [r7, #12] + 800b6ec: 2b00 cmp r3, #0 + 800b6ee: d10c bne.n 800b70a + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ +uint32_t ulNewBASEPRI; + + __asm volatile + 800b6f0: f04f 0350 mov.w r3, #80 ; 0x50 + 800b6f4: b672 cpsid i + 800b6f6: f383 8811 msr BASEPRI, r3 + 800b6fa: f3bf 8f6f isb sy + 800b6fe: f3bf 8f4f dsb sy + 800b702: b662 cpsie i + 800b704: 60bb str r3, [r7, #8] + " isb \n" \ + " dsb \n" \ + " cpsie i \n" \ + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + 800b706: bf00 nop + 800b708: e7fe b.n 800b708 + + taskENTER_CRITICAL(); + 800b70a: f002 f8df bl 800d8cc + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 800b70e: 68fb ldr r3, [r7, #12] + 800b710: 681a ldr r2, [r3, #0] + 800b712: 68fb ldr r3, [r7, #12] + 800b714: 6bdb ldr r3, [r3, #60] ; 0x3c + 800b716: 68f9 ldr r1, [r7, #12] + 800b718: 6c09 ldr r1, [r1, #64] ; 0x40 + 800b71a: fb01 f303 mul.w r3, r1, r3 + 800b71e: 441a add r2, r3 + 800b720: 68fb ldr r3, [r7, #12] + 800b722: 609a str r2, [r3, #8] + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + 800b724: 68fb ldr r3, [r7, #12] + 800b726: 2200 movs r2, #0 + 800b728: 639a str r2, [r3, #56] ; 0x38 + pxQueue->pcWriteTo = pxQueue->pcHead; + 800b72a: 68fb ldr r3, [r7, #12] + 800b72c: 681a ldr r2, [r3, #0] + 800b72e: 68fb ldr r3, [r7, #12] + 800b730: 605a str r2, [r3, #4] + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 800b732: 68fb ldr r3, [r7, #12] + 800b734: 681a ldr r2, [r3, #0] + 800b736: 68fb ldr r3, [r7, #12] + 800b738: 6bdb ldr r3, [r3, #60] ; 0x3c + 800b73a: 3b01 subs r3, #1 + 800b73c: 68f9 ldr r1, [r7, #12] + 800b73e: 6c09 ldr r1, [r1, #64] ; 0x40 + 800b740: fb01 f303 mul.w r3, r1, r3 + 800b744: 441a add r2, r3 + 800b746: 68fb ldr r3, [r7, #12] + 800b748: 60da str r2, [r3, #12] + pxQueue->cRxLock = queueUNLOCKED; + 800b74a: 68fb ldr r3, [r7, #12] + 800b74c: 22ff movs r2, #255 ; 0xff + 800b74e: f883 2044 strb.w r2, [r3, #68] ; 0x44 + pxQueue->cTxLock = queueUNLOCKED; + 800b752: 68fb ldr r3, [r7, #12] + 800b754: 22ff movs r2, #255 ; 0xff + 800b756: f883 2045 strb.w r2, [r3, #69] ; 0x45 + + if( xNewQueue == pdFALSE ) + 800b75a: 683b ldr r3, [r7, #0] + 800b75c: 2b00 cmp r3, #0 + 800b75e: d114 bne.n 800b78a + /* If there are tasks blocked waiting to read from the queue, then + the tasks will remain blocked as after this function exits the queue + will still be empty. If there are tasks blocked waiting to write to + the queue, then one should be unblocked as after this function exits + it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800b760: 68fb ldr r3, [r7, #12] + 800b762: 691b ldr r3, [r3, #16] + 800b764: 2b00 cmp r3, #0 + 800b766: d01a beq.n 800b79e + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800b768: 68fb ldr r3, [r7, #12] + 800b76a: 3310 adds r3, #16 + 800b76c: 4618 mov r0, r3 + 800b76e: f001 fb9b bl 800cea8 + 800b772: 4603 mov r3, r0 + 800b774: 2b00 cmp r3, #0 + 800b776: d012 beq.n 800b79e + { + queueYIELD_IF_USING_PREEMPTION(); + 800b778: 4b0c ldr r3, [pc, #48] ; (800b7ac ) + 800b77a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b77e: 601a str r2, [r3, #0] + 800b780: f3bf 8f4f dsb sy + 800b784: f3bf 8f6f isb sy + 800b788: e009 b.n 800b79e + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + 800b78a: 68fb ldr r3, [r7, #12] + 800b78c: 3310 adds r3, #16 + 800b78e: 4618 mov r0, r3 + 800b790: f7ff fef0 bl 800b574 + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + 800b794: 68fb ldr r3, [r7, #12] + 800b796: 3324 adds r3, #36 ; 0x24 + 800b798: 4618 mov r0, r3 + 800b79a: f7ff feeb bl 800b574 + } + } + taskEXIT_CRITICAL(); + 800b79e: f002 f8c9 bl 800d934 + + /* A value is returned for calling semantic consistency with previous + versions. */ + return pdPASS; + 800b7a2: 2301 movs r3, #1 +} + 800b7a4: 4618 mov r0, r3 + 800b7a6: 3710 adds r7, #16 + 800b7a8: 46bd mov sp, r7 + 800b7aa: bd80 pop {r7, pc} + 800b7ac: e000ed04 .word 0xe000ed04 + +0800b7b0 : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) + { + 800b7b0: b580 push {r7, lr} + 800b7b2: b08e sub sp, #56 ; 0x38 + 800b7b4: af02 add r7, sp, #8 + 800b7b6: 60f8 str r0, [r7, #12] + 800b7b8: 60b9 str r1, [r7, #8] + 800b7ba: 607a str r2, [r7, #4] + 800b7bc: 603b str r3, [r7, #0] + Queue_t *pxNewQueue; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 800b7be: 68fb ldr r3, [r7, #12] + 800b7c0: 2b00 cmp r3, #0 + 800b7c2: d10c bne.n 800b7de + __asm volatile + 800b7c4: f04f 0350 mov.w r3, #80 ; 0x50 + 800b7c8: b672 cpsid i + 800b7ca: f383 8811 msr BASEPRI, r3 + 800b7ce: f3bf 8f6f isb sy + 800b7d2: f3bf 8f4f dsb sy + 800b7d6: b662 cpsie i + 800b7d8: 62bb str r3, [r7, #40] ; 0x28 +} + 800b7da: bf00 nop + 800b7dc: e7fe b.n 800b7dc + + /* The StaticQueue_t structure and the queue storage area must be + supplied. */ + configASSERT( pxStaticQueue != NULL ); + 800b7de: 683b ldr r3, [r7, #0] + 800b7e0: 2b00 cmp r3, #0 + 800b7e2: d10c bne.n 800b7fe + __asm volatile + 800b7e4: f04f 0350 mov.w r3, #80 ; 0x50 + 800b7e8: b672 cpsid i + 800b7ea: f383 8811 msr BASEPRI, r3 + 800b7ee: f3bf 8f6f isb sy + 800b7f2: f3bf 8f4f dsb sy + 800b7f6: b662 cpsie i + 800b7f8: 627b str r3, [r7, #36] ; 0x24 +} + 800b7fa: bf00 nop + 800b7fc: e7fe b.n 800b7fc + + /* A queue storage area should be provided if the item size is not 0, and + should not be provided if the item size is 0. */ + configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); + 800b7fe: 687b ldr r3, [r7, #4] + 800b800: 2b00 cmp r3, #0 + 800b802: d002 beq.n 800b80a + 800b804: 68bb ldr r3, [r7, #8] + 800b806: 2b00 cmp r3, #0 + 800b808: d001 beq.n 800b80e + 800b80a: 2301 movs r3, #1 + 800b80c: e000 b.n 800b810 + 800b80e: 2300 movs r3, #0 + 800b810: 2b00 cmp r3, #0 + 800b812: d10c bne.n 800b82e + __asm volatile + 800b814: f04f 0350 mov.w r3, #80 ; 0x50 + 800b818: b672 cpsid i + 800b81a: f383 8811 msr BASEPRI, r3 + 800b81e: f3bf 8f6f isb sy + 800b822: f3bf 8f4f dsb sy + 800b826: b662 cpsie i + 800b828: 623b str r3, [r7, #32] +} + 800b82a: bf00 nop + 800b82c: e7fe b.n 800b82c + configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); + 800b82e: 687b ldr r3, [r7, #4] + 800b830: 2b00 cmp r3, #0 + 800b832: d102 bne.n 800b83a + 800b834: 68bb ldr r3, [r7, #8] + 800b836: 2b00 cmp r3, #0 + 800b838: d101 bne.n 800b83e + 800b83a: 2301 movs r3, #1 + 800b83c: e000 b.n 800b840 + 800b83e: 2300 movs r3, #0 + 800b840: 2b00 cmp r3, #0 + 800b842: d10c bne.n 800b85e + __asm volatile + 800b844: f04f 0350 mov.w r3, #80 ; 0x50 + 800b848: b672 cpsid i + 800b84a: f383 8811 msr BASEPRI, r3 + 800b84e: f3bf 8f6f isb sy + 800b852: f3bf 8f4f dsb sy + 800b856: b662 cpsie i + 800b858: 61fb str r3, [r7, #28] +} + 800b85a: bf00 nop + 800b85c: e7fe b.n 800b85c + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticQueue_t or StaticSemaphore_t equals the size of + the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + 800b85e: 2348 movs r3, #72 ; 0x48 + 800b860: 617b str r3, [r7, #20] + configASSERT( xSize == sizeof( Queue_t ) ); + 800b862: 697b ldr r3, [r7, #20] + 800b864: 2b48 cmp r3, #72 ; 0x48 + 800b866: d00c beq.n 800b882 + __asm volatile + 800b868: f04f 0350 mov.w r3, #80 ; 0x50 + 800b86c: b672 cpsid i + 800b86e: f383 8811 msr BASEPRI, r3 + 800b872: f3bf 8f6f isb sy + 800b876: f3bf 8f4f dsb sy + 800b87a: b662 cpsie i + 800b87c: 61bb str r3, [r7, #24] +} + 800b87e: bf00 nop + 800b880: e7fe b.n 800b880 + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + 800b882: 697b ldr r3, [r7, #20] + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + The address of a statically allocated storage area was also passed in + but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 800b884: 683b ldr r3, [r7, #0] + 800b886: 62fb str r3, [r7, #44] ; 0x2c + + if( pxNewQueue != NULL ) + 800b888: 6afb ldr r3, [r7, #44] ; 0x2c + 800b88a: 2b00 cmp r3, #0 + 800b88c: d00d beq.n 800b8aa + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + note this queue was allocated statically in case the queue is + later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + 800b88e: 6afb ldr r3, [r7, #44] ; 0x2c + 800b890: 2201 movs r2, #1 + 800b892: f883 2046 strb.w r2, [r3, #70] ; 0x46 + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 800b896: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 + 800b89a: 6afb ldr r3, [r7, #44] ; 0x2c + 800b89c: 9300 str r3, [sp, #0] + 800b89e: 4613 mov r3, r2 + 800b8a0: 687a ldr r2, [r7, #4] + 800b8a2: 68b9 ldr r1, [r7, #8] + 800b8a4: 68f8 ldr r0, [r7, #12] + 800b8a6: f000 f847 bl 800b938 + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 800b8aa: 6afb ldr r3, [r7, #44] ; 0x2c + } + 800b8ac: 4618 mov r0, r3 + 800b8ae: 3730 adds r7, #48 ; 0x30 + 800b8b0: 46bd mov sp, r7 + 800b8b2: bd80 pop {r7, pc} + +0800b8b4 : +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) + { + 800b8b4: b580 push {r7, lr} + 800b8b6: b08a sub sp, #40 ; 0x28 + 800b8b8: af02 add r7, sp, #8 + 800b8ba: 60f8 str r0, [r7, #12] + 800b8bc: 60b9 str r1, [r7, #8] + 800b8be: 4613 mov r3, r2 + 800b8c0: 71fb strb r3, [r7, #7] + Queue_t *pxNewQueue; + size_t xQueueSizeInBytes; + uint8_t *pucQueueStorage; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 800b8c2: 68fb ldr r3, [r7, #12] + 800b8c4: 2b00 cmp r3, #0 + 800b8c6: d10c bne.n 800b8e2 + __asm volatile + 800b8c8: f04f 0350 mov.w r3, #80 ; 0x50 + 800b8cc: b672 cpsid i + 800b8ce: f383 8811 msr BASEPRI, r3 + 800b8d2: f3bf 8f6f isb sy + 800b8d6: f3bf 8f4f dsb sy + 800b8da: b662 cpsie i + 800b8dc: 613b str r3, [r7, #16] +} + 800b8de: bf00 nop + 800b8e0: e7fe b.n 800b8e0 + + if( uxItemSize == ( UBaseType_t ) 0 ) + 800b8e2: 68bb ldr r3, [r7, #8] + 800b8e4: 2b00 cmp r3, #0 + 800b8e6: d102 bne.n 800b8ee + { + /* There is not going to be a queue storage area. */ + xQueueSizeInBytes = ( size_t ) 0; + 800b8e8: 2300 movs r3, #0 + 800b8ea: 61fb str r3, [r7, #28] + 800b8ec: e004 b.n 800b8f8 + } + else + { + /* Allocate enough space to hold the maximum number of items that + can be in the queue at any time. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800b8ee: 68fb ldr r3, [r7, #12] + 800b8f0: 68ba ldr r2, [r7, #8] + 800b8f2: fb02 f303 mul.w r3, r2, r3 + 800b8f6: 61fb str r3, [r7, #28] + alignment requirements of the Queue_t structure - which in this case + is an int8_t *. Therefore, whenever the stack alignment requirements + are greater than or equal to the pointer to char requirements the cast + is safe. In other cases alignment requirements are not strict (one or + two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + 800b8f8: 69fb ldr r3, [r7, #28] + 800b8fa: 3348 adds r3, #72 ; 0x48 + 800b8fc: 4618 mov r0, r3 + 800b8fe: f002 f911 bl 800db24 + 800b902: 61b8 str r0, [r7, #24] + + if( pxNewQueue != NULL ) + 800b904: 69bb ldr r3, [r7, #24] + 800b906: 2b00 cmp r3, #0 + 800b908: d011 beq.n 800b92e + { + /* Jump past the queue structure to find the location of the queue + storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + 800b90a: 69bb ldr r3, [r7, #24] + 800b90c: 617b str r3, [r7, #20] + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + 800b90e: 697b ldr r3, [r7, #20] + 800b910: 3348 adds r3, #72 ; 0x48 + 800b912: 617b str r3, [r7, #20] + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + note this task was created dynamically in case it is later + deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + 800b914: 69bb ldr r3, [r7, #24] + 800b916: 2200 movs r2, #0 + 800b918: f883 2046 strb.w r2, [r3, #70] ; 0x46 + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + 800b91c: 79fa ldrb r2, [r7, #7] + 800b91e: 69bb ldr r3, [r7, #24] + 800b920: 9300 str r3, [sp, #0] + 800b922: 4613 mov r3, r2 + 800b924: 697a ldr r2, [r7, #20] + 800b926: 68b9 ldr r1, [r7, #8] + 800b928: 68f8 ldr r0, [r7, #12] + 800b92a: f000 f805 bl 800b938 + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + 800b92e: 69bb ldr r3, [r7, #24] + } + 800b930: 4618 mov r0, r3 + 800b932: 3720 adds r7, #32 + 800b934: 46bd mov sp, r7 + 800b936: bd80 pop {r7, pc} + +0800b938 : + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) +{ + 800b938: b580 push {r7, lr} + 800b93a: b084 sub sp, #16 + 800b93c: af00 add r7, sp, #0 + 800b93e: 60f8 str r0, [r7, #12] + 800b940: 60b9 str r1, [r7, #8] + 800b942: 607a str r2, [r7, #4] + 800b944: 70fb strb r3, [r7, #3] + /* Remove compiler warnings about unused parameters should + configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + 800b946: 68bb ldr r3, [r7, #8] + 800b948: 2b00 cmp r3, #0 + 800b94a: d103 bne.n 800b954 + { + /* No RAM was allocated for the queue storage area, but PC head cannot + be set to NULL because NULL is used as a key to say the queue is used as + a mutex. Therefore just set pcHead to point to the queue as a benign + value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + 800b94c: 69bb ldr r3, [r7, #24] + 800b94e: 69ba ldr r2, [r7, #24] + 800b950: 601a str r2, [r3, #0] + 800b952: e002 b.n 800b95a + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + 800b954: 69bb ldr r3, [r7, #24] + 800b956: 687a ldr r2, [r7, #4] + 800b958: 601a str r2, [r3, #0] + } + + /* Initialise the queue members as described where the queue type is + defined. */ + pxNewQueue->uxLength = uxQueueLength; + 800b95a: 69bb ldr r3, [r7, #24] + 800b95c: 68fa ldr r2, [r7, #12] + 800b95e: 63da str r2, [r3, #60] ; 0x3c + pxNewQueue->uxItemSize = uxItemSize; + 800b960: 69bb ldr r3, [r7, #24] + 800b962: 68ba ldr r2, [r7, #8] + 800b964: 641a str r2, [r3, #64] ; 0x40 + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + 800b966: 2101 movs r1, #1 + 800b968: 69b8 ldr r0, [r7, #24] + 800b96a: f7ff feb7 bl 800b6dc + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} + 800b96e: bf00 nop + 800b970: 3710 adds r7, #16 + 800b972: 46bd mov sp, r7 + 800b974: bd80 pop {r7, pc} + +0800b976 : +/*-----------------------------------------------------------*/ + +#if( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t *pxNewQueue ) + { + 800b976: b580 push {r7, lr} + 800b978: b082 sub sp, #8 + 800b97a: af00 add r7, sp, #0 + 800b97c: 6078 str r0, [r7, #4] + if( pxNewQueue != NULL ) + 800b97e: 687b ldr r3, [r7, #4] + 800b980: 2b00 cmp r3, #0 + 800b982: d00e beq.n 800b9a2 + { + /* The queue create function will set all the queue structure members + correctly for a generic queue, but this function is creating a + mutex. Overwrite those members that need to be set differently - + in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + 800b984: 687b ldr r3, [r7, #4] + 800b986: 2200 movs r2, #0 + 800b988: 609a str r2, [r3, #8] + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + 800b98a: 687b ldr r3, [r7, #4] + 800b98c: 2200 movs r2, #0 + 800b98e: 601a str r2, [r3, #0] + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + 800b990: 687b ldr r3, [r7, #4] + 800b992: 2200 movs r2, #0 + 800b994: 60da str r2, [r3, #12] + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + 800b996: 2300 movs r3, #0 + 800b998: 2200 movs r2, #0 + 800b99a: 2100 movs r1, #0 + 800b99c: 6878 ldr r0, [r7, #4] + 800b99e: f000 f837 bl 800ba10 + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + 800b9a2: bf00 nop + 800b9a4: 3708 adds r7, #8 + 800b9a6: 46bd mov sp, r7 + 800b9a8: bd80 pop {r7, pc} + +0800b9aa : +/*-----------------------------------------------------------*/ + +#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + 800b9aa: b580 push {r7, lr} + 800b9ac: b086 sub sp, #24 + 800b9ae: af00 add r7, sp, #0 + 800b9b0: 4603 mov r3, r0 + 800b9b2: 71fb strb r3, [r7, #7] + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + 800b9b4: 2301 movs r3, #1 + 800b9b6: 617b str r3, [r7, #20] + 800b9b8: 2300 movs r3, #0 + 800b9ba: 613b str r3, [r7, #16] + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + 800b9bc: 79fb ldrb r3, [r7, #7] + 800b9be: 461a mov r2, r3 + 800b9c0: 6939 ldr r1, [r7, #16] + 800b9c2: 6978 ldr r0, [r7, #20] + 800b9c4: f7ff ff76 bl 800b8b4 + 800b9c8: 60f8 str r0, [r7, #12] + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + 800b9ca: 68f8 ldr r0, [r7, #12] + 800b9cc: f7ff ffd3 bl 800b976 + + return xNewQueue; + 800b9d0: 68fb ldr r3, [r7, #12] + } + 800b9d2: 4618 mov r0, r3 + 800b9d4: 3718 adds r7, #24 + 800b9d6: 46bd mov sp, r7 + 800b9d8: bd80 pop {r7, pc} + +0800b9da : +/*-----------------------------------------------------------*/ + +#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) + { + 800b9da: b580 push {r7, lr} + 800b9dc: b088 sub sp, #32 + 800b9de: af02 add r7, sp, #8 + 800b9e0: 4603 mov r3, r0 + 800b9e2: 6039 str r1, [r7, #0] + 800b9e4: 71fb strb r3, [r7, #7] + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + 800b9e6: 2301 movs r3, #1 + 800b9e8: 617b str r3, [r7, #20] + 800b9ea: 2300 movs r3, #0 + 800b9ec: 613b str r3, [r7, #16] + + /* Prevent compiler warnings about unused parameters if + configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + 800b9ee: 79fb ldrb r3, [r7, #7] + 800b9f0: 9300 str r3, [sp, #0] + 800b9f2: 683b ldr r3, [r7, #0] + 800b9f4: 2200 movs r2, #0 + 800b9f6: 6939 ldr r1, [r7, #16] + 800b9f8: 6978 ldr r0, [r7, #20] + 800b9fa: f7ff fed9 bl 800b7b0 + 800b9fe: 60f8 str r0, [r7, #12] + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + 800ba00: 68f8 ldr r0, [r7, #12] + 800ba02: f7ff ffb8 bl 800b976 + + return xNewQueue; + 800ba06: 68fb ldr r3, [r7, #12] + } + 800ba08: 4618 mov r0, r3 + 800ba0a: 3718 adds r7, #24 + 800ba0c: 46bd mov sp, r7 + 800ba0e: bd80 pop {r7, pc} + +0800ba10 : + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) +{ + 800ba10: b580 push {r7, lr} + 800ba12: b08e sub sp, #56 ; 0x38 + 800ba14: af00 add r7, sp, #0 + 800ba16: 60f8 str r0, [r7, #12] + 800ba18: 60b9 str r1, [r7, #8] + 800ba1a: 607a str r2, [r7, #4] + 800ba1c: 603b str r3, [r7, #0] +BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + 800ba1e: 2300 movs r3, #0 + 800ba20: 637b str r3, [r7, #52] ; 0x34 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 800ba22: 68fb ldr r3, [r7, #12] + 800ba24: 633b str r3, [r7, #48] ; 0x30 + + configASSERT( pxQueue ); + 800ba26: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ba28: 2b00 cmp r3, #0 + 800ba2a: d10c bne.n 800ba46 + __asm volatile + 800ba2c: f04f 0350 mov.w r3, #80 ; 0x50 + 800ba30: b672 cpsid i + 800ba32: f383 8811 msr BASEPRI, r3 + 800ba36: f3bf 8f6f isb sy + 800ba3a: f3bf 8f4f dsb sy + 800ba3e: b662 cpsie i + 800ba40: 62bb str r3, [r7, #40] ; 0x28 +} + 800ba42: bf00 nop + 800ba44: e7fe b.n 800ba44 + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800ba46: 68bb ldr r3, [r7, #8] + 800ba48: 2b00 cmp r3, #0 + 800ba4a: d103 bne.n 800ba54 + 800ba4c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ba4e: 6c1b ldr r3, [r3, #64] ; 0x40 + 800ba50: 2b00 cmp r3, #0 + 800ba52: d101 bne.n 800ba58 + 800ba54: 2301 movs r3, #1 + 800ba56: e000 b.n 800ba5a + 800ba58: 2300 movs r3, #0 + 800ba5a: 2b00 cmp r3, #0 + 800ba5c: d10c bne.n 800ba78 + __asm volatile + 800ba5e: f04f 0350 mov.w r3, #80 ; 0x50 + 800ba62: b672 cpsid i + 800ba64: f383 8811 msr BASEPRI, r3 + 800ba68: f3bf 8f6f isb sy + 800ba6c: f3bf 8f4f dsb sy + 800ba70: b662 cpsie i + 800ba72: 627b str r3, [r7, #36] ; 0x24 +} + 800ba74: bf00 nop + 800ba76: e7fe b.n 800ba76 + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 800ba78: 683b ldr r3, [r7, #0] + 800ba7a: 2b02 cmp r3, #2 + 800ba7c: d103 bne.n 800ba86 + 800ba7e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ba80: 6bdb ldr r3, [r3, #60] ; 0x3c + 800ba82: 2b01 cmp r3, #1 + 800ba84: d101 bne.n 800ba8a + 800ba86: 2301 movs r3, #1 + 800ba88: e000 b.n 800ba8c + 800ba8a: 2300 movs r3, #0 + 800ba8c: 2b00 cmp r3, #0 + 800ba8e: d10c bne.n 800baaa + __asm volatile + 800ba90: f04f 0350 mov.w r3, #80 ; 0x50 + 800ba94: b672 cpsid i + 800ba96: f383 8811 msr BASEPRI, r3 + 800ba9a: f3bf 8f6f isb sy + 800ba9e: f3bf 8f4f dsb sy + 800baa2: b662 cpsie i + 800baa4: 623b str r3, [r7, #32] +} + 800baa6: bf00 nop + 800baa8: e7fe b.n 800baa8 + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 800baaa: f001 fbc5 bl 800d238 + 800baae: 4603 mov r3, r0 + 800bab0: 2b00 cmp r3, #0 + 800bab2: d102 bne.n 800baba + 800bab4: 687b ldr r3, [r7, #4] + 800bab6: 2b00 cmp r3, #0 + 800bab8: d101 bne.n 800babe + 800baba: 2301 movs r3, #1 + 800babc: e000 b.n 800bac0 + 800babe: 2300 movs r3, #0 + 800bac0: 2b00 cmp r3, #0 + 800bac2: d10c bne.n 800bade + __asm volatile + 800bac4: f04f 0350 mov.w r3, #80 ; 0x50 + 800bac8: b672 cpsid i + 800baca: f383 8811 msr BASEPRI, r3 + 800bace: f3bf 8f6f isb sy + 800bad2: f3bf 8f4f dsb sy + 800bad6: b662 cpsie i + 800bad8: 61fb str r3, [r7, #28] +} + 800bada: bf00 nop + 800badc: e7fe b.n 800badc + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 800bade: f001 fef5 bl 800d8cc + { + /* Is there room on the queue now? The running task must be the + highest priority task wanting to access the queue. If the head item + in the queue is to be overwritten then it does not matter if the + queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 800bae2: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bae4: 6b9a ldr r2, [r3, #56] ; 0x38 + 800bae6: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bae8: 6bdb ldr r3, [r3, #60] ; 0x3c + 800baea: 429a cmp r2, r3 + 800baec: d302 bcc.n 800baf4 + 800baee: 683b ldr r3, [r7, #0] + 800baf0: 2b02 cmp r3, #2 + 800baf2: d129 bne.n 800bb48 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 800baf4: 683a ldr r2, [r7, #0] + 800baf6: 68b9 ldr r1, [r7, #8] + 800baf8: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bafa: f000 fc5d bl 800c3b8 + 800bafe: 62f8 str r0, [r7, #44] ; 0x2c + + /* If there was a task waiting for data to arrive on the + queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800bb00: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb02: 6a5b ldr r3, [r3, #36] ; 0x24 + 800bb04: 2b00 cmp r3, #0 + 800bb06: d010 beq.n 800bb2a + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800bb08: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb0a: 3324 adds r3, #36 ; 0x24 + 800bb0c: 4618 mov r0, r3 + 800bb0e: f001 f9cb bl 800cea8 + 800bb12: 4603 mov r3, r0 + 800bb14: 2b00 cmp r3, #0 + 800bb16: d013 beq.n 800bb40 + { + /* The unblocked task has a priority higher than + our own so yield immediately. Yes it is ok to do + this from within the critical section - the kernel + takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + 800bb18: 4b3f ldr r3, [pc, #252] ; (800bc18 ) + 800bb1a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800bb1e: 601a str r2, [r3, #0] + 800bb20: f3bf 8f4f dsb sy + 800bb24: f3bf 8f6f isb sy + 800bb28: e00a b.n 800bb40 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + 800bb2a: 6afb ldr r3, [r7, #44] ; 0x2c + 800bb2c: 2b00 cmp r3, #0 + 800bb2e: d007 beq.n 800bb40 + { + /* This path is a special case that will only get + executed if the task was holding multiple mutexes and + the mutexes were given back in an order that is + different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + 800bb30: 4b39 ldr r3, [pc, #228] ; (800bc18 ) + 800bb32: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800bb36: 601a str r2, [r3, #0] + 800bb38: f3bf 8f4f dsb sy + 800bb3c: f3bf 8f6f isb sy + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + 800bb40: f001 fef8 bl 800d934 + return pdPASS; + 800bb44: 2301 movs r3, #1 + 800bb46: e063 b.n 800bc10 + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 800bb48: 687b ldr r3, [r7, #4] + 800bb4a: 2b00 cmp r3, #0 + 800bb4c: d103 bne.n 800bb56 + { + /* The queue was full and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 800bb4e: f001 fef1 bl 800d934 + + /* Return to the original privilege level before exiting + the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 800bb52: 2300 movs r3, #0 + 800bb54: e05c b.n 800bc10 + } + else if( xEntryTimeSet == pdFALSE ) + 800bb56: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bb58: 2b00 cmp r3, #0 + 800bb5a: d106 bne.n 800bb6a + { + /* The queue was full and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 800bb5c: f107 0314 add.w r3, r7, #20 + 800bb60: 4618 mov r0, r3 + 800bb62: f001 fa05 bl 800cf70 + xEntryTimeSet = pdTRUE; + 800bb66: 2301 movs r3, #1 + 800bb68: 637b str r3, [r7, #52] ; 0x34 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 800bb6a: f001 fee3 bl 800d934 + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 800bb6e: f000 ff89 bl 800ca84 + prvLockQueue( pxQueue ); + 800bb72: f001 feab bl 800d8cc + 800bb76: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb78: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 800bb7c: b25b sxtb r3, r3 + 800bb7e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800bb82: d103 bne.n 800bb8c + 800bb84: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb86: 2200 movs r2, #0 + 800bb88: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800bb8c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb8e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800bb92: b25b sxtb r3, r3 + 800bb94: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800bb98: d103 bne.n 800bba2 + 800bb9a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bb9c: 2200 movs r2, #0 + 800bb9e: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 800bba2: f001 fec7 bl 800d934 + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800bba6: 1d3a adds r2, r7, #4 + 800bba8: f107 0314 add.w r3, r7, #20 + 800bbac: 4611 mov r1, r2 + 800bbae: 4618 mov r0, r3 + 800bbb0: f001 f9f4 bl 800cf9c + 800bbb4: 4603 mov r3, r0 + 800bbb6: 2b00 cmp r3, #0 + 800bbb8: d124 bne.n 800bc04 + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + 800bbba: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bbbc: f000 fcf4 bl 800c5a8 + 800bbc0: 4603 mov r3, r0 + 800bbc2: 2b00 cmp r3, #0 + 800bbc4: d018 beq.n 800bbf8 + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + 800bbc6: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bbc8: 3310 adds r3, #16 + 800bbca: 687a ldr r2, [r7, #4] + 800bbcc: 4611 mov r1, r2 + 800bbce: 4618 mov r0, r3 + 800bbd0: f001 f944 bl 800ce5c + /* Unlocking the queue means queue events can effect the + event list. It is possible that interrupts occurring now + remove this task from the event list again - but as the + scheduler is suspended the task will go onto the pending + ready last instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + 800bbd4: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bbd6: f000 fc7f bl 800c4d8 + /* Resuming the scheduler will move tasks from the pending + ready list into the ready list - so it is feasible that this + task is already in a ready list before it yields - in which + case the yield will not cause a context switch unless there + is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + 800bbda: f000 ff61 bl 800caa0 + 800bbde: 4603 mov r3, r0 + 800bbe0: 2b00 cmp r3, #0 + 800bbe2: f47f af7c bne.w 800bade + { + portYIELD_WITHIN_API(); + 800bbe6: 4b0c ldr r3, [pc, #48] ; (800bc18 ) + 800bbe8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800bbec: 601a str r2, [r3, #0] + 800bbee: f3bf 8f4f dsb sy + 800bbf2: f3bf 8f6f isb sy + 800bbf6: e772 b.n 800bade + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + 800bbf8: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bbfa: f000 fc6d bl 800c4d8 + ( void ) xTaskResumeAll(); + 800bbfe: f000 ff4f bl 800caa0 + 800bc02: e76c b.n 800bade + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + 800bc04: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bc06: f000 fc67 bl 800c4d8 + ( void ) xTaskResumeAll(); + 800bc0a: f000 ff49 bl 800caa0 + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + 800bc0e: 2300 movs r3, #0 + } + } /*lint -restore */ +} + 800bc10: 4618 mov r0, r3 + 800bc12: 3738 adds r7, #56 ; 0x38 + 800bc14: 46bd mov sp, r7 + 800bc16: bd80 pop {r7, pc} + 800bc18: e000ed04 .word 0xe000ed04 + +0800bc1c : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) +{ + 800bc1c: b580 push {r7, lr} + 800bc1e: b08e sub sp, #56 ; 0x38 + 800bc20: af00 add r7, sp, #0 + 800bc22: 60f8 str r0, [r7, #12] + 800bc24: 60b9 str r1, [r7, #8] + 800bc26: 607a str r2, [r7, #4] + 800bc28: 603b str r3, [r7, #0] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 800bc2a: 68fb ldr r3, [r7, #12] + 800bc2c: 633b str r3, [r7, #48] ; 0x30 + + configASSERT( pxQueue ); + 800bc2e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bc30: 2b00 cmp r3, #0 + 800bc32: d10c bne.n 800bc4e + __asm volatile + 800bc34: f04f 0350 mov.w r3, #80 ; 0x50 + 800bc38: b672 cpsid i + 800bc3a: f383 8811 msr BASEPRI, r3 + 800bc3e: f3bf 8f6f isb sy + 800bc42: f3bf 8f4f dsb sy + 800bc46: b662 cpsie i + 800bc48: 627b str r3, [r7, #36] ; 0x24 +} + 800bc4a: bf00 nop + 800bc4c: e7fe b.n 800bc4c + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800bc4e: 68bb ldr r3, [r7, #8] + 800bc50: 2b00 cmp r3, #0 + 800bc52: d103 bne.n 800bc5c + 800bc54: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bc56: 6c1b ldr r3, [r3, #64] ; 0x40 + 800bc58: 2b00 cmp r3, #0 + 800bc5a: d101 bne.n 800bc60 + 800bc5c: 2301 movs r3, #1 + 800bc5e: e000 b.n 800bc62 + 800bc60: 2300 movs r3, #0 + 800bc62: 2b00 cmp r3, #0 + 800bc64: d10c bne.n 800bc80 + __asm volatile + 800bc66: f04f 0350 mov.w r3, #80 ; 0x50 + 800bc6a: b672 cpsid i + 800bc6c: f383 8811 msr BASEPRI, r3 + 800bc70: f3bf 8f6f isb sy + 800bc74: f3bf 8f4f dsb sy + 800bc78: b662 cpsie i + 800bc7a: 623b str r3, [r7, #32] +} + 800bc7c: bf00 nop + 800bc7e: e7fe b.n 800bc7e + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 800bc80: 683b ldr r3, [r7, #0] + 800bc82: 2b02 cmp r3, #2 + 800bc84: d103 bne.n 800bc8e + 800bc86: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bc88: 6bdb ldr r3, [r3, #60] ; 0x3c + 800bc8a: 2b01 cmp r3, #1 + 800bc8c: d101 bne.n 800bc92 + 800bc8e: 2301 movs r3, #1 + 800bc90: e000 b.n 800bc94 + 800bc92: 2300 movs r3, #0 + 800bc94: 2b00 cmp r3, #0 + 800bc96: d10c bne.n 800bcb2 + __asm volatile + 800bc98: f04f 0350 mov.w r3, #80 ; 0x50 + 800bc9c: b672 cpsid i + 800bc9e: f383 8811 msr BASEPRI, r3 + 800bca2: f3bf 8f6f isb sy + 800bca6: f3bf 8f4f dsb sy + 800bcaa: b662 cpsie i + 800bcac: 61fb str r3, [r7, #28] +} + 800bcae: bf00 nop + 800bcb0: e7fe b.n 800bcb0 + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 800bcb2: f001 fef3 bl 800da9c + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ +uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + 800bcb6: f3ef 8211 mrs r2, BASEPRI + 800bcba: f04f 0350 mov.w r3, #80 ; 0x50 + 800bcbe: b672 cpsid i + 800bcc0: f383 8811 msr BASEPRI, r3 + 800bcc4: f3bf 8f6f isb sy + 800bcc8: f3bf 8f4f dsb sy + 800bccc: b662 cpsie i + 800bcce: 61ba str r2, [r7, #24] + 800bcd0: 617b str r3, [r7, #20] + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + warnings. */ + return ulOriginalBASEPRI; + 800bcd2: 69bb ldr r3, [r7, #24] + /* Similar to xQueueGenericSend, except without blocking if there is no room + in the queue. Also don't directly wake a task that was blocked on a queue + read, instead return a flag to say whether a context switch is required or + not (i.e. has a task with a higher priority than us been woken by this + post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 800bcd4: 62fb str r3, [r7, #44] ; 0x2c + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 800bcd6: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bcd8: 6b9a ldr r2, [r3, #56] ; 0x38 + 800bcda: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bcdc: 6bdb ldr r3, [r3, #60] ; 0x3c + 800bcde: 429a cmp r2, r3 + 800bce0: d302 bcc.n 800bce8 + 800bce2: 683b ldr r3, [r7, #0] + 800bce4: 2b02 cmp r3, #2 + 800bce6: d12c bne.n 800bd42 + { + const int8_t cTxLock = pxQueue->cTxLock; + 800bce8: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bcea: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800bcee: f887 302b strb.w r3, [r7, #43] ; 0x2b + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + semaphore or mutex. That means prvCopyDataToQueue() cannot result + in a task disinheriting a priority and prvCopyDataToQueue() can be + called here even though the disinherit function does not check if + the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 800bcf2: 683a ldr r2, [r7, #0] + 800bcf4: 68b9 ldr r1, [r7, #8] + 800bcf6: 6b38 ldr r0, [r7, #48] ; 0x30 + 800bcf8: f000 fb5e bl 800c3b8 + + /* The event list is not altered if the queue is locked. This will + be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + 800bcfc: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b + 800bd00: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800bd04: d112 bne.n 800bd2c + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800bd06: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bd08: 6a5b ldr r3, [r3, #36] ; 0x24 + 800bd0a: 2b00 cmp r3, #0 + 800bd0c: d016 beq.n 800bd3c + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800bd0e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bd10: 3324 adds r3, #36 ; 0x24 + 800bd12: 4618 mov r0, r3 + 800bd14: f001 f8c8 bl 800cea8 + 800bd18: 4603 mov r3, r0 + 800bd1a: 2b00 cmp r3, #0 + 800bd1c: d00e beq.n 800bd3c + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + 800bd1e: 687b ldr r3, [r7, #4] + 800bd20: 2b00 cmp r3, #0 + 800bd22: d00b beq.n 800bd3c + { + *pxHigherPriorityTaskWoken = pdTRUE; + 800bd24: 687b ldr r3, [r7, #4] + 800bd26: 2201 movs r2, #1 + 800bd28: 601a str r2, [r3, #0] + 800bd2a: e007 b.n 800bd3c + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 800bd2c: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 800bd30: 3301 adds r3, #1 + 800bd32: b2db uxtb r3, r3 + 800bd34: b25a sxtb r2, r3 + 800bd36: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bd38: f883 2045 strb.w r2, [r3, #69] ; 0x45 + } + + xReturn = pdPASS; + 800bd3c: 2301 movs r3, #1 + 800bd3e: 637b str r3, [r7, #52] ; 0x34 + { + 800bd40: e001 b.n 800bd46 + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + 800bd42: 2300 movs r3, #0 + 800bd44: 637b str r3, [r7, #52] ; 0x34 + 800bd46: 6afb ldr r3, [r7, #44] ; 0x2c + 800bd48: 613b str r3, [r7, #16] +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + 800bd4a: 693b ldr r3, [r7, #16] + 800bd4c: f383 8811 msr BASEPRI, r3 + ( + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" + ); +} + 800bd50: bf00 nop + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800bd52: 6b7b ldr r3, [r7, #52] ; 0x34 +} + 800bd54: 4618 mov r0, r3 + 800bd56: 3738 adds r7, #56 ; 0x38 + 800bd58: 46bd mov sp, r7 + 800bd5a: bd80 pop {r7, pc} + +0800bd5c : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) +{ + 800bd5c: b580 push {r7, lr} + 800bd5e: b08e sub sp, #56 ; 0x38 + 800bd60: af00 add r7, sp, #0 + 800bd62: 6078 str r0, [r7, #4] + 800bd64: 6039 str r1, [r7, #0] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 800bd66: 687b ldr r3, [r7, #4] + 800bd68: 633b str r3, [r7, #48] ; 0x30 + item size is 0. Don't directly wake a task that was blocked on a queue + read, instead return a flag to say whether a context switch is required or + not (i.e. has a task with a higher priority than us been woken by this + post). */ + + configASSERT( pxQueue ); + 800bd6a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bd6c: 2b00 cmp r3, #0 + 800bd6e: d10c bne.n 800bd8a + __asm volatile + 800bd70: f04f 0350 mov.w r3, #80 ; 0x50 + 800bd74: b672 cpsid i + 800bd76: f383 8811 msr BASEPRI, r3 + 800bd7a: f3bf 8f6f isb sy + 800bd7e: f3bf 8f4f dsb sy + 800bd82: b662 cpsie i + 800bd84: 623b str r3, [r7, #32] +} + 800bd86: bf00 nop + 800bd88: e7fe b.n 800bd88 + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + 800bd8a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bd8c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800bd8e: 2b00 cmp r3, #0 + 800bd90: d00c beq.n 800bdac + __asm volatile + 800bd92: f04f 0350 mov.w r3, #80 ; 0x50 + 800bd96: b672 cpsid i + 800bd98: f383 8811 msr BASEPRI, r3 + 800bd9c: f3bf 8f6f isb sy + 800bda0: f3bf 8f4f dsb sy + 800bda4: b662 cpsie i + 800bda6: 61fb str r3, [r7, #28] +} + 800bda8: bf00 nop + 800bdaa: e7fe b.n 800bdaa + + /* Normally a mutex would not be given from an interrupt, especially if + there is a mutex holder, as priority inheritance makes no sense for an + interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + 800bdac: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bdae: 681b ldr r3, [r3, #0] + 800bdb0: 2b00 cmp r3, #0 + 800bdb2: d103 bne.n 800bdbc + 800bdb4: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bdb6: 689b ldr r3, [r3, #8] + 800bdb8: 2b00 cmp r3, #0 + 800bdba: d101 bne.n 800bdc0 + 800bdbc: 2301 movs r3, #1 + 800bdbe: e000 b.n 800bdc2 + 800bdc0: 2300 movs r3, #0 + 800bdc2: 2b00 cmp r3, #0 + 800bdc4: d10c bne.n 800bde0 + __asm volatile + 800bdc6: f04f 0350 mov.w r3, #80 ; 0x50 + 800bdca: b672 cpsid i + 800bdcc: f383 8811 msr BASEPRI, r3 + 800bdd0: f3bf 8f6f isb sy + 800bdd4: f3bf 8f4f dsb sy + 800bdd8: b662 cpsie i + 800bdda: 61bb str r3, [r7, #24] +} + 800bddc: bf00 nop + 800bdde: e7fe b.n 800bdde + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 800bde0: f001 fe5c bl 800da9c + __asm volatile + 800bde4: f3ef 8211 mrs r2, BASEPRI + 800bde8: f04f 0350 mov.w r3, #80 ; 0x50 + 800bdec: b672 cpsid i + 800bdee: f383 8811 msr BASEPRI, r3 + 800bdf2: f3bf 8f6f isb sy + 800bdf6: f3bf 8f4f dsb sy + 800bdfa: b662 cpsie i + 800bdfc: 617a str r2, [r7, #20] + 800bdfe: 613b str r3, [r7, #16] + return ulOriginalBASEPRI; + 800be00: 697b ldr r3, [r7, #20] + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 800be02: 62fb str r3, [r7, #44] ; 0x2c + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 800be04: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be06: 6b9b ldr r3, [r3, #56] ; 0x38 + 800be08: 62bb str r3, [r7, #40] ; 0x28 + + /* When the queue is used to implement a semaphore no data is ever + moved through the queue but it is still valid to see if the queue 'has + space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + 800be0a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be0c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800be0e: 6aba ldr r2, [r7, #40] ; 0x28 + 800be10: 429a cmp r2, r3 + 800be12: d22b bcs.n 800be6c + { + const int8_t cTxLock = pxQueue->cTxLock; + 800be14: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be16: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800be1a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + holder - and if there is a mutex holder then the mutex cannot be + given from an ISR. As this is the ISR version of the function it + can be assumed there is no mutex holder and no need to determine if + priority disinheritance is needed. Simply increase the count of + messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + 800be1e: 6abb ldr r3, [r7, #40] ; 0x28 + 800be20: 1c5a adds r2, r3, #1 + 800be22: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be24: 639a str r2, [r3, #56] ; 0x38 + + /* The event list is not altered if the queue is locked. This will + be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + 800be26: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 800be2a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800be2e: d112 bne.n 800be56 + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800be30: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be32: 6a5b ldr r3, [r3, #36] ; 0x24 + 800be34: 2b00 cmp r3, #0 + 800be36: d016 beq.n 800be66 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800be38: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be3a: 3324 adds r3, #36 ; 0x24 + 800be3c: 4618 mov r0, r3 + 800be3e: f001 f833 bl 800cea8 + 800be42: 4603 mov r3, r0 + 800be44: 2b00 cmp r3, #0 + 800be46: d00e beq.n 800be66 + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + 800be48: 683b ldr r3, [r7, #0] + 800be4a: 2b00 cmp r3, #0 + 800be4c: d00b beq.n 800be66 + { + *pxHigherPriorityTaskWoken = pdTRUE; + 800be4e: 683b ldr r3, [r7, #0] + 800be50: 2201 movs r2, #1 + 800be52: 601a str r2, [r3, #0] + 800be54: e007 b.n 800be66 + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 800be56: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800be5a: 3301 adds r3, #1 + 800be5c: b2db uxtb r3, r3 + 800be5e: b25a sxtb r2, r3 + 800be60: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be62: f883 2045 strb.w r2, [r3, #69] ; 0x45 + } + + xReturn = pdPASS; + 800be66: 2301 movs r3, #1 + 800be68: 637b str r3, [r7, #52] ; 0x34 + 800be6a: e001 b.n 800be70 + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + 800be6c: 2300 movs r3, #0 + 800be6e: 637b str r3, [r7, #52] ; 0x34 + 800be70: 6afb ldr r3, [r7, #44] ; 0x2c + 800be72: 60fb str r3, [r7, #12] + __asm volatile + 800be74: 68fb ldr r3, [r7, #12] + 800be76: f383 8811 msr BASEPRI, r3 +} + 800be7a: bf00 nop + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800be7c: 6b7b ldr r3, [r7, #52] ; 0x34 +} + 800be7e: 4618 mov r0, r3 + 800be80: 3738 adds r7, #56 ; 0x38 + 800be82: 46bd mov sp, r7 + 800be84: bd80 pop {r7, pc} + ... + +0800be88 : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) +{ + 800be88: b580 push {r7, lr} + 800be8a: b08c sub sp, #48 ; 0x30 + 800be8c: af00 add r7, sp, #0 + 800be8e: 60f8 str r0, [r7, #12] + 800be90: 60b9 str r1, [r7, #8] + 800be92: 607a str r2, [r7, #4] +BaseType_t xEntryTimeSet = pdFALSE; + 800be94: 2300 movs r3, #0 + 800be96: 62fb str r3, [r7, #44] ; 0x2c +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 800be98: 68fb ldr r3, [r7, #12] + 800be9a: 62bb str r3, [r7, #40] ; 0x28 + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + 800be9c: 6abb ldr r3, [r7, #40] ; 0x28 + 800be9e: 2b00 cmp r3, #0 + 800bea0: d10c bne.n 800bebc + __asm volatile + 800bea2: f04f 0350 mov.w r3, #80 ; 0x50 + 800bea6: b672 cpsid i + 800bea8: f383 8811 msr BASEPRI, r3 + 800beac: f3bf 8f6f isb sy + 800beb0: f3bf 8f4f dsb sy + 800beb4: b662 cpsie i + 800beb6: 623b str r3, [r7, #32] +} + 800beb8: bf00 nop + 800beba: e7fe b.n 800beba + + /* The buffer into which data is received can only be NULL if the data size + is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800bebc: 68bb ldr r3, [r7, #8] + 800bebe: 2b00 cmp r3, #0 + 800bec0: d103 bne.n 800beca + 800bec2: 6abb ldr r3, [r7, #40] ; 0x28 + 800bec4: 6c1b ldr r3, [r3, #64] ; 0x40 + 800bec6: 2b00 cmp r3, #0 + 800bec8: d101 bne.n 800bece + 800beca: 2301 movs r3, #1 + 800becc: e000 b.n 800bed0 + 800bece: 2300 movs r3, #0 + 800bed0: 2b00 cmp r3, #0 + 800bed2: d10c bne.n 800beee + __asm volatile + 800bed4: f04f 0350 mov.w r3, #80 ; 0x50 + 800bed8: b672 cpsid i + 800beda: f383 8811 msr BASEPRI, r3 + 800bede: f3bf 8f6f isb sy + 800bee2: f3bf 8f4f dsb sy + 800bee6: b662 cpsie i + 800bee8: 61fb str r3, [r7, #28] +} + 800beea: bf00 nop + 800beec: e7fe b.n 800beec + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 800beee: f001 f9a3 bl 800d238 + 800bef2: 4603 mov r3, r0 + 800bef4: 2b00 cmp r3, #0 + 800bef6: d102 bne.n 800befe + 800bef8: 687b ldr r3, [r7, #4] + 800befa: 2b00 cmp r3, #0 + 800befc: d101 bne.n 800bf02 + 800befe: 2301 movs r3, #1 + 800bf00: e000 b.n 800bf04 + 800bf02: 2300 movs r3, #0 + 800bf04: 2b00 cmp r3, #0 + 800bf06: d10c bne.n 800bf22 + __asm volatile + 800bf08: f04f 0350 mov.w r3, #80 ; 0x50 + 800bf0c: b672 cpsid i + 800bf0e: f383 8811 msr BASEPRI, r3 + 800bf12: f3bf 8f6f isb sy + 800bf16: f3bf 8f4f dsb sy + 800bf1a: b662 cpsie i + 800bf1c: 61bb str r3, [r7, #24] +} + 800bf1e: bf00 nop + 800bf20: e7fe b.n 800bf20 + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 800bf22: f001 fcd3 bl 800d8cc + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 800bf26: 6abb ldr r3, [r7, #40] ; 0x28 + 800bf28: 6b9b ldr r3, [r3, #56] ; 0x38 + 800bf2a: 627b str r3, [r7, #36] ; 0x24 + + /* Is there data in the queue now? To be running the calling task + must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 800bf2c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800bf2e: 2b00 cmp r3, #0 + 800bf30: d01f beq.n 800bf72 + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 800bf32: 68b9 ldr r1, [r7, #8] + 800bf34: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800bf36: f000 faa9 bl 800c48c + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + 800bf3a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800bf3c: 1e5a subs r2, r3, #1 + 800bf3e: 6abb ldr r3, [r7, #40] ; 0x28 + 800bf40: 639a str r2, [r3, #56] ; 0x38 + + /* There is now space in the queue, were any tasks waiting to + post to the queue? If so, unblock the highest priority waiting + task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800bf42: 6abb ldr r3, [r7, #40] ; 0x28 + 800bf44: 691b ldr r3, [r3, #16] + 800bf46: 2b00 cmp r3, #0 + 800bf48: d00f beq.n 800bf6a + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800bf4a: 6abb ldr r3, [r7, #40] ; 0x28 + 800bf4c: 3310 adds r3, #16 + 800bf4e: 4618 mov r0, r3 + 800bf50: f000 ffaa bl 800cea8 + 800bf54: 4603 mov r3, r0 + 800bf56: 2b00 cmp r3, #0 + 800bf58: d007 beq.n 800bf6a + { + queueYIELD_IF_USING_PREEMPTION(); + 800bf5a: 4b3d ldr r3, [pc, #244] ; (800c050 ) + 800bf5c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800bf60: 601a str r2, [r3, #0] + 800bf62: f3bf 8f4f dsb sy + 800bf66: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + 800bf6a: f001 fce3 bl 800d934 + return pdPASS; + 800bf6e: 2301 movs r3, #1 + 800bf70: e069 b.n 800c046 + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 800bf72: 687b ldr r3, [r7, #4] + 800bf74: 2b00 cmp r3, #0 + 800bf76: d103 bne.n 800bf80 + { + /* The queue was empty and no block time is specified (or + the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + 800bf78: f001 fcdc bl 800d934 + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800bf7c: 2300 movs r3, #0 + 800bf7e: e062 b.n 800c046 + } + else if( xEntryTimeSet == pdFALSE ) + 800bf80: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf82: 2b00 cmp r3, #0 + 800bf84: d106 bne.n 800bf94 + { + /* The queue was empty and a block time was specified so + configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 800bf86: f107 0310 add.w r3, r7, #16 + 800bf8a: 4618 mov r0, r3 + 800bf8c: f000 fff0 bl 800cf70 + xEntryTimeSet = pdTRUE; + 800bf90: 2301 movs r3, #1 + 800bf92: 62fb str r3, [r7, #44] ; 0x2c + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 800bf94: f001 fcce bl 800d934 + + /* Interrupts and other tasks can send to and receive from the queue + now the critical section has been exited. */ + + vTaskSuspendAll(); + 800bf98: f000 fd74 bl 800ca84 + prvLockQueue( pxQueue ); + 800bf9c: f001 fc96 bl 800d8cc + 800bfa0: 6abb ldr r3, [r7, #40] ; 0x28 + 800bfa2: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 800bfa6: b25b sxtb r3, r3 + 800bfa8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800bfac: d103 bne.n 800bfb6 + 800bfae: 6abb ldr r3, [r7, #40] ; 0x28 + 800bfb0: 2200 movs r2, #0 + 800bfb2: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800bfb6: 6abb ldr r3, [r7, #40] ; 0x28 + 800bfb8: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800bfbc: b25b sxtb r3, r3 + 800bfbe: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800bfc2: d103 bne.n 800bfcc + 800bfc4: 6abb ldr r3, [r7, #40] ; 0x28 + 800bfc6: 2200 movs r2, #0 + 800bfc8: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 800bfcc: f001 fcb2 bl 800d934 + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800bfd0: 1d3a adds r2, r7, #4 + 800bfd2: f107 0310 add.w r3, r7, #16 + 800bfd6: 4611 mov r1, r2 + 800bfd8: 4618 mov r0, r3 + 800bfda: f000 ffdf bl 800cf9c + 800bfde: 4603 mov r3, r0 + 800bfe0: 2b00 cmp r3, #0 + 800bfe2: d123 bne.n 800c02c + { + /* The timeout has not expired. If the queue is still empty place + the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800bfe4: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800bfe6: f000 fac9 bl 800c57c + 800bfea: 4603 mov r3, r0 + 800bfec: 2b00 cmp r3, #0 + 800bfee: d017 beq.n 800c020 + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 800bff0: 6abb ldr r3, [r7, #40] ; 0x28 + 800bff2: 3324 adds r3, #36 ; 0x24 + 800bff4: 687a ldr r2, [r7, #4] + 800bff6: 4611 mov r1, r2 + 800bff8: 4618 mov r0, r3 + 800bffa: f000 ff2f bl 800ce5c + prvUnlockQueue( pxQueue ); + 800bffe: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800c000: f000 fa6a bl 800c4d8 + if( xTaskResumeAll() == pdFALSE ) + 800c004: f000 fd4c bl 800caa0 + 800c008: 4603 mov r3, r0 + 800c00a: 2b00 cmp r3, #0 + 800c00c: d189 bne.n 800bf22 + { + portYIELD_WITHIN_API(); + 800c00e: 4b10 ldr r3, [pc, #64] ; (800c050 ) + 800c010: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800c014: 601a str r2, [r3, #0] + 800c016: f3bf 8f4f dsb sy + 800c01a: f3bf 8f6f isb sy + 800c01e: e780 b.n 800bf22 + } + else + { + /* The queue contains data again. Loop back to try and read the + data. */ + prvUnlockQueue( pxQueue ); + 800c020: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800c022: f000 fa59 bl 800c4d8 + ( void ) xTaskResumeAll(); + 800c026: f000 fd3b bl 800caa0 + 800c02a: e77a b.n 800bf22 + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + 800c02c: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800c02e: f000 fa53 bl 800c4d8 + ( void ) xTaskResumeAll(); + 800c032: f000 fd35 bl 800caa0 + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800c036: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800c038: f000 faa0 bl 800c57c + 800c03c: 4603 mov r3, r0 + 800c03e: 2b00 cmp r3, #0 + 800c040: f43f af6f beq.w 800bf22 + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800c044: 2300 movs r3, #0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} + 800c046: 4618 mov r0, r3 + 800c048: 3730 adds r7, #48 ; 0x30 + 800c04a: 46bd mov sp, r7 + 800c04c: bd80 pop {r7, pc} + 800c04e: bf00 nop + 800c050: e000ed04 .word 0xe000ed04 + +0800c054 : +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) +{ + 800c054: b580 push {r7, lr} + 800c056: b08e sub sp, #56 ; 0x38 + 800c058: af00 add r7, sp, #0 + 800c05a: 6078 str r0, [r7, #4] + 800c05c: 6039 str r1, [r7, #0] +BaseType_t xEntryTimeSet = pdFALSE; + 800c05e: 2300 movs r3, #0 + 800c060: 637b str r3, [r7, #52] ; 0x34 +TimeOut_t xTimeOut; +Queue_t * const pxQueue = xQueue; + 800c062: 687b ldr r3, [r7, #4] + 800c064: 62fb str r3, [r7, #44] ; 0x2c + +#if( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + 800c066: 2300 movs r3, #0 + 800c068: 633b str r3, [r7, #48] ; 0x30 +#endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + 800c06a: 6afb ldr r3, [r7, #44] ; 0x2c + 800c06c: 2b00 cmp r3, #0 + 800c06e: d10c bne.n 800c08a + __asm volatile + 800c070: f04f 0350 mov.w r3, #80 ; 0x50 + 800c074: b672 cpsid i + 800c076: f383 8811 msr BASEPRI, r3 + 800c07a: f3bf 8f6f isb sy + 800c07e: f3bf 8f4f dsb sy + 800c082: b662 cpsie i + 800c084: 623b str r3, [r7, #32] +} + 800c086: bf00 nop + 800c088: e7fe b.n 800c088 + + /* Check this really is a semaphore, in which case the item size will be + 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + 800c08a: 6afb ldr r3, [r7, #44] ; 0x2c + 800c08c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c08e: 2b00 cmp r3, #0 + 800c090: d00c beq.n 800c0ac + __asm volatile + 800c092: f04f 0350 mov.w r3, #80 ; 0x50 + 800c096: b672 cpsid i + 800c098: f383 8811 msr BASEPRI, r3 + 800c09c: f3bf 8f6f isb sy + 800c0a0: f3bf 8f4f dsb sy + 800c0a4: b662 cpsie i + 800c0a6: 61fb str r3, [r7, #28] +} + 800c0a8: bf00 nop + 800c0aa: e7fe b.n 800c0aa + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 800c0ac: f001 f8c4 bl 800d238 + 800c0b0: 4603 mov r3, r0 + 800c0b2: 2b00 cmp r3, #0 + 800c0b4: d102 bne.n 800c0bc + 800c0b6: 683b ldr r3, [r7, #0] + 800c0b8: 2b00 cmp r3, #0 + 800c0ba: d101 bne.n 800c0c0 + 800c0bc: 2301 movs r3, #1 + 800c0be: e000 b.n 800c0c2 + 800c0c0: 2300 movs r3, #0 + 800c0c2: 2b00 cmp r3, #0 + 800c0c4: d10c bne.n 800c0e0 + __asm volatile + 800c0c6: f04f 0350 mov.w r3, #80 ; 0x50 + 800c0ca: b672 cpsid i + 800c0cc: f383 8811 msr BASEPRI, r3 + 800c0d0: f3bf 8f6f isb sy + 800c0d4: f3bf 8f4f dsb sy + 800c0d8: b662 cpsie i + 800c0da: 61bb str r3, [r7, #24] +} + 800c0dc: bf00 nop + 800c0de: e7fe b.n 800c0de + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + statements within the function itself. This is done in the interest + of execution time efficiency. */ + for( ;; ) + { + taskENTER_CRITICAL(); + 800c0e0: f001 fbf4 bl 800d8cc + { + /* Semaphores are queues with an item size of 0, and where the + number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + 800c0e4: 6afb ldr r3, [r7, #44] ; 0x2c + 800c0e6: 6b9b ldr r3, [r3, #56] ; 0x38 + 800c0e8: 62bb str r3, [r7, #40] ; 0x28 + + /* Is there data in the queue now? To be running the calling task + must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + 800c0ea: 6abb ldr r3, [r7, #40] ; 0x28 + 800c0ec: 2b00 cmp r3, #0 + 800c0ee: d024 beq.n 800c13a + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + 800c0f0: 6abb ldr r3, [r7, #40] ; 0x28 + 800c0f2: 1e5a subs r2, r3, #1 + 800c0f4: 6afb ldr r3, [r7, #44] ; 0x2c + 800c0f6: 639a str r2, [r3, #56] ; 0x38 + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 800c0f8: 6afb ldr r3, [r7, #44] ; 0x2c + 800c0fa: 681b ldr r3, [r3, #0] + 800c0fc: 2b00 cmp r3, #0 + 800c0fe: d104 bne.n 800c10a + { + /* Record the information required to implement + priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + 800c100: f001 fa60 bl 800d5c4 + 800c104: 4602 mov r2, r0 + 800c106: 6afb ldr r3, [r7, #44] ; 0x2c + 800c108: 609a str r2, [r3, #8] + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800c10a: 6afb ldr r3, [r7, #44] ; 0x2c + 800c10c: 691b ldr r3, [r3, #16] + 800c10e: 2b00 cmp r3, #0 + 800c110: d00f beq.n 800c132 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800c112: 6afb ldr r3, [r7, #44] ; 0x2c + 800c114: 3310 adds r3, #16 + 800c116: 4618 mov r0, r3 + 800c118: f000 fec6 bl 800cea8 + 800c11c: 4603 mov r3, r0 + 800c11e: 2b00 cmp r3, #0 + 800c120: d007 beq.n 800c132 + { + queueYIELD_IF_USING_PREEMPTION(); + 800c122: 4b55 ldr r3, [pc, #340] ; (800c278 ) + 800c124: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800c128: 601a str r2, [r3, #0] + 800c12a: f3bf 8f4f dsb sy + 800c12e: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + 800c132: f001 fbff bl 800d934 + return pdPASS; + 800c136: 2301 movs r3, #1 + 800c138: e099 b.n 800c26e + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + 800c13a: 683b ldr r3, [r7, #0] + 800c13c: 2b00 cmp r3, #0 + 800c13e: d113 bne.n 800c168 + /* For inheritance to have occurred there must have been an + initial timeout, and an adjusted timeout cannot become 0, as + if it were 0 the function would have exited. */ + #if( configUSE_MUTEXES == 1 ) + { + configASSERT( xInheritanceOccurred == pdFALSE ); + 800c140: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c142: 2b00 cmp r3, #0 + 800c144: d00c beq.n 800c160 + __asm volatile + 800c146: f04f 0350 mov.w r3, #80 ; 0x50 + 800c14a: b672 cpsid i + 800c14c: f383 8811 msr BASEPRI, r3 + 800c150: f3bf 8f6f isb sy + 800c154: f3bf 8f4f dsb sy + 800c158: b662 cpsie i + 800c15a: 617b str r3, [r7, #20] +} + 800c15c: bf00 nop + 800c15e: e7fe b.n 800c15e + } + #endif /* configUSE_MUTEXES */ + + /* The semaphore count was 0 and no block time is specified + (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + 800c160: f001 fbe8 bl 800d934 + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800c164: 2300 movs r3, #0 + 800c166: e082 b.n 800c26e + } + else if( xEntryTimeSet == pdFALSE ) + 800c168: 6b7b ldr r3, [r7, #52] ; 0x34 + 800c16a: 2b00 cmp r3, #0 + 800c16c: d106 bne.n 800c17c + { + /* The semaphore count was 0 and a block time was specified + so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + 800c16e: f107 030c add.w r3, r7, #12 + 800c172: 4618 mov r0, r3 + 800c174: f000 fefc bl 800cf70 + xEntryTimeSet = pdTRUE; + 800c178: 2301 movs r3, #1 + 800c17a: 637b str r3, [r7, #52] ; 0x34 + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + 800c17c: f001 fbda bl 800d934 + + /* Interrupts and other tasks can give to and take from the semaphore + now the critical section has been exited. */ + + vTaskSuspendAll(); + 800c180: f000 fc80 bl 800ca84 + prvLockQueue( pxQueue ); + 800c184: f001 fba2 bl 800d8cc + 800c188: 6afb ldr r3, [r7, #44] ; 0x2c + 800c18a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 800c18e: b25b sxtb r3, r3 + 800c190: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800c194: d103 bne.n 800c19e + 800c196: 6afb ldr r3, [r7, #44] ; 0x2c + 800c198: 2200 movs r2, #0 + 800c19a: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800c19e: 6afb ldr r3, [r7, #44] ; 0x2c + 800c1a0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800c1a4: b25b sxtb r3, r3 + 800c1a6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800c1aa: d103 bne.n 800c1b4 + 800c1ac: 6afb ldr r3, [r7, #44] ; 0x2c + 800c1ae: 2200 movs r2, #0 + 800c1b0: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 800c1b4: f001 fbbe bl 800d934 + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800c1b8: 463a mov r2, r7 + 800c1ba: f107 030c add.w r3, r7, #12 + 800c1be: 4611 mov r1, r2 + 800c1c0: 4618 mov r0, r3 + 800c1c2: f000 feeb bl 800cf9c + 800c1c6: 4603 mov r3, r0 + 800c1c8: 2b00 cmp r3, #0 + 800c1ca: d132 bne.n 800c232 + { + /* A block time is specified and not expired. If the semaphore + count is 0 then enter the Blocked state to wait for a semaphore to + become available. As semaphores are implemented with queues the + queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800c1cc: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c1ce: f000 f9d5 bl 800c57c + 800c1d2: 4603 mov r3, r0 + 800c1d4: 2b00 cmp r3, #0 + 800c1d6: d026 beq.n 800c226 + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 800c1d8: 6afb ldr r3, [r7, #44] ; 0x2c + 800c1da: 681b ldr r3, [r3, #0] + 800c1dc: 2b00 cmp r3, #0 + 800c1de: d109 bne.n 800c1f4 + { + taskENTER_CRITICAL(); + 800c1e0: f001 fb74 bl 800d8cc + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + 800c1e4: 6afb ldr r3, [r7, #44] ; 0x2c + 800c1e6: 689b ldr r3, [r3, #8] + 800c1e8: 4618 mov r0, r3 + 800c1ea: f001 f843 bl 800d274 + 800c1ee: 6338 str r0, [r7, #48] ; 0x30 + } + taskEXIT_CRITICAL(); + 800c1f0: f001 fba0 bl 800d934 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 800c1f4: 6afb ldr r3, [r7, #44] ; 0x2c + 800c1f6: 3324 adds r3, #36 ; 0x24 + 800c1f8: 683a ldr r2, [r7, #0] + 800c1fa: 4611 mov r1, r2 + 800c1fc: 4618 mov r0, r3 + 800c1fe: f000 fe2d bl 800ce5c + prvUnlockQueue( pxQueue ); + 800c202: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c204: f000 f968 bl 800c4d8 + if( xTaskResumeAll() == pdFALSE ) + 800c208: f000 fc4a bl 800caa0 + 800c20c: 4603 mov r3, r0 + 800c20e: 2b00 cmp r3, #0 + 800c210: f47f af66 bne.w 800c0e0 + { + portYIELD_WITHIN_API(); + 800c214: 4b18 ldr r3, [pc, #96] ; (800c278 ) + 800c216: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800c21a: 601a str r2, [r3, #0] + 800c21c: f3bf 8f4f dsb sy + 800c220: f3bf 8f6f isb sy + 800c224: e75c b.n 800c0e0 + } + else + { + /* There was no timeout and the semaphore count was not 0, so + attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + 800c226: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c228: f000 f956 bl 800c4d8 + ( void ) xTaskResumeAll(); + 800c22c: f000 fc38 bl 800caa0 + 800c230: e756 b.n 800c0e0 + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + 800c232: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c234: f000 f950 bl 800c4d8 + ( void ) xTaskResumeAll(); + 800c238: f000 fc32 bl 800caa0 + + /* If the semaphore count is 0 exit now as the timeout has + expired. Otherwise return to attempt to take the semaphore that is + known to be available. As semaphores are implemented by queues the + queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 800c23c: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c23e: f000 f99d bl 800c57c + 800c242: 4603 mov r3, r0 + 800c244: 2b00 cmp r3, #0 + 800c246: f43f af4b beq.w 800c0e0 + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + 800c24a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c24c: 2b00 cmp r3, #0 + 800c24e: d00d beq.n 800c26c + { + taskENTER_CRITICAL(); + 800c250: f001 fb3c bl 800d8cc + /* This task blocking on the mutex caused another + task to inherit this task's priority. Now this task + has timed out the priority should be disinherited + again, but only as low as the next highest priority + task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + 800c254: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c256: f000 f897 bl 800c388 + 800c25a: 6278 str r0, [r7, #36] ; 0x24 + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + 800c25c: 6afb ldr r3, [r7, #44] ; 0x2c + 800c25e: 689b ldr r3, [r3, #8] + 800c260: 6a79 ldr r1, [r7, #36] ; 0x24 + 800c262: 4618 mov r0, r3 + 800c264: f001 f910 bl 800d488 + } + taskEXIT_CRITICAL(); + 800c268: f001 fb64 bl 800d934 + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + 800c26c: 2300 movs r3, #0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} + 800c26e: 4618 mov r0, r3 + 800c270: 3738 adds r7, #56 ; 0x38 + 800c272: 46bd mov sp, r7 + 800c274: bd80 pop {r7, pc} + 800c276: bf00 nop + 800c278: e000ed04 .word 0xe000ed04 + +0800c27c : + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) +{ + 800c27c: b580 push {r7, lr} + 800c27e: b08e sub sp, #56 ; 0x38 + 800c280: af00 add r7, sp, #0 + 800c282: 60f8 str r0, [r7, #12] + 800c284: 60b9 str r1, [r7, #8] + 800c286: 607a str r2, [r7, #4] +BaseType_t xReturn; +UBaseType_t uxSavedInterruptStatus; +Queue_t * const pxQueue = xQueue; + 800c288: 68fb ldr r3, [r7, #12] + 800c28a: 633b str r3, [r7, #48] ; 0x30 + + configASSERT( pxQueue ); + 800c28c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c28e: 2b00 cmp r3, #0 + 800c290: d10c bne.n 800c2ac + __asm volatile + 800c292: f04f 0350 mov.w r3, #80 ; 0x50 + 800c296: b672 cpsid i + 800c298: f383 8811 msr BASEPRI, r3 + 800c29c: f3bf 8f6f isb sy + 800c2a0: f3bf 8f4f dsb sy + 800c2a4: b662 cpsie i + 800c2a6: 623b str r3, [r7, #32] +} + 800c2a8: bf00 nop + 800c2aa: e7fe b.n 800c2aa + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 800c2ac: 68bb ldr r3, [r7, #8] + 800c2ae: 2b00 cmp r3, #0 + 800c2b0: d103 bne.n 800c2ba + 800c2b2: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c2b4: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c2b6: 2b00 cmp r3, #0 + 800c2b8: d101 bne.n 800c2be + 800c2ba: 2301 movs r3, #1 + 800c2bc: e000 b.n 800c2c0 + 800c2be: 2300 movs r3, #0 + 800c2c0: 2b00 cmp r3, #0 + 800c2c2: d10c bne.n 800c2de + __asm volatile + 800c2c4: f04f 0350 mov.w r3, #80 ; 0x50 + 800c2c8: b672 cpsid i + 800c2ca: f383 8811 msr BASEPRI, r3 + 800c2ce: f3bf 8f6f isb sy + 800c2d2: f3bf 8f4f dsb sy + 800c2d6: b662 cpsie i + 800c2d8: 61fb str r3, [r7, #28] +} + 800c2da: bf00 nop + 800c2dc: e7fe b.n 800c2dc + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 800c2de: f001 fbdd bl 800da9c + __asm volatile + 800c2e2: f3ef 8211 mrs r2, BASEPRI + 800c2e6: f04f 0350 mov.w r3, #80 ; 0x50 + 800c2ea: b672 cpsid i + 800c2ec: f383 8811 msr BASEPRI, r3 + 800c2f0: f3bf 8f6f isb sy + 800c2f4: f3bf 8f4f dsb sy + 800c2f8: b662 cpsie i + 800c2fa: 61ba str r2, [r7, #24] + 800c2fc: 617b str r3, [r7, #20] + return ulOriginalBASEPRI; + 800c2fe: 69bb ldr r3, [r7, #24] + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + 800c300: 62fb str r3, [r7, #44] ; 0x2c + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 800c302: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c304: 6b9b ldr r3, [r3, #56] ; 0x38 + 800c306: 62bb str r3, [r7, #40] ; 0x28 + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 800c308: 6abb ldr r3, [r7, #40] ; 0x28 + 800c30a: 2b00 cmp r3, #0 + 800c30c: d02f beq.n 800c36e + { + const int8_t cRxLock = pxQueue->cRxLock; + 800c30e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c310: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 800c314: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 800c318: 68b9 ldr r1, [r7, #8] + 800c31a: 6b38 ldr r0, [r7, #48] ; 0x30 + 800c31c: f000 f8b6 bl 800c48c + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + 800c320: 6abb ldr r3, [r7, #40] ; 0x28 + 800c322: 1e5a subs r2, r3, #1 + 800c324: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c326: 639a str r2, [r3, #56] ; 0x38 + + /* If the queue is locked the event list will not be modified. + Instead update the lock count so the task that unlocks the queue + will know that an ISR has removed data while the queue was + locked. */ + if( cRxLock == queueUNLOCKED ) + 800c328: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 800c32c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800c330: d112 bne.n 800c358 + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800c332: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c334: 691b ldr r3, [r3, #16] + 800c336: 2b00 cmp r3, #0 + 800c338: d016 beq.n 800c368 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800c33a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c33c: 3310 adds r3, #16 + 800c33e: 4618 mov r0, r3 + 800c340: f000 fdb2 bl 800cea8 + 800c344: 4603 mov r3, r0 + 800c346: 2b00 cmp r3, #0 + 800c348: d00e beq.n 800c368 + { + /* The task waiting has a higher priority than us so + force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + 800c34a: 687b ldr r3, [r7, #4] + 800c34c: 2b00 cmp r3, #0 + 800c34e: d00b beq.n 800c368 + { + *pxHigherPriorityTaskWoken = pdTRUE; + 800c350: 687b ldr r3, [r7, #4] + 800c352: 2201 movs r2, #1 + 800c354: 601a str r2, [r3, #0] + 800c356: e007 b.n 800c368 + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was removed while it was locked. */ + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); + 800c358: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800c35c: 3301 adds r3, #1 + 800c35e: b2db uxtb r3, r3 + 800c360: b25a sxtb r2, r3 + 800c362: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c364: f883 2044 strb.w r2, [r3, #68] ; 0x44 + } + + xReturn = pdPASS; + 800c368: 2301 movs r3, #1 + 800c36a: 637b str r3, [r7, #52] ; 0x34 + 800c36c: e001 b.n 800c372 + } + else + { + xReturn = pdFAIL; + 800c36e: 2300 movs r3, #0 + 800c370: 637b str r3, [r7, #52] ; 0x34 + 800c372: 6afb ldr r3, [r7, #44] ; 0x2c + 800c374: 613b str r3, [r7, #16] + __asm volatile + 800c376: 693b ldr r3, [r7, #16] + 800c378: f383 8811 msr BASEPRI, r3 +} + 800c37c: bf00 nop + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800c37e: 6b7b ldr r3, [r7, #52] ; 0x34 +} + 800c380: 4618 mov r0, r3 + 800c382: 3738 adds r7, #56 ; 0x38 + 800c384: 46bd mov sp, r7 + 800c386: bd80 pop {r7, pc} + +0800c388 : +/*-----------------------------------------------------------*/ + +#if( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + 800c388: b480 push {r7} + 800c38a: b085 sub sp, #20 + 800c38c: af00 add r7, sp, #0 + 800c38e: 6078 str r0, [r7, #4] + priority, but the waiting task times out, then the holder should + disinherit the priority - but only down to the highest priority of any + other tasks that are waiting for the same mutex. For this purpose, + return the priority of the highest priority task that is waiting for the + mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + 800c390: 687b ldr r3, [r7, #4] + 800c392: 6a5b ldr r3, [r3, #36] ; 0x24 + 800c394: 2b00 cmp r3, #0 + 800c396: d006 beq.n 800c3a6 + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + 800c398: 687b ldr r3, [r7, #4] + 800c39a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800c39c: 681b ldr r3, [r3, #0] + 800c39e: f1c3 0307 rsb r3, r3, #7 + 800c3a2: 60fb str r3, [r7, #12] + 800c3a4: e001 b.n 800c3aa + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + 800c3a6: 2300 movs r3, #0 + 800c3a8: 60fb str r3, [r7, #12] + } + + return uxHighestPriorityOfWaitingTasks; + 800c3aa: 68fb ldr r3, [r7, #12] + } + 800c3ac: 4618 mov r0, r3 + 800c3ae: 3714 adds r7, #20 + 800c3b0: 46bd mov sp, r7 + 800c3b2: f85d 7b04 ldr.w r7, [sp], #4 + 800c3b6: 4770 bx lr + +0800c3b8 : + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) +{ + 800c3b8: b580 push {r7, lr} + 800c3ba: b086 sub sp, #24 + 800c3bc: af00 add r7, sp, #0 + 800c3be: 60f8 str r0, [r7, #12] + 800c3c0: 60b9 str r1, [r7, #8] + 800c3c2: 607a str r2, [r7, #4] +BaseType_t xReturn = pdFALSE; + 800c3c4: 2300 movs r3, #0 + 800c3c6: 617b str r3, [r7, #20] +UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 800c3c8: 68fb ldr r3, [r7, #12] + 800c3ca: 6b9b ldr r3, [r3, #56] ; 0x38 + 800c3cc: 613b str r3, [r7, #16] + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + 800c3ce: 68fb ldr r3, [r7, #12] + 800c3d0: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c3d2: 2b00 cmp r3, #0 + 800c3d4: d10d bne.n 800c3f2 + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 800c3d6: 68fb ldr r3, [r7, #12] + 800c3d8: 681b ldr r3, [r3, #0] + 800c3da: 2b00 cmp r3, #0 + 800c3dc: d14d bne.n 800c47a + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + 800c3de: 68fb ldr r3, [r7, #12] + 800c3e0: 689b ldr r3, [r3, #8] + 800c3e2: 4618 mov r0, r3 + 800c3e4: f000 ffc6 bl 800d374 + 800c3e8: 6178 str r0, [r7, #20] + pxQueue->u.xSemaphore.xMutexHolder = NULL; + 800c3ea: 68fb ldr r3, [r7, #12] + 800c3ec: 2200 movs r2, #0 + 800c3ee: 609a str r2, [r3, #8] + 800c3f0: e043 b.n 800c47a + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + 800c3f2: 687b ldr r3, [r7, #4] + 800c3f4: 2b00 cmp r3, #0 + 800c3f6: d119 bne.n 800c42c + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 800c3f8: 68fb ldr r3, [r7, #12] + 800c3fa: 6858 ldr r0, [r3, #4] + 800c3fc: 68fb ldr r3, [r7, #12] + 800c3fe: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c400: 461a mov r2, r3 + 800c402: 68b9 ldr r1, [r7, #8] + 800c404: f00f fd41 bl 801be8a + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 800c408: 68fb ldr r3, [r7, #12] + 800c40a: 685a ldr r2, [r3, #4] + 800c40c: 68fb ldr r3, [r7, #12] + 800c40e: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c410: 441a add r2, r3 + 800c412: 68fb ldr r3, [r7, #12] + 800c414: 605a str r2, [r3, #4] + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 800c416: 68fb ldr r3, [r7, #12] + 800c418: 685a ldr r2, [r3, #4] + 800c41a: 68fb ldr r3, [r7, #12] + 800c41c: 689b ldr r3, [r3, #8] + 800c41e: 429a cmp r2, r3 + 800c420: d32b bcc.n 800c47a + { + pxQueue->pcWriteTo = pxQueue->pcHead; + 800c422: 68fb ldr r3, [r7, #12] + 800c424: 681a ldr r2, [r3, #0] + 800c426: 68fb ldr r3, [r7, #12] + 800c428: 605a str r2, [r3, #4] + 800c42a: e026 b.n 800c47a + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + 800c42c: 68fb ldr r3, [r7, #12] + 800c42e: 68d8 ldr r0, [r3, #12] + 800c430: 68fb ldr r3, [r7, #12] + 800c432: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c434: 461a mov r2, r3 + 800c436: 68b9 ldr r1, [r7, #8] + 800c438: f00f fd27 bl 801be8a + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + 800c43c: 68fb ldr r3, [r7, #12] + 800c43e: 68da ldr r2, [r3, #12] + 800c440: 68fb ldr r3, [r7, #12] + 800c442: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c444: 425b negs r3, r3 + 800c446: 441a add r2, r3 + 800c448: 68fb ldr r3, [r7, #12] + 800c44a: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 800c44c: 68fb ldr r3, [r7, #12] + 800c44e: 68da ldr r2, [r3, #12] + 800c450: 68fb ldr r3, [r7, #12] + 800c452: 681b ldr r3, [r3, #0] + 800c454: 429a cmp r2, r3 + 800c456: d207 bcs.n 800c468 + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + 800c458: 68fb ldr r3, [r7, #12] + 800c45a: 689a ldr r2, [r3, #8] + 800c45c: 68fb ldr r3, [r7, #12] + 800c45e: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c460: 425b negs r3, r3 + 800c462: 441a add r2, r3 + 800c464: 68fb ldr r3, [r7, #12] + 800c466: 60da str r2, [r3, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + 800c468: 687b ldr r3, [r7, #4] + 800c46a: 2b02 cmp r3, #2 + 800c46c: d105 bne.n 800c47a + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 800c46e: 693b ldr r3, [r7, #16] + 800c470: 2b00 cmp r3, #0 + 800c472: d002 beq.n 800c47a + { + /* An item is not being added but overwritten, so subtract + one from the recorded number of items in the queue so when + one is added again below the number of recorded items remains + correct. */ + --uxMessagesWaiting; + 800c474: 693b ldr r3, [r7, #16] + 800c476: 3b01 subs r3, #1 + 800c478: 613b str r3, [r7, #16] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + 800c47a: 693b ldr r3, [r7, #16] + 800c47c: 1c5a adds r2, r3, #1 + 800c47e: 68fb ldr r3, [r7, #12] + 800c480: 639a str r2, [r3, #56] ; 0x38 + + return xReturn; + 800c482: 697b ldr r3, [r7, #20] +} + 800c484: 4618 mov r0, r3 + 800c486: 3718 adds r7, #24 + 800c488: 46bd mov sp, r7 + 800c48a: bd80 pop {r7, pc} + +0800c48c : +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) +{ + 800c48c: b580 push {r7, lr} + 800c48e: b082 sub sp, #8 + 800c490: af00 add r7, sp, #0 + 800c492: 6078 str r0, [r7, #4] + 800c494: 6039 str r1, [r7, #0] + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + 800c496: 687b ldr r3, [r7, #4] + 800c498: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c49a: 2b00 cmp r3, #0 + 800c49c: d018 beq.n 800c4d0 + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + 800c49e: 687b ldr r3, [r7, #4] + 800c4a0: 68da ldr r2, [r3, #12] + 800c4a2: 687b ldr r3, [r7, #4] + 800c4a4: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c4a6: 441a add r2, r3 + 800c4a8: 687b ldr r3, [r7, #4] + 800c4aa: 60da str r2, [r3, #12] + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + 800c4ac: 687b ldr r3, [r7, #4] + 800c4ae: 68da ldr r2, [r3, #12] + 800c4b0: 687b ldr r3, [r7, #4] + 800c4b2: 689b ldr r3, [r3, #8] + 800c4b4: 429a cmp r2, r3 + 800c4b6: d303 bcc.n 800c4c0 + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + 800c4b8: 687b ldr r3, [r7, #4] + 800c4ba: 681a ldr r2, [r3, #0] + 800c4bc: 687b ldr r3, [r7, #4] + 800c4be: 60da str r2, [r3, #12] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + 800c4c0: 687b ldr r3, [r7, #4] + 800c4c2: 68d9 ldr r1, [r3, #12] + 800c4c4: 687b ldr r3, [r7, #4] + 800c4c6: 6c1b ldr r3, [r3, #64] ; 0x40 + 800c4c8: 461a mov r2, r3 + 800c4ca: 6838 ldr r0, [r7, #0] + 800c4cc: f00f fcdd bl 801be8a + } +} + 800c4d0: bf00 nop + 800c4d2: 3708 adds r7, #8 + 800c4d4: 46bd mov sp, r7 + 800c4d6: bd80 pop {r7, pc} + +0800c4d8 : +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + 800c4d8: b580 push {r7, lr} + 800c4da: b084 sub sp, #16 + 800c4dc: af00 add r7, sp, #0 + 800c4de: 6078 str r0, [r7, #4] + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + 800c4e0: f001 f9f4 bl 800d8cc + { + int8_t cTxLock = pxQueue->cTxLock; + 800c4e4: 687b ldr r3, [r7, #4] + 800c4e6: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800c4ea: 73fb strb r3, [r7, #15] + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + 800c4ec: e011 b.n 800c512 + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800c4ee: 687b ldr r3, [r7, #4] + 800c4f0: 6a5b ldr r3, [r3, #36] ; 0x24 + 800c4f2: 2b00 cmp r3, #0 + 800c4f4: d012 beq.n 800c51c + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800c4f6: 687b ldr r3, [r7, #4] + 800c4f8: 3324 adds r3, #36 ; 0x24 + 800c4fa: 4618 mov r0, r3 + 800c4fc: f000 fcd4 bl 800cea8 + 800c500: 4603 mov r3, r0 + 800c502: 2b00 cmp r3, #0 + 800c504: d001 beq.n 800c50a + { + /* The task waiting has a higher priority so record that + a context switch is required. */ + vTaskMissedYield(); + 800c506: f000 fdaf bl 800d068 + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + 800c50a: 7bfb ldrb r3, [r7, #15] + 800c50c: 3b01 subs r3, #1 + 800c50e: b2db uxtb r3, r3 + 800c510: 73fb strb r3, [r7, #15] + while( cTxLock > queueLOCKED_UNMODIFIED ) + 800c512: f997 300f ldrsb.w r3, [r7, #15] + 800c516: 2b00 cmp r3, #0 + 800c518: dce9 bgt.n 800c4ee + 800c51a: e000 b.n 800c51e + break; + 800c51c: bf00 nop + } + + pxQueue->cTxLock = queueUNLOCKED; + 800c51e: 687b ldr r3, [r7, #4] + 800c520: 22ff movs r2, #255 ; 0xff + 800c522: f883 2045 strb.w r2, [r3, #69] ; 0x45 + } + taskEXIT_CRITICAL(); + 800c526: f001 fa05 bl 800d934 + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + 800c52a: f001 f9cf bl 800d8cc + { + int8_t cRxLock = pxQueue->cRxLock; + 800c52e: 687b ldr r3, [r7, #4] + 800c530: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 800c534: 73bb strb r3, [r7, #14] + + while( cRxLock > queueLOCKED_UNMODIFIED ) + 800c536: e011 b.n 800c55c + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800c538: 687b ldr r3, [r7, #4] + 800c53a: 691b ldr r3, [r3, #16] + 800c53c: 2b00 cmp r3, #0 + 800c53e: d012 beq.n 800c566 + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800c540: 687b ldr r3, [r7, #4] + 800c542: 3310 adds r3, #16 + 800c544: 4618 mov r0, r3 + 800c546: f000 fcaf bl 800cea8 + 800c54a: 4603 mov r3, r0 + 800c54c: 2b00 cmp r3, #0 + 800c54e: d001 beq.n 800c554 + { + vTaskMissedYield(); + 800c550: f000 fd8a bl 800d068 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + 800c554: 7bbb ldrb r3, [r7, #14] + 800c556: 3b01 subs r3, #1 + 800c558: b2db uxtb r3, r3 + 800c55a: 73bb strb r3, [r7, #14] + while( cRxLock > queueLOCKED_UNMODIFIED ) + 800c55c: f997 300e ldrsb.w r3, [r7, #14] + 800c560: 2b00 cmp r3, #0 + 800c562: dce9 bgt.n 800c538 + 800c564: e000 b.n 800c568 + } + else + { + break; + 800c566: bf00 nop + } + } + + pxQueue->cRxLock = queueUNLOCKED; + 800c568: 687b ldr r3, [r7, #4] + 800c56a: 22ff movs r2, #255 ; 0xff + 800c56c: f883 2044 strb.w r2, [r3, #68] ; 0x44 + } + taskEXIT_CRITICAL(); + 800c570: f001 f9e0 bl 800d934 +} + 800c574: bf00 nop + 800c576: 3710 adds r7, #16 + 800c578: 46bd mov sp, r7 + 800c57a: bd80 pop {r7, pc} + +0800c57c : +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) +{ + 800c57c: b580 push {r7, lr} + 800c57e: b084 sub sp, #16 + 800c580: af00 add r7, sp, #0 + 800c582: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 800c584: f001 f9a2 bl 800d8cc + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + 800c588: 687b ldr r3, [r7, #4] + 800c58a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800c58c: 2b00 cmp r3, #0 + 800c58e: d102 bne.n 800c596 + { + xReturn = pdTRUE; + 800c590: 2301 movs r3, #1 + 800c592: 60fb str r3, [r7, #12] + 800c594: e001 b.n 800c59a + } + else + { + xReturn = pdFALSE; + 800c596: 2300 movs r3, #0 + 800c598: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 800c59a: f001 f9cb bl 800d934 + + return xReturn; + 800c59e: 68fb ldr r3, [r7, #12] +} + 800c5a0: 4618 mov r0, r3 + 800c5a2: 3710 adds r7, #16 + 800c5a4: 46bd mov sp, r7 + 800c5a6: bd80 pop {r7, pc} + +0800c5a8 : + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) +{ + 800c5a8: b580 push {r7, lr} + 800c5aa: b084 sub sp, #16 + 800c5ac: af00 add r7, sp, #0 + 800c5ae: 6078 str r0, [r7, #4] +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 800c5b0: f001 f98c bl 800d8cc + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + 800c5b4: 687b ldr r3, [r7, #4] + 800c5b6: 6b9a ldr r2, [r3, #56] ; 0x38 + 800c5b8: 687b ldr r3, [r7, #4] + 800c5ba: 6bdb ldr r3, [r3, #60] ; 0x3c + 800c5bc: 429a cmp r2, r3 + 800c5be: d102 bne.n 800c5c6 + { + xReturn = pdTRUE; + 800c5c0: 2301 movs r3, #1 + 800c5c2: 60fb str r3, [r7, #12] + 800c5c4: e001 b.n 800c5ca + } + else + { + xReturn = pdFALSE; + 800c5c6: 2300 movs r3, #0 + 800c5c8: 60fb str r3, [r7, #12] + } + } + taskEXIT_CRITICAL(); + 800c5ca: f001 f9b3 bl 800d934 + + return xReturn; + 800c5ce: 68fb ldr r3, [r7, #12] +} + 800c5d0: 4618 mov r0, r3 + 800c5d2: 3710 adds r7, #16 + 800c5d4: 46bd mov sp, r7 + 800c5d6: bd80 pop {r7, pc} + +0800c5d8 : + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + 800c5d8: b580 push {r7, lr} + 800c5da: b08e sub sp, #56 ; 0x38 + 800c5dc: af04 add r7, sp, #16 + 800c5de: 60f8 str r0, [r7, #12] + 800c5e0: 60b9 str r1, [r7, #8] + 800c5e2: 607a str r2, [r7, #4] + 800c5e4: 603b str r3, [r7, #0] + TCB_t *pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + 800c5e6: 6b7b ldr r3, [r7, #52] ; 0x34 + 800c5e8: 2b00 cmp r3, #0 + 800c5ea: d10c bne.n 800c606 + __asm volatile + 800c5ec: f04f 0350 mov.w r3, #80 ; 0x50 + 800c5f0: b672 cpsid i + 800c5f2: f383 8811 msr BASEPRI, r3 + 800c5f6: f3bf 8f6f isb sy + 800c5fa: f3bf 8f4f dsb sy + 800c5fe: b662 cpsie i + 800c600: 623b str r3, [r7, #32] +} + 800c602: bf00 nop + 800c604: e7fe b.n 800c604 + configASSERT( pxTaskBuffer != NULL ); + 800c606: 6bbb ldr r3, [r7, #56] ; 0x38 + 800c608: 2b00 cmp r3, #0 + 800c60a: d10c bne.n 800c626 + __asm volatile + 800c60c: f04f 0350 mov.w r3, #80 ; 0x50 + 800c610: b672 cpsid i + 800c612: f383 8811 msr BASEPRI, r3 + 800c616: f3bf 8f6f isb sy + 800c61a: f3bf 8f4f dsb sy + 800c61e: b662 cpsie i + 800c620: 61fb str r3, [r7, #28] +} + 800c622: bf00 nop + 800c624: e7fe b.n 800c624 + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticTask_t equals the size of the real task + structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + 800c626: 23b4 movs r3, #180 ; 0xb4 + 800c628: 613b str r3, [r7, #16] + configASSERT( xSize == sizeof( TCB_t ) ); + 800c62a: 693b ldr r3, [r7, #16] + 800c62c: 2bb4 cmp r3, #180 ; 0xb4 + 800c62e: d00c beq.n 800c64a + __asm volatile + 800c630: f04f 0350 mov.w r3, #80 ; 0x50 + 800c634: b672 cpsid i + 800c636: f383 8811 msr BASEPRI, r3 + 800c63a: f3bf 8f6f isb sy + 800c63e: f3bf 8f4f dsb sy + 800c642: b662 cpsie i + 800c644: 61bb str r3, [r7, #24] +} + 800c646: bf00 nop + 800c648: e7fe b.n 800c648 + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + 800c64a: 693b ldr r3, [r7, #16] + } + #endif /* configASSERT_DEFINED */ + + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + 800c64c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800c64e: 2b00 cmp r3, #0 + 800c650: d01e beq.n 800c690 + 800c652: 6b7b ldr r3, [r7, #52] ; 0x34 + 800c654: 2b00 cmp r3, #0 + 800c656: d01b beq.n 800c690 + { + /* The memory used for the task's TCB and stack are passed into this + function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 800c658: 6bbb ldr r3, [r7, #56] ; 0x38 + 800c65a: 627b str r3, [r7, #36] ; 0x24 + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + 800c65c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c65e: 6b7a ldr r2, [r7, #52] ; 0x34 + 800c660: 631a str r2, [r3, #48] ; 0x30 + + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + 800c662: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c664: 2202 movs r2, #2 + 800c666: f883 20b1 strb.w r2, [r3, #177] ; 0xb1 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + 800c66a: 2300 movs r3, #0 + 800c66c: 9303 str r3, [sp, #12] + 800c66e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c670: 9302 str r3, [sp, #8] + 800c672: f107 0314 add.w r3, r7, #20 + 800c676: 9301 str r3, [sp, #4] + 800c678: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c67a: 9300 str r3, [sp, #0] + 800c67c: 683b ldr r3, [r7, #0] + 800c67e: 687a ldr r2, [r7, #4] + 800c680: 68b9 ldr r1, [r7, #8] + 800c682: 68f8 ldr r0, [r7, #12] + 800c684: f000 f850 bl 800c728 + prvAddNewTaskToReadyList( pxNewTCB ); + 800c688: 6a78 ldr r0, [r7, #36] ; 0x24 + 800c68a: f000 f8ed bl 800c868 + 800c68e: e001 b.n 800c694 + } + else + { + xReturn = NULL; + 800c690: 2300 movs r3, #0 + 800c692: 617b str r3, [r7, #20] + } + + return xReturn; + 800c694: 697b ldr r3, [r7, #20] + } + 800c696: 4618 mov r0, r3 + 800c698: 3728 adds r7, #40 ; 0x28 + 800c69a: 46bd mov sp, r7 + 800c69c: bd80 pop {r7, pc} + +0800c69e : + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + 800c69e: b580 push {r7, lr} + 800c6a0: b08c sub sp, #48 ; 0x30 + 800c6a2: af04 add r7, sp, #16 + 800c6a4: 60f8 str r0, [r7, #12] + 800c6a6: 60b9 str r1, [r7, #8] + 800c6a8: 603b str r3, [r7, #0] + 800c6aa: 4613 mov r3, r2 + 800c6ac: 80fb strh r3, [r7, #6] + #else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + 800c6ae: 88fb ldrh r3, [r7, #6] + 800c6b0: 009b lsls r3, r3, #2 + 800c6b2: 4618 mov r0, r3 + 800c6b4: f001 fa36 bl 800db24 + 800c6b8: 6178 str r0, [r7, #20] + + if( pxStack != NULL ) + 800c6ba: 697b ldr r3, [r7, #20] + 800c6bc: 2b00 cmp r3, #0 + 800c6be: d00e beq.n 800c6de + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + 800c6c0: 20b4 movs r0, #180 ; 0xb4 + 800c6c2: f001 fa2f bl 800db24 + 800c6c6: 61f8 str r0, [r7, #28] + + if( pxNewTCB != NULL ) + 800c6c8: 69fb ldr r3, [r7, #28] + 800c6ca: 2b00 cmp r3, #0 + 800c6cc: d003 beq.n 800c6d6 + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + 800c6ce: 69fb ldr r3, [r7, #28] + 800c6d0: 697a ldr r2, [r7, #20] + 800c6d2: 631a str r2, [r3, #48] ; 0x30 + 800c6d4: e005 b.n 800c6e2 + } + else + { + /* The stack cannot be used as the TCB was not created. Free + it again. */ + vPortFree( pxStack ); + 800c6d6: 6978 ldr r0, [r7, #20] + 800c6d8: f001 faee bl 800dcb8 + 800c6dc: e001 b.n 800c6e2 + } + } + else + { + pxNewTCB = NULL; + 800c6de: 2300 movs r3, #0 + 800c6e0: 61fb str r3, [r7, #28] + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + 800c6e2: 69fb ldr r3, [r7, #28] + 800c6e4: 2b00 cmp r3, #0 + 800c6e6: d017 beq.n 800c718 + { + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + 800c6e8: 69fb ldr r3, [r7, #28] + 800c6ea: 2200 movs r2, #0 + 800c6ec: f883 20b1 strb.w r2, [r3, #177] ; 0xb1 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + 800c6f0: 88fa ldrh r2, [r7, #6] + 800c6f2: 2300 movs r3, #0 + 800c6f4: 9303 str r3, [sp, #12] + 800c6f6: 69fb ldr r3, [r7, #28] + 800c6f8: 9302 str r3, [sp, #8] + 800c6fa: 6afb ldr r3, [r7, #44] ; 0x2c + 800c6fc: 9301 str r3, [sp, #4] + 800c6fe: 6abb ldr r3, [r7, #40] ; 0x28 + 800c700: 9300 str r3, [sp, #0] + 800c702: 683b ldr r3, [r7, #0] + 800c704: 68b9 ldr r1, [r7, #8] + 800c706: 68f8 ldr r0, [r7, #12] + 800c708: f000 f80e bl 800c728 + prvAddNewTaskToReadyList( pxNewTCB ); + 800c70c: 69f8 ldr r0, [r7, #28] + 800c70e: f000 f8ab bl 800c868 + xReturn = pdPASS; + 800c712: 2301 movs r3, #1 + 800c714: 61bb str r3, [r7, #24] + 800c716: e002 b.n 800c71e + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 800c718: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800c71c: 61bb str r3, [r7, #24] + } + + return xReturn; + 800c71e: 69bb ldr r3, [r7, #24] + } + 800c720: 4618 mov r0, r3 + 800c722: 3720 adds r7, #32 + 800c724: 46bd mov sp, r7 + 800c726: bd80 pop {r7, pc} + +0800c728 : + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + 800c728: b580 push {r7, lr} + 800c72a: b088 sub sp, #32 + 800c72c: af00 add r7, sp, #0 + 800c72e: 60f8 str r0, [r7, #12] + 800c730: 60b9 str r1, [r7, #8] + 800c732: 607a str r2, [r7, #4] + 800c734: 603b str r3, [r7, #0] + grows from high memory to low (as per the 80x86) or vice versa. + portSTACK_GROWTH is used to make the result positive or negative as required + by the port. */ + #if( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + 800c736: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c738: 6b1a ldr r2, [r3, #48] ; 0x30 + 800c73a: 6879 ldr r1, [r7, #4] + 800c73c: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000 + 800c740: 440b add r3, r1 + 800c742: 009b lsls r3, r3, #2 + 800c744: 4413 add r3, r2 + 800c746: 61bb str r3, [r7, #24] + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + 800c748: 69bb ldr r3, [r7, #24] + 800c74a: f023 0307 bic.w r3, r3, #7 + 800c74e: 61bb str r3, [r7, #24] + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + 800c750: 69bb ldr r3, [r7, #24] + 800c752: f003 0307 and.w r3, r3, #7 + 800c756: 2b00 cmp r3, #0 + 800c758: d00c beq.n 800c774 + __asm volatile + 800c75a: f04f 0350 mov.w r3, #80 ; 0x50 + 800c75e: b672 cpsid i + 800c760: f383 8811 msr BASEPRI, r3 + 800c764: f3bf 8f6f isb sy + 800c768: f3bf 8f4f dsb sy + 800c76c: b662 cpsie i + 800c76e: 617b str r3, [r7, #20] +} + 800c770: bf00 nop + 800c772: e7fe b.n 800c772 + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + 800c774: 68bb ldr r3, [r7, #8] + 800c776: 2b00 cmp r3, #0 + 800c778: d01f beq.n 800c7ba + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 800c77a: 2300 movs r3, #0 + 800c77c: 61fb str r3, [r7, #28] + 800c77e: e012 b.n 800c7a6 + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 800c780: 68ba ldr r2, [r7, #8] + 800c782: 69fb ldr r3, [r7, #28] + 800c784: 4413 add r3, r2 + 800c786: 7819 ldrb r1, [r3, #0] + 800c788: 6b3a ldr r2, [r7, #48] ; 0x30 + 800c78a: 69fb ldr r3, [r7, #28] + 800c78c: 4413 add r3, r2 + 800c78e: 3334 adds r3, #52 ; 0x34 + 800c790: 460a mov r2, r1 + 800c792: 701a strb r2, [r3, #0] + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + 800c794: 68ba ldr r2, [r7, #8] + 800c796: 69fb ldr r3, [r7, #28] + 800c798: 4413 add r3, r2 + 800c79a: 781b ldrb r3, [r3, #0] + 800c79c: 2b00 cmp r3, #0 + 800c79e: d006 beq.n 800c7ae + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 800c7a0: 69fb ldr r3, [r7, #28] + 800c7a2: 3301 adds r3, #1 + 800c7a4: 61fb str r3, [r7, #28] + 800c7a6: 69fb ldr r3, [r7, #28] + 800c7a8: 2b0f cmp r3, #15 + 800c7aa: d9e9 bls.n 800c780 + 800c7ac: e000 b.n 800c7b0 + { + break; + 800c7ae: bf00 nop + } + } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 800c7b0: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7b2: 2200 movs r2, #0 + 800c7b4: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 800c7b8: e003 b.n 800c7c2 + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + 800c7ba: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7bc: 2200 movs r2, #0 + 800c7be: f883 2034 strb.w r2, [r3, #52] ; 0x34 + } + + /* This is used as an array index so must ensure it's not too large. First + remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + 800c7c2: 6abb ldr r3, [r7, #40] ; 0x28 + 800c7c4: 2b06 cmp r3, #6 + 800c7c6: d901 bls.n 800c7cc + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + 800c7c8: 2306 movs r3, #6 + 800c7ca: 62bb str r3, [r7, #40] ; 0x28 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + 800c7cc: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7ce: 6aba ldr r2, [r7, #40] ; 0x28 + 800c7d0: 62da str r2, [r3, #44] ; 0x2c + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + 800c7d2: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7d4: 6aba ldr r2, [r7, #40] ; 0x28 + 800c7d6: 645a str r2, [r3, #68] ; 0x44 + pxNewTCB->uxMutexesHeld = 0; + 800c7d8: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7da: 2200 movs r2, #0 + 800c7dc: 649a str r2, [r3, #72] ; 0x48 + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 800c7de: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7e0: 3304 adds r3, #4 + 800c7e2: 4618 mov r0, r3 + 800c7e4: f7fe fee6 bl 800b5b4 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 800c7e8: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7ea: 3318 adds r3, #24 + 800c7ec: 4618 mov r0, r3 + 800c7ee: f7fe fee1 bl 800b5b4 + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 800c7f2: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c7f4: 6b3a ldr r2, [r7, #48] ; 0x30 + 800c7f6: 611a str r2, [r3, #16] + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800c7f8: 6abb ldr r3, [r7, #40] ; 0x28 + 800c7fa: f1c3 0207 rsb r2, r3, #7 + 800c7fe: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c800: 619a str r2, [r3, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 800c802: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c804: 6b3a ldr r2, [r7, #48] ; 0x30 + 800c806: 625a str r2, [r3, #36] ; 0x24 + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + pxNewTCB->ulNotifiedValue = 0; + 800c808: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c80a: 2200 movs r2, #0 + 800c80c: f8c3 20ac str.w r2, [r3, #172] ; 0xac + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 800c810: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c812: 2200 movs r2, #0 + 800c814: f883 20b0 strb.w r2, [r3, #176] ; 0xb0 + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Initialise this task's Newlib reent structure. */ + _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); + 800c818: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c81a: 334c adds r3, #76 ; 0x4c + 800c81c: 2260 movs r2, #96 ; 0x60 + 800c81e: 2100 movs r1, #0 + 800c820: 4618 mov r0, r3 + 800c822: f00f fb5a bl 801beda + 800c826: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c828: 4a0c ldr r2, [pc, #48] ; (800c85c ) + 800c82a: 651a str r2, [r3, #80] ; 0x50 + 800c82c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c82e: 4a0c ldr r2, [pc, #48] ; (800c860 ) + 800c830: 655a str r2, [r3, #84] ; 0x54 + 800c832: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c834: 4a0b ldr r2, [pc, #44] ; (800c864 ) + 800c836: 659a str r2, [r3, #88] ; 0x58 + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 800c838: 683a ldr r2, [r7, #0] + 800c83a: 68f9 ldr r1, [r7, #12] + 800c83c: 69b8 ldr r0, [r7, #24] + 800c83e: f000 ff3b bl 800d6b8 + 800c842: 4602 mov r2, r0 + 800c844: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c846: 601a str r2, [r3, #0] + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + 800c848: 6afb ldr r3, [r7, #44] ; 0x2c + 800c84a: 2b00 cmp r3, #0 + 800c84c: d002 beq.n 800c854 + { + /* Pass the handle out in an anonymous way. The handle can be used to + change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 800c84e: 6afb ldr r3, [r7, #44] ; 0x2c + 800c850: 6b3a ldr r2, [r7, #48] ; 0x30 + 800c852: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800c854: bf00 nop + 800c856: 3720 adds r7, #32 + 800c858: 46bd mov sp, r7 + 800c85a: bd80 pop {r7, pc} + 800c85c: 08023a58 .word 0x08023a58 + 800c860: 08023a78 .word 0x08023a78 + 800c864: 08023a38 .word 0x08023a38 + +0800c868 : +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) +{ + 800c868: b580 push {r7, lr} + 800c86a: b082 sub sp, #8 + 800c86c: af00 add r7, sp, #0 + 800c86e: 6078 str r0, [r7, #4] + /* Ensure interrupts don't access the task lists while the lists are being + updated. */ + taskENTER_CRITICAL(); + 800c870: f001 f82c bl 800d8cc + { + uxCurrentNumberOfTasks++; + 800c874: 4b2a ldr r3, [pc, #168] ; (800c920 ) + 800c876: 681b ldr r3, [r3, #0] + 800c878: 3301 adds r3, #1 + 800c87a: 4a29 ldr r2, [pc, #164] ; (800c920 ) + 800c87c: 6013 str r3, [r2, #0] + if( pxCurrentTCB == NULL ) + 800c87e: 4b29 ldr r3, [pc, #164] ; (800c924 ) + 800c880: 681b ldr r3, [r3, #0] + 800c882: 2b00 cmp r3, #0 + 800c884: d109 bne.n 800c89a + { + /* There are no other tasks, or all the other tasks are in + the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + 800c886: 4a27 ldr r2, [pc, #156] ; (800c924 ) + 800c888: 687b ldr r3, [r7, #4] + 800c88a: 6013 str r3, [r2, #0] + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 800c88c: 4b24 ldr r3, [pc, #144] ; (800c920 ) + 800c88e: 681b ldr r3, [r3, #0] + 800c890: 2b01 cmp r3, #1 + 800c892: d110 bne.n 800c8b6 + { + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + 800c894: f000 fc0c bl 800d0b0 + 800c898: e00d b.n 800c8b6 + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + 800c89a: 4b23 ldr r3, [pc, #140] ; (800c928 ) + 800c89c: 681b ldr r3, [r3, #0] + 800c89e: 2b00 cmp r3, #0 + 800c8a0: d109 bne.n 800c8b6 + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 800c8a2: 4b20 ldr r3, [pc, #128] ; (800c924 ) + 800c8a4: 681b ldr r3, [r3, #0] + 800c8a6: 6ada ldr r2, [r3, #44] ; 0x2c + 800c8a8: 687b ldr r3, [r7, #4] + 800c8aa: 6adb ldr r3, [r3, #44] ; 0x2c + 800c8ac: 429a cmp r2, r3 + 800c8ae: d802 bhi.n 800c8b6 + { + pxCurrentTCB = pxNewTCB; + 800c8b0: 4a1c ldr r2, [pc, #112] ; (800c924 ) + 800c8b2: 687b ldr r3, [r7, #4] + 800c8b4: 6013 str r3, [r2, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + 800c8b6: 4b1d ldr r3, [pc, #116] ; (800c92c ) + 800c8b8: 681b ldr r3, [r3, #0] + 800c8ba: 3301 adds r3, #1 + 800c8bc: 4a1b ldr r2, [pc, #108] ; (800c92c ) + 800c8be: 6013 str r3, [r2, #0] + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + 800c8c0: 687b ldr r3, [r7, #4] + 800c8c2: 6adb ldr r3, [r3, #44] ; 0x2c + 800c8c4: 2201 movs r2, #1 + 800c8c6: 409a lsls r2, r3 + 800c8c8: 4b19 ldr r3, [pc, #100] ; (800c930 ) + 800c8ca: 681b ldr r3, [r3, #0] + 800c8cc: 4313 orrs r3, r2 + 800c8ce: 4a18 ldr r2, [pc, #96] ; (800c930 ) + 800c8d0: 6013 str r3, [r2, #0] + 800c8d2: 687b ldr r3, [r7, #4] + 800c8d4: 6ada ldr r2, [r3, #44] ; 0x2c + 800c8d6: 4613 mov r3, r2 + 800c8d8: 009b lsls r3, r3, #2 + 800c8da: 4413 add r3, r2 + 800c8dc: 009b lsls r3, r3, #2 + 800c8de: 4a15 ldr r2, [pc, #84] ; (800c934 ) + 800c8e0: 441a add r2, r3 + 800c8e2: 687b ldr r3, [r7, #4] + 800c8e4: 3304 adds r3, #4 + 800c8e6: 4619 mov r1, r3 + 800c8e8: 4610 mov r0, r2 + 800c8ea: f7fe fe70 bl 800b5ce + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + 800c8ee: f001 f821 bl 800d934 + + if( xSchedulerRunning != pdFALSE ) + 800c8f2: 4b0d ldr r3, [pc, #52] ; (800c928 ) + 800c8f4: 681b ldr r3, [r3, #0] + 800c8f6: 2b00 cmp r3, #0 + 800c8f8: d00e beq.n 800c918 + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 800c8fa: 4b0a ldr r3, [pc, #40] ; (800c924 ) + 800c8fc: 681b ldr r3, [r3, #0] + 800c8fe: 6ada ldr r2, [r3, #44] ; 0x2c + 800c900: 687b ldr r3, [r7, #4] + 800c902: 6adb ldr r3, [r3, #44] ; 0x2c + 800c904: 429a cmp r2, r3 + 800c906: d207 bcs.n 800c918 + { + taskYIELD_IF_USING_PREEMPTION(); + 800c908: 4b0b ldr r3, [pc, #44] ; (800c938 ) + 800c90a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800c90e: 601a str r2, [r3, #0] + 800c910: f3bf 8f4f dsb sy + 800c914: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800c918: bf00 nop + 800c91a: 3708 adds r7, #8 + 800c91c: 46bd mov sp, r7 + 800c91e: bd80 pop {r7, pc} + 800c920: 20005588 .word 0x20005588 + 800c924: 20005488 .word 0x20005488 + 800c928: 20005594 .word 0x20005594 + 800c92c: 200055a4 .word 0x200055a4 + 800c930: 20005590 .word 0x20005590 + 800c934: 2000548c .word 0x2000548c + 800c938: e000ed04 .word 0xe000ed04 + +0800c93c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + 800c93c: b580 push {r7, lr} + 800c93e: b084 sub sp, #16 + 800c940: af00 add r7, sp, #0 + 800c942: 6078 str r0, [r7, #4] + BaseType_t xAlreadyYielded = pdFALSE; + 800c944: 2300 movs r3, #0 + 800c946: 60fb str r3, [r7, #12] + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + 800c948: 687b ldr r3, [r7, #4] + 800c94a: 2b00 cmp r3, #0 + 800c94c: d019 beq.n 800c982 + { + configASSERT( uxSchedulerSuspended == 0 ); + 800c94e: 4b14 ldr r3, [pc, #80] ; (800c9a0 ) + 800c950: 681b ldr r3, [r3, #0] + 800c952: 2b00 cmp r3, #0 + 800c954: d00c beq.n 800c970 + __asm volatile + 800c956: f04f 0350 mov.w r3, #80 ; 0x50 + 800c95a: b672 cpsid i + 800c95c: f383 8811 msr BASEPRI, r3 + 800c960: f3bf 8f6f isb sy + 800c964: f3bf 8f4f dsb sy + 800c968: b662 cpsie i + 800c96a: 60bb str r3, [r7, #8] +} + 800c96c: bf00 nop + 800c96e: e7fe b.n 800c96e + vTaskSuspendAll(); + 800c970: f000 f888 bl 800ca84 + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 800c974: 2100 movs r1, #0 + 800c976: 6878 ldr r0, [r7, #4] + 800c978: f000 fe38 bl 800d5ec + } + xAlreadyYielded = xTaskResumeAll(); + 800c97c: f000 f890 bl 800caa0 + 800c980: 60f8 str r0, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + 800c982: 68fb ldr r3, [r7, #12] + 800c984: 2b00 cmp r3, #0 + 800c986: d107 bne.n 800c998 + { + portYIELD_WITHIN_API(); + 800c988: 4b06 ldr r3, [pc, #24] ; (800c9a4 ) + 800c98a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800c98e: 601a str r2, [r3, #0] + 800c990: f3bf 8f4f dsb sy + 800c994: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 800c998: bf00 nop + 800c99a: 3710 adds r7, #16 + 800c99c: 46bd mov sp, r7 + 800c99e: bd80 pop {r7, pc} + 800c9a0: 200055b0 .word 0x200055b0 + 800c9a4: e000ed04 .word 0xe000ed04 + +0800c9a8 : + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + 800c9a8: b580 push {r7, lr} + 800c9aa: b08a sub sp, #40 ; 0x28 + 800c9ac: af04 add r7, sp, #16 +BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t *pxIdleTaskTCBBuffer = NULL; + 800c9ae: 2300 movs r3, #0 + 800c9b0: 60bb str r3, [r7, #8] + StackType_t *pxIdleTaskStackBuffer = NULL; + 800c9b2: 2300 movs r3, #0 + 800c9b4: 607b str r3, [r7, #4] + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + 800c9b6: 463a mov r2, r7 + 800c9b8: 1d39 adds r1, r7, #4 + 800c9ba: f107 0308 add.w r3, r7, #8 + 800c9be: 4618 mov r0, r3 + 800c9c0: f7f5 fdfc bl 80025bc + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + 800c9c4: 6839 ldr r1, [r7, #0] + 800c9c6: 687b ldr r3, [r7, #4] + 800c9c8: 68ba ldr r2, [r7, #8] + 800c9ca: 9202 str r2, [sp, #8] + 800c9cc: 9301 str r3, [sp, #4] + 800c9ce: 2300 movs r3, #0 + 800c9d0: 9300 str r3, [sp, #0] + 800c9d2: 2300 movs r3, #0 + 800c9d4: 460a mov r2, r1 + 800c9d6: 4923 ldr r1, [pc, #140] ; (800ca64 ) + 800c9d8: 4823 ldr r0, [pc, #140] ; (800ca68 ) + 800c9da: f7ff fdfd bl 800c5d8 + 800c9de: 4603 mov r3, r0 + 800c9e0: 4a22 ldr r2, [pc, #136] ; (800ca6c ) + 800c9e2: 6013 str r3, [r2, #0] + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + 800c9e4: 4b21 ldr r3, [pc, #132] ; (800ca6c ) + 800c9e6: 681b ldr r3, [r3, #0] + 800c9e8: 2b00 cmp r3, #0 + 800c9ea: d002 beq.n 800c9f2 + { + xReturn = pdPASS; + 800c9ec: 2301 movs r3, #1 + 800c9ee: 617b str r3, [r7, #20] + 800c9f0: e001 b.n 800c9f6 + } + else + { + xReturn = pdFAIL; + 800c9f2: 2300 movs r3, #0 + 800c9f4: 617b str r3, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + 800c9f6: 697b ldr r3, [r7, #20] + 800c9f8: 2b01 cmp r3, #1 + 800c9fa: d11d bne.n 800ca38 + __asm volatile + 800c9fc: f04f 0350 mov.w r3, #80 ; 0x50 + 800ca00: b672 cpsid i + 800ca02: f383 8811 msr BASEPRI, r3 + 800ca06: f3bf 8f6f isb sy + 800ca0a: f3bf 8f4f dsb sy + 800ca0e: b662 cpsie i + 800ca10: 613b str r3, [r7, #16] +} + 800ca12: bf00 nop + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + structure specific to the task that will run first. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + 800ca14: 4b16 ldr r3, [pc, #88] ; (800ca70 ) + 800ca16: 681b ldr r3, [r3, #0] + 800ca18: 334c adds r3, #76 ; 0x4c + 800ca1a: 4a16 ldr r2, [pc, #88] ; (800ca74 ) + 800ca1c: 6013 str r3, [r2, #0] + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + 800ca1e: 4b16 ldr r3, [pc, #88] ; (800ca78 ) + 800ca20: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800ca24: 601a str r2, [r3, #0] + xSchedulerRunning = pdTRUE; + 800ca26: 4b15 ldr r3, [pc, #84] ; (800ca7c ) + 800ca28: 2201 movs r2, #1 + 800ca2a: 601a str r2, [r3, #0] + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + 800ca2c: 4b14 ldr r3, [pc, #80] ; (800ca80 ) + 800ca2e: 2200 movs r2, #0 + 800ca30: 601a str r2, [r3, #0] + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + 800ca32: f000 fecd bl 800d7d0 + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; +} + 800ca36: e010 b.n 800ca5a + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + 800ca38: 697b ldr r3, [r7, #20] + 800ca3a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800ca3e: d10c bne.n 800ca5a + __asm volatile + 800ca40: f04f 0350 mov.w r3, #80 ; 0x50 + 800ca44: b672 cpsid i + 800ca46: f383 8811 msr BASEPRI, r3 + 800ca4a: f3bf 8f6f isb sy + 800ca4e: f3bf 8f4f dsb sy + 800ca52: b662 cpsie i + 800ca54: 60fb str r3, [r7, #12] +} + 800ca56: bf00 nop + 800ca58: e7fe b.n 800ca58 +} + 800ca5a: bf00 nop + 800ca5c: 3718 adds r7, #24 + 800ca5e: 46bd mov sp, r7 + 800ca60: bd80 pop {r7, pc} + 800ca62: bf00 nop + 800ca64: 0801e8f8 .word 0x0801e8f8 + 800ca68: 0800d081 .word 0x0800d081 + 800ca6c: 200055ac .word 0x200055ac + 800ca70: 20005488 .word 0x20005488 + 800ca74: 200000c4 .word 0x200000c4 + 800ca78: 200055a8 .word 0x200055a8 + 800ca7c: 20005594 .word 0x20005594 + 800ca80: 2000558c .word 0x2000558c + +0800ca84 : + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + 800ca84: b480 push {r7} + 800ca86: af00 add r7, sp, #0 + /* A critical section is not required as the variable is of type + BaseType_t. Please read Richard Barry's reply in the following link to a + post in the FreeRTOS support forum before reporting this as a bug! - + http://goo.gl/wu4acr */ + ++uxSchedulerSuspended; + 800ca88: 4b04 ldr r3, [pc, #16] ; (800ca9c ) + 800ca8a: 681b ldr r3, [r3, #0] + 800ca8c: 3301 adds r3, #1 + 800ca8e: 4a03 ldr r2, [pc, #12] ; (800ca9c ) + 800ca90: 6013 str r3, [r2, #0] + portMEMORY_BARRIER(); +} + 800ca92: bf00 nop + 800ca94: 46bd mov sp, r7 + 800ca96: f85d 7b04 ldr.w r7, [sp], #4 + 800ca9a: 4770 bx lr + 800ca9c: 200055b0 .word 0x200055b0 + +0800caa0 : + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + 800caa0: b580 push {r7, lr} + 800caa2: b084 sub sp, #16 + 800caa4: af00 add r7, sp, #0 +TCB_t *pxTCB = NULL; + 800caa6: 2300 movs r3, #0 + 800caa8: 60fb str r3, [r7, #12] +BaseType_t xAlreadyYielded = pdFALSE; + 800caaa: 2300 movs r3, #0 + 800caac: 60bb str r3, [r7, #8] + + /* If uxSchedulerSuspended is zero then this function does not match a + previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + 800caae: 4b42 ldr r3, [pc, #264] ; (800cbb8 ) + 800cab0: 681b ldr r3, [r3, #0] + 800cab2: 2b00 cmp r3, #0 + 800cab4: d10c bne.n 800cad0 + __asm volatile + 800cab6: f04f 0350 mov.w r3, #80 ; 0x50 + 800caba: b672 cpsid i + 800cabc: f383 8811 msr BASEPRI, r3 + 800cac0: f3bf 8f6f isb sy + 800cac4: f3bf 8f4f dsb sy + 800cac8: b662 cpsie i + 800caca: 603b str r3, [r7, #0] +} + 800cacc: bf00 nop + 800cace: e7fe b.n 800cace + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + 800cad0: f000 fefc bl 800d8cc + { + --uxSchedulerSuspended; + 800cad4: 4b38 ldr r3, [pc, #224] ; (800cbb8 ) + 800cad6: 681b ldr r3, [r3, #0] + 800cad8: 3b01 subs r3, #1 + 800cada: 4a37 ldr r2, [pc, #220] ; (800cbb8 ) + 800cadc: 6013 str r3, [r2, #0] + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800cade: 4b36 ldr r3, [pc, #216] ; (800cbb8 ) + 800cae0: 681b ldr r3, [r3, #0] + 800cae2: 2b00 cmp r3, #0 + 800cae4: d161 bne.n 800cbaa + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 800cae6: 4b35 ldr r3, [pc, #212] ; (800cbbc ) + 800cae8: 681b ldr r3, [r3, #0] + 800caea: 2b00 cmp r3, #0 + 800caec: d05d beq.n 800cbaa + { + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 800caee: e02e b.n 800cb4e + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800caf0: 4b33 ldr r3, [pc, #204] ; (800cbc0 ) + 800caf2: 68db ldr r3, [r3, #12] + 800caf4: 68db ldr r3, [r3, #12] + 800caf6: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 800caf8: 68fb ldr r3, [r7, #12] + 800cafa: 3318 adds r3, #24 + 800cafc: 4618 mov r0, r3 + 800cafe: f7fe fdc3 bl 800b688 + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800cb02: 68fb ldr r3, [r7, #12] + 800cb04: 3304 adds r3, #4 + 800cb06: 4618 mov r0, r3 + 800cb08: f7fe fdbe bl 800b688 + prvAddTaskToReadyList( pxTCB ); + 800cb0c: 68fb ldr r3, [r7, #12] + 800cb0e: 6adb ldr r3, [r3, #44] ; 0x2c + 800cb10: 2201 movs r2, #1 + 800cb12: 409a lsls r2, r3 + 800cb14: 4b2b ldr r3, [pc, #172] ; (800cbc4 ) + 800cb16: 681b ldr r3, [r3, #0] + 800cb18: 4313 orrs r3, r2 + 800cb1a: 4a2a ldr r2, [pc, #168] ; (800cbc4 ) + 800cb1c: 6013 str r3, [r2, #0] + 800cb1e: 68fb ldr r3, [r7, #12] + 800cb20: 6ada ldr r2, [r3, #44] ; 0x2c + 800cb22: 4613 mov r3, r2 + 800cb24: 009b lsls r3, r3, #2 + 800cb26: 4413 add r3, r2 + 800cb28: 009b lsls r3, r3, #2 + 800cb2a: 4a27 ldr r2, [pc, #156] ; (800cbc8 ) + 800cb2c: 441a add r2, r3 + 800cb2e: 68fb ldr r3, [r7, #12] + 800cb30: 3304 adds r3, #4 + 800cb32: 4619 mov r1, r3 + 800cb34: 4610 mov r0, r2 + 800cb36: f7fe fd4a bl 800b5ce + + /* If the moved task has a priority higher than the current + task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800cb3a: 68fb ldr r3, [r7, #12] + 800cb3c: 6ada ldr r2, [r3, #44] ; 0x2c + 800cb3e: 4b23 ldr r3, [pc, #140] ; (800cbcc ) + 800cb40: 681b ldr r3, [r3, #0] + 800cb42: 6adb ldr r3, [r3, #44] ; 0x2c + 800cb44: 429a cmp r2, r3 + 800cb46: d302 bcc.n 800cb4e + { + xYieldPending = pdTRUE; + 800cb48: 4b21 ldr r3, [pc, #132] ; (800cbd0 ) + 800cb4a: 2201 movs r2, #1 + 800cb4c: 601a str r2, [r3, #0] + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 800cb4e: 4b1c ldr r3, [pc, #112] ; (800cbc0 ) + 800cb50: 681b ldr r3, [r3, #0] + 800cb52: 2b00 cmp r3, #0 + 800cb54: d1cc bne.n 800caf0 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + 800cb56: 68fb ldr r3, [r7, #12] + 800cb58: 2b00 cmp r3, #0 + 800cb5a: d001 beq.n 800cb60 + which may have prevented the next unblock time from being + re-calculated, in which case re-calculate it now. Mainly + important for low power tickless implementations, where + this can prevent an unnecessary exit from low power + state. */ + prvResetNextTaskUnblockTime(); + 800cb5c: f000 fb4c bl 800d1f8 + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does + not slip, and that any delayed tasks are resumed at the correct + time. */ + { + UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + 800cb60: 4b1c ldr r3, [pc, #112] ; (800cbd4 ) + 800cb62: 681b ldr r3, [r3, #0] + 800cb64: 607b str r3, [r7, #4] + + if( uxPendedCounts > ( UBaseType_t ) 0U ) + 800cb66: 687b ldr r3, [r7, #4] + 800cb68: 2b00 cmp r3, #0 + 800cb6a: d010 beq.n 800cb8e + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + 800cb6c: f000 f858 bl 800cc20 + 800cb70: 4603 mov r3, r0 + 800cb72: 2b00 cmp r3, #0 + 800cb74: d002 beq.n 800cb7c + { + xYieldPending = pdTRUE; + 800cb76: 4b16 ldr r3, [pc, #88] ; (800cbd0 ) + 800cb78: 2201 movs r2, #1 + 800cb7a: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + --uxPendedCounts; + 800cb7c: 687b ldr r3, [r7, #4] + 800cb7e: 3b01 subs r3, #1 + 800cb80: 607b str r3, [r7, #4] + } while( uxPendedCounts > ( UBaseType_t ) 0U ); + 800cb82: 687b ldr r3, [r7, #4] + 800cb84: 2b00 cmp r3, #0 + 800cb86: d1f1 bne.n 800cb6c + + uxPendedTicks = 0; + 800cb88: 4b12 ldr r3, [pc, #72] ; (800cbd4 ) + 800cb8a: 2200 movs r2, #0 + 800cb8c: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + 800cb8e: 4b10 ldr r3, [pc, #64] ; (800cbd0 ) + 800cb90: 681b ldr r3, [r3, #0] + 800cb92: 2b00 cmp r3, #0 + 800cb94: d009 beq.n 800cbaa + { + #if( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + 800cb96: 2301 movs r3, #1 + 800cb98: 60bb str r3, [r7, #8] + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + 800cb9a: 4b0f ldr r3, [pc, #60] ; (800cbd8 ) + 800cb9c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800cba0: 601a str r2, [r3, #0] + 800cba2: f3bf 8f4f dsb sy + 800cba6: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 800cbaa: f000 fec3 bl 800d934 + + return xAlreadyYielded; + 800cbae: 68bb ldr r3, [r7, #8] +} + 800cbb0: 4618 mov r0, r3 + 800cbb2: 3710 adds r7, #16 + 800cbb4: 46bd mov sp, r7 + 800cbb6: bd80 pop {r7, pc} + 800cbb8: 200055b0 .word 0x200055b0 + 800cbbc: 20005588 .word 0x20005588 + 800cbc0: 20005548 .word 0x20005548 + 800cbc4: 20005590 .word 0x20005590 + 800cbc8: 2000548c .word 0x2000548c + 800cbcc: 20005488 .word 0x20005488 + 800cbd0: 2000559c .word 0x2000559c + 800cbd4: 20005598 .word 0x20005598 + 800cbd8: e000ed04 .word 0xe000ed04 + +0800cbdc : +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + 800cbdc: b480 push {r7} + 800cbde: b083 sub sp, #12 + 800cbe0: af00 add r7, sp, #0 +TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + 800cbe2: 4b05 ldr r3, [pc, #20] ; (800cbf8 ) + 800cbe4: 681b ldr r3, [r3, #0] + 800cbe6: 607b str r3, [r7, #4] + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; + 800cbe8: 687b ldr r3, [r7, #4] +} + 800cbea: 4618 mov r0, r3 + 800cbec: 370c adds r7, #12 + 800cbee: 46bd mov sp, r7 + 800cbf0: f85d 7b04 ldr.w r7, [sp], #4 + 800cbf4: 4770 bx lr + 800cbf6: bf00 nop + 800cbf8: 2000558c .word 0x2000558c + +0800cbfc : +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR( void ) +{ + 800cbfc: b580 push {r7, lr} + 800cbfe: b082 sub sp, #8 + 800cc00: af00 add r7, sp, #0 + that have been assigned a priority at or (logically) below the maximum + system call interrupt priority. FreeRTOS maintains a separate interrupt + safe API to ensure interrupt entry is as fast and as simple as possible. + More information (albeit Cortex-M specific) is provided on the following + link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 800cc02: f000 ff4b bl 800da9c + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + 800cc06: 2300 movs r3, #0 + 800cc08: 607b str r3, [r7, #4] + { + xReturn = xTickCount; + 800cc0a: 4b04 ldr r3, [pc, #16] ; (800cc1c ) + 800cc0c: 681b ldr r3, [r3, #0] + 800cc0e: 603b str r3, [r7, #0] + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + 800cc10: 683b ldr r3, [r7, #0] +} + 800cc12: 4618 mov r0, r3 + 800cc14: 3708 adds r7, #8 + 800cc16: 46bd mov sp, r7 + 800cc18: bd80 pop {r7, pc} + 800cc1a: bf00 nop + 800cc1c: 2000558c .word 0x2000558c + +0800cc20 : + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + 800cc20: b580 push {r7, lr} + 800cc22: b086 sub sp, #24 + 800cc24: af00 add r7, sp, #0 +TCB_t * pxTCB; +TickType_t xItemValue; +BaseType_t xSwitchRequired = pdFALSE; + 800cc26: 2300 movs r3, #0 + 800cc28: 617b str r3, [r7, #20] + + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800cc2a: 4b4f ldr r3, [pc, #316] ; (800cd68 ) + 800cc2c: 681b ldr r3, [r3, #0] + 800cc2e: 2b00 cmp r3, #0 + 800cc30: f040 808a bne.w 800cd48 + { + /* Minor optimisation. The tick count cannot change in this + block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + 800cc34: 4b4d ldr r3, [pc, #308] ; (800cd6c ) + 800cc36: 681b ldr r3, [r3, #0] + 800cc38: 3301 adds r3, #1 + 800cc3a: 613b str r3, [r7, #16] + + /* Increment the RTOS tick, switching the delayed and overflowed + delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + 800cc3c: 4a4b ldr r2, [pc, #300] ; (800cd6c ) + 800cc3e: 693b ldr r3, [r7, #16] + 800cc40: 6013 str r3, [r2, #0] + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + 800cc42: 693b ldr r3, [r7, #16] + 800cc44: 2b00 cmp r3, #0 + 800cc46: d122 bne.n 800cc8e + { + taskSWITCH_DELAYED_LISTS(); + 800cc48: 4b49 ldr r3, [pc, #292] ; (800cd70 ) + 800cc4a: 681b ldr r3, [r3, #0] + 800cc4c: 681b ldr r3, [r3, #0] + 800cc4e: 2b00 cmp r3, #0 + 800cc50: d00c beq.n 800cc6c + __asm volatile + 800cc52: f04f 0350 mov.w r3, #80 ; 0x50 + 800cc56: b672 cpsid i + 800cc58: f383 8811 msr BASEPRI, r3 + 800cc5c: f3bf 8f6f isb sy + 800cc60: f3bf 8f4f dsb sy + 800cc64: b662 cpsie i + 800cc66: 603b str r3, [r7, #0] +} + 800cc68: bf00 nop + 800cc6a: e7fe b.n 800cc6a + 800cc6c: 4b40 ldr r3, [pc, #256] ; (800cd70 ) + 800cc6e: 681b ldr r3, [r3, #0] + 800cc70: 60fb str r3, [r7, #12] + 800cc72: 4b40 ldr r3, [pc, #256] ; (800cd74 ) + 800cc74: 681b ldr r3, [r3, #0] + 800cc76: 4a3e ldr r2, [pc, #248] ; (800cd70 ) + 800cc78: 6013 str r3, [r2, #0] + 800cc7a: 4a3e ldr r2, [pc, #248] ; (800cd74 ) + 800cc7c: 68fb ldr r3, [r7, #12] + 800cc7e: 6013 str r3, [r2, #0] + 800cc80: 4b3d ldr r3, [pc, #244] ; (800cd78 ) + 800cc82: 681b ldr r3, [r3, #0] + 800cc84: 3301 adds r3, #1 + 800cc86: 4a3c ldr r2, [pc, #240] ; (800cd78 ) + 800cc88: 6013 str r3, [r2, #0] + 800cc8a: f000 fab5 bl 800d1f8 + + /* See if this tick has made a timeout expire. Tasks are stored in + the queue in the order of their wake time - meaning once one task + has been found whose block time has not expired there is no need to + look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + 800cc8e: 4b3b ldr r3, [pc, #236] ; (800cd7c ) + 800cc90: 681b ldr r3, [r3, #0] + 800cc92: 693a ldr r2, [r7, #16] + 800cc94: 429a cmp r2, r3 + 800cc96: d348 bcc.n 800cd2a + { + for( ;; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800cc98: 4b35 ldr r3, [pc, #212] ; (800cd70 ) + 800cc9a: 681b ldr r3, [r3, #0] + 800cc9c: 681b ldr r3, [r3, #0] + 800cc9e: 2b00 cmp r3, #0 + 800cca0: d104 bne.n 800ccac + /* The delayed list is empty. Set xNextTaskUnblockTime + to the maximum possible value so it is extremely + unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass + next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800cca2: 4b36 ldr r3, [pc, #216] ; (800cd7c ) + 800cca4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800cca8: 601a str r2, [r3, #0] + break; + 800ccaa: e03e b.n 800cd2a + { + /* The delayed list is not empty, get the value of the + item at the head of the delayed list. This is the time + at which the task at the head of the delayed list must + be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800ccac: 4b30 ldr r3, [pc, #192] ; (800cd70 ) + 800ccae: 681b ldr r3, [r3, #0] + 800ccb0: 68db ldr r3, [r3, #12] + 800ccb2: 68db ldr r3, [r3, #12] + 800ccb4: 60bb str r3, [r7, #8] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 800ccb6: 68bb ldr r3, [r7, #8] + 800ccb8: 685b ldr r3, [r3, #4] + 800ccba: 607b str r3, [r7, #4] + + if( xConstTickCount < xItemValue ) + 800ccbc: 693a ldr r2, [r7, #16] + 800ccbe: 687b ldr r3, [r7, #4] + 800ccc0: 429a cmp r2, r3 + 800ccc2: d203 bcs.n 800cccc + /* It is not time to unblock this item yet, but the + item value is the time at which the task at the head + of the blocked list must be removed from the Blocked + state - so record the item value in + xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + 800ccc4: 4a2d ldr r2, [pc, #180] ; (800cd7c ) + 800ccc6: 687b ldr r3, [r7, #4] + 800ccc8: 6013 str r3, [r2, #0] + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + 800ccca: e02e b.n 800cd2a + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800cccc: 68bb ldr r3, [r7, #8] + 800ccce: 3304 adds r3, #4 + 800ccd0: 4618 mov r0, r3 + 800ccd2: f7fe fcd9 bl 800b688 + + /* Is the task waiting on an event also? If so remove + it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 800ccd6: 68bb ldr r3, [r7, #8] + 800ccd8: 6a9b ldr r3, [r3, #40] ; 0x28 + 800ccda: 2b00 cmp r3, #0 + 800ccdc: d004 beq.n 800cce8 + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 800ccde: 68bb ldr r3, [r7, #8] + 800cce0: 3318 adds r3, #24 + 800cce2: 4618 mov r0, r3 + 800cce4: f7fe fcd0 bl 800b688 + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + list. */ + prvAddTaskToReadyList( pxTCB ); + 800cce8: 68bb ldr r3, [r7, #8] + 800ccea: 6adb ldr r3, [r3, #44] ; 0x2c + 800ccec: 2201 movs r2, #1 + 800ccee: 409a lsls r2, r3 + 800ccf0: 4b23 ldr r3, [pc, #140] ; (800cd80 ) + 800ccf2: 681b ldr r3, [r3, #0] + 800ccf4: 4313 orrs r3, r2 + 800ccf6: 4a22 ldr r2, [pc, #136] ; (800cd80 ) + 800ccf8: 6013 str r3, [r2, #0] + 800ccfa: 68bb ldr r3, [r7, #8] + 800ccfc: 6ada ldr r2, [r3, #44] ; 0x2c + 800ccfe: 4613 mov r3, r2 + 800cd00: 009b lsls r3, r3, #2 + 800cd02: 4413 add r3, r2 + 800cd04: 009b lsls r3, r3, #2 + 800cd06: 4a1f ldr r2, [pc, #124] ; (800cd84 ) + 800cd08: 441a add r2, r3 + 800cd0a: 68bb ldr r3, [r7, #8] + 800cd0c: 3304 adds r3, #4 + 800cd0e: 4619 mov r1, r3 + 800cd10: 4610 mov r0, r2 + 800cd12: f7fe fc5c bl 800b5ce + { + /* Preemption is on, but a context switch should + only be performed if the unblocked task has a + priority that is equal to or higher than the + currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800cd16: 68bb ldr r3, [r7, #8] + 800cd18: 6ada ldr r2, [r3, #44] ; 0x2c + 800cd1a: 4b1b ldr r3, [pc, #108] ; (800cd88 ) + 800cd1c: 681b ldr r3, [r3, #0] + 800cd1e: 6adb ldr r3, [r3, #44] ; 0x2c + 800cd20: 429a cmp r2, r3 + 800cd22: d3b9 bcc.n 800cc98 + { + xSwitchRequired = pdTRUE; + 800cd24: 2301 movs r3, #1 + 800cd26: 617b str r3, [r7, #20] + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800cd28: e7b6 b.n 800cc98 + /* Tasks of equal priority to the currently running task will share + processing time (time slice) if preemption is on, and the application + writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 800cd2a: 4b17 ldr r3, [pc, #92] ; (800cd88 ) + 800cd2c: 681b ldr r3, [r3, #0] + 800cd2e: 6ada ldr r2, [r3, #44] ; 0x2c + 800cd30: 4914 ldr r1, [pc, #80] ; (800cd84 ) + 800cd32: 4613 mov r3, r2 + 800cd34: 009b lsls r3, r3, #2 + 800cd36: 4413 add r3, r2 + 800cd38: 009b lsls r3, r3, #2 + 800cd3a: 440b add r3, r1 + 800cd3c: 681b ldr r3, [r3, #0] + 800cd3e: 2b01 cmp r3, #1 + 800cd40: d907 bls.n 800cd52 + { + xSwitchRequired = pdTRUE; + 800cd42: 2301 movs r3, #1 + 800cd44: 617b str r3, [r7, #20] + 800cd46: e004 b.n 800cd52 + } + #endif /* configUSE_TICK_HOOK */ + } + else + { + ++uxPendedTicks; + 800cd48: 4b10 ldr r3, [pc, #64] ; (800cd8c ) + 800cd4a: 681b ldr r3, [r3, #0] + 800cd4c: 3301 adds r3, #1 + 800cd4e: 4a0f ldr r2, [pc, #60] ; (800cd8c ) + 800cd50: 6013 str r3, [r2, #0] + #endif + } + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + 800cd52: 4b0f ldr r3, [pc, #60] ; (800cd90 ) + 800cd54: 681b ldr r3, [r3, #0] + 800cd56: 2b00 cmp r3, #0 + 800cd58: d001 beq.n 800cd5e + { + xSwitchRequired = pdTRUE; + 800cd5a: 2301 movs r3, #1 + 800cd5c: 617b str r3, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + + return xSwitchRequired; + 800cd5e: 697b ldr r3, [r7, #20] +} + 800cd60: 4618 mov r0, r3 + 800cd62: 3718 adds r7, #24 + 800cd64: 46bd mov sp, r7 + 800cd66: bd80 pop {r7, pc} + 800cd68: 200055b0 .word 0x200055b0 + 800cd6c: 2000558c .word 0x2000558c + 800cd70: 20005540 .word 0x20005540 + 800cd74: 20005544 .word 0x20005544 + 800cd78: 200055a0 .word 0x200055a0 + 800cd7c: 200055a8 .word 0x200055a8 + 800cd80: 20005590 .word 0x20005590 + 800cd84: 2000548c .word 0x2000548c + 800cd88: 20005488 .word 0x20005488 + 800cd8c: 20005598 .word 0x20005598 + 800cd90: 2000559c .word 0x2000559c + +0800cd94 : + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + 800cd94: b480 push {r7} + 800cd96: b087 sub sp, #28 + 800cd98: af00 add r7, sp, #0 + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 800cd9a: 4b2a ldr r3, [pc, #168] ; (800ce44 ) + 800cd9c: 681b ldr r3, [r3, #0] + 800cd9e: 2b00 cmp r3, #0 + 800cda0: d003 beq.n 800cdaa + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xYieldPending = pdTRUE; + 800cda2: 4b29 ldr r3, [pc, #164] ; (800ce48 ) + 800cda4: 2201 movs r2, #1 + 800cda6: 601a str r2, [r3, #0] + structure specific to this task. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} + 800cda8: e046 b.n 800ce38 + xYieldPending = pdFALSE; + 800cdaa: 4b27 ldr r3, [pc, #156] ; (800ce48 ) + 800cdac: 2200 movs r2, #0 + 800cdae: 601a str r2, [r3, #0] + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800cdb0: 4b26 ldr r3, [pc, #152] ; (800ce4c ) + 800cdb2: 681b ldr r3, [r3, #0] + 800cdb4: 60fb str r3, [r7, #12] + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + 800cdb6: 68fb ldr r3, [r7, #12] + 800cdb8: fab3 f383 clz r3, r3 + 800cdbc: 72fb strb r3, [r7, #11] + return ucReturn; + 800cdbe: 7afb ldrb r3, [r7, #11] + 800cdc0: f1c3 031f rsb r3, r3, #31 + 800cdc4: 617b str r3, [r7, #20] + 800cdc6: 4922 ldr r1, [pc, #136] ; (800ce50 ) + 800cdc8: 697a ldr r2, [r7, #20] + 800cdca: 4613 mov r3, r2 + 800cdcc: 009b lsls r3, r3, #2 + 800cdce: 4413 add r3, r2 + 800cdd0: 009b lsls r3, r3, #2 + 800cdd2: 440b add r3, r1 + 800cdd4: 681b ldr r3, [r3, #0] + 800cdd6: 2b00 cmp r3, #0 + 800cdd8: d10c bne.n 800cdf4 + __asm volatile + 800cdda: f04f 0350 mov.w r3, #80 ; 0x50 + 800cdde: b672 cpsid i + 800cde0: f383 8811 msr BASEPRI, r3 + 800cde4: f3bf 8f6f isb sy + 800cde8: f3bf 8f4f dsb sy + 800cdec: b662 cpsie i + 800cdee: 607b str r3, [r7, #4] +} + 800cdf0: bf00 nop + 800cdf2: e7fe b.n 800cdf2 + 800cdf4: 697a ldr r2, [r7, #20] + 800cdf6: 4613 mov r3, r2 + 800cdf8: 009b lsls r3, r3, #2 + 800cdfa: 4413 add r3, r2 + 800cdfc: 009b lsls r3, r3, #2 + 800cdfe: 4a14 ldr r2, [pc, #80] ; (800ce50 ) + 800ce00: 4413 add r3, r2 + 800ce02: 613b str r3, [r7, #16] + 800ce04: 693b ldr r3, [r7, #16] + 800ce06: 685b ldr r3, [r3, #4] + 800ce08: 685a ldr r2, [r3, #4] + 800ce0a: 693b ldr r3, [r7, #16] + 800ce0c: 605a str r2, [r3, #4] + 800ce0e: 693b ldr r3, [r7, #16] + 800ce10: 685a ldr r2, [r3, #4] + 800ce12: 693b ldr r3, [r7, #16] + 800ce14: 3308 adds r3, #8 + 800ce16: 429a cmp r2, r3 + 800ce18: d104 bne.n 800ce24 + 800ce1a: 693b ldr r3, [r7, #16] + 800ce1c: 685b ldr r3, [r3, #4] + 800ce1e: 685a ldr r2, [r3, #4] + 800ce20: 693b ldr r3, [r7, #16] + 800ce22: 605a str r2, [r3, #4] + 800ce24: 693b ldr r3, [r7, #16] + 800ce26: 685b ldr r3, [r3, #4] + 800ce28: 68db ldr r3, [r3, #12] + 800ce2a: 4a0a ldr r2, [pc, #40] ; (800ce54 ) + 800ce2c: 6013 str r3, [r2, #0] + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + 800ce2e: 4b09 ldr r3, [pc, #36] ; (800ce54 ) + 800ce30: 681b ldr r3, [r3, #0] + 800ce32: 334c adds r3, #76 ; 0x4c + 800ce34: 4a08 ldr r2, [pc, #32] ; (800ce58 ) + 800ce36: 6013 str r3, [r2, #0] +} + 800ce38: bf00 nop + 800ce3a: 371c adds r7, #28 + 800ce3c: 46bd mov sp, r7 + 800ce3e: f85d 7b04 ldr.w r7, [sp], #4 + 800ce42: 4770 bx lr + 800ce44: 200055b0 .word 0x200055b0 + 800ce48: 2000559c .word 0x2000559c + 800ce4c: 20005590 .word 0x20005590 + 800ce50: 2000548c .word 0x2000548c + 800ce54: 20005488 .word 0x20005488 + 800ce58: 200000c4 .word 0x200000c4 + +0800ce5c : +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) +{ + 800ce5c: b580 push {r7, lr} + 800ce5e: b084 sub sp, #16 + 800ce60: af00 add r7, sp, #0 + 800ce62: 6078 str r0, [r7, #4] + 800ce64: 6039 str r1, [r7, #0] + configASSERT( pxEventList ); + 800ce66: 687b ldr r3, [r7, #4] + 800ce68: 2b00 cmp r3, #0 + 800ce6a: d10c bne.n 800ce86 + __asm volatile + 800ce6c: f04f 0350 mov.w r3, #80 ; 0x50 + 800ce70: b672 cpsid i + 800ce72: f383 8811 msr BASEPRI, r3 + 800ce76: f3bf 8f6f isb sy + 800ce7a: f3bf 8f4f dsb sy + 800ce7e: b662 cpsie i + 800ce80: 60fb str r3, [r7, #12] +} + 800ce82: bf00 nop + 800ce84: e7fe b.n 800ce84 + + /* Place the event list item of the TCB in the appropriate event list. + This is placed in the list in priority order so the highest priority task + is the first to be woken by the event. The queue that contains the event + list is locked, preventing simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 800ce86: 4b07 ldr r3, [pc, #28] ; (800cea4 ) + 800ce88: 681b ldr r3, [r3, #0] + 800ce8a: 3318 adds r3, #24 + 800ce8c: 4619 mov r1, r3 + 800ce8e: 6878 ldr r0, [r7, #4] + 800ce90: f7fe fbc1 bl 800b616 + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 800ce94: 2101 movs r1, #1 + 800ce96: 6838 ldr r0, [r7, #0] + 800ce98: f000 fba8 bl 800d5ec +} + 800ce9c: bf00 nop + 800ce9e: 3710 adds r7, #16 + 800cea0: 46bd mov sp, r7 + 800cea2: bd80 pop {r7, pc} + 800cea4: 20005488 .word 0x20005488 + +0800cea8 : + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + 800cea8: b580 push {r7, lr} + 800ceaa: b086 sub sp, #24 + 800ceac: af00 add r7, sp, #0 + 800ceae: 6078 str r0, [r7, #4] + get called - the lock count on the queue will get modified instead. This + means exclusive access to the event list is guaranteed here. + + This function assumes that a check has already been made to ensure that + pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800ceb0: 687b ldr r3, [r7, #4] + 800ceb2: 68db ldr r3, [r3, #12] + 800ceb4: 68db ldr r3, [r3, #12] + 800ceb6: 613b str r3, [r7, #16] + configASSERT( pxUnblockedTCB ); + 800ceb8: 693b ldr r3, [r7, #16] + 800ceba: 2b00 cmp r3, #0 + 800cebc: d10c bne.n 800ced8 + __asm volatile + 800cebe: f04f 0350 mov.w r3, #80 ; 0x50 + 800cec2: b672 cpsid i + 800cec4: f383 8811 msr BASEPRI, r3 + 800cec8: f3bf 8f6f isb sy + 800cecc: f3bf 8f4f dsb sy + 800ced0: b662 cpsie i + 800ced2: 60fb str r3, [r7, #12] +} + 800ced4: bf00 nop + 800ced6: e7fe b.n 800ced6 + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + 800ced8: 693b ldr r3, [r7, #16] + 800ceda: 3318 adds r3, #24 + 800cedc: 4618 mov r0, r3 + 800cede: f7fe fbd3 bl 800b688 + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800cee2: 4b1d ldr r3, [pc, #116] ; (800cf58 ) + 800cee4: 681b ldr r3, [r3, #0] + 800cee6: 2b00 cmp r3, #0 + 800cee8: d11c bne.n 800cf24 + { + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + 800ceea: 693b ldr r3, [r7, #16] + 800ceec: 3304 adds r3, #4 + 800ceee: 4618 mov r0, r3 + 800cef0: f7fe fbca bl 800b688 + prvAddTaskToReadyList( pxUnblockedTCB ); + 800cef4: 693b ldr r3, [r7, #16] + 800cef6: 6adb ldr r3, [r3, #44] ; 0x2c + 800cef8: 2201 movs r2, #1 + 800cefa: 409a lsls r2, r3 + 800cefc: 4b17 ldr r3, [pc, #92] ; (800cf5c ) + 800cefe: 681b ldr r3, [r3, #0] + 800cf00: 4313 orrs r3, r2 + 800cf02: 4a16 ldr r2, [pc, #88] ; (800cf5c ) + 800cf04: 6013 str r3, [r2, #0] + 800cf06: 693b ldr r3, [r7, #16] + 800cf08: 6ada ldr r2, [r3, #44] ; 0x2c + 800cf0a: 4613 mov r3, r2 + 800cf0c: 009b lsls r3, r3, #2 + 800cf0e: 4413 add r3, r2 + 800cf10: 009b lsls r3, r3, #2 + 800cf12: 4a13 ldr r2, [pc, #76] ; (800cf60 ) + 800cf14: 441a add r2, r3 + 800cf16: 693b ldr r3, [r7, #16] + 800cf18: 3304 adds r3, #4 + 800cf1a: 4619 mov r1, r3 + 800cf1c: 4610 mov r0, r2 + 800cf1e: f7fe fb56 bl 800b5ce + 800cf22: e005 b.n 800cf30 + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + 800cf24: 693b ldr r3, [r7, #16] + 800cf26: 3318 adds r3, #24 + 800cf28: 4619 mov r1, r3 + 800cf2a: 480e ldr r0, [pc, #56] ; (800cf64 ) + 800cf2c: f7fe fb4f bl 800b5ce + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + 800cf30: 693b ldr r3, [r7, #16] + 800cf32: 6ada ldr r2, [r3, #44] ; 0x2c + 800cf34: 4b0c ldr r3, [pc, #48] ; (800cf68 ) + 800cf36: 681b ldr r3, [r3, #0] + 800cf38: 6adb ldr r3, [r3, #44] ; 0x2c + 800cf3a: 429a cmp r2, r3 + 800cf3c: d905 bls.n 800cf4a + { + /* Return true if the task removed from the event list has a higher + priority than the calling task. This allows the calling task to know if + it should force a context switch now. */ + xReturn = pdTRUE; + 800cf3e: 2301 movs r3, #1 + 800cf40: 617b str r3, [r7, #20] + + /* Mark that a yield is pending in case the user is not using the + "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + 800cf42: 4b0a ldr r3, [pc, #40] ; (800cf6c ) + 800cf44: 2201 movs r2, #1 + 800cf46: 601a str r2, [r3, #0] + 800cf48: e001 b.n 800cf4e + } + else + { + xReturn = pdFALSE; + 800cf4a: 2300 movs r3, #0 + 800cf4c: 617b str r3, [r7, #20] + } + + return xReturn; + 800cf4e: 697b ldr r3, [r7, #20] +} + 800cf50: 4618 mov r0, r3 + 800cf52: 3718 adds r7, #24 + 800cf54: 46bd mov sp, r7 + 800cf56: bd80 pop {r7, pc} + 800cf58: 200055b0 .word 0x200055b0 + 800cf5c: 20005590 .word 0x20005590 + 800cf60: 2000548c .word 0x2000548c + 800cf64: 20005548 .word 0x20005548 + 800cf68: 20005488 .word 0x20005488 + 800cf6c: 2000559c .word 0x2000559c + +0800cf70 : + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + 800cf70: b480 push {r7} + 800cf72: b083 sub sp, #12 + 800cf74: af00 add r7, sp, #0 + 800cf76: 6078 str r0, [r7, #4] + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + 800cf78: 4b06 ldr r3, [pc, #24] ; (800cf94 ) + 800cf7a: 681a ldr r2, [r3, #0] + 800cf7c: 687b ldr r3, [r7, #4] + 800cf7e: 601a str r2, [r3, #0] + pxTimeOut->xTimeOnEntering = xTickCount; + 800cf80: 4b05 ldr r3, [pc, #20] ; (800cf98 ) + 800cf82: 681a ldr r2, [r3, #0] + 800cf84: 687b ldr r3, [r7, #4] + 800cf86: 605a str r2, [r3, #4] +} + 800cf88: bf00 nop + 800cf8a: 370c adds r7, #12 + 800cf8c: 46bd mov sp, r7 + 800cf8e: f85d 7b04 ldr.w r7, [sp], #4 + 800cf92: 4770 bx lr + 800cf94: 200055a0 .word 0x200055a0 + 800cf98: 2000558c .word 0x2000558c + +0800cf9c : +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) +{ + 800cf9c: b580 push {r7, lr} + 800cf9e: b088 sub sp, #32 + 800cfa0: af00 add r7, sp, #0 + 800cfa2: 6078 str r0, [r7, #4] + 800cfa4: 6039 str r1, [r7, #0] +BaseType_t xReturn; + + configASSERT( pxTimeOut ); + 800cfa6: 687b ldr r3, [r7, #4] + 800cfa8: 2b00 cmp r3, #0 + 800cfaa: d10c bne.n 800cfc6 + __asm volatile + 800cfac: f04f 0350 mov.w r3, #80 ; 0x50 + 800cfb0: b672 cpsid i + 800cfb2: f383 8811 msr BASEPRI, r3 + 800cfb6: f3bf 8f6f isb sy + 800cfba: f3bf 8f4f dsb sy + 800cfbe: b662 cpsie i + 800cfc0: 613b str r3, [r7, #16] +} + 800cfc2: bf00 nop + 800cfc4: e7fe b.n 800cfc4 + configASSERT( pxTicksToWait ); + 800cfc6: 683b ldr r3, [r7, #0] + 800cfc8: 2b00 cmp r3, #0 + 800cfca: d10c bne.n 800cfe6 + __asm volatile + 800cfcc: f04f 0350 mov.w r3, #80 ; 0x50 + 800cfd0: b672 cpsid i + 800cfd2: f383 8811 msr BASEPRI, r3 + 800cfd6: f3bf 8f6f isb sy + 800cfda: f3bf 8f4f dsb sy + 800cfde: b662 cpsie i + 800cfe0: 60fb str r3, [r7, #12] +} + 800cfe2: bf00 nop + 800cfe4: e7fe b.n 800cfe4 + + taskENTER_CRITICAL(); + 800cfe6: f000 fc71 bl 800d8cc + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + 800cfea: 4b1d ldr r3, [pc, #116] ; (800d060 ) + 800cfec: 681b ldr r3, [r3, #0] + 800cfee: 61bb str r3, [r7, #24] + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + 800cff0: 687b ldr r3, [r7, #4] + 800cff2: 685b ldr r3, [r3, #4] + 800cff4: 69ba ldr r2, [r7, #24] + 800cff6: 1ad3 subs r3, r2, r3 + 800cff8: 617b str r3, [r7, #20] + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + 800cffa: 683b ldr r3, [r7, #0] + 800cffc: 681b ldr r3, [r3, #0] + 800cffe: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800d002: d102 bne.n 800d00a + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + specified is the maximum block time then the task should block + indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + 800d004: 2300 movs r3, #0 + 800d006: 61fb str r3, [r7, #28] + 800d008: e023 b.n 800d052 + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + 800d00a: 687b ldr r3, [r7, #4] + 800d00c: 681a ldr r2, [r3, #0] + 800d00e: 4b15 ldr r3, [pc, #84] ; (800d064 ) + 800d010: 681b ldr r3, [r3, #0] + 800d012: 429a cmp r2, r3 + 800d014: d007 beq.n 800d026 + 800d016: 687b ldr r3, [r7, #4] + 800d018: 685b ldr r3, [r3, #4] + 800d01a: 69ba ldr r2, [r7, #24] + 800d01c: 429a cmp r2, r3 + 800d01e: d302 bcc.n 800d026 + /* The tick count is greater than the time at which + vTaskSetTimeout() was called, but has also overflowed since + vTaskSetTimeOut() was called. It must have wrapped all the way + around and gone past again. This passed since vTaskSetTimeout() + was called. */ + xReturn = pdTRUE; + 800d020: 2301 movs r3, #1 + 800d022: 61fb str r3, [r7, #28] + 800d024: e015 b.n 800d052 + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + 800d026: 683b ldr r3, [r7, #0] + 800d028: 681b ldr r3, [r3, #0] + 800d02a: 697a ldr r2, [r7, #20] + 800d02c: 429a cmp r2, r3 + 800d02e: d20b bcs.n 800d048 + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + 800d030: 683b ldr r3, [r7, #0] + 800d032: 681a ldr r2, [r3, #0] + 800d034: 697b ldr r3, [r7, #20] + 800d036: 1ad2 subs r2, r2, r3 + 800d038: 683b ldr r3, [r7, #0] + 800d03a: 601a str r2, [r3, #0] + vTaskInternalSetTimeOutState( pxTimeOut ); + 800d03c: 6878 ldr r0, [r7, #4] + 800d03e: f7ff ff97 bl 800cf70 + xReturn = pdFALSE; + 800d042: 2300 movs r3, #0 + 800d044: 61fb str r3, [r7, #28] + 800d046: e004 b.n 800d052 + } + else + { + *pxTicksToWait = 0; + 800d048: 683b ldr r3, [r7, #0] + 800d04a: 2200 movs r2, #0 + 800d04c: 601a str r2, [r3, #0] + xReturn = pdTRUE; + 800d04e: 2301 movs r3, #1 + 800d050: 61fb str r3, [r7, #28] + } + } + taskEXIT_CRITICAL(); + 800d052: f000 fc6f bl 800d934 + + return xReturn; + 800d056: 69fb ldr r3, [r7, #28] +} + 800d058: 4618 mov r0, r3 + 800d05a: 3720 adds r7, #32 + 800d05c: 46bd mov sp, r7 + 800d05e: bd80 pop {r7, pc} + 800d060: 2000558c .word 0x2000558c + 800d064: 200055a0 .word 0x200055a0 + +0800d068 : +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + 800d068: b480 push {r7} + 800d06a: af00 add r7, sp, #0 + xYieldPending = pdTRUE; + 800d06c: 4b03 ldr r3, [pc, #12] ; (800d07c ) + 800d06e: 2201 movs r2, #1 + 800d070: 601a str r2, [r3, #0] +} + 800d072: bf00 nop + 800d074: 46bd mov sp, r7 + 800d076: f85d 7b04 ldr.w r7, [sp], #4 + 800d07a: 4770 bx lr + 800d07c: 2000559c .word 0x2000559c + +0800d080 : + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + 800d080: b580 push {r7, lr} + 800d082: b082 sub sp, #8 + 800d084: af00 add r7, sp, #0 + 800d086: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + 800d088: f000 f852 bl 800d130 + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + 800d08c: 4b06 ldr r3, [pc, #24] ; (800d0a8 ) + 800d08e: 681b ldr r3, [r3, #0] + 800d090: 2b01 cmp r3, #1 + 800d092: d9f9 bls.n 800d088 + { + taskYIELD(); + 800d094: 4b05 ldr r3, [pc, #20] ; (800d0ac ) + 800d096: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800d09a: 601a str r2, [r3, #0] + 800d09c: f3bf 8f4f dsb sy + 800d0a0: f3bf 8f6f isb sy + prvCheckTasksWaitingTermination(); + 800d0a4: e7f0 b.n 800d088 + 800d0a6: bf00 nop + 800d0a8: 2000548c .word 0x2000548c + 800d0ac: e000ed04 .word 0xe000ed04 + +0800d0b0 : + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + 800d0b0: b580 push {r7, lr} + 800d0b2: b082 sub sp, #8 + 800d0b4: af00 add r7, sp, #0 +UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 800d0b6: 2300 movs r3, #0 + 800d0b8: 607b str r3, [r7, #4] + 800d0ba: e00c b.n 800d0d6 + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 800d0bc: 687a ldr r2, [r7, #4] + 800d0be: 4613 mov r3, r2 + 800d0c0: 009b lsls r3, r3, #2 + 800d0c2: 4413 add r3, r2 + 800d0c4: 009b lsls r3, r3, #2 + 800d0c6: 4a12 ldr r2, [pc, #72] ; (800d110 ) + 800d0c8: 4413 add r3, r2 + 800d0ca: 4618 mov r0, r3 + 800d0cc: f7fe fa52 bl 800b574 + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 800d0d0: 687b ldr r3, [r7, #4] + 800d0d2: 3301 adds r3, #1 + 800d0d4: 607b str r3, [r7, #4] + 800d0d6: 687b ldr r3, [r7, #4] + 800d0d8: 2b06 cmp r3, #6 + 800d0da: d9ef bls.n 800d0bc + } + + vListInitialise( &xDelayedTaskList1 ); + 800d0dc: 480d ldr r0, [pc, #52] ; (800d114 ) + 800d0de: f7fe fa49 bl 800b574 + vListInitialise( &xDelayedTaskList2 ); + 800d0e2: 480d ldr r0, [pc, #52] ; (800d118 ) + 800d0e4: f7fe fa46 bl 800b574 + vListInitialise( &xPendingReadyList ); + 800d0e8: 480c ldr r0, [pc, #48] ; (800d11c ) + 800d0ea: f7fe fa43 bl 800b574 + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + 800d0ee: 480c ldr r0, [pc, #48] ; (800d120 ) + 800d0f0: f7fe fa40 bl 800b574 + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + 800d0f4: 480b ldr r0, [pc, #44] ; (800d124 ) + 800d0f6: f7fe fa3d bl 800b574 + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + 800d0fa: 4b0b ldr r3, [pc, #44] ; (800d128 ) + 800d0fc: 4a05 ldr r2, [pc, #20] ; (800d114 ) + 800d0fe: 601a str r2, [r3, #0] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 800d100: 4b0a ldr r3, [pc, #40] ; (800d12c ) + 800d102: 4a05 ldr r2, [pc, #20] ; (800d118 ) + 800d104: 601a str r2, [r3, #0] +} + 800d106: bf00 nop + 800d108: 3708 adds r7, #8 + 800d10a: 46bd mov sp, r7 + 800d10c: bd80 pop {r7, pc} + 800d10e: bf00 nop + 800d110: 2000548c .word 0x2000548c + 800d114: 20005518 .word 0x20005518 + 800d118: 2000552c .word 0x2000552c + 800d11c: 20005548 .word 0x20005548 + 800d120: 2000555c .word 0x2000555c + 800d124: 20005574 .word 0x20005574 + 800d128: 20005540 .word 0x20005540 + 800d12c: 20005544 .word 0x20005544 + +0800d130 : +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + 800d130: b580 push {r7, lr} + 800d132: b082 sub sp, #8 + 800d134: af00 add r7, sp, #0 + { + TCB_t *pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 800d136: e019 b.n 800d16c + { + taskENTER_CRITICAL(); + 800d138: f000 fbc8 bl 800d8cc + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800d13c: 4b10 ldr r3, [pc, #64] ; (800d180 ) + 800d13e: 68db ldr r3, [r3, #12] + 800d140: 68db ldr r3, [r3, #12] + 800d142: 607b str r3, [r7, #4] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800d144: 687b ldr r3, [r7, #4] + 800d146: 3304 adds r3, #4 + 800d148: 4618 mov r0, r3 + 800d14a: f7fe fa9d bl 800b688 + --uxCurrentNumberOfTasks; + 800d14e: 4b0d ldr r3, [pc, #52] ; (800d184 ) + 800d150: 681b ldr r3, [r3, #0] + 800d152: 3b01 subs r3, #1 + 800d154: 4a0b ldr r2, [pc, #44] ; (800d184 ) + 800d156: 6013 str r3, [r2, #0] + --uxDeletedTasksWaitingCleanUp; + 800d158: 4b0b ldr r3, [pc, #44] ; (800d188 ) + 800d15a: 681b ldr r3, [r3, #0] + 800d15c: 3b01 subs r3, #1 + 800d15e: 4a0a ldr r2, [pc, #40] ; (800d188 ) + 800d160: 6013 str r3, [r2, #0] + } + taskEXIT_CRITICAL(); + 800d162: f000 fbe7 bl 800d934 + + prvDeleteTCB( pxTCB ); + 800d166: 6878 ldr r0, [r7, #4] + 800d168: f000 f810 bl 800d18c + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 800d16c: 4b06 ldr r3, [pc, #24] ; (800d188 ) + 800d16e: 681b ldr r3, [r3, #0] + 800d170: 2b00 cmp r3, #0 + 800d172: d1e1 bne.n 800d138 + } + } + #endif /* INCLUDE_vTaskDelete */ +} + 800d174: bf00 nop + 800d176: bf00 nop + 800d178: 3708 adds r7, #8 + 800d17a: 46bd mov sp, r7 + 800d17c: bd80 pop {r7, pc} + 800d17e: bf00 nop + 800d180: 2000555c .word 0x2000555c + 800d184: 20005588 .word 0x20005588 + 800d188: 20005570 .word 0x20005570 + +0800d18c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t *pxTCB ) + { + 800d18c: b580 push {r7, lr} + 800d18e: b084 sub sp, #16 + 800d190: af00 add r7, sp, #0 + 800d192: 6078 str r0, [r7, #4] + + /* Free up the memory allocated by the scheduler for the task. It is up + to the task to free any memory allocated at the application level. */ + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + _reclaim_reent( &( pxTCB->xNewLib_reent ) ); + 800d194: 687b ldr r3, [r7, #4] + 800d196: 334c adds r3, #76 ; 0x4c + 800d198: 4618 mov r0, r3 + 800d19a: f00f f815 bl 801c1c8 <_reclaim_reent> + #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + check what was statically allocated before trying to free the + memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + 800d19e: 687b ldr r3, [r7, #4] + 800d1a0: f893 30b1 ldrb.w r3, [r3, #177] ; 0xb1 + 800d1a4: 2b00 cmp r3, #0 + 800d1a6: d108 bne.n 800d1ba + { + /* Both the stack and TCB were allocated dynamically, so both + must be freed. */ + vPortFree( pxTCB->pxStack ); + 800d1a8: 687b ldr r3, [r7, #4] + 800d1aa: 6b1b ldr r3, [r3, #48] ; 0x30 + 800d1ac: 4618 mov r0, r3 + 800d1ae: f000 fd83 bl 800dcb8 + vPortFree( pxTCB ); + 800d1b2: 6878 ldr r0, [r7, #4] + 800d1b4: f000 fd80 bl 800dcb8 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + 800d1b8: e01a b.n 800d1f0 + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + 800d1ba: 687b ldr r3, [r7, #4] + 800d1bc: f893 30b1 ldrb.w r3, [r3, #177] ; 0xb1 + 800d1c0: 2b01 cmp r3, #1 + 800d1c2: d103 bne.n 800d1cc + vPortFree( pxTCB ); + 800d1c4: 6878 ldr r0, [r7, #4] + 800d1c6: f000 fd77 bl 800dcb8 + } + 800d1ca: e011 b.n 800d1f0 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + 800d1cc: 687b ldr r3, [r7, #4] + 800d1ce: f893 30b1 ldrb.w r3, [r3, #177] ; 0xb1 + 800d1d2: 2b02 cmp r3, #2 + 800d1d4: d00c beq.n 800d1f0 + __asm volatile + 800d1d6: f04f 0350 mov.w r3, #80 ; 0x50 + 800d1da: b672 cpsid i + 800d1dc: f383 8811 msr BASEPRI, r3 + 800d1e0: f3bf 8f6f isb sy + 800d1e4: f3bf 8f4f dsb sy + 800d1e8: b662 cpsie i + 800d1ea: 60fb str r3, [r7, #12] +} + 800d1ec: bf00 nop + 800d1ee: e7fe b.n 800d1ee + } + 800d1f0: bf00 nop + 800d1f2: 3710 adds r7, #16 + 800d1f4: 46bd mov sp, r7 + 800d1f6: bd80 pop {r7, pc} + +0800d1f8 : + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + 800d1f8: b480 push {r7} + 800d1fa: b083 sub sp, #12 + 800d1fc: af00 add r7, sp, #0 +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800d1fe: 4b0c ldr r3, [pc, #48] ; (800d230 ) + 800d200: 681b ldr r3, [r3, #0] + 800d202: 681b ldr r3, [r3, #0] + 800d204: 2b00 cmp r3, #0 + 800d206: d104 bne.n 800d212 + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 800d208: 4b0a ldr r3, [pc, #40] ; (800d234 ) + 800d20a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800d20e: 601a str r2, [r3, #0] + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + } +} + 800d210: e008 b.n 800d224 + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800d212: 4b07 ldr r3, [pc, #28] ; (800d230 ) + 800d214: 681b ldr r3, [r3, #0] + 800d216: 68db ldr r3, [r3, #12] + 800d218: 68db ldr r3, [r3, #12] + 800d21a: 607b str r3, [r7, #4] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 800d21c: 687b ldr r3, [r7, #4] + 800d21e: 685b ldr r3, [r3, #4] + 800d220: 4a04 ldr r2, [pc, #16] ; (800d234 ) + 800d222: 6013 str r3, [r2, #0] +} + 800d224: bf00 nop + 800d226: 370c adds r7, #12 + 800d228: 46bd mov sp, r7 + 800d22a: f85d 7b04 ldr.w r7, [sp], #4 + 800d22e: 4770 bx lr + 800d230: 20005540 .word 0x20005540 + 800d234: 200055a8 .word 0x200055a8 + +0800d238 : +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + 800d238: b480 push {r7} + 800d23a: b083 sub sp, #12 + 800d23c: af00 add r7, sp, #0 + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + 800d23e: 4b0b ldr r3, [pc, #44] ; (800d26c ) + 800d240: 681b ldr r3, [r3, #0] + 800d242: 2b00 cmp r3, #0 + 800d244: d102 bne.n 800d24c + { + xReturn = taskSCHEDULER_NOT_STARTED; + 800d246: 2301 movs r3, #1 + 800d248: 607b str r3, [r7, #4] + 800d24a: e008 b.n 800d25e + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800d24c: 4b08 ldr r3, [pc, #32] ; (800d270 ) + 800d24e: 681b ldr r3, [r3, #0] + 800d250: 2b00 cmp r3, #0 + 800d252: d102 bne.n 800d25a + { + xReturn = taskSCHEDULER_RUNNING; + 800d254: 2302 movs r3, #2 + 800d256: 607b str r3, [r7, #4] + 800d258: e001 b.n 800d25e + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + 800d25a: 2300 movs r3, #0 + 800d25c: 607b str r3, [r7, #4] + } + } + + return xReturn; + 800d25e: 687b ldr r3, [r7, #4] + } + 800d260: 4618 mov r0, r3 + 800d262: 370c adds r7, #12 + 800d264: 46bd mov sp, r7 + 800d266: f85d 7b04 ldr.w r7, [sp], #4 + 800d26a: 4770 bx lr + 800d26c: 20005594 .word 0x20005594 + 800d270: 200055b0 .word 0x200055b0 + +0800d274 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + 800d274: b580 push {r7, lr} + 800d276: b084 sub sp, #16 + 800d278: af00 add r7, sp, #0 + 800d27a: 6078 str r0, [r7, #4] + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + 800d27c: 687b ldr r3, [r7, #4] + 800d27e: 60bb str r3, [r7, #8] + BaseType_t xReturn = pdFALSE; + 800d280: 2300 movs r3, #0 + 800d282: 60fb str r3, [r7, #12] + + /* If the mutex was given back by an interrupt while the queue was + locked then the mutex holder might now be NULL. _RB_ Is this still + needed as interrupts can no longer use mutexes? */ + if( pxMutexHolder != NULL ) + 800d284: 687b ldr r3, [r7, #4] + 800d286: 2b00 cmp r3, #0 + 800d288: d069 beq.n 800d35e + { + /* If the holder of the mutex has a priority below the priority of + the task attempting to obtain the mutex then it will temporarily + inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + 800d28a: 68bb ldr r3, [r7, #8] + 800d28c: 6ada ldr r2, [r3, #44] ; 0x2c + 800d28e: 4b36 ldr r3, [pc, #216] ; (800d368 ) + 800d290: 681b ldr r3, [r3, #0] + 800d292: 6adb ldr r3, [r3, #44] ; 0x2c + 800d294: 429a cmp r2, r3 + 800d296: d259 bcs.n 800d34c + { + /* Adjust the mutex holder state to account for its new + priority. Only reset the event list item value if the value is + not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 800d298: 68bb ldr r3, [r7, #8] + 800d29a: 699b ldr r3, [r3, #24] + 800d29c: 2b00 cmp r3, #0 + 800d29e: db06 blt.n 800d2ae + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800d2a0: 4b31 ldr r3, [pc, #196] ; (800d368 ) + 800d2a2: 681b ldr r3, [r3, #0] + 800d2a4: 6adb ldr r3, [r3, #44] ; 0x2c + 800d2a6: f1c3 0207 rsb r2, r3, #7 + 800d2aa: 68bb ldr r3, [r7, #8] + 800d2ac: 619a str r2, [r3, #24] + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + 800d2ae: 68bb ldr r3, [r7, #8] + 800d2b0: 6959 ldr r1, [r3, #20] + 800d2b2: 68bb ldr r3, [r7, #8] + 800d2b4: 6ada ldr r2, [r3, #44] ; 0x2c + 800d2b6: 4613 mov r3, r2 + 800d2b8: 009b lsls r3, r3, #2 + 800d2ba: 4413 add r3, r2 + 800d2bc: 009b lsls r3, r3, #2 + 800d2be: 4a2b ldr r2, [pc, #172] ; (800d36c ) + 800d2c0: 4413 add r3, r2 + 800d2c2: 4299 cmp r1, r3 + 800d2c4: d13a bne.n 800d33c + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800d2c6: 68bb ldr r3, [r7, #8] + 800d2c8: 3304 adds r3, #4 + 800d2ca: 4618 mov r0, r3 + 800d2cc: f7fe f9dc bl 800b688 + 800d2d0: 4603 mov r3, r0 + 800d2d2: 2b00 cmp r3, #0 + 800d2d4: d115 bne.n 800d302 + { + taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority ); + 800d2d6: 68bb ldr r3, [r7, #8] + 800d2d8: 6ada ldr r2, [r3, #44] ; 0x2c + 800d2da: 4924 ldr r1, [pc, #144] ; (800d36c ) + 800d2dc: 4613 mov r3, r2 + 800d2de: 009b lsls r3, r3, #2 + 800d2e0: 4413 add r3, r2 + 800d2e2: 009b lsls r3, r3, #2 + 800d2e4: 440b add r3, r1 + 800d2e6: 681b ldr r3, [r3, #0] + 800d2e8: 2b00 cmp r3, #0 + 800d2ea: d10a bne.n 800d302 + 800d2ec: 68bb ldr r3, [r7, #8] + 800d2ee: 6adb ldr r3, [r3, #44] ; 0x2c + 800d2f0: 2201 movs r2, #1 + 800d2f2: fa02 f303 lsl.w r3, r2, r3 + 800d2f6: 43da mvns r2, r3 + 800d2f8: 4b1d ldr r3, [pc, #116] ; (800d370 ) + 800d2fa: 681b ldr r3, [r3, #0] + 800d2fc: 4013 ands r3, r2 + 800d2fe: 4a1c ldr r2, [pc, #112] ; (800d370 ) + 800d300: 6013 str r3, [r2, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + 800d302: 4b19 ldr r3, [pc, #100] ; (800d368 ) + 800d304: 681b ldr r3, [r3, #0] + 800d306: 6ada ldr r2, [r3, #44] ; 0x2c + 800d308: 68bb ldr r3, [r7, #8] + 800d30a: 62da str r2, [r3, #44] ; 0x2c + prvAddTaskToReadyList( pxMutexHolderTCB ); + 800d30c: 68bb ldr r3, [r7, #8] + 800d30e: 6adb ldr r3, [r3, #44] ; 0x2c + 800d310: 2201 movs r2, #1 + 800d312: 409a lsls r2, r3 + 800d314: 4b16 ldr r3, [pc, #88] ; (800d370 ) + 800d316: 681b ldr r3, [r3, #0] + 800d318: 4313 orrs r3, r2 + 800d31a: 4a15 ldr r2, [pc, #84] ; (800d370 ) + 800d31c: 6013 str r3, [r2, #0] + 800d31e: 68bb ldr r3, [r7, #8] + 800d320: 6ada ldr r2, [r3, #44] ; 0x2c + 800d322: 4613 mov r3, r2 + 800d324: 009b lsls r3, r3, #2 + 800d326: 4413 add r3, r2 + 800d328: 009b lsls r3, r3, #2 + 800d32a: 4a10 ldr r2, [pc, #64] ; (800d36c ) + 800d32c: 441a add r2, r3 + 800d32e: 68bb ldr r3, [r7, #8] + 800d330: 3304 adds r3, #4 + 800d332: 4619 mov r1, r3 + 800d334: 4610 mov r0, r2 + 800d336: f7fe f94a bl 800b5ce + 800d33a: e004 b.n 800d346 + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + 800d33c: 4b0a ldr r3, [pc, #40] ; (800d368 ) + 800d33e: 681b ldr r3, [r3, #0] + 800d340: 6ada ldr r2, [r3, #44] ; 0x2c + 800d342: 68bb ldr r3, [r7, #8] + 800d344: 62da str r2, [r3, #44] ; 0x2c + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + 800d346: 2301 movs r3, #1 + 800d348: 60fb str r3, [r7, #12] + 800d34a: e008 b.n 800d35e + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + 800d34c: 68bb ldr r3, [r7, #8] + 800d34e: 6c5a ldr r2, [r3, #68] ; 0x44 + 800d350: 4b05 ldr r3, [pc, #20] ; (800d368 ) + 800d352: 681b ldr r3, [r3, #0] + 800d354: 6adb ldr r3, [r3, #44] ; 0x2c + 800d356: 429a cmp r2, r3 + 800d358: d201 bcs.n 800d35e + current priority of the mutex holder is not lower than the + priority of the task attempting to take the mutex. + Therefore the mutex holder must have already inherited a + priority, but inheritance would have occurred if that had + not been the case. */ + xReturn = pdTRUE; + 800d35a: 2301 movs r3, #1 + 800d35c: 60fb str r3, [r7, #12] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 800d35e: 68fb ldr r3, [r7, #12] + } + 800d360: 4618 mov r0, r3 + 800d362: 3710 adds r7, #16 + 800d364: 46bd mov sp, r7 + 800d366: bd80 pop {r7, pc} + 800d368: 20005488 .word 0x20005488 + 800d36c: 2000548c .word 0x2000548c + 800d370: 20005590 .word 0x20005590 + +0800d374 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + 800d374: b580 push {r7, lr} + 800d376: b086 sub sp, #24 + 800d378: af00 add r7, sp, #0 + 800d37a: 6078 str r0, [r7, #4] + TCB_t * const pxTCB = pxMutexHolder; + 800d37c: 687b ldr r3, [r7, #4] + 800d37e: 613b str r3, [r7, #16] + BaseType_t xReturn = pdFALSE; + 800d380: 2300 movs r3, #0 + 800d382: 617b str r3, [r7, #20] + + if( pxMutexHolder != NULL ) + 800d384: 687b ldr r3, [r7, #4] + 800d386: 2b00 cmp r3, #0 + 800d388: d072 beq.n 800d470 + { + /* A task can only have an inherited priority if it holds the mutex. + If the mutex is held by a task then it cannot be given from an + interrupt, and if a mutex is given by the holding task then it must + be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + 800d38a: 4b3c ldr r3, [pc, #240] ; (800d47c ) + 800d38c: 681b ldr r3, [r3, #0] + 800d38e: 693a ldr r2, [r7, #16] + 800d390: 429a cmp r2, r3 + 800d392: d00c beq.n 800d3ae + __asm volatile + 800d394: f04f 0350 mov.w r3, #80 ; 0x50 + 800d398: b672 cpsid i + 800d39a: f383 8811 msr BASEPRI, r3 + 800d39e: f3bf 8f6f isb sy + 800d3a2: f3bf 8f4f dsb sy + 800d3a6: b662 cpsie i + 800d3a8: 60fb str r3, [r7, #12] +} + 800d3aa: bf00 nop + 800d3ac: e7fe b.n 800d3ac + configASSERT( pxTCB->uxMutexesHeld ); + 800d3ae: 693b ldr r3, [r7, #16] + 800d3b0: 6c9b ldr r3, [r3, #72] ; 0x48 + 800d3b2: 2b00 cmp r3, #0 + 800d3b4: d10c bne.n 800d3d0 + __asm volatile + 800d3b6: f04f 0350 mov.w r3, #80 ; 0x50 + 800d3ba: b672 cpsid i + 800d3bc: f383 8811 msr BASEPRI, r3 + 800d3c0: f3bf 8f6f isb sy + 800d3c4: f3bf 8f4f dsb sy + 800d3c8: b662 cpsie i + 800d3ca: 60bb str r3, [r7, #8] +} + 800d3cc: bf00 nop + 800d3ce: e7fe b.n 800d3ce + ( pxTCB->uxMutexesHeld )--; + 800d3d0: 693b ldr r3, [r7, #16] + 800d3d2: 6c9b ldr r3, [r3, #72] ; 0x48 + 800d3d4: 1e5a subs r2, r3, #1 + 800d3d6: 693b ldr r3, [r7, #16] + 800d3d8: 649a str r2, [r3, #72] ; 0x48 + + /* Has the holder of the mutex inherited the priority of another + task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 800d3da: 693b ldr r3, [r7, #16] + 800d3dc: 6ada ldr r2, [r3, #44] ; 0x2c + 800d3de: 693b ldr r3, [r7, #16] + 800d3e0: 6c5b ldr r3, [r3, #68] ; 0x44 + 800d3e2: 429a cmp r2, r3 + 800d3e4: d044 beq.n 800d470 + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + 800d3e6: 693b ldr r3, [r7, #16] + 800d3e8: 6c9b ldr r3, [r3, #72] ; 0x48 + 800d3ea: 2b00 cmp r3, #0 + 800d3ec: d140 bne.n 800d470 + /* A task can only have an inherited priority if it holds + the mutex. If the mutex is held by a task then it cannot be + given from an interrupt, and if a mutex is given by the + holding task then it must be the running state task. Remove + the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800d3ee: 693b ldr r3, [r7, #16] + 800d3f0: 3304 adds r3, #4 + 800d3f2: 4618 mov r0, r3 + 800d3f4: f7fe f948 bl 800b688 + 800d3f8: 4603 mov r3, r0 + 800d3fa: 2b00 cmp r3, #0 + 800d3fc: d115 bne.n 800d42a + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + 800d3fe: 693b ldr r3, [r7, #16] + 800d400: 6ada ldr r2, [r3, #44] ; 0x2c + 800d402: 491f ldr r1, [pc, #124] ; (800d480 ) + 800d404: 4613 mov r3, r2 + 800d406: 009b lsls r3, r3, #2 + 800d408: 4413 add r3, r2 + 800d40a: 009b lsls r3, r3, #2 + 800d40c: 440b add r3, r1 + 800d40e: 681b ldr r3, [r3, #0] + 800d410: 2b00 cmp r3, #0 + 800d412: d10a bne.n 800d42a + 800d414: 693b ldr r3, [r7, #16] + 800d416: 6adb ldr r3, [r3, #44] ; 0x2c + 800d418: 2201 movs r2, #1 + 800d41a: fa02 f303 lsl.w r3, r2, r3 + 800d41e: 43da mvns r2, r3 + 800d420: 4b18 ldr r3, [pc, #96] ; (800d484 ) + 800d422: 681b ldr r3, [r3, #0] + 800d424: 4013 ands r3, r2 + 800d426: 4a17 ldr r2, [pc, #92] ; (800d484 ) + 800d428: 6013 str r3, [r2, #0] + } + + /* Disinherit the priority before adding the task into the + new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + 800d42a: 693b ldr r3, [r7, #16] + 800d42c: 6c5a ldr r2, [r3, #68] ; 0x44 + 800d42e: 693b ldr r3, [r7, #16] + 800d430: 62da str r2, [r3, #44] ; 0x2c + + /* Reset the event list item value. It cannot be in use for + any other purpose if this task is running, and it must be + running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800d432: 693b ldr r3, [r7, #16] + 800d434: 6adb ldr r3, [r3, #44] ; 0x2c + 800d436: f1c3 0207 rsb r2, r3, #7 + 800d43a: 693b ldr r3, [r7, #16] + 800d43c: 619a str r2, [r3, #24] + prvAddTaskToReadyList( pxTCB ); + 800d43e: 693b ldr r3, [r7, #16] + 800d440: 6adb ldr r3, [r3, #44] ; 0x2c + 800d442: 2201 movs r2, #1 + 800d444: 409a lsls r2, r3 + 800d446: 4b0f ldr r3, [pc, #60] ; (800d484 ) + 800d448: 681b ldr r3, [r3, #0] + 800d44a: 4313 orrs r3, r2 + 800d44c: 4a0d ldr r2, [pc, #52] ; (800d484 ) + 800d44e: 6013 str r3, [r2, #0] + 800d450: 693b ldr r3, [r7, #16] + 800d452: 6ada ldr r2, [r3, #44] ; 0x2c + 800d454: 4613 mov r3, r2 + 800d456: 009b lsls r3, r3, #2 + 800d458: 4413 add r3, r2 + 800d45a: 009b lsls r3, r3, #2 + 800d45c: 4a08 ldr r2, [pc, #32] ; (800d480 ) + 800d45e: 441a add r2, r3 + 800d460: 693b ldr r3, [r7, #16] + 800d462: 3304 adds r3, #4 + 800d464: 4619 mov r1, r3 + 800d466: 4610 mov r0, r2 + 800d468: f7fe f8b1 bl 800b5ce + in an order different to that in which they were taken. + If a context switch did not occur when the first mutex was + returned, even if a task was waiting on it, then a context + switch should occur when the last mutex is returned whether + a task is waiting on it or not. */ + xReturn = pdTRUE; + 800d46c: 2301 movs r3, #1 + 800d46e: 617b str r3, [r7, #20] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + 800d470: 697b ldr r3, [r7, #20] + } + 800d472: 4618 mov r0, r3 + 800d474: 3718 adds r7, #24 + 800d476: 46bd mov sp, r7 + 800d478: bd80 pop {r7, pc} + 800d47a: bf00 nop + 800d47c: 20005488 .word 0x20005488 + 800d480: 2000548c .word 0x2000548c + 800d484: 20005590 .word 0x20005590 + +0800d488 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) + { + 800d488: b580 push {r7, lr} + 800d48a: b088 sub sp, #32 + 800d48c: af00 add r7, sp, #0 + 800d48e: 6078 str r0, [r7, #4] + 800d490: 6039 str r1, [r7, #0] + TCB_t * const pxTCB = pxMutexHolder; + 800d492: 687b ldr r3, [r7, #4] + 800d494: 61bb str r3, [r7, #24] + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + 800d496: 2301 movs r3, #1 + 800d498: 617b str r3, [r7, #20] + + if( pxMutexHolder != NULL ) + 800d49a: 687b ldr r3, [r7, #4] + 800d49c: 2b00 cmp r3, #0 + 800d49e: f000 8087 beq.w 800d5b0 + { + /* If pxMutexHolder is not NULL then the holder must hold at least + one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + 800d4a2: 69bb ldr r3, [r7, #24] + 800d4a4: 6c9b ldr r3, [r3, #72] ; 0x48 + 800d4a6: 2b00 cmp r3, #0 + 800d4a8: d10c bne.n 800d4c4 + __asm volatile + 800d4aa: f04f 0350 mov.w r3, #80 ; 0x50 + 800d4ae: b672 cpsid i + 800d4b0: f383 8811 msr BASEPRI, r3 + 800d4b4: f3bf 8f6f isb sy + 800d4b8: f3bf 8f4f dsb sy + 800d4bc: b662 cpsie i + 800d4be: 60fb str r3, [r7, #12] +} + 800d4c0: bf00 nop + 800d4c2: e7fe b.n 800d4c2 + + /* Determine the priority to which the priority of the task that + holds the mutex should be set. This will be the greater of the + holding task's base priority and the priority of the highest + priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + 800d4c4: 69bb ldr r3, [r7, #24] + 800d4c6: 6c5b ldr r3, [r3, #68] ; 0x44 + 800d4c8: 683a ldr r2, [r7, #0] + 800d4ca: 429a cmp r2, r3 + 800d4cc: d902 bls.n 800d4d4 + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + 800d4ce: 683b ldr r3, [r7, #0] + 800d4d0: 61fb str r3, [r7, #28] + 800d4d2: e002 b.n 800d4da + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + 800d4d4: 69bb ldr r3, [r7, #24] + 800d4d6: 6c5b ldr r3, [r3, #68] ; 0x44 + 800d4d8: 61fb str r3, [r7, #28] + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + 800d4da: 69bb ldr r3, [r7, #24] + 800d4dc: 6adb ldr r3, [r3, #44] ; 0x2c + 800d4de: 69fa ldr r2, [r7, #28] + 800d4e0: 429a cmp r2, r3 + 800d4e2: d065 beq.n 800d5b0 + { + /* Only disinherit if no other mutexes are held. This is a + simplification in the priority inheritance implementation. If + the task that holds the mutex is also holding other mutexes then + the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + 800d4e4: 69bb ldr r3, [r7, #24] + 800d4e6: 6c9b ldr r3, [r3, #72] ; 0x48 + 800d4e8: 697a ldr r2, [r7, #20] + 800d4ea: 429a cmp r2, r3 + 800d4ec: d160 bne.n 800d5b0 + { + /* If a task has timed out because it already holds the + mutex it was trying to obtain then it cannot of inherited + its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + 800d4ee: 4b32 ldr r3, [pc, #200] ; (800d5b8 ) + 800d4f0: 681b ldr r3, [r3, #0] + 800d4f2: 69ba ldr r2, [r7, #24] + 800d4f4: 429a cmp r2, r3 + 800d4f6: d10c bne.n 800d512 + __asm volatile + 800d4f8: f04f 0350 mov.w r3, #80 ; 0x50 + 800d4fc: b672 cpsid i + 800d4fe: f383 8811 msr BASEPRI, r3 + 800d502: f3bf 8f6f isb sy + 800d506: f3bf 8f4f dsb sy + 800d50a: b662 cpsie i + 800d50c: 60bb str r3, [r7, #8] +} + 800d50e: bf00 nop + 800d510: e7fe b.n 800d510 + + /* Disinherit the priority, remembering the previous + priority to facilitate determining the subject task's + state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + 800d512: 69bb ldr r3, [r7, #24] + 800d514: 6adb ldr r3, [r3, #44] ; 0x2c + 800d516: 613b str r3, [r7, #16] + pxTCB->uxPriority = uxPriorityToUse; + 800d518: 69bb ldr r3, [r7, #24] + 800d51a: 69fa ldr r2, [r7, #28] + 800d51c: 62da str r2, [r3, #44] ; 0x2c + + /* Only reset the event list item value if the value is not + being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 800d51e: 69bb ldr r3, [r7, #24] + 800d520: 699b ldr r3, [r3, #24] + 800d522: 2b00 cmp r3, #0 + 800d524: db04 blt.n 800d530 + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800d526: 69fb ldr r3, [r7, #28] + 800d528: f1c3 0207 rsb r2, r3, #7 + 800d52c: 69bb ldr r3, [r7, #24] + 800d52e: 619a str r2, [r3, #24] + then the task that holds the mutex could be in either the + Ready, Blocked or Suspended states. Only remove the task + from its current state list if it is in the Ready state as + the task's priority is going to change and there is one + Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + 800d530: 69bb ldr r3, [r7, #24] + 800d532: 6959 ldr r1, [r3, #20] + 800d534: 693a ldr r2, [r7, #16] + 800d536: 4613 mov r3, r2 + 800d538: 009b lsls r3, r3, #2 + 800d53a: 4413 add r3, r2 + 800d53c: 009b lsls r3, r3, #2 + 800d53e: 4a1f ldr r2, [pc, #124] ; (800d5bc ) + 800d540: 4413 add r3, r2 + 800d542: 4299 cmp r1, r3 + 800d544: d134 bne.n 800d5b0 + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800d546: 69bb ldr r3, [r7, #24] + 800d548: 3304 adds r3, #4 + 800d54a: 4618 mov r0, r3 + 800d54c: f7fe f89c bl 800b688 + 800d550: 4603 mov r3, r0 + 800d552: 2b00 cmp r3, #0 + 800d554: d115 bne.n 800d582 + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + 800d556: 69bb ldr r3, [r7, #24] + 800d558: 6ada ldr r2, [r3, #44] ; 0x2c + 800d55a: 4918 ldr r1, [pc, #96] ; (800d5bc ) + 800d55c: 4613 mov r3, r2 + 800d55e: 009b lsls r3, r3, #2 + 800d560: 4413 add r3, r2 + 800d562: 009b lsls r3, r3, #2 + 800d564: 440b add r3, r1 + 800d566: 681b ldr r3, [r3, #0] + 800d568: 2b00 cmp r3, #0 + 800d56a: d10a bne.n 800d582 + 800d56c: 69bb ldr r3, [r7, #24] + 800d56e: 6adb ldr r3, [r3, #44] ; 0x2c + 800d570: 2201 movs r2, #1 + 800d572: fa02 f303 lsl.w r3, r2, r3 + 800d576: 43da mvns r2, r3 + 800d578: 4b11 ldr r3, [pc, #68] ; (800d5c0 ) + 800d57a: 681b ldr r3, [r3, #0] + 800d57c: 4013 ands r3, r2 + 800d57e: 4a10 ldr r2, [pc, #64] ; (800d5c0 ) + 800d580: 6013 str r3, [r2, #0] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + 800d582: 69bb ldr r3, [r7, #24] + 800d584: 6adb ldr r3, [r3, #44] ; 0x2c + 800d586: 2201 movs r2, #1 + 800d588: 409a lsls r2, r3 + 800d58a: 4b0d ldr r3, [pc, #52] ; (800d5c0 ) + 800d58c: 681b ldr r3, [r3, #0] + 800d58e: 4313 orrs r3, r2 + 800d590: 4a0b ldr r2, [pc, #44] ; (800d5c0 ) + 800d592: 6013 str r3, [r2, #0] + 800d594: 69bb ldr r3, [r7, #24] + 800d596: 6ada ldr r2, [r3, #44] ; 0x2c + 800d598: 4613 mov r3, r2 + 800d59a: 009b lsls r3, r3, #2 + 800d59c: 4413 add r3, r2 + 800d59e: 009b lsls r3, r3, #2 + 800d5a0: 4a06 ldr r2, [pc, #24] ; (800d5bc ) + 800d5a2: 441a add r2, r3 + 800d5a4: 69bb ldr r3, [r7, #24] + 800d5a6: 3304 adds r3, #4 + 800d5a8: 4619 mov r1, r3 + 800d5aa: 4610 mov r0, r2 + 800d5ac: f7fe f80f bl 800b5ce + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 800d5b0: bf00 nop + 800d5b2: 3720 adds r7, #32 + 800d5b4: 46bd mov sp, r7 + 800d5b6: bd80 pop {r7, pc} + 800d5b8: 20005488 .word 0x20005488 + 800d5bc: 2000548c .word 0x2000548c + 800d5c0: 20005590 .word 0x20005590 + +0800d5c4 : +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + 800d5c4: b480 push {r7} + 800d5c6: af00 add r7, sp, #0 + /* If xSemaphoreCreateMutex() is called before any tasks have been created + then pxCurrentTCB will be NULL. */ + if( pxCurrentTCB != NULL ) + 800d5c8: 4b07 ldr r3, [pc, #28] ; (800d5e8 ) + 800d5ca: 681b ldr r3, [r3, #0] + 800d5cc: 2b00 cmp r3, #0 + 800d5ce: d004 beq.n 800d5da + { + ( pxCurrentTCB->uxMutexesHeld )++; + 800d5d0: 4b05 ldr r3, [pc, #20] ; (800d5e8 ) + 800d5d2: 681b ldr r3, [r3, #0] + 800d5d4: 6c9a ldr r2, [r3, #72] ; 0x48 + 800d5d6: 3201 adds r2, #1 + 800d5d8: 649a str r2, [r3, #72] ; 0x48 + } + + return pxCurrentTCB; + 800d5da: 4b03 ldr r3, [pc, #12] ; (800d5e8 ) + 800d5dc: 681b ldr r3, [r3, #0] + } + 800d5de: 4618 mov r0, r3 + 800d5e0: 46bd mov sp, r7 + 800d5e2: f85d 7b04 ldr.w r7, [sp], #4 + 800d5e6: 4770 bx lr + 800d5e8: 20005488 .word 0x20005488 + +0800d5ec : + } +#endif +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 800d5ec: b580 push {r7, lr} + 800d5ee: b084 sub sp, #16 + 800d5f0: af00 add r7, sp, #0 + 800d5f2: 6078 str r0, [r7, #4] + 800d5f4: 6039 str r1, [r7, #0] +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 800d5f6: 4b29 ldr r3, [pc, #164] ; (800d69c ) + 800d5f8: 681b ldr r3, [r3, #0] + 800d5fa: 60fb str r3, [r7, #12] + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800d5fc: 4b28 ldr r3, [pc, #160] ; (800d6a0 ) + 800d5fe: 681b ldr r3, [r3, #0] + 800d600: 3304 adds r3, #4 + 800d602: 4618 mov r0, r3 + 800d604: f7fe f840 bl 800b688 + 800d608: 4603 mov r3, r0 + 800d60a: 2b00 cmp r3, #0 + 800d60c: d10b bne.n 800d626 + { + /* The current task must be in a ready list, so there is no need to + check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + 800d60e: 4b24 ldr r3, [pc, #144] ; (800d6a0 ) + 800d610: 681b ldr r3, [r3, #0] + 800d612: 6adb ldr r3, [r3, #44] ; 0x2c + 800d614: 2201 movs r2, #1 + 800d616: fa02 f303 lsl.w r3, r2, r3 + 800d61a: 43da mvns r2, r3 + 800d61c: 4b21 ldr r3, [pc, #132] ; (800d6a4 ) + 800d61e: 681b ldr r3, [r3, #0] + 800d620: 4013 ands r3, r2 + 800d622: 4a20 ldr r2, [pc, #128] ; (800d6a4 ) + 800d624: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 800d626: 687b ldr r3, [r7, #4] + 800d628: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800d62c: d10a bne.n 800d644 + 800d62e: 683b ldr r3, [r7, #0] + 800d630: 2b00 cmp r3, #0 + 800d632: d007 beq.n 800d644 + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800d634: 4b1a ldr r3, [pc, #104] ; (800d6a0 ) + 800d636: 681b ldr r3, [r3, #0] + 800d638: 3304 adds r3, #4 + 800d63a: 4619 mov r1, r3 + 800d63c: 481a ldr r0, [pc, #104] ; (800d6a8 ) + 800d63e: f7fd ffc6 bl 800b5ce + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 800d642: e026 b.n 800d692 + xTimeToWake = xConstTickCount + xTicksToWait; + 800d644: 68fa ldr r2, [r7, #12] + 800d646: 687b ldr r3, [r7, #4] + 800d648: 4413 add r3, r2 + 800d64a: 60bb str r3, [r7, #8] + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 800d64c: 4b14 ldr r3, [pc, #80] ; (800d6a0 ) + 800d64e: 681b ldr r3, [r3, #0] + 800d650: 68ba ldr r2, [r7, #8] + 800d652: 605a str r2, [r3, #4] + if( xTimeToWake < xConstTickCount ) + 800d654: 68ba ldr r2, [r7, #8] + 800d656: 68fb ldr r3, [r7, #12] + 800d658: 429a cmp r2, r3 + 800d65a: d209 bcs.n 800d670 + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800d65c: 4b13 ldr r3, [pc, #76] ; (800d6ac ) + 800d65e: 681a ldr r2, [r3, #0] + 800d660: 4b0f ldr r3, [pc, #60] ; (800d6a0 ) + 800d662: 681b ldr r3, [r3, #0] + 800d664: 3304 adds r3, #4 + 800d666: 4619 mov r1, r3 + 800d668: 4610 mov r0, r2 + 800d66a: f7fd ffd4 bl 800b616 +} + 800d66e: e010 b.n 800d692 + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800d670: 4b0f ldr r3, [pc, #60] ; (800d6b0 ) + 800d672: 681a ldr r2, [r3, #0] + 800d674: 4b0a ldr r3, [pc, #40] ; (800d6a0 ) + 800d676: 681b ldr r3, [r3, #0] + 800d678: 3304 adds r3, #4 + 800d67a: 4619 mov r1, r3 + 800d67c: 4610 mov r0, r2 + 800d67e: f7fd ffca bl 800b616 + if( xTimeToWake < xNextTaskUnblockTime ) + 800d682: 4b0c ldr r3, [pc, #48] ; (800d6b4 ) + 800d684: 681b ldr r3, [r3, #0] + 800d686: 68ba ldr r2, [r7, #8] + 800d688: 429a cmp r2, r3 + 800d68a: d202 bcs.n 800d692 + xNextTaskUnblockTime = xTimeToWake; + 800d68c: 4a09 ldr r2, [pc, #36] ; (800d6b4 ) + 800d68e: 68bb ldr r3, [r7, #8] + 800d690: 6013 str r3, [r2, #0] +} + 800d692: bf00 nop + 800d694: 3710 adds r7, #16 + 800d696: 46bd mov sp, r7 + 800d698: bd80 pop {r7, pc} + 800d69a: bf00 nop + 800d69c: 2000558c .word 0x2000558c + 800d6a0: 20005488 .word 0x20005488 + 800d6a4: 20005590 .word 0x20005590 + 800d6a8: 20005574 .word 0x20005574 + 800d6ac: 20005544 .word 0x20005544 + 800d6b0: 20005540 .word 0x20005540 + 800d6b4: 200055a8 .word 0x200055a8 + +0800d6b8 : + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + 800d6b8: b480 push {r7} + 800d6ba: b085 sub sp, #20 + 800d6bc: af00 add r7, sp, #0 + 800d6be: 60f8 str r0, [r7, #12] + 800d6c0: 60b9 str r1, [r7, #8] + 800d6c2: 607a str r2, [r7, #4] + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + 800d6c4: 68fb ldr r3, [r7, #12] + 800d6c6: 3b04 subs r3, #4 + 800d6c8: 60fb str r3, [r7, #12] + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 800d6ca: 68fb ldr r3, [r7, #12] + 800d6cc: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 800d6d0: 601a str r2, [r3, #0] + pxTopOfStack--; + 800d6d2: 68fb ldr r3, [r7, #12] + 800d6d4: 3b04 subs r3, #4 + 800d6d6: 60fb str r3, [r7, #12] + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 800d6d8: 68bb ldr r3, [r7, #8] + 800d6da: f023 0201 bic.w r2, r3, #1 + 800d6de: 68fb ldr r3, [r7, #12] + 800d6e0: 601a str r2, [r3, #0] + pxTopOfStack--; + 800d6e2: 68fb ldr r3, [r7, #12] + 800d6e4: 3b04 subs r3, #4 + 800d6e6: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 800d6e8: 4a0c ldr r2, [pc, #48] ; (800d71c ) + 800d6ea: 68fb ldr r3, [r7, #12] + 800d6ec: 601a str r2, [r3, #0] + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + 800d6ee: 68fb ldr r3, [r7, #12] + 800d6f0: 3b14 subs r3, #20 + 800d6f2: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 800d6f4: 687a ldr r2, [r7, #4] + 800d6f6: 68fb ldr r3, [r7, #12] + 800d6f8: 601a str r2, [r3, #0] + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + 800d6fa: 68fb ldr r3, [r7, #12] + 800d6fc: 3b04 subs r3, #4 + 800d6fe: 60fb str r3, [r7, #12] + *pxTopOfStack = portINITIAL_EXC_RETURN; + 800d700: 68fb ldr r3, [r7, #12] + 800d702: f06f 0202 mvn.w r2, #2 + 800d706: 601a str r2, [r3, #0] + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + 800d708: 68fb ldr r3, [r7, #12] + 800d70a: 3b20 subs r3, #32 + 800d70c: 60fb str r3, [r7, #12] + + return pxTopOfStack; + 800d70e: 68fb ldr r3, [r7, #12] +} + 800d710: 4618 mov r0, r3 + 800d712: 3714 adds r7, #20 + 800d714: 46bd mov sp, r7 + 800d716: f85d 7b04 ldr.w r7, [sp], #4 + 800d71a: 4770 bx lr + 800d71c: 0800d721 .word 0x0800d721 + +0800d720 : +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + 800d720: b480 push {r7} + 800d722: b085 sub sp, #20 + 800d724: af00 add r7, sp, #0 +volatile uint32_t ulDummy = 0; + 800d726: 2300 movs r3, #0 + 800d728: 607b str r3, [r7, #4] + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 800d72a: 4b14 ldr r3, [pc, #80] ; (800d77c ) + 800d72c: 681b ldr r3, [r3, #0] + 800d72e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800d732: d00c beq.n 800d74e + __asm volatile + 800d734: f04f 0350 mov.w r3, #80 ; 0x50 + 800d738: b672 cpsid i + 800d73a: f383 8811 msr BASEPRI, r3 + 800d73e: f3bf 8f6f isb sy + 800d742: f3bf 8f4f dsb sy + 800d746: b662 cpsie i + 800d748: 60fb str r3, [r7, #12] +} + 800d74a: bf00 nop + 800d74c: e7fe b.n 800d74c + __asm volatile + 800d74e: f04f 0350 mov.w r3, #80 ; 0x50 + 800d752: b672 cpsid i + 800d754: f383 8811 msr BASEPRI, r3 + 800d758: f3bf 8f6f isb sy + 800d75c: f3bf 8f4f dsb sy + 800d760: b662 cpsie i + 800d762: 60bb str r3, [r7, #8] +} + 800d764: bf00 nop + portDISABLE_INTERRUPTS(); + while( ulDummy == 0 ) + 800d766: bf00 nop + 800d768: 687b ldr r3, [r7, #4] + 800d76a: 2b00 cmp r3, #0 + 800d76c: d0fc beq.n 800d768 + about code appearing after this function is called - making ulDummy + volatile makes the compiler think the function could return and + therefore not output an 'unreachable code' warning for code that appears + after it. */ + } +} + 800d76e: bf00 nop + 800d770: bf00 nop + 800d772: 3714 adds r7, #20 + 800d774: 46bd mov sp, r7 + 800d776: f85d 7b04 ldr.w r7, [sp], #4 + 800d77a: 4770 bx lr + 800d77c: 200000b0 .word 0x200000b0 + +0800d780 : +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + 800d780: 4b07 ldr r3, [pc, #28] ; (800d7a0 ) + 800d782: 6819 ldr r1, [r3, #0] + 800d784: 6808 ldr r0, [r1, #0] + 800d786: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d78a: f380 8809 msr PSP, r0 + 800d78e: f3bf 8f6f isb sy + 800d792: f04f 0000 mov.w r0, #0 + 800d796: f380 8811 msr BASEPRI, r0 + 800d79a: 4770 bx lr + 800d79c: f3af 8000 nop.w + +0800d7a0 : + 800d7a0: 20005488 .word 0x20005488 + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} + 800d7a4: bf00 nop + 800d7a6: bf00 nop + +0800d7a8 : +{ + /* Start the first task. This also clears the bit that indicates the FPU is + in use in case the FPU was used before the scheduler was started - which + would otherwise result in the unnecessary leaving of space in the SVC stack + for lazy saving of FPU registers. */ + __asm volatile( + 800d7a8: 4808 ldr r0, [pc, #32] ; (800d7cc ) + 800d7aa: 6800 ldr r0, [r0, #0] + 800d7ac: 6800 ldr r0, [r0, #0] + 800d7ae: f380 8808 msr MSP, r0 + 800d7b2: f04f 0000 mov.w r0, #0 + 800d7b6: f380 8814 msr CONTROL, r0 + 800d7ba: b662 cpsie i + 800d7bc: b661 cpsie f + 800d7be: f3bf 8f4f dsb sy + 800d7c2: f3bf 8f6f isb sy + 800d7c6: df00 svc 0 + 800d7c8: bf00 nop + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + ); +} + 800d7ca: bf00 nop + 800d7cc: e000ed08 .word 0xe000ed08 + +0800d7d0 : + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + 800d7d0: b580 push {r7, lr} + 800d7d2: b084 sub sp, #16 + 800d7d4: af00 add r7, sp, #0 + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + 800d7d6: 4b37 ldr r3, [pc, #220] ; (800d8b4 ) + 800d7d8: 60fb str r3, [r7, #12] + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + 800d7da: 68fb ldr r3, [r7, #12] + 800d7dc: 781b ldrb r3, [r3, #0] + 800d7de: b2db uxtb r3, r3 + 800d7e0: 607b str r3, [r7, #4] + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + 800d7e2: 68fb ldr r3, [r7, #12] + 800d7e4: 22ff movs r2, #255 ; 0xff + 800d7e6: 701a strb r2, [r3, #0] + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + 800d7e8: 68fb ldr r3, [r7, #12] + 800d7ea: 781b ldrb r3, [r3, #0] + 800d7ec: b2db uxtb r3, r3 + 800d7ee: 70fb strb r3, [r7, #3] + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + 800d7f0: 78fb ldrb r3, [r7, #3] + 800d7f2: b2db uxtb r3, r3 + 800d7f4: f003 0350 and.w r3, r3, #80 ; 0x50 + 800d7f8: b2da uxtb r2, r3 + 800d7fa: 4b2f ldr r3, [pc, #188] ; (800d8b8 ) + 800d7fc: 701a strb r2, [r3, #0] + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + 800d7fe: 4b2f ldr r3, [pc, #188] ; (800d8bc ) + 800d800: 2207 movs r2, #7 + 800d802: 601a str r2, [r3, #0] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 800d804: e009 b.n 800d81a + { + ulMaxPRIGROUPValue--; + 800d806: 4b2d ldr r3, [pc, #180] ; (800d8bc ) + 800d808: 681b ldr r3, [r3, #0] + 800d80a: 3b01 subs r3, #1 + 800d80c: 4a2b ldr r2, [pc, #172] ; (800d8bc ) + 800d80e: 6013 str r3, [r2, #0] + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + 800d810: 78fb ldrb r3, [r7, #3] + 800d812: b2db uxtb r3, r3 + 800d814: 005b lsls r3, r3, #1 + 800d816: b2db uxtb r3, r3 + 800d818: 70fb strb r3, [r7, #3] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 800d81a: 78fb ldrb r3, [r7, #3] + 800d81c: b2db uxtb r3, r3 + 800d81e: f003 0380 and.w r3, r3, #128 ; 0x80 + 800d822: 2b80 cmp r3, #128 ; 0x80 + 800d824: d0ef beq.n 800d806 + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + 800d826: 4b25 ldr r3, [pc, #148] ; (800d8bc ) + 800d828: 681b ldr r3, [r3, #0] + 800d82a: f1c3 0307 rsb r3, r3, #7 + 800d82e: 2b04 cmp r3, #4 + 800d830: d00c beq.n 800d84c + __asm volatile + 800d832: f04f 0350 mov.w r3, #80 ; 0x50 + 800d836: b672 cpsid i + 800d838: f383 8811 msr BASEPRI, r3 + 800d83c: f3bf 8f6f isb sy + 800d840: f3bf 8f4f dsb sy + 800d844: b662 cpsie i + 800d846: 60bb str r3, [r7, #8] +} + 800d848: bf00 nop + 800d84a: e7fe b.n 800d84a + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + 800d84c: 4b1b ldr r3, [pc, #108] ; (800d8bc ) + 800d84e: 681b ldr r3, [r3, #0] + 800d850: 021b lsls r3, r3, #8 + 800d852: 4a1a ldr r2, [pc, #104] ; (800d8bc ) + 800d854: 6013 str r3, [r2, #0] + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + 800d856: 4b19 ldr r3, [pc, #100] ; (800d8bc ) + 800d858: 681b ldr r3, [r3, #0] + 800d85a: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 800d85e: 4a17 ldr r2, [pc, #92] ; (800d8bc ) + 800d860: 6013 str r3, [r2, #0] + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + 800d862: 687b ldr r3, [r7, #4] + 800d864: b2da uxtb r2, r3 + 800d866: 68fb ldr r3, [r7, #12] + 800d868: 701a strb r2, [r3, #0] + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + 800d86a: 4b15 ldr r3, [pc, #84] ; (800d8c0 ) + 800d86c: 681b ldr r3, [r3, #0] + 800d86e: 4a14 ldr r2, [pc, #80] ; (800d8c0 ) + 800d870: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 800d874: 6013 str r3, [r2, #0] + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + 800d876: 4b12 ldr r3, [pc, #72] ; (800d8c0 ) + 800d878: 681b ldr r3, [r3, #0] + 800d87a: 4a11 ldr r2, [pc, #68] ; (800d8c0 ) + 800d87c: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000 + 800d880: 6013 str r3, [r2, #0] + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + 800d882: f000 f8dd bl 800da40 + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + 800d886: 4b0f ldr r3, [pc, #60] ; (800d8c4 ) + 800d888: 2200 movs r2, #0 + 800d88a: 601a str r2, [r3, #0] + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + 800d88c: f000 f8fc bl 800da88 + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + 800d890: 4b0d ldr r3, [pc, #52] ; (800d8c8 ) + 800d892: 681b ldr r3, [r3, #0] + 800d894: 4a0c ldr r2, [pc, #48] ; (800d8c8 ) + 800d896: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000 + 800d89a: 6013 str r3, [r2, #0] + + /* Start the first task. */ + prvPortStartFirstTask(); + 800d89c: f7ff ff84 bl 800d7a8 + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. Call + vTaskSwitchContext() so link time optimisation does not remove the + symbol. */ + vTaskSwitchContext(); + 800d8a0: f7ff fa78 bl 800cd94 + prvTaskExitError(); + 800d8a4: f7ff ff3c bl 800d720 + + /* Should not get here! */ + return 0; + 800d8a8: 2300 movs r3, #0 +} + 800d8aa: 4618 mov r0, r3 + 800d8ac: 3710 adds r7, #16 + 800d8ae: 46bd mov sp, r7 + 800d8b0: bd80 pop {r7, pc} + 800d8b2: bf00 nop + 800d8b4: e000e400 .word 0xe000e400 + 800d8b8: 200055b4 .word 0x200055b4 + 800d8bc: 200055b8 .word 0x200055b8 + 800d8c0: e000ed20 .word 0xe000ed20 + 800d8c4: 200000b0 .word 0x200000b0 + 800d8c8: e000ef34 .word 0xe000ef34 + +0800d8cc : + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + 800d8cc: b480 push {r7} + 800d8ce: b083 sub sp, #12 + 800d8d0: af00 add r7, sp, #0 + __asm volatile + 800d8d2: f04f 0350 mov.w r3, #80 ; 0x50 + 800d8d6: b672 cpsid i + 800d8d8: f383 8811 msr BASEPRI, r3 + 800d8dc: f3bf 8f6f isb sy + 800d8e0: f3bf 8f4f dsb sy + 800d8e4: b662 cpsie i + 800d8e6: 607b str r3, [r7, #4] +} + 800d8e8: bf00 nop + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + 800d8ea: 4b10 ldr r3, [pc, #64] ; (800d92c ) + 800d8ec: 681b ldr r3, [r3, #0] + 800d8ee: 3301 adds r3, #1 + 800d8f0: 4a0e ldr r2, [pc, #56] ; (800d92c ) + 800d8f2: 6013 str r3, [r2, #0] + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + 800d8f4: 4b0d ldr r3, [pc, #52] ; (800d92c ) + 800d8f6: 681b ldr r3, [r3, #0] + 800d8f8: 2b01 cmp r3, #1 + 800d8fa: d111 bne.n 800d920 + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + 800d8fc: 4b0c ldr r3, [pc, #48] ; (800d930 ) + 800d8fe: 681b ldr r3, [r3, #0] + 800d900: b2db uxtb r3, r3 + 800d902: 2b00 cmp r3, #0 + 800d904: d00c beq.n 800d920 + __asm volatile + 800d906: f04f 0350 mov.w r3, #80 ; 0x50 + 800d90a: b672 cpsid i + 800d90c: f383 8811 msr BASEPRI, r3 + 800d910: f3bf 8f6f isb sy + 800d914: f3bf 8f4f dsb sy + 800d918: b662 cpsie i + 800d91a: 603b str r3, [r7, #0] +} + 800d91c: bf00 nop + 800d91e: e7fe b.n 800d91e + } +} + 800d920: bf00 nop + 800d922: 370c adds r7, #12 + 800d924: 46bd mov sp, r7 + 800d926: f85d 7b04 ldr.w r7, [sp], #4 + 800d92a: 4770 bx lr + 800d92c: 200000b0 .word 0x200000b0 + 800d930: e000ed04 .word 0xe000ed04 + +0800d934 : +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + 800d934: b480 push {r7} + 800d936: b083 sub sp, #12 + 800d938: af00 add r7, sp, #0 + configASSERT( uxCriticalNesting ); + 800d93a: 4b13 ldr r3, [pc, #76] ; (800d988 ) + 800d93c: 681b ldr r3, [r3, #0] + 800d93e: 2b00 cmp r3, #0 + 800d940: d10c bne.n 800d95c + __asm volatile + 800d942: f04f 0350 mov.w r3, #80 ; 0x50 + 800d946: b672 cpsid i + 800d948: f383 8811 msr BASEPRI, r3 + 800d94c: f3bf 8f6f isb sy + 800d950: f3bf 8f4f dsb sy + 800d954: b662 cpsie i + 800d956: 607b str r3, [r7, #4] +} + 800d958: bf00 nop + 800d95a: e7fe b.n 800d95a + uxCriticalNesting--; + 800d95c: 4b0a ldr r3, [pc, #40] ; (800d988 ) + 800d95e: 681b ldr r3, [r3, #0] + 800d960: 3b01 subs r3, #1 + 800d962: 4a09 ldr r2, [pc, #36] ; (800d988 ) + 800d964: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 0 ) + 800d966: 4b08 ldr r3, [pc, #32] ; (800d988 ) + 800d968: 681b ldr r3, [r3, #0] + 800d96a: 2b00 cmp r3, #0 + 800d96c: d105 bne.n 800d97a + 800d96e: 2300 movs r3, #0 + 800d970: 603b str r3, [r7, #0] + __asm volatile + 800d972: 683b ldr r3, [r7, #0] + 800d974: f383 8811 msr BASEPRI, r3 +} + 800d978: bf00 nop + { + portENABLE_INTERRUPTS(); + } +} + 800d97a: bf00 nop + 800d97c: 370c adds r7, #12 + 800d97e: 46bd mov sp, r7 + 800d980: f85d 7b04 ldr.w r7, [sp], #4 + 800d984: 4770 bx lr + 800d986: bf00 nop + 800d988: 200000b0 .word 0x200000b0 + 800d98c: 00000000 .word 0x00000000 + +0800d990 : + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + 800d990: f3ef 8009 mrs r0, PSP + 800d994: f3bf 8f6f isb sy + 800d998: 4b15 ldr r3, [pc, #84] ; (800d9f0 ) + 800d99a: 681a ldr r2, [r3, #0] + 800d99c: f01e 0f10 tst.w lr, #16 + 800d9a0: bf08 it eq + 800d9a2: ed20 8a10 vstmdbeq r0!, {s16-s31} + 800d9a6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d9aa: 6010 str r0, [r2, #0] + 800d9ac: e92d 0009 stmdb sp!, {r0, r3} + 800d9b0: f04f 0050 mov.w r0, #80 ; 0x50 + 800d9b4: b672 cpsid i + 800d9b6: f380 8811 msr BASEPRI, r0 + 800d9ba: f3bf 8f4f dsb sy + 800d9be: f3bf 8f6f isb sy + 800d9c2: b662 cpsie i + 800d9c4: f7ff f9e6 bl 800cd94 + 800d9c8: f04f 0000 mov.w r0, #0 + 800d9cc: f380 8811 msr BASEPRI, r0 + 800d9d0: bc09 pop {r0, r3} + 800d9d2: 6819 ldr r1, [r3, #0] + 800d9d4: 6808 ldr r0, [r1, #0] + 800d9d6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d9da: f01e 0f10 tst.w lr, #16 + 800d9de: bf08 it eq + 800d9e0: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 800d9e4: f380 8809 msr PSP, r0 + 800d9e8: f3bf 8f6f isb sy + 800d9ec: 4770 bx lr + 800d9ee: bf00 nop + +0800d9f0 : + 800d9f0: 20005488 .word 0x20005488 + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} + 800d9f4: bf00 nop + 800d9f6: bf00 nop + +0800d9f8 : +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + 800d9f8: b580 push {r7, lr} + 800d9fa: b082 sub sp, #8 + 800d9fc: af00 add r7, sp, #0 + __asm volatile + 800d9fe: f04f 0350 mov.w r3, #80 ; 0x50 + 800da02: b672 cpsid i + 800da04: f383 8811 msr BASEPRI, r3 + 800da08: f3bf 8f6f isb sy + 800da0c: f3bf 8f4f dsb sy + 800da10: b662 cpsie i + 800da12: 607b str r3, [r7, #4] +} + 800da14: bf00 nop + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + 800da16: f7ff f903 bl 800cc20 + 800da1a: 4603 mov r3, r0 + 800da1c: 2b00 cmp r3, #0 + 800da1e: d003 beq.n 800da28 + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + 800da20: 4b06 ldr r3, [pc, #24] ; (800da3c ) + 800da22: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800da26: 601a str r2, [r3, #0] + 800da28: 2300 movs r3, #0 + 800da2a: 603b str r3, [r7, #0] + __asm volatile + 800da2c: 683b ldr r3, [r7, #0] + 800da2e: f383 8811 msr BASEPRI, r3 +} + 800da32: bf00 nop + } + } + portENABLE_INTERRUPTS(); +} + 800da34: bf00 nop + 800da36: 3708 adds r7, #8 + 800da38: 46bd mov sp, r7 + 800da3a: bd80 pop {r7, pc} + 800da3c: e000ed04 .word 0xe000ed04 + +0800da40 : +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) +{ + 800da40: b480 push {r7} + 800da42: af00 add r7, sp, #0 + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + 800da44: 4b0b ldr r3, [pc, #44] ; (800da74 ) + 800da46: 2200 movs r2, #0 + 800da48: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + 800da4a: 4b0b ldr r3, [pc, #44] ; (800da78 ) + 800da4c: 2200 movs r2, #0 + 800da4e: 601a str r2, [r3, #0] + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + 800da50: 4b0a ldr r3, [pc, #40] ; (800da7c ) + 800da52: 681b ldr r3, [r3, #0] + 800da54: 4a0a ldr r2, [pc, #40] ; (800da80 ) + 800da56: fba2 2303 umull r2, r3, r2, r3 + 800da5a: 099b lsrs r3, r3, #6 + 800da5c: 4a09 ldr r2, [pc, #36] ; (800da84 ) + 800da5e: 3b01 subs r3, #1 + 800da60: 6013 str r3, [r2, #0] + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + 800da62: 4b04 ldr r3, [pc, #16] ; (800da74 ) + 800da64: 2207 movs r2, #7 + 800da66: 601a str r2, [r3, #0] +} + 800da68: bf00 nop + 800da6a: 46bd mov sp, r7 + 800da6c: f85d 7b04 ldr.w r7, [sp], #4 + 800da70: 4770 bx lr + 800da72: bf00 nop + 800da74: e000e010 .word 0xe000e010 + 800da78: e000e018 .word 0xe000e018 + 800da7c: 2000007c .word 0x2000007c + 800da80: 10624dd3 .word 0x10624dd3 + 800da84: e000e014 .word 0xe000e014 + +0800da88 : +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + 800da88: f8df 000c ldr.w r0, [pc, #12] ; 800da98 + 800da8c: 6801 ldr r1, [r0, #0] + 800da8e: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800da92: 6001 str r1, [r0, #0] + 800da94: 4770 bx lr + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 " + ); +} + 800da96: bf00 nop + 800da98: e000ed88 .word 0xe000ed88 + +0800da9c : +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + 800da9c: b480 push {r7} + 800da9e: b085 sub sp, #20 + 800daa0: af00 add r7, sp, #0 + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + 800daa2: f3ef 8305 mrs r3, IPSR + 800daa6: 60fb str r3, [r7, #12] + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + 800daa8: 68fb ldr r3, [r7, #12] + 800daaa: 2b0f cmp r3, #15 + 800daac: d916 bls.n 800dadc + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + 800daae: 4a19 ldr r2, [pc, #100] ; (800db14 ) + 800dab0: 68fb ldr r3, [r7, #12] + 800dab2: 4413 add r3, r2 + 800dab4: 781b ldrb r3, [r3, #0] + 800dab6: 72fb strb r3, [r7, #11] + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + 800dab8: 4b17 ldr r3, [pc, #92] ; (800db18 ) + 800daba: 781b ldrb r3, [r3, #0] + 800dabc: 7afa ldrb r2, [r7, #11] + 800dabe: 429a cmp r2, r3 + 800dac0: d20c bcs.n 800dadc + __asm volatile + 800dac2: f04f 0350 mov.w r3, #80 ; 0x50 + 800dac6: b672 cpsid i + 800dac8: f383 8811 msr BASEPRI, r3 + 800dacc: f3bf 8f6f isb sy + 800dad0: f3bf 8f4f dsb sy + 800dad4: b662 cpsie i + 800dad6: 607b str r3, [r7, #4] +} + 800dad8: bf00 nop + 800dada: e7fe b.n 800dada + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + 800dadc: 4b0f ldr r3, [pc, #60] ; (800db1c ) + 800dade: 681b ldr r3, [r3, #0] + 800dae0: f403 62e0 and.w r2, r3, #1792 ; 0x700 + 800dae4: 4b0e ldr r3, [pc, #56] ; (800db20 ) + 800dae6: 681b ldr r3, [r3, #0] + 800dae8: 429a cmp r2, r3 + 800daea: d90c bls.n 800db06 + __asm volatile + 800daec: f04f 0350 mov.w r3, #80 ; 0x50 + 800daf0: b672 cpsid i + 800daf2: f383 8811 msr BASEPRI, r3 + 800daf6: f3bf 8f6f isb sy + 800dafa: f3bf 8f4f dsb sy + 800dafe: b662 cpsie i + 800db00: 603b str r3, [r7, #0] +} + 800db02: bf00 nop + 800db04: e7fe b.n 800db04 + } + 800db06: bf00 nop + 800db08: 3714 adds r7, #20 + 800db0a: 46bd mov sp, r7 + 800db0c: f85d 7b04 ldr.w r7, [sp], #4 + 800db10: 4770 bx lr + 800db12: bf00 nop + 800db14: e000e3f0 .word 0xe000e3f0 + 800db18: 200055b4 .word 0x200055b4 + 800db1c: e000ed0c .word 0xe000ed0c + 800db20: 200055b8 .word 0x200055b8 + +0800db24 : +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ + 800db24: b580 push {r7, lr} + 800db26: b08a sub sp, #40 ; 0x28 + 800db28: af00 add r7, sp, #0 + 800db2a: 6078 str r0, [r7, #4] +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + 800db2c: 2300 movs r3, #0 + 800db2e: 61fb str r3, [r7, #28] + + vTaskSuspendAll(); + 800db30: f7fe ffa8 bl 800ca84 + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + 800db34: 4b5b ldr r3, [pc, #364] ; (800dca4 ) + 800db36: 681b ldr r3, [r3, #0] + 800db38: 2b00 cmp r3, #0 + 800db3a: d101 bne.n 800db40 + { + prvHeapInit(); + 800db3c: f000 f91a bl 800dd74 + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 800db40: 4b59 ldr r3, [pc, #356] ; (800dca8 ) + 800db42: 681a ldr r2, [r3, #0] + 800db44: 687b ldr r3, [r7, #4] + 800db46: 4013 ands r3, r2 + 800db48: 2b00 cmp r3, #0 + 800db4a: f040 8092 bne.w 800dc72 + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + 800db4e: 687b ldr r3, [r7, #4] + 800db50: 2b00 cmp r3, #0 + 800db52: d01f beq.n 800db94 + { + xWantedSize += xHeapStructSize; + 800db54: 2208 movs r2, #8 + 800db56: 687b ldr r3, [r7, #4] + 800db58: 4413 add r3, r2 + 800db5a: 607b str r3, [r7, #4] + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 800db5c: 687b ldr r3, [r7, #4] + 800db5e: f003 0307 and.w r3, r3, #7 + 800db62: 2b00 cmp r3, #0 + 800db64: d016 beq.n 800db94 + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 800db66: 687b ldr r3, [r7, #4] + 800db68: f023 0307 bic.w r3, r3, #7 + 800db6c: 3308 adds r3, #8 + 800db6e: 607b str r3, [r7, #4] + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + 800db70: 687b ldr r3, [r7, #4] + 800db72: f003 0307 and.w r3, r3, #7 + 800db76: 2b00 cmp r3, #0 + 800db78: d00c beq.n 800db94 + __asm volatile + 800db7a: f04f 0350 mov.w r3, #80 ; 0x50 + 800db7e: b672 cpsid i + 800db80: f383 8811 msr BASEPRI, r3 + 800db84: f3bf 8f6f isb sy + 800db88: f3bf 8f4f dsb sy + 800db8c: b662 cpsie i + 800db8e: 617b str r3, [r7, #20] +} + 800db90: bf00 nop + 800db92: e7fe b.n 800db92 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 800db94: 687b ldr r3, [r7, #4] + 800db96: 2b00 cmp r3, #0 + 800db98: d06b beq.n 800dc72 + 800db9a: 4b44 ldr r3, [pc, #272] ; (800dcac ) + 800db9c: 681b ldr r3, [r3, #0] + 800db9e: 687a ldr r2, [r7, #4] + 800dba0: 429a cmp r2, r3 + 800dba2: d866 bhi.n 800dc72 + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + 800dba4: 4b42 ldr r3, [pc, #264] ; (800dcb0 ) + 800dba6: 623b str r3, [r7, #32] + pxBlock = xStart.pxNextFreeBlock; + 800dba8: 4b41 ldr r3, [pc, #260] ; (800dcb0 ) + 800dbaa: 681b ldr r3, [r3, #0] + 800dbac: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 800dbae: e004 b.n 800dbba + { + pxPreviousBlock = pxBlock; + 800dbb0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbb2: 623b str r3, [r7, #32] + pxBlock = pxBlock->pxNextFreeBlock; + 800dbb4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbb6: 681b ldr r3, [r3, #0] + 800dbb8: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 800dbba: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbbc: 685b ldr r3, [r3, #4] + 800dbbe: 687a ldr r2, [r7, #4] + 800dbc0: 429a cmp r2, r3 + 800dbc2: d903 bls.n 800dbcc + 800dbc4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbc6: 681b ldr r3, [r3, #0] + 800dbc8: 2b00 cmp r3, #0 + 800dbca: d1f1 bne.n 800dbb0 + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if( pxBlock != pxEnd ) + 800dbcc: 4b35 ldr r3, [pc, #212] ; (800dca4 ) + 800dbce: 681b ldr r3, [r3, #0] + 800dbd0: 6a7a ldr r2, [r7, #36] ; 0x24 + 800dbd2: 429a cmp r2, r3 + 800dbd4: d04d beq.n 800dc72 + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 800dbd6: 6a3b ldr r3, [r7, #32] + 800dbd8: 681b ldr r3, [r3, #0] + 800dbda: 2208 movs r2, #8 + 800dbdc: 4413 add r3, r2 + 800dbde: 61fb str r3, [r7, #28] + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 800dbe0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbe2: 681a ldr r2, [r3, #0] + 800dbe4: 6a3b ldr r3, [r7, #32] + 800dbe6: 601a str r2, [r3, #0] + + /* If the block is larger than required it can be split into + two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 800dbe8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dbea: 685a ldr r2, [r3, #4] + 800dbec: 687b ldr r3, [r7, #4] + 800dbee: 1ad2 subs r2, r2, r3 + 800dbf0: 2308 movs r3, #8 + 800dbf2: 005b lsls r3, r3, #1 + 800dbf4: 429a cmp r2, r3 + 800dbf6: d921 bls.n 800dc3c + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 800dbf8: 6a7a ldr r2, [r7, #36] ; 0x24 + 800dbfa: 687b ldr r3, [r7, #4] + 800dbfc: 4413 add r3, r2 + 800dbfe: 61bb str r3, [r7, #24] + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 800dc00: 69bb ldr r3, [r7, #24] + 800dc02: f003 0307 and.w r3, r3, #7 + 800dc06: 2b00 cmp r3, #0 + 800dc08: d00c beq.n 800dc24 + __asm volatile + 800dc0a: f04f 0350 mov.w r3, #80 ; 0x50 + 800dc0e: b672 cpsid i + 800dc10: f383 8811 msr BASEPRI, r3 + 800dc14: f3bf 8f6f isb sy + 800dc18: f3bf 8f4f dsb sy + 800dc1c: b662 cpsie i + 800dc1e: 613b str r3, [r7, #16] +} + 800dc20: bf00 nop + 800dc22: e7fe b.n 800dc22 + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 800dc24: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc26: 685a ldr r2, [r3, #4] + 800dc28: 687b ldr r3, [r7, #4] + 800dc2a: 1ad2 subs r2, r2, r3 + 800dc2c: 69bb ldr r3, [r7, #24] + 800dc2e: 605a str r2, [r3, #4] + pxBlock->xBlockSize = xWantedSize; + 800dc30: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc32: 687a ldr r2, [r7, #4] + 800dc34: 605a str r2, [r3, #4] + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 800dc36: 69b8 ldr r0, [r7, #24] + 800dc38: f000 f8fe bl 800de38 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + 800dc3c: 4b1b ldr r3, [pc, #108] ; (800dcac ) + 800dc3e: 681a ldr r2, [r3, #0] + 800dc40: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc42: 685b ldr r3, [r3, #4] + 800dc44: 1ad3 subs r3, r2, r3 + 800dc46: 4a19 ldr r2, [pc, #100] ; (800dcac ) + 800dc48: 6013 str r3, [r2, #0] + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 800dc4a: 4b18 ldr r3, [pc, #96] ; (800dcac ) + 800dc4c: 681a ldr r2, [r3, #0] + 800dc4e: 4b19 ldr r3, [pc, #100] ; (800dcb4 ) + 800dc50: 681b ldr r3, [r3, #0] + 800dc52: 429a cmp r2, r3 + 800dc54: d203 bcs.n 800dc5e + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 800dc56: 4b15 ldr r3, [pc, #84] ; (800dcac ) + 800dc58: 681b ldr r3, [r3, #0] + 800dc5a: 4a16 ldr r2, [pc, #88] ; (800dcb4 ) + 800dc5c: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + 800dc5e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc60: 685a ldr r2, [r3, #4] + 800dc62: 4b11 ldr r3, [pc, #68] ; (800dca8 ) + 800dc64: 681b ldr r3, [r3, #0] + 800dc66: 431a orrs r2, r3 + 800dc68: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc6a: 605a str r2, [r3, #4] + pxBlock->pxNextFreeBlock = NULL; + 800dc6c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800dc6e: 2200 movs r2, #0 + 800dc70: 601a str r2, [r3, #0] + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + 800dc72: f7fe ff15 bl 800caa0 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 800dc76: 69fb ldr r3, [r7, #28] + 800dc78: f003 0307 and.w r3, r3, #7 + 800dc7c: 2b00 cmp r3, #0 + 800dc7e: d00c beq.n 800dc9a + __asm volatile + 800dc80: f04f 0350 mov.w r3, #80 ; 0x50 + 800dc84: b672 cpsid i + 800dc86: f383 8811 msr BASEPRI, r3 + 800dc8a: f3bf 8f6f isb sy + 800dc8e: f3bf 8f4f dsb sy + 800dc92: b662 cpsie i + 800dc94: 60fb str r3, [r7, #12] +} + 800dc96: bf00 nop + 800dc98: e7fe b.n 800dc98 + return pvReturn; + 800dc9a: 69fb ldr r3, [r7, #28] +} + 800dc9c: 4618 mov r0, r3 + 800dc9e: 3728 adds r7, #40 ; 0x28 + 800dca0: 46bd mov sp, r7 + 800dca2: bd80 pop {r7, pc} + 800dca4: 200091c4 .word 0x200091c4 + 800dca8: 200091d0 .word 0x200091d0 + 800dcac: 200091c8 .word 0x200091c8 + 800dcb0: 200091bc .word 0x200091bc + 800dcb4: 200091cc .word 0x200091cc + +0800dcb8 : +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + 800dcb8: b580 push {r7, lr} + 800dcba: b086 sub sp, #24 + 800dcbc: af00 add r7, sp, #0 + 800dcbe: 6078 str r0, [r7, #4] +uint8_t *puc = ( uint8_t * ) pv; + 800dcc0: 687b ldr r3, [r7, #4] + 800dcc2: 617b str r3, [r7, #20] +BlockLink_t *pxLink; + + if( pv != NULL ) + 800dcc4: 687b ldr r3, [r7, #4] + 800dcc6: 2b00 cmp r3, #0 + 800dcc8: d04c beq.n 800dd64 + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + 800dcca: 2308 movs r3, #8 + 800dccc: 425b negs r3, r3 + 800dcce: 697a ldr r2, [r7, #20] + 800dcd0: 4413 add r3, r2 + 800dcd2: 617b str r3, [r7, #20] + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + 800dcd4: 697b ldr r3, [r7, #20] + 800dcd6: 613b str r3, [r7, #16] + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 800dcd8: 693b ldr r3, [r7, #16] + 800dcda: 685a ldr r2, [r3, #4] + 800dcdc: 4b23 ldr r3, [pc, #140] ; (800dd6c ) + 800dcde: 681b ldr r3, [r3, #0] + 800dce0: 4013 ands r3, r2 + 800dce2: 2b00 cmp r3, #0 + 800dce4: d10c bne.n 800dd00 + __asm volatile + 800dce6: f04f 0350 mov.w r3, #80 ; 0x50 + 800dcea: b672 cpsid i + 800dcec: f383 8811 msr BASEPRI, r3 + 800dcf0: f3bf 8f6f isb sy + 800dcf4: f3bf 8f4f dsb sy + 800dcf8: b662 cpsie i + 800dcfa: 60fb str r3, [r7, #12] +} + 800dcfc: bf00 nop + 800dcfe: e7fe b.n 800dcfe + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 800dd00: 693b ldr r3, [r7, #16] + 800dd02: 681b ldr r3, [r3, #0] + 800dd04: 2b00 cmp r3, #0 + 800dd06: d00c beq.n 800dd22 + __asm volatile + 800dd08: f04f 0350 mov.w r3, #80 ; 0x50 + 800dd0c: b672 cpsid i + 800dd0e: f383 8811 msr BASEPRI, r3 + 800dd12: f3bf 8f6f isb sy + 800dd16: f3bf 8f4f dsb sy + 800dd1a: b662 cpsie i + 800dd1c: 60bb str r3, [r7, #8] +} + 800dd1e: bf00 nop + 800dd20: e7fe b.n 800dd20 + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + 800dd22: 693b ldr r3, [r7, #16] + 800dd24: 685a ldr r2, [r3, #4] + 800dd26: 4b11 ldr r3, [pc, #68] ; (800dd6c ) + 800dd28: 681b ldr r3, [r3, #0] + 800dd2a: 4013 ands r3, r2 + 800dd2c: 2b00 cmp r3, #0 + 800dd2e: d019 beq.n 800dd64 + { + if( pxLink->pxNextFreeBlock == NULL ) + 800dd30: 693b ldr r3, [r7, #16] + 800dd32: 681b ldr r3, [r3, #0] + 800dd34: 2b00 cmp r3, #0 + 800dd36: d115 bne.n 800dd64 + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 800dd38: 693b ldr r3, [r7, #16] + 800dd3a: 685a ldr r2, [r3, #4] + 800dd3c: 4b0b ldr r3, [pc, #44] ; (800dd6c ) + 800dd3e: 681b ldr r3, [r3, #0] + 800dd40: 43db mvns r3, r3 + 800dd42: 401a ands r2, r3 + 800dd44: 693b ldr r3, [r7, #16] + 800dd46: 605a str r2, [r3, #4] + + vTaskSuspendAll(); + 800dd48: f7fe fe9c bl 800ca84 + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + 800dd4c: 693b ldr r3, [r7, #16] + 800dd4e: 685a ldr r2, [r3, #4] + 800dd50: 4b07 ldr r3, [pc, #28] ; (800dd70 ) + 800dd52: 681b ldr r3, [r3, #0] + 800dd54: 4413 add r3, r2 + 800dd56: 4a06 ldr r2, [pc, #24] ; (800dd70 ) + 800dd58: 6013 str r3, [r2, #0] + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 800dd5a: 6938 ldr r0, [r7, #16] + 800dd5c: f000 f86c bl 800de38 + } + ( void ) xTaskResumeAll(); + 800dd60: f7fe fe9e bl 800caa0 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} + 800dd64: bf00 nop + 800dd66: 3718 adds r7, #24 + 800dd68: 46bd mov sp, r7 + 800dd6a: bd80 pop {r7, pc} + 800dd6c: 200091d0 .word 0x200091d0 + 800dd70: 200091c8 .word 0x200091c8 + +0800dd74 : + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + 800dd74: b480 push {r7} + 800dd76: b085 sub sp, #20 + 800dd78: af00 add r7, sp, #0 +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 800dd7a: f44f 5370 mov.w r3, #15360 ; 0x3c00 + 800dd7e: 60bb str r3, [r7, #8] + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + 800dd80: 4b27 ldr r3, [pc, #156] ; (800de20 ) + 800dd82: 60fb str r3, [r7, #12] + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 800dd84: 68fb ldr r3, [r7, #12] + 800dd86: f003 0307 and.w r3, r3, #7 + 800dd8a: 2b00 cmp r3, #0 + 800dd8c: d00c beq.n 800dda8 + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 800dd8e: 68fb ldr r3, [r7, #12] + 800dd90: 3307 adds r3, #7 + 800dd92: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 800dd94: 68fb ldr r3, [r7, #12] + 800dd96: f023 0307 bic.w r3, r3, #7 + 800dd9a: 60fb str r3, [r7, #12] + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 800dd9c: 68ba ldr r2, [r7, #8] + 800dd9e: 68fb ldr r3, [r7, #12] + 800dda0: 1ad3 subs r3, r2, r3 + 800dda2: 4a1f ldr r2, [pc, #124] ; (800de20 ) + 800dda4: 4413 add r3, r2 + 800dda6: 60bb str r3, [r7, #8] + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + 800dda8: 68fb ldr r3, [r7, #12] + 800ddaa: 607b str r3, [r7, #4] + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 800ddac: 4a1d ldr r2, [pc, #116] ; (800de24 ) + 800ddae: 687b ldr r3, [r7, #4] + 800ddb0: 6013 str r3, [r2, #0] + xStart.xBlockSize = ( size_t ) 0; + 800ddb2: 4b1c ldr r3, [pc, #112] ; (800de24 ) + 800ddb4: 2200 movs r2, #0 + 800ddb6: 605a str r2, [r3, #4] + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 800ddb8: 687b ldr r3, [r7, #4] + 800ddba: 68ba ldr r2, [r7, #8] + 800ddbc: 4413 add r3, r2 + 800ddbe: 60fb str r3, [r7, #12] + uxAddress -= xHeapStructSize; + 800ddc0: 2208 movs r2, #8 + 800ddc2: 68fb ldr r3, [r7, #12] + 800ddc4: 1a9b subs r3, r3, r2 + 800ddc6: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 800ddc8: 68fb ldr r3, [r7, #12] + 800ddca: f023 0307 bic.w r3, r3, #7 + 800ddce: 60fb str r3, [r7, #12] + pxEnd = ( void * ) uxAddress; + 800ddd0: 68fb ldr r3, [r7, #12] + 800ddd2: 4a15 ldr r2, [pc, #84] ; (800de28 ) + 800ddd4: 6013 str r3, [r2, #0] + pxEnd->xBlockSize = 0; + 800ddd6: 4b14 ldr r3, [pc, #80] ; (800de28 ) + 800ddd8: 681b ldr r3, [r3, #0] + 800ddda: 2200 movs r2, #0 + 800dddc: 605a str r2, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 800ddde: 4b12 ldr r3, [pc, #72] ; (800de28 ) + 800dde0: 681b ldr r3, [r3, #0] + 800dde2: 2200 movs r2, #0 + 800dde4: 601a str r2, [r3, #0] + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + 800dde6: 687b ldr r3, [r7, #4] + 800dde8: 603b str r3, [r7, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 800ddea: 683b ldr r3, [r7, #0] + 800ddec: 68fa ldr r2, [r7, #12] + 800ddee: 1ad2 subs r2, r2, r3 + 800ddf0: 683b ldr r3, [r7, #0] + 800ddf2: 605a str r2, [r3, #4] + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 800ddf4: 4b0c ldr r3, [pc, #48] ; (800de28 ) + 800ddf6: 681a ldr r2, [r3, #0] + 800ddf8: 683b ldr r3, [r7, #0] + 800ddfa: 601a str r2, [r3, #0] + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800ddfc: 683b ldr r3, [r7, #0] + 800ddfe: 685b ldr r3, [r3, #4] + 800de00: 4a0a ldr r2, [pc, #40] ; (800de2c ) + 800de02: 6013 str r3, [r2, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800de04: 683b ldr r3, [r7, #0] + 800de06: 685b ldr r3, [r3, #4] + 800de08: 4a09 ldr r2, [pc, #36] ; (800de30 ) + 800de0a: 6013 str r3, [r2, #0] + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 800de0c: 4b09 ldr r3, [pc, #36] ; (800de34 ) + 800de0e: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 800de12: 601a str r2, [r3, #0] +} + 800de14: bf00 nop + 800de16: 3714 adds r7, #20 + 800de18: 46bd mov sp, r7 + 800de1a: f85d 7b04 ldr.w r7, [sp], #4 + 800de1e: 4770 bx lr + 800de20: 200055bc .word 0x200055bc + 800de24: 200091bc .word 0x200091bc + 800de28: 200091c4 .word 0x200091c4 + 800de2c: 200091cc .word 0x200091cc + 800de30: 200091c8 .word 0x200091c8 + 800de34: 200091d0 .word 0x200091d0 + +0800de38 : +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 800de38: b480 push {r7} + 800de3a: b085 sub sp, #20 + 800de3c: af00 add r7, sp, #0 + 800de3e: 6078 str r0, [r7, #4] +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 800de40: 4b28 ldr r3, [pc, #160] ; (800dee4 ) + 800de42: 60fb str r3, [r7, #12] + 800de44: e002 b.n 800de4c + 800de46: 68fb ldr r3, [r7, #12] + 800de48: 681b ldr r3, [r3, #0] + 800de4a: 60fb str r3, [r7, #12] + 800de4c: 68fb ldr r3, [r7, #12] + 800de4e: 681b ldr r3, [r3, #0] + 800de50: 687a ldr r2, [r7, #4] + 800de52: 429a cmp r2, r3 + 800de54: d8f7 bhi.n 800de46 + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + 800de56: 68fb ldr r3, [r7, #12] + 800de58: 60bb str r3, [r7, #8] + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 800de5a: 68fb ldr r3, [r7, #12] + 800de5c: 685b ldr r3, [r3, #4] + 800de5e: 68ba ldr r2, [r7, #8] + 800de60: 4413 add r3, r2 + 800de62: 687a ldr r2, [r7, #4] + 800de64: 429a cmp r2, r3 + 800de66: d108 bne.n 800de7a + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 800de68: 68fb ldr r3, [r7, #12] + 800de6a: 685a ldr r2, [r3, #4] + 800de6c: 687b ldr r3, [r7, #4] + 800de6e: 685b ldr r3, [r3, #4] + 800de70: 441a add r2, r3 + 800de72: 68fb ldr r3, [r7, #12] + 800de74: 605a str r2, [r3, #4] + pxBlockToInsert = pxIterator; + 800de76: 68fb ldr r3, [r7, #12] + 800de78: 607b str r3, [r7, #4] + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + 800de7a: 687b ldr r3, [r7, #4] + 800de7c: 60bb str r3, [r7, #8] + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 800de7e: 687b ldr r3, [r7, #4] + 800de80: 685b ldr r3, [r3, #4] + 800de82: 68ba ldr r2, [r7, #8] + 800de84: 441a add r2, r3 + 800de86: 68fb ldr r3, [r7, #12] + 800de88: 681b ldr r3, [r3, #0] + 800de8a: 429a cmp r2, r3 + 800de8c: d118 bne.n 800dec0 + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 800de8e: 68fb ldr r3, [r7, #12] + 800de90: 681a ldr r2, [r3, #0] + 800de92: 4b15 ldr r3, [pc, #84] ; (800dee8 ) + 800de94: 681b ldr r3, [r3, #0] + 800de96: 429a cmp r2, r3 + 800de98: d00d beq.n 800deb6 + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 800de9a: 687b ldr r3, [r7, #4] + 800de9c: 685a ldr r2, [r3, #4] + 800de9e: 68fb ldr r3, [r7, #12] + 800dea0: 681b ldr r3, [r3, #0] + 800dea2: 685b ldr r3, [r3, #4] + 800dea4: 441a add r2, r3 + 800dea6: 687b ldr r3, [r7, #4] + 800dea8: 605a str r2, [r3, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 800deaa: 68fb ldr r3, [r7, #12] + 800deac: 681b ldr r3, [r3, #0] + 800deae: 681a ldr r2, [r3, #0] + 800deb0: 687b ldr r3, [r7, #4] + 800deb2: 601a str r2, [r3, #0] + 800deb4: e008 b.n 800dec8 + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + 800deb6: 4b0c ldr r3, [pc, #48] ; (800dee8 ) + 800deb8: 681a ldr r2, [r3, #0] + 800deba: 687b ldr r3, [r7, #4] + 800debc: 601a str r2, [r3, #0] + 800debe: e003 b.n 800dec8 + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 800dec0: 68fb ldr r3, [r7, #12] + 800dec2: 681a ldr r2, [r3, #0] + 800dec4: 687b ldr r3, [r7, #4] + 800dec6: 601a str r2, [r3, #0] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 800dec8: 68fa ldr r2, [r7, #12] + 800deca: 687b ldr r3, [r7, #4] + 800decc: 429a cmp r2, r3 + 800dece: d002 beq.n 800ded6 + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 800ded0: 68fb ldr r3, [r7, #12] + 800ded2: 687a ldr r2, [r7, #4] + 800ded4: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800ded6: bf00 nop + 800ded8: 3714 adds r7, #20 + 800deda: 46bd mov sp, r7 + 800dedc: f85d 7b04 ldr.w r7, [sp], #4 + 800dee0: 4770 bx lr + 800dee2: bf00 nop + 800dee4: 200091bc .word 0x200091bc + 800dee8: 200091c4 .word 0x200091c4 + +0800deec : + * @param mbox the mbox to fetch the message from + * @param msg the place to store the message + */ +static void +tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg) +{ + 800deec: b580 push {r7, lr} + 800deee: b084 sub sp, #16 + 800def0: af00 add r7, sp, #0 + 800def2: 6078 str r0, [r7, #4] + 800def4: 6039 str r1, [r7, #0] + u32_t sleeptime, res; + +again: + LWIP_ASSERT_CORE_LOCKED(); + + sleeptime = sys_timeouts_sleeptime(); + 800def6: f008 fc47 bl 8016788 + 800defa: 60f8 str r0, [r7, #12] + if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) { + 800defc: 68fb ldr r3, [r7, #12] + 800defe: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800df02: d10b bne.n 800df1c + UNLOCK_TCPIP_CORE(); + 800df04: 4813 ldr r0, [pc, #76] ; (800df54 ) + 800df06: f00d fe42 bl 801bb8e + sys_arch_mbox_fetch(mbox, msg, 0); + 800df0a: 2200 movs r2, #0 + 800df0c: 6839 ldr r1, [r7, #0] + 800df0e: 6878 ldr r0, [r7, #4] + 800df10: f00d fdb4 bl 801ba7c + LOCK_TCPIP_CORE(); + 800df14: 480f ldr r0, [pc, #60] ; (800df54 ) + 800df16: f00d fe2b bl 801bb70 + return; + 800df1a: e018 b.n 800df4e + } else if (sleeptime == 0) { + 800df1c: 68fb ldr r3, [r7, #12] + 800df1e: 2b00 cmp r3, #0 + 800df20: d102 bne.n 800df28 + sys_check_timeouts(); + 800df22: f008 fbf7 bl 8016714 + /* We try again to fetch a message from the mbox. */ + goto again; + 800df26: e7e6 b.n 800def6 + } + + UNLOCK_TCPIP_CORE(); + 800df28: 480a ldr r0, [pc, #40] ; (800df54 ) + 800df2a: f00d fe30 bl 801bb8e + res = sys_arch_mbox_fetch(mbox, msg, sleeptime); + 800df2e: 68fa ldr r2, [r7, #12] + 800df30: 6839 ldr r1, [r7, #0] + 800df32: 6878 ldr r0, [r7, #4] + 800df34: f00d fda2 bl 801ba7c + 800df38: 60b8 str r0, [r7, #8] + LOCK_TCPIP_CORE(); + 800df3a: 4806 ldr r0, [pc, #24] ; (800df54 ) + 800df3c: f00d fe18 bl 801bb70 + if (res == SYS_ARCH_TIMEOUT) { + 800df40: 68bb ldr r3, [r7, #8] + 800df42: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800df46: d102 bne.n 800df4e + /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred + before a message could be fetched. */ + sys_check_timeouts(); + 800df48: f008 fbe4 bl 8016714 + /* We try again to fetch a message from the mbox. */ + goto again; + 800df4c: e7d3 b.n 800def6 + } +} + 800df4e: 3710 adds r7, #16 + 800df50: 46bd mov sp, r7 + 800df52: bd80 pop {r7, pc} + 800df54: 200091e0 .word 0x200091e0 + +0800df58 : + * + * @param arg unused argument + */ +static void +tcpip_thread(void *arg) +{ + 800df58: b580 push {r7, lr} + 800df5a: b084 sub sp, #16 + 800df5c: af00 add r7, sp, #0 + 800df5e: 6078 str r0, [r7, #4] + struct tcpip_msg *msg; + LWIP_UNUSED_ARG(arg); + + LWIP_MARK_TCPIP_THREAD(); + + LOCK_TCPIP_CORE(); + 800df60: 4810 ldr r0, [pc, #64] ; (800dfa4 ) + 800df62: f00d fe05 bl 801bb70 + if (tcpip_init_done != NULL) { + 800df66: 4b10 ldr r3, [pc, #64] ; (800dfa8 ) + 800df68: 681b ldr r3, [r3, #0] + 800df6a: 2b00 cmp r3, #0 + 800df6c: d005 beq.n 800df7a + tcpip_init_done(tcpip_init_done_arg); + 800df6e: 4b0e ldr r3, [pc, #56] ; (800dfa8 ) + 800df70: 681b ldr r3, [r3, #0] + 800df72: 4a0e ldr r2, [pc, #56] ; (800dfac ) + 800df74: 6812 ldr r2, [r2, #0] + 800df76: 4610 mov r0, r2 + 800df78: 4798 blx r3 + } + + while (1) { /* MAIN Loop */ + LWIP_TCPIP_THREAD_ALIVE(); + /* wait for a message, timeouts are processed while waiting */ + TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg); + 800df7a: f107 030c add.w r3, r7, #12 + 800df7e: 4619 mov r1, r3 + 800df80: 480b ldr r0, [pc, #44] ; (800dfb0 ) + 800df82: f7ff ffb3 bl 800deec + if (msg == NULL) { + 800df86: 68fb ldr r3, [r7, #12] + 800df88: 2b00 cmp r3, #0 + 800df8a: d106 bne.n 800df9a + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n")); + LWIP_ASSERT("tcpip_thread: invalid message", 0); + 800df8c: 4b09 ldr r3, [pc, #36] ; (800dfb4 ) + 800df8e: 2291 movs r2, #145 ; 0x91 + 800df90: 4909 ldr r1, [pc, #36] ; (800dfb8 ) + 800df92: 480a ldr r0, [pc, #40] ; (800dfbc ) + 800df94: f00e f83e bl 801c014 + continue; + 800df98: e003 b.n 800dfa2 + } + tcpip_thread_handle_msg(msg); + 800df9a: 68fb ldr r3, [r7, #12] + 800df9c: 4618 mov r0, r3 + 800df9e: f000 f80f bl 800dfc0 + TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg); + 800dfa2: e7ea b.n 800df7a + 800dfa4: 200091e0 .word 0x200091e0 + 800dfa8: 200091d4 .word 0x200091d4 + 800dfac: 200091d8 .word 0x200091d8 + 800dfb0: 200091dc .word 0x200091dc + 800dfb4: 0801e900 .word 0x0801e900 + 800dfb8: 0801e930 .word 0x0801e930 + 800dfbc: 0801e950 .word 0x0801e950 + +0800dfc0 : +/* Handle a single tcpip_msg + * This is in its own function for access by tests only. + */ +static void +tcpip_thread_handle_msg(struct tcpip_msg *msg) +{ + 800dfc0: b580 push {r7, lr} + 800dfc2: b082 sub sp, #8 + 800dfc4: af00 add r7, sp, #0 + 800dfc6: 6078 str r0, [r7, #4] + switch (msg->type) { + 800dfc8: 687b ldr r3, [r7, #4] + 800dfca: 781b ldrb r3, [r3, #0] + 800dfcc: 2b02 cmp r3, #2 + 800dfce: d026 beq.n 800e01e + 800dfd0: 2b02 cmp r3, #2 + 800dfd2: dc2b bgt.n 800e02c + 800dfd4: 2b00 cmp r3, #0 + 800dfd6: d002 beq.n 800dfde + 800dfd8: 2b01 cmp r3, #1 + 800dfda: d015 beq.n 800e008 + 800dfdc: e026 b.n 800e02c +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + +#if !LWIP_TCPIP_CORE_LOCKING_INPUT + case TCPIP_MSG_INPKT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); + if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) { + 800dfde: 687b ldr r3, [r7, #4] + 800dfe0: 68db ldr r3, [r3, #12] + 800dfe2: 687a ldr r2, [r7, #4] + 800dfe4: 6850 ldr r0, [r2, #4] + 800dfe6: 687a ldr r2, [r7, #4] + 800dfe8: 6892 ldr r2, [r2, #8] + 800dfea: 4611 mov r1, r2 + 800dfec: 4798 blx r3 + 800dfee: 4603 mov r3, r0 + 800dff0: 2b00 cmp r3, #0 + 800dff2: d004 beq.n 800dffe + pbuf_free(msg->msg.inp.p); + 800dff4: 687b ldr r3, [r7, #4] + 800dff6: 685b ldr r3, [r3, #4] + 800dff8: 4618 mov r0, r3 + 800dffa: f002 fd01 bl 8010a00 + } + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + 800dffe: 6879 ldr r1, [r7, #4] + 800e000: 2009 movs r0, #9 + 800e002: f001 fe4d bl 800fca0 + break; + 800e006: e018 b.n 800e03a + break; +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + + case TCPIP_MSG_CALLBACK: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); + msg->msg.cb.function(msg->msg.cb.ctx); + 800e008: 687b ldr r3, [r7, #4] + 800e00a: 685b ldr r3, [r3, #4] + 800e00c: 687a ldr r2, [r7, #4] + 800e00e: 6892 ldr r2, [r2, #8] + 800e010: 4610 mov r0, r2 + 800e012: 4798 blx r3 + memp_free(MEMP_TCPIP_MSG_API, msg); + 800e014: 6879 ldr r1, [r7, #4] + 800e016: 2008 movs r0, #8 + 800e018: f001 fe42 bl 800fca0 + break; + 800e01c: e00d b.n 800e03a + + case TCPIP_MSG_CALLBACK_STATIC: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg)); + msg->msg.cb.function(msg->msg.cb.ctx); + 800e01e: 687b ldr r3, [r7, #4] + 800e020: 685b ldr r3, [r3, #4] + 800e022: 687a ldr r2, [r7, #4] + 800e024: 6892 ldr r2, [r2, #8] + 800e026: 4610 mov r0, r2 + 800e028: 4798 blx r3 + break; + 800e02a: e006 b.n 800e03a + + default: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type)); + LWIP_ASSERT("tcpip_thread: invalid message", 0); + 800e02c: 4b05 ldr r3, [pc, #20] ; (800e044 ) + 800e02e: 22cf movs r2, #207 ; 0xcf + 800e030: 4905 ldr r1, [pc, #20] ; (800e048 ) + 800e032: 4806 ldr r0, [pc, #24] ; (800e04c ) + 800e034: f00d ffee bl 801c014 + break; + 800e038: bf00 nop + } +} + 800e03a: bf00 nop + 800e03c: 3708 adds r7, #8 + 800e03e: 46bd mov sp, r7 + 800e040: bd80 pop {r7, pc} + 800e042: bf00 nop + 800e044: 0801e900 .word 0x0801e900 + 800e048: 0801e930 .word 0x0801e930 + 800e04c: 0801e950 .word 0x0801e950 + +0800e050 : + * @param inp the network interface on which the packet was received + * @param input_fn input function to call + */ +err_t +tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn) +{ + 800e050: b580 push {r7, lr} + 800e052: b086 sub sp, #24 + 800e054: af00 add r7, sp, #0 + 800e056: 60f8 str r0, [r7, #12] + 800e058: 60b9 str r1, [r7, #8] + 800e05a: 607a str r2, [r7, #4] + UNLOCK_TCPIP_CORE(); + return ret; +#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + 800e05c: 481a ldr r0, [pc, #104] ; (800e0c8 ) + 800e05e: f00d fd4c bl 801bafa + 800e062: 4603 mov r3, r0 + 800e064: 2b00 cmp r3, #0 + 800e066: d105 bne.n 800e074 + 800e068: 4b18 ldr r3, [pc, #96] ; (800e0cc ) + 800e06a: 22fc movs r2, #252 ; 0xfc + 800e06c: 4918 ldr r1, [pc, #96] ; (800e0d0 ) + 800e06e: 4819 ldr r0, [pc, #100] ; (800e0d4 ) + 800e070: f00d ffd0 bl 801c014 + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT); + 800e074: 2009 movs r0, #9 + 800e076: f001 fd9d bl 800fbb4 + 800e07a: 6178 str r0, [r7, #20] + if (msg == NULL) { + 800e07c: 697b ldr r3, [r7, #20] + 800e07e: 2b00 cmp r3, #0 + 800e080: d102 bne.n 800e088 + return ERR_MEM; + 800e082: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800e086: e01a b.n 800e0be + } + + msg->type = TCPIP_MSG_INPKT; + 800e088: 697b ldr r3, [r7, #20] + 800e08a: 2200 movs r2, #0 + 800e08c: 701a strb r2, [r3, #0] + msg->msg.inp.p = p; + 800e08e: 697b ldr r3, [r7, #20] + 800e090: 68fa ldr r2, [r7, #12] + 800e092: 605a str r2, [r3, #4] + msg->msg.inp.netif = inp; + 800e094: 697b ldr r3, [r7, #20] + 800e096: 68ba ldr r2, [r7, #8] + 800e098: 609a str r2, [r3, #8] + msg->msg.inp.input_fn = input_fn; + 800e09a: 697b ldr r3, [r7, #20] + 800e09c: 687a ldr r2, [r7, #4] + 800e09e: 60da str r2, [r3, #12] + if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { + 800e0a0: 6979 ldr r1, [r7, #20] + 800e0a2: 4809 ldr r0, [pc, #36] ; (800e0c8 ) + 800e0a4: f00d fcd0 bl 801ba48 + 800e0a8: 4603 mov r3, r0 + 800e0aa: 2b00 cmp r3, #0 + 800e0ac: d006 beq.n 800e0bc + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + 800e0ae: 6979 ldr r1, [r7, #20] + 800e0b0: 2009 movs r0, #9 + 800e0b2: f001 fdf5 bl 800fca0 + return ERR_MEM; + 800e0b6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800e0ba: e000 b.n 800e0be + } + return ERR_OK; + 800e0bc: 2300 movs r3, #0 +#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ +} + 800e0be: 4618 mov r0, r3 + 800e0c0: 3718 adds r7, #24 + 800e0c2: 46bd mov sp, r7 + 800e0c4: bd80 pop {r7, pc} + 800e0c6: bf00 nop + 800e0c8: 200091dc .word 0x200091dc + 800e0cc: 0801e900 .word 0x0801e900 + 800e0d0: 0801e978 .word 0x0801e978 + 800e0d4: 0801e950 .word 0x0801e950 + +0800e0d8 : + * NETIF_FLAG_ETHERNET flags) + * @param inp the network interface on which the packet was received + */ +err_t +tcpip_input(struct pbuf *p, struct netif *inp) +{ + 800e0d8: b580 push {r7, lr} + 800e0da: b082 sub sp, #8 + 800e0dc: af00 add r7, sp, #0 + 800e0de: 6078 str r0, [r7, #4] + 800e0e0: 6039 str r1, [r7, #0] +#if LWIP_ETHERNET + if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { + 800e0e2: 683b ldr r3, [r7, #0] + 800e0e4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 800e0e8: f003 0318 and.w r3, r3, #24 + 800e0ec: 2b00 cmp r3, #0 + 800e0ee: d006 beq.n 800e0fe + return tcpip_inpkt(p, inp, ethernet_input); + 800e0f0: 4a08 ldr r2, [pc, #32] ; (800e114 ) + 800e0f2: 6839 ldr r1, [r7, #0] + 800e0f4: 6878 ldr r0, [r7, #4] + 800e0f6: f7ff ffab bl 800e050 + 800e0fa: 4603 mov r3, r0 + 800e0fc: e005 b.n 800e10a + } else +#endif /* LWIP_ETHERNET */ + return tcpip_inpkt(p, inp, ip_input); + 800e0fe: 4a06 ldr r2, [pc, #24] ; (800e118 ) + 800e100: 6839 ldr r1, [r7, #0] + 800e102: 6878 ldr r0, [r7, #4] + 800e104: f7ff ffa4 bl 800e050 + 800e108: 4603 mov r3, r0 +} + 800e10a: 4618 mov r0, r3 + 800e10c: 3708 adds r7, #8 + 800e10e: 46bd mov sp, r7 + 800e110: bd80 pop {r7, pc} + 800e112: bf00 nop + 800e114: 0801b859 .word 0x0801b859 + 800e118: 0801a3b1 .word 0x0801a3b1 + +0800e11c : + * + * @see tcpip_callback + */ +err_t +tcpip_try_callback(tcpip_callback_fn function, void *ctx) +{ + 800e11c: b580 push {r7, lr} + 800e11e: b084 sub sp, #16 + 800e120: af00 add r7, sp, #0 + 800e122: 6078 str r0, [r7, #4] + 800e124: 6039 str r1, [r7, #0] + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + 800e126: 4819 ldr r0, [pc, #100] ; (800e18c ) + 800e128: f00d fce7 bl 801bafa + 800e12c: 4603 mov r3, r0 + 800e12e: 2b00 cmp r3, #0 + 800e130: d106 bne.n 800e140 + 800e132: 4b17 ldr r3, [pc, #92] ; (800e190 ) + 800e134: f240 125d movw r2, #349 ; 0x15d + 800e138: 4916 ldr r1, [pc, #88] ; (800e194 ) + 800e13a: 4817 ldr r0, [pc, #92] ; (800e198 ) + 800e13c: f00d ff6a bl 801c014 + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + 800e140: 2008 movs r0, #8 + 800e142: f001 fd37 bl 800fbb4 + 800e146: 60f8 str r0, [r7, #12] + if (msg == NULL) { + 800e148: 68fb ldr r3, [r7, #12] + 800e14a: 2b00 cmp r3, #0 + 800e14c: d102 bne.n 800e154 + return ERR_MEM; + 800e14e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800e152: e017 b.n 800e184 + } + + msg->type = TCPIP_MSG_CALLBACK; + 800e154: 68fb ldr r3, [r7, #12] + 800e156: 2201 movs r2, #1 + 800e158: 701a strb r2, [r3, #0] + msg->msg.cb.function = function; + 800e15a: 68fb ldr r3, [r7, #12] + 800e15c: 687a ldr r2, [r7, #4] + 800e15e: 605a str r2, [r3, #4] + msg->msg.cb.ctx = ctx; + 800e160: 68fb ldr r3, [r7, #12] + 800e162: 683a ldr r2, [r7, #0] + 800e164: 609a str r2, [r3, #8] + + if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { + 800e166: 68f9 ldr r1, [r7, #12] + 800e168: 4808 ldr r0, [pc, #32] ; (800e18c ) + 800e16a: f00d fc6d bl 801ba48 + 800e16e: 4603 mov r3, r0 + 800e170: 2b00 cmp r3, #0 + 800e172: d006 beq.n 800e182 + memp_free(MEMP_TCPIP_MSG_API, msg); + 800e174: 68f9 ldr r1, [r7, #12] + 800e176: 2008 movs r0, #8 + 800e178: f001 fd92 bl 800fca0 + return ERR_MEM; + 800e17c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800e180: e000 b.n 800e184 + } + return ERR_OK; + 800e182: 2300 movs r3, #0 +} + 800e184: 4618 mov r0, r3 + 800e186: 3710 adds r7, #16 + 800e188: 46bd mov sp, r7 + 800e18a: bd80 pop {r7, pc} + 800e18c: 200091dc .word 0x200091dc + 800e190: 0801e900 .word 0x0801e900 + 800e194: 0801e978 .word 0x0801e978 + 800e198: 0801e950 .word 0x0801e950 + +0800e19c : + * @param initfunc a function to call when tcpip_thread is running and finished initializing + * @param arg argument to pass to initfunc + */ +void +tcpip_init(tcpip_init_done_fn initfunc, void *arg) +{ + 800e19c: b580 push {r7, lr} + 800e19e: b084 sub sp, #16 + 800e1a0: af02 add r7, sp, #8 + 800e1a2: 6078 str r0, [r7, #4] + 800e1a4: 6039 str r1, [r7, #0] + lwip_init(); + 800e1a6: f001 f859 bl 800f25c + + tcpip_init_done = initfunc; + 800e1aa: 4a17 ldr r2, [pc, #92] ; (800e208 ) + 800e1ac: 687b ldr r3, [r7, #4] + 800e1ae: 6013 str r3, [r2, #0] + tcpip_init_done_arg = arg; + 800e1b0: 4a16 ldr r2, [pc, #88] ; (800e20c ) + 800e1b2: 683b ldr r3, [r7, #0] + 800e1b4: 6013 str r3, [r2, #0] + if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) { + 800e1b6: 2106 movs r1, #6 + 800e1b8: 4815 ldr r0, [pc, #84] ; (800e210 ) + 800e1ba: f00d fc23 bl 801ba04 + 800e1be: 4603 mov r3, r0 + 800e1c0: 2b00 cmp r3, #0 + 800e1c2: d006 beq.n 800e1d2 + LWIP_ASSERT("failed to create tcpip_thread mbox", 0); + 800e1c4: 4b13 ldr r3, [pc, #76] ; (800e214 ) + 800e1c6: f240 2261 movw r2, #609 ; 0x261 + 800e1ca: 4913 ldr r1, [pc, #76] ; (800e218 ) + 800e1cc: 4813 ldr r0, [pc, #76] ; (800e21c ) + 800e1ce: f00d ff21 bl 801c014 + } +#if LWIP_TCPIP_CORE_LOCKING + if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) { + 800e1d2: 4813 ldr r0, [pc, #76] ; (800e220 ) + 800e1d4: f00d fcb0 bl 801bb38 + 800e1d8: 4603 mov r3, r0 + 800e1da: 2b00 cmp r3, #0 + 800e1dc: d006 beq.n 800e1ec + LWIP_ASSERT("failed to create lock_tcpip_core", 0); + 800e1de: 4b0d ldr r3, [pc, #52] ; (800e214 ) + 800e1e0: f240 2265 movw r2, #613 ; 0x265 + 800e1e4: 490f ldr r1, [pc, #60] ; (800e224 ) + 800e1e6: 480d ldr r0, [pc, #52] ; (800e21c ) + 800e1e8: f00d ff14 bl 801c014 + } +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); + 800e1ec: 2300 movs r3, #0 + 800e1ee: 9300 str r3, [sp, #0] + 800e1f0: f44f 6380 mov.w r3, #1024 ; 0x400 + 800e1f4: 2200 movs r2, #0 + 800e1f6: 490c ldr r1, [pc, #48] ; (800e228 ) + 800e1f8: 480c ldr r0, [pc, #48] ; (800e22c ) + 800e1fa: f00d fcd5 bl 801bba8 +} + 800e1fe: bf00 nop + 800e200: 3708 adds r7, #8 + 800e202: 46bd mov sp, r7 + 800e204: bd80 pop {r7, pc} + 800e206: bf00 nop + 800e208: 200091d4 .word 0x200091d4 + 800e20c: 200091d8 .word 0x200091d8 + 800e210: 200091dc .word 0x200091dc + 800e214: 0801e900 .word 0x0801e900 + 800e218: 0801e988 .word 0x0801e988 + 800e21c: 0801e950 .word 0x0801e950 + 800e220: 200091e0 .word 0x200091e0 + 800e224: 0801e9ac .word 0x0801e9ac + 800e228: 0800df59 .word 0x0800df59 + 800e22c: 0801e9d0 .word 0x0801e9d0 + +0800e230 : + * @param n u16_t in host byte order + * @return n in network byte order + */ +u16_t +lwip_htons(u16_t n) +{ + 800e230: b480 push {r7} + 800e232: b083 sub sp, #12 + 800e234: af00 add r7, sp, #0 + 800e236: 4603 mov r3, r0 + 800e238: 80fb strh r3, [r7, #6] + return PP_HTONS(n); + 800e23a: 88fb ldrh r3, [r7, #6] + 800e23c: 021b lsls r3, r3, #8 + 800e23e: b21a sxth r2, r3 + 800e240: 88fb ldrh r3, [r7, #6] + 800e242: 0a1b lsrs r3, r3, #8 + 800e244: b29b uxth r3, r3 + 800e246: b21b sxth r3, r3 + 800e248: 4313 orrs r3, r2 + 800e24a: b21b sxth r3, r3 + 800e24c: b29b uxth r3, r3 +} + 800e24e: 4618 mov r0, r3 + 800e250: 370c adds r7, #12 + 800e252: 46bd mov sp, r7 + 800e254: f85d 7b04 ldr.w r7, [sp], #4 + 800e258: 4770 bx lr + +0800e25a : + * @param n u32_t in host byte order + * @return n in network byte order + */ +u32_t +lwip_htonl(u32_t n) +{ + 800e25a: b480 push {r7} + 800e25c: b083 sub sp, #12 + 800e25e: af00 add r7, sp, #0 + 800e260: 6078 str r0, [r7, #4] + return PP_HTONL(n); + 800e262: 687b ldr r3, [r7, #4] + 800e264: 061a lsls r2, r3, #24 + 800e266: 687b ldr r3, [r7, #4] + 800e268: 021b lsls r3, r3, #8 + 800e26a: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 800e26e: 431a orrs r2, r3 + 800e270: 687b ldr r3, [r7, #4] + 800e272: 0a1b lsrs r3, r3, #8 + 800e274: f403 437f and.w r3, r3, #65280 ; 0xff00 + 800e278: 431a orrs r2, r3 + 800e27a: 687b ldr r3, [r7, #4] + 800e27c: 0e1b lsrs r3, r3, #24 + 800e27e: 4313 orrs r3, r2 +} + 800e280: 4618 mov r0, r3 + 800e282: 370c adds r7, #12 + 800e284: 46bd mov sp, r7 + 800e286: f85d 7b04 ldr.w r7, [sp], #4 + 800e28a: 4770 bx lr + +0800e28c : + * lwIP default implementation for strnicmp() non-standard function. + * This can be \#defined to strnicmp() depending on your platform port. + */ +int +lwip_strnicmp(const char *str1, const char *str2, size_t len) +{ + 800e28c: b480 push {r7} + 800e28e: b087 sub sp, #28 + 800e290: af00 add r7, sp, #0 + 800e292: 60f8 str r0, [r7, #12] + 800e294: 60b9 str r1, [r7, #8] + 800e296: 607a str r2, [r7, #4] + char c1, c2; + + do { + c1 = *str1++; + 800e298: 68fb ldr r3, [r7, #12] + 800e29a: 1c5a adds r2, r3, #1 + 800e29c: 60fa str r2, [r7, #12] + 800e29e: 781b ldrb r3, [r3, #0] + 800e2a0: 75fb strb r3, [r7, #23] + c2 = *str2++; + 800e2a2: 68bb ldr r3, [r7, #8] + 800e2a4: 1c5a adds r2, r3, #1 + 800e2a6: 60ba str r2, [r7, #8] + 800e2a8: 781b ldrb r3, [r3, #0] + 800e2aa: 75bb strb r3, [r7, #22] + if (c1 != c2) { + 800e2ac: 7dfa ldrb r2, [r7, #23] + 800e2ae: 7dbb ldrb r3, [r7, #22] + 800e2b0: 429a cmp r2, r3 + 800e2b2: d016 beq.n 800e2e2 + char c1_upc = c1 | 0x20; + 800e2b4: 7dfb ldrb r3, [r7, #23] + 800e2b6: f043 0320 orr.w r3, r3, #32 + 800e2ba: 757b strb r3, [r7, #21] + if ((c1_upc >= 'a') && (c1_upc <= 'z')) { + 800e2bc: 7d7b ldrb r3, [r7, #21] + 800e2be: 2b60 cmp r3, #96 ; 0x60 + 800e2c0: d90c bls.n 800e2dc + 800e2c2: 7d7b ldrb r3, [r7, #21] + 800e2c4: 2b7a cmp r3, #122 ; 0x7a + 800e2c6: d809 bhi.n 800e2dc + /* characters are not equal an one is in the alphabet range: + downcase both chars and check again */ + char c2_upc = c2 | 0x20; + 800e2c8: 7dbb ldrb r3, [r7, #22] + 800e2ca: f043 0320 orr.w r3, r3, #32 + 800e2ce: 753b strb r3, [r7, #20] + if (c1_upc != c2_upc) { + 800e2d0: 7d7a ldrb r2, [r7, #21] + 800e2d2: 7d3b ldrb r3, [r7, #20] + 800e2d4: 429a cmp r2, r3 + 800e2d6: d003 beq.n 800e2e0 + /* still not equal */ + /* don't care for < or > */ + return 1; + 800e2d8: 2301 movs r3, #1 + 800e2da: e00c b.n 800e2f6 + } + } else { + /* characters are not equal but none is in the alphabet range */ + return 1; + 800e2dc: 2301 movs r3, #1 + 800e2de: e00a b.n 800e2f6 + if ((c1_upc >= 'a') && (c1_upc <= 'z')) { + 800e2e0: bf00 nop + } + } + len--; + 800e2e2: 687b ldr r3, [r7, #4] + 800e2e4: 3b01 subs r3, #1 + 800e2e6: 607b str r3, [r7, #4] + } while ((len != 0) && (c1 != 0)); + 800e2e8: 687b ldr r3, [r7, #4] + 800e2ea: 2b00 cmp r3, #0 + 800e2ec: d002 beq.n 800e2f4 + 800e2ee: 7dfb ldrb r3, [r7, #23] + 800e2f0: 2b00 cmp r3, #0 + 800e2f2: d1d1 bne.n 800e298 + return 0; + 800e2f4: 2300 movs r3, #0 +} + 800e2f6: 4618 mov r0, r3 + 800e2f8: 371c adds r7, #28 + 800e2fa: 46bd mov sp, r7 + 800e2fc: f85d 7b04 ldr.w r7, [sp], #4 + 800e300: 4770 bx lr + +0800e302 : + * Initialize the resolver: set up the UDP pcb and configure the default server + * (if DNS_SERVER_ADDRESS is set). + */ +void +dns_init(void) +{ + 800e302: b480 push {r7} + 800e304: af00 add r7, sp, #0 +#endif + +#if DNS_LOCAL_HOSTLIST + dns_init_local(); +#endif +} + 800e306: bf00 nop + 800e308: 46bd mov sp, r7 + 800e30a: f85d 7b04 ldr.w r7, [sp], #4 + 800e30e: 4770 bx lr + +0800e310 : + * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS + * @param dnsserver IP address of the DNS server to set + */ +void +dns_setserver(u8_t numdns, const ip_addr_t *dnsserver) +{ + 800e310: b480 push {r7} + 800e312: b083 sub sp, #12 + 800e314: af00 add r7, sp, #0 + 800e316: 4603 mov r3, r0 + 800e318: 6039 str r1, [r7, #0] + 800e31a: 71fb strb r3, [r7, #7] + if (numdns < DNS_MAX_SERVERS) { + 800e31c: 79fb ldrb r3, [r7, #7] + 800e31e: 2b01 cmp r3, #1 + 800e320: d80f bhi.n 800e342 + if (dnsserver != NULL) { + 800e322: 683b ldr r3, [r7, #0] + 800e324: 2b00 cmp r3, #0 + 800e326: d006 beq.n 800e336 + dns_servers[numdns] = (*dnsserver); + 800e328: 79fb ldrb r3, [r7, #7] + 800e32a: 4909 ldr r1, [pc, #36] ; (800e350 ) + 800e32c: 683a ldr r2, [r7, #0] + 800e32e: 6812 ldr r2, [r2, #0] + 800e330: f841 2023 str.w r2, [r1, r3, lsl #2] + } else { + dns_servers[numdns] = *IP_ADDR_ANY; + } + } +} + 800e334: e005 b.n 800e342 + dns_servers[numdns] = *IP_ADDR_ANY; + 800e336: 79fb ldrb r3, [r7, #7] + 800e338: 4905 ldr r1, [pc, #20] ; (800e350 ) + 800e33a: 4a06 ldr r2, [pc, #24] ; (800e354 ) + 800e33c: 6812 ldr r2, [r2, #0] + 800e33e: f841 2023 str.w r2, [r1, r3, lsl #2] +} + 800e342: bf00 nop + 800e344: 370c adds r7, #12 + 800e346: 46bd mov sp, r7 + 800e348: f85d 7b04 ldr.w r7, [sp], #4 + 800e34c: 4770 bx lr + 800e34e: bf00 nop + 800e350: 20009668 .word 0x20009668 + 800e354: 08023914 .word 0x08023914 + +0800e358 : + * The DNS resolver client timer - handle retries and timeouts and should + * be called every DNS_TMR_INTERVAL milliseconds (every second by default). + */ +void +dns_tmr(void) +{ + 800e358: b580 push {r7, lr} + 800e35a: af00 add r7, sp, #0 + LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n")); + dns_check_entries(); + 800e35c: f000 fc54 bl 800ec08 +} + 800e360: bf00 nop + 800e362: bd80 pop {r7, pc} + +0800e364 : + * was not found in the cached dns_table. + * @return ERR_OK if found, ERR_ARG if not found + */ +static err_t +dns_lookup(const char *name, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)) +{ + 800e364: b580 push {r7, lr} + 800e366: b084 sub sp, #16 + 800e368: af00 add r7, sp, #0 + 800e36a: 6078 str r0, [r7, #4] + 800e36c: 6039 str r1, [r7, #0] + return ERR_OK; + } +#endif /* DNS_LOOKUP_LOCAL_EXTERN */ + + /* Walk through name list, return entry if found. If not, return NULL. */ + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800e36e: 2300 movs r3, #0 + 800e370: 73fb strb r3, [r7, #15] + 800e372: e02e b.n 800e3d2 + if ((dns_table[i].state == DNS_STATE_DONE) && + 800e374: 7bfa ldrb r2, [r7, #15] + 800e376: 491b ldr r1, [pc, #108] ; (800e3e4 ) + 800e378: 4613 mov r3, r2 + 800e37a: 011b lsls r3, r3, #4 + 800e37c: 4413 add r3, r2 + 800e37e: 011b lsls r3, r3, #4 + 800e380: 440b add r3, r1 + 800e382: 330a adds r3, #10 + 800e384: 781b ldrb r3, [r3, #0] + 800e386: 2b03 cmp r3, #3 + 800e388: d120 bne.n 800e3cc + (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0) && + 800e38a: 7bfa ldrb r2, [r7, #15] + 800e38c: 4613 mov r3, r2 + 800e38e: 011b lsls r3, r3, #4 + 800e390: 4413 add r3, r2 + 800e392: 011b lsls r3, r3, #4 + 800e394: 3310 adds r3, #16 + 800e396: 4a13 ldr r2, [pc, #76] ; (800e3e4 ) + 800e398: 4413 add r3, r2 + 800e39a: f44f 7280 mov.w r2, #256 ; 0x100 + 800e39e: 4619 mov r1, r3 + 800e3a0: 6878 ldr r0, [r7, #4] + 800e3a2: f7ff ff73 bl 800e28c + 800e3a6: 4603 mov r3, r0 + if ((dns_table[i].state == DNS_STATE_DONE) && + 800e3a8: 2b00 cmp r3, #0 + 800e3aa: d10f bne.n 800e3cc + LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, dns_table[i].ipaddr)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name)); + ip_addr_debug_print_val(DNS_DEBUG, dns_table[i].ipaddr); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + if (addr) { + 800e3ac: 683b ldr r3, [r7, #0] + 800e3ae: 2b00 cmp r3, #0 + 800e3b0: d00a beq.n 800e3c8 + ip_addr_copy(*addr, dns_table[i].ipaddr); + 800e3b2: 7bfa ldrb r2, [r7, #15] + 800e3b4: 490b ldr r1, [pc, #44] ; (800e3e4 ) + 800e3b6: 4613 mov r3, r2 + 800e3b8: 011b lsls r3, r3, #4 + 800e3ba: 4413 add r3, r2 + 800e3bc: 011b lsls r3, r3, #4 + 800e3be: 440b add r3, r1 + 800e3c0: 3304 adds r3, #4 + 800e3c2: 681a ldr r2, [r3, #0] + 800e3c4: 683b ldr r3, [r7, #0] + 800e3c6: 601a str r2, [r3, #0] + } + return ERR_OK; + 800e3c8: 2300 movs r3, #0 + 800e3ca: e007 b.n 800e3dc + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800e3cc: 7bfb ldrb r3, [r7, #15] + 800e3ce: 3301 adds r3, #1 + 800e3d0: 73fb strb r3, [r7, #15] + 800e3d2: 7bfb ldrb r3, [r7, #15] + 800e3d4: 2b03 cmp r3, #3 + 800e3d6: d9cd bls.n 800e374 + } + } + + return ERR_ARG; + 800e3d8: f06f 030f mvn.w r3, #15 +} + 800e3dc: 4618 mov r0, r3 + 800e3de: 3710 adds r7, #16 + 800e3e0: 46bd mov sp, r7 + 800e3e2: bd80 pop {r7, pc} + 800e3e4: 200091f8 .word 0x200091f8 + +0800e3e8 : + * @param start_offset offset into p where the name starts + * @return 0xFFFF: names differ, other: names equal -> offset behind name + */ +static u16_t +dns_compare_name(const char *query, struct pbuf *p, u16_t start_offset) +{ + 800e3e8: b580 push {r7, lr} + 800e3ea: b088 sub sp, #32 + 800e3ec: af00 add r7, sp, #0 + 800e3ee: 60f8 str r0, [r7, #12] + 800e3f0: 60b9 str r1, [r7, #8] + 800e3f2: 4613 mov r3, r2 + 800e3f4: 80fb strh r3, [r7, #6] + int n; + u16_t response_offset = start_offset; + 800e3f6: 88fb ldrh r3, [r7, #6] + 800e3f8: 837b strh r3, [r7, #26] + + do { + n = pbuf_try_get_at(p, response_offset); + 800e3fa: 8b7b ldrh r3, [r7, #26] + 800e3fc: 4619 mov r1, r3 + 800e3fe: 68b8 ldr r0, [r7, #8] + 800e400: f002 fee0 bl 80111c4 + 800e404: 61f8 str r0, [r7, #28] + if ((n < 0) || (response_offset == 0xFFFF)) { + 800e406: 69fb ldr r3, [r7, #28] + 800e408: 2b00 cmp r3, #0 + 800e40a: db04 blt.n 800e416 + 800e40c: 8b7b ldrh r3, [r7, #26] + 800e40e: f64f 72ff movw r2, #65535 ; 0xffff + 800e412: 4293 cmp r3, r2 + 800e414: d102 bne.n 800e41c + /* error or overflow */ + return 0xFFFF; + 800e416: f64f 73ff movw r3, #65535 ; 0xffff + 800e41a: e06c b.n 800e4f6 + } + response_offset++; + 800e41c: 8b7b ldrh r3, [r7, #26] + 800e41e: 3301 adds r3, #1 + 800e420: 837b strh r3, [r7, #26] + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + 800e422: 69fb ldr r3, [r7, #28] + 800e424: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 800e428: 2bc0 cmp r3, #192 ; 0xc0 + 800e42a: d144 bne.n 800e4b6 + /* Compressed name: cannot be equal since we don't send them */ + return 0xFFFF; + 800e42c: f64f 73ff movw r3, #65535 ; 0xffff + 800e430: e061 b.n 800e4f6 + } else { + /* Not compressed name */ + while (n > 0) { + int c = pbuf_try_get_at(p, response_offset); + 800e432: 8b7b ldrh r3, [r7, #26] + 800e434: 4619 mov r1, r3 + 800e436: 68b8 ldr r0, [r7, #8] + 800e438: f002 fec4 bl 80111c4 + 800e43c: 6178 str r0, [r7, #20] + if (c < 0) { + 800e43e: 697b ldr r3, [r7, #20] + 800e440: 2b00 cmp r3, #0 + 800e442: da02 bge.n 800e44a + return 0xFFFF; + 800e444: f64f 73ff movw r3, #65535 ; 0xffff + 800e448: e055 b.n 800e4f6 + } + if (lwip_tolower((*query)) != lwip_tolower((u8_t)c)) { + 800e44a: 68fb ldr r3, [r7, #12] + 800e44c: 781b ldrb r3, [r3, #0] + 800e44e: 74fb strb r3, [r7, #19] + 800e450: 7cfb ldrb r3, [r7, #19] + 800e452: 3301 adds r3, #1 + 800e454: 4a2a ldr r2, [pc, #168] ; (800e500 ) + 800e456: 4413 add r3, r2 + 800e458: 781b ldrb r3, [r3, #0] + 800e45a: f003 0303 and.w r3, r3, #3 + 800e45e: 2b01 cmp r3, #1 + 800e460: d103 bne.n 800e46a + 800e462: 7cfb ldrb r3, [r7, #19] + 800e464: f103 0220 add.w r2, r3, #32 + 800e468: e000 b.n 800e46c + 800e46a: 7cfa ldrb r2, [r7, #19] + 800e46c: 697b ldr r3, [r7, #20] + 800e46e: 74bb strb r3, [r7, #18] + 800e470: 7cbb ldrb r3, [r7, #18] + 800e472: 3301 adds r3, #1 + 800e474: 4922 ldr r1, [pc, #136] ; (800e500 ) + 800e476: 440b add r3, r1 + 800e478: 781b ldrb r3, [r3, #0] + 800e47a: f003 0303 and.w r3, r3, #3 + 800e47e: 2b01 cmp r3, #1 + 800e480: d102 bne.n 800e488 + 800e482: 7cbb ldrb r3, [r7, #18] + 800e484: 3320 adds r3, #32 + 800e486: e000 b.n 800e48a + 800e488: 7cbb ldrb r3, [r7, #18] + 800e48a: 429a cmp r2, r3 + 800e48c: d002 beq.n 800e494 + return 0xFFFF; + 800e48e: f64f 73ff movw r3, #65535 ; 0xffff + 800e492: e030 b.n 800e4f6 + } + if (response_offset == 0xFFFF) { + 800e494: 8b7b ldrh r3, [r7, #26] + 800e496: f64f 72ff movw r2, #65535 ; 0xffff + 800e49a: 4293 cmp r3, r2 + 800e49c: d102 bne.n 800e4a4 + /* would overflow */ + return 0xFFFF; + 800e49e: f64f 73ff movw r3, #65535 ; 0xffff + 800e4a2: e028 b.n 800e4f6 + } + response_offset++; + 800e4a4: 8b7b ldrh r3, [r7, #26] + 800e4a6: 3301 adds r3, #1 + 800e4a8: 837b strh r3, [r7, #26] + ++query; + 800e4aa: 68fb ldr r3, [r7, #12] + 800e4ac: 3301 adds r3, #1 + 800e4ae: 60fb str r3, [r7, #12] + --n; + 800e4b0: 69fb ldr r3, [r7, #28] + 800e4b2: 3b01 subs r3, #1 + 800e4b4: 61fb str r3, [r7, #28] + while (n > 0) { + 800e4b6: 69fb ldr r3, [r7, #28] + 800e4b8: 2b00 cmp r3, #0 + 800e4ba: dcba bgt.n 800e432 + } + ++query; + 800e4bc: 68fb ldr r3, [r7, #12] + 800e4be: 3301 adds r3, #1 + 800e4c0: 60fb str r3, [r7, #12] + } + n = pbuf_try_get_at(p, response_offset); + 800e4c2: 8b7b ldrh r3, [r7, #26] + 800e4c4: 4619 mov r1, r3 + 800e4c6: 68b8 ldr r0, [r7, #8] + 800e4c8: f002 fe7c bl 80111c4 + 800e4cc: 61f8 str r0, [r7, #28] + if (n < 0) { + 800e4ce: 69fb ldr r3, [r7, #28] + 800e4d0: 2b00 cmp r3, #0 + 800e4d2: da02 bge.n 800e4da + return 0xFFFF; + 800e4d4: f64f 73ff movw r3, #65535 ; 0xffff + 800e4d8: e00d b.n 800e4f6 + } + } while (n != 0); + 800e4da: 69fb ldr r3, [r7, #28] + 800e4dc: 2b00 cmp r3, #0 + 800e4de: d18c bne.n 800e3fa + + if (response_offset == 0xFFFF) { + 800e4e0: 8b7b ldrh r3, [r7, #26] + 800e4e2: f64f 72ff movw r2, #65535 ; 0xffff + 800e4e6: 4293 cmp r3, r2 + 800e4e8: d102 bne.n 800e4f0 + /* would overflow */ + return 0xFFFF; + 800e4ea: f64f 73ff movw r3, #65535 ; 0xffff + 800e4ee: e002 b.n 800e4f6 + } + return (u16_t)(response_offset + 1); + 800e4f0: 8b7b ldrh r3, [r7, #26] + 800e4f2: 3301 adds r3, #1 + 800e4f4: b29b uxth r3, r3 +} + 800e4f6: 4618 mov r0, r3 + 800e4f8: 3720 adds r7, #32 + 800e4fa: 46bd mov sp, r7 + 800e4fc: bd80 pop {r7, pc} + 800e4fe: bf00 nop + 800e500: 08023934 .word 0x08023934 + +0800e504 : + * @param query_idx start index into p pointing to encoded DNS name in the DNS server response + * @return index to end of the name + */ +static u16_t +dns_skip_name(struct pbuf *p, u16_t query_idx) +{ + 800e504: b580 push {r7, lr} + 800e506: b084 sub sp, #16 + 800e508: af00 add r7, sp, #0 + 800e50a: 6078 str r0, [r7, #4] + 800e50c: 460b mov r3, r1 + 800e50e: 807b strh r3, [r7, #2] + int n; + u16_t offset = query_idx; + 800e510: 887b ldrh r3, [r7, #2] + 800e512: 81fb strh r3, [r7, #14] + + do { + n = pbuf_try_get_at(p, offset++); + 800e514: 89fb ldrh r3, [r7, #14] + 800e516: 1c5a adds r2, r3, #1 + 800e518: 81fa strh r2, [r7, #14] + 800e51a: 4619 mov r1, r3 + 800e51c: 6878 ldr r0, [r7, #4] + 800e51e: f002 fe51 bl 80111c4 + 800e522: 60b8 str r0, [r7, #8] + if ((n < 0) || (offset == 0)) { + 800e524: 68bb ldr r3, [r7, #8] + 800e526: 2b00 cmp r3, #0 + 800e528: db02 blt.n 800e530 + 800e52a: 89fb ldrh r3, [r7, #14] + 800e52c: 2b00 cmp r3, #0 + 800e52e: d102 bne.n 800e536 + return 0xFFFF; + 800e530: f64f 73ff movw r3, #65535 ; 0xffff + 800e534: e02f b.n 800e596 + } + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + 800e536: 68bb ldr r3, [r7, #8] + 800e538: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 800e53c: 2bc0 cmp r3, #192 ; 0xc0 + 800e53e: d01e beq.n 800e57e + /* Compressed name: since we only want to skip it (not check it), stop here */ + break; + } else { + /* Not compressed name */ + if (offset + n >= p->tot_len) { + 800e540: 89fa ldrh r2, [r7, #14] + 800e542: 68bb ldr r3, [r7, #8] + 800e544: 4413 add r3, r2 + 800e546: 687a ldr r2, [r7, #4] + 800e548: 8912 ldrh r2, [r2, #8] + 800e54a: 4293 cmp r3, r2 + 800e54c: db02 blt.n 800e554 + return 0xFFFF; + 800e54e: f64f 73ff movw r3, #65535 ; 0xffff + 800e552: e020 b.n 800e596 + } + offset = (u16_t)(offset + n); + 800e554: 68bb ldr r3, [r7, #8] + 800e556: b29a uxth r2, r3 + 800e558: 89fb ldrh r3, [r7, #14] + 800e55a: 4413 add r3, r2 + 800e55c: 81fb strh r3, [r7, #14] + } + n = pbuf_try_get_at(p, offset); + 800e55e: 89fb ldrh r3, [r7, #14] + 800e560: 4619 mov r1, r3 + 800e562: 6878 ldr r0, [r7, #4] + 800e564: f002 fe2e bl 80111c4 + 800e568: 60b8 str r0, [r7, #8] + if (n < 0) { + 800e56a: 68bb ldr r3, [r7, #8] + 800e56c: 2b00 cmp r3, #0 + 800e56e: da02 bge.n 800e576 + return 0xFFFF; + 800e570: f64f 73ff movw r3, #65535 ; 0xffff + 800e574: e00f b.n 800e596 + } + } while (n != 0); + 800e576: 68bb ldr r3, [r7, #8] + 800e578: 2b00 cmp r3, #0 + 800e57a: d1cb bne.n 800e514 + 800e57c: e000 b.n 800e580 + break; + 800e57e: bf00 nop + + if (offset == 0xFFFF) { + 800e580: 89fb ldrh r3, [r7, #14] + 800e582: f64f 72ff movw r2, #65535 ; 0xffff + 800e586: 4293 cmp r3, r2 + 800e588: d102 bne.n 800e590 + return 0xFFFF; + 800e58a: f64f 73ff movw r3, #65535 ; 0xffff + 800e58e: e002 b.n 800e596 + } + return (u16_t)(offset + 1); + 800e590: 89fb ldrh r3, [r7, #14] + 800e592: 3301 adds r3, #1 + 800e594: b29b uxth r3, r3 +} + 800e596: 4618 mov r0, r3 + 800e598: 3710 adds r7, #16 + 800e59a: 46bd mov sp, r7 + 800e59c: bd80 pop {r7, pc} + ... + +0800e5a0 : + * @param idx the DNS table entry index for which to send a request + * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise + */ +static err_t +dns_send(u8_t idx) +{ + 800e5a0: b580 push {r7, lr} + 800e5a2: b090 sub sp, #64 ; 0x40 + 800e5a4: af00 add r7, sp, #0 + 800e5a6: 4603 mov r3, r0 + 800e5a8: 71fb strb r3, [r7, #7] + struct pbuf *p; + u16_t query_idx, copy_len; + const char *hostname, *hostname_part; + u8_t n; + u8_t pcb_idx; + struct dns_table_entry *entry = &dns_table[idx]; + 800e5aa: 79fa ldrb r2, [r7, #7] + 800e5ac: 4613 mov r3, r2 + 800e5ae: 011b lsls r3, r3, #4 + 800e5b0: 4413 add r3, r2 + 800e5b2: 011b lsls r3, r3, #4 + 800e5b4: 4a6c ldr r2, [pc, #432] ; (800e768 ) + 800e5b6: 4413 add r3, r2 + 800e5b8: 633b str r3, [r7, #48] ; 0x30 + + LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n", + (u16_t)(entry->server_idx), entry->name)); + LWIP_ASSERT("dns server out of array", entry->server_idx < DNS_MAX_SERVERS); + 800e5ba: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e5bc: 7adb ldrb r3, [r3, #11] + 800e5be: 2b01 cmp r3, #1 + 800e5c0: d906 bls.n 800e5d0 + 800e5c2: 4b6a ldr r3, [pc, #424] ; (800e76c ) + 800e5c4: f240 22fa movw r2, #762 ; 0x2fa + 800e5c8: 4969 ldr r1, [pc, #420] ; (800e770 ) + 800e5ca: 486a ldr r0, [pc, #424] ; (800e774 ) + 800e5cc: f00d fd22 bl 801c014 + if (ip_addr_isany_val(dns_servers[entry->server_idx]) + 800e5d0: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e5d2: 7adb ldrb r3, [r3, #11] + 800e5d4: 461a mov r2, r3 + 800e5d6: 4b68 ldr r3, [pc, #416] ; (800e778 ) + 800e5d8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800e5dc: 2b00 cmp r3, #0 + 800e5de: d109 bne.n 800e5f4 + && !entry->is_mdns +#endif + ) { + /* DNS server not valid anymore, e.g. PPP netif has been shut down */ + /* call specified callback function if provided */ + dns_call_found(idx, NULL); + 800e5e0: 79fb ldrb r3, [r7, #7] + 800e5e2: 2100 movs r1, #0 + 800e5e4: 4618 mov r0, r3 + 800e5e6: f000 f959 bl 800e89c + /* flush this entry */ + entry->state = DNS_STATE_UNUSED; + 800e5ea: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e5ec: 2200 movs r2, #0 + 800e5ee: 729a strb r2, [r3, #10] + return ERR_OK; + 800e5f0: 2300 movs r3, #0 + 800e5f2: e0b4 b.n 800e75e + } + + /* if here, we have either a new query or a retry on a previous query to process */ + p = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(SIZEOF_DNS_HDR + strlen(entry->name) + 2 + + 800e5f4: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e5f6: 3310 adds r3, #16 + 800e5f8: 4618 mov r0, r3 + 800e5fa: f7f1 fe09 bl 8000210 + 800e5fe: 4603 mov r3, r0 + 800e600: b29b uxth r3, r3 + 800e602: 3312 adds r3, #18 + 800e604: b29b uxth r3, r3 + 800e606: f44f 7220 mov.w r2, #640 ; 0x280 + 800e60a: 4619 mov r1, r3 + 800e60c: 2036 movs r0, #54 ; 0x36 + 800e60e: f001 ff13 bl 8010438 + 800e612: 62f8 str r0, [r7, #44] ; 0x2c + SIZEOF_DNS_QUERY), PBUF_RAM); + if (p != NULL) { + 800e614: 6afb ldr r3, [r7, #44] ; 0x2c + 800e616: 2b00 cmp r3, #0 + 800e618: f000 8095 beq.w 800e746 + const ip_addr_t *dst; + u16_t dst_port; + /* fill dns header */ + memset(&hdr, 0, SIZEOF_DNS_HDR); + 800e61c: f107 0310 add.w r3, r7, #16 + 800e620: 220c movs r2, #12 + 800e622: 2100 movs r1, #0 + 800e624: 4618 mov r0, r3 + 800e626: f00d fc58 bl 801beda + hdr.id = lwip_htons(entry->txid); + 800e62a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e62c: 891b ldrh r3, [r3, #8] + 800e62e: 4618 mov r0, r3 + 800e630: f7ff fdfe bl 800e230 + 800e634: 4603 mov r3, r0 + 800e636: 823b strh r3, [r7, #16] + hdr.flags1 = DNS_FLAG1_RD; + 800e638: 2301 movs r3, #1 + 800e63a: 74bb strb r3, [r7, #18] + hdr.numquestions = PP_HTONS(1); + 800e63c: f44f 7380 mov.w r3, #256 ; 0x100 + 800e640: 82bb strh r3, [r7, #20] + pbuf_take(p, &hdr, SIZEOF_DNS_HDR); + 800e642: f107 0310 add.w r3, r7, #16 + 800e646: 220c movs r2, #12 + 800e648: 4619 mov r1, r3 + 800e64a: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e64c: f002 fc8c bl 8010f68 + hostname = entry->name; + 800e650: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e652: 3310 adds r3, #16 + 800e654: 63bb str r3, [r7, #56] ; 0x38 + --hostname; + 800e656: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e658: 3b01 subs r3, #1 + 800e65a: 63bb str r3, [r7, #56] ; 0x38 + + /* convert hostname into suitable query format. */ + query_idx = SIZEOF_DNS_HDR; + 800e65c: 230c movs r3, #12 + 800e65e: 87bb strh r3, [r7, #60] ; 0x3c + do { + ++hostname; + 800e660: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e662: 3301 adds r3, #1 + 800e664: 63bb str r3, [r7, #56] ; 0x38 + hostname_part = hostname; + 800e666: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e668: 62bb str r3, [r7, #40] ; 0x28 + for (n = 0; *hostname != '.' && *hostname != 0; ++hostname) { + 800e66a: 2300 movs r3, #0 + 800e66c: f887 3037 strb.w r3, [r7, #55] ; 0x37 + 800e670: e007 b.n 800e682 + ++n; + 800e672: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 + 800e676: 3301 adds r3, #1 + 800e678: f887 3037 strb.w r3, [r7, #55] ; 0x37 + for (n = 0; *hostname != '.' && *hostname != 0; ++hostname) { + 800e67c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e67e: 3301 adds r3, #1 + 800e680: 63bb str r3, [r7, #56] ; 0x38 + 800e682: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e684: 781b ldrb r3, [r3, #0] + 800e686: 2b2e cmp r3, #46 ; 0x2e + 800e688: d003 beq.n 800e692 + 800e68a: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e68c: 781b ldrb r3, [r3, #0] + 800e68e: 2b00 cmp r3, #0 + 800e690: d1ef bne.n 800e672 + } + copy_len = (u16_t)(hostname - hostname_part); + 800e692: 6bba ldr r2, [r7, #56] ; 0x38 + 800e694: 6abb ldr r3, [r7, #40] ; 0x28 + 800e696: 1ad3 subs r3, r2, r3 + 800e698: 84fb strh r3, [r7, #38] ; 0x26 + if (query_idx + n + 1 > 0xFFFF) { + 800e69a: 8fba ldrh r2, [r7, #60] ; 0x3c + 800e69c: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 + 800e6a0: 4413 add r3, r2 + 800e6a2: f64f 72fe movw r2, #65534 ; 0xfffe + 800e6a6: 4293 cmp r3, r2 + 800e6a8: dc53 bgt.n 800e752 + /* u16_t overflow */ + goto overflow_return; + } + pbuf_put_at(p, query_idx, n); + 800e6aa: f897 2037 ldrb.w r2, [r7, #55] ; 0x37 + 800e6ae: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e6b0: 4619 mov r1, r3 + 800e6b2: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e6b4: f002 fda8 bl 8011208 + pbuf_take_at(p, hostname_part, copy_len, (u16_t)(query_idx + 1)); + 800e6b8: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e6ba: 3301 adds r3, #1 + 800e6bc: b29b uxth r3, r3 + 800e6be: 8cfa ldrh r2, [r7, #38] ; 0x26 + 800e6c0: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800e6c2: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e6c4: f002 fce2 bl 801108c + query_idx = (u16_t)(query_idx + n + 1); + 800e6c8: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 + 800e6cc: b29a uxth r2, r3 + 800e6ce: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e6d0: 4413 add r3, r2 + 800e6d2: b29b uxth r3, r3 + 800e6d4: 3301 adds r3, #1 + 800e6d6: 87bb strh r3, [r7, #60] ; 0x3c + } while (*hostname != 0); + 800e6d8: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e6da: 781b ldrb r3, [r3, #0] + 800e6dc: 2b00 cmp r3, #0 + 800e6de: d1bf bne.n 800e660 + pbuf_put_at(p, query_idx, 0); + 800e6e0: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e6e2: 2200 movs r2, #0 + 800e6e4: 4619 mov r1, r3 + 800e6e6: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e6e8: f002 fd8e bl 8011208 + query_idx++; + 800e6ec: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e6ee: 3301 adds r3, #1 + 800e6f0: 87bb strh r3, [r7, #60] ; 0x3c + + /* fill dns query */ + if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) { + qry.type = PP_HTONS(DNS_RRTYPE_AAAA); + } else { + qry.type = PP_HTONS(DNS_RRTYPE_A); + 800e6f2: f44f 7380 mov.w r3, #256 ; 0x100 + 800e6f6: 81bb strh r3, [r7, #12] + } + qry.cls = PP_HTONS(DNS_RRCLASS_IN); + 800e6f8: f44f 7380 mov.w r3, #256 ; 0x100 + 800e6fc: 81fb strh r3, [r7, #14] + pbuf_take_at(p, &qry, SIZEOF_DNS_QUERY, query_idx); + 800e6fe: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800e700: f107 010c add.w r1, r7, #12 + 800e704: 2204 movs r2, #4 + 800e706: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e708: f002 fcc0 bl 801108c + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + pcb_idx = entry->pcb_idx; + 800e70c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e70e: 7bdb ldrb r3, [r3, #15] + 800e710: f887 3025 strb.w r3, [r7, #37] ; 0x25 + } +#endif + } else +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + dst_port = DNS_SERVER_PORT; + 800e714: 2335 movs r3, #53 ; 0x35 + 800e716: 847b strh r3, [r7, #34] ; 0x22 + dst = &dns_servers[entry->server_idx]; + 800e718: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e71a: 7adb ldrb r3, [r3, #11] + 800e71c: 009b lsls r3, r3, #2 + 800e71e: 4a16 ldr r2, [pc, #88] ; (800e778 ) + 800e720: 4413 add r3, r2 + 800e722: 61fb str r3, [r7, #28] + } + err = udp_sendto(dns_pcbs[pcb_idx], p, dst, dst_port); + 800e724: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 + 800e728: 4a14 ldr r2, [pc, #80] ; (800e77c ) + 800e72a: f852 0023 ldr.w r0, [r2, r3, lsl #2] + 800e72e: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800e730: 69fa ldr r2, [r7, #28] + 800e732: 6af9 ldr r1, [r7, #44] ; 0x2c + 800e734: f008 fa56 bl 8016be4 + 800e738: 4603 mov r3, r0 + 800e73a: f887 303f strb.w r3, [r7, #63] ; 0x3f + + /* free pbuf */ + pbuf_free(p); + 800e73e: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e740: f002 f95e bl 8010a00 + 800e744: e002 b.n 800e74c + } else { + err = ERR_MEM; + 800e746: 23ff movs r3, #255 ; 0xff + 800e748: f887 303f strb.w r3, [r7, #63] ; 0x3f + } + + return err; + 800e74c: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f + 800e750: e005 b.n 800e75e + goto overflow_return; + 800e752: bf00 nop +overflow_return: + pbuf_free(p); + 800e754: 6af8 ldr r0, [r7, #44] ; 0x2c + 800e756: f002 f953 bl 8010a00 + return ERR_VAL; + 800e75a: f06f 0305 mvn.w r3, #5 +} + 800e75e: 4618 mov r0, r3 + 800e760: 3740 adds r7, #64 ; 0x40 + 800e762: 46bd mov sp, r7 + 800e764: bd80 pop {r7, pc} + 800e766: bf00 nop + 800e768: 200091f8 .word 0x200091f8 + 800e76c: 0801e9e0 .word 0x0801e9e0 + 800e770: 0801ea10 .word 0x0801ea10 + 800e774: 0801ea28 .word 0x0801ea28 + 800e778: 20009668 .word 0x20009668 + 800e77c: 200091e4 .word 0x200091e4 + +0800e780 : + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) +static struct udp_pcb * +dns_alloc_random_port(void) +{ + 800e780: b580 push {r7, lr} + 800e782: b084 sub sp, #16 + 800e784: af00 add r7, sp, #0 + err_t err; + struct udp_pcb *pcb; + + pcb = udp_new_ip_type(IPADDR_TYPE_ANY); + 800e786: 202e movs r0, #46 ; 0x2e + 800e788: f008 fd79 bl 801727e + 800e78c: 60b8 str r0, [r7, #8] + if (pcb == NULL) { + 800e78e: 68bb ldr r3, [r7, #8] + 800e790: 2b00 cmp r3, #0 + 800e792: d101 bne.n 800e798 + /* out of memory, have to reuse an existing pcb */ + return NULL; + 800e794: 2300 movs r3, #0 + 800e796: e026 b.n 800e7e6 + } + do { + u16_t port = (u16_t)DNS_RAND_TXID(); + 800e798: f00d fcca bl 801c130 + 800e79c: 4603 mov r3, r0 + 800e79e: 80fb strh r3, [r7, #6] + if (DNS_PORT_ALLOWED(port)) { + 800e7a0: 88fb ldrh r3, [r7, #6] + 800e7a2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800e7a6: d308 bcc.n 800e7ba + err = udp_bind(pcb, IP_ANY_TYPE, port); + 800e7a8: 88fb ldrh r3, [r7, #6] + 800e7aa: 461a mov r2, r3 + 800e7ac: 4910 ldr r1, [pc, #64] ; (800e7f0 ) + 800e7ae: 68b8 ldr r0, [r7, #8] + 800e7b0: f008 fbce bl 8016f50 + 800e7b4: 4603 mov r3, r0 + 800e7b6: 73fb strb r3, [r7, #15] + 800e7b8: e001 b.n 800e7be + } else { + /* this port is not allowed, try again */ + err = ERR_USE; + 800e7ba: 23f8 movs r3, #248 ; 0xf8 + 800e7bc: 73fb strb r3, [r7, #15] + } + } while (err == ERR_USE); + 800e7be: f997 300f ldrsb.w r3, [r7, #15] + 800e7c2: f113 0f08 cmn.w r3, #8 + 800e7c6: d0e7 beq.n 800e798 + if (err != ERR_OK) { + 800e7c8: f997 300f ldrsb.w r3, [r7, #15] + 800e7cc: 2b00 cmp r3, #0 + 800e7ce: d004 beq.n 800e7da + udp_remove(pcb); + 800e7d0: 68b8 ldr r0, [r7, #8] + 800e7d2: f008 fcfb bl 80171cc + return NULL; + 800e7d6: 2300 movs r3, #0 + 800e7d8: e005 b.n 800e7e6 + } + udp_recv(pcb, dns_recv, NULL); + 800e7da: 2200 movs r2, #0 + 800e7dc: 4905 ldr r1, [pc, #20] ; (800e7f4 ) + 800e7de: 68b8 ldr r0, [r7, #8] + 800e7e0: f008 fcd4 bl 801718c + return pcb; + 800e7e4: 68bb ldr r3, [r7, #8] +} + 800e7e6: 4618 mov r0, r3 + 800e7e8: 3710 adds r7, #16 + 800e7ea: 46bd mov sp, r7 + 800e7ec: bd80 pop {r7, pc} + 800e7ee: bf00 nop + 800e7f0: 08023914 .word 0x08023914 + 800e7f4: 0800eca1 .word 0x0800eca1 + +0800e7f8 : + * + * @return an index into dns_pcbs + */ +static u8_t +dns_alloc_pcb(void) +{ + 800e7f8: b590 push {r4, r7, lr} + 800e7fa: b083 sub sp, #12 + 800e7fc: af00 add r7, sp, #0 + u8_t i; + u8_t idx; + + for (i = 0; i < DNS_MAX_SOURCE_PORTS; i++) { + 800e7fe: 2300 movs r3, #0 + 800e800: 71fb strb r3, [r7, #7] + 800e802: e008 b.n 800e816 + if (dns_pcbs[i] == NULL) { + 800e804: 79fb ldrb r3, [r7, #7] + 800e806: 4a23 ldr r2, [pc, #140] ; (800e894 ) + 800e808: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800e80c: 2b00 cmp r3, #0 + 800e80e: d006 beq.n 800e81e + for (i = 0; i < DNS_MAX_SOURCE_PORTS; i++) { + 800e810: 79fb ldrb r3, [r7, #7] + 800e812: 3301 adds r3, #1 + 800e814: 71fb strb r3, [r7, #7] + 800e816: 79fb ldrb r3, [r7, #7] + 800e818: 2b03 cmp r3, #3 + 800e81a: d9f3 bls.n 800e804 + 800e81c: e000 b.n 800e820 + break; + 800e81e: bf00 nop + } + } + if (i < DNS_MAX_SOURCE_PORTS) { + 800e820: 79fb ldrb r3, [r7, #7] + 800e822: 2b03 cmp r3, #3 + 800e824: d811 bhi.n 800e84a + dns_pcbs[i] = dns_alloc_random_port(); + 800e826: 79fc ldrb r4, [r7, #7] + 800e828: f7ff ffaa bl 800e780 + 800e82c: 4603 mov r3, r0 + 800e82e: 4a19 ldr r2, [pc, #100] ; (800e894 ) + 800e830: f842 3024 str.w r3, [r2, r4, lsl #2] + if (dns_pcbs[i] != NULL) { + 800e834: 79fb ldrb r3, [r7, #7] + 800e836: 4a17 ldr r2, [pc, #92] ; (800e894 ) + 800e838: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800e83c: 2b00 cmp r3, #0 + 800e83e: d004 beq.n 800e84a + /* succeeded */ + dns_last_pcb_idx = i; + 800e840: 4a15 ldr r2, [pc, #84] ; (800e898 ) + 800e842: 79fb ldrb r3, [r7, #7] + 800e844: 7013 strb r3, [r2, #0] + return i; + 800e846: 79fb ldrb r3, [r7, #7] + 800e848: e020 b.n 800e88c + } + } + /* if we come here, creating a new UDP pcb failed, so we have to use + an already existing one (so overflow is no issue) */ + for (i = 0, idx = (u8_t)(dns_last_pcb_idx + 1); i < DNS_MAX_SOURCE_PORTS; i++, idx++) { + 800e84a: 2300 movs r3, #0 + 800e84c: 71fb strb r3, [r7, #7] + 800e84e: 4b12 ldr r3, [pc, #72] ; (800e898 ) + 800e850: 781b ldrb r3, [r3, #0] + 800e852: 3301 adds r3, #1 + 800e854: 71bb strb r3, [r7, #6] + 800e856: e015 b.n 800e884 + if (idx >= DNS_MAX_SOURCE_PORTS) { + 800e858: 79bb ldrb r3, [r7, #6] + 800e85a: 2b03 cmp r3, #3 + 800e85c: d901 bls.n 800e862 + idx = 0; + 800e85e: 2300 movs r3, #0 + 800e860: 71bb strb r3, [r7, #6] + } + if (dns_pcbs[idx] != NULL) { + 800e862: 79bb ldrb r3, [r7, #6] + 800e864: 4a0b ldr r2, [pc, #44] ; (800e894 ) + 800e866: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800e86a: 2b00 cmp r3, #0 + 800e86c: d004 beq.n 800e878 + dns_last_pcb_idx = idx; + 800e86e: 4a0a ldr r2, [pc, #40] ; (800e898 ) + 800e870: 79bb ldrb r3, [r7, #6] + 800e872: 7013 strb r3, [r2, #0] + return idx; + 800e874: 79bb ldrb r3, [r7, #6] + 800e876: e009 b.n 800e88c + for (i = 0, idx = (u8_t)(dns_last_pcb_idx + 1); i < DNS_MAX_SOURCE_PORTS; i++, idx++) { + 800e878: 79fb ldrb r3, [r7, #7] + 800e87a: 3301 adds r3, #1 + 800e87c: 71fb strb r3, [r7, #7] + 800e87e: 79bb ldrb r3, [r7, #6] + 800e880: 3301 adds r3, #1 + 800e882: 71bb strb r3, [r7, #6] + 800e884: 79fb ldrb r3, [r7, #7] + 800e886: 2b03 cmp r3, #3 + 800e888: d9e6 bls.n 800e858 + } + } + return DNS_MAX_SOURCE_PORTS; + 800e88a: 2304 movs r3, #4 +} + 800e88c: 4618 mov r0, r3 + 800e88e: 370c adds r7, #12 + 800e890: 46bd mov sp, r7 + 800e892: bd90 pop {r4, r7, pc} + 800e894: 200091e4 .word 0x200091e4 + 800e898: 200091f4 .word 0x200091f4 + +0800e89c : + * @param idx dns table index of the entry that is resolved or removed + * @param addr IP address for the hostname (or NULL on error or memory shortage) + */ +static void +dns_call_found(u8_t idx, ip_addr_t *addr) +{ + 800e89c: b590 push {r4, r7, lr} + 800e89e: b085 sub sp, #20 + 800e8a0: af00 add r7, sp, #0 + 800e8a2: 4603 mov r3, r0 + 800e8a4: 6039 str r1, [r7, #0] + 800e8a6: 71fb strb r3, [r7, #7] + } + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + 800e8a8: 2300 movs r3, #0 + 800e8aa: 73fb strb r3, [r7, #15] + 800e8ac: e03d b.n 800e92a + if (dns_requests[i].found && (dns_requests[i].dns_table_idx == idx)) { + 800e8ae: 7bfa ldrb r2, [r7, #15] + 800e8b0: 4957 ldr r1, [pc, #348] ; (800ea10 ) + 800e8b2: 4613 mov r3, r2 + 800e8b4: 005b lsls r3, r3, #1 + 800e8b6: 4413 add r3, r2 + 800e8b8: 009b lsls r3, r3, #2 + 800e8ba: 440b add r3, r1 + 800e8bc: 681b ldr r3, [r3, #0] + 800e8be: 2b00 cmp r3, #0 + 800e8c0: d030 beq.n 800e924 + 800e8c2: 7bfa ldrb r2, [r7, #15] + 800e8c4: 4952 ldr r1, [pc, #328] ; (800ea10 ) + 800e8c6: 4613 mov r3, r2 + 800e8c8: 005b lsls r3, r3, #1 + 800e8ca: 4413 add r3, r2 + 800e8cc: 009b lsls r3, r3, #2 + 800e8ce: 440b add r3, r1 + 800e8d0: 3308 adds r3, #8 + 800e8d2: 781b ldrb r3, [r3, #0] + 800e8d4: 79fa ldrb r2, [r7, #7] + 800e8d6: 429a cmp r2, r3 + 800e8d8: d124 bne.n 800e924 + (*dns_requests[i].found)(dns_table[idx].name, addr, dns_requests[i].arg); + 800e8da: 7bfa ldrb r2, [r7, #15] + 800e8dc: 494c ldr r1, [pc, #304] ; (800ea10 ) + 800e8de: 4613 mov r3, r2 + 800e8e0: 005b lsls r3, r3, #1 + 800e8e2: 4413 add r3, r2 + 800e8e4: 009b lsls r3, r3, #2 + 800e8e6: 440b add r3, r1 + 800e8e8: 681c ldr r4, [r3, #0] + 800e8ea: 79fa ldrb r2, [r7, #7] + 800e8ec: 4613 mov r3, r2 + 800e8ee: 011b lsls r3, r3, #4 + 800e8f0: 4413 add r3, r2 + 800e8f2: 011b lsls r3, r3, #4 + 800e8f4: 3310 adds r3, #16 + 800e8f6: 4a47 ldr r2, [pc, #284] ; (800ea14 ) + 800e8f8: 1898 adds r0, r3, r2 + 800e8fa: 7bfa ldrb r2, [r7, #15] + 800e8fc: 4944 ldr r1, [pc, #272] ; (800ea10 ) + 800e8fe: 4613 mov r3, r2 + 800e900: 005b lsls r3, r3, #1 + 800e902: 4413 add r3, r2 + 800e904: 009b lsls r3, r3, #2 + 800e906: 440b add r3, r1 + 800e908: 3304 adds r3, #4 + 800e90a: 681b ldr r3, [r3, #0] + 800e90c: 461a mov r2, r3 + 800e90e: 6839 ldr r1, [r7, #0] + 800e910: 47a0 blx r4 + /* flush this entry */ + dns_requests[i].found = NULL; + 800e912: 7bfa ldrb r2, [r7, #15] + 800e914: 493e ldr r1, [pc, #248] ; (800ea10 ) + 800e916: 4613 mov r3, r2 + 800e918: 005b lsls r3, r3, #1 + 800e91a: 4413 add r3, r2 + 800e91c: 009b lsls r3, r3, #2 + 800e91e: 440b add r3, r1 + 800e920: 2200 movs r2, #0 + 800e922: 601a str r2, [r3, #0] + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + 800e924: 7bfb ldrb r3, [r7, #15] + 800e926: 3301 adds r3, #1 + 800e928: 73fb strb r3, [r7, #15] + 800e92a: 7bfb ldrb r3, [r7, #15] + 800e92c: 2b03 cmp r3, #3 + 800e92e: d9be bls.n 800e8ae + } + dns_requests[idx].found = NULL; +#endif +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + /* close the pcb used unless other request are using it */ + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + 800e930: 2300 movs r3, #0 + 800e932: 73fb strb r3, [r7, #15] + 800e934: e031 b.n 800e99a + if (i == idx) { + 800e936: 7bfa ldrb r2, [r7, #15] + 800e938: 79fb ldrb r3, [r7, #7] + 800e93a: 429a cmp r2, r3 + 800e93c: d029 beq.n 800e992 + continue; /* only check other requests */ + } + if (dns_table[i].state == DNS_STATE_ASKING) { + 800e93e: 7bfa ldrb r2, [r7, #15] + 800e940: 4934 ldr r1, [pc, #208] ; (800ea14 ) + 800e942: 4613 mov r3, r2 + 800e944: 011b lsls r3, r3, #4 + 800e946: 4413 add r3, r2 + 800e948: 011b lsls r3, r3, #4 + 800e94a: 440b add r3, r1 + 800e94c: 330a adds r3, #10 + 800e94e: 781b ldrb r3, [r3, #0] + 800e950: 2b02 cmp r3, #2 + 800e952: d11f bne.n 800e994 + if (dns_table[i].pcb_idx == dns_table[idx].pcb_idx) { + 800e954: 7bfa ldrb r2, [r7, #15] + 800e956: 492f ldr r1, [pc, #188] ; (800ea14 ) + 800e958: 4613 mov r3, r2 + 800e95a: 011b lsls r3, r3, #4 + 800e95c: 4413 add r3, r2 + 800e95e: 011b lsls r3, r3, #4 + 800e960: 440b add r3, r1 + 800e962: 330f adds r3, #15 + 800e964: 7819 ldrb r1, [r3, #0] + 800e966: 79fa ldrb r2, [r7, #7] + 800e968: 482a ldr r0, [pc, #168] ; (800ea14 ) + 800e96a: 4613 mov r3, r2 + 800e96c: 011b lsls r3, r3, #4 + 800e96e: 4413 add r3, r2 + 800e970: 011b lsls r3, r3, #4 + 800e972: 4403 add r3, r0 + 800e974: 330f adds r3, #15 + 800e976: 781b ldrb r3, [r3, #0] + 800e978: 4299 cmp r1, r3 + 800e97a: d10b bne.n 800e994 + /* another request is still using the same pcb */ + dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; + 800e97c: 79fa ldrb r2, [r7, #7] + 800e97e: 4925 ldr r1, [pc, #148] ; (800ea14 ) + 800e980: 4613 mov r3, r2 + 800e982: 011b lsls r3, r3, #4 + 800e984: 4413 add r3, r2 + 800e986: 011b lsls r3, r3, #4 + 800e988: 440b add r3, r1 + 800e98a: 330f adds r3, #15 + 800e98c: 2204 movs r2, #4 + 800e98e: 701a strb r2, [r3, #0] + break; + 800e990: e006 b.n 800e9a0 + continue; /* only check other requests */ + 800e992: bf00 nop + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + 800e994: 7bfb ldrb r3, [r7, #15] + 800e996: 3301 adds r3, #1 + 800e998: 73fb strb r3, [r7, #15] + 800e99a: 7bfb ldrb r3, [r7, #15] + 800e99c: 2b03 cmp r3, #3 + 800e99e: d9ca bls.n 800e936 + } + } + } + if (dns_table[idx].pcb_idx < DNS_MAX_SOURCE_PORTS) { + 800e9a0: 79fa ldrb r2, [r7, #7] + 800e9a2: 491c ldr r1, [pc, #112] ; (800ea14 ) + 800e9a4: 4613 mov r3, r2 + 800e9a6: 011b lsls r3, r3, #4 + 800e9a8: 4413 add r3, r2 + 800e9aa: 011b lsls r3, r3, #4 + 800e9ac: 440b add r3, r1 + 800e9ae: 330f adds r3, #15 + 800e9b0: 781b ldrb r3, [r3, #0] + 800e9b2: 2b03 cmp r3, #3 + 800e9b4: d827 bhi.n 800ea06 + /* if we come here, the pcb is not used any more and can be removed */ + udp_remove(dns_pcbs[dns_table[idx].pcb_idx]); + 800e9b6: 79fa ldrb r2, [r7, #7] + 800e9b8: 4916 ldr r1, [pc, #88] ; (800ea14 ) + 800e9ba: 4613 mov r3, r2 + 800e9bc: 011b lsls r3, r3, #4 + 800e9be: 4413 add r3, r2 + 800e9c0: 011b lsls r3, r3, #4 + 800e9c2: 440b add r3, r1 + 800e9c4: 330f adds r3, #15 + 800e9c6: 781b ldrb r3, [r3, #0] + 800e9c8: 461a mov r2, r3 + 800e9ca: 4b13 ldr r3, [pc, #76] ; (800ea18 ) + 800e9cc: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800e9d0: 4618 mov r0, r3 + 800e9d2: f008 fbfb bl 80171cc + dns_pcbs[dns_table[idx].pcb_idx] = NULL; + 800e9d6: 79fa ldrb r2, [r7, #7] + 800e9d8: 490e ldr r1, [pc, #56] ; (800ea14 ) + 800e9da: 4613 mov r3, r2 + 800e9dc: 011b lsls r3, r3, #4 + 800e9de: 4413 add r3, r2 + 800e9e0: 011b lsls r3, r3, #4 + 800e9e2: 440b add r3, r1 + 800e9e4: 330f adds r3, #15 + 800e9e6: 781b ldrb r3, [r3, #0] + 800e9e8: 4619 mov r1, r3 + 800e9ea: 4b0b ldr r3, [pc, #44] ; (800ea18 ) + 800e9ec: 2200 movs r2, #0 + 800e9ee: f843 2021 str.w r2, [r3, r1, lsl #2] + dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; + 800e9f2: 79fa ldrb r2, [r7, #7] + 800e9f4: 4907 ldr r1, [pc, #28] ; (800ea14 ) + 800e9f6: 4613 mov r3, r2 + 800e9f8: 011b lsls r3, r3, #4 + 800e9fa: 4413 add r3, r2 + 800e9fc: 011b lsls r3, r3, #4 + 800e9fe: 440b add r3, r1 + 800ea00: 330f adds r3, #15 + 800ea02: 2204 movs r2, #4 + 800ea04: 701a strb r2, [r3, #0] + } +#endif +} + 800ea06: bf00 nop + 800ea08: 3714 adds r7, #20 + 800ea0a: 46bd mov sp, r7 + 800ea0c: bd90 pop {r4, r7, pc} + 800ea0e: bf00 nop + 800ea10: 20009638 .word 0x20009638 + 800ea14: 200091f8 .word 0x200091f8 + 800ea18: 200091e4 .word 0x200091e4 + +0800ea1c : + +/* Create a query transmission ID that is unique for all outstanding queries */ +static u16_t +dns_create_txid(void) +{ + 800ea1c: b580 push {r7, lr} + 800ea1e: b082 sub sp, #8 + 800ea20: af00 add r7, sp, #0 + u16_t txid; + u8_t i; + +again: + txid = (u16_t)DNS_RAND_TXID(); + 800ea22: f00d fb85 bl 801c130 + 800ea26: 4603 mov r3, r0 + 800ea28: 80bb strh r3, [r7, #4] + + /* check whether the ID is unique */ + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800ea2a: 2300 movs r3, #0 + 800ea2c: 71fb strb r3, [r7, #7] + 800ea2e: e01a b.n 800ea66 + if ((dns_table[i].state == DNS_STATE_ASKING) && + 800ea30: 79fa ldrb r2, [r7, #7] + 800ea32: 4911 ldr r1, [pc, #68] ; (800ea78 ) + 800ea34: 4613 mov r3, r2 + 800ea36: 011b lsls r3, r3, #4 + 800ea38: 4413 add r3, r2 + 800ea3a: 011b lsls r3, r3, #4 + 800ea3c: 440b add r3, r1 + 800ea3e: 330a adds r3, #10 + 800ea40: 781b ldrb r3, [r3, #0] + 800ea42: 2b02 cmp r3, #2 + 800ea44: d10c bne.n 800ea60 + (dns_table[i].txid == txid)) { + 800ea46: 79fa ldrb r2, [r7, #7] + 800ea48: 490b ldr r1, [pc, #44] ; (800ea78 ) + 800ea4a: 4613 mov r3, r2 + 800ea4c: 011b lsls r3, r3, #4 + 800ea4e: 4413 add r3, r2 + 800ea50: 011b lsls r3, r3, #4 + 800ea52: 440b add r3, r1 + 800ea54: 3308 adds r3, #8 + 800ea56: 881b ldrh r3, [r3, #0] + if ((dns_table[i].state == DNS_STATE_ASKING) && + 800ea58: 88ba ldrh r2, [r7, #4] + 800ea5a: 429a cmp r2, r3 + 800ea5c: d100 bne.n 800ea60 + /* ID already used by another pending query */ + goto again; + 800ea5e: e7e0 b.n 800ea22 + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800ea60: 79fb ldrb r3, [r7, #7] + 800ea62: 3301 adds r3, #1 + 800ea64: 71fb strb r3, [r7, #7] + 800ea66: 79fb ldrb r3, [r7, #7] + 800ea68: 2b03 cmp r3, #3 + 800ea6a: d9e1 bls.n 800ea30 + } + } + + return txid; + 800ea6c: 88bb ldrh r3, [r7, #4] +} + 800ea6e: 4618 mov r0, r3 + 800ea70: 3708 adds r7, #8 + 800ea72: 46bd mov sp, r7 + 800ea74: bd80 pop {r7, pc} + 800ea76: bf00 nop + 800ea78: 200091f8 .word 0x200091f8 + +0800ea7c : +/** + * Check whether there are other backup DNS servers available to try + */ +static u8_t +dns_backupserver_available(struct dns_table_entry *pentry) +{ + 800ea7c: b480 push {r7} + 800ea7e: b085 sub sp, #20 + 800ea80: af00 add r7, sp, #0 + 800ea82: 6078 str r0, [r7, #4] + u8_t ret = 0; + 800ea84: 2300 movs r3, #0 + 800ea86: 73fb strb r3, [r7, #15] + + if (pentry) { + 800ea88: 687b ldr r3, [r7, #4] + 800ea8a: 2b00 cmp r3, #0 + 800ea8c: d00d beq.n 800eaaa + if ((pentry->server_idx + 1 < DNS_MAX_SERVERS) && !ip_addr_isany_val(dns_servers[pentry->server_idx + 1])) { + 800ea8e: 687b ldr r3, [r7, #4] + 800ea90: 7adb ldrb r3, [r3, #11] + 800ea92: 2b00 cmp r3, #0 + 800ea94: d109 bne.n 800eaaa + 800ea96: 687b ldr r3, [r7, #4] + 800ea98: 7adb ldrb r3, [r3, #11] + 800ea9a: 3301 adds r3, #1 + 800ea9c: 4a06 ldr r2, [pc, #24] ; (800eab8 ) + 800ea9e: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800eaa2: 2b00 cmp r3, #0 + 800eaa4: d001 beq.n 800eaaa + ret = 1; + 800eaa6: 2301 movs r3, #1 + 800eaa8: 73fb strb r3, [r7, #15] + } + } + + return ret; + 800eaaa: 7bfb ldrb r3, [r7, #15] +} + 800eaac: 4618 mov r0, r3 + 800eaae: 3714 adds r7, #20 + 800eab0: 46bd mov sp, r7 + 800eab2: f85d 7b04 ldr.w r7, [sp], #4 + 800eab6: 4770 bx lr + 800eab8: 20009668 .word 0x20009668 + +0800eabc : + * + * @param i index of the dns_table entry to check + */ +static void +dns_check_entry(u8_t i) +{ + 800eabc: b580 push {r7, lr} + 800eabe: b084 sub sp, #16 + 800eac0: af00 add r7, sp, #0 + 800eac2: 4603 mov r3, r0 + 800eac4: 71fb strb r3, [r7, #7] + err_t err; + struct dns_table_entry *entry = &dns_table[i]; + 800eac6: 79fa ldrb r2, [r7, #7] + 800eac8: 4613 mov r3, r2 + 800eaca: 011b lsls r3, r3, #4 + 800eacc: 4413 add r3, r2 + 800eace: 011b lsls r3, r3, #4 + 800ead0: 4a48 ldr r2, [pc, #288] ; (800ebf4 ) + 800ead2: 4413 add r3, r2 + 800ead4: 60fb str r3, [r7, #12] + + LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE); + 800ead6: 79fb ldrb r3, [r7, #7] + 800ead8: 2b03 cmp r3, #3 + 800eada: d906 bls.n 800eaea + 800eadc: 4b46 ldr r3, [pc, #280] ; (800ebf8 ) + 800eade: f240 421c movw r2, #1052 ; 0x41c + 800eae2: 4946 ldr r1, [pc, #280] ; (800ebfc ) + 800eae4: 4846 ldr r0, [pc, #280] ; (800ec00 ) + 800eae6: f00d fa95 bl 801c014 + + switch (entry->state) { + 800eaea: 68fb ldr r3, [r7, #12] + 800eaec: 7a9b ldrb r3, [r3, #10] + 800eaee: 2b03 cmp r3, #3 + 800eaf0: d86f bhi.n 800ebd2 + 800eaf2: a201 add r2, pc, #4 ; (adr r2, 800eaf8 ) + 800eaf4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800eaf8: 0800ebe3 .word 0x0800ebe3 + 800eafc: 0800eb09 .word 0x0800eb09 + 800eb00: 0800eb3b .word 0x0800eb3b + 800eb04: 0800ebb1 .word 0x0800ebb1 + case DNS_STATE_NEW: + /* initialize new entry */ + entry->txid = dns_create_txid(); + 800eb08: f7ff ff88 bl 800ea1c + 800eb0c: 4603 mov r3, r0 + 800eb0e: 461a mov r2, r3 + 800eb10: 68fb ldr r3, [r7, #12] + 800eb12: 811a strh r2, [r3, #8] + entry->state = DNS_STATE_ASKING; + 800eb14: 68fb ldr r3, [r7, #12] + 800eb16: 2202 movs r2, #2 + 800eb18: 729a strb r2, [r3, #10] + entry->server_idx = 0; + 800eb1a: 68fb ldr r3, [r7, #12] + 800eb1c: 2200 movs r2, #0 + 800eb1e: 72da strb r2, [r3, #11] + entry->tmr = 1; + 800eb20: 68fb ldr r3, [r7, #12] + 800eb22: 2201 movs r2, #1 + 800eb24: 731a strb r2, [r3, #12] + entry->retries = 0; + 800eb26: 68fb ldr r3, [r7, #12] + 800eb28: 2200 movs r2, #0 + 800eb2a: 735a strb r2, [r3, #13] + + /* send DNS packet for this entry */ + err = dns_send(i); + 800eb2c: 79fb ldrb r3, [r7, #7] + 800eb2e: 4618 mov r0, r3 + 800eb30: f7ff fd36 bl 800e5a0 + 800eb34: 4603 mov r3, r0 + 800eb36: 72fb strb r3, [r7, #11] + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + break; + 800eb38: e058 b.n 800ebec + case DNS_STATE_ASKING: + if (--entry->tmr == 0) { + 800eb3a: 68fb ldr r3, [r7, #12] + 800eb3c: 7b1b ldrb r3, [r3, #12] + 800eb3e: 3b01 subs r3, #1 + 800eb40: b2da uxtb r2, r3 + 800eb42: 68fb ldr r3, [r7, #12] + 800eb44: 731a strb r2, [r3, #12] + 800eb46: 68fb ldr r3, [r7, #12] + 800eb48: 7b1b ldrb r3, [r3, #12] + 800eb4a: 2b00 cmp r3, #0 + 800eb4c: d14b bne.n 800ebe6 + if (++entry->retries == DNS_MAX_RETRIES) { + 800eb4e: 68fb ldr r3, [r7, #12] + 800eb50: 7b5b ldrb r3, [r3, #13] + 800eb52: 3301 adds r3, #1 + 800eb54: b2da uxtb r2, r3 + 800eb56: 68fb ldr r3, [r7, #12] + 800eb58: 735a strb r2, [r3, #13] + 800eb5a: 68fb ldr r3, [r7, #12] + 800eb5c: 7b5b ldrb r3, [r3, #13] + 800eb5e: 2b04 cmp r3, #4 + 800eb60: d11b bne.n 800eb9a + if (dns_backupserver_available(entry) + 800eb62: 68f8 ldr r0, [r7, #12] + 800eb64: f7ff ff8a bl 800ea7c + 800eb68: 4603 mov r3, r0 + 800eb6a: 2b00 cmp r3, #0 + 800eb6c: d00c beq.n 800eb88 +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + && !entry->is_mdns +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + ) { + /* change of server */ + entry->server_idx++; + 800eb6e: 68fb ldr r3, [r7, #12] + 800eb70: 7adb ldrb r3, [r3, #11] + 800eb72: 3301 adds r3, #1 + 800eb74: b2da uxtb r2, r3 + 800eb76: 68fb ldr r3, [r7, #12] + 800eb78: 72da strb r2, [r3, #11] + entry->tmr = 1; + 800eb7a: 68fb ldr r3, [r7, #12] + 800eb7c: 2201 movs r2, #1 + 800eb7e: 731a strb r2, [r3, #12] + entry->retries = 0; + 800eb80: 68fb ldr r3, [r7, #12] + 800eb82: 2200 movs r2, #0 + 800eb84: 735a strb r2, [r3, #13] + 800eb86: e00c b.n 800eba2 + } else { + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", entry->name)); + /* call specified callback function if provided */ + dns_call_found(i, NULL); + 800eb88: 79fb ldrb r3, [r7, #7] + 800eb8a: 2100 movs r1, #0 + 800eb8c: 4618 mov r0, r3 + 800eb8e: f7ff fe85 bl 800e89c + /* flush this entry */ + entry->state = DNS_STATE_UNUSED; + 800eb92: 68fb ldr r3, [r7, #12] + 800eb94: 2200 movs r2, #0 + 800eb96: 729a strb r2, [r3, #10] + break; + 800eb98: e028 b.n 800ebec + } + } else { + /* wait longer for the next retry */ + entry->tmr = entry->retries; + 800eb9a: 68fb ldr r3, [r7, #12] + 800eb9c: 7b5a ldrb r2, [r3, #13] + 800eb9e: 68fb ldr r3, [r7, #12] + 800eba0: 731a strb r2, [r3, #12] + } + + /* send DNS packet for this entry */ + err = dns_send(i); + 800eba2: 79fb ldrb r3, [r7, #7] + 800eba4: 4618 mov r0, r3 + 800eba6: f7ff fcfb bl 800e5a0 + 800ebaa: 4603 mov r3, r0 + 800ebac: 72fb strb r3, [r7, #11] + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + } + break; + 800ebae: e01a b.n 800ebe6 + case DNS_STATE_DONE: + /* if the time to live is nul */ + if ((entry->ttl == 0) || (--entry->ttl == 0)) { + 800ebb0: 68fb ldr r3, [r7, #12] + 800ebb2: 681b ldr r3, [r3, #0] + 800ebb4: 2b00 cmp r3, #0 + 800ebb6: d008 beq.n 800ebca + 800ebb8: 68fb ldr r3, [r7, #12] + 800ebba: 681b ldr r3, [r3, #0] + 800ebbc: 1e5a subs r2, r3, #1 + 800ebbe: 68fb ldr r3, [r7, #12] + 800ebc0: 601a str r2, [r3, #0] + 800ebc2: 68fb ldr r3, [r7, #12] + 800ebc4: 681b ldr r3, [r3, #0] + 800ebc6: 2b00 cmp r3, #0 + 800ebc8: d10f bne.n 800ebea + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", entry->name)); + /* flush this entry, there cannot be any related pending entries in this state */ + entry->state = DNS_STATE_UNUSED; + 800ebca: 68fb ldr r3, [r7, #12] + 800ebcc: 2200 movs r2, #0 + 800ebce: 729a strb r2, [r3, #10] + } + break; + 800ebd0: e00b b.n 800ebea + case DNS_STATE_UNUSED: + /* nothing to do */ + break; + default: + LWIP_ASSERT("unknown dns_table entry state:", 0); + 800ebd2: 4b09 ldr r3, [pc, #36] ; (800ebf8 ) + 800ebd4: f240 425b movw r2, #1115 ; 0x45b + 800ebd8: 490a ldr r1, [pc, #40] ; (800ec04 ) + 800ebda: 4809 ldr r0, [pc, #36] ; (800ec00 ) + 800ebdc: f00d fa1a bl 801c014 + break; + 800ebe0: e004 b.n 800ebec + break; + 800ebe2: bf00 nop + 800ebe4: e002 b.n 800ebec + break; + 800ebe6: bf00 nop + 800ebe8: e000 b.n 800ebec + break; + 800ebea: bf00 nop + } +} + 800ebec: bf00 nop + 800ebee: 3710 adds r7, #16 + 800ebf0: 46bd mov sp, r7 + 800ebf2: bd80 pop {r7, pc} + 800ebf4: 200091f8 .word 0x200091f8 + 800ebf8: 0801e9e0 .word 0x0801e9e0 + 800ebfc: 0801ea50 .word 0x0801ea50 + 800ec00: 0801ea28 .word 0x0801ea28 + 800ec04: 0801ea6c .word 0x0801ea6c + +0800ec08 : +/** + * Call dns_check_entry for each entry in dns_table - check all entries. + */ +static void +dns_check_entries(void) +{ + 800ec08: b580 push {r7, lr} + 800ec0a: b082 sub sp, #8 + 800ec0c: af00 add r7, sp, #0 + u8_t i; + + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800ec0e: 2300 movs r3, #0 + 800ec10: 71fb strb r3, [r7, #7] + 800ec12: e006 b.n 800ec22 + dns_check_entry(i); + 800ec14: 79fb ldrb r3, [r7, #7] + 800ec16: 4618 mov r0, r3 + 800ec18: f7ff ff50 bl 800eabc + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800ec1c: 79fb ldrb r3, [r7, #7] + 800ec1e: 3301 adds r3, #1 + 800ec20: 71fb strb r3, [r7, #7] + 800ec22: 79fb ldrb r3, [r7, #7] + 800ec24: 2b03 cmp r3, #3 + 800ec26: d9f5 bls.n 800ec14 + } +} + 800ec28: bf00 nop + 800ec2a: bf00 nop + 800ec2c: 3708 adds r7, #8 + 800ec2e: 46bd mov sp, r7 + 800ec30: bd80 pop {r7, pc} + ... + +0800ec34 : +/** + * Save TTL and call dns_call_found for correct response. + */ +static void +dns_correct_response(u8_t idx, u32_t ttl) +{ + 800ec34: b580 push {r7, lr} + 800ec36: b084 sub sp, #16 + 800ec38: af00 add r7, sp, #0 + 800ec3a: 4603 mov r3, r0 + 800ec3c: 6039 str r1, [r7, #0] + 800ec3e: 71fb strb r3, [r7, #7] + struct dns_table_entry *entry = &dns_table[idx]; + 800ec40: 79fa ldrb r2, [r7, #7] + 800ec42: 4613 mov r3, r2 + 800ec44: 011b lsls r3, r3, #4 + 800ec46: 4413 add r3, r2 + 800ec48: 011b lsls r3, r3, #4 + 800ec4a: 4a13 ldr r2, [pc, #76] ; (800ec98 ) + 800ec4c: 4413 add r3, r2 + 800ec4e: 60fb str r3, [r7, #12] + + entry->state = DNS_STATE_DONE; + 800ec50: 68fb ldr r3, [r7, #12] + 800ec52: 2203 movs r2, #3 + 800ec54: 729a strb r2, [r3, #10] + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", entry->name)); + ip_addr_debug_print_val(DNS_DEBUG, entry->ipaddr); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + + /* read the answer resource record's TTL, and maximize it if needed */ + entry->ttl = ttl; + 800ec56: 68fb ldr r3, [r7, #12] + 800ec58: 683a ldr r2, [r7, #0] + 800ec5a: 601a str r2, [r3, #0] + if (entry->ttl > DNS_MAX_TTL) { + 800ec5c: 68fb ldr r3, [r7, #12] + 800ec5e: 681b ldr r3, [r3, #0] + 800ec60: 4a0e ldr r2, [pc, #56] ; (800ec9c ) + 800ec62: 4293 cmp r3, r2 + 800ec64: d902 bls.n 800ec6c + entry->ttl = DNS_MAX_TTL; + 800ec66: 68fb ldr r3, [r7, #12] + 800ec68: 4a0c ldr r2, [pc, #48] ; (800ec9c ) + 800ec6a: 601a str r2, [r3, #0] + } + dns_call_found(idx, &entry->ipaddr); + 800ec6c: 68fb ldr r3, [r7, #12] + 800ec6e: 1d1a adds r2, r3, #4 + 800ec70: 79fb ldrb r3, [r7, #7] + 800ec72: 4611 mov r1, r2 + 800ec74: 4618 mov r0, r3 + 800ec76: f7ff fe11 bl 800e89c + + if (entry->ttl == 0) { + 800ec7a: 68fb ldr r3, [r7, #12] + 800ec7c: 681b ldr r3, [r3, #0] + 800ec7e: 2b00 cmp r3, #0 + 800ec80: d106 bne.n 800ec90 + /* RFC 883, page 29: "Zero values are + interpreted to mean that the RR can only be used for the + transaction in progress, and should not be cached." + -> flush this entry now */ + /* entry reused during callback? */ + if (entry->state == DNS_STATE_DONE) { + 800ec82: 68fb ldr r3, [r7, #12] + 800ec84: 7a9b ldrb r3, [r3, #10] + 800ec86: 2b03 cmp r3, #3 + 800ec88: d102 bne.n 800ec90 + entry->state = DNS_STATE_UNUSED; + 800ec8a: 68fb ldr r3, [r7, #12] + 800ec8c: 2200 movs r2, #0 + 800ec8e: 729a strb r2, [r3, #10] + } + } +} + 800ec90: bf00 nop + 800ec92: 3710 adds r7, #16 + 800ec94: 46bd mov sp, r7 + 800ec96: bd80 pop {r7, pc} + 800ec98: 200091f8 .word 0x200091f8 + 800ec9c: 00093a80 .word 0x00093a80 + +0800eca0 : +/** + * Receive input function for DNS response packets arriving for the dns UDP pcb. + */ +static void +dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + 800eca0: b590 push {r4, r7, lr} + 800eca2: b091 sub sp, #68 ; 0x44 + 800eca4: af00 add r7, sp, #0 + 800eca6: 60f8 str r0, [r7, #12] + 800eca8: 60b9 str r1, [r7, #8] + 800ecaa: 607a str r2, [r7, #4] + 800ecac: 603b str r3, [r7, #0] + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(port); + + /* is the dns message big enough ? */ + if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY)) { + 800ecae: 687b ldr r3, [r7, #4] + 800ecb0: 891b ldrh r3, [r3, #8] + 800ecb2: 2b0f cmp r3, #15 + 800ecb4: f240 811e bls.w 800eef4 + /* free pbuf and return */ + goto ignore_packet; + } + + /* copy dns payload inside static buffer for processing */ + if (pbuf_copy_partial(p, &hdr, SIZEOF_DNS_HDR, 0) == SIZEOF_DNS_HDR) { + 800ecb8: f107 0124 add.w r1, r7, #36 ; 0x24 + 800ecbc: 2300 movs r3, #0 + 800ecbe: 220c movs r2, #12 + 800ecc0: 6878 ldr r0, [r7, #4] + 800ecc2: f002 f8a3 bl 8010e0c + 800ecc6: 4603 mov r3, r0 + 800ecc8: 2b0c cmp r3, #12 + 800ecca: f040 8115 bne.w 800eef8 + /* Match the ID in the DNS header with the name table. */ + txid = lwip_htons(hdr.id); + 800ecce: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800ecd0: 4618 mov r0, r3 + 800ecd2: f7ff faad bl 800e230 + 800ecd6: 4603 mov r3, r0 + 800ecd8: 873b strh r3, [r7, #56] ; 0x38 + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800ecda: 2300 movs r3, #0 + 800ecdc: f887 303f strb.w r3, [r7, #63] ; 0x3f + 800ece0: e102 b.n 800eee8 + struct dns_table_entry *entry = &dns_table[i]; + 800ece2: f897 203f ldrb.w r2, [r7, #63] ; 0x3f + 800ece6: 4613 mov r3, r2 + 800ece8: 011b lsls r3, r3, #4 + 800ecea: 4413 add r3, r2 + 800ecec: 011b lsls r3, r3, #4 + 800ecee: 4a92 ldr r2, [pc, #584] ; (800ef38 ) + 800ecf0: 4413 add r3, r2 + 800ecf2: 637b str r3, [r7, #52] ; 0x34 + if ((entry->state == DNS_STATE_ASKING) && + 800ecf4: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ecf6: 7a9b ldrb r3, [r3, #10] + 800ecf8: 2b02 cmp r3, #2 + 800ecfa: f040 80f0 bne.w 800eede + (entry->txid == txid)) { + 800ecfe: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ed00: 891b ldrh r3, [r3, #8] + if ((entry->state == DNS_STATE_ASKING) && + 800ed02: 8f3a ldrh r2, [r7, #56] ; 0x38 + 800ed04: 429a cmp r2, r3 + 800ed06: f040 80ea bne.w 800eede + + /* We only care about the question(s) and the answers. The authrr + and the extrarr are simply discarded. */ + nquestions = lwip_htons(hdr.numquestions); + 800ed0a: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800ed0c: 4618 mov r0, r3 + 800ed0e: f7ff fa8f bl 800e230 + 800ed12: 4603 mov r3, r0 + 800ed14: 867b strh r3, [r7, #50] ; 0x32 + nanswers = lwip_htons(hdr.numanswers); + 800ed16: 8d7b ldrh r3, [r7, #42] ; 0x2a + 800ed18: 4618 mov r0, r3 + 800ed1a: f7ff fa89 bl 800e230 + 800ed1e: 4603 mov r3, r0 + 800ed20: 877b strh r3, [r7, #58] ; 0x3a + + /* Check for correct response. */ + if ((hdr.flags1 & DNS_FLAG1_RESPONSE) == 0) { + 800ed22: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800ed26: b25b sxtb r3, r3 + 800ed28: 2b00 cmp r3, #0 + 800ed2a: f280 80e7 bge.w 800eefc + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": not a response\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + if (nquestions != 1) { + 800ed2e: 8e7b ldrh r3, [r7, #50] ; 0x32 + 800ed30: 2b01 cmp r3, #1 + 800ed32: f040 80e5 bne.w 800ef00 + if (!entry->is_mdns) +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + /* Check whether response comes from the same network address to which the + question was sent. (RFC 5452) */ + if (!ip_addr_cmp(addr, &dns_servers[entry->server_idx])) { + 800ed36: 683b ldr r3, [r7, #0] + 800ed38: 681a ldr r2, [r3, #0] + 800ed3a: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ed3c: 7adb ldrb r3, [r3, #11] + 800ed3e: 4619 mov r1, r3 + 800ed40: 4b7e ldr r3, [pc, #504] ; (800ef3c ) + 800ed42: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 800ed46: 429a cmp r2, r3 + 800ed48: f040 80dc bne.w 800ef04 + } + } + + /* Check if the name in the "question" part match with the name in the entry and + skip it if equal. */ + res_idx = dns_compare_name(entry->name, p, SIZEOF_DNS_HDR); + 800ed4c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ed4e: 3310 adds r3, #16 + 800ed50: 220c movs r2, #12 + 800ed52: 6879 ldr r1, [r7, #4] + 800ed54: 4618 mov r0, r3 + 800ed56: f7ff fb47 bl 800e3e8 + 800ed5a: 4603 mov r3, r0 + 800ed5c: 87bb strh r3, [r7, #60] ; 0x3c + if (res_idx == 0xFFFF) { + 800ed5e: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ed60: f64f 72ff movw r2, #65535 ; 0xffff + 800ed64: 4293 cmp r3, r2 + 800ed66: f000 80cf beq.w 800ef08 + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + + /* check if "question" part matches the request */ + if (pbuf_copy_partial(p, &qry, SIZEOF_DNS_QUERY, res_idx) != SIZEOF_DNS_QUERY) { + 800ed6a: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ed6c: f107 0114 add.w r1, r7, #20 + 800ed70: 2204 movs r2, #4 + 800ed72: 6878 ldr r0, [r7, #4] + 800ed74: f002 f84a bl 8010e0c + 800ed78: 4603 mov r3, r0 + 800ed7a: 2b04 cmp r3, #4 + 800ed7c: f040 80c6 bne.w 800ef0c + goto ignore_packet; /* ignore this packet */ + } + if ((qry.cls != PP_HTONS(DNS_RRCLASS_IN)) || + 800ed80: 8afb ldrh r3, [r7, #22] + 800ed82: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800ed86: f040 80c3 bne.w 800ef10 + (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_AAAA))) || + (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_A)))) { + 800ed8a: 8abb ldrh r3, [r7, #20] + (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_AAAA))) || + 800ed8c: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800ed90: f040 80be bne.w 800ef10 + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + /* skip the rest of the "question" part */ + if (res_idx + SIZEOF_DNS_QUERY > 0xFFFF) { + 800ed94: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ed96: f64f 72fb movw r2, #65531 ; 0xfffb + 800ed9a: 4293 cmp r3, r2 + 800ed9c: f200 80ba bhi.w 800ef14 + goto ignore_packet; + } + res_idx = (u16_t)(res_idx + SIZEOF_DNS_QUERY); + 800eda0: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800eda2: 3304 adds r3, #4 + 800eda4: 87bb strh r3, [r7, #60] ; 0x3c + + /* Check for error. If so, call callback to inform. */ + if (hdr.flags2 & DNS_FLAG2_ERR_MASK) { + 800eda6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800edaa: f003 030f and.w r3, r3, #15 + 800edae: 2b00 cmp r3, #0 + 800edb0: d078 beq.n 800eea4 + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", entry->name)); + + /* if there is another backup DNS server to try + * then don't stop the DNS request + */ + if (dns_backupserver_available(entry)) { + 800edb2: 6b78 ldr r0, [r7, #52] ; 0x34 + 800edb4: f7ff fe62 bl 800ea7c + 800edb8: 4603 mov r3, r0 + 800edba: 2b00 cmp r3, #0 + 800edbc: d07a beq.n 800eeb4 + /* avoid retrying the same server */ + entry->retries = DNS_MAX_RETRIES-1; + 800edbe: 6b7b ldr r3, [r7, #52] ; 0x34 + 800edc0: 2203 movs r2, #3 + 800edc2: 735a strb r2, [r3, #13] + entry->tmr = 1; + 800edc4: 6b7b ldr r3, [r7, #52] ; 0x34 + 800edc6: 2201 movs r2, #1 + 800edc8: 731a strb r2, [r3, #12] + + /* contact next available server for this entry */ + dns_check_entry(i); + 800edca: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 800edce: 4618 mov r0, r3 + 800edd0: f7ff fe74 bl 800eabc + + goto ignore_packet; + 800edd4: e0a9 b.n 800ef2a + } + } else { + while ((nanswers > 0) && (res_idx < p->tot_len)) { + /* skip answer resource record's host name */ + res_idx = dns_skip_name(p, res_idx); + 800edd6: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800edd8: 4619 mov r1, r3 + 800edda: 6878 ldr r0, [r7, #4] + 800eddc: f7ff fb92 bl 800e504 + 800ede0: 4603 mov r3, r0 + 800ede2: 87bb strh r3, [r7, #60] ; 0x3c + if (res_idx == 0xFFFF) { + 800ede4: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ede6: f64f 72ff movw r2, #65535 ; 0xffff + 800edea: 4293 cmp r3, r2 + 800edec: f000 8094 beq.w 800ef18 + goto ignore_packet; /* ignore this packet */ + } + + /* Check for IP address type and Internet class. Others are discarded. */ + if (pbuf_copy_partial(p, &ans, SIZEOF_DNS_ANSWER, res_idx) != SIZEOF_DNS_ANSWER) { + 800edf0: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800edf2: f107 0118 add.w r1, r7, #24 + 800edf6: 220a movs r2, #10 + 800edf8: 6878 ldr r0, [r7, #4] + 800edfa: f002 f807 bl 8010e0c + 800edfe: 4603 mov r3, r0 + 800ee00: 2b0a cmp r3, #10 + 800ee02: f040 808b bne.w 800ef1c + goto ignore_packet; /* ignore this packet */ + } + if (res_idx + SIZEOF_DNS_ANSWER > 0xFFFF) { + 800ee06: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ee08: f64f 72f5 movw r2, #65525 ; 0xfff5 + 800ee0c: 4293 cmp r3, r2 + 800ee0e: f200 8087 bhi.w 800ef20 + goto ignore_packet; + } + res_idx = (u16_t)(res_idx + SIZEOF_DNS_ANSWER); + 800ee12: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ee14: 330a adds r3, #10 + 800ee16: 87bb strh r3, [r7, #60] ; 0x3c + + if (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) { + 800ee18: 8b7b ldrh r3, [r7, #26] + 800ee1a: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800ee1e: d12b bne.n 800ee78 +#if LWIP_IPV4 + if ((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.len == PP_HTONS(sizeof(ip4_addr_t)))) { + 800ee20: 8b3b ldrh r3, [r7, #24] + 800ee22: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800ee26: d127 bne.n 800ee78 + 800ee28: 8c3b ldrh r3, [r7, #32] + 800ee2a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800ee2e: d123 bne.n 800ee78 + if (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + { + ip4_addr_t ip4addr; + /* read the IP address after answer resource record's header */ + if (pbuf_copy_partial(p, &ip4addr, sizeof(ip4_addr_t), res_idx) != sizeof(ip4_addr_t)) { + 800ee30: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ee32: f107 0110 add.w r1, r7, #16 + 800ee36: 2204 movs r2, #4 + 800ee38: 6878 ldr r0, [r7, #4] + 800ee3a: f001 ffe7 bl 8010e0c + 800ee3e: 4603 mov r3, r0 + 800ee40: 2b04 cmp r3, #4 + 800ee42: d16f bne.n 800ef24 + goto ignore_packet; /* ignore this packet */ + } + ip_addr_copy_from_ip4(dns_table[i].ipaddr, ip4addr); + 800ee44: f897 203f ldrb.w r2, [r7, #63] ; 0x3f + 800ee48: 6939 ldr r1, [r7, #16] + 800ee4a: 483b ldr r0, [pc, #236] ; (800ef38 ) + 800ee4c: 4613 mov r3, r2 + 800ee4e: 011b lsls r3, r3, #4 + 800ee50: 4413 add r3, r2 + 800ee52: 011b lsls r3, r3, #4 + 800ee54: 4403 add r3, r0 + 800ee56: 3304 adds r3, #4 + 800ee58: 6019 str r1, [r3, #0] + pbuf_free(p); + 800ee5a: 6878 ldr r0, [r7, #4] + 800ee5c: f001 fdd0 bl 8010a00 + /* handle correct response */ + dns_correct_response(i, lwip_ntohl(ans.ttl)); + 800ee60: 69fb ldr r3, [r7, #28] + 800ee62: 4618 mov r0, r3 + 800ee64: f7ff f9f9 bl 800e25a + 800ee68: 4602 mov r2, r0 + 800ee6a: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 800ee6e: 4611 mov r1, r2 + 800ee70: 4618 mov r0, r3 + 800ee72: f7ff fedf bl 800ec34 + 800ee76: e05c b.n 800ef32 + } + } +#endif /* LWIP_IPV6 */ + } + /* skip this answer */ + if ((int)(res_idx + lwip_htons(ans.len)) > 0xFFFF) { + 800ee78: 8fbc ldrh r4, [r7, #60] ; 0x3c + 800ee7a: 8c3b ldrh r3, [r7, #32] + 800ee7c: 4618 mov r0, r3 + 800ee7e: f7ff f9d7 bl 800e230 + 800ee82: 4603 mov r3, r0 + 800ee84: 4423 add r3, r4 + 800ee86: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800ee8a: da4d bge.n 800ef28 + goto ignore_packet; /* ignore this packet */ + } + res_idx = (u16_t)(res_idx + lwip_htons(ans.len)); + 800ee8c: 8c3b ldrh r3, [r7, #32] + 800ee8e: 4618 mov r0, r3 + 800ee90: f7ff f9ce bl 800e230 + 800ee94: 4603 mov r3, r0 + 800ee96: 461a mov r2, r3 + 800ee98: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800ee9a: 4413 add r3, r2 + 800ee9c: 87bb strh r3, [r7, #60] ; 0x3c + --nanswers; + 800ee9e: 8f7b ldrh r3, [r7, #58] ; 0x3a + 800eea0: 3b01 subs r3, #1 + 800eea2: 877b strh r3, [r7, #58] ; 0x3a + while ((nanswers > 0) && (res_idx < p->tot_len)) { + 800eea4: 8f7b ldrh r3, [r7, #58] ; 0x3a + 800eea6: 2b00 cmp r3, #0 + 800eea8: d004 beq.n 800eeb4 + 800eeaa: 687b ldr r3, [r7, #4] + 800eeac: 891b ldrh r3, [r3, #8] + 800eeae: 8fba ldrh r2, [r7, #60] ; 0x3c + 800eeb0: 429a cmp r2, r3 + 800eeb2: d390 bcc.n 800edd6 + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", entry->name)); + } + /* call callback to indicate error, clean up memory and return */ + pbuf_free(p); + 800eeb4: 6878 ldr r0, [r7, #4] + 800eeb6: f001 fda3 bl 8010a00 + dns_call_found(i, NULL); + 800eeba: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 800eebe: 2100 movs r1, #0 + 800eec0: 4618 mov r0, r3 + 800eec2: f7ff fceb bl 800e89c + dns_table[i].state = DNS_STATE_UNUSED; + 800eec6: f897 203f ldrb.w r2, [r7, #63] ; 0x3f + 800eeca: 491b ldr r1, [pc, #108] ; (800ef38 ) + 800eecc: 4613 mov r3, r2 + 800eece: 011b lsls r3, r3, #4 + 800eed0: 4413 add r3, r2 + 800eed2: 011b lsls r3, r3, #4 + 800eed4: 440b add r3, r1 + 800eed6: 330a adds r3, #10 + 800eed8: 2200 movs r2, #0 + 800eeda: 701a strb r2, [r3, #0] + return; + 800eedc: e029 b.n 800ef32 + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800eede: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 800eee2: 3301 adds r3, #1 + 800eee4: f887 303f strb.w r3, [r7, #63] ; 0x3f + 800eee8: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 800eeec: 2b03 cmp r3, #3 + 800eeee: f67f aef8 bls.w 800ece2 + } + } + } + +ignore_packet: + 800eef2: e001 b.n 800eef8 + goto ignore_packet; + 800eef4: bf00 nop + 800eef6: e018 b.n 800ef2a +ignore_packet: + 800eef8: bf00 nop + 800eefa: e016 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800eefc: bf00 nop + 800eefe: e014 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef00: bf00 nop + 800ef02: e012 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef04: bf00 nop + 800ef06: e010 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef08: bf00 nop + 800ef0a: e00e b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef0c: bf00 nop + 800ef0e: e00c b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef10: bf00 nop + 800ef12: e00a b.n 800ef2a + goto ignore_packet; + 800ef14: bf00 nop + 800ef16: e008 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef18: bf00 nop + 800ef1a: e006 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef1c: bf00 nop + 800ef1e: e004 b.n 800ef2a + goto ignore_packet; + 800ef20: bf00 nop + 800ef22: e002 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef24: bf00 nop + 800ef26: e000 b.n 800ef2a + goto ignore_packet; /* ignore this packet */ + 800ef28: bf00 nop + /* deallocate memory and return */ + pbuf_free(p); + 800ef2a: 6878 ldr r0, [r7, #4] + 800ef2c: f001 fd68 bl 8010a00 + return; + 800ef30: bf00 nop +} + 800ef32: 3744 adds r7, #68 ; 0x44 + 800ef34: 46bd mov sp, r7 + 800ef36: bd90 pop {r4, r7, pc} + 800ef38: 200091f8 .word 0x200091f8 + 800ef3c: 20009668 .word 0x20009668 + +0800ef40 : + * @return err_t return code. + */ +static err_t +dns_enqueue(const char *name, size_t hostnamelen, dns_found_callback found, + void *callback_arg LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype) LWIP_DNS_ISMDNS_ARG(u8_t is_mdns)) +{ + 800ef40: b580 push {r7, lr} + 800ef42: b08a sub sp, #40 ; 0x28 + 800ef44: af00 add r7, sp, #0 + 800ef46: 60f8 str r0, [r7, #12] + 800ef48: 60b9 str r1, [r7, #8] + 800ef4a: 607a str r2, [r7, #4] + 800ef4c: 603b str r3, [r7, #0] + u8_t i; + u8_t lseq, lseqi; + struct dns_table_entry *entry = NULL; + 800ef4e: 2300 movs r3, #0 + 800ef50: 623b str r3, [r7, #32] + struct dns_req_entry *req; + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + u8_t r; + /* check for duplicate entries */ + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800ef52: 2300 movs r3, #0 + 800ef54: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800ef58: e056 b.n 800f008 + if ((dns_table[i].state == DNS_STATE_ASKING) && + 800ef5a: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800ef5e: 4990 ldr r1, [pc, #576] ; (800f1a0 ) + 800ef60: 4613 mov r3, r2 + 800ef62: 011b lsls r3, r3, #4 + 800ef64: 4413 add r3, r2 + 800ef66: 011b lsls r3, r3, #4 + 800ef68: 440b add r3, r1 + 800ef6a: 330a adds r3, #10 + 800ef6c: 781b ldrb r3, [r3, #0] + 800ef6e: 2b02 cmp r3, #2 + 800ef70: d145 bne.n 800effe + (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0)) { + 800ef72: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800ef76: 4613 mov r3, r2 + 800ef78: 011b lsls r3, r3, #4 + 800ef7a: 4413 add r3, r2 + 800ef7c: 011b lsls r3, r3, #4 + 800ef7e: 3310 adds r3, #16 + 800ef80: 4a87 ldr r2, [pc, #540] ; (800f1a0 ) + 800ef82: 4413 add r3, r2 + 800ef84: f44f 7280 mov.w r2, #256 ; 0x100 + 800ef88: 4619 mov r1, r3 + 800ef8a: 68f8 ldr r0, [r7, #12] + 800ef8c: f7ff f97e bl 800e28c + 800ef90: 4603 mov r3, r0 + if ((dns_table[i].state == DNS_STATE_ASKING) && + 800ef92: 2b00 cmp r3, #0 + 800ef94: d133 bne.n 800effe + for the same host should not be that common */ + continue; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + /* this is a duplicate entry, find a free request entry */ + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + 800ef96: 2300 movs r3, #0 + 800ef98: 76fb strb r3, [r7, #27] + 800ef9a: e02d b.n 800eff8 + if (dns_requests[r].found == 0) { + 800ef9c: 7efa ldrb r2, [r7, #27] + 800ef9e: 4981 ldr r1, [pc, #516] ; (800f1a4 ) + 800efa0: 4613 mov r3, r2 + 800efa2: 005b lsls r3, r3, #1 + 800efa4: 4413 add r3, r2 + 800efa6: 009b lsls r3, r3, #2 + 800efa8: 440b add r3, r1 + 800efaa: 681b ldr r3, [r3, #0] + 800efac: 2b00 cmp r3, #0 + 800efae: d120 bne.n 800eff2 + dns_requests[r].found = found; + 800efb0: 7efa ldrb r2, [r7, #27] + 800efb2: 497c ldr r1, [pc, #496] ; (800f1a4 ) + 800efb4: 4613 mov r3, r2 + 800efb6: 005b lsls r3, r3, #1 + 800efb8: 4413 add r3, r2 + 800efba: 009b lsls r3, r3, #2 + 800efbc: 440b add r3, r1 + 800efbe: 687a ldr r2, [r7, #4] + 800efc0: 601a str r2, [r3, #0] + dns_requests[r].arg = callback_arg; + 800efc2: 7efa ldrb r2, [r7, #27] + 800efc4: 4977 ldr r1, [pc, #476] ; (800f1a4 ) + 800efc6: 4613 mov r3, r2 + 800efc8: 005b lsls r3, r3, #1 + 800efca: 4413 add r3, r2 + 800efcc: 009b lsls r3, r3, #2 + 800efce: 440b add r3, r1 + 800efd0: 3304 adds r3, #4 + 800efd2: 683a ldr r2, [r7, #0] + 800efd4: 601a str r2, [r3, #0] + dns_requests[r].dns_table_idx = i; + 800efd6: 7efa ldrb r2, [r7, #27] + 800efd8: 4972 ldr r1, [pc, #456] ; (800f1a4 ) + 800efda: 4613 mov r3, r2 + 800efdc: 005b lsls r3, r3, #1 + 800efde: 4413 add r3, r2 + 800efe0: 009b lsls r3, r3, #2 + 800efe2: 440b add r3, r1 + 800efe4: 3308 adds r3, #8 + 800efe6: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800efea: 701a strb r2, [r3, #0] + LWIP_DNS_SET_ADDRTYPE(dns_requests[r].reqaddrtype, dns_addrtype); + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": duplicate request\n", name)); + return ERR_INPROGRESS; + 800efec: f06f 0304 mvn.w r3, #4 + 800eff0: e0d1 b.n 800f196 + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + 800eff2: 7efb ldrb r3, [r7, #27] + 800eff4: 3301 adds r3, #1 + 800eff6: 76fb strb r3, [r7, #27] + 800eff8: 7efb ldrb r3, [r7, #27] + 800effa: 2b03 cmp r3, #3 + 800effc: d9ce bls.n 800ef9c + for (i = 0; i < DNS_TABLE_SIZE; i++) { + 800effe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f002: 3301 adds r3, #1 + 800f004: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800f008: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f00c: 2b03 cmp r3, #3 + 800f00e: d9a4 bls.n 800ef5a + } + /* no duplicate entries found */ +#endif + + /* search an unused entry, or the oldest one */ + lseq = 0; + 800f010: 2300 movs r3, #0 + 800f012: f887 3026 strb.w r3, [r7, #38] ; 0x26 + lseqi = DNS_TABLE_SIZE; + 800f016: 2304 movs r3, #4 + 800f018: f887 3025 strb.w r3, [r7, #37] ; 0x25 + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800f01c: 2300 movs r3, #0 + 800f01e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800f022: e027 b.n 800f074 + entry = &dns_table[i]; + 800f024: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800f028: 4613 mov r3, r2 + 800f02a: 011b lsls r3, r3, #4 + 800f02c: 4413 add r3, r2 + 800f02e: 011b lsls r3, r3, #4 + 800f030: 4a5b ldr r2, [pc, #364] ; (800f1a0 ) + 800f032: 4413 add r3, r2 + 800f034: 623b str r3, [r7, #32] + /* is it an unused entry ? */ + if (entry->state == DNS_STATE_UNUSED) { + 800f036: 6a3b ldr r3, [r7, #32] + 800f038: 7a9b ldrb r3, [r3, #10] + 800f03a: 2b00 cmp r3, #0 + 800f03c: d01f beq.n 800f07e + break; + } + /* check if this is the oldest completed entry */ + if (entry->state == DNS_STATE_DONE) { + 800f03e: 6a3b ldr r3, [r7, #32] + 800f040: 7a9b ldrb r3, [r3, #10] + 800f042: 2b03 cmp r3, #3 + 800f044: d111 bne.n 800f06a + u8_t age = (u8_t)(dns_seqno - entry->seqno); + 800f046: 4b58 ldr r3, [pc, #352] ; (800f1a8 ) + 800f048: 781a ldrb r2, [r3, #0] + 800f04a: 6a3b ldr r3, [r7, #32] + 800f04c: 7b9b ldrb r3, [r3, #14] + 800f04e: 1ad3 subs r3, r2, r3 + 800f050: 76bb strb r3, [r7, #26] + if (age > lseq) { + 800f052: 7eba ldrb r2, [r7, #26] + 800f054: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800f058: 429a cmp r2, r3 + 800f05a: d906 bls.n 800f06a + lseq = age; + 800f05c: 7ebb ldrb r3, [r7, #26] + 800f05e: f887 3026 strb.w r3, [r7, #38] ; 0x26 + lseqi = i; + 800f062: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f066: f887 3025 strb.w r3, [r7, #37] ; 0x25 + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + 800f06a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f06e: 3301 adds r3, #1 + 800f070: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800f074: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f078: 2b03 cmp r3, #3 + 800f07a: d9d3 bls.n 800f024 + 800f07c: e000 b.n 800f080 + break; + 800f07e: bf00 nop + } + } + } + + /* if we don't have found an unused entry, use the oldest completed one */ + if (i == DNS_TABLE_SIZE) { + 800f080: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f084: 2b04 cmp r3, #4 + 800f086: d11f bne.n 800f0c8 + if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) { + 800f088: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 + 800f08c: 2b03 cmp r3, #3 + 800f08e: d80b bhi.n 800f0a8 + 800f090: f897 2025 ldrb.w r2, [r7, #37] ; 0x25 + 800f094: 4942 ldr r1, [pc, #264] ; (800f1a0 ) + 800f096: 4613 mov r3, r2 + 800f098: 011b lsls r3, r3, #4 + 800f09a: 4413 add r3, r2 + 800f09c: 011b lsls r3, r3, #4 + 800f09e: 440b add r3, r1 + 800f0a0: 330a adds r3, #10 + 800f0a2: 781b ldrb r3, [r3, #0] + 800f0a4: 2b03 cmp r3, #3 + 800f0a6: d002 beq.n 800f0ae + /* no entry can be used now, table is full */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name)); + return ERR_MEM; + 800f0a8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800f0ac: e073 b.n 800f196 + } else { + /* use the oldest completed one */ + i = lseqi; + 800f0ae: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 + 800f0b2: f887 3027 strb.w r3, [r7, #39] ; 0x27 + entry = &dns_table[i]; + 800f0b6: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800f0ba: 4613 mov r3, r2 + 800f0bc: 011b lsls r3, r3, #4 + 800f0be: 4413 add r3, r2 + 800f0c0: 011b lsls r3, r3, #4 + 800f0c2: 4a37 ldr r2, [pc, #220] ; (800f1a0 ) + 800f0c4: 4413 add r3, r2 + 800f0c6: 623b str r3, [r7, #32] + } + } + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + /* find a free request entry */ + req = NULL; + 800f0c8: 2300 movs r3, #0 + 800f0ca: 61fb str r3, [r7, #28] + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + 800f0cc: 2300 movs r3, #0 + 800f0ce: 76fb strb r3, [r7, #27] + 800f0d0: e015 b.n 800f0fe + if (dns_requests[r].found == NULL) { + 800f0d2: 7efa ldrb r2, [r7, #27] + 800f0d4: 4933 ldr r1, [pc, #204] ; (800f1a4 ) + 800f0d6: 4613 mov r3, r2 + 800f0d8: 005b lsls r3, r3, #1 + 800f0da: 4413 add r3, r2 + 800f0dc: 009b lsls r3, r3, #2 + 800f0de: 440b add r3, r1 + 800f0e0: 681b ldr r3, [r3, #0] + 800f0e2: 2b00 cmp r3, #0 + 800f0e4: d108 bne.n 800f0f8 + req = &dns_requests[r]; + 800f0e6: 7efa ldrb r2, [r7, #27] + 800f0e8: 4613 mov r3, r2 + 800f0ea: 005b lsls r3, r3, #1 + 800f0ec: 4413 add r3, r2 + 800f0ee: 009b lsls r3, r3, #2 + 800f0f0: 4a2c ldr r2, [pc, #176] ; (800f1a4 ) + 800f0f2: 4413 add r3, r2 + 800f0f4: 61fb str r3, [r7, #28] + break; + 800f0f6: e005 b.n 800f104 + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + 800f0f8: 7efb ldrb r3, [r7, #27] + 800f0fa: 3301 adds r3, #1 + 800f0fc: 76fb strb r3, [r7, #27] + 800f0fe: 7efb ldrb r3, [r7, #27] + 800f100: 2b03 cmp r3, #3 + 800f102: d9e6 bls.n 800f0d2 + } + } + if (req == NULL) { + 800f104: 69fb ldr r3, [r7, #28] + 800f106: 2b00 cmp r3, #0 + 800f108: d102 bne.n 800f110 + /* no request entry can be used now, table is full */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS request entries table is full\n", name)); + return ERR_MEM; + 800f10a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800f10e: e042 b.n 800f196 + } + req->dns_table_idx = i; + 800f110: 69fb ldr r3, [r7, #28] + 800f112: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800f116: 721a strb r2, [r3, #8] + + /* use this entry */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i))); + + /* fill the entry */ + entry->state = DNS_STATE_NEW; + 800f118: 6a3b ldr r3, [r7, #32] + 800f11a: 2201 movs r2, #1 + 800f11c: 729a strb r2, [r3, #10] + entry->seqno = dns_seqno; + 800f11e: 4b22 ldr r3, [pc, #136] ; (800f1a8 ) + 800f120: 781a ldrb r2, [r3, #0] + 800f122: 6a3b ldr r3, [r7, #32] + 800f124: 739a strb r2, [r3, #14] + LWIP_DNS_SET_ADDRTYPE(entry->reqaddrtype, dns_addrtype); + LWIP_DNS_SET_ADDRTYPE(req->reqaddrtype, dns_addrtype); + req->found = found; + 800f126: 69fb ldr r3, [r7, #28] + 800f128: 687a ldr r2, [r7, #4] + 800f12a: 601a str r2, [r3, #0] + req->arg = callback_arg; + 800f12c: 69fb ldr r3, [r7, #28] + 800f12e: 683a ldr r2, [r7, #0] + 800f130: 605a str r2, [r3, #4] + namelen = LWIP_MIN(hostnamelen, DNS_MAX_NAME_LENGTH - 1); + 800f132: 68bb ldr r3, [r7, #8] + 800f134: 2bff cmp r3, #255 ; 0xff + 800f136: bf28 it cs + 800f138: 23ff movcs r3, #255 ; 0xff + 800f13a: 617b str r3, [r7, #20] + MEMCPY(entry->name, name, namelen); + 800f13c: 6a3b ldr r3, [r7, #32] + 800f13e: 3310 adds r3, #16 + 800f140: 697a ldr r2, [r7, #20] + 800f142: 68f9 ldr r1, [r7, #12] + 800f144: 4618 mov r0, r3 + 800f146: f00c fea0 bl 801be8a + entry->name[namelen] = 0; + 800f14a: 6a3a ldr r2, [r7, #32] + 800f14c: 697b ldr r3, [r7, #20] + 800f14e: 4413 add r3, r2 + 800f150: 3310 adds r3, #16 + 800f152: 2200 movs r2, #0 + 800f154: 701a strb r2, [r3, #0] + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + entry->pcb_idx = dns_alloc_pcb(); + 800f156: f7ff fb4f bl 800e7f8 + 800f15a: 4603 mov r3, r0 + 800f15c: 461a mov r2, r3 + 800f15e: 6a3b ldr r3, [r7, #32] + 800f160: 73da strb r2, [r3, #15] + if (entry->pcb_idx >= DNS_MAX_SOURCE_PORTS) { + 800f162: 6a3b ldr r3, [r7, #32] + 800f164: 7bdb ldrb r3, [r3, #15] + 800f166: 2b03 cmp r3, #3 + 800f168: d908 bls.n 800f17c + /* failed to get a UDP pcb */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": failed to allocate a pcb\n", name)); + entry->state = DNS_STATE_UNUSED; + 800f16a: 6a3b ldr r3, [r7, #32] + 800f16c: 2200 movs r2, #0 + 800f16e: 729a strb r2, [r3, #10] + req->found = NULL; + 800f170: 69fb ldr r3, [r7, #28] + 800f172: 2200 movs r2, #0 + 800f174: 601a str r2, [r3, #0] + return ERR_MEM; + 800f176: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800f17a: e00c b.n 800f196 + +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + entry->is_mdns = is_mdns; +#endif + + dns_seqno++; + 800f17c: 4b0a ldr r3, [pc, #40] ; (800f1a8 ) + 800f17e: 781b ldrb r3, [r3, #0] + 800f180: 3301 adds r3, #1 + 800f182: b2da uxtb r2, r3 + 800f184: 4b08 ldr r3, [pc, #32] ; (800f1a8 ) + 800f186: 701a strb r2, [r3, #0] + + /* force to send query without waiting timer */ + dns_check_entry(i); + 800f188: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800f18c: 4618 mov r0, r3 + 800f18e: f7ff fc95 bl 800eabc + + /* dns query is enqueued */ + return ERR_INPROGRESS; + 800f192: f06f 0304 mvn.w r3, #4 +} + 800f196: 4618 mov r0, r3 + 800f198: 3728 adds r7, #40 ; 0x28 + 800f19a: 46bd mov sp, r7 + 800f19c: bd80 pop {r7, pc} + 800f19e: bf00 nop + 800f1a0: 200091f8 .word 0x200091f8 + 800f1a4: 20009638 .word 0x20009638 + 800f1a8: 200091f5 .word 0x200091f5 + +0800f1ac : + * @return a err_t return code. + */ +err_t +dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found, + void *callback_arg) +{ + 800f1ac: b580 push {r7, lr} + 800f1ae: b086 sub sp, #24 + 800f1b0: af02 add r7, sp, #8 + 800f1b2: 60f8 str r0, [r7, #12] + 800f1b4: 60b9 str r1, [r7, #8] + 800f1b6: 607a str r2, [r7, #4] + 800f1b8: 603b str r3, [r7, #0] + return dns_gethostbyname_addrtype(hostname, addr, found, callback_arg, LWIP_DNS_ADDRTYPE_DEFAULT); + 800f1ba: 2300 movs r3, #0 + 800f1bc: 9300 str r3, [sp, #0] + 800f1be: 683b ldr r3, [r7, #0] + 800f1c0: 687a ldr r2, [r7, #4] + 800f1c2: 68b9 ldr r1, [r7, #8] + 800f1c4: 68f8 ldr r0, [r7, #12] + 800f1c6: f000 f805 bl 800f1d4 + 800f1ca: 4603 mov r3, r0 +} + 800f1cc: 4618 mov r0, r3 + 800f1ce: 3710 adds r7, #16 + 800f1d0: 46bd mov sp, r7 + 800f1d2: bd80 pop {r7, pc} + +0800f1d4 : + * - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only + */ +err_t +dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, dns_found_callback found, + void *callback_arg, u8_t dns_addrtype) +{ + 800f1d4: b580 push {r7, lr} + 800f1d6: b086 sub sp, #24 + 800f1d8: af00 add r7, sp, #0 + 800f1da: 60f8 str r0, [r7, #12] + 800f1dc: 60b9 str r1, [r7, #8] + 800f1de: 607a str r2, [r7, #4] + 800f1e0: 603b str r3, [r7, #0] +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + u8_t is_mdns; +#endif + /* not initialized or no valid server yet, or invalid addr pointer + * or invalid hostname or invalid hostname length */ + if ((addr == NULL) || + 800f1e2: 68bb ldr r3, [r7, #8] + 800f1e4: 2b00 cmp r3, #0 + 800f1e6: d006 beq.n 800f1f6 + 800f1e8: 68fb ldr r3, [r7, #12] + 800f1ea: 2b00 cmp r3, #0 + 800f1ec: d003 beq.n 800f1f6 + (!hostname) || (!hostname[0])) { + 800f1ee: 68fb ldr r3, [r7, #12] + 800f1f0: 781b ldrb r3, [r3, #0] + 800f1f2: 2b00 cmp r3, #0 + 800f1f4: d102 bne.n 800f1fc + return ERR_ARG; + 800f1f6: f06f 030f mvn.w r3, #15 + 800f1fa: e029 b.n 800f250 +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0) + if (dns_pcbs[0] == NULL) { + return ERR_ARG; + } +#endif + hostnamelen = strlen(hostname); + 800f1fc: 68f8 ldr r0, [r7, #12] + 800f1fe: f7f1 f807 bl 8000210 + 800f202: 6178 str r0, [r7, #20] + if (hostnamelen >= DNS_MAX_NAME_LENGTH) { + 800f204: 697b ldr r3, [r7, #20] + 800f206: 2bff cmp r3, #255 ; 0xff + 800f208: d902 bls.n 800f210 + LWIP_DEBUGF(DNS_DEBUG, ("dns_gethostbyname: name too long to resolve")); + return ERR_ARG; + 800f20a: f06f 030f mvn.w r3, #15 + 800f20e: e01f b.n 800f250 + return ERR_OK; + } +#endif /* LWIP_HAVE_LOOPIF */ + + /* host name already in octet notation? set ip addr and return ERR_OK */ + if (ipaddr_aton(hostname, addr)) { + 800f210: 68b9 ldr r1, [r7, #8] + 800f212: 68f8 ldr r0, [r7, #12] + 800f214: f00b fb28 bl 801a868 + 800f218: 4603 mov r3, r0 + 800f21a: 2b00 cmp r3, #0 + 800f21c: d001 beq.n 800f222 +#if LWIP_IPV4 && LWIP_IPV6 + if ((IP_IS_V6(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV4)) || + (IP_IS_V4(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV6))) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + { + return ERR_OK; + 800f21e: 2300 movs r3, #0 + 800f220: e016 b.n 800f250 + } + } + /* already have this address cached? */ + if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) { + 800f222: 68b9 ldr r1, [r7, #8] + 800f224: 68f8 ldr r0, [r7, #12] + 800f226: f7ff f89d bl 800e364 + 800f22a: 4603 mov r3, r0 + 800f22c: 2b00 cmp r3, #0 + 800f22e: d101 bne.n 800f234 + return ERR_OK; + 800f230: 2300 movs r3, #0 + 800f232: e00d b.n 800f250 + + if (!is_mdns) +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + /* prevent calling found callback if no server is set, return error instead */ + if (ip_addr_isany_val(dns_servers[0])) { + 800f234: 4b08 ldr r3, [pc, #32] ; (800f258 ) + 800f236: 681b ldr r3, [r3, #0] + 800f238: 2b00 cmp r3, #0 + 800f23a: d102 bne.n 800f242 + return ERR_VAL; + 800f23c: f06f 0305 mvn.w r3, #5 + 800f240: e006 b.n 800f250 + } + } + + /* queue query with specified callback */ + return dns_enqueue(hostname, hostnamelen, found, callback_arg LWIP_DNS_ADDRTYPE_ARG(dns_addrtype) + 800f242: 683b ldr r3, [r7, #0] + 800f244: 687a ldr r2, [r7, #4] + 800f246: 6979 ldr r1, [r7, #20] + 800f248: 68f8 ldr r0, [r7, #12] + 800f24a: f7ff fe79 bl 800ef40 + 800f24e: 4603 mov r3, r0 + LWIP_DNS_ISMDNS_ARG(is_mdns)); +} + 800f250: 4618 mov r0, r3 + 800f252: 3718 adds r7, #24 + 800f254: 46bd mov sp, r7 + 800f256: bd80 pop {r7, pc} + 800f258: 20009668 .word 0x20009668 + +0800f25c : + * Initialize all modules. + * Use this in NO_SYS mode. Use tcpip_init() otherwise. + */ +void +lwip_init(void) +{ + 800f25c: b580 push {r7, lr} + 800f25e: b082 sub sp, #8 + 800f260: af00 add r7, sp, #0 +#ifndef LWIP_SKIP_CONST_CHECK + int a = 0; + 800f262: 2300 movs r3, #0 + 800f264: 607b str r3, [r7, #4] +#endif + + /* Modules initialization */ + stats_init(); +#if !NO_SYS + sys_init(); + 800f266: f00c fc59 bl 801bb1c +#endif /* !NO_SYS */ + mem_init(); + 800f26a: f000 f8d7 bl 800f41c + memp_init(); + 800f26e: f000 fc33 bl 800fad8 + pbuf_init(); + netif_init(); + 800f272: f000 fd3f bl 800fcf4 +#endif /* LWIP_IPV4 */ +#if LWIP_RAW + raw_init(); +#endif /* LWIP_RAW */ +#if LWIP_UDP + udp_init(); + 800f276: f007 fabf bl 80167f8 +#endif /* LWIP_UDP */ +#if LWIP_TCP + tcp_init(); + 800f27a: f001 ffe7 bl 801124c +#endif /* LWIP_TCP */ +#if LWIP_IGMP + igmp_init(); +#endif /* LWIP_IGMP */ +#if LWIP_DNS + dns_init(); + 800f27e: f7ff f840 bl 800e302 +#if PPP_SUPPORT + ppp_init(); +#endif + +#if LWIP_TIMERS + sys_timeouts_init(); + 800f282: f007 f9ff bl 8016684 +#endif /* LWIP_TIMERS */ +} + 800f286: bf00 nop + 800f288: 3708 adds r7, #8 + 800f28a: 46bd mov sp, r7 + 800f28c: bd80 pop {r7, pc} + ... + +0800f290 : +#define mem_overflow_check_element(mem) +#endif /* MEM_OVERFLOW_CHECK */ + +static struct mem * +ptr_to_mem(mem_size_t ptr) +{ + 800f290: b480 push {r7} + 800f292: b083 sub sp, #12 + 800f294: af00 add r7, sp, #0 + 800f296: 4603 mov r3, r0 + 800f298: 80fb strh r3, [r7, #6] + return (struct mem *)(void *)&ram[ptr]; + 800f29a: 4b05 ldr r3, [pc, #20] ; (800f2b0 ) + 800f29c: 681a ldr r2, [r3, #0] + 800f29e: 88fb ldrh r3, [r7, #6] + 800f2a0: 4413 add r3, r2 +} + 800f2a2: 4618 mov r0, r3 + 800f2a4: 370c adds r7, #12 + 800f2a6: 46bd mov sp, r7 + 800f2a8: f85d 7b04 ldr.w r7, [sp], #4 + 800f2ac: 4770 bx lr + 800f2ae: bf00 nop + 800f2b0: 20009cdc .word 0x20009cdc + +0800f2b4 : + +static mem_size_t +mem_to_ptr(void *mem) +{ + 800f2b4: b480 push {r7} + 800f2b6: b083 sub sp, #12 + 800f2b8: af00 add r7, sp, #0 + 800f2ba: 6078 str r0, [r7, #4] + return (mem_size_t)((u8_t *)mem - ram); + 800f2bc: 4b05 ldr r3, [pc, #20] ; (800f2d4 ) + 800f2be: 681b ldr r3, [r3, #0] + 800f2c0: 687a ldr r2, [r7, #4] + 800f2c2: 1ad3 subs r3, r2, r3 + 800f2c4: b29b uxth r3, r3 +} + 800f2c6: 4618 mov r0, r3 + 800f2c8: 370c adds r7, #12 + 800f2ca: 46bd mov sp, r7 + 800f2cc: f85d 7b04 ldr.w r7, [sp], #4 + 800f2d0: 4770 bx lr + 800f2d2: bf00 nop + 800f2d4: 20009cdc .word 0x20009cdc + +0800f2d8 : + * This assumes access to the heap is protected by the calling function + * already. + */ +static void +plug_holes(struct mem *mem) +{ + 800f2d8: b590 push {r4, r7, lr} + 800f2da: b085 sub sp, #20 + 800f2dc: af00 add r7, sp, #0 + 800f2de: 6078 str r0, [r7, #4] + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + 800f2e0: 4b45 ldr r3, [pc, #276] ; (800f3f8 ) + 800f2e2: 681b ldr r3, [r3, #0] + 800f2e4: 687a ldr r2, [r7, #4] + 800f2e6: 429a cmp r2, r3 + 800f2e8: d206 bcs.n 800f2f8 + 800f2ea: 4b44 ldr r3, [pc, #272] ; (800f3fc ) + 800f2ec: f240 12df movw r2, #479 ; 0x1df + 800f2f0: 4943 ldr r1, [pc, #268] ; (800f400 ) + 800f2f2: 4844 ldr r0, [pc, #272] ; (800f404 ) + 800f2f4: f00c fe8e bl 801c014 + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + 800f2f8: 4b43 ldr r3, [pc, #268] ; (800f408 ) + 800f2fa: 681b ldr r3, [r3, #0] + 800f2fc: 687a ldr r2, [r7, #4] + 800f2fe: 429a cmp r2, r3 + 800f300: d306 bcc.n 800f310 + 800f302: 4b3e ldr r3, [pc, #248] ; (800f3fc ) + 800f304: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 800f308: 4940 ldr r1, [pc, #256] ; (800f40c ) + 800f30a: 483e ldr r0, [pc, #248] ; (800f404 ) + 800f30c: f00c fe82 bl 801c014 + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + 800f310: 687b ldr r3, [r7, #4] + 800f312: 791b ldrb r3, [r3, #4] + 800f314: 2b00 cmp r3, #0 + 800f316: d006 beq.n 800f326 + 800f318: 4b38 ldr r3, [pc, #224] ; (800f3fc ) + 800f31a: f240 12e1 movw r2, #481 ; 0x1e1 + 800f31e: 493c ldr r1, [pc, #240] ; (800f410 ) + 800f320: 4838 ldr r0, [pc, #224] ; (800f404 ) + 800f322: f00c fe77 bl 801c014 + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); + 800f326: 687b ldr r3, [r7, #4] + 800f328: 881b ldrh r3, [r3, #0] + 800f32a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f32e: d906 bls.n 800f33e + 800f330: 4b32 ldr r3, [pc, #200] ; (800f3fc ) + 800f332: f44f 72f2 mov.w r2, #484 ; 0x1e4 + 800f336: 4937 ldr r1, [pc, #220] ; (800f414 ) + 800f338: 4832 ldr r0, [pc, #200] ; (800f404 ) + 800f33a: f00c fe6b bl 801c014 + + nmem = ptr_to_mem(mem->next); + 800f33e: 687b ldr r3, [r7, #4] + 800f340: 881b ldrh r3, [r3, #0] + 800f342: 4618 mov r0, r3 + 800f344: f7ff ffa4 bl 800f290 + 800f348: 60f8 str r0, [r7, #12] + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + 800f34a: 687a ldr r2, [r7, #4] + 800f34c: 68fb ldr r3, [r7, #12] + 800f34e: 429a cmp r2, r3 + 800f350: d024 beq.n 800f39c + 800f352: 68fb ldr r3, [r7, #12] + 800f354: 791b ldrb r3, [r3, #4] + 800f356: 2b00 cmp r3, #0 + 800f358: d120 bne.n 800f39c + 800f35a: 4b2b ldr r3, [pc, #172] ; (800f408 ) + 800f35c: 681b ldr r3, [r3, #0] + 800f35e: 68fa ldr r2, [r7, #12] + 800f360: 429a cmp r2, r3 + 800f362: d01b beq.n 800f39c + /* if mem->next is unused and not end of ram, combine mem and mem->next */ + if (lfree == nmem) { + 800f364: 4b2c ldr r3, [pc, #176] ; (800f418 ) + 800f366: 681b ldr r3, [r3, #0] + 800f368: 68fa ldr r2, [r7, #12] + 800f36a: 429a cmp r2, r3 + 800f36c: d102 bne.n 800f374 + lfree = mem; + 800f36e: 4a2a ldr r2, [pc, #168] ; (800f418 ) + 800f370: 687b ldr r3, [r7, #4] + 800f372: 6013 str r3, [r2, #0] + } + mem->next = nmem->next; + 800f374: 68fb ldr r3, [r7, #12] + 800f376: 881a ldrh r2, [r3, #0] + 800f378: 687b ldr r3, [r7, #4] + 800f37a: 801a strh r2, [r3, #0] + if (nmem->next != MEM_SIZE_ALIGNED) { + 800f37c: 68fb ldr r3, [r7, #12] + 800f37e: 881b ldrh r3, [r3, #0] + 800f380: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f384: d00a beq.n 800f39c + ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem); + 800f386: 68fb ldr r3, [r7, #12] + 800f388: 881b ldrh r3, [r3, #0] + 800f38a: 4618 mov r0, r3 + 800f38c: f7ff ff80 bl 800f290 + 800f390: 4604 mov r4, r0 + 800f392: 6878 ldr r0, [r7, #4] + 800f394: f7ff ff8e bl 800f2b4 + 800f398: 4603 mov r3, r0 + 800f39a: 8063 strh r3, [r4, #2] + } + } + + /* plug hole backward */ + pmem = ptr_to_mem(mem->prev); + 800f39c: 687b ldr r3, [r7, #4] + 800f39e: 885b ldrh r3, [r3, #2] + 800f3a0: 4618 mov r0, r3 + 800f3a2: f7ff ff75 bl 800f290 + 800f3a6: 60b8 str r0, [r7, #8] + if (pmem != mem && pmem->used == 0) { + 800f3a8: 68ba ldr r2, [r7, #8] + 800f3aa: 687b ldr r3, [r7, #4] + 800f3ac: 429a cmp r2, r3 + 800f3ae: d01f beq.n 800f3f0 + 800f3b0: 68bb ldr r3, [r7, #8] + 800f3b2: 791b ldrb r3, [r3, #4] + 800f3b4: 2b00 cmp r3, #0 + 800f3b6: d11b bne.n 800f3f0 + /* if mem->prev is unused, combine mem and mem->prev */ + if (lfree == mem) { + 800f3b8: 4b17 ldr r3, [pc, #92] ; (800f418 ) + 800f3ba: 681b ldr r3, [r3, #0] + 800f3bc: 687a ldr r2, [r7, #4] + 800f3be: 429a cmp r2, r3 + 800f3c0: d102 bne.n 800f3c8 + lfree = pmem; + 800f3c2: 4a15 ldr r2, [pc, #84] ; (800f418 ) + 800f3c4: 68bb ldr r3, [r7, #8] + 800f3c6: 6013 str r3, [r2, #0] + } + pmem->next = mem->next; + 800f3c8: 687b ldr r3, [r7, #4] + 800f3ca: 881a ldrh r2, [r3, #0] + 800f3cc: 68bb ldr r3, [r7, #8] + 800f3ce: 801a strh r2, [r3, #0] + if (mem->next != MEM_SIZE_ALIGNED) { + 800f3d0: 687b ldr r3, [r7, #4] + 800f3d2: 881b ldrh r3, [r3, #0] + 800f3d4: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f3d8: d00a beq.n 800f3f0 + ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem); + 800f3da: 687b ldr r3, [r7, #4] + 800f3dc: 881b ldrh r3, [r3, #0] + 800f3de: 4618 mov r0, r3 + 800f3e0: f7ff ff56 bl 800f290 + 800f3e4: 4604 mov r4, r0 + 800f3e6: 68b8 ldr r0, [r7, #8] + 800f3e8: f7ff ff64 bl 800f2b4 + 800f3ec: 4603 mov r3, r0 + 800f3ee: 8063 strh r3, [r4, #2] + } + } +} + 800f3f0: bf00 nop + 800f3f2: 3714 adds r7, #20 + 800f3f4: 46bd mov sp, r7 + 800f3f6: bd90 pop {r4, r7, pc} + 800f3f8: 20009cdc .word 0x20009cdc + 800f3fc: 0801ea8c .word 0x0801ea8c + 800f400: 0801eabc .word 0x0801eabc + 800f404: 0801ead4 .word 0x0801ead4 + 800f408: 20009ce0 .word 0x20009ce0 + 800f40c: 0801eafc .word 0x0801eafc + 800f410: 0801eb18 .word 0x0801eb18 + 800f414: 0801eb34 .word 0x0801eb34 + 800f418: 20009ce8 .word 0x20009ce8 + +0800f41c : +/** + * Zero the heap and initialize start, end and lowest-free + */ +void +mem_init(void) +{ + 800f41c: b580 push {r7, lr} + 800f41e: b082 sub sp, #8 + 800f420: af00 add r7, sp, #0 + + LWIP_ASSERT("Sanity check alignment", + (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0); + + /* align the heap */ + ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); + 800f422: 4b1f ldr r3, [pc, #124] ; (800f4a0 ) + 800f424: 3303 adds r3, #3 + 800f426: f023 0303 bic.w r3, r3, #3 + 800f42a: 461a mov r2, r3 + 800f42c: 4b1d ldr r3, [pc, #116] ; (800f4a4 ) + 800f42e: 601a str r2, [r3, #0] + /* initialize the start of the heap */ + mem = (struct mem *)(void *)ram; + 800f430: 4b1c ldr r3, [pc, #112] ; (800f4a4 ) + 800f432: 681b ldr r3, [r3, #0] + 800f434: 607b str r3, [r7, #4] + mem->next = MEM_SIZE_ALIGNED; + 800f436: 687b ldr r3, [r7, #4] + 800f438: f44f 62c8 mov.w r2, #1600 ; 0x640 + 800f43c: 801a strh r2, [r3, #0] + mem->prev = 0; + 800f43e: 687b ldr r3, [r7, #4] + 800f440: 2200 movs r2, #0 + 800f442: 805a strh r2, [r3, #2] + mem->used = 0; + 800f444: 687b ldr r3, [r7, #4] + 800f446: 2200 movs r2, #0 + 800f448: 711a strb r2, [r3, #4] + /* initialize the end of the heap */ + ram_end = ptr_to_mem(MEM_SIZE_ALIGNED); + 800f44a: f44f 60c8 mov.w r0, #1600 ; 0x640 + 800f44e: f7ff ff1f bl 800f290 + 800f452: 4603 mov r3, r0 + 800f454: 4a14 ldr r2, [pc, #80] ; (800f4a8 ) + 800f456: 6013 str r3, [r2, #0] + ram_end->used = 1; + 800f458: 4b13 ldr r3, [pc, #76] ; (800f4a8 ) + 800f45a: 681b ldr r3, [r3, #0] + 800f45c: 2201 movs r2, #1 + 800f45e: 711a strb r2, [r3, #4] + ram_end->next = MEM_SIZE_ALIGNED; + 800f460: 4b11 ldr r3, [pc, #68] ; (800f4a8 ) + 800f462: 681b ldr r3, [r3, #0] + 800f464: f44f 62c8 mov.w r2, #1600 ; 0x640 + 800f468: 801a strh r2, [r3, #0] + ram_end->prev = MEM_SIZE_ALIGNED; + 800f46a: 4b0f ldr r3, [pc, #60] ; (800f4a8 ) + 800f46c: 681b ldr r3, [r3, #0] + 800f46e: f44f 62c8 mov.w r2, #1600 ; 0x640 + 800f472: 805a strh r2, [r3, #2] + MEM_SANITY(); + + /* initialize the lowest-free pointer to the start of the heap */ + lfree = (struct mem *)(void *)ram; + 800f474: 4b0b ldr r3, [pc, #44] ; (800f4a4 ) + 800f476: 681b ldr r3, [r3, #0] + 800f478: 4a0c ldr r2, [pc, #48] ; (800f4ac ) + 800f47a: 6013 str r3, [r2, #0] + + MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); + + if (sys_mutex_new(&mem_mutex) != ERR_OK) { + 800f47c: 480c ldr r0, [pc, #48] ; (800f4b0 ) + 800f47e: f00c fb5b bl 801bb38 + 800f482: 4603 mov r3, r0 + 800f484: 2b00 cmp r3, #0 + 800f486: d006 beq.n 800f496 + LWIP_ASSERT("failed to create mem_mutex", 0); + 800f488: 4b0a ldr r3, [pc, #40] ; (800f4b4 ) + 800f48a: f240 221f movw r2, #543 ; 0x21f + 800f48e: 490a ldr r1, [pc, #40] ; (800f4b8 ) + 800f490: 480a ldr r0, [pc, #40] ; (800f4bc ) + 800f492: f00c fdbf bl 801c014 + } +} + 800f496: bf00 nop + 800f498: 3708 adds r7, #8 + 800f49a: 46bd mov sp, r7 + 800f49c: bd80 pop {r7, pc} + 800f49e: bf00 nop + 800f4a0: 20009688 .word 0x20009688 + 800f4a4: 20009cdc .word 0x20009cdc + 800f4a8: 20009ce0 .word 0x20009ce0 + 800f4ac: 20009ce8 .word 0x20009ce8 + 800f4b0: 20009ce4 .word 0x20009ce4 + 800f4b4: 0801ea8c .word 0x0801ea8c + 800f4b8: 0801eb60 .word 0x0801eb60 + 800f4bc: 0801ead4 .word 0x0801ead4 + +0800f4c0 : +/* Check if a struct mem is correctly linked. + * If not, double-free is a possible reason. + */ +static int +mem_link_valid(struct mem *mem) +{ + 800f4c0: b580 push {r7, lr} + 800f4c2: b086 sub sp, #24 + 800f4c4: af00 add r7, sp, #0 + 800f4c6: 6078 str r0, [r7, #4] + struct mem *nmem, *pmem; + mem_size_t rmem_idx; + rmem_idx = mem_to_ptr(mem); + 800f4c8: 6878 ldr r0, [r7, #4] + 800f4ca: f7ff fef3 bl 800f2b4 + 800f4ce: 4603 mov r3, r0 + 800f4d0: 82fb strh r3, [r7, #22] + nmem = ptr_to_mem(mem->next); + 800f4d2: 687b ldr r3, [r7, #4] + 800f4d4: 881b ldrh r3, [r3, #0] + 800f4d6: 4618 mov r0, r3 + 800f4d8: f7ff feda bl 800f290 + 800f4dc: 6138 str r0, [r7, #16] + pmem = ptr_to_mem(mem->prev); + 800f4de: 687b ldr r3, [r7, #4] + 800f4e0: 885b ldrh r3, [r3, #2] + 800f4e2: 4618 mov r0, r3 + 800f4e4: f7ff fed4 bl 800f290 + 800f4e8: 60f8 str r0, [r7, #12] + if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || + 800f4ea: 687b ldr r3, [r7, #4] + 800f4ec: 881b ldrh r3, [r3, #0] + 800f4ee: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f4f2: d818 bhi.n 800f526 + 800f4f4: 687b ldr r3, [r7, #4] + 800f4f6: 885b ldrh r3, [r3, #2] + 800f4f8: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f4fc: d813 bhi.n 800f526 + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 800f4fe: 687b ldr r3, [r7, #4] + 800f500: 885b ldrh r3, [r3, #2] + if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || + 800f502: 8afa ldrh r2, [r7, #22] + 800f504: 429a cmp r2, r3 + 800f506: d004 beq.n 800f512 + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 800f508: 68fb ldr r3, [r7, #12] + 800f50a: 881b ldrh r3, [r3, #0] + 800f50c: 8afa ldrh r2, [r7, #22] + 800f50e: 429a cmp r2, r3 + 800f510: d109 bne.n 800f526 + ((nmem != ram_end) && (nmem->prev != rmem_idx))) { + 800f512: 4b08 ldr r3, [pc, #32] ; (800f534 ) + 800f514: 681b ldr r3, [r3, #0] + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 800f516: 693a ldr r2, [r7, #16] + 800f518: 429a cmp r2, r3 + 800f51a: d006 beq.n 800f52a + ((nmem != ram_end) && (nmem->prev != rmem_idx))) { + 800f51c: 693b ldr r3, [r7, #16] + 800f51e: 885b ldrh r3, [r3, #2] + 800f520: 8afa ldrh r2, [r7, #22] + 800f522: 429a cmp r2, r3 + 800f524: d001 beq.n 800f52a + return 0; + 800f526: 2300 movs r3, #0 + 800f528: e000 b.n 800f52c + } + return 1; + 800f52a: 2301 movs r3, #1 +} + 800f52c: 4618 mov r0, r3 + 800f52e: 3718 adds r7, #24 + 800f530: 46bd mov sp, r7 + 800f532: bd80 pop {r7, pc} + 800f534: 20009ce0 .word 0x20009ce0 + +0800f538 : + * @param rmem is the data portion of a struct mem as returned by a previous + * call to mem_malloc() + */ +void +mem_free(void *rmem) +{ + 800f538: b580 push {r7, lr} + 800f53a: b088 sub sp, #32 + 800f53c: af00 add r7, sp, #0 + 800f53e: 6078 str r0, [r7, #4] + struct mem *mem; + LWIP_MEM_FREE_DECL_PROTECT(); + + if (rmem == NULL) { + 800f540: 687b ldr r3, [r7, #4] + 800f542: 2b00 cmp r3, #0 + 800f544: d070 beq.n 800f628 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); + return; + } + if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) { + 800f546: 687b ldr r3, [r7, #4] + 800f548: f003 0303 and.w r3, r3, #3 + 800f54c: 2b00 cmp r3, #0 + 800f54e: d00d beq.n 800f56c + LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment"); + 800f550: 4b37 ldr r3, [pc, #220] ; (800f630 ) + 800f552: f240 2273 movw r2, #627 ; 0x273 + 800f556: 4937 ldr r1, [pc, #220] ; (800f634 ) + 800f558: 4837 ldr r0, [pc, #220] ; (800f638 ) + 800f55a: f00c fd5b bl 801c014 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + 800f55e: f00c fb49 bl 801bbf4 + 800f562: 60f8 str r0, [r7, #12] + 800f564: 68f8 ldr r0, [r7, #12] + 800f566: f00c fb53 bl 801bc10 + return; + 800f56a: e05e b.n 800f62a + } + + /* Get the corresponding struct mem: */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); + 800f56c: 687b ldr r3, [r7, #4] + 800f56e: 3b08 subs r3, #8 + 800f570: 61fb str r3, [r7, #28] + + if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) { + 800f572: 4b32 ldr r3, [pc, #200] ; (800f63c ) + 800f574: 681b ldr r3, [r3, #0] + 800f576: 69fa ldr r2, [r7, #28] + 800f578: 429a cmp r2, r3 + 800f57a: d306 bcc.n 800f58a + 800f57c: 687b ldr r3, [r7, #4] + 800f57e: f103 020c add.w r2, r3, #12 + 800f582: 4b2f ldr r3, [pc, #188] ; (800f640 ) + 800f584: 681b ldr r3, [r3, #0] + 800f586: 429a cmp r2, r3 + 800f588: d90d bls.n 800f5a6 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory"); + 800f58a: 4b29 ldr r3, [pc, #164] ; (800f630 ) + 800f58c: f240 227f movw r2, #639 ; 0x27f + 800f590: 492c ldr r1, [pc, #176] ; (800f644 ) + 800f592: 4829 ldr r0, [pc, #164] ; (800f638 ) + 800f594: f00c fd3e bl 801c014 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + 800f598: f00c fb2c bl 801bbf4 + 800f59c: 6138 str r0, [r7, #16] + 800f59e: 6938 ldr r0, [r7, #16] + 800f5a0: f00c fb36 bl 801bc10 + return; + 800f5a4: e041 b.n 800f62a + } +#if MEM_OVERFLOW_CHECK + mem_overflow_check_element(mem); +#endif + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + 800f5a6: 4828 ldr r0, [pc, #160] ; (800f648 ) + 800f5a8: f00c fae2 bl 801bb70 + /* mem has to be in a used state */ + if (!mem->used) { + 800f5ac: 69fb ldr r3, [r7, #28] + 800f5ae: 791b ldrb r3, [r3, #4] + 800f5b0: 2b00 cmp r3, #0 + 800f5b2: d110 bne.n 800f5d6 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free"); + 800f5b4: 4b1e ldr r3, [pc, #120] ; (800f630 ) + 800f5b6: f44f 7223 mov.w r2, #652 ; 0x28c + 800f5ba: 4924 ldr r1, [pc, #144] ; (800f64c ) + 800f5bc: 481e ldr r0, [pc, #120] ; (800f638 ) + 800f5be: f00c fd29 bl 801c014 + LWIP_MEM_FREE_UNPROTECT(); + 800f5c2: 4821 ldr r0, [pc, #132] ; (800f648 ) + 800f5c4: f00c fae3 bl 801bb8e + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + 800f5c8: f00c fb14 bl 801bbf4 + 800f5cc: 6178 str r0, [r7, #20] + 800f5ce: 6978 ldr r0, [r7, #20] + 800f5d0: f00c fb1e bl 801bc10 + return; + 800f5d4: e029 b.n 800f62a + } + + if (!mem_link_valid(mem)) { + 800f5d6: 69f8 ldr r0, [r7, #28] + 800f5d8: f7ff ff72 bl 800f4c0 + 800f5dc: 4603 mov r3, r0 + 800f5de: 2b00 cmp r3, #0 + 800f5e0: d110 bne.n 800f604 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free"); + 800f5e2: 4b13 ldr r3, [pc, #76] ; (800f630 ) + 800f5e4: f240 2295 movw r2, #661 ; 0x295 + 800f5e8: 4919 ldr r1, [pc, #100] ; (800f650 ) + 800f5ea: 4813 ldr r0, [pc, #76] ; (800f638 ) + 800f5ec: f00c fd12 bl 801c014 + LWIP_MEM_FREE_UNPROTECT(); + 800f5f0: 4815 ldr r0, [pc, #84] ; (800f648 ) + 800f5f2: f00c facc bl 801bb8e + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + 800f5f6: f00c fafd bl 801bbf4 + 800f5fa: 61b8 str r0, [r7, #24] + 800f5fc: 69b8 ldr r0, [r7, #24] + 800f5fe: f00c fb07 bl 801bc10 + return; + 800f602: e012 b.n 800f62a + } + + /* mem is now unused. */ + mem->used = 0; + 800f604: 69fb ldr r3, [r7, #28] + 800f606: 2200 movs r2, #0 + 800f608: 711a strb r2, [r3, #4] + + if (mem < lfree) { + 800f60a: 4b12 ldr r3, [pc, #72] ; (800f654 ) + 800f60c: 681b ldr r3, [r3, #0] + 800f60e: 69fa ldr r2, [r7, #28] + 800f610: 429a cmp r2, r3 + 800f612: d202 bcs.n 800f61a + /* the newly freed struct is now the lowest */ + lfree = mem; + 800f614: 4a0f ldr r2, [pc, #60] ; (800f654 ) + 800f616: 69fb ldr r3, [r7, #28] + 800f618: 6013 str r3, [r2, #0] + } + + MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); + + /* finally, see if prev or next are free also */ + plug_holes(mem); + 800f61a: 69f8 ldr r0, [r7, #28] + 800f61c: f7ff fe5c bl 800f2d8 + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); + 800f620: 4809 ldr r0, [pc, #36] ; (800f648 ) + 800f622: f00c fab4 bl 801bb8e + 800f626: e000 b.n 800f62a + return; + 800f628: bf00 nop +} + 800f62a: 3720 adds r7, #32 + 800f62c: 46bd mov sp, r7 + 800f62e: bd80 pop {r7, pc} + 800f630: 0801ea8c .word 0x0801ea8c + 800f634: 0801eb7c .word 0x0801eb7c + 800f638: 0801ead4 .word 0x0801ead4 + 800f63c: 20009cdc .word 0x20009cdc + 800f640: 20009ce0 .word 0x20009ce0 + 800f644: 0801eba0 .word 0x0801eba0 + 800f648: 20009ce4 .word 0x20009ce4 + 800f64c: 0801ebbc .word 0x0801ebbc + 800f650: 0801ebe4 .word 0x0801ebe4 + 800f654: 20009ce8 .word 0x20009ce8 + +0800f658 : + * or NULL if newsize is > old size, in which case rmem is NOT touched + * or freed! + */ +void * +mem_trim(void *rmem, mem_size_t new_size) +{ + 800f658: b580 push {r7, lr} + 800f65a: b088 sub sp, #32 + 800f65c: af00 add r7, sp, #0 + 800f65e: 6078 str r0, [r7, #4] + 800f660: 460b mov r3, r1 + 800f662: 807b strh r3, [r7, #2] + /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ + LWIP_MEM_FREE_DECL_PROTECT(); + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size); + 800f664: 887b ldrh r3, [r7, #2] + 800f666: 3303 adds r3, #3 + 800f668: b29b uxth r3, r3 + 800f66a: f023 0303 bic.w r3, r3, #3 + 800f66e: 83fb strh r3, [r7, #30] + if (newsize < MIN_SIZE_ALIGNED) { + 800f670: 8bfb ldrh r3, [r7, #30] + 800f672: 2b0b cmp r3, #11 + 800f674: d801 bhi.n 800f67a + /* every data block must be at least MIN_SIZE_ALIGNED long */ + newsize = MIN_SIZE_ALIGNED; + 800f676: 230c movs r3, #12 + 800f678: 83fb strh r3, [r7, #30] + } +#if MEM_OVERFLOW_CHECK + newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) { + 800f67a: 8bfb ldrh r3, [r7, #30] + 800f67c: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f680: d803 bhi.n 800f68a + 800f682: 8bfa ldrh r2, [r7, #30] + 800f684: 887b ldrh r3, [r7, #2] + 800f686: 429a cmp r2, r3 + 800f688: d201 bcs.n 800f68e + return NULL; + 800f68a: 2300 movs r3, #0 + 800f68c: e0d8 b.n 800f840 + } + + LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && + 800f68e: 4b6e ldr r3, [pc, #440] ; (800f848 ) + 800f690: 681b ldr r3, [r3, #0] + 800f692: 687a ldr r2, [r7, #4] + 800f694: 429a cmp r2, r3 + 800f696: d304 bcc.n 800f6a2 + 800f698: 4b6c ldr r3, [pc, #432] ; (800f84c ) + 800f69a: 681b ldr r3, [r3, #0] + 800f69c: 687a ldr r2, [r7, #4] + 800f69e: 429a cmp r2, r3 + 800f6a0: d306 bcc.n 800f6b0 + 800f6a2: 4b6b ldr r3, [pc, #428] ; (800f850 ) + 800f6a4: f240 22d1 movw r2, #721 ; 0x2d1 + 800f6a8: 496a ldr r1, [pc, #424] ; (800f854 ) + 800f6aa: 486b ldr r0, [pc, #428] ; (800f858 ) + 800f6ac: f00c fcb2 bl 801c014 + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + 800f6b0: 4b65 ldr r3, [pc, #404] ; (800f848 ) + 800f6b2: 681b ldr r3, [r3, #0] + 800f6b4: 687a ldr r2, [r7, #4] + 800f6b6: 429a cmp r2, r3 + 800f6b8: d304 bcc.n 800f6c4 + 800f6ba: 4b64 ldr r3, [pc, #400] ; (800f84c ) + 800f6bc: 681b ldr r3, [r3, #0] + 800f6be: 687a ldr r2, [r7, #4] + 800f6c0: 429a cmp r2, r3 + 800f6c2: d307 bcc.n 800f6d4 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + 800f6c4: f00c fa96 bl 801bbf4 + 800f6c8: 60b8 str r0, [r7, #8] + 800f6ca: 68b8 ldr r0, [r7, #8] + 800f6cc: f00c faa0 bl 801bc10 + return rmem; + 800f6d0: 687b ldr r3, [r7, #4] + 800f6d2: e0b5 b.n 800f840 + } + /* Get the corresponding struct mem ... */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); + 800f6d4: 687b ldr r3, [r7, #4] + 800f6d6: 3b08 subs r3, #8 + 800f6d8: 61bb str r3, [r7, #24] +#if MEM_OVERFLOW_CHECK + mem_overflow_check_element(mem); +#endif + /* ... and its offset pointer */ + ptr = mem_to_ptr(mem); + 800f6da: 69b8 ldr r0, [r7, #24] + 800f6dc: f7ff fdea bl 800f2b4 + 800f6e0: 4603 mov r3, r0 + 800f6e2: 82fb strh r3, [r7, #22] + + size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD)); + 800f6e4: 69bb ldr r3, [r7, #24] + 800f6e6: 881a ldrh r2, [r3, #0] + 800f6e8: 8afb ldrh r3, [r7, #22] + 800f6ea: 1ad3 subs r3, r2, r3 + 800f6ec: b29b uxth r3, r3 + 800f6ee: 3b08 subs r3, #8 + 800f6f0: 82bb strh r3, [r7, #20] + LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); + 800f6f2: 8bfa ldrh r2, [r7, #30] + 800f6f4: 8abb ldrh r3, [r7, #20] + 800f6f6: 429a cmp r2, r3 + 800f6f8: d906 bls.n 800f708 + 800f6fa: 4b55 ldr r3, [pc, #340] ; (800f850 ) + 800f6fc: f44f 7239 mov.w r2, #740 ; 0x2e4 + 800f700: 4956 ldr r1, [pc, #344] ; (800f85c ) + 800f702: 4855 ldr r0, [pc, #340] ; (800f858 ) + 800f704: f00c fc86 bl 801c014 + if (newsize > size) { + 800f708: 8bfa ldrh r2, [r7, #30] + 800f70a: 8abb ldrh r3, [r7, #20] + 800f70c: 429a cmp r2, r3 + 800f70e: d901 bls.n 800f714 + /* not supported */ + return NULL; + 800f710: 2300 movs r3, #0 + 800f712: e095 b.n 800f840 + } + if (newsize == size) { + 800f714: 8bfa ldrh r2, [r7, #30] + 800f716: 8abb ldrh r3, [r7, #20] + 800f718: 429a cmp r2, r3 + 800f71a: d101 bne.n 800f720 + /* No change in size, simply return */ + return rmem; + 800f71c: 687b ldr r3, [r7, #4] + 800f71e: e08f b.n 800f840 + } + + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + 800f720: 484f ldr r0, [pc, #316] ; (800f860 ) + 800f722: f00c fa25 bl 801bb70 + + mem2 = ptr_to_mem(mem->next); + 800f726: 69bb ldr r3, [r7, #24] + 800f728: 881b ldrh r3, [r3, #0] + 800f72a: 4618 mov r0, r3 + 800f72c: f7ff fdb0 bl 800f290 + 800f730: 6138 str r0, [r7, #16] + if (mem2->used == 0) { + 800f732: 693b ldr r3, [r7, #16] + 800f734: 791b ldrb r3, [r3, #4] + 800f736: 2b00 cmp r3, #0 + 800f738: d13f bne.n 800f7ba + /* The next struct is unused, we can simply move it at little */ + mem_size_t next; + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + 800f73a: 69bb ldr r3, [r7, #24] + 800f73c: 881b ldrh r3, [r3, #0] + 800f73e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f742: d106 bne.n 800f752 + 800f744: 4b42 ldr r3, [pc, #264] ; (800f850 ) + 800f746: f240 22f5 movw r2, #757 ; 0x2f5 + 800f74a: 4946 ldr r1, [pc, #280] ; (800f864 ) + 800f74c: 4842 ldr r0, [pc, #264] ; (800f858 ) + 800f74e: f00c fc61 bl 801c014 + /* remember the old next pointer */ + next = mem2->next; + 800f752: 693b ldr r3, [r7, #16] + 800f754: 881b ldrh r3, [r3, #0] + 800f756: 81bb strh r3, [r7, #12] + /* create new struct mem which is moved directly after the shrinked mem */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + 800f758: 8afa ldrh r2, [r7, #22] + 800f75a: 8bfb ldrh r3, [r7, #30] + 800f75c: 4413 add r3, r2 + 800f75e: b29b uxth r3, r3 + 800f760: 3308 adds r3, #8 + 800f762: 81fb strh r3, [r7, #14] + if (lfree == mem2) { + 800f764: 4b40 ldr r3, [pc, #256] ; (800f868 ) + 800f766: 681b ldr r3, [r3, #0] + 800f768: 693a ldr r2, [r7, #16] + 800f76a: 429a cmp r2, r3 + 800f76c: d106 bne.n 800f77c + lfree = ptr_to_mem(ptr2); + 800f76e: 89fb ldrh r3, [r7, #14] + 800f770: 4618 mov r0, r3 + 800f772: f7ff fd8d bl 800f290 + 800f776: 4603 mov r3, r0 + 800f778: 4a3b ldr r2, [pc, #236] ; (800f868 ) + 800f77a: 6013 str r3, [r2, #0] + } + mem2 = ptr_to_mem(ptr2); + 800f77c: 89fb ldrh r3, [r7, #14] + 800f77e: 4618 mov r0, r3 + 800f780: f7ff fd86 bl 800f290 + 800f784: 6138 str r0, [r7, #16] + mem2->used = 0; + 800f786: 693b ldr r3, [r7, #16] + 800f788: 2200 movs r2, #0 + 800f78a: 711a strb r2, [r3, #4] + /* restore the next pointer */ + mem2->next = next; + 800f78c: 693b ldr r3, [r7, #16] + 800f78e: 89ba ldrh r2, [r7, #12] + 800f790: 801a strh r2, [r3, #0] + /* link it back to mem */ + mem2->prev = ptr; + 800f792: 693b ldr r3, [r7, #16] + 800f794: 8afa ldrh r2, [r7, #22] + 800f796: 805a strh r2, [r3, #2] + /* link mem to it */ + mem->next = ptr2; + 800f798: 69bb ldr r3, [r7, #24] + 800f79a: 89fa ldrh r2, [r7, #14] + 800f79c: 801a strh r2, [r3, #0] + /* last thing to restore linked list: as we have moved mem2, + * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not + * the end of the heap */ + if (mem2->next != MEM_SIZE_ALIGNED) { + 800f79e: 693b ldr r3, [r7, #16] + 800f7a0: 881b ldrh r3, [r3, #0] + 800f7a2: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f7a6: d047 beq.n 800f838 + ptr_to_mem(mem2->next)->prev = ptr2; + 800f7a8: 693b ldr r3, [r7, #16] + 800f7aa: 881b ldrh r3, [r3, #0] + 800f7ac: 4618 mov r0, r3 + 800f7ae: f7ff fd6f bl 800f290 + 800f7b2: 4602 mov r2, r0 + 800f7b4: 89fb ldrh r3, [r7, #14] + 800f7b6: 8053 strh r3, [r2, #2] + 800f7b8: e03e b.n 800f838 + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* no need to plug holes, we've already done that */ + } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { + 800f7ba: 8bfb ldrh r3, [r7, #30] + 800f7bc: f103 0214 add.w r2, r3, #20 + 800f7c0: 8abb ldrh r3, [r7, #20] + 800f7c2: 429a cmp r2, r3 + 800f7c4: d838 bhi.n 800f838 + * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem + * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + 800f7c6: 8afa ldrh r2, [r7, #22] + 800f7c8: 8bfb ldrh r3, [r7, #30] + 800f7ca: 4413 add r3, r2 + 800f7cc: b29b uxth r3, r3 + 800f7ce: 3308 adds r3, #8 + 800f7d0: 81fb strh r3, [r7, #14] + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + 800f7d2: 69bb ldr r3, [r7, #24] + 800f7d4: 881b ldrh r3, [r3, #0] + 800f7d6: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f7da: d106 bne.n 800f7ea + 800f7dc: 4b1c ldr r3, [pc, #112] ; (800f850 ) + 800f7de: f240 3216 movw r2, #790 ; 0x316 + 800f7e2: 4920 ldr r1, [pc, #128] ; (800f864 ) + 800f7e4: 481c ldr r0, [pc, #112] ; (800f858 ) + 800f7e6: f00c fc15 bl 801c014 + mem2 = ptr_to_mem(ptr2); + 800f7ea: 89fb ldrh r3, [r7, #14] + 800f7ec: 4618 mov r0, r3 + 800f7ee: f7ff fd4f bl 800f290 + 800f7f2: 6138 str r0, [r7, #16] + if (mem2 < lfree) { + 800f7f4: 4b1c ldr r3, [pc, #112] ; (800f868 ) + 800f7f6: 681b ldr r3, [r3, #0] + 800f7f8: 693a ldr r2, [r7, #16] + 800f7fa: 429a cmp r2, r3 + 800f7fc: d202 bcs.n 800f804 + lfree = mem2; + 800f7fe: 4a1a ldr r2, [pc, #104] ; (800f868 ) + 800f800: 693b ldr r3, [r7, #16] + 800f802: 6013 str r3, [r2, #0] + } + mem2->used = 0; + 800f804: 693b ldr r3, [r7, #16] + 800f806: 2200 movs r2, #0 + 800f808: 711a strb r2, [r3, #4] + mem2->next = mem->next; + 800f80a: 69bb ldr r3, [r7, #24] + 800f80c: 881a ldrh r2, [r3, #0] + 800f80e: 693b ldr r3, [r7, #16] + 800f810: 801a strh r2, [r3, #0] + mem2->prev = ptr; + 800f812: 693b ldr r3, [r7, #16] + 800f814: 8afa ldrh r2, [r7, #22] + 800f816: 805a strh r2, [r3, #2] + mem->next = ptr2; + 800f818: 69bb ldr r3, [r7, #24] + 800f81a: 89fa ldrh r2, [r7, #14] + 800f81c: 801a strh r2, [r3, #0] + if (mem2->next != MEM_SIZE_ALIGNED) { + 800f81e: 693b ldr r3, [r7, #16] + 800f820: 881b ldrh r3, [r3, #0] + 800f822: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f826: d007 beq.n 800f838 + ptr_to_mem(mem2->next)->prev = ptr2; + 800f828: 693b ldr r3, [r7, #16] + 800f82a: 881b ldrh r3, [r3, #0] + 800f82c: 4618 mov r0, r3 + 800f82e: f7ff fd2f bl 800f290 + 800f832: 4602 mov r2, r0 + 800f834: 89fb ldrh r3, [r7, #14] + 800f836: 8053 strh r3, [r2, #2] +#endif + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); + 800f838: 4809 ldr r0, [pc, #36] ; (800f860 ) + 800f83a: f00c f9a8 bl 801bb8e + return rmem; + 800f83e: 687b ldr r3, [r7, #4] +} + 800f840: 4618 mov r0, r3 + 800f842: 3720 adds r7, #32 + 800f844: 46bd mov sp, r7 + 800f846: bd80 pop {r7, pc} + 800f848: 20009cdc .word 0x20009cdc + 800f84c: 20009ce0 .word 0x20009ce0 + 800f850: 0801ea8c .word 0x0801ea8c + 800f854: 0801ec18 .word 0x0801ec18 + 800f858: 0801ead4 .word 0x0801ead4 + 800f85c: 0801ec30 .word 0x0801ec30 + 800f860: 20009ce4 .word 0x20009ce4 + 800f864: 0801ec50 .word 0x0801ec50 + 800f868: 20009ce8 .word 0x20009ce8 + +0800f86c : + * + * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). + */ +void * +mem_malloc(mem_size_t size_in) +{ + 800f86c: b580 push {r7, lr} + 800f86e: b088 sub sp, #32 + 800f870: af00 add r7, sp, #0 + 800f872: 4603 mov r3, r0 + 800f874: 80fb strh r3, [r7, #6] +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + u8_t local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_ALLOC_DECL_PROTECT(); + + if (size_in == 0) { + 800f876: 88fb ldrh r3, [r7, #6] + 800f878: 2b00 cmp r3, #0 + 800f87a: d101 bne.n 800f880 + return NULL; + 800f87c: 2300 movs r3, #0 + 800f87e: e0e2 b.n 800fa46 + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in); + 800f880: 88fb ldrh r3, [r7, #6] + 800f882: 3303 adds r3, #3 + 800f884: b29b uxth r3, r3 + 800f886: f023 0303 bic.w r3, r3, #3 + 800f88a: 83bb strh r3, [r7, #28] + if (size < MIN_SIZE_ALIGNED) { + 800f88c: 8bbb ldrh r3, [r7, #28] + 800f88e: 2b0b cmp r3, #11 + 800f890: d801 bhi.n 800f896 + /* every data block must be at least MIN_SIZE_ALIGNED long */ + size = MIN_SIZE_ALIGNED; + 800f892: 230c movs r3, #12 + 800f894: 83bb strh r3, [r7, #28] + } +#if MEM_OVERFLOW_CHECK + size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) { + 800f896: 8bbb ldrh r3, [r7, #28] + 800f898: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f89c: d803 bhi.n 800f8a6 + 800f89e: 8bba ldrh r2, [r7, #28] + 800f8a0: 88fb ldrh r3, [r7, #6] + 800f8a2: 429a cmp r2, r3 + 800f8a4: d201 bcs.n 800f8aa + return NULL; + 800f8a6: 2300 movs r3, #0 + 800f8a8: e0cd b.n 800fa46 + } + + /* protect the heap from concurrent access */ + sys_mutex_lock(&mem_mutex); + 800f8aa: 4869 ldr r0, [pc, #420] ; (800fa50 ) + 800f8ac: f00c f960 bl 801bb70 +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + /* Scan through the heap searching for a free block that is big enough, + * beginning with the lowest free block. + */ + for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; + 800f8b0: 4b68 ldr r3, [pc, #416] ; (800fa54 ) + 800f8b2: 681b ldr r3, [r3, #0] + 800f8b4: 4618 mov r0, r3 + 800f8b6: f7ff fcfd bl 800f2b4 + 800f8ba: 4603 mov r3, r0 + 800f8bc: 83fb strh r3, [r7, #30] + 800f8be: e0b7 b.n 800fa30 + ptr = ptr_to_mem(ptr)->next) { + mem = ptr_to_mem(ptr); + 800f8c0: 8bfb ldrh r3, [r7, #30] + 800f8c2: 4618 mov r0, r3 + 800f8c4: f7ff fce4 bl 800f290 + 800f8c8: 6178 str r0, [r7, #20] + local_mem_free_count = 1; + break; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + if ((!mem->used) && + 800f8ca: 697b ldr r3, [r7, #20] + 800f8cc: 791b ldrb r3, [r3, #4] + 800f8ce: 2b00 cmp r3, #0 + 800f8d0: f040 80a7 bne.w 800fa22 + (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { + 800f8d4: 697b ldr r3, [r7, #20] + 800f8d6: 881b ldrh r3, [r3, #0] + 800f8d8: 461a mov r2, r3 + 800f8da: 8bfb ldrh r3, [r7, #30] + 800f8dc: 1ad3 subs r3, r2, r3 + 800f8de: f1a3 0208 sub.w r2, r3, #8 + 800f8e2: 8bbb ldrh r3, [r7, #28] + if ((!mem->used) && + 800f8e4: 429a cmp r2, r3 + 800f8e6: f0c0 809c bcc.w 800fa22 + /* mem is not used and at least perfect fit is possible: + * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ + + if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { + 800f8ea: 697b ldr r3, [r7, #20] + 800f8ec: 881b ldrh r3, [r3, #0] + 800f8ee: 461a mov r2, r3 + 800f8f0: 8bfb ldrh r3, [r7, #30] + 800f8f2: 1ad3 subs r3, r2, r3 + 800f8f4: f1a3 0208 sub.w r2, r3, #8 + 800f8f8: 8bbb ldrh r3, [r7, #28] + 800f8fa: 3314 adds r3, #20 + 800f8fc: 429a cmp r2, r3 + 800f8fe: d333 bcc.n 800f968 + * struct mem would fit in but no data between mem2 and mem2->next + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory + */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size); + 800f900: 8bfa ldrh r2, [r7, #30] + 800f902: 8bbb ldrh r3, [r7, #28] + 800f904: 4413 add r3, r2 + 800f906: b29b uxth r3, r3 + 800f908: 3308 adds r3, #8 + 800f90a: 827b strh r3, [r7, #18] + LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED); + 800f90c: 8a7b ldrh r3, [r7, #18] + 800f90e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f912: d106 bne.n 800f922 + 800f914: 4b50 ldr r3, [pc, #320] ; (800fa58 ) + 800f916: f240 3287 movw r2, #903 ; 0x387 + 800f91a: 4950 ldr r1, [pc, #320] ; (800fa5c ) + 800f91c: 4850 ldr r0, [pc, #320] ; (800fa60 ) + 800f91e: f00c fb79 bl 801c014 + /* create mem2 struct */ + mem2 = ptr_to_mem(ptr2); + 800f922: 8a7b ldrh r3, [r7, #18] + 800f924: 4618 mov r0, r3 + 800f926: f7ff fcb3 bl 800f290 + 800f92a: 60f8 str r0, [r7, #12] + mem2->used = 0; + 800f92c: 68fb ldr r3, [r7, #12] + 800f92e: 2200 movs r2, #0 + 800f930: 711a strb r2, [r3, #4] + mem2->next = mem->next; + 800f932: 697b ldr r3, [r7, #20] + 800f934: 881a ldrh r2, [r3, #0] + 800f936: 68fb ldr r3, [r7, #12] + 800f938: 801a strh r2, [r3, #0] + mem2->prev = ptr; + 800f93a: 68fb ldr r3, [r7, #12] + 800f93c: 8bfa ldrh r2, [r7, #30] + 800f93e: 805a strh r2, [r3, #2] + /* and insert it between mem and mem->next */ + mem->next = ptr2; + 800f940: 697b ldr r3, [r7, #20] + 800f942: 8a7a ldrh r2, [r7, #18] + 800f944: 801a strh r2, [r3, #0] + mem->used = 1; + 800f946: 697b ldr r3, [r7, #20] + 800f948: 2201 movs r2, #1 + 800f94a: 711a strb r2, [r3, #4] + + if (mem2->next != MEM_SIZE_ALIGNED) { + 800f94c: 68fb ldr r3, [r7, #12] + 800f94e: 881b ldrh r3, [r3, #0] + 800f950: f5b3 6fc8 cmp.w r3, #1600 ; 0x640 + 800f954: d00b beq.n 800f96e + ptr_to_mem(mem2->next)->prev = ptr2; + 800f956: 68fb ldr r3, [r7, #12] + 800f958: 881b ldrh r3, [r3, #0] + 800f95a: 4618 mov r0, r3 + 800f95c: f7ff fc98 bl 800f290 + 800f960: 4602 mov r2, r0 + 800f962: 8a7b ldrh r3, [r7, #18] + 800f964: 8053 strh r3, [r2, #2] + 800f966: e002 b.n 800f96e + * take care of this). + * -> near fit or exact fit: do not split, no mem2 creation + * also can't move mem->next directly behind mem, since mem->next + * will always be used at this point! + */ + mem->used = 1; + 800f968: 697b ldr r3, [r7, #20] + 800f96a: 2201 movs r2, #1 + 800f96c: 711a strb r2, [r3, #4] + MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem)); + } +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +mem_malloc_adjust_lfree: +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + if (mem == lfree) { + 800f96e: 4b39 ldr r3, [pc, #228] ; (800fa54 ) + 800f970: 681b ldr r3, [r3, #0] + 800f972: 697a ldr r2, [r7, #20] + 800f974: 429a cmp r2, r3 + 800f976: d127 bne.n 800f9c8 + struct mem *cur = lfree; + 800f978: 4b36 ldr r3, [pc, #216] ; (800fa54 ) + 800f97a: 681b ldr r3, [r3, #0] + 800f97c: 61bb str r3, [r7, #24] + /* Find next free block after mem and update lowest free pointer */ + while (cur->used && cur != ram_end) { + 800f97e: e005 b.n 800f98c + /* If mem_free or mem_trim have run, we have to restart since they + could have altered our current struct mem or lfree. */ + goto mem_malloc_adjust_lfree; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + cur = ptr_to_mem(cur->next); + 800f980: 69bb ldr r3, [r7, #24] + 800f982: 881b ldrh r3, [r3, #0] + 800f984: 4618 mov r0, r3 + 800f986: f7ff fc83 bl 800f290 + 800f98a: 61b8 str r0, [r7, #24] + while (cur->used && cur != ram_end) { + 800f98c: 69bb ldr r3, [r7, #24] + 800f98e: 791b ldrb r3, [r3, #4] + 800f990: 2b00 cmp r3, #0 + 800f992: d004 beq.n 800f99e + 800f994: 4b33 ldr r3, [pc, #204] ; (800fa64 ) + 800f996: 681b ldr r3, [r3, #0] + 800f998: 69ba ldr r2, [r7, #24] + 800f99a: 429a cmp r2, r3 + 800f99c: d1f0 bne.n 800f980 + } + lfree = cur; + 800f99e: 4a2d ldr r2, [pc, #180] ; (800fa54 ) + 800f9a0: 69bb ldr r3, [r7, #24] + 800f9a2: 6013 str r3, [r2, #0] + LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); + 800f9a4: 4b2b ldr r3, [pc, #172] ; (800fa54 ) + 800f9a6: 681a ldr r2, [r3, #0] + 800f9a8: 4b2e ldr r3, [pc, #184] ; (800fa64 ) + 800f9aa: 681b ldr r3, [r3, #0] + 800f9ac: 429a cmp r2, r3 + 800f9ae: d00b beq.n 800f9c8 + 800f9b0: 4b28 ldr r3, [pc, #160] ; (800fa54 ) + 800f9b2: 681b ldr r3, [r3, #0] + 800f9b4: 791b ldrb r3, [r3, #4] + 800f9b6: 2b00 cmp r3, #0 + 800f9b8: d006 beq.n 800f9c8 + 800f9ba: 4b27 ldr r3, [pc, #156] ; (800fa58 ) + 800f9bc: f240 32b5 movw r2, #949 ; 0x3b5 + 800f9c0: 4929 ldr r1, [pc, #164] ; (800fa68 ) + 800f9c2: 4827 ldr r0, [pc, #156] ; (800fa60 ) + 800f9c4: f00c fb26 bl 801c014 + } + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + 800f9c8: 4821 ldr r0, [pc, #132] ; (800fa50 ) + 800f9ca: f00c f8e0 bl 801bb8e + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + 800f9ce: 8bba ldrh r2, [r7, #28] + 800f9d0: 697b ldr r3, [r7, #20] + 800f9d2: 4413 add r3, r2 + 800f9d4: 3308 adds r3, #8 + 800f9d6: 4a23 ldr r2, [pc, #140] ; (800fa64 ) + 800f9d8: 6812 ldr r2, [r2, #0] + 800f9da: 4293 cmp r3, r2 + 800f9dc: d906 bls.n 800f9ec + 800f9de: 4b1e ldr r3, [pc, #120] ; (800fa58 ) + 800f9e0: f240 32b9 movw r2, #953 ; 0x3b9 + 800f9e4: 4921 ldr r1, [pc, #132] ; (800fa6c ) + 800f9e6: 481e ldr r0, [pc, #120] ; (800fa60 ) + 800f9e8: f00c fb14 bl 801c014 + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + 800f9ec: 697b ldr r3, [r7, #20] + 800f9ee: f003 0303 and.w r3, r3, #3 + 800f9f2: 2b00 cmp r3, #0 + 800f9f4: d006 beq.n 800fa04 + 800f9f6: 4b18 ldr r3, [pc, #96] ; (800fa58 ) + 800f9f8: f240 32bb movw r2, #955 ; 0x3bb + 800f9fc: 491c ldr r1, [pc, #112] ; (800fa70 ) + 800f9fe: 4818 ldr r0, [pc, #96] ; (800fa60 ) + 800fa00: f00c fb08 bl 801c014 + ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + LWIP_ASSERT("mem_malloc: sanity check alignment", + 800fa04: 697b ldr r3, [r7, #20] + 800fa06: f003 0303 and.w r3, r3, #3 + 800fa0a: 2b00 cmp r3, #0 + 800fa0c: d006 beq.n 800fa1c + 800fa0e: 4b12 ldr r3, [pc, #72] ; (800fa58 ) + 800fa10: f240 32bd movw r2, #957 ; 0x3bd + 800fa14: 4917 ldr r1, [pc, #92] ; (800fa74 ) + 800fa16: 4812 ldr r0, [pc, #72] ; (800fa60 ) + 800fa18: f00c fafc bl 801c014 + +#if MEM_OVERFLOW_CHECK + mem_overflow_init_element(mem, size_in); +#endif + MEM_SANITY(); + return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; + 800fa1c: 697b ldr r3, [r7, #20] + 800fa1e: 3308 adds r3, #8 + 800fa20: e011 b.n 800fa46 + ptr = ptr_to_mem(ptr)->next) { + 800fa22: 8bfb ldrh r3, [r7, #30] + 800fa24: 4618 mov r0, r3 + 800fa26: f7ff fc33 bl 800f290 + 800fa2a: 4603 mov r3, r0 + 800fa2c: 881b ldrh r3, [r3, #0] + 800fa2e: 83fb strh r3, [r7, #30] + for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; + 800fa30: 8bfa ldrh r2, [r7, #30] + 800fa32: 8bbb ldrh r3, [r7, #28] + 800fa34: f5c3 63c8 rsb r3, r3, #1600 ; 0x640 + 800fa38: 429a cmp r2, r3 + 800fa3a: f4ff af41 bcc.w 800f8c0 + /* if we got interrupted by a mem_free, try again */ + } while (local_mem_free_count != 0); +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + MEM_STATS_INC(err); + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + 800fa3e: 4804 ldr r0, [pc, #16] ; (800fa50 ) + 800fa40: f00c f8a5 bl 801bb8e + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); + return NULL; + 800fa44: 2300 movs r3, #0 +} + 800fa46: 4618 mov r0, r3 + 800fa48: 3720 adds r7, #32 + 800fa4a: 46bd mov sp, r7 + 800fa4c: bd80 pop {r7, pc} + 800fa4e: bf00 nop + 800fa50: 20009ce4 .word 0x20009ce4 + 800fa54: 20009ce8 .word 0x20009ce8 + 800fa58: 0801ea8c .word 0x0801ea8c + 800fa5c: 0801ec50 .word 0x0801ec50 + 800fa60: 0801ead4 .word 0x0801ead4 + 800fa64: 20009ce0 .word 0x20009ce0 + 800fa68: 0801ec64 .word 0x0801ec64 + 800fa6c: 0801ec80 .word 0x0801ec80 + 800fa70: 0801ecb0 .word 0x0801ecb0 + 800fa74: 0801ece0 .word 0x0801ece0 + +0800fa78 : + * + * @param desc pool to initialize + */ +void +memp_init_pool(const struct memp_desc *desc) +{ + 800fa78: b480 push {r7} + 800fa7a: b085 sub sp, #20 + 800fa7c: af00 add r7, sp, #0 + 800fa7e: 6078 str r0, [r7, #4] + LWIP_UNUSED_ARG(desc); +#else + int i; + struct memp *memp; + + *desc->tab = NULL; + 800fa80: 687b ldr r3, [r7, #4] + 800fa82: 689b ldr r3, [r3, #8] + 800fa84: 2200 movs r2, #0 + 800fa86: 601a str r2, [r3, #0] + memp = (struct memp *)LWIP_MEM_ALIGN(desc->base); + 800fa88: 687b ldr r3, [r7, #4] + 800fa8a: 685b ldr r3, [r3, #4] + 800fa8c: 3303 adds r3, #3 + 800fa8e: f023 0303 bic.w r3, r3, #3 + 800fa92: 60bb str r3, [r7, #8] + + MEM_SANITY_REGION_AFTER_ALIGNED +#endif + )); +#endif + /* create a linked list of memp elements */ + for (i = 0; i < desc->num; ++i) { + 800fa94: 2300 movs r3, #0 + 800fa96: 60fb str r3, [r7, #12] + 800fa98: e011 b.n 800fabe + memp->next = *desc->tab; + 800fa9a: 687b ldr r3, [r7, #4] + 800fa9c: 689b ldr r3, [r3, #8] + 800fa9e: 681a ldr r2, [r3, #0] + 800faa0: 68bb ldr r3, [r7, #8] + 800faa2: 601a str r2, [r3, #0] + *desc->tab = memp; + 800faa4: 687b ldr r3, [r7, #4] + 800faa6: 689b ldr r3, [r3, #8] + 800faa8: 68ba ldr r2, [r7, #8] + 800faaa: 601a str r2, [r3, #0] +#if MEMP_OVERFLOW_CHECK + memp_overflow_init_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size + 800faac: 687b ldr r3, [r7, #4] + 800faae: 881b ldrh r3, [r3, #0] + 800fab0: 461a mov r2, r3 + 800fab2: 68bb ldr r3, [r7, #8] + 800fab4: 4413 add r3, r2 + 800fab6: 60bb str r3, [r7, #8] + for (i = 0; i < desc->num; ++i) { + 800fab8: 68fb ldr r3, [r7, #12] + 800faba: 3301 adds r3, #1 + 800fabc: 60fb str r3, [r7, #12] + 800fabe: 687b ldr r3, [r7, #4] + 800fac0: 885b ldrh r3, [r3, #2] + 800fac2: 461a mov r2, r3 + 800fac4: 68fb ldr r3, [r7, #12] + 800fac6: 4293 cmp r3, r2 + 800fac8: dbe7 blt.n 800fa9a +#endif /* !MEMP_MEM_MALLOC */ + +#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) + desc->stats->name = desc->desc; +#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */ +} + 800faca: bf00 nop + 800facc: bf00 nop + 800face: 3714 adds r7, #20 + 800fad0: 46bd mov sp, r7 + 800fad2: f85d 7b04 ldr.w r7, [sp], #4 + 800fad6: 4770 bx lr + +0800fad8 : + * + * Carves out memp_memory into linked lists for each pool-type. + */ +void +memp_init(void) +{ + 800fad8: b580 push {r7, lr} + 800fada: b082 sub sp, #8 + 800fadc: af00 add r7, sp, #0 + u16_t i; + + /* for every pool: */ + for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { + 800fade: 2300 movs r3, #0 + 800fae0: 80fb strh r3, [r7, #6] + 800fae2: e009 b.n 800faf8 + memp_init_pool(memp_pools[i]); + 800fae4: 88fb ldrh r3, [r7, #6] + 800fae6: 4a08 ldr r2, [pc, #32] ; (800fb08 ) + 800fae8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800faec: 4618 mov r0, r3 + 800faee: f7ff ffc3 bl 800fa78 + for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { + 800faf2: 88fb ldrh r3, [r7, #6] + 800faf4: 3301 adds r3, #1 + 800faf6: 80fb strh r3, [r7, #6] + 800faf8: 88fb ldrh r3, [r7, #6] + 800fafa: 2b0d cmp r3, #13 + 800fafc: d9f2 bls.n 800fae4 + +#if MEMP_OVERFLOW_CHECK >= 2 + /* check everything a first time to see if it worked */ + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ +} + 800fafe: bf00 nop + 800fb00: bf00 nop + 800fb02: 3708 adds r7, #8 + 800fb04: 46bd mov sp, r7 + 800fb06: bd80 pop {r7, pc} + 800fb08: 08023884 .word 0x08023884 + +0800fb0c : +#if !MEMP_OVERFLOW_CHECK +do_memp_malloc_pool(const struct memp_desc *desc) +#else +do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + 800fb0c: b580 push {r7, lr} + 800fb0e: b084 sub sp, #16 + 800fb10: af00 add r7, sp, #0 + 800fb12: 6078 str r0, [r7, #4] + +#if MEMP_MEM_MALLOC + memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size)); + SYS_ARCH_PROTECT(old_level); +#else /* MEMP_MEM_MALLOC */ + SYS_ARCH_PROTECT(old_level); + 800fb14: f00c f86e bl 801bbf4 + 800fb18: 60f8 str r0, [r7, #12] + + memp = *desc->tab; + 800fb1a: 687b ldr r3, [r7, #4] + 800fb1c: 689b ldr r3, [r3, #8] + 800fb1e: 681b ldr r3, [r3, #0] + 800fb20: 60bb str r3, [r7, #8] +#endif /* MEMP_MEM_MALLOC */ + + if (memp != NULL) { + 800fb22: 68bb ldr r3, [r7, #8] + 800fb24: 2b00 cmp r3, #0 + 800fb26: d015 beq.n 800fb54 +#if !MEMP_MEM_MALLOC +#if MEMP_OVERFLOW_CHECK == 1 + memp_overflow_check_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + + *desc->tab = memp->next; + 800fb28: 687b ldr r3, [r7, #4] + 800fb2a: 689b ldr r3, [r3, #8] + 800fb2c: 68ba ldr r2, [r7, #8] + 800fb2e: 6812 ldr r2, [r2, #0] + 800fb30: 601a str r2, [r3, #0] + memp->line = line; +#if MEMP_MEM_MALLOC + memp_overflow_init_element(memp, desc); +#endif /* MEMP_MEM_MALLOC */ +#endif /* MEMP_OVERFLOW_CHECK */ + LWIP_ASSERT("memp_malloc: memp properly aligned", + 800fb32: 68bb ldr r3, [r7, #8] + 800fb34: f003 0303 and.w r3, r3, #3 + 800fb38: 2b00 cmp r3, #0 + 800fb3a: d006 beq.n 800fb4a + 800fb3c: 4b09 ldr r3, [pc, #36] ; (800fb64 ) + 800fb3e: f44f 728c mov.w r2, #280 ; 0x118 + 800fb42: 4909 ldr r1, [pc, #36] ; (800fb68 ) + 800fb44: 4809 ldr r0, [pc, #36] ; (800fb6c ) + 800fb46: f00c fa65 bl 801c014 + desc->stats->used++; + if (desc->stats->used > desc->stats->max) { + desc->stats->max = desc->stats->used; + } +#endif + SYS_ARCH_UNPROTECT(old_level); + 800fb4a: 68f8 ldr r0, [r7, #12] + 800fb4c: f00c f860 bl 801bc10 + /* cast through u8_t* to get rid of alignment warnings */ + return ((u8_t *)memp + MEMP_SIZE); + 800fb50: 68bb ldr r3, [r7, #8] + 800fb52: e003 b.n 800fb5c + } else { +#if MEMP_STATS + desc->stats->err++; +#endif + SYS_ARCH_UNPROTECT(old_level); + 800fb54: 68f8 ldr r0, [r7, #12] + 800fb56: f00c f85b bl 801bc10 + LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc)); + } + + return NULL; + 800fb5a: 2300 movs r3, #0 +} + 800fb5c: 4618 mov r0, r3 + 800fb5e: 3710 adds r7, #16 + 800fb60: 46bd mov sp, r7 + 800fb62: bd80 pop {r7, pc} + 800fb64: 0801ed04 .word 0x0801ed04 + 800fb68: 0801ed34 .word 0x0801ed34 + 800fb6c: 0801ed58 .word 0x0801ed58 + +0800fb70 : +#if !MEMP_OVERFLOW_CHECK +memp_malloc_pool(const struct memp_desc *desc) +#else +memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + 800fb70: b580 push {r7, lr} + 800fb72: b082 sub sp, #8 + 800fb74: af00 add r7, sp, #0 + 800fb76: 6078 str r0, [r7, #4] + LWIP_ASSERT("invalid pool desc", desc != NULL); + 800fb78: 687b ldr r3, [r7, #4] + 800fb7a: 2b00 cmp r3, #0 + 800fb7c: d106 bne.n 800fb8c + 800fb7e: 4b0a ldr r3, [pc, #40] ; (800fba8 ) + 800fb80: f44f 729e mov.w r2, #316 ; 0x13c + 800fb84: 4909 ldr r1, [pc, #36] ; (800fbac ) + 800fb86: 480a ldr r0, [pc, #40] ; (800fbb0 ) + 800fb88: f00c fa44 bl 801c014 + if (desc == NULL) { + 800fb8c: 687b ldr r3, [r7, #4] + 800fb8e: 2b00 cmp r3, #0 + 800fb90: d101 bne.n 800fb96 + return NULL; + 800fb92: 2300 movs r3, #0 + 800fb94: e003 b.n 800fb9e + } + +#if !MEMP_OVERFLOW_CHECK + return do_memp_malloc_pool(desc); + 800fb96: 6878 ldr r0, [r7, #4] + 800fb98: f7ff ffb8 bl 800fb0c + 800fb9c: 4603 mov r3, r0 +#else + return do_memp_malloc_pool_fn(desc, file, line); +#endif +} + 800fb9e: 4618 mov r0, r3 + 800fba0: 3708 adds r7, #8 + 800fba2: 46bd mov sp, r7 + 800fba4: bd80 pop {r7, pc} + 800fba6: bf00 nop + 800fba8: 0801ed04 .word 0x0801ed04 + 800fbac: 0801ed80 .word 0x0801ed80 + 800fbb0: 0801ed58 .word 0x0801ed58 + +0800fbb4 : +#if !MEMP_OVERFLOW_CHECK +memp_malloc(memp_t type) +#else +memp_malloc_fn(memp_t type, const char *file, const int line) +#endif +{ + 800fbb4: b580 push {r7, lr} + 800fbb6: b084 sub sp, #16 + 800fbb8: af00 add r7, sp, #0 + 800fbba: 4603 mov r3, r0 + 800fbbc: 71fb strb r3, [r7, #7] + void *memp; + LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); + 800fbbe: 79fb ldrb r3, [r7, #7] + 800fbc0: 2b0d cmp r3, #13 + 800fbc2: d908 bls.n 800fbd6 + 800fbc4: 4b0a ldr r3, [pc, #40] ; (800fbf0 ) + 800fbc6: f240 1257 movw r2, #343 ; 0x157 + 800fbca: 490a ldr r1, [pc, #40] ; (800fbf4 ) + 800fbcc: 480a ldr r0, [pc, #40] ; (800fbf8 ) + 800fbce: f00c fa21 bl 801c014 + 800fbd2: 2300 movs r3, #0 + 800fbd4: e008 b.n 800fbe8 +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ + +#if !MEMP_OVERFLOW_CHECK + memp = do_memp_malloc_pool(memp_pools[type]); + 800fbd6: 79fb ldrb r3, [r7, #7] + 800fbd8: 4a08 ldr r2, [pc, #32] ; (800fbfc ) + 800fbda: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800fbde: 4618 mov r0, r3 + 800fbe0: f7ff ff94 bl 800fb0c + 800fbe4: 60f8 str r0, [r7, #12] +#else + memp = do_memp_malloc_pool_fn(memp_pools[type], file, line); +#endif + + return memp; + 800fbe6: 68fb ldr r3, [r7, #12] +} + 800fbe8: 4618 mov r0, r3 + 800fbea: 3710 adds r7, #16 + 800fbec: 46bd mov sp, r7 + 800fbee: bd80 pop {r7, pc} + 800fbf0: 0801ed04 .word 0x0801ed04 + 800fbf4: 0801ed94 .word 0x0801ed94 + 800fbf8: 0801ed58 .word 0x0801ed58 + 800fbfc: 08023884 .word 0x08023884 + +0800fc00 : + +static void +do_memp_free_pool(const struct memp_desc *desc, void *mem) +{ + 800fc00: b580 push {r7, lr} + 800fc02: b084 sub sp, #16 + 800fc04: af00 add r7, sp, #0 + 800fc06: 6078 str r0, [r7, #4] + 800fc08: 6039 str r1, [r7, #0] + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("memp_free: mem properly aligned", + 800fc0a: 683b ldr r3, [r7, #0] + 800fc0c: f003 0303 and.w r3, r3, #3 + 800fc10: 2b00 cmp r3, #0 + 800fc12: d006 beq.n 800fc22 + 800fc14: 4b0d ldr r3, [pc, #52] ; (800fc4c ) + 800fc16: f44f 72b6 mov.w r2, #364 ; 0x16c + 800fc1a: 490d ldr r1, [pc, #52] ; (800fc50 ) + 800fc1c: 480d ldr r0, [pc, #52] ; (800fc54 ) + 800fc1e: f00c f9f9 bl 801c014 + ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); + + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE); + 800fc22: 683b ldr r3, [r7, #0] + 800fc24: 60fb str r3, [r7, #12] + + SYS_ARCH_PROTECT(old_level); + 800fc26: f00b ffe5 bl 801bbf4 + 800fc2a: 60b8 str r0, [r7, #8] +#if MEMP_MEM_MALLOC + LWIP_UNUSED_ARG(desc); + SYS_ARCH_UNPROTECT(old_level); + mem_free(memp); +#else /* MEMP_MEM_MALLOC */ + memp->next = *desc->tab; + 800fc2c: 687b ldr r3, [r7, #4] + 800fc2e: 689b ldr r3, [r3, #8] + 800fc30: 681a ldr r2, [r3, #0] + 800fc32: 68fb ldr r3, [r7, #12] + 800fc34: 601a str r2, [r3, #0] + *desc->tab = memp; + 800fc36: 687b ldr r3, [r7, #4] + 800fc38: 689b ldr r3, [r3, #8] + 800fc3a: 68fa ldr r2, [r7, #12] + 800fc3c: 601a str r2, [r3, #0] + +#if MEMP_SANITY_CHECK + LWIP_ASSERT("memp sanity", memp_sanity(desc)); +#endif /* MEMP_SANITY_CHECK */ + + SYS_ARCH_UNPROTECT(old_level); + 800fc3e: 68b8 ldr r0, [r7, #8] + 800fc40: f00b ffe6 bl 801bc10 +#endif /* !MEMP_MEM_MALLOC */ +} + 800fc44: bf00 nop + 800fc46: 3710 adds r7, #16 + 800fc48: 46bd mov sp, r7 + 800fc4a: bd80 pop {r7, pc} + 800fc4c: 0801ed04 .word 0x0801ed04 + 800fc50: 0801edb4 .word 0x0801edb4 + 800fc54: 0801ed58 .word 0x0801ed58 + +0800fc58 : + * @param desc the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free_pool(const struct memp_desc *desc, void *mem) +{ + 800fc58: b580 push {r7, lr} + 800fc5a: b082 sub sp, #8 + 800fc5c: af00 add r7, sp, #0 + 800fc5e: 6078 str r0, [r7, #4] + 800fc60: 6039 str r1, [r7, #0] + LWIP_ASSERT("invalid pool desc", desc != NULL); + 800fc62: 687b ldr r3, [r7, #4] + 800fc64: 2b00 cmp r3, #0 + 800fc66: d106 bne.n 800fc76 + 800fc68: 4b0a ldr r3, [pc, #40] ; (800fc94 ) + 800fc6a: f240 1295 movw r2, #405 ; 0x195 + 800fc6e: 490a ldr r1, [pc, #40] ; (800fc98 ) + 800fc70: 480a ldr r0, [pc, #40] ; (800fc9c ) + 800fc72: f00c f9cf bl 801c014 + if ((desc == NULL) || (mem == NULL)) { + 800fc76: 687b ldr r3, [r7, #4] + 800fc78: 2b00 cmp r3, #0 + 800fc7a: d007 beq.n 800fc8c + 800fc7c: 683b ldr r3, [r7, #0] + 800fc7e: 2b00 cmp r3, #0 + 800fc80: d004 beq.n 800fc8c + return; + } + + do_memp_free_pool(desc, mem); + 800fc82: 6839 ldr r1, [r7, #0] + 800fc84: 6878 ldr r0, [r7, #4] + 800fc86: f7ff ffbb bl 800fc00 + 800fc8a: e000 b.n 800fc8e + return; + 800fc8c: bf00 nop +} + 800fc8e: 3708 adds r7, #8 + 800fc90: 46bd mov sp, r7 + 800fc92: bd80 pop {r7, pc} + 800fc94: 0801ed04 .word 0x0801ed04 + 800fc98: 0801ed80 .word 0x0801ed80 + 800fc9c: 0801ed58 .word 0x0801ed58 + +0800fca0 : + * @param type the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free(memp_t type, void *mem) +{ + 800fca0: b580 push {r7, lr} + 800fca2: b082 sub sp, #8 + 800fca4: af00 add r7, sp, #0 + 800fca6: 4603 mov r3, r0 + 800fca8: 6039 str r1, [r7, #0] + 800fcaa: 71fb strb r3, [r7, #7] +#ifdef LWIP_HOOK_MEMP_AVAILABLE + struct memp *old_first; +#endif + + LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;); + 800fcac: 79fb ldrb r3, [r7, #7] + 800fcae: 2b0d cmp r3, #13 + 800fcb0: d907 bls.n 800fcc2 + 800fcb2: 4b0c ldr r3, [pc, #48] ; (800fce4 ) + 800fcb4: f44f 72d5 mov.w r2, #426 ; 0x1aa + 800fcb8: 490b ldr r1, [pc, #44] ; (800fce8 ) + 800fcba: 480c ldr r0, [pc, #48] ; (800fcec ) + 800fcbc: f00c f9aa bl 801c014 + 800fcc0: e00c b.n 800fcdc + + if (mem == NULL) { + 800fcc2: 683b ldr r3, [r7, #0] + 800fcc4: 2b00 cmp r3, #0 + 800fcc6: d008 beq.n 800fcda + +#ifdef LWIP_HOOK_MEMP_AVAILABLE + old_first = *memp_pools[type]->tab; +#endif + + do_memp_free_pool(memp_pools[type], mem); + 800fcc8: 79fb ldrb r3, [r7, #7] + 800fcca: 4a09 ldr r2, [pc, #36] ; (800fcf0 ) + 800fccc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800fcd0: 6839 ldr r1, [r7, #0] + 800fcd2: 4618 mov r0, r3 + 800fcd4: f7ff ff94 bl 800fc00 + 800fcd8: e000 b.n 800fcdc + return; + 800fcda: bf00 nop +#ifdef LWIP_HOOK_MEMP_AVAILABLE + if (old_first == NULL) { + LWIP_HOOK_MEMP_AVAILABLE(type); + } +#endif +} + 800fcdc: 3708 adds r7, #8 + 800fcde: 46bd mov sp, r7 + 800fce0: bd80 pop {r7, pc} + 800fce2: bf00 nop + 800fce4: 0801ed04 .word 0x0801ed04 + 800fce8: 0801edd4 .word 0x0801edd4 + 800fcec: 0801ed58 .word 0x0801ed58 + 800fcf0: 08023884 .word 0x08023884 + +0800fcf4 : +} +#endif /* LWIP_HAVE_LOOPIF */ + +void +netif_init(void) +{ + 800fcf4: b480 push {r7} + 800fcf6: af00 add r7, sp, #0 + + netif_set_link_up(&loop_netif); + netif_set_up(&loop_netif); + +#endif /* LWIP_HAVE_LOOPIF */ +} + 800fcf8: bf00 nop + 800fcfa: 46bd mov sp, r7 + 800fcfc: f85d 7b04 ldr.w r7, [sp], #4 + 800fd00: 4770 bx lr + ... + +0800fd04 : +netif_add(struct netif *netif, +#if LWIP_IPV4 + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, +#endif /* LWIP_IPV4 */ + void *state, netif_init_fn init, netif_input_fn input) +{ + 800fd04: b580 push {r7, lr} + 800fd06: b086 sub sp, #24 + 800fd08: af00 add r7, sp, #0 + 800fd0a: 60f8 str r0, [r7, #12] + 800fd0c: 60b9 str r1, [r7, #8] + 800fd0e: 607a str r2, [r7, #4] + 800fd10: 603b str r3, [r7, #0] + LWIP_ASSERT("single netif already set", 0); + return NULL; + } +#endif + + LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL); + 800fd12: 68fb ldr r3, [r7, #12] + 800fd14: 2b00 cmp r3, #0 + 800fd16: d108 bne.n 800fd2a + 800fd18: 4b5b ldr r3, [pc, #364] ; (800fe88 ) + 800fd1a: f240 1227 movw r2, #295 ; 0x127 + 800fd1e: 495b ldr r1, [pc, #364] ; (800fe8c ) + 800fd20: 485b ldr r0, [pc, #364] ; (800fe90 ) + 800fd22: f00c f977 bl 801c014 + 800fd26: 2300 movs r3, #0 + 800fd28: e0a9 b.n 800fe7e + LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL); + 800fd2a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fd2c: 2b00 cmp r3, #0 + 800fd2e: d108 bne.n 800fd42 + 800fd30: 4b55 ldr r3, [pc, #340] ; (800fe88 ) + 800fd32: f44f 7294 mov.w r2, #296 ; 0x128 + 800fd36: 4957 ldr r1, [pc, #348] ; (800fe94 ) + 800fd38: 4855 ldr r0, [pc, #340] ; (800fe90 ) + 800fd3a: f00c f96b bl 801c014 + 800fd3e: 2300 movs r3, #0 + 800fd40: e09d b.n 800fe7e + +#if LWIP_IPV4 + if (ipaddr == NULL) { + 800fd42: 68bb ldr r3, [r7, #8] + 800fd44: 2b00 cmp r3, #0 + 800fd46: d101 bne.n 800fd4c + ipaddr = ip_2_ip4(IP4_ADDR_ANY); + 800fd48: 4b53 ldr r3, [pc, #332] ; (800fe98 ) + 800fd4a: 60bb str r3, [r7, #8] + } + if (netmask == NULL) { + 800fd4c: 687b ldr r3, [r7, #4] + 800fd4e: 2b00 cmp r3, #0 + 800fd50: d101 bne.n 800fd56 + netmask = ip_2_ip4(IP4_ADDR_ANY); + 800fd52: 4b51 ldr r3, [pc, #324] ; (800fe98 ) + 800fd54: 607b str r3, [r7, #4] + } + if (gw == NULL) { + 800fd56: 683b ldr r3, [r7, #0] + 800fd58: 2b00 cmp r3, #0 + 800fd5a: d101 bne.n 800fd60 + gw = ip_2_ip4(IP4_ADDR_ANY); + 800fd5c: 4b4e ldr r3, [pc, #312] ; (800fe98 ) + 800fd5e: 603b str r3, [r7, #0] + } + + /* reset new interface configuration state */ + ip_addr_set_zero_ip4(&netif->ip_addr); + 800fd60: 68fb ldr r3, [r7, #12] + 800fd62: 2200 movs r2, #0 + 800fd64: 605a str r2, [r3, #4] + ip_addr_set_zero_ip4(&netif->netmask); + 800fd66: 68fb ldr r3, [r7, #12] + 800fd68: 2200 movs r2, #0 + 800fd6a: 609a str r2, [r3, #8] + ip_addr_set_zero_ip4(&netif->gw); + 800fd6c: 68fb ldr r3, [r7, #12] + 800fd6e: 2200 movs r2, #0 + 800fd70: 60da str r2, [r3, #12] + netif->output = netif_null_output_ip4; + 800fd72: 68fb ldr r3, [r7, #12] + 800fd74: 4a49 ldr r2, [pc, #292] ; (800fe9c ) + 800fd76: 615a str r2, [r3, #20] +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + } + netif->output_ip6 = netif_null_output_ip6; +#endif /* LWIP_IPV6 */ + NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL); + netif->mtu = 0; + 800fd78: 68fb ldr r3, [r7, #12] + 800fd7a: 2200 movs r2, #0 + 800fd7c: 851a strh r2, [r3, #40] ; 0x28 + netif->flags = 0; + 800fd7e: 68fb ldr r3, [r7, #12] + 800fd80: 2200 movs r2, #0 + 800fd82: f883 2031 strb.w r2, [r3, #49] ; 0x31 +#ifdef netif_get_client_data + memset(netif->client_data, 0, sizeof(netif->client_data)); + 800fd86: 68fb ldr r3, [r7, #12] + 800fd88: 3324 adds r3, #36 ; 0x24 + 800fd8a: 2204 movs r2, #4 + 800fd8c: 2100 movs r1, #0 + 800fd8e: 4618 mov r0, r3 + 800fd90: f00c f8a3 bl 801beda +#endif /* LWIP_IPV6 */ +#if LWIP_NETIF_STATUS_CALLBACK + netif->status_callback = NULL; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + netif->link_callback = NULL; + 800fd94: 68fb ldr r3, [r7, #12] + 800fd96: 2200 movs r2, #0 + 800fd98: 61da str r2, [r3, #28] + netif->loop_first = NULL; + netif->loop_last = NULL; +#endif /* ENABLE_LOOPBACK */ + + /* remember netif specific state information data */ + netif->state = state; + 800fd9a: 68fb ldr r3, [r7, #12] + 800fd9c: 6a3a ldr r2, [r7, #32] + 800fd9e: 621a str r2, [r3, #32] + netif->num = netif_num; + 800fda0: 4b3f ldr r3, [pc, #252] ; (800fea0 ) + 800fda2: 781a ldrb r2, [r3, #0] + 800fda4: 68fb ldr r3, [r7, #12] + 800fda6: f883 2034 strb.w r2, [r3, #52] ; 0x34 + netif->input = input; + 800fdaa: 68fb ldr r3, [r7, #12] + 800fdac: 6aba ldr r2, [r7, #40] ; 0x28 + 800fdae: 611a str r2, [r3, #16] +#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS + netif->loop_cnt_current = 0; +#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ + +#if LWIP_IPV4 + netif_set_addr(netif, ipaddr, netmask, gw); + 800fdb0: 683b ldr r3, [r7, #0] + 800fdb2: 687a ldr r2, [r7, #4] + 800fdb4: 68b9 ldr r1, [r7, #8] + 800fdb6: 68f8 ldr r0, [r7, #12] + 800fdb8: f000 f914 bl 800ffe4 +#endif /* LWIP_IPV4 */ + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + 800fdbc: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fdbe: 68f8 ldr r0, [r7, #12] + 800fdc0: 4798 blx r3 + 800fdc2: 4603 mov r3, r0 + 800fdc4: 2b00 cmp r3, #0 + 800fdc6: d001 beq.n 800fdcc + return NULL; + 800fdc8: 2300 movs r3, #0 + 800fdca: e058 b.n 800fe7e + */ + { + struct netif *netif2; + int num_netifs; + do { + if (netif->num == 255) { + 800fdcc: 68fb ldr r3, [r7, #12] + 800fdce: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 800fdd2: 2bff cmp r3, #255 ; 0xff + 800fdd4: d103 bne.n 800fdde + netif->num = 0; + 800fdd6: 68fb ldr r3, [r7, #12] + 800fdd8: 2200 movs r2, #0 + 800fdda: f883 2034 strb.w r2, [r3, #52] ; 0x34 + } + num_netifs = 0; + 800fdde: 2300 movs r3, #0 + 800fde0: 613b str r3, [r7, #16] + for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { + 800fde2: 4b30 ldr r3, [pc, #192] ; (800fea4 ) + 800fde4: 681b ldr r3, [r3, #0] + 800fde6: 617b str r3, [r7, #20] + 800fde8: e02b b.n 800fe42 + LWIP_ASSERT("netif already added", netif2 != netif); + 800fdea: 697a ldr r2, [r7, #20] + 800fdec: 68fb ldr r3, [r7, #12] + 800fdee: 429a cmp r2, r3 + 800fdf0: d106 bne.n 800fe00 + 800fdf2: 4b25 ldr r3, [pc, #148] ; (800fe88 ) + 800fdf4: f240 128b movw r2, #395 ; 0x18b + 800fdf8: 492b ldr r1, [pc, #172] ; (800fea8 ) + 800fdfa: 4825 ldr r0, [pc, #148] ; (800fe90 ) + 800fdfc: f00c f90a bl 801c014 + num_netifs++; + 800fe00: 693b ldr r3, [r7, #16] + 800fe02: 3301 adds r3, #1 + 800fe04: 613b str r3, [r7, #16] + LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255); + 800fe06: 693b ldr r3, [r7, #16] + 800fe08: 2bff cmp r3, #255 ; 0xff + 800fe0a: dd06 ble.n 800fe1a + 800fe0c: 4b1e ldr r3, [pc, #120] ; (800fe88 ) + 800fe0e: f240 128d movw r2, #397 ; 0x18d + 800fe12: 4926 ldr r1, [pc, #152] ; (800feac ) + 800fe14: 481e ldr r0, [pc, #120] ; (800fe90 ) + 800fe16: f00c f8fd bl 801c014 + if (netif2->num == netif->num) { + 800fe1a: 697b ldr r3, [r7, #20] + 800fe1c: f893 2034 ldrb.w r2, [r3, #52] ; 0x34 + 800fe20: 68fb ldr r3, [r7, #12] + 800fe22: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 800fe26: 429a cmp r2, r3 + 800fe28: d108 bne.n 800fe3c + netif->num++; + 800fe2a: 68fb ldr r3, [r7, #12] + 800fe2c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 800fe30: 3301 adds r3, #1 + 800fe32: b2da uxtb r2, r3 + 800fe34: 68fb ldr r3, [r7, #12] + 800fe36: f883 2034 strb.w r2, [r3, #52] ; 0x34 + break; + 800fe3a: e005 b.n 800fe48 + for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { + 800fe3c: 697b ldr r3, [r7, #20] + 800fe3e: 681b ldr r3, [r3, #0] + 800fe40: 617b str r3, [r7, #20] + 800fe42: 697b ldr r3, [r7, #20] + 800fe44: 2b00 cmp r3, #0 + 800fe46: d1d0 bne.n 800fdea + } + } + } while (netif2 != NULL); + 800fe48: 697b ldr r3, [r7, #20] + 800fe4a: 2b00 cmp r3, #0 + 800fe4c: d1be bne.n 800fdcc + } + if (netif->num == 254) { + 800fe4e: 68fb ldr r3, [r7, #12] + 800fe50: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 800fe54: 2bfe cmp r3, #254 ; 0xfe + 800fe56: d103 bne.n 800fe60 + netif_num = 0; + 800fe58: 4b11 ldr r3, [pc, #68] ; (800fea0 ) + 800fe5a: 2200 movs r2, #0 + 800fe5c: 701a strb r2, [r3, #0] + 800fe5e: e006 b.n 800fe6e + } else { + netif_num = (u8_t)(netif->num + 1); + 800fe60: 68fb ldr r3, [r7, #12] + 800fe62: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 800fe66: 3301 adds r3, #1 + 800fe68: b2da uxtb r2, r3 + 800fe6a: 4b0d ldr r3, [pc, #52] ; (800fea0 ) + 800fe6c: 701a strb r2, [r3, #0] + } + + /* add this netif to the list */ + netif->next = netif_list; + 800fe6e: 4b0d ldr r3, [pc, #52] ; (800fea4 ) + 800fe70: 681a ldr r2, [r3, #0] + 800fe72: 68fb ldr r3, [r7, #12] + 800fe74: 601a str r2, [r3, #0] + netif_list = netif; + 800fe76: 4a0b ldr r2, [pc, #44] ; (800fea4 ) + 800fe78: 68fb ldr r3, [r7, #12] + 800fe7a: 6013 str r3, [r2, #0] +#endif /* LWIP_IPV4 */ + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + + netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL); + + return netif; + 800fe7c: 68fb ldr r3, [r7, #12] +} + 800fe7e: 4618 mov r0, r3 + 800fe80: 3718 adds r7, #24 + 800fe82: 46bd mov sp, r7 + 800fe84: bd80 pop {r7, pc} + 800fe86: bf00 nop + 800fe88: 0801edf0 .word 0x0801edf0 + 800fe8c: 0801ee84 .word 0x0801ee84 + 800fe90: 0801ee40 .word 0x0801ee40 + 800fe94: 0801eea0 .word 0x0801eea0 + 800fe98: 08023914 .word 0x08023914 + 800fe9c: 080102c7 .word 0x080102c7 + 800fea0: 2000cf2c .word 0x2000cf2c + 800fea4: 2000cf24 .word 0x2000cf24 + 800fea8: 0801eec4 .word 0x0801eec4 + 800feac: 0801eed8 .word 0x0801eed8 + +0800feb0 : + +static void +netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 800feb0: b580 push {r7, lr} + 800feb2: b082 sub sp, #8 + 800feb4: af00 add r7, sp, #0 + 800feb6: 6078 str r0, [r7, #4] + 800feb8: 6039 str r1, [r7, #0] +#if LWIP_TCP + tcp_netif_ip_addr_changed(old_addr, new_addr); + 800feba: 6839 ldr r1, [r7, #0] + 800febc: 6878 ldr r0, [r7, #4] + 800febe: f002 fd0d bl 80128dc +#endif /* LWIP_TCP */ +#if LWIP_UDP + udp_netif_ip_addr_changed(old_addr, new_addr); + 800fec2: 6839 ldr r1, [r7, #0] + 800fec4: 6878 ldr r0, [r7, #4] + 800fec6: f007 f9e7 bl 8017298 +#endif /* LWIP_UDP */ +#if LWIP_RAW + raw_netif_ip_addr_changed(old_addr, new_addr); +#endif /* LWIP_RAW */ +} + 800feca: bf00 nop + 800fecc: 3708 adds r7, #8 + 800fece: 46bd mov sp, r7 + 800fed0: bd80 pop {r7, pc} + ... + +0800fed4 : + +#if LWIP_IPV4 +static int +netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr) +{ + 800fed4: b580 push {r7, lr} + 800fed6: b086 sub sp, #24 + 800fed8: af00 add r7, sp, #0 + 800feda: 60f8 str r0, [r7, #12] + 800fedc: 60b9 str r1, [r7, #8] + 800fede: 607a str r2, [r7, #4] + LWIP_ASSERT("invalid pointer", ipaddr != NULL); + 800fee0: 68bb ldr r3, [r7, #8] + 800fee2: 2b00 cmp r3, #0 + 800fee4: d106 bne.n 800fef4 + 800fee6: 4b1d ldr r3, [pc, #116] ; (800ff5c ) + 800fee8: f240 12cb movw r2, #459 ; 0x1cb + 800feec: 491c ldr r1, [pc, #112] ; (800ff60 ) + 800feee: 481d ldr r0, [pc, #116] ; (800ff64 ) + 800fef0: f00c f890 bl 801c014 + LWIP_ASSERT("invalid pointer", old_addr != NULL); + 800fef4: 687b ldr r3, [r7, #4] + 800fef6: 2b00 cmp r3, #0 + 800fef8: d106 bne.n 800ff08 + 800fefa: 4b18 ldr r3, [pc, #96] ; (800ff5c ) + 800fefc: f44f 72e6 mov.w r2, #460 ; 0x1cc + 800ff00: 4917 ldr r1, [pc, #92] ; (800ff60 ) + 800ff02: 4818 ldr r0, [pc, #96] ; (800ff64 ) + 800ff04: f00c f886 bl 801c014 + + /* address is actually being changed? */ + if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) { + 800ff08: 68bb ldr r3, [r7, #8] + 800ff0a: 681a ldr r2, [r3, #0] + 800ff0c: 68fb ldr r3, [r7, #12] + 800ff0e: 3304 adds r3, #4 + 800ff10: 681b ldr r3, [r3, #0] + 800ff12: 429a cmp r2, r3 + 800ff14: d01c beq.n 800ff50 + ip_addr_t new_addr; + *ip_2_ip4(&new_addr) = *ipaddr; + 800ff16: 68bb ldr r3, [r7, #8] + 800ff18: 681b ldr r3, [r3, #0] + 800ff1a: 617b str r3, [r7, #20] + IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4); + + ip_addr_copy(*old_addr, *netif_ip_addr4(netif)); + 800ff1c: 68fb ldr r3, [r7, #12] + 800ff1e: 3304 adds r3, #4 + 800ff20: 681a ldr r2, [r3, #0] + 800ff22: 687b ldr r3, [r7, #4] + 800ff24: 601a str r2, [r3, #0] + + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); + netif_do_ip_addr_changed(old_addr, &new_addr); + 800ff26: f107 0314 add.w r3, r7, #20 + 800ff2a: 4619 mov r1, r3 + 800ff2c: 6878 ldr r0, [r7, #4] + 800ff2e: f7ff ffbf bl 800feb0 + + mib2_remove_ip4(netif); + mib2_remove_route_ip4(0, netif); + /* set new IP address to netif */ + ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr); + 800ff32: 68bb ldr r3, [r7, #8] + 800ff34: 2b00 cmp r3, #0 + 800ff36: d002 beq.n 800ff3e + 800ff38: 68bb ldr r3, [r7, #8] + 800ff3a: 681b ldr r3, [r3, #0] + 800ff3c: e000 b.n 800ff40 + 800ff3e: 2300 movs r3, #0 + 800ff40: 68fa ldr r2, [r7, #12] + 800ff42: 6053 str r3, [r2, #4] + IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4); + mib2_add_ip4(netif); + mib2_add_route_ip4(0, netif); + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4); + 800ff44: 2101 movs r1, #1 + 800ff46: 68f8 ldr r0, [r7, #12] + 800ff48: f000 f8d2 bl 80100f0 + + NETIF_STATUS_CALLBACK(netif); + return 1; /* address changed */ + 800ff4c: 2301 movs r3, #1 + 800ff4e: e000 b.n 800ff52 + } + return 0; /* address unchanged */ + 800ff50: 2300 movs r3, #0 +} + 800ff52: 4618 mov r0, r3 + 800ff54: 3718 adds r7, #24 + 800ff56: 46bd mov sp, r7 + 800ff58: bd80 pop {r7, pc} + 800ff5a: bf00 nop + 800ff5c: 0801edf0 .word 0x0801edf0 + 800ff60: 0801ef08 .word 0x0801ef08 + 800ff64: 0801ee40 .word 0x0801ee40 + +0800ff68 : + } +} + +static int +netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm) +{ + 800ff68: b480 push {r7} + 800ff6a: b085 sub sp, #20 + 800ff6c: af00 add r7, sp, #0 + 800ff6e: 60f8 str r0, [r7, #12] + 800ff70: 60b9 str r1, [r7, #8] + 800ff72: 607a str r2, [r7, #4] + /* address is actually being changed? */ + if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) { + 800ff74: 68bb ldr r3, [r7, #8] + 800ff76: 681a ldr r2, [r3, #0] + 800ff78: 68fb ldr r3, [r7, #12] + 800ff7a: 3308 adds r3, #8 + 800ff7c: 681b ldr r3, [r3, #0] + 800ff7e: 429a cmp r2, r3 + 800ff80: d00a beq.n 800ff98 +#else + LWIP_UNUSED_ARG(old_nm); +#endif + mib2_remove_route_ip4(0, netif); + /* set new netmask to netif */ + ip4_addr_set(ip_2_ip4(&netif->netmask), netmask); + 800ff82: 68bb ldr r3, [r7, #8] + 800ff84: 2b00 cmp r3, #0 + 800ff86: d002 beq.n 800ff8e + 800ff88: 68bb ldr r3, [r7, #8] + 800ff8a: 681b ldr r3, [r3, #0] + 800ff8c: e000 b.n 800ff90 + 800ff8e: 2300 movs r3, #0 + 800ff90: 68fa ldr r2, [r7, #12] + 800ff92: 6093 str r3, [r2, #8] + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_netmask(netif)), + ip4_addr2_16(netif_ip4_netmask(netif)), + ip4_addr3_16(netif_ip4_netmask(netif)), + ip4_addr4_16(netif_ip4_netmask(netif)))); + return 1; /* netmask changed */ + 800ff94: 2301 movs r3, #1 + 800ff96: e000 b.n 800ff9a + } + return 0; /* netmask unchanged */ + 800ff98: 2300 movs r3, #0 +} + 800ff9a: 4618 mov r0, r3 + 800ff9c: 3714 adds r7, #20 + 800ff9e: 46bd mov sp, r7 + 800ffa0: f85d 7b04 ldr.w r7, [sp], #4 + 800ffa4: 4770 bx lr + +0800ffa6 : + } +} + +static int +netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw) +{ + 800ffa6: b480 push {r7} + 800ffa8: b085 sub sp, #20 + 800ffaa: af00 add r7, sp, #0 + 800ffac: 60f8 str r0, [r7, #12] + 800ffae: 60b9 str r1, [r7, #8] + 800ffb0: 607a str r2, [r7, #4] + /* address is actually being changed? */ + if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) { + 800ffb2: 68bb ldr r3, [r7, #8] + 800ffb4: 681a ldr r2, [r3, #0] + 800ffb6: 68fb ldr r3, [r7, #12] + 800ffb8: 330c adds r3, #12 + 800ffba: 681b ldr r3, [r3, #0] + 800ffbc: 429a cmp r2, r3 + 800ffbe: d00a beq.n 800ffd6 + ip_addr_copy(*old_gw, *netif_ip_gw4(netif)); +#else + LWIP_UNUSED_ARG(old_gw); +#endif + + ip4_addr_set(ip_2_ip4(&netif->gw), gw); + 800ffc0: 68bb ldr r3, [r7, #8] + 800ffc2: 2b00 cmp r3, #0 + 800ffc4: d002 beq.n 800ffcc + 800ffc6: 68bb ldr r3, [r7, #8] + 800ffc8: 681b ldr r3, [r3, #0] + 800ffca: e000 b.n 800ffce + 800ffcc: 2300 movs r3, #0 + 800ffce: 68fa ldr r2, [r7, #12] + 800ffd0: 60d3 str r3, [r2, #12] + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_gw(netif)), + ip4_addr2_16(netif_ip4_gw(netif)), + ip4_addr3_16(netif_ip4_gw(netif)), + ip4_addr4_16(netif_ip4_gw(netif)))); + return 1; /* gateway changed */ + 800ffd2: 2301 movs r3, #1 + 800ffd4: e000 b.n 800ffd8 + } + return 0; /* gateway unchanged */ + 800ffd6: 2300 movs r3, #0 +} + 800ffd8: 4618 mov r0, r3 + 800ffda: 3714 adds r7, #20 + 800ffdc: 46bd mov sp, r7 + 800ffde: f85d 7b04 ldr.w r7, [sp], #4 + 800ffe2: 4770 bx lr + +0800ffe4 : + * @param gw the new default gateway + */ +void +netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, + const ip4_addr_t *gw) +{ + 800ffe4: b580 push {r7, lr} + 800ffe6: b088 sub sp, #32 + 800ffe8: af00 add r7, sp, #0 + 800ffea: 60f8 str r0, [r7, #12] + 800ffec: 60b9 str r1, [r7, #8] + 800ffee: 607a str r2, [r7, #4] + 800fff0: 603b str r3, [r7, #0] + ip_addr_t old_nm_val; + ip_addr_t old_gw_val; + ip_addr_t *old_nm = &old_nm_val; + ip_addr_t *old_gw = &old_gw_val; +#else + ip_addr_t *old_nm = NULL; + 800fff2: 2300 movs r3, #0 + 800fff4: 61fb str r3, [r7, #28] + ip_addr_t *old_gw = NULL; + 800fff6: 2300 movs r3, #0 + 800fff8: 61bb str r3, [r7, #24] + int remove; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + 800fffa: 68bb ldr r3, [r7, #8] + 800fffc: 2b00 cmp r3, #0 + 800fffe: d101 bne.n 8010004 + ipaddr = IP4_ADDR_ANY4; + 8010000: 4b1c ldr r3, [pc, #112] ; (8010074 ) + 8010002: 60bb str r3, [r7, #8] + } + if (netmask == NULL) { + 8010004: 687b ldr r3, [r7, #4] + 8010006: 2b00 cmp r3, #0 + 8010008: d101 bne.n 801000e + netmask = IP4_ADDR_ANY4; + 801000a: 4b1a ldr r3, [pc, #104] ; (8010074 ) + 801000c: 607b str r3, [r7, #4] + } + if (gw == NULL) { + 801000e: 683b ldr r3, [r7, #0] + 8010010: 2b00 cmp r3, #0 + 8010012: d101 bne.n 8010018 + gw = IP4_ADDR_ANY4; + 8010014: 4b17 ldr r3, [pc, #92] ; (8010074 ) + 8010016: 603b str r3, [r7, #0] + } + + remove = ip4_addr_isany(ipaddr); + 8010018: 68bb ldr r3, [r7, #8] + 801001a: 2b00 cmp r3, #0 + 801001c: d003 beq.n 8010026 + 801001e: 68bb ldr r3, [r7, #8] + 8010020: 681b ldr r3, [r3, #0] + 8010022: 2b00 cmp r3, #0 + 8010024: d101 bne.n 801002a + 8010026: 2301 movs r3, #1 + 8010028: e000 b.n 801002c + 801002a: 2300 movs r3, #0 + 801002c: 617b str r3, [r7, #20] + if (remove) { + 801002e: 697b ldr r3, [r7, #20] + 8010030: 2b00 cmp r3, #0 + 8010032: d006 beq.n 8010042 + /* when removing an address, we have to remove it *before* changing netmask/gw + to ensure that tcp RST segment can be sent correctly */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { + 8010034: f107 0310 add.w r3, r7, #16 + 8010038: 461a mov r2, r3 + 801003a: 68b9 ldr r1, [r7, #8] + 801003c: 68f8 ldr r0, [r7, #12] + 801003e: f7ff ff49 bl 800fed4 + change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address = &old_addr; +#endif + } + } + if (netif_do_set_netmask(netif, netmask, old_nm)) { + 8010042: 69fa ldr r2, [r7, #28] + 8010044: 6879 ldr r1, [r7, #4] + 8010046: 68f8 ldr r0, [r7, #12] + 8010048: f7ff ff8e bl 800ff68 +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED; + cb_args.ipv4_changed.old_netmask = old_nm; +#endif + } + if (netif_do_set_gw(netif, gw, old_gw)) { + 801004c: 69ba ldr r2, [r7, #24] + 801004e: 6839 ldr r1, [r7, #0] + 8010050: 68f8 ldr r0, [r7, #12] + 8010052: f7ff ffa8 bl 800ffa6 +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED; + cb_args.ipv4_changed.old_gw = old_gw; +#endif + } + if (!remove) { + 8010056: 697b ldr r3, [r7, #20] + 8010058: 2b00 cmp r3, #0 + 801005a: d106 bne.n 801006a + /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { + 801005c: f107 0310 add.w r3, r7, #16 + 8010060: 461a mov r2, r3 + 8010062: 68b9 ldr r1, [r7, #8] + 8010064: 68f8 ldr r0, [r7, #12] + 8010066: f7ff ff35 bl 800fed4 + if (change_reason != LWIP_NSC_NONE) { + change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED; + netif_invoke_ext_callback(netif, change_reason, &cb_args); + } +#endif +} + 801006a: bf00 nop + 801006c: 3720 adds r7, #32 + 801006e: 46bd mov sp, r7 + 8010070: bd80 pop {r7, pc} + 8010072: bf00 nop + 8010074: 08023914 .word 0x08023914 + +08010078 : + * + * @param netif the default network interface + */ +void +netif_set_default(struct netif *netif) +{ + 8010078: b480 push {r7} + 801007a: b083 sub sp, #12 + 801007c: af00 add r7, sp, #0 + 801007e: 6078 str r0, [r7, #4] + mib2_remove_route_ip4(1, netif); + } else { + /* install default route */ + mib2_add_route_ip4(1, netif); + } + netif_default = netif; + 8010080: 4a04 ldr r2, [pc, #16] ; (8010094 ) + 8010082: 687b ldr r3, [r7, #4] + 8010084: 6013 str r3, [r2, #0] + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + 8010086: bf00 nop + 8010088: 370c adds r7, #12 + 801008a: 46bd mov sp, r7 + 801008c: f85d 7b04 ldr.w r7, [sp], #4 + 8010090: 4770 bx lr + 8010092: bf00 nop + 8010094: 2000cf28 .word 0x2000cf28 + +08010098 : + * Bring an interface up, available for processing + * traffic. + */ +void +netif_set_up(struct netif *netif) +{ + 8010098: b580 push {r7, lr} + 801009a: b082 sub sp, #8 + 801009c: af00 add r7, sp, #0 + 801009e: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return); + 80100a0: 687b ldr r3, [r7, #4] + 80100a2: 2b00 cmp r3, #0 + 80100a4: d107 bne.n 80100b6 + 80100a6: 4b0f ldr r3, [pc, #60] ; (80100e4 ) + 80100a8: f44f 7254 mov.w r2, #848 ; 0x350 + 80100ac: 490e ldr r1, [pc, #56] ; (80100e8 ) + 80100ae: 480f ldr r0, [pc, #60] ; (80100ec ) + 80100b0: f00b ffb0 bl 801c014 + 80100b4: e013 b.n 80100de + + if (!(netif->flags & NETIF_FLAG_UP)) { + 80100b6: 687b ldr r3, [r7, #4] + 80100b8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 80100bc: f003 0301 and.w r3, r3, #1 + 80100c0: 2b00 cmp r3, #0 + 80100c2: d10c bne.n 80100de + netif_set_flags(netif, NETIF_FLAG_UP); + 80100c4: 687b ldr r3, [r7, #4] + 80100c6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 80100ca: f043 0301 orr.w r3, r3, #1 + 80100ce: b2da uxtb r2, r3 + 80100d0: 687b ldr r3, [r7, #4] + 80100d2: f883 2031 strb.w r2, [r3, #49] ; 0x31 + args.status_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); + 80100d6: 2103 movs r1, #3 + 80100d8: 6878 ldr r0, [r7, #4] + 80100da: f000 f809 bl 80100f0 +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + } +} + 80100de: 3708 adds r7, #8 + 80100e0: 46bd mov sp, r7 + 80100e2: bd80 pop {r7, pc} + 80100e4: 0801edf0 .word 0x0801edf0 + 80100e8: 0801ef78 .word 0x0801ef78 + 80100ec: 0801ee40 .word 0x0801ee40 + +080100f0 : + +/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change + */ +static void +netif_issue_reports(struct netif *netif, u8_t report_type) +{ + 80100f0: b580 push {r7, lr} + 80100f2: b082 sub sp, #8 + 80100f4: af00 add r7, sp, #0 + 80100f6: 6078 str r0, [r7, #4] + 80100f8: 460b mov r3, r1 + 80100fa: 70fb strb r3, [r7, #3] + LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL); + 80100fc: 687b ldr r3, [r7, #4] + 80100fe: 2b00 cmp r3, #0 + 8010100: d106 bne.n 8010110 + 8010102: 4b18 ldr r3, [pc, #96] ; (8010164 ) + 8010104: f240 326d movw r2, #877 ; 0x36d + 8010108: 4917 ldr r1, [pc, #92] ; (8010168 ) + 801010a: 4818 ldr r0, [pc, #96] ; (801016c ) + 801010c: f00b ff82 bl 801c014 + + /* Only send reports when both link and admin states are up */ + if (!(netif->flags & NETIF_FLAG_LINK_UP) || + 8010110: 687b ldr r3, [r7, #4] + 8010112: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010116: f003 0304 and.w r3, r3, #4 + 801011a: 2b00 cmp r3, #0 + 801011c: d01e beq.n 801015c + !(netif->flags & NETIF_FLAG_UP)) { + 801011e: 687b ldr r3, [r7, #4] + 8010120: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010124: f003 0301 and.w r3, r3, #1 + if (!(netif->flags & NETIF_FLAG_LINK_UP) || + 8010128: 2b00 cmp r3, #0 + 801012a: d017 beq.n 801015c + return; + } + +#if LWIP_IPV4 + if ((report_type & NETIF_REPORT_TYPE_IPV4) && + 801012c: 78fb ldrb r3, [r7, #3] + 801012e: f003 0301 and.w r3, r3, #1 + 8010132: 2b00 cmp r3, #0 + 8010134: d013 beq.n 801015e + !ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 8010136: 687b ldr r3, [r7, #4] + 8010138: 3304 adds r3, #4 + 801013a: 681b ldr r3, [r3, #0] + if ((report_type & NETIF_REPORT_TYPE_IPV4) && + 801013c: 2b00 cmp r3, #0 + 801013e: d00e beq.n 801015e +#if LWIP_ARP + /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ + if (netif->flags & (NETIF_FLAG_ETHARP)) { + 8010140: 687b ldr r3, [r7, #4] + 8010142: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010146: f003 0308 and.w r3, r3, #8 + 801014a: 2b00 cmp r3, #0 + 801014c: d007 beq.n 801015e + etharp_gratuitous(netif); + 801014e: 687b ldr r3, [r7, #4] + 8010150: 3304 adds r3, #4 + 8010152: 4619 mov r1, r3 + 8010154: 6878 ldr r0, [r7, #4] + 8010156: f009 fef1 bl 8019f3c + 801015a: e000 b.n 801015e + return; + 801015c: bf00 nop + /* send mld memberships */ + mld6_report_groups(netif); +#endif /* LWIP_IPV6_MLD */ + } +#endif /* LWIP_IPV6 */ +} + 801015e: 3708 adds r7, #8 + 8010160: 46bd mov sp, r7 + 8010162: bd80 pop {r7, pc} + 8010164: 0801edf0 .word 0x0801edf0 + 8010168: 0801ef94 .word 0x0801ef94 + 801016c: 0801ee40 .word 0x0801ee40 + +08010170 : + * @ingroup netif + * Bring an interface down, disabling any traffic processing. + */ +void +netif_set_down(struct netif *netif) +{ + 8010170: b580 push {r7, lr} + 8010172: b082 sub sp, #8 + 8010174: af00 add r7, sp, #0 + 8010176: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return); + 8010178: 687b ldr r3, [r7, #4] + 801017a: 2b00 cmp r3, #0 + 801017c: d107 bne.n 801018e + 801017e: 4b12 ldr r3, [pc, #72] ; (80101c8 ) + 8010180: f240 329b movw r2, #923 ; 0x39b + 8010184: 4911 ldr r1, [pc, #68] ; (80101cc ) + 8010186: 4812 ldr r0, [pc, #72] ; (80101d0 ) + 8010188: f00b ff44 bl 801c014 + 801018c: e019 b.n 80101c2 + + if (netif->flags & NETIF_FLAG_UP) { + 801018e: 687b ldr r3, [r7, #4] + 8010190: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010194: f003 0301 and.w r3, r3, #1 + 8010198: 2b00 cmp r3, #0 + 801019a: d012 beq.n 80101c2 + args.status_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_clear_flags(netif, NETIF_FLAG_UP); + 801019c: 687b ldr r3, [r7, #4] + 801019e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 80101a2: f023 0301 bic.w r3, r3, #1 + 80101a6: b2da uxtb r2, r3 + 80101a8: 687b ldr r3, [r7, #4] + 80101aa: f883 2031 strb.w r2, [r3, #49] ; 0x31 + MIB2_COPY_SYSUPTIME_TO(&netif->ts); + +#if LWIP_IPV4 && LWIP_ARP + if (netif->flags & NETIF_FLAG_ETHARP) { + 80101ae: 687b ldr r3, [r7, #4] + 80101b0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 80101b4: f003 0308 and.w r3, r3, #8 + 80101b8: 2b00 cmp r3, #0 + 80101ba: d002 beq.n 80101c2 + etharp_cleanup_netif(netif); + 80101bc: 6878 ldr r0, [r7, #4] + 80101be: f009 fa77 bl 80196b0 + nd6_cleanup_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_STATUS_CALLBACK(netif); + } +} + 80101c2: 3708 adds r7, #8 + 80101c4: 46bd mov sp, r7 + 80101c6: bd80 pop {r7, pc} + 80101c8: 0801edf0 .word 0x0801edf0 + 80101cc: 0801efb8 .word 0x0801efb8 + 80101d0: 0801ee40 .word 0x0801ee40 + +080101d4 : + * @ingroup netif + * Called by a driver when its link goes up + */ +void +netif_set_link_up(struct netif *netif) +{ + 80101d4: b580 push {r7, lr} + 80101d6: b082 sub sp, #8 + 80101d8: af00 add r7, sp, #0 + 80101da: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return); + 80101dc: 687b ldr r3, [r7, #4] + 80101de: 2b00 cmp r3, #0 + 80101e0: d107 bne.n 80101f2 + 80101e2: 4b15 ldr r3, [pc, #84] ; (8010238 ) + 80101e4: f44f 7278 mov.w r2, #992 ; 0x3e0 + 80101e8: 4914 ldr r1, [pc, #80] ; (801023c ) + 80101ea: 4815 ldr r0, [pc, #84] ; (8010240 ) + 80101ec: f00b ff12 bl 801c014 + 80101f0: e01e b.n 8010230 + + if (!(netif->flags & NETIF_FLAG_LINK_UP)) { + 80101f2: 687b ldr r3, [r7, #4] + 80101f4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 80101f8: f003 0304 and.w r3, r3, #4 + 80101fc: 2b00 cmp r3, #0 + 80101fe: d117 bne.n 8010230 + netif_set_flags(netif, NETIF_FLAG_LINK_UP); + 8010200: 687b ldr r3, [r7, #4] + 8010202: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010206: f043 0304 orr.w r3, r3, #4 + 801020a: b2da uxtb r2, r3 + 801020c: 687b ldr r3, [r7, #4] + 801020e: f883 2031 strb.w r2, [r3, #49] ; 0x31 + +#if LWIP_DHCP + dhcp_network_changed(netif); + 8010212: 6878 ldr r0, [r7, #4] + 8010214: f007 fc8c bl 8017b30 + +#if LWIP_AUTOIP + autoip_network_changed(netif); +#endif /* LWIP_AUTOIP */ + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); + 8010218: 2103 movs r1, #3 + 801021a: 6878 ldr r0, [r7, #4] + 801021c: f7ff ff68 bl 80100f0 +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_LINK_CALLBACK(netif); + 8010220: 687b ldr r3, [r7, #4] + 8010222: 69db ldr r3, [r3, #28] + 8010224: 2b00 cmp r3, #0 + 8010226: d003 beq.n 8010230 + 8010228: 687b ldr r3, [r7, #4] + 801022a: 69db ldr r3, [r3, #28] + 801022c: 6878 ldr r0, [r7, #4] + 801022e: 4798 blx r3 + args.link_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + 8010230: 3708 adds r7, #8 + 8010232: 46bd mov sp, r7 + 8010234: bd80 pop {r7, pc} + 8010236: bf00 nop + 8010238: 0801edf0 .word 0x0801edf0 + 801023c: 0801efd8 .word 0x0801efd8 + 8010240: 0801ee40 .word 0x0801ee40 + +08010244 : + * @ingroup netif + * Called by a driver when its link goes down + */ +void +netif_set_link_down(struct netif *netif) +{ + 8010244: b580 push {r7, lr} + 8010246: b082 sub sp, #8 + 8010248: af00 add r7, sp, #0 + 801024a: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return); + 801024c: 687b ldr r3, [r7, #4] + 801024e: 2b00 cmp r3, #0 + 8010250: d107 bne.n 8010262 + 8010252: 4b11 ldr r3, [pc, #68] ; (8010298 ) + 8010254: f240 4206 movw r2, #1030 ; 0x406 + 8010258: 4910 ldr r1, [pc, #64] ; (801029c ) + 801025a: 4811 ldr r0, [pc, #68] ; (80102a0 ) + 801025c: f00b feda bl 801c014 + 8010260: e017 b.n 8010292 + + if (netif->flags & NETIF_FLAG_LINK_UP) { + 8010262: 687b ldr r3, [r7, #4] + 8010264: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010268: f003 0304 and.w r3, r3, #4 + 801026c: 2b00 cmp r3, #0 + 801026e: d010 beq.n 8010292 + netif_clear_flags(netif, NETIF_FLAG_LINK_UP); + 8010270: 687b ldr r3, [r7, #4] + 8010272: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8010276: f023 0304 bic.w r3, r3, #4 + 801027a: b2da uxtb r2, r3 + 801027c: 687b ldr r3, [r7, #4] + 801027e: f883 2031 strb.w r2, [r3, #49] ; 0x31 + NETIF_LINK_CALLBACK(netif); + 8010282: 687b ldr r3, [r7, #4] + 8010284: 69db ldr r3, [r3, #28] + 8010286: 2b00 cmp r3, #0 + 8010288: d003 beq.n 8010292 + 801028a: 687b ldr r3, [r7, #4] + 801028c: 69db ldr r3, [r3, #28] + 801028e: 6878 ldr r0, [r7, #4] + 8010290: 4798 blx r3 + args.link_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + 8010292: 3708 adds r7, #8 + 8010294: 46bd mov sp, r7 + 8010296: bd80 pop {r7, pc} + 8010298: 0801edf0 .word 0x0801edf0 + 801029c: 0801effc .word 0x0801effc + 80102a0: 0801ee40 .word 0x0801ee40 + +080102a4 : + * @ingroup netif + * Set callback to be called when link is brought up/down + */ +void +netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) +{ + 80102a4: b480 push {r7} + 80102a6: b083 sub sp, #12 + 80102a8: af00 add r7, sp, #0 + 80102aa: 6078 str r0, [r7, #4] + 80102ac: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + + if (netif) { + 80102ae: 687b ldr r3, [r7, #4] + 80102b0: 2b00 cmp r3, #0 + 80102b2: d002 beq.n 80102ba + netif->link_callback = link_callback; + 80102b4: 687b ldr r3, [r7, #4] + 80102b6: 683a ldr r2, [r7, #0] + 80102b8: 61da str r2, [r3, #28] + } +} + 80102ba: bf00 nop + 80102bc: 370c adds r7, #12 + 80102be: 46bd mov sp, r7 + 80102c0: f85d 7b04 ldr.w r7, [sp], #4 + 80102c4: 4770 bx lr + +080102c6 : +#if LWIP_IPV4 +/** Dummy IPv4 output function for netifs not supporting IPv4 + */ +static err_t +netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) +{ + 80102c6: b480 push {r7} + 80102c8: b085 sub sp, #20 + 80102ca: af00 add r7, sp, #0 + 80102cc: 60f8 str r0, [r7, #12] + 80102ce: 60b9 str r1, [r7, #8] + 80102d0: 607a str r2, [r7, #4] + LWIP_UNUSED_ARG(netif); + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(ipaddr); + + return ERR_IF; + 80102d2: f06f 030b mvn.w r3, #11 +} + 80102d6: 4618 mov r0, r3 + 80102d8: 3714 adds r7, #20 + 80102da: 46bd mov sp, r7 + 80102dc: f85d 7b04 ldr.w r7, [sp], #4 + 80102e0: 4770 bx lr + ... + +080102e4 : +* +* @param idx index of netif to find +*/ +struct netif * +netif_get_by_index(u8_t idx) +{ + 80102e4: b480 push {r7} + 80102e6: b085 sub sp, #20 + 80102e8: af00 add r7, sp, #0 + 80102ea: 4603 mov r3, r0 + 80102ec: 71fb strb r3, [r7, #7] + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + if (idx != NETIF_NO_INDEX) { + 80102ee: 79fb ldrb r3, [r7, #7] + 80102f0: 2b00 cmp r3, #0 + 80102f2: d013 beq.n 801031c + NETIF_FOREACH(netif) { + 80102f4: 4b0d ldr r3, [pc, #52] ; (801032c ) + 80102f6: 681b ldr r3, [r3, #0] + 80102f8: 60fb str r3, [r7, #12] + 80102fa: e00c b.n 8010316 + if (idx == netif_get_index(netif)) { + 80102fc: 68fb ldr r3, [r7, #12] + 80102fe: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 8010302: 3301 adds r3, #1 + 8010304: b2db uxtb r3, r3 + 8010306: 79fa ldrb r2, [r7, #7] + 8010308: 429a cmp r2, r3 + 801030a: d101 bne.n 8010310 + return netif; /* found! */ + 801030c: 68fb ldr r3, [r7, #12] + 801030e: e006 b.n 801031e + NETIF_FOREACH(netif) { + 8010310: 68fb ldr r3, [r7, #12] + 8010312: 681b ldr r3, [r3, #0] + 8010314: 60fb str r3, [r7, #12] + 8010316: 68fb ldr r3, [r7, #12] + 8010318: 2b00 cmp r3, #0 + 801031a: d1ef bne.n 80102fc + } + } + } + + return NULL; + 801031c: 2300 movs r3, #0 +} + 801031e: 4618 mov r0, r3 + 8010320: 3714 adds r7, #20 + 8010322: 46bd mov sp, r7 + 8010324: f85d 7b04 ldr.w r7, [sp], #4 + 8010328: 4770 bx lr + 801032a: bf00 nop + 801032c: 2000cf24 .word 0x2000cf24 + +08010330 : +#if !NO_SYS +static +#endif /* !NO_SYS */ +void +pbuf_free_ooseq(void) +{ + 8010330: b580 push {r7, lr} + 8010332: b082 sub sp, #8 + 8010334: af00 add r7, sp, #0 + struct tcp_pcb *pcb; + SYS_ARCH_SET(pbuf_free_ooseq_pending, 0); + 8010336: f00b fc5d bl 801bbf4 + 801033a: 6038 str r0, [r7, #0] + 801033c: 4b0d ldr r3, [pc, #52] ; (8010374 ) + 801033e: 2200 movs r2, #0 + 8010340: 701a strb r2, [r3, #0] + 8010342: 6838 ldr r0, [r7, #0] + 8010344: f00b fc64 bl 801bc10 + + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + 8010348: 4b0b ldr r3, [pc, #44] ; (8010378 ) + 801034a: 681b ldr r3, [r3, #0] + 801034c: 607b str r3, [r7, #4] + 801034e: e00a b.n 8010366 + if (pcb->ooseq != NULL) { + 8010350: 687b ldr r3, [r7, #4] + 8010352: 6f5b ldr r3, [r3, #116] ; 0x74 + 8010354: 2b00 cmp r3, #0 + 8010356: d003 beq.n 8010360 + /** Free the ooseq pbufs of one PCB only */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); + tcp_free_ooseq(pcb); + 8010358: 6878 ldr r0, [r7, #4] + 801035a: f002 fafd bl 8012958 + return; + 801035e: e005 b.n 801036c + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + 8010360: 687b ldr r3, [r7, #4] + 8010362: 68db ldr r3, [r3, #12] + 8010364: 607b str r3, [r7, #4] + 8010366: 687b ldr r3, [r7, #4] + 8010368: 2b00 cmp r3, #0 + 801036a: d1f1 bne.n 8010350 + } + } +} + 801036c: 3708 adds r7, #8 + 801036e: 46bd mov sp, r7 + 8010370: bd80 pop {r7, pc} + 8010372: bf00 nop + 8010374: 2000cf2d .word 0x2000cf2d + 8010378: 2000cf3c .word 0x2000cf3c + +0801037c : +/** + * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq(). + */ +static void +pbuf_free_ooseq_callback(void *arg) +{ + 801037c: b580 push {r7, lr} + 801037e: b082 sub sp, #8 + 8010380: af00 add r7, sp, #0 + 8010382: 6078 str r0, [r7, #4] + LWIP_UNUSED_ARG(arg); + pbuf_free_ooseq(); + 8010384: f7ff ffd4 bl 8010330 +} + 8010388: bf00 nop + 801038a: 3708 adds r7, #8 + 801038c: 46bd mov sp, r7 + 801038e: bd80 pop {r7, pc} + +08010390 : +#endif /* !NO_SYS */ + +/** Queue a call to pbuf_free_ooseq if not already queued. */ +static void +pbuf_pool_is_empty(void) +{ + 8010390: b580 push {r7, lr} + 8010392: b082 sub sp, #8 + 8010394: af00 add r7, sp, #0 +#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL + SYS_ARCH_SET(pbuf_free_ooseq_pending, 1); +#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ + u8_t queued; + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + 8010396: f00b fc2d bl 801bbf4 + 801039a: 6078 str r0, [r7, #4] + queued = pbuf_free_ooseq_pending; + 801039c: 4b0f ldr r3, [pc, #60] ; (80103dc ) + 801039e: 781b ldrb r3, [r3, #0] + 80103a0: 70fb strb r3, [r7, #3] + pbuf_free_ooseq_pending = 1; + 80103a2: 4b0e ldr r3, [pc, #56] ; (80103dc ) + 80103a4: 2201 movs r2, #1 + 80103a6: 701a strb r2, [r3, #0] + SYS_ARCH_UNPROTECT(old_level); + 80103a8: 6878 ldr r0, [r7, #4] + 80103aa: f00b fc31 bl 801bc10 + + if (!queued) { + 80103ae: 78fb ldrb r3, [r7, #3] + 80103b0: 2b00 cmp r3, #0 + 80103b2: d10f bne.n 80103d4 + /* queue a call to pbuf_free_ooseq if not already queued */ + PBUF_POOL_FREE_OOSEQ_QUEUE_CALL(); + 80103b4: 2100 movs r1, #0 + 80103b6: 480a ldr r0, [pc, #40] ; (80103e0 ) + 80103b8: f7fd feb0 bl 800e11c + 80103bc: 4603 mov r3, r0 + 80103be: 2b00 cmp r3, #0 + 80103c0: d008 beq.n 80103d4 + 80103c2: f00b fc17 bl 801bbf4 + 80103c6: 6078 str r0, [r7, #4] + 80103c8: 4b04 ldr r3, [pc, #16] ; (80103dc ) + 80103ca: 2200 movs r2, #0 + 80103cc: 701a strb r2, [r3, #0] + 80103ce: 6878 ldr r0, [r7, #4] + 80103d0: f00b fc1e bl 801bc10 + } +#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ +} + 80103d4: bf00 nop + 80103d6: 3708 adds r7, #8 + 80103d8: 46bd mov sp, r7 + 80103da: bd80 pop {r7, pc} + 80103dc: 2000cf2d .word 0x2000cf2d + 80103e0: 0801037d .word 0x0801037d + +080103e4 : +#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ + +/* Initialize members of struct pbuf after allocation */ +static void +pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags) +{ + 80103e4: b480 push {r7} + 80103e6: b085 sub sp, #20 + 80103e8: af00 add r7, sp, #0 + 80103ea: 60f8 str r0, [r7, #12] + 80103ec: 60b9 str r1, [r7, #8] + 80103ee: 4611 mov r1, r2 + 80103f0: 461a mov r2, r3 + 80103f2: 460b mov r3, r1 + 80103f4: 80fb strh r3, [r7, #6] + 80103f6: 4613 mov r3, r2 + 80103f8: 80bb strh r3, [r7, #4] + p->next = NULL; + 80103fa: 68fb ldr r3, [r7, #12] + 80103fc: 2200 movs r2, #0 + 80103fe: 601a str r2, [r3, #0] + p->payload = payload; + 8010400: 68fb ldr r3, [r7, #12] + 8010402: 68ba ldr r2, [r7, #8] + 8010404: 605a str r2, [r3, #4] + p->tot_len = tot_len; + 8010406: 68fb ldr r3, [r7, #12] + 8010408: 88fa ldrh r2, [r7, #6] + 801040a: 811a strh r2, [r3, #8] + p->len = len; + 801040c: 68fb ldr r3, [r7, #12] + 801040e: 88ba ldrh r2, [r7, #4] + 8010410: 815a strh r2, [r3, #10] + p->type_internal = (u8_t)type; + 8010412: 8b3b ldrh r3, [r7, #24] + 8010414: b2da uxtb r2, r3 + 8010416: 68fb ldr r3, [r7, #12] + 8010418: 731a strb r2, [r3, #12] + p->flags = flags; + 801041a: 68fb ldr r3, [r7, #12] + 801041c: 7f3a ldrb r2, [r7, #28] + 801041e: 735a strb r2, [r3, #13] + p->ref = 1; + 8010420: 68fb ldr r3, [r7, #12] + 8010422: 2201 movs r2, #1 + 8010424: 739a strb r2, [r3, #14] + p->if_idx = NETIF_NO_INDEX; + 8010426: 68fb ldr r3, [r7, #12] + 8010428: 2200 movs r2, #0 + 801042a: 73da strb r2, [r3, #15] +} + 801042c: bf00 nop + 801042e: 3714 adds r7, #20 + 8010430: 46bd mov sp, r7 + 8010432: f85d 7b04 ldr.w r7, [sp], #4 + 8010436: 4770 bx lr + +08010438 : + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) +{ + 8010438: b580 push {r7, lr} + 801043a: b08c sub sp, #48 ; 0x30 + 801043c: af02 add r7, sp, #8 + 801043e: 4603 mov r3, r0 + 8010440: 71fb strb r3, [r7, #7] + 8010442: 460b mov r3, r1 + 8010444: 80bb strh r3, [r7, #4] + 8010446: 4613 mov r3, r2 + 8010448: 807b strh r3, [r7, #2] + struct pbuf *p; + u16_t offset = (u16_t)layer; + 801044a: 79fb ldrb r3, [r7, #7] + 801044c: 847b strh r3, [r7, #34] ; 0x22 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); + + switch (type) { + 801044e: 887b ldrh r3, [r7, #2] + 8010450: f5b3 7f20 cmp.w r3, #640 ; 0x280 + 8010454: d07f beq.n 8010556 + 8010456: f5b3 7f20 cmp.w r3, #640 ; 0x280 + 801045a: f300 80c8 bgt.w 80105ee + 801045e: f5b3 7fc1 cmp.w r3, #386 ; 0x182 + 8010462: d010 beq.n 8010486 + 8010464: f5b3 7fc1 cmp.w r3, #386 ; 0x182 + 8010468: f300 80c1 bgt.w 80105ee + 801046c: 2b01 cmp r3, #1 + 801046e: d002 beq.n 8010476 + 8010470: 2b41 cmp r3, #65 ; 0x41 + 8010472: f040 80bc bne.w 80105ee + case PBUF_REF: /* fall through */ + case PBUF_ROM: + p = pbuf_alloc_reference(NULL, length, type); + 8010476: 887a ldrh r2, [r7, #2] + 8010478: 88bb ldrh r3, [r7, #4] + 801047a: 4619 mov r1, r3 + 801047c: 2000 movs r0, #0 + 801047e: f000 f8d1 bl 8010624 + 8010482: 6278 str r0, [r7, #36] ; 0x24 + break; + 8010484: e0bd b.n 8010602 + case PBUF_POOL: { + struct pbuf *q, *last; + u16_t rem_len; /* remaining length */ + p = NULL; + 8010486: 2300 movs r3, #0 + 8010488: 627b str r3, [r7, #36] ; 0x24 + last = NULL; + 801048a: 2300 movs r3, #0 + 801048c: 61fb str r3, [r7, #28] + rem_len = length; + 801048e: 88bb ldrh r3, [r7, #4] + 8010490: 837b strh r3, [r7, #26] + do { + u16_t qlen; + q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); + 8010492: 200d movs r0, #13 + 8010494: f7ff fb8e bl 800fbb4 + 8010498: 6138 str r0, [r7, #16] + if (q == NULL) { + 801049a: 693b ldr r3, [r7, #16] + 801049c: 2b00 cmp r3, #0 + 801049e: d109 bne.n 80104b4 + PBUF_POOL_IS_EMPTY(); + 80104a0: f7ff ff76 bl 8010390 + /* free chain so far allocated */ + if (p) { + 80104a4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80104a6: 2b00 cmp r3, #0 + 80104a8: d002 beq.n 80104b0 + pbuf_free(p); + 80104aa: 6a78 ldr r0, [r7, #36] ; 0x24 + 80104ac: f000 faa8 bl 8010a00 + } + /* bail out unsuccessfully */ + return NULL; + 80104b0: 2300 movs r3, #0 + 80104b2: e0a7 b.n 8010604 + } + qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset))); + 80104b4: 8c7b ldrh r3, [r7, #34] ; 0x22 + 80104b6: 3303 adds r3, #3 + 80104b8: b29b uxth r3, r3 + 80104ba: f023 0303 bic.w r3, r3, #3 + 80104be: b29b uxth r3, r3 + 80104c0: f5c3 7314 rsb r3, r3, #592 ; 0x250 + 80104c4: b29b uxth r3, r3 + 80104c6: 8b7a ldrh r2, [r7, #26] + 80104c8: 4293 cmp r3, r2 + 80104ca: bf28 it cs + 80104cc: 4613 movcs r3, r2 + 80104ce: 81fb strh r3, [r7, #14] + pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)), + 80104d0: 8c7b ldrh r3, [r7, #34] ; 0x22 + 80104d2: 3310 adds r3, #16 + 80104d4: 693a ldr r2, [r7, #16] + 80104d6: 4413 add r3, r2 + 80104d8: 3303 adds r3, #3 + 80104da: f023 0303 bic.w r3, r3, #3 + 80104de: 4618 mov r0, r3 + 80104e0: 89f9 ldrh r1, [r7, #14] + 80104e2: 8b7a ldrh r2, [r7, #26] + 80104e4: 2300 movs r3, #0 + 80104e6: 9301 str r3, [sp, #4] + 80104e8: 887b ldrh r3, [r7, #2] + 80104ea: 9300 str r3, [sp, #0] + 80104ec: 460b mov r3, r1 + 80104ee: 4601 mov r1, r0 + 80104f0: 6938 ldr r0, [r7, #16] + 80104f2: f7ff ff77 bl 80103e4 + rem_len, qlen, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + 80104f6: 693b ldr r3, [r7, #16] + 80104f8: 685b ldr r3, [r3, #4] + 80104fa: f003 0303 and.w r3, r3, #3 + 80104fe: 2b00 cmp r3, #0 + 8010500: d006 beq.n 8010510 + 8010502: 4b42 ldr r3, [pc, #264] ; (801060c ) + 8010504: f44f 7280 mov.w r2, #256 ; 0x100 + 8010508: 4941 ldr r1, [pc, #260] ; (8010610 ) + 801050a: 4842 ldr r0, [pc, #264] ; (8010614 ) + 801050c: f00b fd82 bl 801c014 + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", + 8010510: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8010512: 3303 adds r3, #3 + 8010514: f023 0303 bic.w r3, r3, #3 + 8010518: f5b3 7f14 cmp.w r3, #592 ; 0x250 + 801051c: d106 bne.n 801052c + 801051e: 4b3b ldr r3, [pc, #236] ; (801060c ) + 8010520: f44f 7281 mov.w r2, #258 ; 0x102 + 8010524: 493c ldr r1, [pc, #240] ; (8010618 ) + 8010526: 483b ldr r0, [pc, #236] ; (8010614 ) + 8010528: f00b fd74 bl 801c014 + (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); + if (p == NULL) { + 801052c: 6a7b ldr r3, [r7, #36] ; 0x24 + 801052e: 2b00 cmp r3, #0 + 8010530: d102 bne.n 8010538 + /* allocated head of pbuf chain (into p) */ + p = q; + 8010532: 693b ldr r3, [r7, #16] + 8010534: 627b str r3, [r7, #36] ; 0x24 + 8010536: e002 b.n 801053e + } else { + /* make previous pbuf point to this pbuf */ + last->next = q; + 8010538: 69fb ldr r3, [r7, #28] + 801053a: 693a ldr r2, [r7, #16] + 801053c: 601a str r2, [r3, #0] + } + last = q; + 801053e: 693b ldr r3, [r7, #16] + 8010540: 61fb str r3, [r7, #28] + rem_len = (u16_t)(rem_len - qlen); + 8010542: 8b7a ldrh r2, [r7, #26] + 8010544: 89fb ldrh r3, [r7, #14] + 8010546: 1ad3 subs r3, r2, r3 + 8010548: 837b strh r3, [r7, #26] + offset = 0; + 801054a: 2300 movs r3, #0 + 801054c: 847b strh r3, [r7, #34] ; 0x22 + } while (rem_len > 0); + 801054e: 8b7b ldrh r3, [r7, #26] + 8010550: 2b00 cmp r3, #0 + 8010552: d19e bne.n 8010492 + break; + 8010554: e055 b.n 8010602 + } + case PBUF_RAM: { + u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length)); + 8010556: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8010558: 3303 adds r3, #3 + 801055a: b29b uxth r3, r3 + 801055c: f023 0303 bic.w r3, r3, #3 + 8010560: b29a uxth r2, r3 + 8010562: 88bb ldrh r3, [r7, #4] + 8010564: 3303 adds r3, #3 + 8010566: b29b uxth r3, r3 + 8010568: f023 0303 bic.w r3, r3, #3 + 801056c: b29b uxth r3, r3 + 801056e: 4413 add r3, r2 + 8010570: 833b strh r3, [r7, #24] + mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len); + 8010572: 8b3b ldrh r3, [r7, #24] + 8010574: 3310 adds r3, #16 + 8010576: 82fb strh r3, [r7, #22] + + /* bug #50040: Check for integer overflow when calculating alloc_len */ + if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || + 8010578: 8b3a ldrh r2, [r7, #24] + 801057a: 88bb ldrh r3, [r7, #4] + 801057c: 3303 adds r3, #3 + 801057e: f023 0303 bic.w r3, r3, #3 + 8010582: 429a cmp r2, r3 + 8010584: d306 bcc.n 8010594 + (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) { + 8010586: 8afa ldrh r2, [r7, #22] + 8010588: 88bb ldrh r3, [r7, #4] + 801058a: 3303 adds r3, #3 + 801058c: f023 0303 bic.w r3, r3, #3 + if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || + 8010590: 429a cmp r2, r3 + 8010592: d201 bcs.n 8010598 + return NULL; + 8010594: 2300 movs r3, #0 + 8010596: e035 b.n 8010604 + } + + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = (struct pbuf *)mem_malloc(alloc_len); + 8010598: 8afb ldrh r3, [r7, #22] + 801059a: 4618 mov r0, r3 + 801059c: f7ff f966 bl 800f86c + 80105a0: 6278 str r0, [r7, #36] ; 0x24 + if (p == NULL) { + 80105a2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80105a4: 2b00 cmp r3, #0 + 80105a6: d101 bne.n 80105ac + return NULL; + 80105a8: 2300 movs r3, #0 + 80105aa: e02b b.n 8010604 + } + pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)), + 80105ac: 8c7b ldrh r3, [r7, #34] ; 0x22 + 80105ae: 3310 adds r3, #16 + 80105b0: 6a7a ldr r2, [r7, #36] ; 0x24 + 80105b2: 4413 add r3, r2 + 80105b4: 3303 adds r3, #3 + 80105b6: f023 0303 bic.w r3, r3, #3 + 80105ba: 4618 mov r0, r3 + 80105bc: 88b9 ldrh r1, [r7, #4] + 80105be: 88ba ldrh r2, [r7, #4] + 80105c0: 2300 movs r3, #0 + 80105c2: 9301 str r3, [sp, #4] + 80105c4: 887b ldrh r3, [r7, #2] + 80105c6: 9300 str r3, [sp, #0] + 80105c8: 460b mov r3, r1 + 80105ca: 4601 mov r1, r0 + 80105cc: 6a78 ldr r0, [r7, #36] ; 0x24 + 80105ce: f7ff ff09 bl 80103e4 + length, length, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + 80105d2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80105d4: 685b ldr r3, [r3, #4] + 80105d6: f003 0303 and.w r3, r3, #3 + 80105da: 2b00 cmp r3, #0 + 80105dc: d010 beq.n 8010600 + 80105de: 4b0b ldr r3, [pc, #44] ; (801060c ) + 80105e0: f44f 7291 mov.w r2, #290 ; 0x122 + 80105e4: 490d ldr r1, [pc, #52] ; (801061c ) + 80105e6: 480b ldr r0, [pc, #44] ; (8010614 ) + 80105e8: f00b fd14 bl 801c014 + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + 80105ec: e008 b.n 8010600 + } + default: + LWIP_ASSERT("pbuf_alloc: erroneous type", 0); + 80105ee: 4b07 ldr r3, [pc, #28] ; (801060c ) + 80105f0: f240 1227 movw r2, #295 ; 0x127 + 80105f4: 490a ldr r1, [pc, #40] ; (8010620 ) + 80105f6: 4807 ldr r0, [pc, #28] ; (8010614 ) + 80105f8: f00b fd0c bl 801c014 + return NULL; + 80105fc: 2300 movs r3, #0 + 80105fe: e001 b.n 8010604 + break; + 8010600: bf00 nop + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; + 8010602: 6a7b ldr r3, [r7, #36] ; 0x24 +} + 8010604: 4618 mov r0, r3 + 8010606: 3728 adds r7, #40 ; 0x28 + 8010608: 46bd mov sp, r7 + 801060a: bd80 pop {r7, pc} + 801060c: 0801f020 .word 0x0801f020 + 8010610: 0801f050 .word 0x0801f050 + 8010614: 0801f080 .word 0x0801f080 + 8010618: 0801f0a8 .word 0x0801f0a8 + 801061c: 0801f0dc .word 0x0801f0dc + 8010620: 0801f108 .word 0x0801f108 + +08010624 : + * + * @return the allocated pbuf. + */ +struct pbuf * +pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type) +{ + 8010624: b580 push {r7, lr} + 8010626: b086 sub sp, #24 + 8010628: af02 add r7, sp, #8 + 801062a: 6078 str r0, [r7, #4] + 801062c: 460b mov r3, r1 + 801062e: 807b strh r3, [r7, #2] + 8010630: 4613 mov r3, r2 + 8010632: 803b strh r3, [r7, #0] + struct pbuf *p; + LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM)); + 8010634: 883b ldrh r3, [r7, #0] + 8010636: 2b41 cmp r3, #65 ; 0x41 + 8010638: d009 beq.n 801064e + 801063a: 883b ldrh r3, [r7, #0] + 801063c: 2b01 cmp r3, #1 + 801063e: d006 beq.n 801064e + 8010640: 4b0f ldr r3, [pc, #60] ; (8010680 ) + 8010642: f44f 72a5 mov.w r2, #330 ; 0x14a + 8010646: 490f ldr r1, [pc, #60] ; (8010684 ) + 8010648: 480f ldr r0, [pc, #60] ; (8010688 ) + 801064a: f00b fce3 bl 801c014 + /* only allocate memory for the pbuf structure */ + p = (struct pbuf *)memp_malloc(MEMP_PBUF); + 801064e: 200c movs r0, #12 + 8010650: f7ff fab0 bl 800fbb4 + 8010654: 60f8 str r0, [r7, #12] + if (p == NULL) { + 8010656: 68fb ldr r3, [r7, #12] + 8010658: 2b00 cmp r3, #0 + 801065a: d101 bne.n 8010660 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n", + (type == PBUF_ROM) ? "ROM" : "REF")); + return NULL; + 801065c: 2300 movs r3, #0 + 801065e: e00b b.n 8010678 + } + pbuf_init_alloced_pbuf(p, payload, length, length, type, 0); + 8010660: 8879 ldrh r1, [r7, #2] + 8010662: 887a ldrh r2, [r7, #2] + 8010664: 2300 movs r3, #0 + 8010666: 9301 str r3, [sp, #4] + 8010668: 883b ldrh r3, [r7, #0] + 801066a: 9300 str r3, [sp, #0] + 801066c: 460b mov r3, r1 + 801066e: 6879 ldr r1, [r7, #4] + 8010670: 68f8 ldr r0, [r7, #12] + 8010672: f7ff feb7 bl 80103e4 + return p; + 8010676: 68fb ldr r3, [r7, #12] +} + 8010678: 4618 mov r0, r3 + 801067a: 3710 adds r7, #16 + 801067c: 46bd mov sp, r7 + 801067e: bd80 pop {r7, pc} + 8010680: 0801f020 .word 0x0801f020 + 8010684: 0801f124 .word 0x0801f124 + 8010688: 0801f080 .word 0x0801f080 + +0801068c : + * big enough to hold 'length' plus the header size + */ +struct pbuf * +pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, + void *payload_mem, u16_t payload_mem_len) +{ + 801068c: b580 push {r7, lr} + 801068e: b088 sub sp, #32 + 8010690: af02 add r7, sp, #8 + 8010692: 607b str r3, [r7, #4] + 8010694: 4603 mov r3, r0 + 8010696: 73fb strb r3, [r7, #15] + 8010698: 460b mov r3, r1 + 801069a: 81bb strh r3, [r7, #12] + 801069c: 4613 mov r3, r2 + 801069e: 817b strh r3, [r7, #10] + u16_t offset = (u16_t)l; + 80106a0: 7bfb ldrb r3, [r7, #15] + 80106a2: 827b strh r3, [r7, #18] + void *payload; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); + + if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) { + 80106a4: 8a7b ldrh r3, [r7, #18] + 80106a6: 3303 adds r3, #3 + 80106a8: f023 0203 bic.w r2, r3, #3 + 80106ac: 89bb ldrh r3, [r7, #12] + 80106ae: 441a add r2, r3 + 80106b0: 8cbb ldrh r3, [r7, #36] ; 0x24 + 80106b2: 429a cmp r2, r3 + 80106b4: d901 bls.n 80106ba + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); + return NULL; + 80106b6: 2300 movs r3, #0 + 80106b8: e018 b.n 80106ec + } + + if (payload_mem != NULL) { + 80106ba: 6a3b ldr r3, [r7, #32] + 80106bc: 2b00 cmp r3, #0 + 80106be: d007 beq.n 80106d0 + payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset); + 80106c0: 8a7b ldrh r3, [r7, #18] + 80106c2: 3303 adds r3, #3 + 80106c4: f023 0303 bic.w r3, r3, #3 + 80106c8: 6a3a ldr r2, [r7, #32] + 80106ca: 4413 add r3, r2 + 80106cc: 617b str r3, [r7, #20] + 80106ce: e001 b.n 80106d4 + } else { + payload = NULL; + 80106d0: 2300 movs r3, #0 + 80106d2: 617b str r3, [r7, #20] + } + pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM); + 80106d4: 6878 ldr r0, [r7, #4] + 80106d6: 89b9 ldrh r1, [r7, #12] + 80106d8: 89ba ldrh r2, [r7, #12] + 80106da: 2302 movs r3, #2 + 80106dc: 9301 str r3, [sp, #4] + 80106de: 897b ldrh r3, [r7, #10] + 80106e0: 9300 str r3, [sp, #0] + 80106e2: 460b mov r3, r1 + 80106e4: 6979 ldr r1, [r7, #20] + 80106e6: f7ff fe7d bl 80103e4 + return &p->pbuf; + 80106ea: 687b ldr r3, [r7, #4] +} + 80106ec: 4618 mov r0, r3 + 80106ee: 3718 adds r7, #24 + 80106f0: 46bd mov sp, r7 + 80106f2: bd80 pop {r7, pc} + +080106f4 : + * + * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + 80106f4: b580 push {r7, lr} + 80106f6: b084 sub sp, #16 + 80106f8: af00 add r7, sp, #0 + 80106fa: 6078 str r0, [r7, #4] + 80106fc: 460b mov r3, r1 + 80106fe: 807b strh r3, [r7, #2] + struct pbuf *q; + u16_t rem_len; /* remaining length */ + u16_t shrink; + + LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); + 8010700: 687b ldr r3, [r7, #4] + 8010702: 2b00 cmp r3, #0 + 8010704: d106 bne.n 8010714 + 8010706: 4b3a ldr r3, [pc, #232] ; (80107f0 ) + 8010708: f44f 72cc mov.w r2, #408 ; 0x198 + 801070c: 4939 ldr r1, [pc, #228] ; (80107f4 ) + 801070e: 483a ldr r0, [pc, #232] ; (80107f8 ) + 8010710: f00b fc80 bl 801c014 + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + 8010714: 687b ldr r3, [r7, #4] + 8010716: 891b ldrh r3, [r3, #8] + 8010718: 887a ldrh r2, [r7, #2] + 801071a: 429a cmp r2, r3 + 801071c: d263 bcs.n 80107e6 + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + shrink = (u16_t)(p->tot_len - new_len); + 801071e: 687b ldr r3, [r7, #4] + 8010720: 891a ldrh r2, [r3, #8] + 8010722: 887b ldrh r3, [r7, #2] + 8010724: 1ad3 subs r3, r2, r3 + 8010726: 813b strh r3, [r7, #8] + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + 8010728: 887b ldrh r3, [r7, #2] + 801072a: 817b strh r3, [r7, #10] + q = p; + 801072c: 687b ldr r3, [r7, #4] + 801072e: 60fb str r3, [r7, #12] + /* should this pbuf be kept? */ + while (rem_len > q->len) { + 8010730: e018 b.n 8010764 + /* decrease remaining length by pbuf length */ + rem_len = (u16_t)(rem_len - q->len); + 8010732: 68fb ldr r3, [r7, #12] + 8010734: 895b ldrh r3, [r3, #10] + 8010736: 897a ldrh r2, [r7, #10] + 8010738: 1ad3 subs r3, r2, r3 + 801073a: 817b strh r3, [r7, #10] + /* decrease total length indicator */ + q->tot_len = (u16_t)(q->tot_len - shrink); + 801073c: 68fb ldr r3, [r7, #12] + 801073e: 891a ldrh r2, [r3, #8] + 8010740: 893b ldrh r3, [r7, #8] + 8010742: 1ad3 subs r3, r2, r3 + 8010744: b29a uxth r2, r3 + 8010746: 68fb ldr r3, [r7, #12] + 8010748: 811a strh r2, [r3, #8] + /* proceed to next pbuf in chain */ + q = q->next; + 801074a: 68fb ldr r3, [r7, #12] + 801074c: 681b ldr r3, [r3, #0] + 801074e: 60fb str r3, [r7, #12] + LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); + 8010750: 68fb ldr r3, [r7, #12] + 8010752: 2b00 cmp r3, #0 + 8010754: d106 bne.n 8010764 + 8010756: 4b26 ldr r3, [pc, #152] ; (80107f0 ) + 8010758: f240 12af movw r2, #431 ; 0x1af + 801075c: 4927 ldr r1, [pc, #156] ; (80107fc ) + 801075e: 4826 ldr r0, [pc, #152] ; (80107f8 ) + 8010760: f00b fc58 bl 801c014 + while (rem_len > q->len) { + 8010764: 68fb ldr r3, [r7, #12] + 8010766: 895b ldrh r3, [r3, #10] + 8010768: 897a ldrh r2, [r7, #10] + 801076a: 429a cmp r2, r3 + 801076c: d8e1 bhi.n 8010732 + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len) + 801076e: 68fb ldr r3, [r7, #12] + 8010770: 7b1b ldrb r3, [r3, #12] + 8010772: f003 030f and.w r3, r3, #15 + 8010776: 2b00 cmp r3, #0 + 8010778: d121 bne.n 80107be + 801077a: 68fb ldr r3, [r7, #12] + 801077c: 895b ldrh r3, [r3, #10] + 801077e: 897a ldrh r2, [r7, #10] + 8010780: 429a cmp r2, r3 + 8010782: d01c beq.n 80107be +#if LWIP_SUPPORT_CUSTOM_PBUF + && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0) + 8010784: 68fb ldr r3, [r7, #12] + 8010786: 7b5b ldrb r3, [r3, #13] + 8010788: f003 0302 and.w r3, r3, #2 + 801078c: 2b00 cmp r3, #0 + 801078e: d116 bne.n 80107be +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + ) { + /* reallocate and adjust the length of the pbuf that will be split */ + q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len)); + 8010790: 68fb ldr r3, [r7, #12] + 8010792: 685a ldr r2, [r3, #4] + 8010794: 68fb ldr r3, [r7, #12] + 8010796: 1ad3 subs r3, r2, r3 + 8010798: b29a uxth r2, r3 + 801079a: 897b ldrh r3, [r7, #10] + 801079c: 4413 add r3, r2 + 801079e: b29b uxth r3, r3 + 80107a0: 4619 mov r1, r3 + 80107a2: 68f8 ldr r0, [r7, #12] + 80107a4: f7fe ff58 bl 800f658 + 80107a8: 60f8 str r0, [r7, #12] + LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); + 80107aa: 68fb ldr r3, [r7, #12] + 80107ac: 2b00 cmp r3, #0 + 80107ae: d106 bne.n 80107be + 80107b0: 4b0f ldr r3, [pc, #60] ; (80107f0 ) + 80107b2: f240 12bd movw r2, #445 ; 0x1bd + 80107b6: 4912 ldr r1, [pc, #72] ; (8010800 ) + 80107b8: 480f ldr r0, [pc, #60] ; (80107f8 ) + 80107ba: f00b fc2b bl 801c014 + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + 80107be: 68fb ldr r3, [r7, #12] + 80107c0: 897a ldrh r2, [r7, #10] + 80107c2: 815a strh r2, [r3, #10] + q->tot_len = q->len; + 80107c4: 68fb ldr r3, [r7, #12] + 80107c6: 895a ldrh r2, [r3, #10] + 80107c8: 68fb ldr r3, [r7, #12] + 80107ca: 811a strh r2, [r3, #8] + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + 80107cc: 68fb ldr r3, [r7, #12] + 80107ce: 681b ldr r3, [r3, #0] + 80107d0: 2b00 cmp r3, #0 + 80107d2: d004 beq.n 80107de + /* free remaining pbufs in chain */ + pbuf_free(q->next); + 80107d4: 68fb ldr r3, [r7, #12] + 80107d6: 681b ldr r3, [r3, #0] + 80107d8: 4618 mov r0, r3 + 80107da: f000 f911 bl 8010a00 + } + /* q is last packet in chain */ + q->next = NULL; + 80107de: 68fb ldr r3, [r7, #12] + 80107e0: 2200 movs r2, #0 + 80107e2: 601a str r2, [r3, #0] + 80107e4: e000 b.n 80107e8 + return; + 80107e6: bf00 nop + +} + 80107e8: 3710 adds r7, #16 + 80107ea: 46bd mov sp, r7 + 80107ec: bd80 pop {r7, pc} + 80107ee: bf00 nop + 80107f0: 0801f020 .word 0x0801f020 + 80107f4: 0801f138 .word 0x0801f138 + 80107f8: 0801f080 .word 0x0801f080 + 80107fc: 0801f150 .word 0x0801f150 + 8010800: 0801f168 .word 0x0801f168 + +08010804 : + * @return non-zero on failure, zero on success. + * + */ +static u8_t +pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force) +{ + 8010804: b580 push {r7, lr} + 8010806: b086 sub sp, #24 + 8010808: af00 add r7, sp, #0 + 801080a: 60f8 str r0, [r7, #12] + 801080c: 60b9 str r1, [r7, #8] + 801080e: 4613 mov r3, r2 + 8010810: 71fb strb r3, [r7, #7] + u16_t type_internal; + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + 8010812: 68fb ldr r3, [r7, #12] + 8010814: 2b00 cmp r3, #0 + 8010816: d106 bne.n 8010826 + 8010818: 4b2b ldr r3, [pc, #172] ; (80108c8 ) + 801081a: f240 12df movw r2, #479 ; 0x1df + 801081e: 492b ldr r1, [pc, #172] ; (80108cc ) + 8010820: 482b ldr r0, [pc, #172] ; (80108d0 ) + 8010822: f00b fbf7 bl 801c014 + if ((p == NULL) || (header_size_increment > 0xFFFF)) { + 8010826: 68fb ldr r3, [r7, #12] + 8010828: 2b00 cmp r3, #0 + 801082a: d003 beq.n 8010834 + 801082c: 68bb ldr r3, [r7, #8] + 801082e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8010832: d301 bcc.n 8010838 + return 1; + 8010834: 2301 movs r3, #1 + 8010836: e043 b.n 80108c0 + } + if (header_size_increment == 0) { + 8010838: 68bb ldr r3, [r7, #8] + 801083a: 2b00 cmp r3, #0 + 801083c: d101 bne.n 8010842 + return 0; + 801083e: 2300 movs r3, #0 + 8010840: e03e b.n 80108c0 + } + + increment_magnitude = (u16_t)header_size_increment; + 8010842: 68bb ldr r3, [r7, #8] + 8010844: 827b strh r3, [r7, #18] + /* Do not allow tot_len to wrap as a result. */ + if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) { + 8010846: 68fb ldr r3, [r7, #12] + 8010848: 891a ldrh r2, [r3, #8] + 801084a: 8a7b ldrh r3, [r7, #18] + 801084c: 4413 add r3, r2 + 801084e: b29b uxth r3, r3 + 8010850: 8a7a ldrh r2, [r7, #18] + 8010852: 429a cmp r2, r3 + 8010854: d901 bls.n 801085a + return 1; + 8010856: 2301 movs r3, #1 + 8010858: e032 b.n 80108c0 + } + + type_internal = p->type_internal; + 801085a: 68fb ldr r3, [r7, #12] + 801085c: 7b1b ldrb r3, [r3, #12] + 801085e: 823b strh r3, [r7, #16] + + /* pbuf types containing payloads? */ + if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) { + 8010860: 8a3b ldrh r3, [r7, #16] + 8010862: f003 0380 and.w r3, r3, #128 ; 0x80 + 8010866: 2b00 cmp r3, #0 + 8010868: d00c beq.n 8010884 + /* set new payload pointer */ + payload = (u8_t *)p->payload - header_size_increment; + 801086a: 68fb ldr r3, [r7, #12] + 801086c: 685a ldr r2, [r3, #4] + 801086e: 68bb ldr r3, [r7, #8] + 8010870: 425b negs r3, r3 + 8010872: 4413 add r3, r2 + 8010874: 617b str r3, [r7, #20] + /* boundary check fails? */ + if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { + 8010876: 68fb ldr r3, [r7, #12] + 8010878: 3310 adds r3, #16 + 801087a: 697a ldr r2, [r7, #20] + 801087c: 429a cmp r2, r3 + 801087e: d20d bcs.n 801089c + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n", + (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF))); + /* bail out unsuccessfully */ + return 1; + 8010880: 2301 movs r3, #1 + 8010882: e01d b.n 80108c0 + } + /* pbuf types referring to external payloads? */ + } else { + /* hide a header in the payload? */ + if (force) { + 8010884: 79fb ldrb r3, [r7, #7] + 8010886: 2b00 cmp r3, #0 + 8010888: d006 beq.n 8010898 + payload = (u8_t *)p->payload - header_size_increment; + 801088a: 68fb ldr r3, [r7, #12] + 801088c: 685a ldr r2, [r3, #4] + 801088e: 68bb ldr r3, [r7, #8] + 8010890: 425b negs r3, r3 + 8010892: 4413 add r3, r2 + 8010894: 617b str r3, [r7, #20] + 8010896: e001 b.n 801089c + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccessfully */ + return 1; + 8010898: 2301 movs r3, #1 + 801089a: e011 b.n 80108c0 + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n", + (void *)p->payload, (void *)payload, increment_magnitude)); + + /* modify pbuf fields */ + p->payload = payload; + 801089c: 68fb ldr r3, [r7, #12] + 801089e: 697a ldr r2, [r7, #20] + 80108a0: 605a str r2, [r3, #4] + p->len = (u16_t)(p->len + increment_magnitude); + 80108a2: 68fb ldr r3, [r7, #12] + 80108a4: 895a ldrh r2, [r3, #10] + 80108a6: 8a7b ldrh r3, [r7, #18] + 80108a8: 4413 add r3, r2 + 80108aa: b29a uxth r2, r3 + 80108ac: 68fb ldr r3, [r7, #12] + 80108ae: 815a strh r2, [r3, #10] + p->tot_len = (u16_t)(p->tot_len + increment_magnitude); + 80108b0: 68fb ldr r3, [r7, #12] + 80108b2: 891a ldrh r2, [r3, #8] + 80108b4: 8a7b ldrh r3, [r7, #18] + 80108b6: 4413 add r3, r2 + 80108b8: b29a uxth r2, r3 + 80108ba: 68fb ldr r3, [r7, #12] + 80108bc: 811a strh r2, [r3, #8] + + + return 0; + 80108be: 2300 movs r3, #0 +} + 80108c0: 4618 mov r0, r3 + 80108c2: 3718 adds r7, #24 + 80108c4: 46bd mov sp, r7 + 80108c6: bd80 pop {r7, pc} + 80108c8: 0801f020 .word 0x0801f020 + 80108cc: 0801f184 .word 0x0801f184 + 80108d0: 0801f080 .word 0x0801f080 + +080108d4 : + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_add_header(struct pbuf *p, size_t header_size_increment) +{ + 80108d4: b580 push {r7, lr} + 80108d6: b082 sub sp, #8 + 80108d8: af00 add r7, sp, #0 + 80108da: 6078 str r0, [r7, #4] + 80108dc: 6039 str r1, [r7, #0] + return pbuf_add_header_impl(p, header_size_increment, 0); + 80108de: 2200 movs r2, #0 + 80108e0: 6839 ldr r1, [r7, #0] + 80108e2: 6878 ldr r0, [r7, #4] + 80108e4: f7ff ff8e bl 8010804 + 80108e8: 4603 mov r3, r0 +} + 80108ea: 4618 mov r0, r3 + 80108ec: 3708 adds r7, #8 + 80108ee: 46bd mov sp, r7 + 80108f0: bd80 pop {r7, pc} + ... + +080108f4 : + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_remove_header(struct pbuf *p, size_t header_size_decrement) +{ + 80108f4: b580 push {r7, lr} + 80108f6: b084 sub sp, #16 + 80108f8: af00 add r7, sp, #0 + 80108fa: 6078 str r0, [r7, #4] + 80108fc: 6039 str r1, [r7, #0] + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + 80108fe: 687b ldr r3, [r7, #4] + 8010900: 2b00 cmp r3, #0 + 8010902: d106 bne.n 8010912 + 8010904: 4b20 ldr r3, [pc, #128] ; (8010988 ) + 8010906: f240 224b movw r2, #587 ; 0x24b + 801090a: 4920 ldr r1, [pc, #128] ; (801098c ) + 801090c: 4820 ldr r0, [pc, #128] ; (8010990 ) + 801090e: f00b fb81 bl 801c014 + if ((p == NULL) || (header_size_decrement > 0xFFFF)) { + 8010912: 687b ldr r3, [r7, #4] + 8010914: 2b00 cmp r3, #0 + 8010916: d003 beq.n 8010920 + 8010918: 683b ldr r3, [r7, #0] + 801091a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 801091e: d301 bcc.n 8010924 + return 1; + 8010920: 2301 movs r3, #1 + 8010922: e02c b.n 801097e + } + if (header_size_decrement == 0) { + 8010924: 683b ldr r3, [r7, #0] + 8010926: 2b00 cmp r3, #0 + 8010928: d101 bne.n 801092e + return 0; + 801092a: 2300 movs r3, #0 + 801092c: e027 b.n 801097e + } + + increment_magnitude = (u16_t)header_size_decrement; + 801092e: 683b ldr r3, [r7, #0] + 8010930: 81fb strh r3, [r7, #14] + /* Check that we aren't going to move off the end of the pbuf */ + LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); + 8010932: 687b ldr r3, [r7, #4] + 8010934: 895b ldrh r3, [r3, #10] + 8010936: 89fa ldrh r2, [r7, #14] + 8010938: 429a cmp r2, r3 + 801093a: d908 bls.n 801094e + 801093c: 4b12 ldr r3, [pc, #72] ; (8010988 ) + 801093e: f240 2255 movw r2, #597 ; 0x255 + 8010942: 4914 ldr r1, [pc, #80] ; (8010994 ) + 8010944: 4812 ldr r0, [pc, #72] ; (8010990 ) + 8010946: f00b fb65 bl 801c014 + 801094a: 2301 movs r3, #1 + 801094c: e017 b.n 801097e + + /* remember current payload pointer */ + payload = p->payload; + 801094e: 687b ldr r3, [r7, #4] + 8010950: 685b ldr r3, [r3, #4] + 8010952: 60bb str r3, [r7, #8] + LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */ + + /* increase payload pointer (guarded by length check above) */ + p->payload = (u8_t *)p->payload + header_size_decrement; + 8010954: 687b ldr r3, [r7, #4] + 8010956: 685a ldr r2, [r3, #4] + 8010958: 683b ldr r3, [r7, #0] + 801095a: 441a add r2, r3 + 801095c: 687b ldr r3, [r7, #4] + 801095e: 605a str r2, [r3, #4] + /* modify pbuf length fields */ + p->len = (u16_t)(p->len - increment_magnitude); + 8010960: 687b ldr r3, [r7, #4] + 8010962: 895a ldrh r2, [r3, #10] + 8010964: 89fb ldrh r3, [r7, #14] + 8010966: 1ad3 subs r3, r2, r3 + 8010968: b29a uxth r2, r3 + 801096a: 687b ldr r3, [r7, #4] + 801096c: 815a strh r2, [r3, #10] + p->tot_len = (u16_t)(p->tot_len - increment_magnitude); + 801096e: 687b ldr r3, [r7, #4] + 8010970: 891a ldrh r2, [r3, #8] + 8010972: 89fb ldrh r3, [r7, #14] + 8010974: 1ad3 subs r3, r2, r3 + 8010976: b29a uxth r2, r3 + 8010978: 687b ldr r3, [r7, #4] + 801097a: 811a strh r2, [r3, #8] + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n", + (void *)payload, (void *)p->payload, increment_magnitude)); + + return 0; + 801097c: 2300 movs r3, #0 +} + 801097e: 4618 mov r0, r3 + 8010980: 3710 adds r7, #16 + 8010982: 46bd mov sp, r7 + 8010984: bd80 pop {r7, pc} + 8010986: bf00 nop + 8010988: 0801f020 .word 0x0801f020 + 801098c: 0801f184 .word 0x0801f184 + 8010990: 0801f080 .word 0x0801f080 + 8010994: 0801f190 .word 0x0801f190 + +08010998 : + +static u8_t +pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force) +{ + 8010998: b580 push {r7, lr} + 801099a: b082 sub sp, #8 + 801099c: af00 add r7, sp, #0 + 801099e: 6078 str r0, [r7, #4] + 80109a0: 460b mov r3, r1 + 80109a2: 807b strh r3, [r7, #2] + 80109a4: 4613 mov r3, r2 + 80109a6: 707b strb r3, [r7, #1] + if (header_size_increment < 0) { + 80109a8: f9b7 3002 ldrsh.w r3, [r7, #2] + 80109ac: 2b00 cmp r3, #0 + 80109ae: da08 bge.n 80109c2 + return pbuf_remove_header(p, (size_t) - header_size_increment); + 80109b0: f9b7 3002 ldrsh.w r3, [r7, #2] + 80109b4: 425b negs r3, r3 + 80109b6: 4619 mov r1, r3 + 80109b8: 6878 ldr r0, [r7, #4] + 80109ba: f7ff ff9b bl 80108f4 + 80109be: 4603 mov r3, r0 + 80109c0: e007 b.n 80109d2 + } else { + return pbuf_add_header_impl(p, (size_t)header_size_increment, force); + 80109c2: f9b7 3002 ldrsh.w r3, [r7, #2] + 80109c6: 787a ldrb r2, [r7, #1] + 80109c8: 4619 mov r1, r3 + 80109ca: 6878 ldr r0, [r7, #4] + 80109cc: f7ff ff1a bl 8010804 + 80109d0: 4603 mov r3, r0 + } +} + 80109d2: 4618 mov r0, r3 + 80109d4: 3708 adds r7, #8 + 80109d6: 46bd mov sp, r7 + 80109d8: bd80 pop {r7, pc} + +080109da : + * Same as pbuf_header but does not check if 'header_size > 0' is allowed. + * This is used internally only, to allow PBUF_REF for RX. + */ +u8_t +pbuf_header_force(struct pbuf *p, s16_t header_size_increment) +{ + 80109da: b580 push {r7, lr} + 80109dc: b082 sub sp, #8 + 80109de: af00 add r7, sp, #0 + 80109e0: 6078 str r0, [r7, #4] + 80109e2: 460b mov r3, r1 + 80109e4: 807b strh r3, [r7, #2] + return pbuf_header_impl(p, header_size_increment, 1); + 80109e6: f9b7 3002 ldrsh.w r3, [r7, #2] + 80109ea: 2201 movs r2, #1 + 80109ec: 4619 mov r1, r3 + 80109ee: 6878 ldr r0, [r7, #4] + 80109f0: f7ff ffd2 bl 8010998 + 80109f4: 4603 mov r3, r0 +} + 80109f6: 4618 mov r0, r3 + 80109f8: 3708 adds r7, #8 + 80109fa: 46bd mov sp, r7 + 80109fc: bd80 pop {r7, pc} + ... + +08010a00 : + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + 8010a00: b580 push {r7, lr} + 8010a02: b088 sub sp, #32 + 8010a04: af00 add r7, sp, #0 + 8010a06: 6078 str r0, [r7, #4] + u8_t alloc_src; + struct pbuf *q; + u8_t count; + + if (p == NULL) { + 8010a08: 687b ldr r3, [r7, #4] + 8010a0a: 2b00 cmp r3, #0 + 8010a0c: d10b bne.n 8010a26 + LWIP_ASSERT("p != NULL", p != NULL); + 8010a0e: 687b ldr r3, [r7, #4] + 8010a10: 2b00 cmp r3, #0 + 8010a12: d106 bne.n 8010a22 + 8010a14: 4b3b ldr r3, [pc, #236] ; (8010b04 ) + 8010a16: f44f 7237 mov.w r2, #732 ; 0x2dc + 8010a1a: 493b ldr r1, [pc, #236] ; (8010b08 ) + 8010a1c: 483b ldr r0, [pc, #236] ; (8010b0c ) + 8010a1e: f00b faf9 bl 801c014 + /* if assertions are disabled, proceed with debug output */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_free(p == NULL) was called.\n")); + return 0; + 8010a22: 2300 movs r3, #0 + 8010a24: e069 b.n 8010afa + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + count = 0; + 8010a26: 2300 movs r3, #0 + 8010a28: 77fb strb r3, [r7, #31] + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + 8010a2a: e062 b.n 8010af2 + LWIP_PBUF_REF_T ref; + SYS_ARCH_DECL_PROTECT(old_level); + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. We put the new ref into a local variable to prevent + * further protection. */ + SYS_ARCH_PROTECT(old_level); + 8010a2c: f00b f8e2 bl 801bbf4 + 8010a30: 61b8 str r0, [r7, #24] + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + 8010a32: 687b ldr r3, [r7, #4] + 8010a34: 7b9b ldrb r3, [r3, #14] + 8010a36: 2b00 cmp r3, #0 + 8010a38: d106 bne.n 8010a48 + 8010a3a: 4b32 ldr r3, [pc, #200] ; (8010b04 ) + 8010a3c: f240 22f1 movw r2, #753 ; 0x2f1 + 8010a40: 4933 ldr r1, [pc, #204] ; (8010b10 ) + 8010a42: 4832 ldr r0, [pc, #200] ; (8010b0c ) + 8010a44: f00b fae6 bl 801c014 + /* decrease reference count (number of pointers to pbuf) */ + ref = --(p->ref); + 8010a48: 687b ldr r3, [r7, #4] + 8010a4a: 7b9b ldrb r3, [r3, #14] + 8010a4c: 3b01 subs r3, #1 + 8010a4e: b2da uxtb r2, r3 + 8010a50: 687b ldr r3, [r7, #4] + 8010a52: 739a strb r2, [r3, #14] + 8010a54: 687b ldr r3, [r7, #4] + 8010a56: 7b9b ldrb r3, [r3, #14] + 8010a58: 75fb strb r3, [r7, #23] + SYS_ARCH_UNPROTECT(old_level); + 8010a5a: 69b8 ldr r0, [r7, #24] + 8010a5c: f00b f8d8 bl 801bc10 + /* this pbuf is no longer referenced to? */ + if (ref == 0) { + 8010a60: 7dfb ldrb r3, [r7, #23] + 8010a62: 2b00 cmp r3, #0 + 8010a64: d143 bne.n 8010aee + /* remember next pbuf in chain for next iteration */ + q = p->next; + 8010a66: 687b ldr r3, [r7, #4] + 8010a68: 681b ldr r3, [r3, #0] + 8010a6a: 613b str r3, [r7, #16] + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); + alloc_src = pbuf_get_allocsrc(p); + 8010a6c: 687b ldr r3, [r7, #4] + 8010a6e: 7b1b ldrb r3, [r3, #12] + 8010a70: f003 030f and.w r3, r3, #15 + 8010a74: 73fb strb r3, [r7, #15] +#if LWIP_SUPPORT_CUSTOM_PBUF + /* is this a custom pbuf? */ + if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { + 8010a76: 687b ldr r3, [r7, #4] + 8010a78: 7b5b ldrb r3, [r3, #13] + 8010a7a: f003 0302 and.w r3, r3, #2 + 8010a7e: 2b00 cmp r3, #0 + 8010a80: d011 beq.n 8010aa6 + struct pbuf_custom *pc = (struct pbuf_custom *)p; + 8010a82: 687b ldr r3, [r7, #4] + 8010a84: 60bb str r3, [r7, #8] + LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); + 8010a86: 68bb ldr r3, [r7, #8] + 8010a88: 691b ldr r3, [r3, #16] + 8010a8a: 2b00 cmp r3, #0 + 8010a8c: d106 bne.n 8010a9c + 8010a8e: 4b1d ldr r3, [pc, #116] ; (8010b04 ) + 8010a90: f240 22ff movw r2, #767 ; 0x2ff + 8010a94: 491f ldr r1, [pc, #124] ; (8010b14 ) + 8010a96: 481d ldr r0, [pc, #116] ; (8010b0c ) + 8010a98: f00b fabc bl 801c014 + pc->custom_free_function(p); + 8010a9c: 68bb ldr r3, [r7, #8] + 8010a9e: 691b ldr r3, [r3, #16] + 8010aa0: 6878 ldr r0, [r7, #4] + 8010aa2: 4798 blx r3 + 8010aa4: e01d b.n 8010ae2 + } else +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + { + /* is this a pbuf from the pool? */ + if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) { + 8010aa6: 7bfb ldrb r3, [r7, #15] + 8010aa8: 2b02 cmp r3, #2 + 8010aaa: d104 bne.n 8010ab6 + memp_free(MEMP_PBUF_POOL, p); + 8010aac: 6879 ldr r1, [r7, #4] + 8010aae: 200d movs r0, #13 + 8010ab0: f7ff f8f6 bl 800fca0 + 8010ab4: e015 b.n 8010ae2 + /* is this a ROM or RAM referencing pbuf? */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) { + 8010ab6: 7bfb ldrb r3, [r7, #15] + 8010ab8: 2b01 cmp r3, #1 + 8010aba: d104 bne.n 8010ac6 + memp_free(MEMP_PBUF, p); + 8010abc: 6879 ldr r1, [r7, #4] + 8010abe: 200c movs r0, #12 + 8010ac0: f7ff f8ee bl 800fca0 + 8010ac4: e00d b.n 8010ae2 + /* type == PBUF_RAM */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) { + 8010ac6: 7bfb ldrb r3, [r7, #15] + 8010ac8: 2b00 cmp r3, #0 + 8010aca: d103 bne.n 8010ad4 + mem_free(p); + 8010acc: 6878 ldr r0, [r7, #4] + 8010ace: f7fe fd33 bl 800f538 + 8010ad2: e006 b.n 8010ae2 + } else { + /* @todo: support freeing other types */ + LWIP_ASSERT("invalid pbuf type", 0); + 8010ad4: 4b0b ldr r3, [pc, #44] ; (8010b04 ) + 8010ad6: f240 320f movw r2, #783 ; 0x30f + 8010ada: 490f ldr r1, [pc, #60] ; (8010b18 ) + 8010adc: 480b ldr r0, [pc, #44] ; (8010b0c ) + 8010ade: f00b fa99 bl 801c014 + } + } + count++; + 8010ae2: 7ffb ldrb r3, [r7, #31] + 8010ae4: 3301 adds r3, #1 + 8010ae6: 77fb strb r3, [r7, #31] + /* proceed to next pbuf */ + p = q; + 8010ae8: 693b ldr r3, [r7, #16] + 8010aea: 607b str r3, [r7, #4] + 8010aec: e001 b.n 8010af2 + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref)); + /* stop walking through the chain */ + p = NULL; + 8010aee: 2300 movs r3, #0 + 8010af0: 607b str r3, [r7, #4] + while (p != NULL) { + 8010af2: 687b ldr r3, [r7, #4] + 8010af4: 2b00 cmp r3, #0 + 8010af6: d199 bne.n 8010a2c + } + } + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + return count; + 8010af8: 7ffb ldrb r3, [r7, #31] +} + 8010afa: 4618 mov r0, r3 + 8010afc: 3720 adds r7, #32 + 8010afe: 46bd mov sp, r7 + 8010b00: bd80 pop {r7, pc} + 8010b02: bf00 nop + 8010b04: 0801f020 .word 0x0801f020 + 8010b08: 0801f184 .word 0x0801f184 + 8010b0c: 0801f080 .word 0x0801f080 + 8010b10: 0801f1b0 .word 0x0801f1b0 + 8010b14: 0801f1c8 .word 0x0801f1c8 + 8010b18: 0801f1ec .word 0x0801f1ec + +08010b1c : + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ +u16_t +pbuf_clen(const struct pbuf *p) +{ + 8010b1c: b480 push {r7} + 8010b1e: b085 sub sp, #20 + 8010b20: af00 add r7, sp, #0 + 8010b22: 6078 str r0, [r7, #4] + u16_t len; + + len = 0; + 8010b24: 2300 movs r3, #0 + 8010b26: 81fb strh r3, [r7, #14] + while (p != NULL) { + 8010b28: e005 b.n 8010b36 + ++len; + 8010b2a: 89fb ldrh r3, [r7, #14] + 8010b2c: 3301 adds r3, #1 + 8010b2e: 81fb strh r3, [r7, #14] + p = p->next; + 8010b30: 687b ldr r3, [r7, #4] + 8010b32: 681b ldr r3, [r3, #0] + 8010b34: 607b str r3, [r7, #4] + while (p != NULL) { + 8010b36: 687b ldr r3, [r7, #4] + 8010b38: 2b00 cmp r3, #0 + 8010b3a: d1f6 bne.n 8010b2a + } + return len; + 8010b3c: 89fb ldrh r3, [r7, #14] +} + 8010b3e: 4618 mov r0, r3 + 8010b40: 3714 adds r7, #20 + 8010b42: 46bd mov sp, r7 + 8010b44: f85d 7b04 ldr.w r7, [sp], #4 + 8010b48: 4770 bx lr + ... + +08010b4c : + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + 8010b4c: b580 push {r7, lr} + 8010b4e: b084 sub sp, #16 + 8010b50: af00 add r7, sp, #0 + 8010b52: 6078 str r0, [r7, #4] + /* pbuf given? */ + if (p != NULL) { + 8010b54: 687b ldr r3, [r7, #4] + 8010b56: 2b00 cmp r3, #0 + 8010b58: d016 beq.n 8010b88 + SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1)); + 8010b5a: f00b f84b bl 801bbf4 + 8010b5e: 60f8 str r0, [r7, #12] + 8010b60: 687b ldr r3, [r7, #4] + 8010b62: 7b9b ldrb r3, [r3, #14] + 8010b64: 3301 adds r3, #1 + 8010b66: b2da uxtb r2, r3 + 8010b68: 687b ldr r3, [r7, #4] + 8010b6a: 739a strb r2, [r3, #14] + 8010b6c: 68f8 ldr r0, [r7, #12] + 8010b6e: f00b f84f bl 801bc10 + LWIP_ASSERT("pbuf ref overflow", p->ref > 0); + 8010b72: 687b ldr r3, [r7, #4] + 8010b74: 7b9b ldrb r3, [r3, #14] + 8010b76: 2b00 cmp r3, #0 + 8010b78: d106 bne.n 8010b88 + 8010b7a: 4b05 ldr r3, [pc, #20] ; (8010b90 ) + 8010b7c: f240 3242 movw r2, #834 ; 0x342 + 8010b80: 4904 ldr r1, [pc, #16] ; (8010b94 ) + 8010b82: 4805 ldr r0, [pc, #20] ; (8010b98 ) + 8010b84: f00b fa46 bl 801c014 + } +} + 8010b88: bf00 nop + 8010b8a: 3710 adds r7, #16 + 8010b8c: 46bd mov sp, r7 + 8010b8e: bd80 pop {r7, pc} + 8010b90: 0801f020 .word 0x0801f020 + 8010b94: 0801f200 .word 0x0801f200 + 8010b98: 0801f080 .word 0x0801f080 + +08010b9c : + * + * @see pbuf_chain() + */ +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + 8010b9c: b580 push {r7, lr} + 8010b9e: b084 sub sp, #16 + 8010ba0: af00 add r7, sp, #0 + 8010ba2: 6078 str r0, [r7, #4] + 8010ba4: 6039 str r1, [r7, #0] + struct pbuf *p; + + LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", + 8010ba6: 687b ldr r3, [r7, #4] + 8010ba8: 2b00 cmp r3, #0 + 8010baa: d002 beq.n 8010bb2 + 8010bac: 683b ldr r3, [r7, #0] + 8010bae: 2b00 cmp r3, #0 + 8010bb0: d107 bne.n 8010bc2 + 8010bb2: 4b20 ldr r3, [pc, #128] ; (8010c34 ) + 8010bb4: f240 3259 movw r2, #857 ; 0x359 + 8010bb8: 491f ldr r1, [pc, #124] ; (8010c38 ) + 8010bba: 4820 ldr r0, [pc, #128] ; (8010c3c ) + 8010bbc: f00b fa2a bl 801c014 + 8010bc0: e034 b.n 8010c2c + ((h != NULL) && (t != NULL)), return;); + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + 8010bc2: 687b ldr r3, [r7, #4] + 8010bc4: 60fb str r3, [r7, #12] + 8010bc6: e00a b.n 8010bde + /* add total length of second chain to all totals of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + 8010bc8: 68fb ldr r3, [r7, #12] + 8010bca: 891a ldrh r2, [r3, #8] + 8010bcc: 683b ldr r3, [r7, #0] + 8010bce: 891b ldrh r3, [r3, #8] + 8010bd0: 4413 add r3, r2 + 8010bd2: b29a uxth r2, r3 + 8010bd4: 68fb ldr r3, [r7, #12] + 8010bd6: 811a strh r2, [r3, #8] + for (p = h; p->next != NULL; p = p->next) { + 8010bd8: 68fb ldr r3, [r7, #12] + 8010bda: 681b ldr r3, [r3, #0] + 8010bdc: 60fb str r3, [r7, #12] + 8010bde: 68fb ldr r3, [r7, #12] + 8010be0: 681b ldr r3, [r3, #0] + 8010be2: 2b00 cmp r3, #0 + 8010be4: d1f0 bne.n 8010bc8 + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + 8010be6: 68fb ldr r3, [r7, #12] + 8010be8: 891a ldrh r2, [r3, #8] + 8010bea: 68fb ldr r3, [r7, #12] + 8010bec: 895b ldrh r3, [r3, #10] + 8010bee: 429a cmp r2, r3 + 8010bf0: d006 beq.n 8010c00 + 8010bf2: 4b10 ldr r3, [pc, #64] ; (8010c34 ) + 8010bf4: f240 3262 movw r2, #866 ; 0x362 + 8010bf8: 4911 ldr r1, [pc, #68] ; (8010c40 ) + 8010bfa: 4810 ldr r0, [pc, #64] ; (8010c3c ) + 8010bfc: f00b fa0a bl 801c014 + LWIP_ASSERT("p->next == NULL", p->next == NULL); + 8010c00: 68fb ldr r3, [r7, #12] + 8010c02: 681b ldr r3, [r3, #0] + 8010c04: 2b00 cmp r3, #0 + 8010c06: d006 beq.n 8010c16 + 8010c08: 4b0a ldr r3, [pc, #40] ; (8010c34 ) + 8010c0a: f240 3263 movw r2, #867 ; 0x363 + 8010c0e: 490d ldr r1, [pc, #52] ; (8010c44 ) + 8010c10: 480a ldr r0, [pc, #40] ; (8010c3c ) + 8010c12: f00b f9ff bl 801c014 + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + 8010c16: 68fb ldr r3, [r7, #12] + 8010c18: 891a ldrh r2, [r3, #8] + 8010c1a: 683b ldr r3, [r7, #0] + 8010c1c: 891b ldrh r3, [r3, #8] + 8010c1e: 4413 add r3, r2 + 8010c20: b29a uxth r2, r3 + 8010c22: 68fb ldr r3, [r7, #12] + 8010c24: 811a strh r2, [r3, #8] + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + 8010c26: 68fb ldr r3, [r7, #12] + 8010c28: 683a ldr r2, [r7, #0] + 8010c2a: 601a str r2, [r3, #0] + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + 8010c2c: 3710 adds r7, #16 + 8010c2e: 46bd mov sp, r7 + 8010c30: bd80 pop {r7, pc} + 8010c32: bf00 nop + 8010c34: 0801f020 .word 0x0801f020 + 8010c38: 0801f214 .word 0x0801f214 + 8010c3c: 0801f080 .word 0x0801f080 + 8010c40: 0801f24c .word 0x0801f24c + 8010c44: 0801f27c .word 0x0801f27c + +08010c48 : + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + 8010c48: b580 push {r7, lr} + 8010c4a: b082 sub sp, #8 + 8010c4c: af00 add r7, sp, #0 + 8010c4e: 6078 str r0, [r7, #4] + 8010c50: 6039 str r1, [r7, #0] + pbuf_cat(h, t); + 8010c52: 6839 ldr r1, [r7, #0] + 8010c54: 6878 ldr r0, [r7, #4] + 8010c56: f7ff ffa1 bl 8010b9c + /* t is now referenced by h */ + pbuf_ref(t); + 8010c5a: 6838 ldr r0, [r7, #0] + 8010c5c: f7ff ff76 bl 8010b4c + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + 8010c60: bf00 nop + 8010c62: 3708 adds r7, #8 + 8010c64: 46bd mov sp, r7 + 8010c66: bd80 pop {r7, pc} + +08010c68 : + * ERR_ARG if one of the pbufs is NULL or p_to is not big + * enough to hold p_from + */ +err_t +pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from) +{ + 8010c68: b580 push {r7, lr} + 8010c6a: b086 sub sp, #24 + 8010c6c: af00 add r7, sp, #0 + 8010c6e: 6078 str r0, [r7, #4] + 8010c70: 6039 str r1, [r7, #0] + size_t offset_to = 0, offset_from = 0, len; + 8010c72: 2300 movs r3, #0 + 8010c74: 617b str r3, [r7, #20] + 8010c76: 2300 movs r3, #0 + 8010c78: 613b str r3, [r7, #16] + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", + (const void *)p_to, (const void *)p_from)); + + /* is the target big enough to hold the source? */ + LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && + 8010c7a: 687b ldr r3, [r7, #4] + 8010c7c: 2b00 cmp r3, #0 + 8010c7e: d008 beq.n 8010c92 + 8010c80: 683b ldr r3, [r7, #0] + 8010c82: 2b00 cmp r3, #0 + 8010c84: d005 beq.n 8010c92 + 8010c86: 687b ldr r3, [r7, #4] + 8010c88: 891a ldrh r2, [r3, #8] + 8010c8a: 683b ldr r3, [r7, #0] + 8010c8c: 891b ldrh r3, [r3, #8] + 8010c8e: 429a cmp r2, r3 + 8010c90: d209 bcs.n 8010ca6 + 8010c92: 4b57 ldr r3, [pc, #348] ; (8010df0 ) + 8010c94: f240 32c9 movw r2, #969 ; 0x3c9 + 8010c98: 4956 ldr r1, [pc, #344] ; (8010df4 ) + 8010c9a: 4857 ldr r0, [pc, #348] ; (8010df8 ) + 8010c9c: f00b f9ba bl 801c014 + 8010ca0: f06f 030f mvn.w r3, #15 + 8010ca4: e09f b.n 8010de6 + (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); + + /* iterate through pbuf chain */ + do { + /* copy one part of the original chain */ + if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { + 8010ca6: 687b ldr r3, [r7, #4] + 8010ca8: 895b ldrh r3, [r3, #10] + 8010caa: 461a mov r2, r3 + 8010cac: 697b ldr r3, [r7, #20] + 8010cae: 1ad2 subs r2, r2, r3 + 8010cb0: 683b ldr r3, [r7, #0] + 8010cb2: 895b ldrh r3, [r3, #10] + 8010cb4: 4619 mov r1, r3 + 8010cb6: 693b ldr r3, [r7, #16] + 8010cb8: 1acb subs r3, r1, r3 + 8010cba: 429a cmp r2, r3 + 8010cbc: d306 bcc.n 8010ccc + /* complete current p_from fits into current p_to */ + len = p_from->len - offset_from; + 8010cbe: 683b ldr r3, [r7, #0] + 8010cc0: 895b ldrh r3, [r3, #10] + 8010cc2: 461a mov r2, r3 + 8010cc4: 693b ldr r3, [r7, #16] + 8010cc6: 1ad3 subs r3, r2, r3 + 8010cc8: 60fb str r3, [r7, #12] + 8010cca: e005 b.n 8010cd8 + } else { + /* current p_from does not fit into current p_to */ + len = p_to->len - offset_to; + 8010ccc: 687b ldr r3, [r7, #4] + 8010cce: 895b ldrh r3, [r3, #10] + 8010cd0: 461a mov r2, r3 + 8010cd2: 697b ldr r3, [r7, #20] + 8010cd4: 1ad3 subs r3, r2, r3 + 8010cd6: 60fb str r3, [r7, #12] + } + MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len); + 8010cd8: 687b ldr r3, [r7, #4] + 8010cda: 685a ldr r2, [r3, #4] + 8010cdc: 697b ldr r3, [r7, #20] + 8010cde: 18d0 adds r0, r2, r3 + 8010ce0: 683b ldr r3, [r7, #0] + 8010ce2: 685a ldr r2, [r3, #4] + 8010ce4: 693b ldr r3, [r7, #16] + 8010ce6: 4413 add r3, r2 + 8010ce8: 68fa ldr r2, [r7, #12] + 8010cea: 4619 mov r1, r3 + 8010cec: f00b f8cd bl 801be8a + offset_to += len; + 8010cf0: 697a ldr r2, [r7, #20] + 8010cf2: 68fb ldr r3, [r7, #12] + 8010cf4: 4413 add r3, r2 + 8010cf6: 617b str r3, [r7, #20] + offset_from += len; + 8010cf8: 693a ldr r2, [r7, #16] + 8010cfa: 68fb ldr r3, [r7, #12] + 8010cfc: 4413 add r3, r2 + 8010cfe: 613b str r3, [r7, #16] + LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); + 8010d00: 687b ldr r3, [r7, #4] + 8010d02: 895b ldrh r3, [r3, #10] + 8010d04: 461a mov r2, r3 + 8010d06: 697b ldr r3, [r7, #20] + 8010d08: 4293 cmp r3, r2 + 8010d0a: d906 bls.n 8010d1a + 8010d0c: 4b38 ldr r3, [pc, #224] ; (8010df0 ) + 8010d0e: f240 32d9 movw r2, #985 ; 0x3d9 + 8010d12: 493a ldr r1, [pc, #232] ; (8010dfc ) + 8010d14: 4838 ldr r0, [pc, #224] ; (8010df8 ) + 8010d16: f00b f97d bl 801c014 + LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); + 8010d1a: 683b ldr r3, [r7, #0] + 8010d1c: 895b ldrh r3, [r3, #10] + 8010d1e: 461a mov r2, r3 + 8010d20: 693b ldr r3, [r7, #16] + 8010d22: 4293 cmp r3, r2 + 8010d24: d906 bls.n 8010d34 + 8010d26: 4b32 ldr r3, [pc, #200] ; (8010df0 ) + 8010d28: f240 32da movw r2, #986 ; 0x3da + 8010d2c: 4934 ldr r1, [pc, #208] ; (8010e00 ) + 8010d2e: 4832 ldr r0, [pc, #200] ; (8010df8 ) + 8010d30: f00b f970 bl 801c014 + if (offset_from >= p_from->len) { + 8010d34: 683b ldr r3, [r7, #0] + 8010d36: 895b ldrh r3, [r3, #10] + 8010d38: 461a mov r2, r3 + 8010d3a: 693b ldr r3, [r7, #16] + 8010d3c: 4293 cmp r3, r2 + 8010d3e: d304 bcc.n 8010d4a + /* on to next p_from (if any) */ + offset_from = 0; + 8010d40: 2300 movs r3, #0 + 8010d42: 613b str r3, [r7, #16] + p_from = p_from->next; + 8010d44: 683b ldr r3, [r7, #0] + 8010d46: 681b ldr r3, [r3, #0] + 8010d48: 603b str r3, [r7, #0] + } + if (offset_to == p_to->len) { + 8010d4a: 687b ldr r3, [r7, #4] + 8010d4c: 895b ldrh r3, [r3, #10] + 8010d4e: 461a mov r2, r3 + 8010d50: 697b ldr r3, [r7, #20] + 8010d52: 4293 cmp r3, r2 + 8010d54: d114 bne.n 8010d80 + /* on to next p_to (if any) */ + offset_to = 0; + 8010d56: 2300 movs r3, #0 + 8010d58: 617b str r3, [r7, #20] + p_to = p_to->next; + 8010d5a: 687b ldr r3, [r7, #4] + 8010d5c: 681b ldr r3, [r3, #0] + 8010d5e: 607b str r3, [r7, #4] + LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;); + 8010d60: 687b ldr r3, [r7, #4] + 8010d62: 2b00 cmp r3, #0 + 8010d64: d10c bne.n 8010d80 + 8010d66: 683b ldr r3, [r7, #0] + 8010d68: 2b00 cmp r3, #0 + 8010d6a: d009 beq.n 8010d80 + 8010d6c: 4b20 ldr r3, [pc, #128] ; (8010df0 ) + 8010d6e: f44f 7279 mov.w r2, #996 ; 0x3e4 + 8010d72: 4924 ldr r1, [pc, #144] ; (8010e04 ) + 8010d74: 4820 ldr r0, [pc, #128] ; (8010df8 ) + 8010d76: f00b f94d bl 801c014 + 8010d7a: f06f 030f mvn.w r3, #15 + 8010d7e: e032 b.n 8010de6 + } + + if ((p_from != NULL) && (p_from->len == p_from->tot_len)) { + 8010d80: 683b ldr r3, [r7, #0] + 8010d82: 2b00 cmp r3, #0 + 8010d84: d013 beq.n 8010dae + 8010d86: 683b ldr r3, [r7, #0] + 8010d88: 895a ldrh r2, [r3, #10] + 8010d8a: 683b ldr r3, [r7, #0] + 8010d8c: 891b ldrh r3, [r3, #8] + 8010d8e: 429a cmp r2, r3 + 8010d90: d10d bne.n 8010dae + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + 8010d92: 683b ldr r3, [r7, #0] + 8010d94: 681b ldr r3, [r3, #0] + 8010d96: 2b00 cmp r3, #0 + 8010d98: d009 beq.n 8010dae + 8010d9a: 4b15 ldr r3, [pc, #84] ; (8010df0 ) + 8010d9c: f240 32e9 movw r2, #1001 ; 0x3e9 + 8010da0: 4919 ldr r1, [pc, #100] ; (8010e08 ) + 8010da2: 4815 ldr r0, [pc, #84] ; (8010df8 ) + 8010da4: f00b f936 bl 801c014 + 8010da8: f06f 0305 mvn.w r3, #5 + 8010dac: e01b b.n 8010de6 + (p_from->next == NULL), return ERR_VAL;); + } + if ((p_to != NULL) && (p_to->len == p_to->tot_len)) { + 8010dae: 687b ldr r3, [r7, #4] + 8010db0: 2b00 cmp r3, #0 + 8010db2: d013 beq.n 8010ddc + 8010db4: 687b ldr r3, [r7, #4] + 8010db6: 895a ldrh r2, [r3, #10] + 8010db8: 687b ldr r3, [r7, #4] + 8010dba: 891b ldrh r3, [r3, #8] + 8010dbc: 429a cmp r2, r3 + 8010dbe: d10d bne.n 8010ddc + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + 8010dc0: 687b ldr r3, [r7, #4] + 8010dc2: 681b ldr r3, [r3, #0] + 8010dc4: 2b00 cmp r3, #0 + 8010dc6: d009 beq.n 8010ddc + 8010dc8: 4b09 ldr r3, [pc, #36] ; (8010df0 ) + 8010dca: f240 32ee movw r2, #1006 ; 0x3ee + 8010dce: 490e ldr r1, [pc, #56] ; (8010e08 ) + 8010dd0: 4809 ldr r0, [pc, #36] ; (8010df8 ) + 8010dd2: f00b f91f bl 801c014 + 8010dd6: f06f 0305 mvn.w r3, #5 + 8010dda: e004 b.n 8010de6 + (p_to->next == NULL), return ERR_VAL;); + } + } while (p_from); + 8010ddc: 683b ldr r3, [r7, #0] + 8010dde: 2b00 cmp r3, #0 + 8010de0: f47f af61 bne.w 8010ca6 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); + return ERR_OK; + 8010de4: 2300 movs r3, #0 +} + 8010de6: 4618 mov r0, r3 + 8010de8: 3718 adds r7, #24 + 8010dea: 46bd mov sp, r7 + 8010dec: bd80 pop {r7, pc} + 8010dee: bf00 nop + 8010df0: 0801f020 .word 0x0801f020 + 8010df4: 0801f2c8 .word 0x0801f2c8 + 8010df8: 0801f080 .word 0x0801f080 + 8010dfc: 0801f2f8 .word 0x0801f2f8 + 8010e00: 0801f310 .word 0x0801f310 + 8010e04: 0801f32c .word 0x0801f32c + 8010e08: 0801f33c .word 0x0801f33c + +08010e0c : + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +u16_t +pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + 8010e0c: b580 push {r7, lr} + 8010e0e: b088 sub sp, #32 + 8010e10: af00 add r7, sp, #0 + 8010e12: 60f8 str r0, [r7, #12] + 8010e14: 60b9 str r1, [r7, #8] + 8010e16: 4611 mov r1, r2 + 8010e18: 461a mov r2, r3 + 8010e1a: 460b mov r3, r1 + 8010e1c: 80fb strh r3, [r7, #6] + 8010e1e: 4613 mov r3, r2 + 8010e20: 80bb strh r3, [r7, #4] + const struct pbuf *p; + u16_t left = 0; + 8010e22: 2300 movs r3, #0 + 8010e24: 837b strh r3, [r7, #26] + u16_t buf_copy_len; + u16_t copied_total = 0; + 8010e26: 2300 movs r3, #0 + 8010e28: 82fb strh r3, [r7, #22] + + LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); + 8010e2a: 68fb ldr r3, [r7, #12] + 8010e2c: 2b00 cmp r3, #0 + 8010e2e: d108 bne.n 8010e42 + 8010e30: 4b2b ldr r3, [pc, #172] ; (8010ee0 ) + 8010e32: f240 420a movw r2, #1034 ; 0x40a + 8010e36: 492b ldr r1, [pc, #172] ; (8010ee4 ) + 8010e38: 482b ldr r0, [pc, #172] ; (8010ee8 ) + 8010e3a: f00b f8eb bl 801c014 + 8010e3e: 2300 movs r3, #0 + 8010e40: e04a b.n 8010ed8 + LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); + 8010e42: 68bb ldr r3, [r7, #8] + 8010e44: 2b00 cmp r3, #0 + 8010e46: d108 bne.n 8010e5a + 8010e48: 4b25 ldr r3, [pc, #148] ; (8010ee0 ) + 8010e4a: f240 420b movw r2, #1035 ; 0x40b + 8010e4e: 4927 ldr r1, [pc, #156] ; (8010eec ) + 8010e50: 4825 ldr r0, [pc, #148] ; (8010ee8 ) + 8010e52: f00b f8df bl 801c014 + 8010e56: 2300 movs r3, #0 + 8010e58: e03e b.n 8010ed8 + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for (p = buf; len != 0 && p != NULL; p = p->next) { + 8010e5a: 68fb ldr r3, [r7, #12] + 8010e5c: 61fb str r3, [r7, #28] + 8010e5e: e034 b.n 8010eca + if ((offset != 0) && (offset >= p->len)) { + 8010e60: 88bb ldrh r3, [r7, #4] + 8010e62: 2b00 cmp r3, #0 + 8010e64: d00a beq.n 8010e7c + 8010e66: 69fb ldr r3, [r7, #28] + 8010e68: 895b ldrh r3, [r3, #10] + 8010e6a: 88ba ldrh r2, [r7, #4] + 8010e6c: 429a cmp r2, r3 + 8010e6e: d305 bcc.n 8010e7c + /* don't copy from this buffer -> on to the next */ + offset = (u16_t)(offset - p->len); + 8010e70: 69fb ldr r3, [r7, #28] + 8010e72: 895b ldrh r3, [r3, #10] + 8010e74: 88ba ldrh r2, [r7, #4] + 8010e76: 1ad3 subs r3, r2, r3 + 8010e78: 80bb strh r3, [r7, #4] + 8010e7a: e023 b.n 8010ec4 + } else { + /* copy from this buffer. maybe only partially. */ + buf_copy_len = (u16_t)(p->len - offset); + 8010e7c: 69fb ldr r3, [r7, #28] + 8010e7e: 895a ldrh r2, [r3, #10] + 8010e80: 88bb ldrh r3, [r7, #4] + 8010e82: 1ad3 subs r3, r2, r3 + 8010e84: 833b strh r3, [r7, #24] + if (buf_copy_len > len) { + 8010e86: 8b3a ldrh r2, [r7, #24] + 8010e88: 88fb ldrh r3, [r7, #6] + 8010e8a: 429a cmp r2, r3 + 8010e8c: d901 bls.n 8010e92 + buf_copy_len = len; + 8010e8e: 88fb ldrh r3, [r7, #6] + 8010e90: 833b strh r3, [r7, #24] + } + /* copy the necessary parts of the buffer */ + MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len); + 8010e92: 8b7b ldrh r3, [r7, #26] + 8010e94: 68ba ldr r2, [r7, #8] + 8010e96: 18d0 adds r0, r2, r3 + 8010e98: 69fb ldr r3, [r7, #28] + 8010e9a: 685a ldr r2, [r3, #4] + 8010e9c: 88bb ldrh r3, [r7, #4] + 8010e9e: 4413 add r3, r2 + 8010ea0: 8b3a ldrh r2, [r7, #24] + 8010ea2: 4619 mov r1, r3 + 8010ea4: f00a fff1 bl 801be8a + copied_total = (u16_t)(copied_total + buf_copy_len); + 8010ea8: 8afa ldrh r2, [r7, #22] + 8010eaa: 8b3b ldrh r3, [r7, #24] + 8010eac: 4413 add r3, r2 + 8010eae: 82fb strh r3, [r7, #22] + left = (u16_t)(left + buf_copy_len); + 8010eb0: 8b7a ldrh r2, [r7, #26] + 8010eb2: 8b3b ldrh r3, [r7, #24] + 8010eb4: 4413 add r3, r2 + 8010eb6: 837b strh r3, [r7, #26] + len = (u16_t)(len - buf_copy_len); + 8010eb8: 88fa ldrh r2, [r7, #6] + 8010eba: 8b3b ldrh r3, [r7, #24] + 8010ebc: 1ad3 subs r3, r2, r3 + 8010ebe: 80fb strh r3, [r7, #6] + offset = 0; + 8010ec0: 2300 movs r3, #0 + 8010ec2: 80bb strh r3, [r7, #4] + for (p = buf; len != 0 && p != NULL; p = p->next) { + 8010ec4: 69fb ldr r3, [r7, #28] + 8010ec6: 681b ldr r3, [r3, #0] + 8010ec8: 61fb str r3, [r7, #28] + 8010eca: 88fb ldrh r3, [r7, #6] + 8010ecc: 2b00 cmp r3, #0 + 8010ece: d002 beq.n 8010ed6 + 8010ed0: 69fb ldr r3, [r7, #28] + 8010ed2: 2b00 cmp r3, #0 + 8010ed4: d1c4 bne.n 8010e60 + } + } + return copied_total; + 8010ed6: 8afb ldrh r3, [r7, #22] +} + 8010ed8: 4618 mov r0, r3 + 8010eda: 3720 adds r7, #32 + 8010edc: 46bd mov sp, r7 + 8010ede: bd80 pop {r7, pc} + 8010ee0: 0801f020 .word 0x0801f020 + 8010ee4: 0801f368 .word 0x0801f368 + 8010ee8: 0801f080 .word 0x0801f080 + 8010eec: 0801f388 .word 0x0801f388 + +08010ef0 : +#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + +/* Actual implementation of pbuf_skip() but returning const pointer... */ +static const struct pbuf * +pbuf_skip_const(const struct pbuf *in, u16_t in_offset, u16_t *out_offset) +{ + 8010ef0: b480 push {r7} + 8010ef2: b087 sub sp, #28 + 8010ef4: af00 add r7, sp, #0 + 8010ef6: 60f8 str r0, [r7, #12] + 8010ef8: 460b mov r3, r1 + 8010efa: 607a str r2, [r7, #4] + 8010efc: 817b strh r3, [r7, #10] + u16_t offset_left = in_offset; + 8010efe: 897b ldrh r3, [r7, #10] + 8010f00: 82fb strh r3, [r7, #22] + const struct pbuf *q = in; + 8010f02: 68fb ldr r3, [r7, #12] + 8010f04: 613b str r3, [r7, #16] + + /* get the correct pbuf */ + while ((q != NULL) && (q->len <= offset_left)) { + 8010f06: e007 b.n 8010f18 + offset_left = (u16_t)(offset_left - q->len); + 8010f08: 693b ldr r3, [r7, #16] + 8010f0a: 895b ldrh r3, [r3, #10] + 8010f0c: 8afa ldrh r2, [r7, #22] + 8010f0e: 1ad3 subs r3, r2, r3 + 8010f10: 82fb strh r3, [r7, #22] + q = q->next; + 8010f12: 693b ldr r3, [r7, #16] + 8010f14: 681b ldr r3, [r3, #0] + 8010f16: 613b str r3, [r7, #16] + while ((q != NULL) && (q->len <= offset_left)) { + 8010f18: 693b ldr r3, [r7, #16] + 8010f1a: 2b00 cmp r3, #0 + 8010f1c: d004 beq.n 8010f28 + 8010f1e: 693b ldr r3, [r7, #16] + 8010f20: 895b ldrh r3, [r3, #10] + 8010f22: 8afa ldrh r2, [r7, #22] + 8010f24: 429a cmp r2, r3 + 8010f26: d2ef bcs.n 8010f08 + } + if (out_offset != NULL) { + 8010f28: 687b ldr r3, [r7, #4] + 8010f2a: 2b00 cmp r3, #0 + 8010f2c: d002 beq.n 8010f34 + *out_offset = offset_left; + 8010f2e: 687b ldr r3, [r7, #4] + 8010f30: 8afa ldrh r2, [r7, #22] + 8010f32: 801a strh r2, [r3, #0] + } + return q; + 8010f34: 693b ldr r3, [r7, #16] +} + 8010f36: 4618 mov r0, r3 + 8010f38: 371c adds r7, #28 + 8010f3a: 46bd mov sp, r7 + 8010f3c: f85d 7b04 ldr.w r7, [sp], #4 + 8010f40: 4770 bx lr + +08010f42 : + * @param out_offset resulting offset in the returned pbuf + * @return the pbuf in the queue where the offset is + */ +struct pbuf * +pbuf_skip(struct pbuf *in, u16_t in_offset, u16_t *out_offset) +{ + 8010f42: b580 push {r7, lr} + 8010f44: b086 sub sp, #24 + 8010f46: af00 add r7, sp, #0 + 8010f48: 60f8 str r0, [r7, #12] + 8010f4a: 460b mov r3, r1 + 8010f4c: 607a str r2, [r7, #4] + 8010f4e: 817b strh r3, [r7, #10] + const struct pbuf *out = pbuf_skip_const(in, in_offset, out_offset); + 8010f50: 897b ldrh r3, [r7, #10] + 8010f52: 687a ldr r2, [r7, #4] + 8010f54: 4619 mov r1, r3 + 8010f56: 68f8 ldr r0, [r7, #12] + 8010f58: f7ff ffca bl 8010ef0 + 8010f5c: 6178 str r0, [r7, #20] + return LWIP_CONST_CAST(struct pbuf *, out); + 8010f5e: 697b ldr r3, [r7, #20] +} + 8010f60: 4618 mov r0, r3 + 8010f62: 3718 adds r7, #24 + 8010f64: 46bd mov sp, r7 + 8010f66: bd80 pop {r7, pc} + +08010f68 : + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) +{ + 8010f68: b580 push {r7, lr} + 8010f6a: b088 sub sp, #32 + 8010f6c: af00 add r7, sp, #0 + 8010f6e: 60f8 str r0, [r7, #12] + 8010f70: 60b9 str r1, [r7, #8] + 8010f72: 4613 mov r3, r2 + 8010f74: 80fb strh r3, [r7, #6] + struct pbuf *p; + size_t buf_copy_len; + size_t total_copy_len = len; + 8010f76: 88fb ldrh r3, [r7, #6] + 8010f78: 617b str r3, [r7, #20] + size_t copied_total = 0; + 8010f7a: 2300 movs r3, #0 + 8010f7c: 613b str r3, [r7, #16] + + LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return ERR_ARG;); + 8010f7e: 68fb ldr r3, [r7, #12] + 8010f80: 2b00 cmp r3, #0 + 8010f82: d109 bne.n 8010f98 + 8010f84: 4b3a ldr r3, [pc, #232] ; (8011070 ) + 8010f86: f240 42b3 movw r2, #1203 ; 0x4b3 + 8010f8a: 493a ldr r1, [pc, #232] ; (8011074 ) + 8010f8c: 483a ldr r0, [pc, #232] ; (8011078 ) + 8010f8e: f00b f841 bl 801c014 + 8010f92: f06f 030f mvn.w r3, #15 + 8010f96: e067 b.n 8011068 + LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return ERR_ARG;); + 8010f98: 68bb ldr r3, [r7, #8] + 8010f9a: 2b00 cmp r3, #0 + 8010f9c: d109 bne.n 8010fb2 + 8010f9e: 4b34 ldr r3, [pc, #208] ; (8011070 ) + 8010fa0: f240 42b4 movw r2, #1204 ; 0x4b4 + 8010fa4: 4935 ldr r1, [pc, #212] ; (801107c ) + 8010fa6: 4834 ldr r0, [pc, #208] ; (8011078 ) + 8010fa8: f00b f834 bl 801c014 + 8010fac: f06f 030f mvn.w r3, #15 + 8010fb0: e05a b.n 8011068 + LWIP_ERROR("pbuf_take: buf not large enough", (buf->tot_len >= len), return ERR_MEM;); + 8010fb2: 68fb ldr r3, [r7, #12] + 8010fb4: 891b ldrh r3, [r3, #8] + 8010fb6: 88fa ldrh r2, [r7, #6] + 8010fb8: 429a cmp r2, r3 + 8010fba: d909 bls.n 8010fd0 + 8010fbc: 4b2c ldr r3, [pc, #176] ; (8011070 ) + 8010fbe: f240 42b5 movw r2, #1205 ; 0x4b5 + 8010fc2: 492f ldr r1, [pc, #188] ; (8011080 ) + 8010fc4: 482c ldr r0, [pc, #176] ; (8011078 ) + 8010fc6: f00b f825 bl 801c014 + 8010fca: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8010fce: e04b b.n 8011068 + + if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { + 8010fd0: 68fb ldr r3, [r7, #12] + 8010fd2: 2b00 cmp r3, #0 + 8010fd4: d007 beq.n 8010fe6 + 8010fd6: 68bb ldr r3, [r7, #8] + 8010fd8: 2b00 cmp r3, #0 + 8010fda: d004 beq.n 8010fe6 + 8010fdc: 68fb ldr r3, [r7, #12] + 8010fde: 891b ldrh r3, [r3, #8] + 8010fe0: 88fa ldrh r2, [r7, #6] + 8010fe2: 429a cmp r2, r3 + 8010fe4: d902 bls.n 8010fec + return ERR_ARG; + 8010fe6: f06f 030f mvn.w r3, #15 + 8010fea: e03d b.n 8011068 + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for (p = buf; total_copy_len != 0; p = p->next) { + 8010fec: 68fb ldr r3, [r7, #12] + 8010fee: 61fb str r3, [r7, #28] + 8010ff0: e028 b.n 8011044 + LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); + 8010ff2: 69fb ldr r3, [r7, #28] + 8010ff4: 2b00 cmp r3, #0 + 8010ff6: d106 bne.n 8011006 + 8010ff8: 4b1d ldr r3, [pc, #116] ; (8011070 ) + 8010ffa: f240 42bd movw r2, #1213 ; 0x4bd + 8010ffe: 4921 ldr r1, [pc, #132] ; (8011084 ) + 8011000: 481d ldr r0, [pc, #116] ; (8011078 ) + 8011002: f00b f807 bl 801c014 + buf_copy_len = total_copy_len; + 8011006: 697b ldr r3, [r7, #20] + 8011008: 61bb str r3, [r7, #24] + if (buf_copy_len > p->len) { + 801100a: 69fb ldr r3, [r7, #28] + 801100c: 895b ldrh r3, [r3, #10] + 801100e: 461a mov r2, r3 + 8011010: 69bb ldr r3, [r7, #24] + 8011012: 4293 cmp r3, r2 + 8011014: d902 bls.n 801101c + /* this pbuf cannot hold all remaining data */ + buf_copy_len = p->len; + 8011016: 69fb ldr r3, [r7, #28] + 8011018: 895b ldrh r3, [r3, #10] + 801101a: 61bb str r3, [r7, #24] + } + /* copy the necessary parts of the buffer */ + MEMCPY(p->payload, &((const char *)dataptr)[copied_total], buf_copy_len); + 801101c: 69fb ldr r3, [r7, #28] + 801101e: 6858 ldr r0, [r3, #4] + 8011020: 68ba ldr r2, [r7, #8] + 8011022: 693b ldr r3, [r7, #16] + 8011024: 4413 add r3, r2 + 8011026: 69ba ldr r2, [r7, #24] + 8011028: 4619 mov r1, r3 + 801102a: f00a ff2e bl 801be8a + total_copy_len -= buf_copy_len; + 801102e: 697a ldr r2, [r7, #20] + 8011030: 69bb ldr r3, [r7, #24] + 8011032: 1ad3 subs r3, r2, r3 + 8011034: 617b str r3, [r7, #20] + copied_total += buf_copy_len; + 8011036: 693a ldr r2, [r7, #16] + 8011038: 69bb ldr r3, [r7, #24] + 801103a: 4413 add r3, r2 + 801103c: 613b str r3, [r7, #16] + for (p = buf; total_copy_len != 0; p = p->next) { + 801103e: 69fb ldr r3, [r7, #28] + 8011040: 681b ldr r3, [r3, #0] + 8011042: 61fb str r3, [r7, #28] + 8011044: 697b ldr r3, [r7, #20] + 8011046: 2b00 cmp r3, #0 + 8011048: d1d3 bne.n 8010ff2 + } + LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); + 801104a: 697b ldr r3, [r7, #20] + 801104c: 2b00 cmp r3, #0 + 801104e: d103 bne.n 8011058 + 8011050: 88fb ldrh r3, [r7, #6] + 8011052: 693a ldr r2, [r7, #16] + 8011054: 429a cmp r2, r3 + 8011056: d006 beq.n 8011066 + 8011058: 4b05 ldr r3, [pc, #20] ; (8011070 ) + 801105a: f44f 6299 mov.w r2, #1224 ; 0x4c8 + 801105e: 490a ldr r1, [pc, #40] ; (8011088 ) + 8011060: 4805 ldr r0, [pc, #20] ; (8011078 ) + 8011062: f00a ffd7 bl 801c014 + return ERR_OK; + 8011066: 2300 movs r3, #0 +} + 8011068: 4618 mov r0, r3 + 801106a: 3720 adds r7, #32 + 801106c: 46bd mov sp, r7 + 801106e: bd80 pop {r7, pc} + 8011070: 0801f020 .word 0x0801f020 + 8011074: 0801f3f8 .word 0x0801f3f8 + 8011078: 0801f080 .word 0x0801f080 + 801107c: 0801f410 .word 0x0801f410 + 8011080: 0801f42c .word 0x0801f42c + 8011084: 0801f44c .word 0x0801f44c + 8011088: 0801f464 .word 0x0801f464 + +0801108c : + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset) +{ + 801108c: b580 push {r7, lr} + 801108e: b088 sub sp, #32 + 8011090: af00 add r7, sp, #0 + 8011092: 60f8 str r0, [r7, #12] + 8011094: 60b9 str r1, [r7, #8] + 8011096: 4611 mov r1, r2 + 8011098: 461a mov r2, r3 + 801109a: 460b mov r3, r1 + 801109c: 80fb strh r3, [r7, #6] + 801109e: 4613 mov r3, r2 + 80110a0: 80bb strh r3, [r7, #4] + u16_t target_offset; + struct pbuf *q = pbuf_skip(buf, offset, &target_offset); + 80110a2: f107 0210 add.w r2, r7, #16 + 80110a6: 88bb ldrh r3, [r7, #4] + 80110a8: 4619 mov r1, r3 + 80110aa: 68f8 ldr r0, [r7, #12] + 80110ac: f7ff ff49 bl 8010f42 + 80110b0: 61f8 str r0, [r7, #28] + + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->tot_len >= target_offset + len)) { + 80110b2: 69fb ldr r3, [r7, #28] + 80110b4: 2b00 cmp r3, #0 + 80110b6: d047 beq.n 8011148 + 80110b8: 69fb ldr r3, [r7, #28] + 80110ba: 891b ldrh r3, [r3, #8] + 80110bc: 461a mov r2, r3 + 80110be: 8a3b ldrh r3, [r7, #16] + 80110c0: 4619 mov r1, r3 + 80110c2: 88fb ldrh r3, [r7, #6] + 80110c4: 440b add r3, r1 + 80110c6: 429a cmp r2, r3 + 80110c8: db3e blt.n 8011148 + u16_t remaining_len = len; + 80110ca: 88fb ldrh r3, [r7, #6] + 80110cc: 837b strh r3, [r7, #26] + const u8_t *src_ptr = (const u8_t *)dataptr; + 80110ce: 68bb ldr r3, [r7, #8] + 80110d0: 617b str r3, [r7, #20] + /* copy the part that goes into the first pbuf */ + u16_t first_copy_len; + LWIP_ASSERT("check pbuf_skip result", target_offset < q->len); + 80110d2: 69fb ldr r3, [r7, #28] + 80110d4: 895a ldrh r2, [r3, #10] + 80110d6: 8a3b ldrh r3, [r7, #16] + 80110d8: 429a cmp r2, r3 + 80110da: d806 bhi.n 80110ea + 80110dc: 4b1d ldr r3, [pc, #116] ; (8011154 ) + 80110de: f240 42e3 movw r2, #1251 ; 0x4e3 + 80110e2: 491d ldr r1, [pc, #116] ; (8011158 ) + 80110e4: 481d ldr r0, [pc, #116] ; (801115c ) + 80110e6: f00a ff95 bl 801c014 + first_copy_len = (u16_t)LWIP_MIN(q->len - target_offset, len); + 80110ea: 69fb ldr r3, [r7, #28] + 80110ec: 895b ldrh r3, [r3, #10] + 80110ee: 461a mov r2, r3 + 80110f0: 8a3b ldrh r3, [r7, #16] + 80110f2: 1ad2 subs r2, r2, r3 + 80110f4: 88fb ldrh r3, [r7, #6] + 80110f6: 429a cmp r2, r3 + 80110f8: da05 bge.n 8011106 + 80110fa: 69fb ldr r3, [r7, #28] + 80110fc: 895a ldrh r2, [r3, #10] + 80110fe: 8a3b ldrh r3, [r7, #16] + 8011100: 1ad3 subs r3, r2, r3 + 8011102: b29b uxth r3, r3 + 8011104: e000 b.n 8011108 + 8011106: 88fb ldrh r3, [r7, #6] + 8011108: 827b strh r3, [r7, #18] + MEMCPY(((u8_t *)q->payload) + target_offset, dataptr, first_copy_len); + 801110a: 69fb ldr r3, [r7, #28] + 801110c: 685b ldr r3, [r3, #4] + 801110e: 8a3a ldrh r2, [r7, #16] + 8011110: 4413 add r3, r2 + 8011112: 8a7a ldrh r2, [r7, #18] + 8011114: 68b9 ldr r1, [r7, #8] + 8011116: 4618 mov r0, r3 + 8011118: f00a feb7 bl 801be8a + remaining_len = (u16_t)(remaining_len - first_copy_len); + 801111c: 8b7a ldrh r2, [r7, #26] + 801111e: 8a7b ldrh r3, [r7, #18] + 8011120: 1ad3 subs r3, r2, r3 + 8011122: 837b strh r3, [r7, #26] + src_ptr += first_copy_len; + 8011124: 8a7b ldrh r3, [r7, #18] + 8011126: 697a ldr r2, [r7, #20] + 8011128: 4413 add r3, r2 + 801112a: 617b str r3, [r7, #20] + if (remaining_len > 0) { + 801112c: 8b7b ldrh r3, [r7, #26] + 801112e: 2b00 cmp r3, #0 + 8011130: d008 beq.n 8011144 + return pbuf_take(q->next, src_ptr, remaining_len); + 8011132: 69fb ldr r3, [r7, #28] + 8011134: 681b ldr r3, [r3, #0] + 8011136: 8b7a ldrh r2, [r7, #26] + 8011138: 6979 ldr r1, [r7, #20] + 801113a: 4618 mov r0, r3 + 801113c: f7ff ff14 bl 8010f68 + 8011140: 4603 mov r3, r0 + 8011142: e003 b.n 801114c + } + return ERR_OK; + 8011144: 2300 movs r3, #0 + 8011146: e001 b.n 801114c + } + return ERR_MEM; + 8011148: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 801114c: 4618 mov r0, r3 + 801114e: 3720 adds r7, #32 + 8011150: 46bd mov sp, r7 + 8011152: bd80 pop {r7, pc} + 8011154: 0801f020 .word 0x0801f020 + 8011158: 0801f47c .word 0x0801f47c + 801115c: 0801f080 .word 0x0801f080 + +08011160 : + * + * @return a new pbuf or NULL if allocation fails + */ +struct pbuf * +pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p) +{ + 8011160: b580 push {r7, lr} + 8011162: b084 sub sp, #16 + 8011164: af00 add r7, sp, #0 + 8011166: 4603 mov r3, r0 + 8011168: 603a str r2, [r7, #0] + 801116a: 71fb strb r3, [r7, #7] + 801116c: 460b mov r3, r1 + 801116e: 80bb strh r3, [r7, #4] + struct pbuf *q; + err_t err; + q = pbuf_alloc(layer, p->tot_len, type); + 8011170: 683b ldr r3, [r7, #0] + 8011172: 8919 ldrh r1, [r3, #8] + 8011174: 88ba ldrh r2, [r7, #4] + 8011176: 79fb ldrb r3, [r7, #7] + 8011178: 4618 mov r0, r3 + 801117a: f7ff f95d bl 8010438 + 801117e: 60f8 str r0, [r7, #12] + if (q == NULL) { + 8011180: 68fb ldr r3, [r7, #12] + 8011182: 2b00 cmp r3, #0 + 8011184: d101 bne.n 801118a + return NULL; + 8011186: 2300 movs r3, #0 + 8011188: e011 b.n 80111ae + } + err = pbuf_copy(q, p); + 801118a: 6839 ldr r1, [r7, #0] + 801118c: 68f8 ldr r0, [r7, #12] + 801118e: f7ff fd6b bl 8010c68 + 8011192: 4603 mov r3, r0 + 8011194: 72fb strb r3, [r7, #11] + LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); + 8011196: f997 300b ldrsb.w r3, [r7, #11] + 801119a: 2b00 cmp r3, #0 + 801119c: d006 beq.n 80111ac + 801119e: 4b06 ldr r3, [pc, #24] ; (80111b8 ) + 80111a0: f240 5224 movw r2, #1316 ; 0x524 + 80111a4: 4905 ldr r1, [pc, #20] ; (80111bc ) + 80111a6: 4806 ldr r0, [pc, #24] ; (80111c0 ) + 80111a8: f00a ff34 bl 801c014 + return q; + 80111ac: 68fb ldr r3, [r7, #12] +} + 80111ae: 4618 mov r0, r3 + 80111b0: 3710 adds r7, #16 + 80111b2: 46bd mov sp, r7 + 80111b4: bd80 pop {r7, pc} + 80111b6: bf00 nop + 80111b8: 0801f020 .word 0x0801f020 + 80111bc: 0801f494 .word 0x0801f494 + 80111c0: 0801f080 .word 0x0801f080 + +080111c4 : + * @param offset offset into p of the byte to return + * @return byte at an offset into p [0..0xFF] OR negative if 'offset' >= p->tot_len + */ +int +pbuf_try_get_at(const struct pbuf *p, u16_t offset) +{ + 80111c4: b580 push {r7, lr} + 80111c6: b084 sub sp, #16 + 80111c8: af00 add r7, sp, #0 + 80111ca: 6078 str r0, [r7, #4] + 80111cc: 460b mov r3, r1 + 80111ce: 807b strh r3, [r7, #2] + u16_t q_idx; + const struct pbuf *q = pbuf_skip_const(p, offset, &q_idx); + 80111d0: f107 020a add.w r2, r7, #10 + 80111d4: 887b ldrh r3, [r7, #2] + 80111d6: 4619 mov r1, r3 + 80111d8: 6878 ldr r0, [r7, #4] + 80111da: f7ff fe89 bl 8010ef0 + 80111de: 60f8 str r0, [r7, #12] + + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->len > q_idx)) { + 80111e0: 68fb ldr r3, [r7, #12] + 80111e2: 2b00 cmp r3, #0 + 80111e4: d00a beq.n 80111fc + 80111e6: 68fb ldr r3, [r7, #12] + 80111e8: 895a ldrh r2, [r3, #10] + 80111ea: 897b ldrh r3, [r7, #10] + 80111ec: 429a cmp r2, r3 + 80111ee: d905 bls.n 80111fc + return ((u8_t *)q->payload)[q_idx]; + 80111f0: 68fb ldr r3, [r7, #12] + 80111f2: 685b ldr r3, [r3, #4] + 80111f4: 897a ldrh r2, [r7, #10] + 80111f6: 4413 add r3, r2 + 80111f8: 781b ldrb r3, [r3, #0] + 80111fa: e001 b.n 8011200 + } + return -1; + 80111fc: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 8011200: 4618 mov r0, r3 + 8011202: 3710 adds r7, #16 + 8011204: 46bd mov sp, r7 + 8011206: bd80 pop {r7, pc} + +08011208 : + * @param offset offset into p of the byte to write + * @param data byte to write at an offset into p + */ +void +pbuf_put_at(struct pbuf *p, u16_t offset, u8_t data) +{ + 8011208: b580 push {r7, lr} + 801120a: b084 sub sp, #16 + 801120c: af00 add r7, sp, #0 + 801120e: 6078 str r0, [r7, #4] + 8011210: 460b mov r3, r1 + 8011212: 807b strh r3, [r7, #2] + 8011214: 4613 mov r3, r2 + 8011216: 707b strb r3, [r7, #1] + u16_t q_idx; + struct pbuf *q = pbuf_skip(p, offset, &q_idx); + 8011218: f107 020a add.w r2, r7, #10 + 801121c: 887b ldrh r3, [r7, #2] + 801121e: 4619 mov r1, r3 + 8011220: 6878 ldr r0, [r7, #4] + 8011222: f7ff fe8e bl 8010f42 + 8011226: 60f8 str r0, [r7, #12] + + /* write requested data if pbuf is OK */ + if ((q != NULL) && (q->len > q_idx)) { + 8011228: 68fb ldr r3, [r7, #12] + 801122a: 2b00 cmp r3, #0 + 801122c: d00a beq.n 8011244 + 801122e: 68fb ldr r3, [r7, #12] + 8011230: 895a ldrh r2, [r3, #10] + 8011232: 897b ldrh r3, [r7, #10] + 8011234: 429a cmp r2, r3 + 8011236: d905 bls.n 8011244 + ((u8_t *)q->payload)[q_idx] = data; + 8011238: 68fb ldr r3, [r7, #12] + 801123a: 685b ldr r3, [r3, #4] + 801123c: 897a ldrh r2, [r7, #10] + 801123e: 4413 add r3, r2 + 8011240: 787a ldrb r2, [r7, #1] + 8011242: 701a strb r2, [r3, #0] + } +} + 8011244: bf00 nop + 8011246: 3710 adds r7, #16 + 8011248: 46bd mov sp, r7 + 801124a: bd80 pop {r7, pc} + +0801124c : +/** + * Initialize this module. + */ +void +tcp_init(void) +{ + 801124c: b580 push {r7, lr} + 801124e: af00 add r7, sp, #0 +#ifdef LWIP_RAND + tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); + 8011250: f00a ff6e bl 801c130 + 8011254: 4603 mov r3, r0 + 8011256: b29b uxth r3, r3 + 8011258: f3c3 030d ubfx r3, r3, #0, #14 + 801125c: b29b uxth r3, r3 + 801125e: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 + 8011262: b29a uxth r2, r3 + 8011264: 4b01 ldr r3, [pc, #4] ; (801126c ) + 8011266: 801a strh r2, [r3, #0] +#endif /* LWIP_RAND */ +} + 8011268: bf00 nop + 801126a: bd80 pop {r7, pc} + 801126c: 200000b4 .word 0x200000b4 + +08011270 : + +/** Free a tcp pcb */ +void +tcp_free(struct tcp_pcb *pcb) +{ + 8011270: b580 push {r7, lr} + 8011272: b082 sub sp, #8 + 8011274: af00 add r7, sp, #0 + 8011276: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN); + 8011278: 687b ldr r3, [r7, #4] + 801127a: 7d1b ldrb r3, [r3, #20] + 801127c: 2b01 cmp r3, #1 + 801127e: d105 bne.n 801128c + 8011280: 4b06 ldr r3, [pc, #24] ; (801129c ) + 8011282: 22d4 movs r2, #212 ; 0xd4 + 8011284: 4906 ldr r1, [pc, #24] ; (80112a0 ) + 8011286: 4807 ldr r0, [pc, #28] ; (80112a4 ) + 8011288: f00a fec4 bl 801c014 +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB, pcb); + 801128c: 6879 ldr r1, [r7, #4] + 801128e: 2001 movs r0, #1 + 8011290: f7fe fd06 bl 800fca0 +} + 8011294: bf00 nop + 8011296: 3708 adds r7, #8 + 8011298: 46bd mov sp, r7 + 801129a: bd80 pop {r7, pc} + 801129c: 0801f520 .word 0x0801f520 + 80112a0: 0801f550 .word 0x0801f550 + 80112a4: 0801f564 .word 0x0801f564 + +080112a8 : + +/** Free a tcp listen pcb */ +static void +tcp_free_listen(struct tcp_pcb *pcb) +{ + 80112a8: b580 push {r7, lr} + 80112aa: b082 sub sp, #8 + 80112ac: af00 add r7, sp, #0 + 80112ae: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN); + 80112b0: 687b ldr r3, [r7, #4] + 80112b2: 7d1b ldrb r3, [r3, #20] + 80112b4: 2b01 cmp r3, #1 + 80112b6: d105 bne.n 80112c4 + 80112b8: 4b06 ldr r3, [pc, #24] ; (80112d4 ) + 80112ba: 22df movs r2, #223 ; 0xdf + 80112bc: 4906 ldr r1, [pc, #24] ; (80112d8 ) + 80112be: 4807 ldr r0, [pc, #28] ; (80112dc ) + 80112c0: f00a fea8 bl 801c014 +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + 80112c4: 6879 ldr r1, [r7, #4] + 80112c6: 2002 movs r0, #2 + 80112c8: f7fe fcea bl 800fca0 +} + 80112cc: bf00 nop + 80112ce: 3708 adds r7, #8 + 80112d0: 46bd mov sp, r7 + 80112d2: bd80 pop {r7, pc} + 80112d4: 0801f520 .word 0x0801f520 + 80112d8: 0801f58c .word 0x0801f58c + 80112dc: 0801f564 .word 0x0801f564 + +080112e0 : +/** + * Called periodically to dispatch TCP timers. + */ +void +tcp_tmr(void) +{ + 80112e0: b580 push {r7, lr} + 80112e2: af00 add r7, sp, #0 + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + 80112e4: f000 fea2 bl 801202c + + if (++tcp_timer & 1) { + 80112e8: 4b07 ldr r3, [pc, #28] ; (8011308 ) + 80112ea: 781b ldrb r3, [r3, #0] + 80112ec: 3301 adds r3, #1 + 80112ee: b2da uxtb r2, r3 + 80112f0: 4b05 ldr r3, [pc, #20] ; (8011308 ) + 80112f2: 701a strb r2, [r3, #0] + 80112f4: 4b04 ldr r3, [pc, #16] ; (8011308 ) + 80112f6: 781b ldrb r3, [r3, #0] + 80112f8: f003 0301 and.w r3, r3, #1 + 80112fc: 2b00 cmp r3, #0 + 80112fe: d001 beq.n 8011304 + /* Call tcp_slowtmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + 8011300: f000 fb54 bl 80119ac + } +} + 8011304: bf00 nop + 8011306: bd80 pop {r7, pc} + 8011308: 2000cf45 .word 0x2000cf45 + +0801130c : +/** Called when a listen pcb is closed. Iterates one pcb list and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb) +{ + 801130c: b580 push {r7, lr} + 801130e: b084 sub sp, #16 + 8011310: af00 add r7, sp, #0 + 8011312: 6078 str r0, [r7, #4] + 8011314: 6039 str r1, [r7, #0] + struct tcp_pcb *pcb; + + LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL); + 8011316: 683b ldr r3, [r7, #0] + 8011318: 2b00 cmp r3, #0 + 801131a: d105 bne.n 8011328 + 801131c: 4b0d ldr r3, [pc, #52] ; (8011354 ) + 801131e: 22ff movs r2, #255 ; 0xff + 8011320: 490d ldr r1, [pc, #52] ; (8011358 ) + 8011322: 480e ldr r0, [pc, #56] ; (801135c ) + 8011324: f00a fe76 bl 801c014 + + for (pcb = list; pcb != NULL; pcb = pcb->next) { + 8011328: 687b ldr r3, [r7, #4] + 801132a: 60fb str r3, [r7, #12] + 801132c: e00a b.n 8011344 + if (pcb->listener == lpcb) { + 801132e: 68fb ldr r3, [r7, #12] + 8011330: 6fdb ldr r3, [r3, #124] ; 0x7c + 8011332: 683a ldr r2, [r7, #0] + 8011334: 429a cmp r2, r3 + 8011336: d102 bne.n 801133e + pcb->listener = NULL; + 8011338: 68fb ldr r3, [r7, #12] + 801133a: 2200 movs r2, #0 + 801133c: 67da str r2, [r3, #124] ; 0x7c + for (pcb = list; pcb != NULL; pcb = pcb->next) { + 801133e: 68fb ldr r3, [r7, #12] + 8011340: 68db ldr r3, [r3, #12] + 8011342: 60fb str r3, [r7, #12] + 8011344: 68fb ldr r3, [r7, #12] + 8011346: 2b00 cmp r3, #0 + 8011348: d1f1 bne.n 801132e + } + } +} + 801134a: bf00 nop + 801134c: bf00 nop + 801134e: 3710 adds r7, #16 + 8011350: 46bd mov sp, r7 + 8011352: bd80 pop {r7, pc} + 8011354: 0801f520 .word 0x0801f520 + 8011358: 0801f5a8 .word 0x0801f5a8 + 801135c: 0801f564 .word 0x0801f564 + +08011360 : +/** Called when a listen pcb is closed. Iterates all pcb lists and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_listen_closed(struct tcp_pcb *pcb) +{ + 8011360: b580 push {r7, lr} + 8011362: b084 sub sp, #16 + 8011364: af00 add r7, sp, #0 + 8011366: 6078 str r0, [r7, #4] +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + size_t i; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + 8011368: 687b ldr r3, [r7, #4] + 801136a: 2b00 cmp r3, #0 + 801136c: d106 bne.n 801137c + 801136e: 4b14 ldr r3, [pc, #80] ; (80113c0 ) + 8011370: f240 1211 movw r2, #273 ; 0x111 + 8011374: 4913 ldr r1, [pc, #76] ; (80113c4 ) + 8011376: 4814 ldr r0, [pc, #80] ; (80113c8 ) + 8011378: f00a fe4c bl 801c014 + LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN); + 801137c: 687b ldr r3, [r7, #4] + 801137e: 7d1b ldrb r3, [r3, #20] + 8011380: 2b01 cmp r3, #1 + 8011382: d006 beq.n 8011392 + 8011384: 4b0e ldr r3, [pc, #56] ; (80113c0 ) + 8011386: f44f 7289 mov.w r2, #274 ; 0x112 + 801138a: 4910 ldr r1, [pc, #64] ; (80113cc ) + 801138c: 480e ldr r0, [pc, #56] ; (80113c8 ) + 801138e: f00a fe41 bl 801c014 + for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { + 8011392: 2301 movs r3, #1 + 8011394: 60fb str r3, [r7, #12] + 8011396: e00b b.n 80113b0 + tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb); + 8011398: 4a0d ldr r2, [pc, #52] ; (80113d0 ) + 801139a: 68fb ldr r3, [r7, #12] + 801139c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80113a0: 681b ldr r3, [r3, #0] + 80113a2: 6879 ldr r1, [r7, #4] + 80113a4: 4618 mov r0, r3 + 80113a6: f7ff ffb1 bl 801130c + for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { + 80113aa: 68fb ldr r3, [r7, #12] + 80113ac: 3301 adds r3, #1 + 80113ae: 60fb str r3, [r7, #12] + 80113b0: 68fb ldr r3, [r7, #12] + 80113b2: 2b03 cmp r3, #3 + 80113b4: d9f0 bls.n 8011398 + } +#endif + LWIP_UNUSED_ARG(pcb); +} + 80113b6: bf00 nop + 80113b8: bf00 nop + 80113ba: 3710 adds r7, #16 + 80113bc: 46bd mov sp, r7 + 80113be: bd80 pop {r7, pc} + 80113c0: 0801f520 .word 0x0801f520 + 80113c4: 0801f5d0 .word 0x0801f5d0 + 80113c8: 0801f564 .word 0x0801f564 + 80113cc: 0801f5dc .word 0x0801f5dc + 80113d0: 080238d4 .word 0x080238d4 + +080113d4 : + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +static err_t +tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) +{ + 80113d4: b5b0 push {r4, r5, r7, lr} + 80113d6: b088 sub sp, #32 + 80113d8: af04 add r7, sp, #16 + 80113da: 6078 str r0, [r7, #4] + 80113dc: 460b mov r3, r1 + 80113de: 70fb strb r3, [r7, #3] + LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL); + 80113e0: 687b ldr r3, [r7, #4] + 80113e2: 2b00 cmp r3, #0 + 80113e4: d106 bne.n 80113f4 + 80113e6: 4b63 ldr r3, [pc, #396] ; (8011574 ) + 80113e8: f44f 72af mov.w r2, #350 ; 0x15e + 80113ec: 4962 ldr r1, [pc, #392] ; (8011578 ) + 80113ee: 4863 ldr r0, [pc, #396] ; (801157c ) + 80113f0: f00a fe10 bl 801c014 + + if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + 80113f4: 78fb ldrb r3, [r7, #3] + 80113f6: 2b00 cmp r3, #0 + 80113f8: d066 beq.n 80114c8 + 80113fa: 687b ldr r3, [r7, #4] + 80113fc: 7d1b ldrb r3, [r3, #20] + 80113fe: 2b04 cmp r3, #4 + 8011400: d003 beq.n 801140a + 8011402: 687b ldr r3, [r7, #4] + 8011404: 7d1b ldrb r3, [r3, #20] + 8011406: 2b07 cmp r3, #7 + 8011408: d15e bne.n 80114c8 + if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) { + 801140a: 687b ldr r3, [r7, #4] + 801140c: 6f9b ldr r3, [r3, #120] ; 0x78 + 801140e: 2b00 cmp r3, #0 + 8011410: d104 bne.n 801141c + 8011412: 687b ldr r3, [r7, #4] + 8011414: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8011416: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 801141a: d055 beq.n 80114c8 + /* Not all data received by application, send RST to tell the remote + side about this. */ + LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); + 801141c: 687b ldr r3, [r7, #4] + 801141e: 8b5b ldrh r3, [r3, #26] + 8011420: f003 0310 and.w r3, r3, #16 + 8011424: 2b00 cmp r3, #0 + 8011426: d106 bne.n 8011436 + 8011428: 4b52 ldr r3, [pc, #328] ; (8011574 ) + 801142a: f44f 72b2 mov.w r2, #356 ; 0x164 + 801142e: 4954 ldr r1, [pc, #336] ; (8011580 ) + 8011430: 4852 ldr r0, [pc, #328] ; (801157c ) + 8011432: f00a fdef bl 801c014 + + /* don't call tcp_abort here: we must not deallocate the pcb since + that might not be expected when calling tcp_close */ + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + 8011436: 687b ldr r3, [r7, #4] + 8011438: 6d18 ldr r0, [r3, #80] ; 0x50 + 801143a: 687b ldr r3, [r7, #4] + 801143c: 6a5c ldr r4, [r3, #36] ; 0x24 + 801143e: 687d ldr r5, [r7, #4] + 8011440: 687b ldr r3, [r7, #4] + 8011442: 3304 adds r3, #4 + 8011444: 687a ldr r2, [r7, #4] + 8011446: 8ad2 ldrh r2, [r2, #22] + 8011448: 6879 ldr r1, [r7, #4] + 801144a: 8b09 ldrh r1, [r1, #24] + 801144c: 9102 str r1, [sp, #8] + 801144e: 9201 str r2, [sp, #4] + 8011450: 9300 str r3, [sp, #0] + 8011452: 462b mov r3, r5 + 8011454: 4622 mov r2, r4 + 8011456: 4601 mov r1, r0 + 8011458: 6878 ldr r0, [r7, #4] + 801145a: f004 fe91 bl 8016180 + pcb->local_port, pcb->remote_port); + + tcp_pcb_purge(pcb); + 801145e: 6878 ldr r0, [r7, #4] + 8011460: f001 f8c6 bl 80125f0 + TCP_RMV_ACTIVE(pcb); + 8011464: 4b47 ldr r3, [pc, #284] ; (8011584 ) + 8011466: 681b ldr r3, [r3, #0] + 8011468: 687a ldr r2, [r7, #4] + 801146a: 429a cmp r2, r3 + 801146c: d105 bne.n 801147a + 801146e: 4b45 ldr r3, [pc, #276] ; (8011584 ) + 8011470: 681b ldr r3, [r3, #0] + 8011472: 68db ldr r3, [r3, #12] + 8011474: 4a43 ldr r2, [pc, #268] ; (8011584 ) + 8011476: 6013 str r3, [r2, #0] + 8011478: e013 b.n 80114a2 + 801147a: 4b42 ldr r3, [pc, #264] ; (8011584 ) + 801147c: 681b ldr r3, [r3, #0] + 801147e: 60fb str r3, [r7, #12] + 8011480: e00c b.n 801149c + 8011482: 68fb ldr r3, [r7, #12] + 8011484: 68db ldr r3, [r3, #12] + 8011486: 687a ldr r2, [r7, #4] + 8011488: 429a cmp r2, r3 + 801148a: d104 bne.n 8011496 + 801148c: 687b ldr r3, [r7, #4] + 801148e: 68da ldr r2, [r3, #12] + 8011490: 68fb ldr r3, [r7, #12] + 8011492: 60da str r2, [r3, #12] + 8011494: e005 b.n 80114a2 + 8011496: 68fb ldr r3, [r7, #12] + 8011498: 68db ldr r3, [r3, #12] + 801149a: 60fb str r3, [r7, #12] + 801149c: 68fb ldr r3, [r7, #12] + 801149e: 2b00 cmp r3, #0 + 80114a0: d1ef bne.n 8011482 + 80114a2: 687b ldr r3, [r7, #4] + 80114a4: 2200 movs r2, #0 + 80114a6: 60da str r2, [r3, #12] + 80114a8: 4b37 ldr r3, [pc, #220] ; (8011588 ) + 80114aa: 2201 movs r2, #1 + 80114ac: 701a strb r2, [r3, #0] + /* Deallocate the pcb since we already sent a RST for it */ + if (tcp_input_pcb == pcb) { + 80114ae: 4b37 ldr r3, [pc, #220] ; (801158c ) + 80114b0: 681b ldr r3, [r3, #0] + 80114b2: 687a ldr r2, [r7, #4] + 80114b4: 429a cmp r2, r3 + 80114b6: d102 bne.n 80114be + /* prevent using a deallocated pcb: free it from tcp_input later */ + tcp_trigger_input_pcb_close(); + 80114b8: f003 fd5e bl 8014f78 + 80114bc: e002 b.n 80114c4 + } else { + tcp_free(pcb); + 80114be: 6878 ldr r0, [r7, #4] + 80114c0: f7ff fed6 bl 8011270 + } + return ERR_OK; + 80114c4: 2300 movs r3, #0 + 80114c6: e050 b.n 801156a + } + } + + /* - states which free the pcb are handled here, + - states which send FIN and change state are handled in tcp_close_shutdown_fin() */ + switch (pcb->state) { + 80114c8: 687b ldr r3, [r7, #4] + 80114ca: 7d1b ldrb r3, [r3, #20] + 80114cc: 2b02 cmp r3, #2 + 80114ce: d03b beq.n 8011548 + 80114d0: 2b02 cmp r3, #2 + 80114d2: dc44 bgt.n 801155e + 80114d4: 2b00 cmp r3, #0 + 80114d6: d002 beq.n 80114de + 80114d8: 2b01 cmp r3, #1 + 80114da: d02a beq.n 8011532 + 80114dc: e03f b.n 801155e + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + if (pcb->local_port != 0) { + 80114de: 687b ldr r3, [r7, #4] + 80114e0: 8adb ldrh r3, [r3, #22] + 80114e2: 2b00 cmp r3, #0 + 80114e4: d021 beq.n 801152a + TCP_RMV(&tcp_bound_pcbs, pcb); + 80114e6: 4b2a ldr r3, [pc, #168] ; (8011590 ) + 80114e8: 681b ldr r3, [r3, #0] + 80114ea: 687a ldr r2, [r7, #4] + 80114ec: 429a cmp r2, r3 + 80114ee: d105 bne.n 80114fc + 80114f0: 4b27 ldr r3, [pc, #156] ; (8011590 ) + 80114f2: 681b ldr r3, [r3, #0] + 80114f4: 68db ldr r3, [r3, #12] + 80114f6: 4a26 ldr r2, [pc, #152] ; (8011590 ) + 80114f8: 6013 str r3, [r2, #0] + 80114fa: e013 b.n 8011524 + 80114fc: 4b24 ldr r3, [pc, #144] ; (8011590 ) + 80114fe: 681b ldr r3, [r3, #0] + 8011500: 60bb str r3, [r7, #8] + 8011502: e00c b.n 801151e + 8011504: 68bb ldr r3, [r7, #8] + 8011506: 68db ldr r3, [r3, #12] + 8011508: 687a ldr r2, [r7, #4] + 801150a: 429a cmp r2, r3 + 801150c: d104 bne.n 8011518 + 801150e: 687b ldr r3, [r7, #4] + 8011510: 68da ldr r2, [r3, #12] + 8011512: 68bb ldr r3, [r7, #8] + 8011514: 60da str r2, [r3, #12] + 8011516: e005 b.n 8011524 + 8011518: 68bb ldr r3, [r7, #8] + 801151a: 68db ldr r3, [r3, #12] + 801151c: 60bb str r3, [r7, #8] + 801151e: 68bb ldr r3, [r7, #8] + 8011520: 2b00 cmp r3, #0 + 8011522: d1ef bne.n 8011504 + 8011524: 687b ldr r3, [r7, #4] + 8011526: 2200 movs r2, #0 + 8011528: 60da str r2, [r3, #12] + } + tcp_free(pcb); + 801152a: 6878 ldr r0, [r7, #4] + 801152c: f7ff fea0 bl 8011270 + break; + 8011530: e01a b.n 8011568 + case LISTEN: + tcp_listen_closed(pcb); + 8011532: 6878 ldr r0, [r7, #4] + 8011534: f7ff ff14 bl 8011360 + tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); + 8011538: 6879 ldr r1, [r7, #4] + 801153a: 4816 ldr r0, [pc, #88] ; (8011594 ) + 801153c: f001 f8a8 bl 8012690 + tcp_free_listen(pcb); + 8011540: 6878 ldr r0, [r7, #4] + 8011542: f7ff feb1 bl 80112a8 + break; + 8011546: e00f b.n 8011568 + case SYN_SENT: + TCP_PCB_REMOVE_ACTIVE(pcb); + 8011548: 6879 ldr r1, [r7, #4] + 801154a: 480e ldr r0, [pc, #56] ; (8011584 ) + 801154c: f001 f8a0 bl 8012690 + 8011550: 4b0d ldr r3, [pc, #52] ; (8011588 ) + 8011552: 2201 movs r2, #1 + 8011554: 701a strb r2, [r3, #0] + tcp_free(pcb); + 8011556: 6878 ldr r0, [r7, #4] + 8011558: f7ff fe8a bl 8011270 + MIB2_STATS_INC(mib2.tcpattemptfails); + break; + 801155c: e004 b.n 8011568 + default: + return tcp_close_shutdown_fin(pcb); + 801155e: 6878 ldr r0, [r7, #4] + 8011560: f000 f81a bl 8011598 + 8011564: 4603 mov r3, r0 + 8011566: e000 b.n 801156a + } + return ERR_OK; + 8011568: 2300 movs r3, #0 +} + 801156a: 4618 mov r0, r3 + 801156c: 3710 adds r7, #16 + 801156e: 46bd mov sp, r7 + 8011570: bdb0 pop {r4, r5, r7, pc} + 8011572: bf00 nop + 8011574: 0801f520 .word 0x0801f520 + 8011578: 0801f5f4 .word 0x0801f5f4 + 801157c: 0801f564 .word 0x0801f564 + 8011580: 0801f614 .word 0x0801f614 + 8011584: 2000cf3c .word 0x2000cf3c + 8011588: 2000cf44 .word 0x2000cf44 + 801158c: 2000cf7c .word 0x2000cf7c + 8011590: 2000cf34 .word 0x2000cf34 + 8011594: 2000cf38 .word 0x2000cf38 + +08011598 : + +static err_t +tcp_close_shutdown_fin(struct tcp_pcb *pcb) +{ + 8011598: b580 push {r7, lr} + 801159a: b084 sub sp, #16 + 801159c: af00 add r7, sp, #0 + 801159e: 6078 str r0, [r7, #4] + err_t err; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + 80115a0: 687b ldr r3, [r7, #4] + 80115a2: 2b00 cmp r3, #0 + 80115a4: d106 bne.n 80115b4 + 80115a6: 4b2e ldr r3, [pc, #184] ; (8011660 ) + 80115a8: f44f 72ce mov.w r2, #412 ; 0x19c + 80115ac: 492d ldr r1, [pc, #180] ; (8011664 ) + 80115ae: 482e ldr r0, [pc, #184] ; (8011668 ) + 80115b0: f00a fd30 bl 801c014 + + switch (pcb->state) { + 80115b4: 687b ldr r3, [r7, #4] + 80115b6: 7d1b ldrb r3, [r3, #20] + 80115b8: 2b07 cmp r3, #7 + 80115ba: d020 beq.n 80115fe + 80115bc: 2b07 cmp r3, #7 + 80115be: dc2b bgt.n 8011618 + 80115c0: 2b03 cmp r3, #3 + 80115c2: d002 beq.n 80115ca + 80115c4: 2b04 cmp r3, #4 + 80115c6: d00d beq.n 80115e4 + 80115c8: e026 b.n 8011618 + case SYN_RCVD: + err = tcp_send_fin(pcb); + 80115ca: 6878 ldr r0, [r7, #4] + 80115cc: f003 fee6 bl 801539c + 80115d0: 4603 mov r3, r0 + 80115d2: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 80115d4: f997 300f ldrsb.w r3, [r7, #15] + 80115d8: 2b00 cmp r3, #0 + 80115da: d11f bne.n 801161c + tcp_backlog_accepted(pcb); + MIB2_STATS_INC(mib2.tcpattemptfails); + pcb->state = FIN_WAIT_1; + 80115dc: 687b ldr r3, [r7, #4] + 80115de: 2205 movs r2, #5 + 80115e0: 751a strb r2, [r3, #20] + } + break; + 80115e2: e01b b.n 801161c + case ESTABLISHED: + err = tcp_send_fin(pcb); + 80115e4: 6878 ldr r0, [r7, #4] + 80115e6: f003 fed9 bl 801539c + 80115ea: 4603 mov r3, r0 + 80115ec: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 80115ee: f997 300f ldrsb.w r3, [r7, #15] + 80115f2: 2b00 cmp r3, #0 + 80115f4: d114 bne.n 8011620 + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = FIN_WAIT_1; + 80115f6: 687b ldr r3, [r7, #4] + 80115f8: 2205 movs r2, #5 + 80115fa: 751a strb r2, [r3, #20] + } + break; + 80115fc: e010 b.n 8011620 + case CLOSE_WAIT: + err = tcp_send_fin(pcb); + 80115fe: 6878 ldr r0, [r7, #4] + 8011600: f003 fecc bl 801539c + 8011604: 4603 mov r3, r0 + 8011606: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 8011608: f997 300f ldrsb.w r3, [r7, #15] + 801160c: 2b00 cmp r3, #0 + 801160e: d109 bne.n 8011624 + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = LAST_ACK; + 8011610: 687b ldr r3, [r7, #4] + 8011612: 2209 movs r2, #9 + 8011614: 751a strb r2, [r3, #20] + } + break; + 8011616: e005 b.n 8011624 + default: + /* Has already been closed, do nothing. */ + return ERR_OK; + 8011618: 2300 movs r3, #0 + 801161a: e01c b.n 8011656 + break; + 801161c: bf00 nop + 801161e: e002 b.n 8011626 + break; + 8011620: bf00 nop + 8011622: e000 b.n 8011626 + break; + 8011624: bf00 nop + } + + if (err == ERR_OK) { + 8011626: f997 300f ldrsb.w r3, [r7, #15] + 801162a: 2b00 cmp r3, #0 + 801162c: d103 bne.n 8011636 + /* To ensure all data has been sent when tcp_close returns, we have + to make sure tcp_output doesn't fail. + Since we don't really have to ensure all data has been sent when tcp_close + returns (unsent data is sent from tcp timer functions, also), we don't care + for the return value of tcp_output for now. */ + tcp_output(pcb); + 801162e: 6878 ldr r0, [r7, #4] + 8011630: f003 fff2 bl 8015618 + 8011634: e00d b.n 8011652 + } else if (err == ERR_MEM) { + 8011636: f997 300f ldrsb.w r3, [r7, #15] + 801163a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 801163e: d108 bne.n 8011652 + /* Mark this pcb for closing. Closing is retried from tcp_tmr. */ + tcp_set_flags(pcb, TF_CLOSEPEND); + 8011640: 687b ldr r3, [r7, #4] + 8011642: 8b5b ldrh r3, [r3, #26] + 8011644: f043 0308 orr.w r3, r3, #8 + 8011648: b29a uxth r2, r3 + 801164a: 687b ldr r3, [r7, #4] + 801164c: 835a strh r2, [r3, #26] + /* We have to return ERR_OK from here to indicate to the callers that this + pcb should not be used any more as it will be freed soon via tcp_tmr. + This is OK here since sending FIN does not guarantee a time frime for + actually freeing the pcb, either (it is left in closure states for + remote ACK or timeout) */ + return ERR_OK; + 801164e: 2300 movs r3, #0 + 8011650: e001 b.n 8011656 + } + return err; + 8011652: f997 300f ldrsb.w r3, [r7, #15] +} + 8011656: 4618 mov r0, r3 + 8011658: 3710 adds r7, #16 + 801165a: 46bd mov sp, r7 + 801165c: bd80 pop {r7, pc} + 801165e: bf00 nop + 8011660: 0801f520 .word 0x0801f520 + 8011664: 0801f5d0 .word 0x0801f5d0 + 8011668: 0801f564 .word 0x0801f564 + +0801166c : + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + 801166c: b580 push {r7, lr} + 801166e: b082 sub sp, #8 + 8011670: af00 add r7, sp, #0 + 8011672: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG); + 8011674: 687b ldr r3, [r7, #4] + 8011676: 2b00 cmp r3, #0 + 8011678: d109 bne.n 801168e + 801167a: 4b0f ldr r3, [pc, #60] ; (80116b8 ) + 801167c: f44f 72f4 mov.w r2, #488 ; 0x1e8 + 8011680: 490e ldr r1, [pc, #56] ; (80116bc ) + 8011682: 480f ldr r0, [pc, #60] ; (80116c0 ) + 8011684: f00a fcc6 bl 801c014 + 8011688: f06f 030f mvn.w r3, #15 + 801168c: e00f b.n 80116ae + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + + tcp_debug_print_state(pcb->state); + + if (pcb->state != LISTEN) { + 801168e: 687b ldr r3, [r7, #4] + 8011690: 7d1b ldrb r3, [r3, #20] + 8011692: 2b01 cmp r3, #1 + 8011694: d006 beq.n 80116a4 + /* Set a flag not to receive any more data... */ + tcp_set_flags(pcb, TF_RXCLOSED); + 8011696: 687b ldr r3, [r7, #4] + 8011698: 8b5b ldrh r3, [r3, #26] + 801169a: f043 0310 orr.w r3, r3, #16 + 801169e: b29a uxth r2, r3 + 80116a0: 687b ldr r3, [r7, #4] + 80116a2: 835a strh r2, [r3, #26] + } + /* ... and close */ + return tcp_close_shutdown(pcb, 1); + 80116a4: 2101 movs r1, #1 + 80116a6: 6878 ldr r0, [r7, #4] + 80116a8: f7ff fe94 bl 80113d4 + 80116ac: 4603 mov r3, r0 +} + 80116ae: 4618 mov r0, r3 + 80116b0: 3708 adds r7, #8 + 80116b2: 46bd mov sp, r7 + 80116b4: bd80 pop {r7, pc} + 80116b6: bf00 nop + 80116b8: 0801f520 .word 0x0801f520 + 80116bc: 0801f630 .word 0x0801f630 + 80116c0: 0801f564 .word 0x0801f564 + +080116c4 : + * @param pcb the tcp_pcb to abort + * @param reset boolean to indicate whether a reset should be sent + */ +void +tcp_abandon(struct tcp_pcb *pcb, int reset) +{ + 80116c4: b580 push {r7, lr} + 80116c6: b08e sub sp, #56 ; 0x38 + 80116c8: af04 add r7, sp, #16 + 80116ca: 6078 str r0, [r7, #4] + 80116cc: 6039 str r1, [r7, #0] +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return); + 80116ce: 687b ldr r3, [r7, #4] + 80116d0: 2b00 cmp r3, #0 + 80116d2: d107 bne.n 80116e4 + 80116d4: 4b52 ldr r3, [pc, #328] ; (8011820 ) + 80116d6: f240 223d movw r2, #573 ; 0x23d + 80116da: 4952 ldr r1, [pc, #328] ; (8011824 ) + 80116dc: 4852 ldr r0, [pc, #328] ; (8011828 ) + 80116de: f00a fc99 bl 801c014 + 80116e2: e099 b.n 8011818 + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", + 80116e4: 687b ldr r3, [r7, #4] + 80116e6: 7d1b ldrb r3, [r3, #20] + 80116e8: 2b01 cmp r3, #1 + 80116ea: d106 bne.n 80116fa + 80116ec: 4b4c ldr r3, [pc, #304] ; (8011820 ) + 80116ee: f44f 7210 mov.w r2, #576 ; 0x240 + 80116f2: 494e ldr r1, [pc, #312] ; (801182c ) + 80116f4: 484c ldr r0, [pc, #304] ; (8011828 ) + 80116f6: f00a fc8d bl 801c014 + pcb->state != LISTEN); + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + 80116fa: 687b ldr r3, [r7, #4] + 80116fc: 7d1b ldrb r3, [r3, #20] + 80116fe: 2b0a cmp r3, #10 + 8011700: d107 bne.n 8011712 + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + 8011702: 6879 ldr r1, [r7, #4] + 8011704: 484a ldr r0, [pc, #296] ; (8011830 ) + 8011706: f000 ffc3 bl 8012690 + tcp_free(pcb); + 801170a: 6878 ldr r0, [r7, #4] + 801170c: f7ff fdb0 bl 8011270 + 8011710: e082 b.n 8011818 + } else { + int send_rst = 0; + 8011712: 2300 movs r3, #0 + 8011714: 627b str r3, [r7, #36] ; 0x24 + u16_t local_port = 0; + 8011716: 2300 movs r3, #0 + 8011718: 847b strh r3, [r7, #34] ; 0x22 + enum tcp_state last_state; + seqno = pcb->snd_nxt; + 801171a: 687b ldr r3, [r7, #4] + 801171c: 6d1b ldr r3, [r3, #80] ; 0x50 + 801171e: 61bb str r3, [r7, #24] + ackno = pcb->rcv_nxt; + 8011720: 687b ldr r3, [r7, #4] + 8011722: 6a5b ldr r3, [r3, #36] ; 0x24 + 8011724: 617b str r3, [r7, #20] +#if LWIP_CALLBACK_API + errf = pcb->errf; + 8011726: 687b ldr r3, [r7, #4] + 8011728: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 801172c: 613b str r3, [r7, #16] +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + 801172e: 687b ldr r3, [r7, #4] + 8011730: 691b ldr r3, [r3, #16] + 8011732: 60fb str r3, [r7, #12] + if (pcb->state == CLOSED) { + 8011734: 687b ldr r3, [r7, #4] + 8011736: 7d1b ldrb r3, [r3, #20] + 8011738: 2b00 cmp r3, #0 + 801173a: d126 bne.n 801178a + if (pcb->local_port != 0) { + 801173c: 687b ldr r3, [r7, #4] + 801173e: 8adb ldrh r3, [r3, #22] + 8011740: 2b00 cmp r3, #0 + 8011742: d02e beq.n 80117a2 + /* bound, not yet opened */ + TCP_RMV(&tcp_bound_pcbs, pcb); + 8011744: 4b3b ldr r3, [pc, #236] ; (8011834 ) + 8011746: 681b ldr r3, [r3, #0] + 8011748: 687a ldr r2, [r7, #4] + 801174a: 429a cmp r2, r3 + 801174c: d105 bne.n 801175a + 801174e: 4b39 ldr r3, [pc, #228] ; (8011834 ) + 8011750: 681b ldr r3, [r3, #0] + 8011752: 68db ldr r3, [r3, #12] + 8011754: 4a37 ldr r2, [pc, #220] ; (8011834 ) + 8011756: 6013 str r3, [r2, #0] + 8011758: e013 b.n 8011782 + 801175a: 4b36 ldr r3, [pc, #216] ; (8011834 ) + 801175c: 681b ldr r3, [r3, #0] + 801175e: 61fb str r3, [r7, #28] + 8011760: e00c b.n 801177c + 8011762: 69fb ldr r3, [r7, #28] + 8011764: 68db ldr r3, [r3, #12] + 8011766: 687a ldr r2, [r7, #4] + 8011768: 429a cmp r2, r3 + 801176a: d104 bne.n 8011776 + 801176c: 687b ldr r3, [r7, #4] + 801176e: 68da ldr r2, [r3, #12] + 8011770: 69fb ldr r3, [r7, #28] + 8011772: 60da str r2, [r3, #12] + 8011774: e005 b.n 8011782 + 8011776: 69fb ldr r3, [r7, #28] + 8011778: 68db ldr r3, [r3, #12] + 801177a: 61fb str r3, [r7, #28] + 801177c: 69fb ldr r3, [r7, #28] + 801177e: 2b00 cmp r3, #0 + 8011780: d1ef bne.n 8011762 + 8011782: 687b ldr r3, [r7, #4] + 8011784: 2200 movs r2, #0 + 8011786: 60da str r2, [r3, #12] + 8011788: e00b b.n 80117a2 + } + } else { + send_rst = reset; + 801178a: 683b ldr r3, [r7, #0] + 801178c: 627b str r3, [r7, #36] ; 0x24 + local_port = pcb->local_port; + 801178e: 687b ldr r3, [r7, #4] + 8011790: 8adb ldrh r3, [r3, #22] + 8011792: 847b strh r3, [r7, #34] ; 0x22 + TCP_PCB_REMOVE_ACTIVE(pcb); + 8011794: 6879 ldr r1, [r7, #4] + 8011796: 4828 ldr r0, [pc, #160] ; (8011838 ) + 8011798: f000 ff7a bl 8012690 + 801179c: 4b27 ldr r3, [pc, #156] ; (801183c ) + 801179e: 2201 movs r2, #1 + 80117a0: 701a strb r2, [r3, #0] + } + if (pcb->unacked != NULL) { + 80117a2: 687b ldr r3, [r7, #4] + 80117a4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80117a6: 2b00 cmp r3, #0 + 80117a8: d004 beq.n 80117b4 + tcp_segs_free(pcb->unacked); + 80117aa: 687b ldr r3, [r7, #4] + 80117ac: 6f1b ldr r3, [r3, #112] ; 0x70 + 80117ae: 4618 mov r0, r3 + 80117b0: f000 fd1c bl 80121ec + } + if (pcb->unsent != NULL) { + 80117b4: 687b ldr r3, [r7, #4] + 80117b6: 6edb ldr r3, [r3, #108] ; 0x6c + 80117b8: 2b00 cmp r3, #0 + 80117ba: d004 beq.n 80117c6 + tcp_segs_free(pcb->unsent); + 80117bc: 687b ldr r3, [r7, #4] + 80117be: 6edb ldr r3, [r3, #108] ; 0x6c + 80117c0: 4618 mov r0, r3 + 80117c2: f000 fd13 bl 80121ec + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + 80117c6: 687b ldr r3, [r7, #4] + 80117c8: 6f5b ldr r3, [r3, #116] ; 0x74 + 80117ca: 2b00 cmp r3, #0 + 80117cc: d004 beq.n 80117d8 + tcp_segs_free(pcb->ooseq); + 80117ce: 687b ldr r3, [r7, #4] + 80117d0: 6f5b ldr r3, [r3, #116] ; 0x74 + 80117d2: 4618 mov r0, r3 + 80117d4: f000 fd0a bl 80121ec + } +#endif /* TCP_QUEUE_OOSEQ */ + tcp_backlog_accepted(pcb); + if (send_rst) { + 80117d8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80117da: 2b00 cmp r3, #0 + 80117dc: d00e beq.n 80117fc + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); + tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port); + 80117de: 6879 ldr r1, [r7, #4] + 80117e0: 687b ldr r3, [r7, #4] + 80117e2: 3304 adds r3, #4 + 80117e4: 687a ldr r2, [r7, #4] + 80117e6: 8b12 ldrh r2, [r2, #24] + 80117e8: 9202 str r2, [sp, #8] + 80117ea: 8c7a ldrh r2, [r7, #34] ; 0x22 + 80117ec: 9201 str r2, [sp, #4] + 80117ee: 9300 str r3, [sp, #0] + 80117f0: 460b mov r3, r1 + 80117f2: 697a ldr r2, [r7, #20] + 80117f4: 69b9 ldr r1, [r7, #24] + 80117f6: 6878 ldr r0, [r7, #4] + 80117f8: f004 fcc2 bl 8016180 + } + last_state = pcb->state; + 80117fc: 687b ldr r3, [r7, #4] + 80117fe: 7d1b ldrb r3, [r3, #20] + 8011800: 72fb strb r3, [r7, #11] + tcp_free(pcb); + 8011802: 6878 ldr r0, [r7, #4] + 8011804: f7ff fd34 bl 8011270 + TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT); + 8011808: 693b ldr r3, [r7, #16] + 801180a: 2b00 cmp r3, #0 + 801180c: d004 beq.n 8011818 + 801180e: 693b ldr r3, [r7, #16] + 8011810: f06f 010c mvn.w r1, #12 + 8011814: 68f8 ldr r0, [r7, #12] + 8011816: 4798 blx r3 + } +} + 8011818: 3728 adds r7, #40 ; 0x28 + 801181a: 46bd mov sp, r7 + 801181c: bd80 pop {r7, pc} + 801181e: bf00 nop + 8011820: 0801f520 .word 0x0801f520 + 8011824: 0801f664 .word 0x0801f664 + 8011828: 0801f564 .word 0x0801f564 + 801182c: 0801f680 .word 0x0801f680 + 8011830: 2000cf40 .word 0x2000cf40 + 8011834: 2000cf34 .word 0x2000cf34 + 8011838: 2000cf3c .word 0x2000cf3c + 801183c: 2000cf44 .word 0x2000cf44 + +08011840 : + * + * @param pcb the tcp pcb to abort + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + 8011840: b580 push {r7, lr} + 8011842: b082 sub sp, #8 + 8011844: af00 add r7, sp, #0 + 8011846: 6078 str r0, [r7, #4] + tcp_abandon(pcb, 1); + 8011848: 2101 movs r1, #1 + 801184a: 6878 ldr r0, [r7, #4] + 801184c: f7ff ff3a bl 80116c4 +} + 8011850: bf00 nop + 8011852: 3708 adds r7, #8 + 8011854: 46bd mov sp, r7 + 8011856: bd80 pop {r7, pc} + +08011858 : + * Returns how much extra window would be advertised if we sent an + * update now. + */ +u32_t +tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) +{ + 8011858: b580 push {r7, lr} + 801185a: b084 sub sp, #16 + 801185c: af00 add r7, sp, #0 + 801185e: 6078 str r0, [r7, #4] + u32_t new_right_edge; + + LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL); + 8011860: 687b ldr r3, [r7, #4] + 8011862: 2b00 cmp r3, #0 + 8011864: d106 bne.n 8011874 + 8011866: 4b25 ldr r3, [pc, #148] ; (80118fc ) + 8011868: f240 32a6 movw r2, #934 ; 0x3a6 + 801186c: 4924 ldr r1, [pc, #144] ; (8011900 ) + 801186e: 4825 ldr r0, [pc, #148] ; (8011904 ) + 8011870: f00a fbd0 bl 801c014 + new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; + 8011874: 687b ldr r3, [r7, #4] + 8011876: 6a5b ldr r3, [r3, #36] ; 0x24 + 8011878: 687a ldr r2, [r7, #4] + 801187a: 8d12 ldrh r2, [r2, #40] ; 0x28 + 801187c: 4413 add r3, r2 + 801187e: 60fb str r3, [r7, #12] + + if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { + 8011880: 687b ldr r3, [r7, #4] + 8011882: 6adb ldr r3, [r3, #44] ; 0x2c + 8011884: 687a ldr r2, [r7, #4] + 8011886: 8e52 ldrh r2, [r2, #50] ; 0x32 + 8011888: f5b2 6f86 cmp.w r2, #1072 ; 0x430 + 801188c: bf28 it cs + 801188e: f44f 6286 movcs.w r2, #1072 ; 0x430 + 8011892: b292 uxth r2, r2 + 8011894: 4413 add r3, r2 + 8011896: 68fa ldr r2, [r7, #12] + 8011898: 1ad3 subs r3, r2, r3 + 801189a: 2b00 cmp r3, #0 + 801189c: db08 blt.n 80118b0 + /* we can advertise more window */ + pcb->rcv_ann_wnd = pcb->rcv_wnd; + 801189e: 687b ldr r3, [r7, #4] + 80118a0: 8d1a ldrh r2, [r3, #40] ; 0x28 + 80118a2: 687b ldr r3, [r7, #4] + 80118a4: 855a strh r2, [r3, #42] ; 0x2a + return new_right_edge - pcb->rcv_ann_right_edge; + 80118a6: 687b ldr r3, [r7, #4] + 80118a8: 6adb ldr r3, [r3, #44] ; 0x2c + 80118aa: 68fa ldr r2, [r7, #12] + 80118ac: 1ad3 subs r3, r2, r3 + 80118ae: e020 b.n 80118f2 + } else { + if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { + 80118b0: 687b ldr r3, [r7, #4] + 80118b2: 6a5a ldr r2, [r3, #36] ; 0x24 + 80118b4: 687b ldr r3, [r7, #4] + 80118b6: 6adb ldr r3, [r3, #44] ; 0x2c + 80118b8: 1ad3 subs r3, r2, r3 + 80118ba: 2b00 cmp r3, #0 + 80118bc: dd03 ble.n 80118c6 + /* Can happen due to other end sending out of advertised window, + * but within actual available (but not yet advertised) window */ + pcb->rcv_ann_wnd = 0; + 80118be: 687b ldr r3, [r7, #4] + 80118c0: 2200 movs r2, #0 + 80118c2: 855a strh r2, [r3, #42] ; 0x2a + 80118c4: e014 b.n 80118f0 + } else { + /* keep the right edge of window constant */ + u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; + 80118c6: 687b ldr r3, [r7, #4] + 80118c8: 6ada ldr r2, [r3, #44] ; 0x2c + 80118ca: 687b ldr r3, [r7, #4] + 80118cc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80118ce: 1ad3 subs r3, r2, r3 + 80118d0: 60bb str r3, [r7, #8] +#if !LWIP_WND_SCALE + LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); + 80118d2: 68bb ldr r3, [r7, #8] + 80118d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80118d8: d306 bcc.n 80118e8 + 80118da: 4b08 ldr r3, [pc, #32] ; (80118fc ) + 80118dc: f240 32b6 movw r2, #950 ; 0x3b6 + 80118e0: 4909 ldr r1, [pc, #36] ; (8011908 ) + 80118e2: 4808 ldr r0, [pc, #32] ; (8011904 ) + 80118e4: f00a fb96 bl 801c014 +#endif + pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd; + 80118e8: 68bb ldr r3, [r7, #8] + 80118ea: b29a uxth r2, r3 + 80118ec: 687b ldr r3, [r7, #4] + 80118ee: 855a strh r2, [r3, #42] ; 0x2a + } + return 0; + 80118f0: 2300 movs r3, #0 + } +} + 80118f2: 4618 mov r0, r3 + 80118f4: 3710 adds r7, #16 + 80118f6: 46bd mov sp, r7 + 80118f8: bd80 pop {r7, pc} + 80118fa: bf00 nop + 80118fc: 0801f520 .word 0x0801f520 + 8011900: 0801f77c .word 0x0801f77c + 8011904: 0801f564 .word 0x0801f564 + 8011908: 0801f7a0 .word 0x0801f7a0 + +0801190c : + * @param pcb the tcp_pcb for which data is read + * @param len the amount of bytes that have been read by the application + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + 801190c: b580 push {r7, lr} + 801190e: b084 sub sp, #16 + 8011910: af00 add r7, sp, #0 + 8011912: 6078 str r0, [r7, #4] + 8011914: 460b mov r3, r1 + 8011916: 807b strh r3, [r7, #2] + u32_t wnd_inflation; + tcpwnd_size_t rcv_wnd; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return); + 8011918: 687b ldr r3, [r7, #4] + 801191a: 2b00 cmp r3, #0 + 801191c: d107 bne.n 801192e + 801191e: 4b1f ldr r3, [pc, #124] ; (801199c ) + 8011920: f240 32cf movw r2, #975 ; 0x3cf + 8011924: 491e ldr r1, [pc, #120] ; (80119a0 ) + 8011926: 481f ldr r0, [pc, #124] ; (80119a4 ) + 8011928: f00a fb74 bl 801c014 + 801192c: e032 b.n 8011994 + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_recved for listen-pcbs", + 801192e: 687b ldr r3, [r7, #4] + 8011930: 7d1b ldrb r3, [r3, #20] + 8011932: 2b01 cmp r3, #1 + 8011934: d106 bne.n 8011944 + 8011936: 4b19 ldr r3, [pc, #100] ; (801199c ) + 8011938: f240 32d2 movw r2, #978 ; 0x3d2 + 801193c: 491a ldr r1, [pc, #104] ; (80119a8 ) + 801193e: 4819 ldr r0, [pc, #100] ; (80119a4 ) + 8011940: f00a fb68 bl 801c014 + pcb->state != LISTEN); + + rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len); + 8011944: 687b ldr r3, [r7, #4] + 8011946: 8d1a ldrh r2, [r3, #40] ; 0x28 + 8011948: 887b ldrh r3, [r7, #2] + 801194a: 4413 add r3, r2 + 801194c: 81fb strh r3, [r7, #14] + if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) { + 801194e: 89fb ldrh r3, [r7, #14] + 8011950: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 8011954: d804 bhi.n 8011960 + 8011956: 687b ldr r3, [r7, #4] + 8011958: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801195a: 89fa ldrh r2, [r7, #14] + 801195c: 429a cmp r2, r3 + 801195e: d204 bcs.n 801196a + /* window got too big or tcpwnd_size_t overflow */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n")); + pcb->rcv_wnd = TCP_WND_MAX(pcb); + 8011960: 687b ldr r3, [r7, #4] + 8011962: f44f 6206 mov.w r2, #2144 ; 0x860 + 8011966: 851a strh r2, [r3, #40] ; 0x28 + 8011968: e002 b.n 8011970 + } else { + pcb->rcv_wnd = rcv_wnd; + 801196a: 687b ldr r3, [r7, #4] + 801196c: 89fa ldrh r2, [r7, #14] + 801196e: 851a strh r2, [r3, #40] ; 0x28 + } + + wnd_inflation = tcp_update_rcv_ann_wnd(pcb); + 8011970: 6878 ldr r0, [r7, #4] + 8011972: f7ff ff71 bl 8011858 + 8011976: 60b8 str r0, [r7, #8] + + /* If the change in the right edge of window is significant (default + * watermark is TCP_WND/4), then send an explicit update now. + * Otherwise wait for a packet to be sent in the normal course of + * events (or more window to be available later) */ + if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { + 8011978: 68bb ldr r3, [r7, #8] + 801197a: f5b3 7f06 cmp.w r3, #536 ; 0x218 + 801197e: d309 bcc.n 8011994 + tcp_ack_now(pcb); + 8011980: 687b ldr r3, [r7, #4] + 8011982: 8b5b ldrh r3, [r3, #26] + 8011984: f043 0302 orr.w r3, r3, #2 + 8011988: b29a uxth r2, r3 + 801198a: 687b ldr r3, [r7, #4] + 801198c: 835a strh r2, [r3, #26] + tcp_output(pcb); + 801198e: 6878 ldr r0, [r7, #4] + 8011990: f003 fe42 bl 8015618 + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n", + len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd))); +} + 8011994: 3710 adds r7, #16 + 8011996: 46bd mov sp, r7 + 8011998: bd80 pop {r7, pc} + 801199a: bf00 nop + 801199c: 0801f520 .word 0x0801f520 + 80119a0: 0801f7bc .word 0x0801f7bc + 80119a4: 0801f564 .word 0x0801f564 + 80119a8: 0801f7d4 .word 0x0801f7d4 + +080119ac : + * + * Automatically called from tcp_tmr(). + */ +void +tcp_slowtmr(void) +{ + 80119ac: b5b0 push {r4, r5, r7, lr} + 80119ae: b090 sub sp, #64 ; 0x40 + 80119b0: af04 add r7, sp, #16 + tcpwnd_size_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + u8_t pcb_reset; /* flag if a RST should be sent when removing */ + err_t err; + + err = ERR_OK; + 80119b2: 2300 movs r3, #0 + 80119b4: f887 3025 strb.w r3, [r7, #37] ; 0x25 + + ++tcp_ticks; + 80119b8: 4b94 ldr r3, [pc, #592] ; (8011c0c ) + 80119ba: 681b ldr r3, [r3, #0] + 80119bc: 3301 adds r3, #1 + 80119be: 4a93 ldr r2, [pc, #588] ; (8011c0c ) + 80119c0: 6013 str r3, [r2, #0] + ++tcp_timer_ctr; + 80119c2: 4b93 ldr r3, [pc, #588] ; (8011c10 ) + 80119c4: 781b ldrb r3, [r3, #0] + 80119c6: 3301 adds r3, #1 + 80119c8: b2da uxtb r2, r3 + 80119ca: 4b91 ldr r3, [pc, #580] ; (8011c10 ) + 80119cc: 701a strb r2, [r3, #0] + +tcp_slowtmr_start: + /* Steps through all of the active PCBs. */ + prev = NULL; + 80119ce: 2300 movs r3, #0 + 80119d0: 62bb str r3, [r7, #40] ; 0x28 + pcb = tcp_active_pcbs; + 80119d2: 4b90 ldr r3, [pc, #576] ; (8011c14 ) + 80119d4: 681b ldr r3, [r3, #0] + 80119d6: 62fb str r3, [r7, #44] ; 0x2c + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + 80119d8: e29d b.n 8011f16 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + 80119da: 6afb ldr r3, [r7, #44] ; 0x2c + 80119dc: 7d1b ldrb r3, [r3, #20] + 80119de: 2b00 cmp r3, #0 + 80119e0: d106 bne.n 80119f0 + 80119e2: 4b8d ldr r3, [pc, #564] ; (8011c18 ) + 80119e4: f240 42be movw r2, #1214 ; 0x4be + 80119e8: 498c ldr r1, [pc, #560] ; (8011c1c ) + 80119ea: 488d ldr r0, [pc, #564] ; (8011c20 ) + 80119ec: f00a fb12 bl 801c014 + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + 80119f0: 6afb ldr r3, [r7, #44] ; 0x2c + 80119f2: 7d1b ldrb r3, [r3, #20] + 80119f4: 2b01 cmp r3, #1 + 80119f6: d106 bne.n 8011a06 + 80119f8: 4b87 ldr r3, [pc, #540] ; (8011c18 ) + 80119fa: f240 42bf movw r2, #1215 ; 0x4bf + 80119fe: 4989 ldr r1, [pc, #548] ; (8011c24 ) + 8011a00: 4887 ldr r0, [pc, #540] ; (8011c20 ) + 8011a02: f00a fb07 bl 801c014 + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + 8011a06: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a08: 7d1b ldrb r3, [r3, #20] + 8011a0a: 2b0a cmp r3, #10 + 8011a0c: d106 bne.n 8011a1c + 8011a0e: 4b82 ldr r3, [pc, #520] ; (8011c18 ) + 8011a10: f44f 6298 mov.w r2, #1216 ; 0x4c0 + 8011a14: 4984 ldr r1, [pc, #528] ; (8011c28 ) + 8011a16: 4882 ldr r0, [pc, #520] ; (8011c20 ) + 8011a18: f00a fafc bl 801c014 + if (pcb->last_timer == tcp_timer_ctr) { + 8011a1c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a1e: 7f9a ldrb r2, [r3, #30] + 8011a20: 4b7b ldr r3, [pc, #492] ; (8011c10 ) + 8011a22: 781b ldrb r3, [r3, #0] + 8011a24: 429a cmp r2, r3 + 8011a26: d105 bne.n 8011a34 + /* skip this pcb, we have already processed it */ + prev = pcb; + 8011a28: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a2a: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 8011a2c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a2e: 68db ldr r3, [r3, #12] + 8011a30: 62fb str r3, [r7, #44] ; 0x2c + continue; + 8011a32: e270 b.n 8011f16 + } + pcb->last_timer = tcp_timer_ctr; + 8011a34: 4b76 ldr r3, [pc, #472] ; (8011c10 ) + 8011a36: 781a ldrb r2, [r3, #0] + 8011a38: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a3a: 779a strb r2, [r3, #30] + + pcb_remove = 0; + 8011a3c: 2300 movs r3, #0 + 8011a3e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + pcb_reset = 0; + 8011a42: 2300 movs r3, #0 + 8011a44: f887 3026 strb.w r3, [r7, #38] ; 0x26 + + if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) { + 8011a48: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a4a: 7d1b ldrb r3, [r3, #20] + 8011a4c: 2b02 cmp r3, #2 + 8011a4e: d10a bne.n 8011a66 + 8011a50: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a52: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8011a56: 2b05 cmp r3, #5 + 8011a58: d905 bls.n 8011a66 + ++pcb_remove; + 8011a5a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011a5e: 3301 adds r3, #1 + 8011a60: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8011a64: e11e b.n 8011ca4 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } else if (pcb->nrtx >= TCP_MAXRTX) { + 8011a66: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a68: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8011a6c: 2b0b cmp r3, #11 + 8011a6e: d905 bls.n 8011a7c + ++pcb_remove; + 8011a70: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011a74: 3301 adds r3, #1 + 8011a76: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8011a7a: e113 b.n 8011ca4 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + if (pcb->persist_backoff > 0) { + 8011a7c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a7e: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 8011a82: 2b00 cmp r3, #0 + 8011a84: d075 beq.n 8011b72 + LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL); + 8011a86: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a88: 6f1b ldr r3, [r3, #112] ; 0x70 + 8011a8a: 2b00 cmp r3, #0 + 8011a8c: d006 beq.n 8011a9c + 8011a8e: 4b62 ldr r3, [pc, #392] ; (8011c18 ) + 8011a90: f240 42d4 movw r2, #1236 ; 0x4d4 + 8011a94: 4965 ldr r1, [pc, #404] ; (8011c2c ) + 8011a96: 4862 ldr r0, [pc, #392] ; (8011c20 ) + 8011a98: f00a fabc bl 801c014 + LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL); + 8011a9c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011a9e: 6edb ldr r3, [r3, #108] ; 0x6c + 8011aa0: 2b00 cmp r3, #0 + 8011aa2: d106 bne.n 8011ab2 + 8011aa4: 4b5c ldr r3, [pc, #368] ; (8011c18 ) + 8011aa6: f240 42d5 movw r2, #1237 ; 0x4d5 + 8011aaa: 4961 ldr r1, [pc, #388] ; (8011c30 ) + 8011aac: 485c ldr r0, [pc, #368] ; (8011c20 ) + 8011aae: f00a fab1 bl 801c014 + if (pcb->persist_probe >= TCP_MAXRTX) { + 8011ab2: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ab4: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 8011ab8: 2b0b cmp r3, #11 + 8011aba: d905 bls.n 8011ac8 + ++pcb_remove; /* max probes reached */ + 8011abc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011ac0: 3301 adds r3, #1 + 8011ac2: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8011ac6: e0ed b.n 8011ca4 + } else { + u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1]; + 8011ac8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011aca: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 8011ace: 3b01 subs r3, #1 + 8011ad0: 4a58 ldr r2, [pc, #352] ; (8011c34 ) + 8011ad2: 5cd3 ldrb r3, [r2, r3] + 8011ad4: 747b strb r3, [r7, #17] + if (pcb->persist_cnt < backoff_cnt) { + 8011ad6: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ad8: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 8011adc: 7c7a ldrb r2, [r7, #17] + 8011ade: 429a cmp r2, r3 + 8011ae0: d907 bls.n 8011af2 + pcb->persist_cnt++; + 8011ae2: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ae4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 8011ae8: 3301 adds r3, #1 + 8011aea: b2da uxtb r2, r3 + 8011aec: 6afb ldr r3, [r7, #44] ; 0x2c + 8011aee: f883 2098 strb.w r2, [r3, #152] ; 0x98 + } + if (pcb->persist_cnt >= backoff_cnt) { + 8011af2: 6afb ldr r3, [r7, #44] ; 0x2c + 8011af4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 8011af8: 7c7a ldrb r2, [r7, #17] + 8011afa: 429a cmp r2, r3 + 8011afc: f200 80d2 bhi.w 8011ca4 + int next_slot = 1; /* increment timer to next slot */ + 8011b00: 2301 movs r3, #1 + 8011b02: 623b str r3, [r7, #32] + /* If snd_wnd is zero, send 1 byte probes */ + if (pcb->snd_wnd == 0) { + 8011b04: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b06: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8011b0a: 2b00 cmp r3, #0 + 8011b0c: d108 bne.n 8011b20 + if (tcp_zero_window_probe(pcb) != ERR_OK) { + 8011b0e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011b10: f004 fc2a bl 8016368 + 8011b14: 4603 mov r3, r0 + 8011b16: 2b00 cmp r3, #0 + 8011b18: d014 beq.n 8011b44 + next_slot = 0; /* try probe again with current slot */ + 8011b1a: 2300 movs r3, #0 + 8011b1c: 623b str r3, [r7, #32] + 8011b1e: e011 b.n 8011b44 + } + /* snd_wnd not fully closed, split unsent head and fill window */ + } else { + if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) { + 8011b20: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b22: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8011b26: 4619 mov r1, r3 + 8011b28: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011b2a: f003 faef bl 801510c + 8011b2e: 4603 mov r3, r0 + 8011b30: 2b00 cmp r3, #0 + 8011b32: d107 bne.n 8011b44 + if (tcp_output(pcb) == ERR_OK) { + 8011b34: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011b36: f003 fd6f bl 8015618 + 8011b3a: 4603 mov r3, r0 + 8011b3c: 2b00 cmp r3, #0 + 8011b3e: d101 bne.n 8011b44 + /* sending will cancel persist timer, else retry with current slot */ + next_slot = 0; + 8011b40: 2300 movs r3, #0 + 8011b42: 623b str r3, [r7, #32] + } + } + } + if (next_slot) { + 8011b44: 6a3b ldr r3, [r7, #32] + 8011b46: 2b00 cmp r3, #0 + 8011b48: f000 80ac beq.w 8011ca4 + pcb->persist_cnt = 0; + 8011b4c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b4e: 2200 movs r2, #0 + 8011b50: f883 2098 strb.w r2, [r3, #152] ; 0x98 + if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { + 8011b54: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b56: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 8011b5a: 2b06 cmp r3, #6 + 8011b5c: f200 80a2 bhi.w 8011ca4 + pcb->persist_backoff++; + 8011b60: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b62: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 8011b66: 3301 adds r3, #1 + 8011b68: b2da uxtb r2, r3 + 8011b6a: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b6c: f883 2099 strb.w r2, [r3, #153] ; 0x99 + 8011b70: e098 b.n 8011ca4 + } + } + } + } else { + /* Increase the retransmission timer if it is running */ + if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) { + 8011b72: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b74: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 8011b78: 2b00 cmp r3, #0 + 8011b7a: db0f blt.n 8011b9c + 8011b7c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b7e: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 8011b82: f647 72ff movw r2, #32767 ; 0x7fff + 8011b86: 4293 cmp r3, r2 + 8011b88: d008 beq.n 8011b9c + ++pcb->rtime; + 8011b8a: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b8c: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 8011b90: b29b uxth r3, r3 + 8011b92: 3301 adds r3, #1 + 8011b94: b29b uxth r3, r3 + 8011b96: b21a sxth r2, r3 + 8011b98: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b9a: 861a strh r2, [r3, #48] ; 0x30 + } + + if (pcb->rtime >= pcb->rto) { + 8011b9c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011b9e: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30 + 8011ba2: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ba4: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 + 8011ba8: 429a cmp r2, r3 + 8011baa: db7b blt.n 8011ca4 + " pcb->rto %"S16_F"\n", + pcb->rtime, pcb->rto)); + /* If prepare phase fails but we have unsent data but no unacked data, + still execute the backoff calculations below, as this means we somehow + failed to send segment. */ + if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) { + 8011bac: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011bae: f004 f825 bl 8015bfc + 8011bb2: 4603 mov r3, r0 + 8011bb4: 2b00 cmp r3, #0 + 8011bb6: d007 beq.n 8011bc8 + 8011bb8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011bba: 6f1b ldr r3, [r3, #112] ; 0x70 + 8011bbc: 2b00 cmp r3, #0 + 8011bbe: d171 bne.n 8011ca4 + 8011bc0: 6afb ldr r3, [r7, #44] ; 0x2c + 8011bc2: 6edb ldr r3, [r3, #108] ; 0x6c + 8011bc4: 2b00 cmp r3, #0 + 8011bc6: d06d beq.n 8011ca4 + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + 8011bc8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011bca: 7d1b ldrb r3, [r3, #20] + 8011bcc: 2b02 cmp r3, #2 + 8011bce: d03a beq.n 8011c46 + u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1); + 8011bd0: 6afb ldr r3, [r7, #44] ; 0x2c + 8011bd2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8011bd6: 2b0c cmp r3, #12 + 8011bd8: bf28 it cs + 8011bda: 230c movcs r3, #12 + 8011bdc: 76fb strb r3, [r7, #27] + int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx]; + 8011bde: 6afb ldr r3, [r7, #44] ; 0x2c + 8011be0: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 8011be4: 10db asrs r3, r3, #3 + 8011be6: b21b sxth r3, r3 + 8011be8: 461a mov r2, r3 + 8011bea: 6afb ldr r3, [r7, #44] ; 0x2c + 8011bec: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 8011bf0: 4413 add r3, r2 + 8011bf2: 7efa ldrb r2, [r7, #27] + 8011bf4: 4910 ldr r1, [pc, #64] ; (8011c38 ) + 8011bf6: 5c8a ldrb r2, [r1, r2] + 8011bf8: 4093 lsls r3, r2 + 8011bfa: 617b str r3, [r7, #20] + pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF); + 8011bfc: 697b ldr r3, [r7, #20] + 8011bfe: f647 72fe movw r2, #32766 ; 0x7ffe + 8011c02: 4293 cmp r3, r2 + 8011c04: dc1a bgt.n 8011c3c + 8011c06: 697b ldr r3, [r7, #20] + 8011c08: b21a sxth r2, r3 + 8011c0a: e019 b.n 8011c40 + 8011c0c: 2000cf30 .word 0x2000cf30 + 8011c10: 2000cf46 .word 0x2000cf46 + 8011c14: 2000cf3c .word 0x2000cf3c + 8011c18: 0801f520 .word 0x0801f520 + 8011c1c: 0801f864 .word 0x0801f864 + 8011c20: 0801f564 .word 0x0801f564 + 8011c24: 0801f890 .word 0x0801f890 + 8011c28: 0801f8bc .word 0x0801f8bc + 8011c2c: 0801f8ec .word 0x0801f8ec + 8011c30: 0801f920 .word 0x0801f920 + 8011c34: 080238cc .word 0x080238cc + 8011c38: 080238bc .word 0x080238bc + 8011c3c: f647 72ff movw r2, #32767 ; 0x7fff + 8011c40: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c42: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + } + + /* Reset the retransmission timer. */ + pcb->rtime = 0; + 8011c46: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c48: 2200 movs r2, #0 + 8011c4a: 861a strh r2, [r3, #48] ; 0x30 + + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + 8011c4c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c4e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 8011c52: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c54: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 8011c58: 4293 cmp r3, r2 + 8011c5a: bf28 it cs + 8011c5c: 4613 movcs r3, r2 + 8011c5e: 827b strh r3, [r7, #18] + pcb->ssthresh = eff_wnd >> 1; + 8011c60: 8a7b ldrh r3, [r7, #18] + 8011c62: 085b lsrs r3, r3, #1 + 8011c64: b29a uxth r2, r3 + 8011c66: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c68: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) { + 8011c6c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c6e: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 8011c72: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c74: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8011c76: 005b lsls r3, r3, #1 + 8011c78: b29b uxth r3, r3 + 8011c7a: 429a cmp r2, r3 + 8011c7c: d206 bcs.n 8011c8c + pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1); + 8011c7e: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c80: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8011c82: 005b lsls r3, r3, #1 + 8011c84: b29a uxth r2, r3 + 8011c86: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c88: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + } + pcb->cwnd = pcb->mss; + 8011c8c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c8e: 8e5a ldrh r2, [r3, #50] ; 0x32 + 8011c90: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c92: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + pcb->bytes_acked = 0; + 8011c96: 6afb ldr r3, [r7, #44] ; 0x2c + 8011c98: 2200 movs r2, #0 + 8011c9a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + + /* The following needs to be called AFTER cwnd is set to one + mss - STJ */ + tcp_rexmit_rto_commit(pcb); + 8011c9e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011ca0: f004 f81c bl 8015cdc + } + } + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + 8011ca4: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ca6: 7d1b ldrb r3, [r3, #20] + 8011ca8: 2b06 cmp r3, #6 + 8011caa: d111 bne.n 8011cd0 + /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */ + if (pcb->flags & TF_RXCLOSED) { + 8011cac: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cae: 8b5b ldrh r3, [r3, #26] + 8011cb0: f003 0310 and.w r3, r3, #16 + 8011cb4: 2b00 cmp r3, #0 + 8011cb6: d00b beq.n 8011cd0 + /* PCB was fully closed (either through close() or SHUT_RDWR): + normal FIN-WAIT timeout handling. */ + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011cb8: 4b9c ldr r3, [pc, #624] ; (8011f2c ) + 8011cba: 681a ldr r2, [r3, #0] + 8011cbc: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cbe: 6a1b ldr r3, [r3, #32] + 8011cc0: 1ad3 subs r3, r2, r3 + 8011cc2: 2b28 cmp r3, #40 ; 0x28 + 8011cc4: d904 bls.n 8011cd0 + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + 8011cc6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011cca: 3301 adds r3, #1 + 8011ccc: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + } + } + + /* Check if KEEPALIVE should be sent */ + if (ip_get_option(pcb, SOF_KEEPALIVE) && + 8011cd0: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cd2: 7a5b ldrb r3, [r3, #9] + 8011cd4: f003 0308 and.w r3, r3, #8 + 8011cd8: 2b00 cmp r3, #0 + 8011cda: d04a beq.n 8011d72 + ((pcb->state == ESTABLISHED) || + 8011cdc: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cde: 7d1b ldrb r3, [r3, #20] + if (ip_get_option(pcb, SOF_KEEPALIVE) && + 8011ce0: 2b04 cmp r3, #4 + 8011ce2: d003 beq.n 8011cec + (pcb->state == CLOSE_WAIT))) { + 8011ce4: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ce6: 7d1b ldrb r3, [r3, #20] + ((pcb->state == ESTABLISHED) || + 8011ce8: 2b07 cmp r3, #7 + 8011cea: d142 bne.n 8011d72 + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011cec: 4b8f ldr r3, [pc, #572] ; (8011f2c ) + 8011cee: 681a ldr r2, [r3, #0] + 8011cf0: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cf2: 6a1b ldr r3, [r3, #32] + 8011cf4: 1ad2 subs r2, r2, r3 + (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) { + 8011cf6: 6afb ldr r3, [r7, #44] ; 0x2c + 8011cf8: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 + 8011cfc: 4b8c ldr r3, [pc, #560] ; (8011f30 ) + 8011cfe: 440b add r3, r1 + 8011d00: 498c ldr r1, [pc, #560] ; (8011f34 ) + 8011d02: fba1 1303 umull r1, r3, r1, r3 + 8011d06: 095b lsrs r3, r3, #5 + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011d08: 429a cmp r2, r3 + 8011d0a: d90a bls.n 8011d22 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to ")); + ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + ++pcb_remove; + 8011d0c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011d10: 3301 adds r3, #1 + 8011d12: f887 3027 strb.w r3, [r7, #39] ; 0x27 + ++pcb_reset; + 8011d16: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8011d1a: 3301 adds r3, #1 + 8011d1c: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8011d20: e027 b.n 8011d72 + } else if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011d22: 4b82 ldr r3, [pc, #520] ; (8011f2c ) + 8011d24: 681a ldr r2, [r3, #0] + 8011d26: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d28: 6a1b ldr r3, [r3, #32] + 8011d2a: 1ad2 subs r2, r2, r3 + (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb)) + 8011d2c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d2e: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 + 8011d32: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d34: f893 309b ldrb.w r3, [r3, #155] ; 0x9b + 8011d38: 4618 mov r0, r3 + 8011d3a: 4b7f ldr r3, [pc, #508] ; (8011f38 ) + 8011d3c: fb00 f303 mul.w r3, r0, r3 + 8011d40: 440b add r3, r1 + / TCP_SLOW_INTERVAL) { + 8011d42: 497c ldr r1, [pc, #496] ; (8011f34 ) + 8011d44: fba1 1303 umull r1, r3, r1, r3 + 8011d48: 095b lsrs r3, r3, #5 + } else if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011d4a: 429a cmp r2, r3 + 8011d4c: d911 bls.n 8011d72 + err = tcp_keepalive(pcb); + 8011d4e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011d50: f004 faca bl 80162e8 + 8011d54: 4603 mov r3, r0 + 8011d56: f887 3025 strb.w r3, [r7, #37] ; 0x25 + if (err == ERR_OK) { + 8011d5a: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 + 8011d5e: 2b00 cmp r3, #0 + 8011d60: d107 bne.n 8011d72 + pcb->keep_cnt_sent++; + 8011d62: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d64: f893 309b ldrb.w r3, [r3, #155] ; 0x9b + 8011d68: 3301 adds r3, #1 + 8011d6a: b2da uxtb r2, r3 + 8011d6c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d6e: f883 209b strb.w r2, [r3, #155] ; 0x9b + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + 8011d72: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d74: 6f5b ldr r3, [r3, #116] ; 0x74 + 8011d76: 2b00 cmp r3, #0 + 8011d78: d011 beq.n 8011d9e + (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) { + 8011d7a: 4b6c ldr r3, [pc, #432] ; (8011f2c ) + 8011d7c: 681a ldr r2, [r3, #0] + 8011d7e: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d80: 6a1b ldr r3, [r3, #32] + 8011d82: 1ad2 subs r2, r2, r3 + 8011d84: 6afb ldr r3, [r7, #44] ; 0x2c + 8011d86: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 + 8011d8a: 4619 mov r1, r3 + 8011d8c: 460b mov r3, r1 + 8011d8e: 005b lsls r3, r3, #1 + 8011d90: 440b add r3, r1 + 8011d92: 005b lsls r3, r3, #1 + if (pcb->ooseq != NULL && + 8011d94: 429a cmp r2, r3 + 8011d96: d302 bcc.n 8011d9e + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + tcp_free_ooseq(pcb); + 8011d98: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011d9a: f000 fddd bl 8012958 + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + 8011d9e: 6afb ldr r3, [r7, #44] ; 0x2c + 8011da0: 7d1b ldrb r3, [r3, #20] + 8011da2: 2b03 cmp r3, #3 + 8011da4: d10b bne.n 8011dbe + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8011da6: 4b61 ldr r3, [pc, #388] ; (8011f2c ) + 8011da8: 681a ldr r2, [r3, #0] + 8011daa: 6afb ldr r3, [r7, #44] ; 0x2c + 8011dac: 6a1b ldr r3, [r3, #32] + 8011dae: 1ad3 subs r3, r2, r3 + 8011db0: 2b28 cmp r3, #40 ; 0x28 + 8011db2: d904 bls.n 8011dbe + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + 8011db4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011db8: 3301 adds r3, #1 + 8011dba: f887 3027 strb.w r3, [r7, #39] ; 0x27 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + 8011dbe: 6afb ldr r3, [r7, #44] ; 0x2c + 8011dc0: 7d1b ldrb r3, [r3, #20] + 8011dc2: 2b09 cmp r3, #9 + 8011dc4: d10b bne.n 8011dde + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + 8011dc6: 4b59 ldr r3, [pc, #356] ; (8011f2c ) + 8011dc8: 681a ldr r2, [r3, #0] + 8011dca: 6afb ldr r3, [r7, #44] ; 0x2c + 8011dcc: 6a1b ldr r3, [r3, #32] + 8011dce: 1ad3 subs r3, r2, r3 + 8011dd0: 2bf0 cmp r3, #240 ; 0xf0 + 8011dd2: d904 bls.n 8011dde + ++pcb_remove; + 8011dd4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011dd8: 3301 adds r3, #1 + 8011dda: f887 3027 strb.w r3, [r7, #39] ; 0x27 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + 8011dde: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011de2: 2b00 cmp r3, #0 + 8011de4: d060 beq.n 8011ea8 + struct tcp_pcb *pcb2; +#if LWIP_CALLBACK_API + tcp_err_fn err_fn = pcb->errf; + 8011de6: 6afb ldr r3, [r7, #44] ; 0x2c + 8011de8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8011dec: 60fb str r3, [r7, #12] +#endif /* LWIP_CALLBACK_API */ + void *err_arg; + enum tcp_state last_state; + tcp_pcb_purge(pcb); + 8011dee: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011df0: f000 fbfe bl 80125f0 + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + 8011df4: 6abb ldr r3, [r7, #40] ; 0x28 + 8011df6: 2b00 cmp r3, #0 + 8011df8: d010 beq.n 8011e1c + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + 8011dfa: 4b50 ldr r3, [pc, #320] ; (8011f3c ) + 8011dfc: 681b ldr r3, [r3, #0] + 8011dfe: 6afa ldr r2, [r7, #44] ; 0x2c + 8011e00: 429a cmp r2, r3 + 8011e02: d106 bne.n 8011e12 + 8011e04: 4b4e ldr r3, [pc, #312] ; (8011f40 ) + 8011e06: f240 526d movw r2, #1389 ; 0x56d + 8011e0a: 494e ldr r1, [pc, #312] ; (8011f44 ) + 8011e0c: 484e ldr r0, [pc, #312] ; (8011f48 ) + 8011e0e: f00a f901 bl 801c014 + prev->next = pcb->next; + 8011e12: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e14: 68da ldr r2, [r3, #12] + 8011e16: 6abb ldr r3, [r7, #40] ; 0x28 + 8011e18: 60da str r2, [r3, #12] + 8011e1a: e00f b.n 8011e3c + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + 8011e1c: 4b47 ldr r3, [pc, #284] ; (8011f3c ) + 8011e1e: 681b ldr r3, [r3, #0] + 8011e20: 6afa ldr r2, [r7, #44] ; 0x2c + 8011e22: 429a cmp r2, r3 + 8011e24: d006 beq.n 8011e34 + 8011e26: 4b46 ldr r3, [pc, #280] ; (8011f40 ) + 8011e28: f240 5271 movw r2, #1393 ; 0x571 + 8011e2c: 4947 ldr r1, [pc, #284] ; (8011f4c ) + 8011e2e: 4846 ldr r0, [pc, #280] ; (8011f48 ) + 8011e30: f00a f8f0 bl 801c014 + tcp_active_pcbs = pcb->next; + 8011e34: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e36: 68db ldr r3, [r3, #12] + 8011e38: 4a40 ldr r2, [pc, #256] ; (8011f3c ) + 8011e3a: 6013 str r3, [r2, #0] + } + + if (pcb_reset) { + 8011e3c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8011e40: 2b00 cmp r3, #0 + 8011e42: d013 beq.n 8011e6c + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + 8011e44: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e46: 6d18 ldr r0, [r3, #80] ; 0x50 + 8011e48: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e4a: 6a5c ldr r4, [r3, #36] ; 0x24 + 8011e4c: 6afd ldr r5, [r7, #44] ; 0x2c + 8011e4e: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e50: 3304 adds r3, #4 + 8011e52: 6afa ldr r2, [r7, #44] ; 0x2c + 8011e54: 8ad2 ldrh r2, [r2, #22] + 8011e56: 6af9 ldr r1, [r7, #44] ; 0x2c + 8011e58: 8b09 ldrh r1, [r1, #24] + 8011e5a: 9102 str r1, [sp, #8] + 8011e5c: 9201 str r2, [sp, #4] + 8011e5e: 9300 str r3, [sp, #0] + 8011e60: 462b mov r3, r5 + 8011e62: 4622 mov r2, r4 + 8011e64: 4601 mov r1, r0 + 8011e66: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011e68: f004 f98a bl 8016180 + pcb->local_port, pcb->remote_port); + } + + err_arg = pcb->callback_arg; + 8011e6c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e6e: 691b ldr r3, [r3, #16] + 8011e70: 60bb str r3, [r7, #8] + last_state = pcb->state; + 8011e72: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e74: 7d1b ldrb r3, [r3, #20] + 8011e76: 71fb strb r3, [r7, #7] + pcb2 = pcb; + 8011e78: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e7a: 603b str r3, [r7, #0] + pcb = pcb->next; + 8011e7c: 6afb ldr r3, [r7, #44] ; 0x2c + 8011e7e: 68db ldr r3, [r3, #12] + 8011e80: 62fb str r3, [r7, #44] ; 0x2c + tcp_free(pcb2); + 8011e82: 6838 ldr r0, [r7, #0] + 8011e84: f7ff f9f4 bl 8011270 + + tcp_active_pcbs_changed = 0; + 8011e88: 4b31 ldr r3, [pc, #196] ; (8011f50 ) + 8011e8a: 2200 movs r2, #0 + 8011e8c: 701a strb r2, [r3, #0] + TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT); + 8011e8e: 68fb ldr r3, [r7, #12] + 8011e90: 2b00 cmp r3, #0 + 8011e92: d004 beq.n 8011e9e + 8011e94: 68fb ldr r3, [r7, #12] + 8011e96: f06f 010c mvn.w r1, #12 + 8011e9a: 68b8 ldr r0, [r7, #8] + 8011e9c: 4798 blx r3 + if (tcp_active_pcbs_changed) { + 8011e9e: 4b2c ldr r3, [pc, #176] ; (8011f50 ) + 8011ea0: 781b ldrb r3, [r3, #0] + 8011ea2: 2b00 cmp r3, #0 + 8011ea4: d037 beq.n 8011f16 + goto tcp_slowtmr_start; + 8011ea6: e592 b.n 80119ce + } + } else { + /* get the 'next' element now and work with 'prev' below (in case of abort) */ + prev = pcb; + 8011ea8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011eaa: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 8011eac: 6afb ldr r3, [r7, #44] ; 0x2c + 8011eae: 68db ldr r3, [r3, #12] + 8011eb0: 62fb str r3, [r7, #44] ; 0x2c + + /* We check if we should poll the connection. */ + ++prev->polltmr; + 8011eb2: 6abb ldr r3, [r7, #40] ; 0x28 + 8011eb4: 7f1b ldrb r3, [r3, #28] + 8011eb6: 3301 adds r3, #1 + 8011eb8: b2da uxtb r2, r3 + 8011eba: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ebc: 771a strb r2, [r3, #28] + if (prev->polltmr >= prev->pollinterval) { + 8011ebe: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ec0: 7f1a ldrb r2, [r3, #28] + 8011ec2: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ec4: 7f5b ldrb r3, [r3, #29] + 8011ec6: 429a cmp r2, r3 + 8011ec8: d325 bcc.n 8011f16 + prev->polltmr = 0; + 8011eca: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ecc: 2200 movs r2, #0 + 8011ece: 771a strb r2, [r3, #28] + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + tcp_active_pcbs_changed = 0; + 8011ed0: 4b1f ldr r3, [pc, #124] ; (8011f50 ) + 8011ed2: 2200 movs r2, #0 + 8011ed4: 701a strb r2, [r3, #0] + TCP_EVENT_POLL(prev, err); + 8011ed6: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ed8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8011edc: 2b00 cmp r3, #0 + 8011ede: d00b beq.n 8011ef8 + 8011ee0: 6abb ldr r3, [r7, #40] ; 0x28 + 8011ee2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8011ee6: 6aba ldr r2, [r7, #40] ; 0x28 + 8011ee8: 6912 ldr r2, [r2, #16] + 8011eea: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8011eec: 4610 mov r0, r2 + 8011eee: 4798 blx r3 + 8011ef0: 4603 mov r3, r0 + 8011ef2: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 8011ef6: e002 b.n 8011efe + 8011ef8: 2300 movs r3, #0 + 8011efa: f887 3025 strb.w r3, [r7, #37] ; 0x25 + if (tcp_active_pcbs_changed) { + 8011efe: 4b14 ldr r3, [pc, #80] ; (8011f50 ) + 8011f00: 781b ldrb r3, [r3, #0] + 8011f02: 2b00 cmp r3, #0 + 8011f04: d000 beq.n 8011f08 + goto tcp_slowtmr_start; + 8011f06: e562 b.n 80119ce + } + /* if err == ERR_ABRT, 'prev' is already deallocated */ + if (err == ERR_OK) { + 8011f08: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 + 8011f0c: 2b00 cmp r3, #0 + 8011f0e: d102 bne.n 8011f16 + tcp_output(prev); + 8011f10: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8011f12: f003 fb81 bl 8015618 + while (pcb != NULL) { + 8011f16: 6afb ldr r3, [r7, #44] ; 0x2c + 8011f18: 2b00 cmp r3, #0 + 8011f1a: f47f ad5e bne.w 80119da + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + 8011f1e: 2300 movs r3, #0 + 8011f20: 62bb str r3, [r7, #40] ; 0x28 + pcb = tcp_tw_pcbs; + 8011f22: 4b0c ldr r3, [pc, #48] ; (8011f54 ) + 8011f24: 681b ldr r3, [r3, #0] + 8011f26: 62fb str r3, [r7, #44] ; 0x2c + while (pcb != NULL) { + 8011f28: e069 b.n 8011ffe + 8011f2a: bf00 nop + 8011f2c: 2000cf30 .word 0x2000cf30 + 8011f30: 000a4cb8 .word 0x000a4cb8 + 8011f34: 10624dd3 .word 0x10624dd3 + 8011f38: 000124f8 .word 0x000124f8 + 8011f3c: 2000cf3c .word 0x2000cf3c + 8011f40: 0801f520 .word 0x0801f520 + 8011f44: 0801f958 .word 0x0801f958 + 8011f48: 0801f564 .word 0x0801f564 + 8011f4c: 0801f984 .word 0x0801f984 + 8011f50: 2000cf44 .word 0x2000cf44 + 8011f54: 2000cf40 .word 0x2000cf40 + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + 8011f58: 6afb ldr r3, [r7, #44] ; 0x2c + 8011f5a: 7d1b ldrb r3, [r3, #20] + 8011f5c: 2b0a cmp r3, #10 + 8011f5e: d006 beq.n 8011f6e + 8011f60: 4b2b ldr r3, [pc, #172] ; (8012010 ) + 8011f62: f240 52a1 movw r2, #1441 ; 0x5a1 + 8011f66: 492b ldr r1, [pc, #172] ; (8012014 ) + 8011f68: 482b ldr r0, [pc, #172] ; (8012018 ) + 8011f6a: f00a f853 bl 801c014 + pcb_remove = 0; + 8011f6e: 2300 movs r3, #0 + 8011f70: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + 8011f74: 4b29 ldr r3, [pc, #164] ; (801201c ) + 8011f76: 681a ldr r2, [r3, #0] + 8011f78: 6afb ldr r3, [r7, #44] ; 0x2c + 8011f7a: 6a1b ldr r3, [r3, #32] + 8011f7c: 1ad3 subs r3, r2, r3 + 8011f7e: 2bf0 cmp r3, #240 ; 0xf0 + 8011f80: d904 bls.n 8011f8c + ++pcb_remove; + 8011f82: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011f86: 3301 adds r3, #1 + 8011f88: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + 8011f8c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8011f90: 2b00 cmp r3, #0 + 8011f92: d02f beq.n 8011ff4 + struct tcp_pcb *pcb2; + tcp_pcb_purge(pcb); + 8011f94: 6af8 ldr r0, [r7, #44] ; 0x2c + 8011f96: f000 fb2b bl 80125f0 + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + 8011f9a: 6abb ldr r3, [r7, #40] ; 0x28 + 8011f9c: 2b00 cmp r3, #0 + 8011f9e: d010 beq.n 8011fc2 + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + 8011fa0: 4b1f ldr r3, [pc, #124] ; (8012020 ) + 8011fa2: 681b ldr r3, [r3, #0] + 8011fa4: 6afa ldr r2, [r7, #44] ; 0x2c + 8011fa6: 429a cmp r2, r3 + 8011fa8: d106 bne.n 8011fb8 + 8011faa: 4b19 ldr r3, [pc, #100] ; (8012010 ) + 8011fac: f240 52af movw r2, #1455 ; 0x5af + 8011fb0: 491c ldr r1, [pc, #112] ; (8012024 ) + 8011fb2: 4819 ldr r0, [pc, #100] ; (8012018 ) + 8011fb4: f00a f82e bl 801c014 + prev->next = pcb->next; + 8011fb8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011fba: 68da ldr r2, [r3, #12] + 8011fbc: 6abb ldr r3, [r7, #40] ; 0x28 + 8011fbe: 60da str r2, [r3, #12] + 8011fc0: e00f b.n 8011fe2 + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + 8011fc2: 4b17 ldr r3, [pc, #92] ; (8012020 ) + 8011fc4: 681b ldr r3, [r3, #0] + 8011fc6: 6afa ldr r2, [r7, #44] ; 0x2c + 8011fc8: 429a cmp r2, r3 + 8011fca: d006 beq.n 8011fda + 8011fcc: 4b10 ldr r3, [pc, #64] ; (8012010 ) + 8011fce: f240 52b3 movw r2, #1459 ; 0x5b3 + 8011fd2: 4915 ldr r1, [pc, #84] ; (8012028 ) + 8011fd4: 4810 ldr r0, [pc, #64] ; (8012018 ) + 8011fd6: f00a f81d bl 801c014 + tcp_tw_pcbs = pcb->next; + 8011fda: 6afb ldr r3, [r7, #44] ; 0x2c + 8011fdc: 68db ldr r3, [r3, #12] + 8011fde: 4a10 ldr r2, [pc, #64] ; (8012020 ) + 8011fe0: 6013 str r3, [r2, #0] + } + pcb2 = pcb; + 8011fe2: 6afb ldr r3, [r7, #44] ; 0x2c + 8011fe4: 61fb str r3, [r7, #28] + pcb = pcb->next; + 8011fe6: 6afb ldr r3, [r7, #44] ; 0x2c + 8011fe8: 68db ldr r3, [r3, #12] + 8011fea: 62fb str r3, [r7, #44] ; 0x2c + tcp_free(pcb2); + 8011fec: 69f8 ldr r0, [r7, #28] + 8011fee: f7ff f93f bl 8011270 + 8011ff2: e004 b.n 8011ffe + } else { + prev = pcb; + 8011ff4: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ff6: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 8011ff8: 6afb ldr r3, [r7, #44] ; 0x2c + 8011ffa: 68db ldr r3, [r3, #12] + 8011ffc: 62fb str r3, [r7, #44] ; 0x2c + while (pcb != NULL) { + 8011ffe: 6afb ldr r3, [r7, #44] ; 0x2c + 8012000: 2b00 cmp r3, #0 + 8012002: d1a9 bne.n 8011f58 + } + } +} + 8012004: bf00 nop + 8012006: bf00 nop + 8012008: 3730 adds r7, #48 ; 0x30 + 801200a: 46bd mov sp, r7 + 801200c: bdb0 pop {r4, r5, r7, pc} + 801200e: bf00 nop + 8012010: 0801f520 .word 0x0801f520 + 8012014: 0801f9b0 .word 0x0801f9b0 + 8012018: 0801f564 .word 0x0801f564 + 801201c: 2000cf30 .word 0x2000cf30 + 8012020: 2000cf40 .word 0x2000cf40 + 8012024: 0801f9e0 .word 0x0801f9e0 + 8012028: 0801fa08 .word 0x0801fa08 + +0801202c : + * + * Automatically called from tcp_tmr(). + */ +void +tcp_fasttmr(void) +{ + 801202c: b580 push {r7, lr} + 801202e: b082 sub sp, #8 + 8012030: af00 add r7, sp, #0 + struct tcp_pcb *pcb; + + ++tcp_timer_ctr; + 8012032: 4b2d ldr r3, [pc, #180] ; (80120e8 ) + 8012034: 781b ldrb r3, [r3, #0] + 8012036: 3301 adds r3, #1 + 8012038: b2da uxtb r2, r3 + 801203a: 4b2b ldr r3, [pc, #172] ; (80120e8 ) + 801203c: 701a strb r2, [r3, #0] + +tcp_fasttmr_start: + pcb = tcp_active_pcbs; + 801203e: 4b2b ldr r3, [pc, #172] ; (80120ec ) + 8012040: 681b ldr r3, [r3, #0] + 8012042: 607b str r3, [r7, #4] + + while (pcb != NULL) { + 8012044: e048 b.n 80120d8 + if (pcb->last_timer != tcp_timer_ctr) { + 8012046: 687b ldr r3, [r7, #4] + 8012048: 7f9a ldrb r2, [r3, #30] + 801204a: 4b27 ldr r3, [pc, #156] ; (80120e8 ) + 801204c: 781b ldrb r3, [r3, #0] + 801204e: 429a cmp r2, r3 + 8012050: d03f beq.n 80120d2 + struct tcp_pcb *next; + pcb->last_timer = tcp_timer_ctr; + 8012052: 4b25 ldr r3, [pc, #148] ; (80120e8 ) + 8012054: 781a ldrb r2, [r3, #0] + 8012056: 687b ldr r3, [r7, #4] + 8012058: 779a strb r2, [r3, #30] + /* send delayed ACKs */ + if (pcb->flags & TF_ACK_DELAY) { + 801205a: 687b ldr r3, [r7, #4] + 801205c: 8b5b ldrh r3, [r3, #26] + 801205e: f003 0301 and.w r3, r3, #1 + 8012062: 2b00 cmp r3, #0 + 8012064: d010 beq.n 8012088 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + 8012066: 687b ldr r3, [r7, #4] + 8012068: 8b5b ldrh r3, [r3, #26] + 801206a: f043 0302 orr.w r3, r3, #2 + 801206e: b29a uxth r2, r3 + 8012070: 687b ldr r3, [r7, #4] + 8012072: 835a strh r2, [r3, #26] + tcp_output(pcb); + 8012074: 6878 ldr r0, [r7, #4] + 8012076: f003 facf bl 8015618 + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 801207a: 687b ldr r3, [r7, #4] + 801207c: 8b5b ldrh r3, [r3, #26] + 801207e: f023 0303 bic.w r3, r3, #3 + 8012082: b29a uxth r2, r3 + 8012084: 687b ldr r3, [r7, #4] + 8012086: 835a strh r2, [r3, #26] + } + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + 8012088: 687b ldr r3, [r7, #4] + 801208a: 8b5b ldrh r3, [r3, #26] + 801208c: f003 0308 and.w r3, r3, #8 + 8012090: 2b00 cmp r3, #0 + 8012092: d009 beq.n 80120a8 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + 8012094: 687b ldr r3, [r7, #4] + 8012096: 8b5b ldrh r3, [r3, #26] + 8012098: f023 0308 bic.w r3, r3, #8 + 801209c: b29a uxth r2, r3 + 801209e: 687b ldr r3, [r7, #4] + 80120a0: 835a strh r2, [r3, #26] + tcp_close_shutdown_fin(pcb); + 80120a2: 6878 ldr r0, [r7, #4] + 80120a4: f7ff fa78 bl 8011598 + } + + next = pcb->next; + 80120a8: 687b ldr r3, [r7, #4] + 80120aa: 68db ldr r3, [r3, #12] + 80120ac: 603b str r3, [r7, #0] + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + 80120ae: 687b ldr r3, [r7, #4] + 80120b0: 6f9b ldr r3, [r3, #120] ; 0x78 + 80120b2: 2b00 cmp r3, #0 + 80120b4: d00a beq.n 80120cc + tcp_active_pcbs_changed = 0; + 80120b6: 4b0e ldr r3, [pc, #56] ; (80120f0 ) + 80120b8: 2200 movs r2, #0 + 80120ba: 701a strb r2, [r3, #0] + tcp_process_refused_data(pcb); + 80120bc: 6878 ldr r0, [r7, #4] + 80120be: f000 f819 bl 80120f4 + if (tcp_active_pcbs_changed) { + 80120c2: 4b0b ldr r3, [pc, #44] ; (80120f0 ) + 80120c4: 781b ldrb r3, [r3, #0] + 80120c6: 2b00 cmp r3, #0 + 80120c8: d000 beq.n 80120cc + /* application callback has changed the pcb list: restart the loop */ + goto tcp_fasttmr_start; + 80120ca: e7b8 b.n 801203e + } + } + pcb = next; + 80120cc: 683b ldr r3, [r7, #0] + 80120ce: 607b str r3, [r7, #4] + 80120d0: e002 b.n 80120d8 + } else { + pcb = pcb->next; + 80120d2: 687b ldr r3, [r7, #4] + 80120d4: 68db ldr r3, [r3, #12] + 80120d6: 607b str r3, [r7, #4] + while (pcb != NULL) { + 80120d8: 687b ldr r3, [r7, #4] + 80120da: 2b00 cmp r3, #0 + 80120dc: d1b3 bne.n 8012046 + } + } +} + 80120de: bf00 nop + 80120e0: bf00 nop + 80120e2: 3708 adds r7, #8 + 80120e4: 46bd mov sp, r7 + 80120e6: bd80 pop {r7, pc} + 80120e8: 2000cf46 .word 0x2000cf46 + 80120ec: 2000cf3c .word 0x2000cf3c + 80120f0: 2000cf44 .word 0x2000cf44 + +080120f4 : +} + +/** Pass pcb->refused_data to the recv callback */ +err_t +tcp_process_refused_data(struct tcp_pcb *pcb) +{ + 80120f4: b590 push {r4, r7, lr} + 80120f6: b085 sub sp, #20 + 80120f8: af00 add r7, sp, #0 + 80120fa: 6078 str r0, [r7, #4] +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + struct pbuf *rest; +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG); + 80120fc: 687b ldr r3, [r7, #4] + 80120fe: 2b00 cmp r3, #0 + 8012100: d109 bne.n 8012116 + 8012102: 4b37 ldr r3, [pc, #220] ; (80121e0 ) + 8012104: f240 6209 movw r2, #1545 ; 0x609 + 8012108: 4936 ldr r1, [pc, #216] ; (80121e4 ) + 801210a: 4837 ldr r0, [pc, #220] ; (80121e8 ) + 801210c: f009 ff82 bl 801c014 + 8012110: f06f 030f mvn.w r3, #15 + 8012114: e060 b.n 80121d8 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (pcb->refused_data != NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + { + err_t err; + u8_t refused_flags = pcb->refused_data->flags; + 8012116: 687b ldr r3, [r7, #4] + 8012118: 6f9b ldr r3, [r3, #120] ; 0x78 + 801211a: 7b5b ldrb r3, [r3, #13] + 801211c: 73bb strb r3, [r7, #14] + /* set pcb->refused_data to NULL in case the callback frees it and then + closes the pcb */ + struct pbuf *refused_data = pcb->refused_data; + 801211e: 687b ldr r3, [r7, #4] + 8012120: 6f9b ldr r3, [r3, #120] ; 0x78 + 8012122: 60bb str r3, [r7, #8] +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + pbuf_split_64k(refused_data, &rest); + pcb->refused_data = rest; +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = NULL; + 8012124: 687b ldr r3, [r7, #4] + 8012126: 2200 movs r2, #0 + 8012128: 679a str r2, [r3, #120] ; 0x78 +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + /* Notify again application with data previously received. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); + TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err); + 801212a: 687b ldr r3, [r7, #4] + 801212c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8012130: 2b00 cmp r3, #0 + 8012132: d00b beq.n 801214c + 8012134: 687b ldr r3, [r7, #4] + 8012136: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 801213a: 687b ldr r3, [r7, #4] + 801213c: 6918 ldr r0, [r3, #16] + 801213e: 2300 movs r3, #0 + 8012140: 68ba ldr r2, [r7, #8] + 8012142: 6879 ldr r1, [r7, #4] + 8012144: 47a0 blx r4 + 8012146: 4603 mov r3, r0 + 8012148: 73fb strb r3, [r7, #15] + 801214a: e007 b.n 801215c + 801214c: 2300 movs r3, #0 + 801214e: 68ba ldr r2, [r7, #8] + 8012150: 6879 ldr r1, [r7, #4] + 8012152: 2000 movs r0, #0 + 8012154: f000 f8a4 bl 80122a0 + 8012158: 4603 mov r3, r0 + 801215a: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 801215c: f997 300f ldrsb.w r3, [r7, #15] + 8012160: 2b00 cmp r3, #0 + 8012162: d12a bne.n 80121ba + /* did refused_data include a FIN? */ + if ((refused_flags & PBUF_FLAG_TCP_FIN) + 8012164: 7bbb ldrb r3, [r7, #14] + 8012166: f003 0320 and.w r3, r3, #32 + 801216a: 2b00 cmp r3, #0 + 801216c: d033 beq.n 80121d6 + && (rest == NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + ) { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + 801216e: 687b ldr r3, [r7, #4] + 8012170: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8012172: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 8012176: d005 beq.n 8012184 + pcb->rcv_wnd++; + 8012178: 687b ldr r3, [r7, #4] + 801217a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801217c: 3301 adds r3, #1 + 801217e: b29a uxth r2, r3 + 8012180: 687b ldr r3, [r7, #4] + 8012182: 851a strh r2, [r3, #40] ; 0x28 + } + TCP_EVENT_CLOSED(pcb, err); + 8012184: 687b ldr r3, [r7, #4] + 8012186: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 801218a: 2b00 cmp r3, #0 + 801218c: d00b beq.n 80121a6 + 801218e: 687b ldr r3, [r7, #4] + 8012190: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 8012194: 687b ldr r3, [r7, #4] + 8012196: 6918 ldr r0, [r3, #16] + 8012198: 2300 movs r3, #0 + 801219a: 2200 movs r2, #0 + 801219c: 6879 ldr r1, [r7, #4] + 801219e: 47a0 blx r4 + 80121a0: 4603 mov r3, r0 + 80121a2: 73fb strb r3, [r7, #15] + 80121a4: e001 b.n 80121aa + 80121a6: 2300 movs r3, #0 + 80121a8: 73fb strb r3, [r7, #15] + if (err == ERR_ABRT) { + 80121aa: f997 300f ldrsb.w r3, [r7, #15] + 80121ae: f113 0f0d cmn.w r3, #13 + 80121b2: d110 bne.n 80121d6 + return ERR_ABRT; + 80121b4: f06f 030c mvn.w r3, #12 + 80121b8: e00e b.n 80121d8 + } + } + } else if (err == ERR_ABRT) { + 80121ba: f997 300f ldrsb.w r3, [r7, #15] + 80121be: f113 0f0d cmn.w r3, #13 + 80121c2: d102 bne.n 80121ca + /* if err == ERR_ABRT, 'pcb' is already deallocated */ + /* Drop incoming packets because pcb is "full" (only if the incoming + segment contains data). */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); + return ERR_ABRT; + 80121c4: f06f 030c mvn.w r3, #12 + 80121c8: e006 b.n 80121d8 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(refused_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = refused_data; + 80121ca: 687b ldr r3, [r7, #4] + 80121cc: 68ba ldr r2, [r7, #8] + 80121ce: 679a str r2, [r3, #120] ; 0x78 + return ERR_INPROGRESS; + 80121d0: f06f 0304 mvn.w r3, #4 + 80121d4: e000 b.n 80121d8 + } + } + return ERR_OK; + 80121d6: 2300 movs r3, #0 +} + 80121d8: 4618 mov r0, r3 + 80121da: 3714 adds r7, #20 + 80121dc: 46bd mov sp, r7 + 80121de: bd90 pop {r4, r7, pc} + 80121e0: 0801f520 .word 0x0801f520 + 80121e4: 0801fa30 .word 0x0801fa30 + 80121e8: 0801f564 .word 0x0801f564 + +080121ec : + * + * @param seg tcp_seg list of TCP segments to free + */ +void +tcp_segs_free(struct tcp_seg *seg) +{ + 80121ec: b580 push {r7, lr} + 80121ee: b084 sub sp, #16 + 80121f0: af00 add r7, sp, #0 + 80121f2: 6078 str r0, [r7, #4] + while (seg != NULL) { + 80121f4: e007 b.n 8012206 + struct tcp_seg *next = seg->next; + 80121f6: 687b ldr r3, [r7, #4] + 80121f8: 681b ldr r3, [r3, #0] + 80121fa: 60fb str r3, [r7, #12] + tcp_seg_free(seg); + 80121fc: 6878 ldr r0, [r7, #4] + 80121fe: f000 f80a bl 8012216 + seg = next; + 8012202: 68fb ldr r3, [r7, #12] + 8012204: 607b str r3, [r7, #4] + while (seg != NULL) { + 8012206: 687b ldr r3, [r7, #4] + 8012208: 2b00 cmp r3, #0 + 801220a: d1f4 bne.n 80121f6 + } +} + 801220c: bf00 nop + 801220e: bf00 nop + 8012210: 3710 adds r7, #16 + 8012212: 46bd mov sp, r7 + 8012214: bd80 pop {r7, pc} + +08012216 : + * + * @param seg single tcp_seg to free + */ +void +tcp_seg_free(struct tcp_seg *seg) +{ + 8012216: b580 push {r7, lr} + 8012218: b082 sub sp, #8 + 801221a: af00 add r7, sp, #0 + 801221c: 6078 str r0, [r7, #4] + if (seg != NULL) { + 801221e: 687b ldr r3, [r7, #4] + 8012220: 2b00 cmp r3, #0 + 8012222: d00c beq.n 801223e + if (seg->p != NULL) { + 8012224: 687b ldr r3, [r7, #4] + 8012226: 685b ldr r3, [r3, #4] + 8012228: 2b00 cmp r3, #0 + 801222a: d004 beq.n 8012236 + pbuf_free(seg->p); + 801222c: 687b ldr r3, [r7, #4] + 801222e: 685b ldr r3, [r3, #4] + 8012230: 4618 mov r0, r3 + 8012232: f7fe fbe5 bl 8010a00 +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + 8012236: 6879 ldr r1, [r7, #4] + 8012238: 2003 movs r0, #3 + 801223a: f7fd fd31 bl 800fca0 + } +} + 801223e: bf00 nop + 8012240: 3708 adds r7, #8 + 8012242: 46bd mov sp, r7 + 8012244: bd80 pop {r7, pc} + ... + +08012248 : + * @param seg the old tcp_seg + * @return a copy of seg + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + 8012248: b580 push {r7, lr} + 801224a: b084 sub sp, #16 + 801224c: af00 add r7, sp, #0 + 801224e: 6078 str r0, [r7, #4] + struct tcp_seg *cseg; + + LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL); + 8012250: 687b ldr r3, [r7, #4] + 8012252: 2b00 cmp r3, #0 + 8012254: d106 bne.n 8012264 + 8012256: 4b0f ldr r3, [pc, #60] ; (8012294 ) + 8012258: f240 6282 movw r2, #1666 ; 0x682 + 801225c: 490e ldr r1, [pc, #56] ; (8012298 ) + 801225e: 480f ldr r0, [pc, #60] ; (801229c ) + 8012260: f009 fed8 bl 801c014 + + cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); + 8012264: 2003 movs r0, #3 + 8012266: f7fd fca5 bl 800fbb4 + 801226a: 60f8 str r0, [r7, #12] + if (cseg == NULL) { + 801226c: 68fb ldr r3, [r7, #12] + 801226e: 2b00 cmp r3, #0 + 8012270: d101 bne.n 8012276 + return NULL; + 8012272: 2300 movs r3, #0 + 8012274: e00a b.n 801228c + } + SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + 8012276: 2210 movs r2, #16 + 8012278: 6879 ldr r1, [r7, #4] + 801227a: 68f8 ldr r0, [r7, #12] + 801227c: f009 fe05 bl 801be8a + pbuf_ref(cseg->p); + 8012280: 68fb ldr r3, [r7, #12] + 8012282: 685b ldr r3, [r3, #4] + 8012284: 4618 mov r0, r3 + 8012286: f7fe fc61 bl 8010b4c + return cseg; + 801228a: 68fb ldr r3, [r7, #12] +} + 801228c: 4618 mov r0, r3 + 801228e: 3710 adds r7, #16 + 8012290: 46bd mov sp, r7 + 8012292: bd80 pop {r7, pc} + 8012294: 0801f520 .word 0x0801f520 + 8012298: 0801fa74 .word 0x0801fa74 + 801229c: 0801f564 .word 0x0801f564 + +080122a0 : + * Default receive callback that is called if the user didn't register + * a recv callback for the pcb. + */ +err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + 80122a0: b580 push {r7, lr} + 80122a2: b084 sub sp, #16 + 80122a4: af00 add r7, sp, #0 + 80122a6: 60f8 str r0, [r7, #12] + 80122a8: 60b9 str r1, [r7, #8] + 80122aa: 607a str r2, [r7, #4] + 80122ac: 70fb strb r3, [r7, #3] + LWIP_UNUSED_ARG(arg); + + LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG); + 80122ae: 68bb ldr r3, [r7, #8] + 80122b0: 2b00 cmp r3, #0 + 80122b2: d109 bne.n 80122c8 + 80122b4: 4b12 ldr r3, [pc, #72] ; (8012300 ) + 80122b6: f44f 62d3 mov.w r2, #1688 ; 0x698 + 80122ba: 4912 ldr r1, [pc, #72] ; (8012304 ) + 80122bc: 4812 ldr r0, [pc, #72] ; (8012308 ) + 80122be: f009 fea9 bl 801c014 + 80122c2: f06f 030f mvn.w r3, #15 + 80122c6: e016 b.n 80122f6 + + if (p != NULL) { + 80122c8: 687b ldr r3, [r7, #4] + 80122ca: 2b00 cmp r3, #0 + 80122cc: d009 beq.n 80122e2 + tcp_recved(pcb, p->tot_len); + 80122ce: 687b ldr r3, [r7, #4] + 80122d0: 891b ldrh r3, [r3, #8] + 80122d2: 4619 mov r1, r3 + 80122d4: 68b8 ldr r0, [r7, #8] + 80122d6: f7ff fb19 bl 801190c + pbuf_free(p); + 80122da: 6878 ldr r0, [r7, #4] + 80122dc: f7fe fb90 bl 8010a00 + 80122e0: e008 b.n 80122f4 + } else if (err == ERR_OK) { + 80122e2: f997 3003 ldrsb.w r3, [r7, #3] + 80122e6: 2b00 cmp r3, #0 + 80122e8: d104 bne.n 80122f4 + return tcp_close(pcb); + 80122ea: 68b8 ldr r0, [r7, #8] + 80122ec: f7ff f9be bl 801166c + 80122f0: 4603 mov r3, r0 + 80122f2: e000 b.n 80122f6 + } + return ERR_OK; + 80122f4: 2300 movs r3, #0 +} + 80122f6: 4618 mov r0, r3 + 80122f8: 3710 adds r7, #16 + 80122fa: 46bd mov sp, r7 + 80122fc: bd80 pop {r7, pc} + 80122fe: bf00 nop + 8012300: 0801f520 .word 0x0801f520 + 8012304: 0801fa90 .word 0x0801fa90 + 8012308: 0801f564 .word 0x0801f564 + +0801230c : + * + * @param prio minimum priority + */ +static void +tcp_kill_prio(u8_t prio) +{ + 801230c: b580 push {r7, lr} + 801230e: b086 sub sp, #24 + 8012310: af00 add r7, sp, #0 + 8012312: 4603 mov r3, r0 + 8012314: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + mprio = LWIP_MIN(TCP_PRIO_MAX, prio); + 8012316: f997 3007 ldrsb.w r3, [r7, #7] + 801231a: 2b00 cmp r3, #0 + 801231c: db01 blt.n 8012322 + 801231e: 79fb ldrb r3, [r7, #7] + 8012320: e000 b.n 8012324 + 8012322: 237f movs r3, #127 ; 0x7f + 8012324: 72fb strb r3, [r7, #11] + + /* We want to kill connections with a lower prio, so bail out if + * supplied prio is 0 - there can never be a lower prio + */ + if (mprio == 0) { + 8012326: 7afb ldrb r3, [r7, #11] + 8012328: 2b00 cmp r3, #0 + 801232a: d034 beq.n 8012396 + /* We only want kill connections with a lower prio, so decrement prio by one + * and start searching for oldest connection with same or lower priority than mprio. + * We want to find the connections with the lowest possible prio, and among + * these the one with the longest inactivity time. + */ + mprio--; + 801232c: 7afb ldrb r3, [r7, #11] + 801232e: 3b01 subs r3, #1 + 8012330: 72fb strb r3, [r7, #11] + + inactivity = 0; + 8012332: 2300 movs r3, #0 + 8012334: 60fb str r3, [r7, #12] + inactive = NULL; + 8012336: 2300 movs r3, #0 + 8012338: 613b str r3, [r7, #16] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 801233a: 4b19 ldr r3, [pc, #100] ; (80123a0 ) + 801233c: 681b ldr r3, [r3, #0] + 801233e: 617b str r3, [r7, #20] + 8012340: e01f b.n 8012382 + /* lower prio is always a kill candidate */ + if ((pcb->prio < mprio) || + 8012342: 697b ldr r3, [r7, #20] + 8012344: 7d5b ldrb r3, [r3, #21] + 8012346: 7afa ldrb r2, [r7, #11] + 8012348: 429a cmp r2, r3 + 801234a: d80c bhi.n 8012366 + /* longer inactivity is also a kill candidate */ + ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { + 801234c: 697b ldr r3, [r7, #20] + 801234e: 7d5b ldrb r3, [r3, #21] + if ((pcb->prio < mprio) || + 8012350: 7afa ldrb r2, [r7, #11] + 8012352: 429a cmp r2, r3 + 8012354: d112 bne.n 801237c + ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { + 8012356: 4b13 ldr r3, [pc, #76] ; (80123a4 ) + 8012358: 681a ldr r2, [r3, #0] + 801235a: 697b ldr r3, [r7, #20] + 801235c: 6a1b ldr r3, [r3, #32] + 801235e: 1ad3 subs r3, r2, r3 + 8012360: 68fa ldr r2, [r7, #12] + 8012362: 429a cmp r2, r3 + 8012364: d80a bhi.n 801237c + inactivity = tcp_ticks - pcb->tmr; + 8012366: 4b0f ldr r3, [pc, #60] ; (80123a4 ) + 8012368: 681a ldr r2, [r3, #0] + 801236a: 697b ldr r3, [r7, #20] + 801236c: 6a1b ldr r3, [r3, #32] + 801236e: 1ad3 subs r3, r2, r3 + 8012370: 60fb str r3, [r7, #12] + inactive = pcb; + 8012372: 697b ldr r3, [r7, #20] + 8012374: 613b str r3, [r7, #16] + mprio = pcb->prio; + 8012376: 697b ldr r3, [r7, #20] + 8012378: 7d5b ldrb r3, [r3, #21] + 801237a: 72fb strb r3, [r7, #11] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 801237c: 697b ldr r3, [r7, #20] + 801237e: 68db ldr r3, [r3, #12] + 8012380: 617b str r3, [r7, #20] + 8012382: 697b ldr r3, [r7, #20] + 8012384: 2b00 cmp r3, #0 + 8012386: d1dc bne.n 8012342 + } + } + if (inactive != NULL) { + 8012388: 693b ldr r3, [r7, #16] + 801238a: 2b00 cmp r3, #0 + 801238c: d004 beq.n 8012398 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + 801238e: 6938 ldr r0, [r7, #16] + 8012390: f7ff fa56 bl 8011840 + 8012394: e000 b.n 8012398 + return; + 8012396: bf00 nop + } +} + 8012398: 3718 adds r7, #24 + 801239a: 46bd mov sp, r7 + 801239c: bd80 pop {r7, pc} + 801239e: bf00 nop + 80123a0: 2000cf3c .word 0x2000cf3c + 80123a4: 2000cf30 .word 0x2000cf30 + +080123a8 : + * Kills the oldest connection that is in specific state. + * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available. + */ +static void +tcp_kill_state(enum tcp_state state) +{ + 80123a8: b580 push {r7, lr} + 80123aa: b086 sub sp, #24 + 80123ac: af00 add r7, sp, #0 + 80123ae: 4603 mov r3, r0 + 80123b0: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK)); + 80123b2: 79fb ldrb r3, [r7, #7] + 80123b4: 2b08 cmp r3, #8 + 80123b6: d009 beq.n 80123cc + 80123b8: 79fb ldrb r3, [r7, #7] + 80123ba: 2b09 cmp r3, #9 + 80123bc: d006 beq.n 80123cc + 80123be: 4b1a ldr r3, [pc, #104] ; (8012428 ) + 80123c0: f240 62dd movw r2, #1757 ; 0x6dd + 80123c4: 4919 ldr r1, [pc, #100] ; (801242c ) + 80123c6: 481a ldr r0, [pc, #104] ; (8012430 ) + 80123c8: f009 fe24 bl 801c014 + + inactivity = 0; + 80123cc: 2300 movs r3, #0 + 80123ce: 60fb str r3, [r7, #12] + inactive = NULL; + 80123d0: 2300 movs r3, #0 + 80123d2: 613b str r3, [r7, #16] + /* Go through the list of active pcbs and get the oldest pcb that is in state + CLOSING/LAST_ACK. */ + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 80123d4: 4b17 ldr r3, [pc, #92] ; (8012434 ) + 80123d6: 681b ldr r3, [r3, #0] + 80123d8: 617b str r3, [r7, #20] + 80123da: e017 b.n 801240c + if (pcb->state == state) { + 80123dc: 697b ldr r3, [r7, #20] + 80123de: 7d1b ldrb r3, [r3, #20] + 80123e0: 79fa ldrb r2, [r7, #7] + 80123e2: 429a cmp r2, r3 + 80123e4: d10f bne.n 8012406 + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + 80123e6: 4b14 ldr r3, [pc, #80] ; (8012438 ) + 80123e8: 681a ldr r2, [r3, #0] + 80123ea: 697b ldr r3, [r7, #20] + 80123ec: 6a1b ldr r3, [r3, #32] + 80123ee: 1ad3 subs r3, r2, r3 + 80123f0: 68fa ldr r2, [r7, #12] + 80123f2: 429a cmp r2, r3 + 80123f4: d807 bhi.n 8012406 + inactivity = tcp_ticks - pcb->tmr; + 80123f6: 4b10 ldr r3, [pc, #64] ; (8012438 ) + 80123f8: 681a ldr r2, [r3, #0] + 80123fa: 697b ldr r3, [r7, #20] + 80123fc: 6a1b ldr r3, [r3, #32] + 80123fe: 1ad3 subs r3, r2, r3 + 8012400: 60fb str r3, [r7, #12] + inactive = pcb; + 8012402: 697b ldr r3, [r7, #20] + 8012404: 613b str r3, [r7, #16] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8012406: 697b ldr r3, [r7, #20] + 8012408: 68db ldr r3, [r3, #12] + 801240a: 617b str r3, [r7, #20] + 801240c: 697b ldr r3, [r7, #20] + 801240e: 2b00 cmp r3, #0 + 8012410: d1e4 bne.n 80123dc + } + } + } + if (inactive != NULL) { + 8012412: 693b ldr r3, [r7, #16] + 8012414: 2b00 cmp r3, #0 + 8012416: d003 beq.n 8012420 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n", + tcp_state_str[state], (void *)inactive, inactivity)); + /* Don't send a RST, since no data is lost. */ + tcp_abandon(inactive, 0); + 8012418: 2100 movs r1, #0 + 801241a: 6938 ldr r0, [r7, #16] + 801241c: f7ff f952 bl 80116c4 + } +} + 8012420: bf00 nop + 8012422: 3718 adds r7, #24 + 8012424: 46bd mov sp, r7 + 8012426: bd80 pop {r7, pc} + 8012428: 0801f520 .word 0x0801f520 + 801242c: 0801faac .word 0x0801faac + 8012430: 0801f564 .word 0x0801f564 + 8012434: 2000cf3c .word 0x2000cf3c + 8012438: 2000cf30 .word 0x2000cf30 + +0801243c : + * Kills the oldest connection that is in TIME_WAIT state. + * Called from tcp_alloc() if no more connections are available. + */ +static void +tcp_kill_timewait(void) +{ + 801243c: b580 push {r7, lr} + 801243e: b084 sub sp, #16 + 8012440: af00 add r7, sp, #0 + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + 8012442: 2300 movs r3, #0 + 8012444: 607b str r3, [r7, #4] + inactive = NULL; + 8012446: 2300 movs r3, #0 + 8012448: 60bb str r3, [r7, #8] + /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 801244a: 4b12 ldr r3, [pc, #72] ; (8012494 ) + 801244c: 681b ldr r3, [r3, #0] + 801244e: 60fb str r3, [r7, #12] + 8012450: e012 b.n 8012478 + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + 8012452: 4b11 ldr r3, [pc, #68] ; (8012498 ) + 8012454: 681a ldr r2, [r3, #0] + 8012456: 68fb ldr r3, [r7, #12] + 8012458: 6a1b ldr r3, [r3, #32] + 801245a: 1ad3 subs r3, r2, r3 + 801245c: 687a ldr r2, [r7, #4] + 801245e: 429a cmp r2, r3 + 8012460: d807 bhi.n 8012472 + inactivity = tcp_ticks - pcb->tmr; + 8012462: 4b0d ldr r3, [pc, #52] ; (8012498 ) + 8012464: 681a ldr r2, [r3, #0] + 8012466: 68fb ldr r3, [r7, #12] + 8012468: 6a1b ldr r3, [r3, #32] + 801246a: 1ad3 subs r3, r2, r3 + 801246c: 607b str r3, [r7, #4] + inactive = pcb; + 801246e: 68fb ldr r3, [r7, #12] + 8012470: 60bb str r3, [r7, #8] + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 8012472: 68fb ldr r3, [r7, #12] + 8012474: 68db ldr r3, [r3, #12] + 8012476: 60fb str r3, [r7, #12] + 8012478: 68fb ldr r3, [r7, #12] + 801247a: 2b00 cmp r3, #0 + 801247c: d1e9 bne.n 8012452 + } + } + if (inactive != NULL) { + 801247e: 68bb ldr r3, [r7, #8] + 8012480: 2b00 cmp r3, #0 + 8012482: d002 beq.n 801248a + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + 8012484: 68b8 ldr r0, [r7, #8] + 8012486: f7ff f9db bl 8011840 + } +} + 801248a: bf00 nop + 801248c: 3710 adds r7, #16 + 801248e: 46bd mov sp, r7 + 8012490: bd80 pop {r7, pc} + 8012492: bf00 nop + 8012494: 2000cf40 .word 0x2000cf40 + 8012498: 2000cf30 .word 0x2000cf30 + +0801249c : + * now send the FIN (which failed before), the pcb might be in a state that is + * OK for us to now free it. + */ +static void +tcp_handle_closepend(void) +{ + 801249c: b580 push {r7, lr} + 801249e: b082 sub sp, #8 + 80124a0: af00 add r7, sp, #0 + struct tcp_pcb *pcb = tcp_active_pcbs; + 80124a2: 4b10 ldr r3, [pc, #64] ; (80124e4 ) + 80124a4: 681b ldr r3, [r3, #0] + 80124a6: 607b str r3, [r7, #4] + + while (pcb != NULL) { + 80124a8: e014 b.n 80124d4 + struct tcp_pcb *next = pcb->next; + 80124aa: 687b ldr r3, [r7, #4] + 80124ac: 68db ldr r3, [r3, #12] + 80124ae: 603b str r3, [r7, #0] + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + 80124b0: 687b ldr r3, [r7, #4] + 80124b2: 8b5b ldrh r3, [r3, #26] + 80124b4: f003 0308 and.w r3, r3, #8 + 80124b8: 2b00 cmp r3, #0 + 80124ba: d009 beq.n 80124d0 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + 80124bc: 687b ldr r3, [r7, #4] + 80124be: 8b5b ldrh r3, [r3, #26] + 80124c0: f023 0308 bic.w r3, r3, #8 + 80124c4: b29a uxth r2, r3 + 80124c6: 687b ldr r3, [r7, #4] + 80124c8: 835a strh r2, [r3, #26] + tcp_close_shutdown_fin(pcb); + 80124ca: 6878 ldr r0, [r7, #4] + 80124cc: f7ff f864 bl 8011598 + } + pcb = next; + 80124d0: 683b ldr r3, [r7, #0] + 80124d2: 607b str r3, [r7, #4] + while (pcb != NULL) { + 80124d4: 687b ldr r3, [r7, #4] + 80124d6: 2b00 cmp r3, #0 + 80124d8: d1e7 bne.n 80124aa + } +} + 80124da: bf00 nop + 80124dc: bf00 nop + 80124de: 3708 adds r7, #8 + 80124e0: 46bd mov sp, r7 + 80124e2: bd80 pop {r7, pc} + 80124e4: 2000cf3c .word 0x2000cf3c + +080124e8 : + * @param prio priority for the new pcb + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + 80124e8: b580 push {r7, lr} + 80124ea: b084 sub sp, #16 + 80124ec: af00 add r7, sp, #0 + 80124ee: 4603 mov r3, r0 + 80124f0: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 80124f2: 2001 movs r0, #1 + 80124f4: f7fd fb5e bl 800fbb4 + 80124f8: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 80124fa: 68fb ldr r3, [r7, #12] + 80124fc: 2b00 cmp r3, #0 + 80124fe: d126 bne.n 801254e + /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */ + tcp_handle_closepend(); + 8012500: f7ff ffcc bl 801249c + + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + 8012504: f7ff ff9a bl 801243c + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8012508: 2001 movs r0, #1 + 801250a: f7fd fb53 bl 800fbb4 + 801250e: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8012510: 68fb ldr r3, [r7, #12] + 8012512: 2b00 cmp r3, #0 + 8012514: d11b bne.n 801254e + /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n")); + tcp_kill_state(LAST_ACK); + 8012516: 2009 movs r0, #9 + 8012518: f7ff ff46 bl 80123a8 + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 801251c: 2001 movs r0, #1 + 801251e: f7fd fb49 bl 800fbb4 + 8012522: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8012524: 68fb ldr r3, [r7, #12] + 8012526: 2b00 cmp r3, #0 + 8012528: d111 bne.n 801254e + /* Try killing oldest connection in CLOSING. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n")); + tcp_kill_state(CLOSING); + 801252a: 2008 movs r0, #8 + 801252c: f7ff ff3c bl 80123a8 + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8012530: 2001 movs r0, #1 + 8012532: f7fd fb3f bl 800fbb4 + 8012536: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8012538: 68fb ldr r3, [r7, #12] + 801253a: 2b00 cmp r3, #0 + 801253c: d107 bne.n 801254e + /* Try killing oldest active connection with lower priority than the new one. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio)); + tcp_kill_prio(prio); + 801253e: 79fb ldrb r3, [r7, #7] + 8012540: 4618 mov r0, r3 + 8012542: f7ff fee3 bl 801230c + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8012546: 2001 movs r0, #1 + 8012548: f7fd fb34 bl 800fbb4 + 801254c: 60f8 str r0, [r7, #12] + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed above */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + 801254e: 68fb ldr r3, [r7, #12] + 8012550: 2b00 cmp r3, #0 + 8012552: d03f beq.n 80125d4 + /* zero out the whole pcb, so there is no need to initialize members to zero */ + memset(pcb, 0, sizeof(struct tcp_pcb)); + 8012554: 229c movs r2, #156 ; 0x9c + 8012556: 2100 movs r1, #0 + 8012558: 68f8 ldr r0, [r7, #12] + 801255a: f009 fcbe bl 801beda + pcb->prio = prio; + 801255e: 68fb ldr r3, [r7, #12] + 8012560: 79fa ldrb r2, [r7, #7] + 8012562: 755a strb r2, [r3, #21] + pcb->snd_buf = TCP_SND_BUF; + 8012564: 68fb ldr r3, [r7, #12] + 8012566: f44f 6286 mov.w r2, #1072 ; 0x430 + 801256a: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 + /* Start with a window that does not need scaling. When window scaling is + enabled and used, the window is enlarged when both sides agree on scaling. */ + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); + 801256e: 68fb ldr r3, [r7, #12] + 8012570: f44f 6206 mov.w r2, #2144 ; 0x860 + 8012574: 855a strh r2, [r3, #42] ; 0x2a + 8012576: 68fb ldr r3, [r7, #12] + 8012578: 8d5a ldrh r2, [r3, #42] ; 0x2a + 801257a: 68fb ldr r3, [r7, #12] + 801257c: 851a strh r2, [r3, #40] ; 0x28 + pcb->ttl = TCP_TTL; + 801257e: 68fb ldr r3, [r7, #12] + 8012580: 22ff movs r2, #255 ; 0xff + 8012582: 72da strb r2, [r3, #11] + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = INITIAL_MSS; + 8012584: 68fb ldr r3, [r7, #12] + 8012586: f44f 7206 mov.w r2, #536 ; 0x218 + 801258a: 865a strh r2, [r3, #50] ; 0x32 + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + 801258c: 68fb ldr r3, [r7, #12] + 801258e: 2206 movs r2, #6 + 8012590: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + 8012594: 68fb ldr r3, [r7, #12] + 8012596: 2206 movs r2, #6 + 8012598: 87da strh r2, [r3, #62] ; 0x3e + pcb->rtime = -1; + 801259a: 68fb ldr r3, [r7, #12] + 801259c: f64f 72ff movw r2, #65535 ; 0xffff + 80125a0: 861a strh r2, [r3, #48] ; 0x30 + pcb->cwnd = 1; + 80125a2: 68fb ldr r3, [r7, #12] + 80125a4: 2201 movs r2, #1 + 80125a6: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->tmr = tcp_ticks; + 80125aa: 4b0d ldr r3, [pc, #52] ; (80125e0 ) + 80125ac: 681a ldr r2, [r3, #0] + 80125ae: 68fb ldr r3, [r7, #12] + 80125b0: 621a str r2, [r3, #32] + pcb->last_timer = tcp_timer_ctr; + 80125b2: 4b0c ldr r3, [pc, #48] ; (80125e4 ) + 80125b4: 781a ldrb r2, [r3, #0] + 80125b6: 68fb ldr r3, [r7, #12] + 80125b8: 779a strb r2, [r3, #30] + of using the largest advertised receive window. We've seen complications with + receiving TCPs that use window scaling and/or window auto-tuning where the + initial advertised window is very small and then grows rapidly once the + connection is established. To avoid these complications, we set ssthresh to the + largest effective cwnd (amount of in-flight data) that the sender can have. */ + pcb->ssthresh = TCP_SND_BUF; + 80125ba: 68fb ldr r3, [r7, #12] + 80125bc: f44f 6286 mov.w r2, #1072 ; 0x430 + 80125c0: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; + 80125c4: 68fb ldr r3, [r7, #12] + 80125c6: 4a08 ldr r2, [pc, #32] ; (80125e8 ) + 80125c8: f8c3 2084 str.w r2, [r3, #132] ; 0x84 +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; + 80125cc: 68fb ldr r3, [r7, #12] + 80125ce: 4a07 ldr r2, [pc, #28] ; (80125ec ) + 80125d0: f8c3 2094 str.w r2, [r3, #148] ; 0x94 +#if LWIP_TCP_KEEPALIVE + pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; + pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; +#endif /* LWIP_TCP_KEEPALIVE */ + } + return pcb; + 80125d4: 68fb ldr r3, [r7, #12] +} + 80125d6: 4618 mov r0, r3 + 80125d8: 3710 adds r7, #16 + 80125da: 46bd mov sp, r7 + 80125dc: bd80 pop {r7, pc} + 80125de: bf00 nop + 80125e0: 2000cf30 .word 0x2000cf30 + 80125e4: 2000cf46 .word 0x2000cf46 + 80125e8: 080122a1 .word 0x080122a1 + 80125ec: 006ddd00 .word 0x006ddd00 + +080125f0 : + * + * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + 80125f0: b580 push {r7, lr} + 80125f2: b082 sub sp, #8 + 80125f4: af00 add r7, sp, #0 + 80125f6: 6078 str r0, [r7, #4] + LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return); + 80125f8: 687b ldr r3, [r7, #4] + 80125fa: 2b00 cmp r3, #0 + 80125fc: d107 bne.n 801260e + 80125fe: 4b21 ldr r3, [pc, #132] ; (8012684 ) + 8012600: f640 0251 movw r2, #2129 ; 0x851 + 8012604: 4920 ldr r1, [pc, #128] ; (8012688 ) + 8012606: 4821 ldr r0, [pc, #132] ; (801268c ) + 8012608: f009 fd04 bl 801c014 + 801260c: e037 b.n 801267e + + if (pcb->state != CLOSED && + 801260e: 687b ldr r3, [r7, #4] + 8012610: 7d1b ldrb r3, [r3, #20] + 8012612: 2b00 cmp r3, #0 + 8012614: d033 beq.n 801267e + pcb->state != TIME_WAIT && + 8012616: 687b ldr r3, [r7, #4] + 8012618: 7d1b ldrb r3, [r3, #20] + if (pcb->state != CLOSED && + 801261a: 2b0a cmp r3, #10 + 801261c: d02f beq.n 801267e + pcb->state != LISTEN) { + 801261e: 687b ldr r3, [r7, #4] + 8012620: 7d1b ldrb r3, [r3, #20] + pcb->state != TIME_WAIT && + 8012622: 2b01 cmp r3, #1 + 8012624: d02b beq.n 801267e + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + + tcp_backlog_accepted(pcb); + + if (pcb->refused_data != NULL) { + 8012626: 687b ldr r3, [r7, #4] + 8012628: 6f9b ldr r3, [r3, #120] ; 0x78 + 801262a: 2b00 cmp r3, #0 + 801262c: d007 beq.n 801263e + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); + pbuf_free(pcb->refused_data); + 801262e: 687b ldr r3, [r7, #4] + 8012630: 6f9b ldr r3, [r3, #120] ; 0x78 + 8012632: 4618 mov r0, r3 + 8012634: f7fe f9e4 bl 8010a00 + pcb->refused_data = NULL; + 8012638: 687b ldr r3, [r7, #4] + 801263a: 2200 movs r2, #0 + 801263c: 679a str r2, [r3, #120] ; 0x78 + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + 801263e: 687b ldr r3, [r7, #4] + 8012640: 6f5b ldr r3, [r3, #116] ; 0x74 + 8012642: 2b00 cmp r3, #0 + 8012644: d002 beq.n 801264c + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + tcp_free_ooseq(pcb); + 8012646: 6878 ldr r0, [r7, #4] + 8012648: f000 f986 bl 8012958 + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Stop the retransmission timer as it will expect data on unacked + queue if it fires */ + pcb->rtime = -1; + 801264c: 687b ldr r3, [r7, #4] + 801264e: f64f 72ff movw r2, #65535 ; 0xffff + 8012652: 861a strh r2, [r3, #48] ; 0x30 + + tcp_segs_free(pcb->unsent); + 8012654: 687b ldr r3, [r7, #4] + 8012656: 6edb ldr r3, [r3, #108] ; 0x6c + 8012658: 4618 mov r0, r3 + 801265a: f7ff fdc7 bl 80121ec + tcp_segs_free(pcb->unacked); + 801265e: 687b ldr r3, [r7, #4] + 8012660: 6f1b ldr r3, [r3, #112] ; 0x70 + 8012662: 4618 mov r0, r3 + 8012664: f7ff fdc2 bl 80121ec + pcb->unacked = pcb->unsent = NULL; + 8012668: 687b ldr r3, [r7, #4] + 801266a: 2200 movs r2, #0 + 801266c: 66da str r2, [r3, #108] ; 0x6c + 801266e: 687b ldr r3, [r7, #4] + 8012670: 6eda ldr r2, [r3, #108] ; 0x6c + 8012672: 687b ldr r3, [r7, #4] + 8012674: 671a str r2, [r3, #112] ; 0x70 +#if TCP_OVERSIZE + pcb->unsent_oversize = 0; + 8012676: 687b ldr r3, [r7, #4] + 8012678: 2200 movs r2, #0 + 801267a: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +#endif /* TCP_OVERSIZE */ + } +} + 801267e: 3708 adds r7, #8 + 8012680: 46bd mov sp, r7 + 8012682: bd80 pop {r7, pc} + 8012684: 0801f520 .word 0x0801f520 + 8012688: 0801fb6c .word 0x0801fb6c + 801268c: 0801f564 .word 0x0801f564 + +08012690 : + * @param pcblist PCB list to purge. + * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + 8012690: b580 push {r7, lr} + 8012692: b084 sub sp, #16 + 8012694: af00 add r7, sp, #0 + 8012696: 6078 str r0, [r7, #4] + 8012698: 6039 str r1, [r7, #0] + LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL); + 801269a: 683b ldr r3, [r7, #0] + 801269c: 2b00 cmp r3, #0 + 801269e: d106 bne.n 80126ae + 80126a0: 4b3e ldr r3, [pc, #248] ; (801279c ) + 80126a2: f640 0283 movw r2, #2179 ; 0x883 + 80126a6: 493e ldr r1, [pc, #248] ; (80127a0 ) + 80126a8: 483e ldr r0, [pc, #248] ; (80127a4 ) + 80126aa: f009 fcb3 bl 801c014 + LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL); + 80126ae: 687b ldr r3, [r7, #4] + 80126b0: 2b00 cmp r3, #0 + 80126b2: d106 bne.n 80126c2 + 80126b4: 4b39 ldr r3, [pc, #228] ; (801279c ) + 80126b6: f640 0284 movw r2, #2180 ; 0x884 + 80126ba: 493b ldr r1, [pc, #236] ; (80127a8 ) + 80126bc: 4839 ldr r0, [pc, #228] ; (80127a4 ) + 80126be: f009 fca9 bl 801c014 + + TCP_RMV(pcblist, pcb); + 80126c2: 687b ldr r3, [r7, #4] + 80126c4: 681b ldr r3, [r3, #0] + 80126c6: 683a ldr r2, [r7, #0] + 80126c8: 429a cmp r2, r3 + 80126ca: d105 bne.n 80126d8 + 80126cc: 687b ldr r3, [r7, #4] + 80126ce: 681b ldr r3, [r3, #0] + 80126d0: 68da ldr r2, [r3, #12] + 80126d2: 687b ldr r3, [r7, #4] + 80126d4: 601a str r2, [r3, #0] + 80126d6: e013 b.n 8012700 + 80126d8: 687b ldr r3, [r7, #4] + 80126da: 681b ldr r3, [r3, #0] + 80126dc: 60fb str r3, [r7, #12] + 80126de: e00c b.n 80126fa + 80126e0: 68fb ldr r3, [r7, #12] + 80126e2: 68db ldr r3, [r3, #12] + 80126e4: 683a ldr r2, [r7, #0] + 80126e6: 429a cmp r2, r3 + 80126e8: d104 bne.n 80126f4 + 80126ea: 683b ldr r3, [r7, #0] + 80126ec: 68da ldr r2, [r3, #12] + 80126ee: 68fb ldr r3, [r7, #12] + 80126f0: 60da str r2, [r3, #12] + 80126f2: e005 b.n 8012700 + 80126f4: 68fb ldr r3, [r7, #12] + 80126f6: 68db ldr r3, [r3, #12] + 80126f8: 60fb str r3, [r7, #12] + 80126fa: 68fb ldr r3, [r7, #12] + 80126fc: 2b00 cmp r3, #0 + 80126fe: d1ef bne.n 80126e0 + 8012700: 683b ldr r3, [r7, #0] + 8012702: 2200 movs r2, #0 + 8012704: 60da str r2, [r3, #12] + + tcp_pcb_purge(pcb); + 8012706: 6838 ldr r0, [r7, #0] + 8012708: f7ff ff72 bl 80125f0 + + /* if there is an outstanding delayed ACKs, send it */ + if ((pcb->state != TIME_WAIT) && + 801270c: 683b ldr r3, [r7, #0] + 801270e: 7d1b ldrb r3, [r3, #20] + 8012710: 2b0a cmp r3, #10 + 8012712: d013 beq.n 801273c + (pcb->state != LISTEN) && + 8012714: 683b ldr r3, [r7, #0] + 8012716: 7d1b ldrb r3, [r3, #20] + if ((pcb->state != TIME_WAIT) && + 8012718: 2b01 cmp r3, #1 + 801271a: d00f beq.n 801273c + (pcb->flags & TF_ACK_DELAY)) { + 801271c: 683b ldr r3, [r7, #0] + 801271e: 8b5b ldrh r3, [r3, #26] + 8012720: f003 0301 and.w r3, r3, #1 + (pcb->state != LISTEN) && + 8012724: 2b00 cmp r3, #0 + 8012726: d009 beq.n 801273c + tcp_ack_now(pcb); + 8012728: 683b ldr r3, [r7, #0] + 801272a: 8b5b ldrh r3, [r3, #26] + 801272c: f043 0302 orr.w r3, r3, #2 + 8012730: b29a uxth r2, r3 + 8012732: 683b ldr r3, [r7, #0] + 8012734: 835a strh r2, [r3, #26] + tcp_output(pcb); + 8012736: 6838 ldr r0, [r7, #0] + 8012738: f002 ff6e bl 8015618 + } + + if (pcb->state != LISTEN) { + 801273c: 683b ldr r3, [r7, #0] + 801273e: 7d1b ldrb r3, [r3, #20] + 8012740: 2b01 cmp r3, #1 + 8012742: d020 beq.n 8012786 + LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); + 8012744: 683b ldr r3, [r7, #0] + 8012746: 6edb ldr r3, [r3, #108] ; 0x6c + 8012748: 2b00 cmp r3, #0 + 801274a: d006 beq.n 801275a + 801274c: 4b13 ldr r3, [pc, #76] ; (801279c ) + 801274e: f640 0293 movw r2, #2195 ; 0x893 + 8012752: 4916 ldr r1, [pc, #88] ; (80127ac ) + 8012754: 4813 ldr r0, [pc, #76] ; (80127a4 ) + 8012756: f009 fc5d bl 801c014 + LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); + 801275a: 683b ldr r3, [r7, #0] + 801275c: 6f1b ldr r3, [r3, #112] ; 0x70 + 801275e: 2b00 cmp r3, #0 + 8012760: d006 beq.n 8012770 + 8012762: 4b0e ldr r3, [pc, #56] ; (801279c ) + 8012764: f640 0294 movw r2, #2196 ; 0x894 + 8012768: 4911 ldr r1, [pc, #68] ; (80127b0 ) + 801276a: 480e ldr r0, [pc, #56] ; (80127a4 ) + 801276c: f009 fc52 bl 801c014 +#if TCP_QUEUE_OOSEQ + LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); + 8012770: 683b ldr r3, [r7, #0] + 8012772: 6f5b ldr r3, [r3, #116] ; 0x74 + 8012774: 2b00 cmp r3, #0 + 8012776: d006 beq.n 8012786 + 8012778: 4b08 ldr r3, [pc, #32] ; (801279c ) + 801277a: f640 0296 movw r2, #2198 ; 0x896 + 801277e: 490d ldr r1, [pc, #52] ; (80127b4 ) + 8012780: 4808 ldr r0, [pc, #32] ; (80127a4 ) + 8012782: f009 fc47 bl 801c014 +#endif /* TCP_QUEUE_OOSEQ */ + } + + pcb->state = CLOSED; + 8012786: 683b ldr r3, [r7, #0] + 8012788: 2200 movs r2, #0 + 801278a: 751a strb r2, [r3, #20] + /* reset the local port to prevent the pcb from being 'bound' */ + pcb->local_port = 0; + 801278c: 683b ldr r3, [r7, #0] + 801278e: 2200 movs r2, #0 + 8012790: 82da strh r2, [r3, #22] + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + 8012792: bf00 nop + 8012794: 3710 adds r7, #16 + 8012796: 46bd mov sp, r7 + 8012798: bd80 pop {r7, pc} + 801279a: bf00 nop + 801279c: 0801f520 .word 0x0801f520 + 80127a0: 0801fb88 .word 0x0801fb88 + 80127a4: 0801f564 .word 0x0801f564 + 80127a8: 0801fba4 .word 0x0801fba4 + 80127ac: 0801fbc4 .word 0x0801fbc4 + 80127b0: 0801fbdc .word 0x0801fbdc + 80127b4: 0801fbf8 .word 0x0801fbf8 + +080127b8 : + * + * @return u32_t pseudo random sequence number + */ +u32_t +tcp_next_iss(struct tcp_pcb *pcb) +{ + 80127b8: b580 push {r7, lr} + 80127ba: b082 sub sp, #8 + 80127bc: af00 add r7, sp, #0 + 80127be: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port); +#else /* LWIP_HOOK_TCP_ISN */ + static u32_t iss = 6510; + + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + 80127c0: 687b ldr r3, [r7, #4] + 80127c2: 2b00 cmp r3, #0 + 80127c4: d106 bne.n 80127d4 + 80127c6: 4b0a ldr r3, [pc, #40] ; (80127f0 ) + 80127c8: f640 02af movw r2, #2223 ; 0x8af + 80127cc: 4909 ldr r1, [pc, #36] ; (80127f4 ) + 80127ce: 480a ldr r0, [pc, #40] ; (80127f8 ) + 80127d0: f009 fc20 bl 801c014 + LWIP_UNUSED_ARG(pcb); + + iss += tcp_ticks; /* XXX */ + 80127d4: 4b09 ldr r3, [pc, #36] ; (80127fc ) + 80127d6: 681a ldr r2, [r3, #0] + 80127d8: 4b09 ldr r3, [pc, #36] ; (8012800 ) + 80127da: 681b ldr r3, [r3, #0] + 80127dc: 4413 add r3, r2 + 80127de: 4a07 ldr r2, [pc, #28] ; (80127fc ) + 80127e0: 6013 str r3, [r2, #0] + return iss; + 80127e2: 4b06 ldr r3, [pc, #24] ; (80127fc ) + 80127e4: 681b ldr r3, [r3, #0] +#endif /* LWIP_HOOK_TCP_ISN */ +} + 80127e6: 4618 mov r0, r3 + 80127e8: 3708 adds r7, #8 + 80127ea: 46bd mov sp, r7 + 80127ec: bd80 pop {r7, pc} + 80127ee: bf00 nop + 80127f0: 0801f520 .word 0x0801f520 + 80127f4: 0801fc10 .word 0x0801fc10 + 80127f8: 0801f564 .word 0x0801f564 + 80127fc: 200000b8 .word 0x200000b8 + 8012800: 2000cf30 .word 0x2000cf30 + +08012804 : + * by calculating the minimum of TCP_MSS and the mtu (if set) of the target + * netif (if not NULL). + */ +u16_t +tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest) +{ + 8012804: b580 push {r7, lr} + 8012806: b086 sub sp, #24 + 8012808: af00 add r7, sp, #0 + 801280a: 4603 mov r3, r0 + 801280c: 60b9 str r1, [r7, #8] + 801280e: 607a str r2, [r7, #4] + 8012810: 81fb strh r3, [r7, #14] + u16_t mss_s; + u16_t mtu; + + LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */ + + LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL); + 8012812: 687b ldr r3, [r7, #4] + 8012814: 2b00 cmp r3, #0 + 8012816: d106 bne.n 8012826 + 8012818: 4b14 ldr r3, [pc, #80] ; (801286c ) + 801281a: f640 02c5 movw r2, #2245 ; 0x8c5 + 801281e: 4914 ldr r1, [pc, #80] ; (8012870 ) + 8012820: 4814 ldr r0, [pc, #80] ; (8012874 ) + 8012822: f009 fbf7 bl 801c014 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + if (outif == NULL) { + 8012826: 68bb ldr r3, [r7, #8] + 8012828: 2b00 cmp r3, #0 + 801282a: d101 bne.n 8012830 + return sendmss; + 801282c: 89fb ldrh r3, [r7, #14] + 801282e: e019 b.n 8012864 + } + mtu = outif->mtu; + 8012830: 68bb ldr r3, [r7, #8] + 8012832: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8012834: 82fb strh r3, [r7, #22] + } +#endif /* LWIP_IPV4 */ + + if (mtu != 0) { + 8012836: 8afb ldrh r3, [r7, #22] + 8012838: 2b00 cmp r3, #0 + 801283a: d012 beq.n 8012862 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + offset = IP_HLEN + TCP_HLEN; + 801283c: 2328 movs r3, #40 ; 0x28 + 801283e: 82bb strh r3, [r7, #20] + } +#endif /* LWIP_IPV4 */ + mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0; + 8012840: 8afa ldrh r2, [r7, #22] + 8012842: 8abb ldrh r3, [r7, #20] + 8012844: 429a cmp r2, r3 + 8012846: d904 bls.n 8012852 + 8012848: 8afa ldrh r2, [r7, #22] + 801284a: 8abb ldrh r3, [r7, #20] + 801284c: 1ad3 subs r3, r2, r3 + 801284e: b29b uxth r3, r3 + 8012850: e000 b.n 8012854 + 8012852: 2300 movs r3, #0 + 8012854: 827b strh r3, [r7, #18] + /* RFC 1122, chap 4.2.2.6: + * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize + * We correct for TCP options in tcp_write(), and don't support IP options. + */ + sendmss = LWIP_MIN(sendmss, mss_s); + 8012856: 8a7a ldrh r2, [r7, #18] + 8012858: 89fb ldrh r3, [r7, #14] + 801285a: 4293 cmp r3, r2 + 801285c: bf28 it cs + 801285e: 4613 movcs r3, r2 + 8012860: 81fb strh r3, [r7, #14] + } + return sendmss; + 8012862: 89fb ldrh r3, [r7, #14] +} + 8012864: 4618 mov r0, r3 + 8012866: 3718 adds r7, #24 + 8012868: 46bd mov sp, r7 + 801286a: bd80 pop {r7, pc} + 801286c: 0801f520 .word 0x0801f520 + 8012870: 0801fc2c .word 0x0801fc2c + 8012874: 0801f564 .word 0x0801f564 + +08012878 : +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */ +static void +tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list) +{ + 8012878: b580 push {r7, lr} + 801287a: b084 sub sp, #16 + 801287c: af00 add r7, sp, #0 + 801287e: 6078 str r0, [r7, #4] + 8012880: 6039 str r1, [r7, #0] + struct tcp_pcb *pcb; + pcb = pcb_list; + 8012882: 683b ldr r3, [r7, #0] + 8012884: 60fb str r3, [r7, #12] + + LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL); + 8012886: 687b ldr r3, [r7, #4] + 8012888: 2b00 cmp r3, #0 + 801288a: d119 bne.n 80128c0 + 801288c: 4b10 ldr r3, [pc, #64] ; (80128d0 ) + 801288e: f44f 6210 mov.w r2, #2304 ; 0x900 + 8012892: 4910 ldr r1, [pc, #64] ; (80128d4 ) + 8012894: 4810 ldr r0, [pc, #64] ; (80128d8 ) + 8012896: f009 fbbd bl 801c014 + + while (pcb != NULL) { + 801289a: e011 b.n 80128c0 + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&pcb->local_ip, old_addr) + 801289c: 68fb ldr r3, [r7, #12] + 801289e: 681a ldr r2, [r3, #0] + 80128a0: 687b ldr r3, [r7, #4] + 80128a2: 681b ldr r3, [r3, #0] + 80128a4: 429a cmp r2, r3 + 80128a6: d108 bne.n 80128ba + /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ + && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip))) +#endif /* LWIP_AUTOIP */ + ) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + 80128a8: 68fb ldr r3, [r7, #12] + 80128aa: 68db ldr r3, [r3, #12] + 80128ac: 60bb str r3, [r7, #8] + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + tcp_abort(pcb); + 80128ae: 68f8 ldr r0, [r7, #12] + 80128b0: f7fe ffc6 bl 8011840 + pcb = next; + 80128b4: 68bb ldr r3, [r7, #8] + 80128b6: 60fb str r3, [r7, #12] + 80128b8: e002 b.n 80128c0 + } else { + pcb = pcb->next; + 80128ba: 68fb ldr r3, [r7, #12] + 80128bc: 68db ldr r3, [r3, #12] + 80128be: 60fb str r3, [r7, #12] + while (pcb != NULL) { + 80128c0: 68fb ldr r3, [r7, #12] + 80128c2: 2b00 cmp r3, #0 + 80128c4: d1ea bne.n 801289c + } + } +} + 80128c6: bf00 nop + 80128c8: bf00 nop + 80128ca: 3710 adds r7, #16 + 80128cc: 46bd mov sp, r7 + 80128ce: bd80 pop {r7, pc} + 80128d0: 0801f520 .word 0x0801f520 + 80128d4: 0801fc54 .word 0x0801fc54 + 80128d8: 0801f564 .word 0x0801f564 + +080128dc : + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change or NULL if netif has been removed + */ +void +tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 80128dc: b580 push {r7, lr} + 80128de: b084 sub sp, #16 + 80128e0: af00 add r7, sp, #0 + 80128e2: 6078 str r0, [r7, #4] + 80128e4: 6039 str r1, [r7, #0] + struct tcp_pcb_listen *lpcb; + + if (!ip_addr_isany(old_addr)) { + 80128e6: 687b ldr r3, [r7, #4] + 80128e8: 2b00 cmp r3, #0 + 80128ea: d02a beq.n 8012942 + 80128ec: 687b ldr r3, [r7, #4] + 80128ee: 681b ldr r3, [r3, #0] + 80128f0: 2b00 cmp r3, #0 + 80128f2: d026 beq.n 8012942 + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs); + 80128f4: 4b15 ldr r3, [pc, #84] ; (801294c ) + 80128f6: 681b ldr r3, [r3, #0] + 80128f8: 4619 mov r1, r3 + 80128fa: 6878 ldr r0, [r7, #4] + 80128fc: f7ff ffbc bl 8012878 + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs); + 8012900: 4b13 ldr r3, [pc, #76] ; (8012950 ) + 8012902: 681b ldr r3, [r3, #0] + 8012904: 4619 mov r1, r3 + 8012906: 6878 ldr r0, [r7, #4] + 8012908: f7ff ffb6 bl 8012878 + + if (!ip_addr_isany(new_addr)) { + 801290c: 683b ldr r3, [r7, #0] + 801290e: 2b00 cmp r3, #0 + 8012910: d017 beq.n 8012942 + 8012912: 683b ldr r3, [r7, #0] + 8012914: 681b ldr r3, [r3, #0] + 8012916: 2b00 cmp r3, #0 + 8012918: d013 beq.n 8012942 + /* PCB bound to current local interface address? */ + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 801291a: 4b0e ldr r3, [pc, #56] ; (8012954 ) + 801291c: 681b ldr r3, [r3, #0] + 801291e: 60fb str r3, [r7, #12] + 8012920: e00c b.n 801293c + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&lpcb->local_ip, old_addr)) { + 8012922: 68fb ldr r3, [r7, #12] + 8012924: 681a ldr r2, [r3, #0] + 8012926: 687b ldr r3, [r7, #4] + 8012928: 681b ldr r3, [r3, #0] + 801292a: 429a cmp r2, r3 + 801292c: d103 bne.n 8012936 + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_copy(lpcb->local_ip, *new_addr); + 801292e: 683b ldr r3, [r7, #0] + 8012930: 681a ldr r2, [r3, #0] + 8012932: 68fb ldr r3, [r7, #12] + 8012934: 601a str r2, [r3, #0] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8012936: 68fb ldr r3, [r7, #12] + 8012938: 68db ldr r3, [r3, #12] + 801293a: 60fb str r3, [r7, #12] + 801293c: 68fb ldr r3, [r7, #12] + 801293e: 2b00 cmp r3, #0 + 8012940: d1ef bne.n 8012922 + } + } + } + } +} + 8012942: bf00 nop + 8012944: 3710 adds r7, #16 + 8012946: 46bd mov sp, r7 + 8012948: bd80 pop {r7, pc} + 801294a: bf00 nop + 801294c: 2000cf3c .word 0x2000cf3c + 8012950: 2000cf34 .word 0x2000cf34 + 8012954: 2000cf38 .word 0x2000cf38 + +08012958 : + +#if TCP_QUEUE_OOSEQ +/* Free all ooseq pbufs (and possibly reset SACK state) */ +void +tcp_free_ooseq(struct tcp_pcb *pcb) +{ + 8012958: b580 push {r7, lr} + 801295a: b082 sub sp, #8 + 801295c: af00 add r7, sp, #0 + 801295e: 6078 str r0, [r7, #4] + if (pcb->ooseq) { + 8012960: 687b ldr r3, [r7, #4] + 8012962: 6f5b ldr r3, [r3, #116] ; 0x74 + 8012964: 2b00 cmp r3, #0 + 8012966: d007 beq.n 8012978 + tcp_segs_free(pcb->ooseq); + 8012968: 687b ldr r3, [r7, #4] + 801296a: 6f5b ldr r3, [r3, #116] ; 0x74 + 801296c: 4618 mov r0, r3 + 801296e: f7ff fc3d bl 80121ec + pcb->ooseq = NULL; + 8012972: 687b ldr r3, [r7, #4] + 8012974: 2200 movs r2, #0 + 8012976: 675a str r2, [r3, #116] ; 0x74 +#if LWIP_TCP_SACK_OUT + memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks)); +#endif /* LWIP_TCP_SACK_OUT */ + } +} + 8012978: bf00 nop + 801297a: 3708 adds r7, #8 + 801297c: 46bd mov sp, r7 + 801297e: bd80 pop {r7, pc} + +08012980 : + * @param p received TCP segment to process (p->payload pointing to the TCP header) + * @param inp network interface on which this segment was received + */ +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + 8012980: b590 push {r4, r7, lr} + 8012982: b08d sub sp, #52 ; 0x34 + 8012984: af04 add r7, sp, #16 + 8012986: 6078 str r0, [r7, #4] + 8012988: 6039 str r1, [r7, #0] + u8_t hdrlen_bytes; + err_t err; + + LWIP_UNUSED_ARG(inp); + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL); + 801298a: 687b ldr r3, [r7, #4] + 801298c: 2b00 cmp r3, #0 + 801298e: d105 bne.n 801299c + 8012990: 4b9b ldr r3, [pc, #620] ; (8012c00 ) + 8012992: 2283 movs r2, #131 ; 0x83 + 8012994: 499b ldr r1, [pc, #620] ; (8012c04 ) + 8012996: 489c ldr r0, [pc, #624] ; (8012c08 ) + 8012998: f009 fb3c bl 801c014 + PERF_START; + + TCP_STATS_INC(tcp.recv); + MIB2_STATS_INC(mib2.tcpinsegs); + + tcphdr = (struct tcp_hdr *)p->payload; + 801299c: 687b ldr r3, [r7, #4] + 801299e: 685b ldr r3, [r3, #4] + 80129a0: 4a9a ldr r2, [pc, #616] ; (8012c0c ) + 80129a2: 6013 str r3, [r2, #0] +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* Check that TCP header fits in payload */ + if (p->len < TCP_HLEN) { + 80129a4: 687b ldr r3, [r7, #4] + 80129a6: 895b ldrh r3, [r3, #10] + 80129a8: 2b13 cmp r3, #19 + 80129aa: f240 83d1 bls.w 8013150 + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || + 80129ae: 4b98 ldr r3, [pc, #608] ; (8012c10 ) + 80129b0: 695b ldr r3, [r3, #20] + 80129b2: 4a97 ldr r2, [pc, #604] ; (8012c10 ) + 80129b4: 6812 ldr r2, [r2, #0] + 80129b6: 4611 mov r1, r2 + 80129b8: 4618 mov r0, r3 + 80129ba: f007 ff13 bl 801a7e4 + 80129be: 4603 mov r3, r0 + 80129c0: 2b00 cmp r3, #0 + 80129c2: f040 83c7 bne.w 8013154 + ip_addr_ismulticast(ip_current_dest_addr())) { + 80129c6: 4b92 ldr r3, [pc, #584] ; (8012c10 ) + 80129c8: 695b ldr r3, [r3, #20] + 80129ca: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || + 80129ce: 2be0 cmp r3, #224 ; 0xe0 + 80129d0: f000 83c0 beq.w 8013154 + } + } +#endif /* CHECKSUM_CHECK_TCP */ + + /* sanity-check header length */ + hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr); + 80129d4: 4b8d ldr r3, [pc, #564] ; (8012c0c ) + 80129d6: 681b ldr r3, [r3, #0] + 80129d8: 899b ldrh r3, [r3, #12] + 80129da: b29b uxth r3, r3 + 80129dc: 4618 mov r0, r3 + 80129de: f7fb fc27 bl 800e230 + 80129e2: 4603 mov r3, r0 + 80129e4: 0b1b lsrs r3, r3, #12 + 80129e6: b29b uxth r3, r3 + 80129e8: b2db uxtb r3, r3 + 80129ea: 009b lsls r3, r3, #2 + 80129ec: 74bb strb r3, [r7, #18] + if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) { + 80129ee: 7cbb ldrb r3, [r7, #18] + 80129f0: 2b13 cmp r3, #19 + 80129f2: f240 83b1 bls.w 8013158 + 80129f6: 7cbb ldrb r3, [r7, #18] + 80129f8: b29a uxth r2, r3 + 80129fa: 687b ldr r3, [r7, #4] + 80129fc: 891b ldrh r3, [r3, #8] + 80129fe: 429a cmp r2, r3 + 8012a00: f200 83aa bhi.w 8013158 + goto dropped; + } + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN); + 8012a04: 7cbb ldrb r3, [r7, #18] + 8012a06: b29b uxth r3, r3 + 8012a08: 3b14 subs r3, #20 + 8012a0a: b29a uxth r2, r3 + 8012a0c: 4b81 ldr r3, [pc, #516] ; (8012c14 ) + 8012a0e: 801a strh r2, [r3, #0] + tcphdr_opt2 = NULL; + 8012a10: 4b81 ldr r3, [pc, #516] ; (8012c18 ) + 8012a12: 2200 movs r2, #0 + 8012a14: 601a str r2, [r3, #0] + if (p->len >= hdrlen_bytes) { + 8012a16: 687b ldr r3, [r7, #4] + 8012a18: 895a ldrh r2, [r3, #10] + 8012a1a: 7cbb ldrb r3, [r7, #18] + 8012a1c: b29b uxth r3, r3 + 8012a1e: 429a cmp r2, r3 + 8012a20: d309 bcc.n 8012a36 + /* all options are in the first pbuf */ + tcphdr_opt1len = tcphdr_optlen; + 8012a22: 4b7c ldr r3, [pc, #496] ; (8012c14 ) + 8012a24: 881a ldrh r2, [r3, #0] + 8012a26: 4b7d ldr r3, [pc, #500] ; (8012c1c ) + 8012a28: 801a strh r2, [r3, #0] + pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */ + 8012a2a: 7cbb ldrb r3, [r7, #18] + 8012a2c: 4619 mov r1, r3 + 8012a2e: 6878 ldr r0, [r7, #4] + 8012a30: f7fd ff60 bl 80108f4 + 8012a34: e04e b.n 8012ad4 + } else { + u16_t opt2len; + /* TCP header fits into first pbuf, options don't - data is in the next pbuf */ + /* there must be a next pbuf, due to hdrlen_bytes sanity check above */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + 8012a36: 687b ldr r3, [r7, #4] + 8012a38: 681b ldr r3, [r3, #0] + 8012a3a: 2b00 cmp r3, #0 + 8012a3c: d105 bne.n 8012a4a + 8012a3e: 4b70 ldr r3, [pc, #448] ; (8012c00 ) + 8012a40: 22c2 movs r2, #194 ; 0xc2 + 8012a42: 4977 ldr r1, [pc, #476] ; (8012c20 ) + 8012a44: 4870 ldr r0, [pc, #448] ; (8012c08 ) + 8012a46: f009 fae5 bl 801c014 + + /* advance over the TCP header (cannot fail) */ + pbuf_remove_header(p, TCP_HLEN); + 8012a4a: 2114 movs r1, #20 + 8012a4c: 6878 ldr r0, [r7, #4] + 8012a4e: f7fd ff51 bl 80108f4 + + /* determine how long the first and second parts of the options are */ + tcphdr_opt1len = p->len; + 8012a52: 687b ldr r3, [r7, #4] + 8012a54: 895a ldrh r2, [r3, #10] + 8012a56: 4b71 ldr r3, [pc, #452] ; (8012c1c ) + 8012a58: 801a strh r2, [r3, #0] + opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len); + 8012a5a: 4b6e ldr r3, [pc, #440] ; (8012c14 ) + 8012a5c: 881a ldrh r2, [r3, #0] + 8012a5e: 4b6f ldr r3, [pc, #444] ; (8012c1c ) + 8012a60: 881b ldrh r3, [r3, #0] + 8012a62: 1ad3 subs r3, r2, r3 + 8012a64: 823b strh r3, [r7, #16] + + /* options continue in the next pbuf: set p to zero length and hide the + options in the next pbuf (adjusting p->tot_len) */ + pbuf_remove_header(p, tcphdr_opt1len); + 8012a66: 4b6d ldr r3, [pc, #436] ; (8012c1c ) + 8012a68: 881b ldrh r3, [r3, #0] + 8012a6a: 4619 mov r1, r3 + 8012a6c: 6878 ldr r0, [r7, #4] + 8012a6e: f7fd ff41 bl 80108f4 + + /* check that the options fit in the second pbuf */ + if (opt2len > p->next->len) { + 8012a72: 687b ldr r3, [r7, #4] + 8012a74: 681b ldr r3, [r3, #0] + 8012a76: 895b ldrh r3, [r3, #10] + 8012a78: 8a3a ldrh r2, [r7, #16] + 8012a7a: 429a cmp r2, r3 + 8012a7c: f200 836e bhi.w 801315c + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* remember the pointer to the second part of the options */ + tcphdr_opt2 = (u8_t *)p->next->payload; + 8012a80: 687b ldr r3, [r7, #4] + 8012a82: 681b ldr r3, [r3, #0] + 8012a84: 685b ldr r3, [r3, #4] + 8012a86: 4a64 ldr r2, [pc, #400] ; (8012c18 ) + 8012a88: 6013 str r3, [r2, #0] + + /* advance p->next to point after the options, and manually + adjust p->tot_len to keep it consistent with the changed p->next */ + pbuf_remove_header(p->next, opt2len); + 8012a8a: 687b ldr r3, [r7, #4] + 8012a8c: 681b ldr r3, [r3, #0] + 8012a8e: 8a3a ldrh r2, [r7, #16] + 8012a90: 4611 mov r1, r2 + 8012a92: 4618 mov r0, r3 + 8012a94: f7fd ff2e bl 80108f4 + p->tot_len = (u16_t)(p->tot_len - opt2len); + 8012a98: 687b ldr r3, [r7, #4] + 8012a9a: 891a ldrh r2, [r3, #8] + 8012a9c: 8a3b ldrh r3, [r7, #16] + 8012a9e: 1ad3 subs r3, r2, r3 + 8012aa0: b29a uxth r2, r3 + 8012aa2: 687b ldr r3, [r7, #4] + 8012aa4: 811a strh r2, [r3, #8] + + LWIP_ASSERT("p->len == 0", p->len == 0); + 8012aa6: 687b ldr r3, [r7, #4] + 8012aa8: 895b ldrh r3, [r3, #10] + 8012aaa: 2b00 cmp r3, #0 + 8012aac: d005 beq.n 8012aba + 8012aae: 4b54 ldr r3, [pc, #336] ; (8012c00 ) + 8012ab0: 22df movs r2, #223 ; 0xdf + 8012ab2: 495c ldr r1, [pc, #368] ; (8012c24 ) + 8012ab4: 4854 ldr r0, [pc, #336] ; (8012c08 ) + 8012ab6: f009 faad bl 801c014 + LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len); + 8012aba: 687b ldr r3, [r7, #4] + 8012abc: 891a ldrh r2, [r3, #8] + 8012abe: 687b ldr r3, [r7, #4] + 8012ac0: 681b ldr r3, [r3, #0] + 8012ac2: 891b ldrh r3, [r3, #8] + 8012ac4: 429a cmp r2, r3 + 8012ac6: d005 beq.n 8012ad4 + 8012ac8: 4b4d ldr r3, [pc, #308] ; (8012c00 ) + 8012aca: 22e0 movs r2, #224 ; 0xe0 + 8012acc: 4956 ldr r1, [pc, #344] ; (8012c28 ) + 8012ace: 484e ldr r0, [pc, #312] ; (8012c08 ) + 8012ad0: f009 faa0 bl 801c014 + } + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = lwip_ntohs(tcphdr->src); + 8012ad4: 4b4d ldr r3, [pc, #308] ; (8012c0c ) + 8012ad6: 681b ldr r3, [r3, #0] + 8012ad8: 881b ldrh r3, [r3, #0] + 8012ada: b29b uxth r3, r3 + 8012adc: 4a4b ldr r2, [pc, #300] ; (8012c0c ) + 8012ade: 6814 ldr r4, [r2, #0] + 8012ae0: 4618 mov r0, r3 + 8012ae2: f7fb fba5 bl 800e230 + 8012ae6: 4603 mov r3, r0 + 8012ae8: 8023 strh r3, [r4, #0] + tcphdr->dest = lwip_ntohs(tcphdr->dest); + 8012aea: 4b48 ldr r3, [pc, #288] ; (8012c0c ) + 8012aec: 681b ldr r3, [r3, #0] + 8012aee: 885b ldrh r3, [r3, #2] + 8012af0: b29b uxth r3, r3 + 8012af2: 4a46 ldr r2, [pc, #280] ; (8012c0c ) + 8012af4: 6814 ldr r4, [r2, #0] + 8012af6: 4618 mov r0, r3 + 8012af8: f7fb fb9a bl 800e230 + 8012afc: 4603 mov r3, r0 + 8012afe: 8063 strh r3, [r4, #2] + seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno); + 8012b00: 4b42 ldr r3, [pc, #264] ; (8012c0c ) + 8012b02: 681b ldr r3, [r3, #0] + 8012b04: 685b ldr r3, [r3, #4] + 8012b06: 4a41 ldr r2, [pc, #260] ; (8012c0c ) + 8012b08: 6814 ldr r4, [r2, #0] + 8012b0a: 4618 mov r0, r3 + 8012b0c: f7fb fba5 bl 800e25a + 8012b10: 4603 mov r3, r0 + 8012b12: 6063 str r3, [r4, #4] + 8012b14: 6863 ldr r3, [r4, #4] + 8012b16: 4a45 ldr r2, [pc, #276] ; (8012c2c ) + 8012b18: 6013 str r3, [r2, #0] + ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno); + 8012b1a: 4b3c ldr r3, [pc, #240] ; (8012c0c ) + 8012b1c: 681b ldr r3, [r3, #0] + 8012b1e: 689b ldr r3, [r3, #8] + 8012b20: 4a3a ldr r2, [pc, #232] ; (8012c0c ) + 8012b22: 6814 ldr r4, [r2, #0] + 8012b24: 4618 mov r0, r3 + 8012b26: f7fb fb98 bl 800e25a + 8012b2a: 4603 mov r3, r0 + 8012b2c: 60a3 str r3, [r4, #8] + 8012b2e: 68a3 ldr r3, [r4, #8] + 8012b30: 4a3f ldr r2, [pc, #252] ; (8012c30 ) + 8012b32: 6013 str r3, [r2, #0] + tcphdr->wnd = lwip_ntohs(tcphdr->wnd); + 8012b34: 4b35 ldr r3, [pc, #212] ; (8012c0c ) + 8012b36: 681b ldr r3, [r3, #0] + 8012b38: 89db ldrh r3, [r3, #14] + 8012b3a: b29b uxth r3, r3 + 8012b3c: 4a33 ldr r2, [pc, #204] ; (8012c0c ) + 8012b3e: 6814 ldr r4, [r2, #0] + 8012b40: 4618 mov r0, r3 + 8012b42: f7fb fb75 bl 800e230 + 8012b46: 4603 mov r3, r0 + 8012b48: 81e3 strh r3, [r4, #14] + + flags = TCPH_FLAGS(tcphdr); + 8012b4a: 4b30 ldr r3, [pc, #192] ; (8012c0c ) + 8012b4c: 681b ldr r3, [r3, #0] + 8012b4e: 899b ldrh r3, [r3, #12] + 8012b50: b29b uxth r3, r3 + 8012b52: 4618 mov r0, r3 + 8012b54: f7fb fb6c bl 800e230 + 8012b58: 4603 mov r3, r0 + 8012b5a: b2db uxtb r3, r3 + 8012b5c: f003 033f and.w r3, r3, #63 ; 0x3f + 8012b60: b2da uxtb r2, r3 + 8012b62: 4b34 ldr r3, [pc, #208] ; (8012c34 ) + 8012b64: 701a strb r2, [r3, #0] + tcplen = p->tot_len; + 8012b66: 687b ldr r3, [r7, #4] + 8012b68: 891a ldrh r2, [r3, #8] + 8012b6a: 4b33 ldr r3, [pc, #204] ; (8012c38 ) + 8012b6c: 801a strh r2, [r3, #0] + if (flags & (TCP_FIN | TCP_SYN)) { + 8012b6e: 4b31 ldr r3, [pc, #196] ; (8012c34 ) + 8012b70: 781b ldrb r3, [r3, #0] + 8012b72: f003 0303 and.w r3, r3, #3 + 8012b76: 2b00 cmp r3, #0 + 8012b78: d00c beq.n 8012b94 + tcplen++; + 8012b7a: 4b2f ldr r3, [pc, #188] ; (8012c38 ) + 8012b7c: 881b ldrh r3, [r3, #0] + 8012b7e: 3301 adds r3, #1 + 8012b80: b29a uxth r2, r3 + 8012b82: 4b2d ldr r3, [pc, #180] ; (8012c38 ) + 8012b84: 801a strh r2, [r3, #0] + if (tcplen < p->tot_len) { + 8012b86: 687b ldr r3, [r7, #4] + 8012b88: 891a ldrh r2, [r3, #8] + 8012b8a: 4b2b ldr r3, [pc, #172] ; (8012c38 ) + 8012b8c: 881b ldrh r3, [r3, #0] + 8012b8e: 429a cmp r2, r3 + 8012b90: f200 82e6 bhi.w 8013160 + } + } + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + 8012b94: 2300 movs r3, #0 + 8012b96: 61bb str r3, [r7, #24] + + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8012b98: 4b28 ldr r3, [pc, #160] ; (8012c3c ) + 8012b9a: 681b ldr r3, [r3, #0] + 8012b9c: 61fb str r3, [r7, #28] + 8012b9e: e09d b.n 8012cdc + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + 8012ba0: 69fb ldr r3, [r7, #28] + 8012ba2: 7d1b ldrb r3, [r3, #20] + 8012ba4: 2b00 cmp r3, #0 + 8012ba6: d105 bne.n 8012bb4 + 8012ba8: 4b15 ldr r3, [pc, #84] ; (8012c00 ) + 8012baa: 22fb movs r2, #251 ; 0xfb + 8012bac: 4924 ldr r1, [pc, #144] ; (8012c40 ) + 8012bae: 4816 ldr r0, [pc, #88] ; (8012c08 ) + 8012bb0: f009 fa30 bl 801c014 + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + 8012bb4: 69fb ldr r3, [r7, #28] + 8012bb6: 7d1b ldrb r3, [r3, #20] + 8012bb8: 2b0a cmp r3, #10 + 8012bba: d105 bne.n 8012bc8 + 8012bbc: 4b10 ldr r3, [pc, #64] ; (8012c00 ) + 8012bbe: 22fc movs r2, #252 ; 0xfc + 8012bc0: 4920 ldr r1, [pc, #128] ; (8012c44 ) + 8012bc2: 4811 ldr r0, [pc, #68] ; (8012c08 ) + 8012bc4: f009 fa26 bl 801c014 + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + 8012bc8: 69fb ldr r3, [r7, #28] + 8012bca: 7d1b ldrb r3, [r3, #20] + 8012bcc: 2b01 cmp r3, #1 + 8012bce: d105 bne.n 8012bdc + 8012bd0: 4b0b ldr r3, [pc, #44] ; (8012c00 ) + 8012bd2: 22fd movs r2, #253 ; 0xfd + 8012bd4: 491c ldr r1, [pc, #112] ; (8012c48 ) + 8012bd6: 480c ldr r0, [pc, #48] ; (8012c08 ) + 8012bd8: f009 fa1c bl 801c014 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8012bdc: 69fb ldr r3, [r7, #28] + 8012bde: 7a1b ldrb r3, [r3, #8] + 8012be0: 2b00 cmp r3, #0 + 8012be2: d033 beq.n 8012c4c + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 8012be4: 69fb ldr r3, [r7, #28] + 8012be6: 7a1a ldrb r2, [r3, #8] + 8012be8: 4b09 ldr r3, [pc, #36] ; (8012c10 ) + 8012bea: 685b ldr r3, [r3, #4] + 8012bec: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 8012bf0: 3301 adds r3, #1 + 8012bf2: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8012bf4: 429a cmp r2, r3 + 8012bf6: d029 beq.n 8012c4c + prev = pcb; + 8012bf8: 69fb ldr r3, [r7, #28] + 8012bfa: 61bb str r3, [r7, #24] + continue; + 8012bfc: e06b b.n 8012cd6 + 8012bfe: bf00 nop + 8012c00: 0801fc88 .word 0x0801fc88 + 8012c04: 0801fcbc .word 0x0801fcbc + 8012c08: 0801fcd4 .word 0x0801fcd4 + 8012c0c: 2000cf58 .word 0x2000cf58 + 8012c10: 20009670 .word 0x20009670 + 8012c14: 2000cf5c .word 0x2000cf5c + 8012c18: 2000cf60 .word 0x2000cf60 + 8012c1c: 2000cf5e .word 0x2000cf5e + 8012c20: 0801fcfc .word 0x0801fcfc + 8012c24: 0801fd0c .word 0x0801fd0c + 8012c28: 0801fd18 .word 0x0801fd18 + 8012c2c: 2000cf68 .word 0x2000cf68 + 8012c30: 2000cf6c .word 0x2000cf6c + 8012c34: 2000cf74 .word 0x2000cf74 + 8012c38: 2000cf72 .word 0x2000cf72 + 8012c3c: 2000cf3c .word 0x2000cf3c + 8012c40: 0801fd38 .word 0x0801fd38 + 8012c44: 0801fd60 .word 0x0801fd60 + 8012c48: 0801fd8c .word 0x0801fd8c + } + + if (pcb->remote_port == tcphdr->src && + 8012c4c: 69fb ldr r3, [r7, #28] + 8012c4e: 8b1a ldrh r2, [r3, #24] + 8012c50: 4b72 ldr r3, [pc, #456] ; (8012e1c ) + 8012c52: 681b ldr r3, [r3, #0] + 8012c54: 881b ldrh r3, [r3, #0] + 8012c56: b29b uxth r3, r3 + 8012c58: 429a cmp r2, r3 + 8012c5a: d13a bne.n 8012cd2 + pcb->local_port == tcphdr->dest && + 8012c5c: 69fb ldr r3, [r7, #28] + 8012c5e: 8ada ldrh r2, [r3, #22] + 8012c60: 4b6e ldr r3, [pc, #440] ; (8012e1c ) + 8012c62: 681b ldr r3, [r3, #0] + 8012c64: 885b ldrh r3, [r3, #2] + 8012c66: b29b uxth r3, r3 + if (pcb->remote_port == tcphdr->src && + 8012c68: 429a cmp r2, r3 + 8012c6a: d132 bne.n 8012cd2 + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 8012c6c: 69fb ldr r3, [r7, #28] + 8012c6e: 685a ldr r2, [r3, #4] + 8012c70: 4b6b ldr r3, [pc, #428] ; (8012e20 ) + 8012c72: 691b ldr r3, [r3, #16] + pcb->local_port == tcphdr->dest && + 8012c74: 429a cmp r2, r3 + 8012c76: d12c bne.n 8012cd2 + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 8012c78: 69fb ldr r3, [r7, #28] + 8012c7a: 681a ldr r2, [r3, #0] + 8012c7c: 4b68 ldr r3, [pc, #416] ; (8012e20 ) + 8012c7e: 695b ldr r3, [r3, #20] + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 8012c80: 429a cmp r2, r3 + 8012c82: d126 bne.n 8012cd2 + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + 8012c84: 69fb ldr r3, [r7, #28] + 8012c86: 68db ldr r3, [r3, #12] + 8012c88: 69fa ldr r2, [r7, #28] + 8012c8a: 429a cmp r2, r3 + 8012c8c: d106 bne.n 8012c9c + 8012c8e: 4b65 ldr r3, [pc, #404] ; (8012e24 ) + 8012c90: f240 120d movw r2, #269 ; 0x10d + 8012c94: 4964 ldr r1, [pc, #400] ; (8012e28 ) + 8012c96: 4865 ldr r0, [pc, #404] ; (8012e2c ) + 8012c98: f009 f9bc bl 801c014 + if (prev != NULL) { + 8012c9c: 69bb ldr r3, [r7, #24] + 8012c9e: 2b00 cmp r3, #0 + 8012ca0: d00a beq.n 8012cb8 + prev->next = pcb->next; + 8012ca2: 69fb ldr r3, [r7, #28] + 8012ca4: 68da ldr r2, [r3, #12] + 8012ca6: 69bb ldr r3, [r7, #24] + 8012ca8: 60da str r2, [r3, #12] + pcb->next = tcp_active_pcbs; + 8012caa: 4b61 ldr r3, [pc, #388] ; (8012e30 ) + 8012cac: 681a ldr r2, [r3, #0] + 8012cae: 69fb ldr r3, [r7, #28] + 8012cb0: 60da str r2, [r3, #12] + tcp_active_pcbs = pcb; + 8012cb2: 4a5f ldr r2, [pc, #380] ; (8012e30 ) + 8012cb4: 69fb ldr r3, [r7, #28] + 8012cb6: 6013 str r3, [r2, #0] + } else { + TCP_STATS_INC(tcp.cachehit); + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + 8012cb8: 69fb ldr r3, [r7, #28] + 8012cba: 68db ldr r3, [r3, #12] + 8012cbc: 69fa ldr r2, [r7, #28] + 8012cbe: 429a cmp r2, r3 + 8012cc0: d111 bne.n 8012ce6 + 8012cc2: 4b58 ldr r3, [pc, #352] ; (8012e24 ) + 8012cc4: f240 1215 movw r2, #277 ; 0x115 + 8012cc8: 495a ldr r1, [pc, #360] ; (8012e34 ) + 8012cca: 4858 ldr r0, [pc, #352] ; (8012e2c ) + 8012ccc: f009 f9a2 bl 801c014 + break; + 8012cd0: e009 b.n 8012ce6 + } + prev = pcb; + 8012cd2: 69fb ldr r3, [r7, #28] + 8012cd4: 61bb str r3, [r7, #24] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8012cd6: 69fb ldr r3, [r7, #28] + 8012cd8: 68db ldr r3, [r3, #12] + 8012cda: 61fb str r3, [r7, #28] + 8012cdc: 69fb ldr r3, [r7, #28] + 8012cde: 2b00 cmp r3, #0 + 8012ce0: f47f af5e bne.w 8012ba0 + 8012ce4: e000 b.n 8012ce8 + break; + 8012ce6: bf00 nop + } + + if (pcb == NULL) { + 8012ce8: 69fb ldr r3, [r7, #28] + 8012cea: 2b00 cmp r3, #0 + 8012cec: f040 80aa bne.w 8012e44 + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 8012cf0: 4b51 ldr r3, [pc, #324] ; (8012e38 ) + 8012cf2: 681b ldr r3, [r3, #0] + 8012cf4: 61fb str r3, [r7, #28] + 8012cf6: e03f b.n 8012d78 + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + 8012cf8: 69fb ldr r3, [r7, #28] + 8012cfa: 7d1b ldrb r3, [r3, #20] + 8012cfc: 2b0a cmp r3, #10 + 8012cfe: d006 beq.n 8012d0e + 8012d00: 4b48 ldr r3, [pc, #288] ; (8012e24 ) + 8012d02: f240 121f movw r2, #287 ; 0x11f + 8012d06: 494d ldr r1, [pc, #308] ; (8012e3c ) + 8012d08: 4848 ldr r0, [pc, #288] ; (8012e2c ) + 8012d0a: f009 f983 bl 801c014 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8012d0e: 69fb ldr r3, [r7, #28] + 8012d10: 7a1b ldrb r3, [r3, #8] + 8012d12: 2b00 cmp r3, #0 + 8012d14: d009 beq.n 8012d2a + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 8012d16: 69fb ldr r3, [r7, #28] + 8012d18: 7a1a ldrb r2, [r3, #8] + 8012d1a: 4b41 ldr r3, [pc, #260] ; (8012e20 ) + 8012d1c: 685b ldr r3, [r3, #4] + 8012d1e: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 8012d22: 3301 adds r3, #1 + 8012d24: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8012d26: 429a cmp r2, r3 + 8012d28: d122 bne.n 8012d70 + continue; + } + + if (pcb->remote_port == tcphdr->src && + 8012d2a: 69fb ldr r3, [r7, #28] + 8012d2c: 8b1a ldrh r2, [r3, #24] + 8012d2e: 4b3b ldr r3, [pc, #236] ; (8012e1c ) + 8012d30: 681b ldr r3, [r3, #0] + 8012d32: 881b ldrh r3, [r3, #0] + 8012d34: b29b uxth r3, r3 + 8012d36: 429a cmp r2, r3 + 8012d38: d11b bne.n 8012d72 + pcb->local_port == tcphdr->dest && + 8012d3a: 69fb ldr r3, [r7, #28] + 8012d3c: 8ada ldrh r2, [r3, #22] + 8012d3e: 4b37 ldr r3, [pc, #220] ; (8012e1c ) + 8012d40: 681b ldr r3, [r3, #0] + 8012d42: 885b ldrh r3, [r3, #2] + 8012d44: b29b uxth r3, r3 + if (pcb->remote_port == tcphdr->src && + 8012d46: 429a cmp r2, r3 + 8012d48: d113 bne.n 8012d72 + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 8012d4a: 69fb ldr r3, [r7, #28] + 8012d4c: 685a ldr r2, [r3, #4] + 8012d4e: 4b34 ldr r3, [pc, #208] ; (8012e20 ) + 8012d50: 691b ldr r3, [r3, #16] + pcb->local_port == tcphdr->dest && + 8012d52: 429a cmp r2, r3 + 8012d54: d10d bne.n 8012d72 + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 8012d56: 69fb ldr r3, [r7, #28] + 8012d58: 681a ldr r2, [r3, #0] + 8012d5a: 4b31 ldr r3, [pc, #196] ; (8012e20 ) + 8012d5c: 695b ldr r3, [r3, #20] + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 8012d5e: 429a cmp r2, r3 + 8012d60: d107 bne.n 8012d72 +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len, + tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_timewait_input(pcb); + 8012d62: 69f8 ldr r0, [r7, #28] + 8012d64: f000 fb56 bl 8013414 + } + pbuf_free(p); + 8012d68: 6878 ldr r0, [r7, #4] + 8012d6a: f7fd fe49 bl 8010a00 + return; + 8012d6e: e1fd b.n 801316c + continue; + 8012d70: bf00 nop + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 8012d72: 69fb ldr r3, [r7, #28] + 8012d74: 68db ldr r3, [r3, #12] + 8012d76: 61fb str r3, [r7, #28] + 8012d78: 69fb ldr r3, [r7, #28] + 8012d7a: 2b00 cmp r3, #0 + 8012d7c: d1bc bne.n 8012cf8 + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + 8012d7e: 2300 movs r3, #0 + 8012d80: 61bb str r3, [r7, #24] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8012d82: 4b2f ldr r3, [pc, #188] ; (8012e40 ) + 8012d84: 681b ldr r3, [r3, #0] + 8012d86: 617b str r3, [r7, #20] + 8012d88: e02a b.n 8012de0 + /* check if PCB is bound to specific netif */ + if ((lpcb->netif_idx != NETIF_NO_INDEX) && + 8012d8a: 697b ldr r3, [r7, #20] + 8012d8c: 7a1b ldrb r3, [r3, #8] + 8012d8e: 2b00 cmp r3, #0 + 8012d90: d00c beq.n 8012dac + (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 8012d92: 697b ldr r3, [r7, #20] + 8012d94: 7a1a ldrb r2, [r3, #8] + 8012d96: 4b22 ldr r3, [pc, #136] ; (8012e20 ) + 8012d98: 685b ldr r3, [r3, #4] + 8012d9a: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 8012d9e: 3301 adds r3, #1 + 8012da0: b2db uxtb r3, r3 + if ((lpcb->netif_idx != NETIF_NO_INDEX) && + 8012da2: 429a cmp r2, r3 + 8012da4: d002 beq.n 8012dac + prev = (struct tcp_pcb *)lpcb; + 8012da6: 697b ldr r3, [r7, #20] + 8012da8: 61bb str r3, [r7, #24] + continue; + 8012daa: e016 b.n 8012dda + } + + if (lpcb->local_port == tcphdr->dest) { + 8012dac: 697b ldr r3, [r7, #20] + 8012dae: 8ada ldrh r2, [r3, #22] + 8012db0: 4b1a ldr r3, [pc, #104] ; (8012e1c ) + 8012db2: 681b ldr r3, [r3, #0] + 8012db4: 885b ldrh r3, [r3, #2] + 8012db6: b29b uxth r3, r3 + 8012db8: 429a cmp r2, r3 + 8012dba: d10c bne.n 8012dd6 + lpcb_prev = prev; +#else /* SO_REUSE */ + break; +#endif /* SO_REUSE */ + } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) { + if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) { + 8012dbc: 697b ldr r3, [r7, #20] + 8012dbe: 681a ldr r2, [r3, #0] + 8012dc0: 4b17 ldr r3, [pc, #92] ; (8012e20 ) + 8012dc2: 695b ldr r3, [r3, #20] + 8012dc4: 429a cmp r2, r3 + 8012dc6: d00f beq.n 8012de8 + /* found an exact match */ + break; + } else if (ip_addr_isany(&lpcb->local_ip)) { + 8012dc8: 697b ldr r3, [r7, #20] + 8012dca: 2b00 cmp r3, #0 + 8012dcc: d00d beq.n 8012dea + 8012dce: 697b ldr r3, [r7, #20] + 8012dd0: 681b ldr r3, [r3, #0] + 8012dd2: 2b00 cmp r3, #0 + 8012dd4: d009 beq.n 8012dea + break; +#endif /* SO_REUSE */ + } + } + } + prev = (struct tcp_pcb *)lpcb; + 8012dd6: 697b ldr r3, [r7, #20] + 8012dd8: 61bb str r3, [r7, #24] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8012dda: 697b ldr r3, [r7, #20] + 8012ddc: 68db ldr r3, [r3, #12] + 8012dde: 617b str r3, [r7, #20] + 8012de0: 697b ldr r3, [r7, #20] + 8012de2: 2b00 cmp r3, #0 + 8012de4: d1d1 bne.n 8012d8a + 8012de6: e000 b.n 8012dea + break; + 8012de8: bf00 nop + /* only pass to ANY if no specific local IP has been found */ + lpcb = lpcb_any; + prev = lpcb_prev; + } +#endif /* SO_REUSE */ + if (lpcb != NULL) { + 8012dea: 697b ldr r3, [r7, #20] + 8012dec: 2b00 cmp r3, #0 + 8012dee: d029 beq.n 8012e44 + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + 8012df0: 69bb ldr r3, [r7, #24] + 8012df2: 2b00 cmp r3, #0 + 8012df4: d00a beq.n 8012e0c + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + 8012df6: 697b ldr r3, [r7, #20] + 8012df8: 68da ldr r2, [r3, #12] + 8012dfa: 69bb ldr r3, [r7, #24] + 8012dfc: 60da str r2, [r3, #12] + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + 8012dfe: 4b10 ldr r3, [pc, #64] ; (8012e40 ) + 8012e00: 681a ldr r2, [r3, #0] + 8012e02: 697b ldr r3, [r7, #20] + 8012e04: 60da str r2, [r3, #12] + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + 8012e06: 4a0e ldr r2, [pc, #56] ; (8012e40 ) + 8012e08: 697b ldr r3, [r7, #20] + 8012e0a: 6013 str r3, [r2, #0] +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen, + tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_listen_input(lpcb); + 8012e0c: 6978 ldr r0, [r7, #20] + 8012e0e: f000 fa03 bl 8013218 + } + pbuf_free(p); + 8012e12: 6878 ldr r0, [r7, #4] + 8012e14: f7fd fdf4 bl 8010a00 + return; + 8012e18: e1a8 b.n 801316c + 8012e1a: bf00 nop + 8012e1c: 2000cf58 .word 0x2000cf58 + 8012e20: 20009670 .word 0x20009670 + 8012e24: 0801fc88 .word 0x0801fc88 + 8012e28: 0801fdb4 .word 0x0801fdb4 + 8012e2c: 0801fcd4 .word 0x0801fcd4 + 8012e30: 2000cf3c .word 0x2000cf3c + 8012e34: 0801fde0 .word 0x0801fde0 + 8012e38: 2000cf40 .word 0x2000cf40 + 8012e3c: 0801fe0c .word 0x0801fe0c + 8012e40: 2000cf38 .word 0x2000cf38 + tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) { + pbuf_free(p); + return; + } +#endif + if (pcb != NULL) { + 8012e44: 69fb ldr r3, [r7, #28] + 8012e46: 2b00 cmp r3, #0 + 8012e48: f000 8158 beq.w 80130fc +#if TCP_INPUT_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + 8012e4c: 4b95 ldr r3, [pc, #596] ; (80130a4 ) + 8012e4e: 2200 movs r2, #0 + 8012e50: 601a str r2, [r3, #0] + inseg.len = p->tot_len; + 8012e52: 687b ldr r3, [r7, #4] + 8012e54: 891a ldrh r2, [r3, #8] + 8012e56: 4b93 ldr r3, [pc, #588] ; (80130a4 ) + 8012e58: 811a strh r2, [r3, #8] + inseg.p = p; + 8012e5a: 4a92 ldr r2, [pc, #584] ; (80130a4 ) + 8012e5c: 687b ldr r3, [r7, #4] + 8012e5e: 6053 str r3, [r2, #4] + inseg.tcphdr = tcphdr; + 8012e60: 4b91 ldr r3, [pc, #580] ; (80130a8 ) + 8012e62: 681b ldr r3, [r3, #0] + 8012e64: 4a8f ldr r2, [pc, #572] ; (80130a4 ) + 8012e66: 60d3 str r3, [r2, #12] + + recv_data = NULL; + 8012e68: 4b90 ldr r3, [pc, #576] ; (80130ac ) + 8012e6a: 2200 movs r2, #0 + 8012e6c: 601a str r2, [r3, #0] + recv_flags = 0; + 8012e6e: 4b90 ldr r3, [pc, #576] ; (80130b0 ) + 8012e70: 2200 movs r2, #0 + 8012e72: 701a strb r2, [r3, #0] + recv_acked = 0; + 8012e74: 4b8f ldr r3, [pc, #572] ; (80130b4 ) + 8012e76: 2200 movs r2, #0 + 8012e78: 801a strh r2, [r3, #0] + + if (flags & TCP_PSH) { + 8012e7a: 4b8f ldr r3, [pc, #572] ; (80130b8 ) + 8012e7c: 781b ldrb r3, [r3, #0] + 8012e7e: f003 0308 and.w r3, r3, #8 + 8012e82: 2b00 cmp r3, #0 + 8012e84: d006 beq.n 8012e94 + p->flags |= PBUF_FLAG_PUSH; + 8012e86: 687b ldr r3, [r7, #4] + 8012e88: 7b5b ldrb r3, [r3, #13] + 8012e8a: f043 0301 orr.w r3, r3, #1 + 8012e8e: b2da uxtb r2, r3 + 8012e90: 687b ldr r3, [r7, #4] + 8012e92: 735a strb r2, [r3, #13] + } + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + 8012e94: 69fb ldr r3, [r7, #28] + 8012e96: 6f9b ldr r3, [r3, #120] ; 0x78 + 8012e98: 2b00 cmp r3, #0 + 8012e9a: d017 beq.n 8012ecc + if ((tcp_process_refused_data(pcb) == ERR_ABRT) || + 8012e9c: 69f8 ldr r0, [r7, #28] + 8012e9e: f7ff f929 bl 80120f4 + 8012ea2: 4603 mov r3, r0 + 8012ea4: f113 0f0d cmn.w r3, #13 + 8012ea8: d007 beq.n 8012eba + ((pcb->refused_data != NULL) && (tcplen > 0))) { + 8012eaa: 69fb ldr r3, [r7, #28] + 8012eac: 6f9b ldr r3, [r3, #120] ; 0x78 + if ((tcp_process_refused_data(pcb) == ERR_ABRT) || + 8012eae: 2b00 cmp r3, #0 + 8012eb0: d00c beq.n 8012ecc + ((pcb->refused_data != NULL) && (tcplen > 0))) { + 8012eb2: 4b82 ldr r3, [pc, #520] ; (80130bc ) + 8012eb4: 881b ldrh r3, [r3, #0] + 8012eb6: 2b00 cmp r3, #0 + 8012eb8: d008 beq.n 8012ecc + /* pcb has been aborted or refused data is still refused and the new + segment contains data */ + if (pcb->rcv_ann_wnd == 0) { + 8012eba: 69fb ldr r3, [r7, #28] + 8012ebc: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8012ebe: 2b00 cmp r3, #0 + 8012ec0: f040 80e3 bne.w 801308a + /* this is a zero-window probe, we respond to it with current RCV.NXT + and drop the data segment */ + tcp_send_empty_ack(pcb); + 8012ec4: 69f8 ldr r0, [r7, #28] + 8012ec6: f003 f9ad bl 8016224 + } + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + goto aborted; + 8012eca: e0de b.n 801308a + } + } + tcp_input_pcb = pcb; + 8012ecc: 4a7c ldr r2, [pc, #496] ; (80130c0 ) + 8012ece: 69fb ldr r3, [r7, #28] + 8012ed0: 6013 str r3, [r2, #0] + err = tcp_process(pcb); + 8012ed2: 69f8 ldr r0, [r7, #28] + 8012ed4: f000 fb18 bl 8013508 + 8012ed8: 4603 mov r3, r0 + 8012eda: 74fb strb r3, [r7, #19] + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + 8012edc: f997 3013 ldrsb.w r3, [r7, #19] + 8012ee0: f113 0f0d cmn.w r3, #13 + 8012ee4: f000 80d3 beq.w 801308e + if (recv_flags & TF_RESET) { + 8012ee8: 4b71 ldr r3, [pc, #452] ; (80130b0 ) + 8012eea: 781b ldrb r3, [r3, #0] + 8012eec: f003 0308 and.w r3, r3, #8 + 8012ef0: 2b00 cmp r3, #0 + 8012ef2: d015 beq.n 8012f20 + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST); + 8012ef4: 69fb ldr r3, [r7, #28] + 8012ef6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8012efa: 2b00 cmp r3, #0 + 8012efc: d008 beq.n 8012f10 + 8012efe: 69fb ldr r3, [r7, #28] + 8012f00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8012f04: 69fa ldr r2, [r7, #28] + 8012f06: 6912 ldr r2, [r2, #16] + 8012f08: f06f 010d mvn.w r1, #13 + 8012f0c: 4610 mov r0, r2 + 8012f0e: 4798 blx r3 + tcp_pcb_remove(&tcp_active_pcbs, pcb); + 8012f10: 69f9 ldr r1, [r7, #28] + 8012f12: 486c ldr r0, [pc, #432] ; (80130c4 ) + 8012f14: f7ff fbbc bl 8012690 + tcp_free(pcb); + 8012f18: 69f8 ldr r0, [r7, #28] + 8012f1a: f7fe f9a9 bl 8011270 + 8012f1e: e0da b.n 80130d6 + } else { + err = ERR_OK; + 8012f20: 2300 movs r3, #0 + 8012f22: 74fb strb r3, [r7, #19] + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (recv_acked > 0) { + 8012f24: 4b63 ldr r3, [pc, #396] ; (80130b4 ) + 8012f26: 881b ldrh r3, [r3, #0] + 8012f28: 2b00 cmp r3, #0 + 8012f2a: d01d beq.n 8012f68 + while (acked > 0) { + acked16 = (u16_t)LWIP_MIN(acked, 0xffffu); + acked -= acked16; +#else + { + acked16 = recv_acked; + 8012f2c: 4b61 ldr r3, [pc, #388] ; (80130b4 ) + 8012f2e: 881b ldrh r3, [r3, #0] + 8012f30: 81fb strh r3, [r7, #14] +#endif + TCP_EVENT_SENT(pcb, (u16_t)acked16, err); + 8012f32: 69fb ldr r3, [r7, #28] + 8012f34: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8012f38: 2b00 cmp r3, #0 + 8012f3a: d00a beq.n 8012f52 + 8012f3c: 69fb ldr r3, [r7, #28] + 8012f3e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8012f42: 69fa ldr r2, [r7, #28] + 8012f44: 6910 ldr r0, [r2, #16] + 8012f46: 89fa ldrh r2, [r7, #14] + 8012f48: 69f9 ldr r1, [r7, #28] + 8012f4a: 4798 blx r3 + 8012f4c: 4603 mov r3, r0 + 8012f4e: 74fb strb r3, [r7, #19] + 8012f50: e001 b.n 8012f56 + 8012f52: 2300 movs r3, #0 + 8012f54: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 8012f56: f997 3013 ldrsb.w r3, [r7, #19] + 8012f5a: f113 0f0d cmn.w r3, #13 + 8012f5e: f000 8098 beq.w 8013092 + goto aborted; + } + } + recv_acked = 0; + 8012f62: 4b54 ldr r3, [pc, #336] ; (80130b4 ) + 8012f64: 2200 movs r2, #0 + 8012f66: 801a strh r2, [r3, #0] + } + if (tcp_input_delayed_close(pcb)) { + 8012f68: 69f8 ldr r0, [r7, #28] + 8012f6a: f000 f915 bl 8013198 + 8012f6e: 4603 mov r3, r0 + 8012f70: 2b00 cmp r3, #0 + 8012f72: f040 8090 bne.w 8013096 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (recv_data != NULL) { + struct pbuf *rest = NULL; + pbuf_split_64k(recv_data, &rest); +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + if (recv_data != NULL) { + 8012f76: 4b4d ldr r3, [pc, #308] ; (80130ac ) + 8012f78: 681b ldr r3, [r3, #0] + 8012f7a: 2b00 cmp r3, #0 + 8012f7c: d041 beq.n 8013002 +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); + 8012f7e: 69fb ldr r3, [r7, #28] + 8012f80: 6f9b ldr r3, [r3, #120] ; 0x78 + 8012f82: 2b00 cmp r3, #0 + 8012f84: d006 beq.n 8012f94 + 8012f86: 4b50 ldr r3, [pc, #320] ; (80130c8 ) + 8012f88: f44f 72f3 mov.w r2, #486 ; 0x1e6 + 8012f8c: 494f ldr r1, [pc, #316] ; (80130cc ) + 8012f8e: 4850 ldr r0, [pc, #320] ; (80130d0 ) + 8012f90: f009 f840 bl 801c014 + if (pcb->flags & TF_RXCLOSED) { + 8012f94: 69fb ldr r3, [r7, #28] + 8012f96: 8b5b ldrh r3, [r3, #26] + 8012f98: f003 0310 and.w r3, r3, #16 + 8012f9c: 2b00 cmp r3, #0 + 8012f9e: d008 beq.n 8012fb2 + /* received data although already closed -> abort (send RST) to + notify the remote host that not all data has been processed */ + pbuf_free(recv_data); + 8012fa0: 4b42 ldr r3, [pc, #264] ; (80130ac ) + 8012fa2: 681b ldr r3, [r3, #0] + 8012fa4: 4618 mov r0, r3 + 8012fa6: f7fd fd2b bl 8010a00 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_free(rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + tcp_abort(pcb); + 8012faa: 69f8 ldr r0, [r7, #28] + 8012fac: f7fe fc48 bl 8011840 + goto aborted; + 8012fb0: e091 b.n 80130d6 + } + + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + 8012fb2: 69fb ldr r3, [r7, #28] + 8012fb4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8012fb8: 2b00 cmp r3, #0 + 8012fba: d00c beq.n 8012fd6 + 8012fbc: 69fb ldr r3, [r7, #28] + 8012fbe: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 8012fc2: 69fb ldr r3, [r7, #28] + 8012fc4: 6918 ldr r0, [r3, #16] + 8012fc6: 4b39 ldr r3, [pc, #228] ; (80130ac ) + 8012fc8: 681a ldr r2, [r3, #0] + 8012fca: 2300 movs r3, #0 + 8012fcc: 69f9 ldr r1, [r7, #28] + 8012fce: 47a0 blx r4 + 8012fd0: 4603 mov r3, r0 + 8012fd2: 74fb strb r3, [r7, #19] + 8012fd4: e008 b.n 8012fe8 + 8012fd6: 4b35 ldr r3, [pc, #212] ; (80130ac ) + 8012fd8: 681a ldr r2, [r3, #0] + 8012fda: 2300 movs r3, #0 + 8012fdc: 69f9 ldr r1, [r7, #28] + 8012fde: 2000 movs r0, #0 + 8012fe0: f7ff f95e bl 80122a0 + 8012fe4: 4603 mov r3, r0 + 8012fe6: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 8012fe8: f997 3013 ldrsb.w r3, [r7, #19] + 8012fec: f113 0f0d cmn.w r3, #13 + 8012ff0: d053 beq.n 801309a +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + goto aborted; + } + + /* If the upper layer can't receive this data, store it */ + if (err != ERR_OK) { + 8012ff2: f997 3013 ldrsb.w r3, [r7, #19] + 8012ff6: 2b00 cmp r3, #0 + 8012ff8: d003 beq.n 8013002 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(recv_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = recv_data; + 8012ffa: 4b2c ldr r3, [pc, #176] ; (80130ac ) + 8012ffc: 681a ldr r2, [r3, #0] + 8012ffe: 69fb ldr r3, [r7, #28] + 8013000: 679a str r2, [r3, #120] ; 0x78 + } + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + 8013002: 4b2b ldr r3, [pc, #172] ; (80130b0 ) + 8013004: 781b ldrb r3, [r3, #0] + 8013006: f003 0320 and.w r3, r3, #32 + 801300a: 2b00 cmp r3, #0 + 801300c: d030 beq.n 8013070 + if (pcb->refused_data != NULL) { + 801300e: 69fb ldr r3, [r7, #28] + 8013010: 6f9b ldr r3, [r3, #120] ; 0x78 + 8013012: 2b00 cmp r3, #0 + 8013014: d009 beq.n 801302a + /* Delay this if we have refused data. */ + pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN; + 8013016: 69fb ldr r3, [r7, #28] + 8013018: 6f9b ldr r3, [r3, #120] ; 0x78 + 801301a: 7b5a ldrb r2, [r3, #13] + 801301c: 69fb ldr r3, [r7, #28] + 801301e: 6f9b ldr r3, [r3, #120] ; 0x78 + 8013020: f042 0220 orr.w r2, r2, #32 + 8013024: b2d2 uxtb r2, r2 + 8013026: 735a strb r2, [r3, #13] + 8013028: e022 b.n 8013070 + } else { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + 801302a: 69fb ldr r3, [r7, #28] + 801302c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801302e: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 8013032: d005 beq.n 8013040 + pcb->rcv_wnd++; + 8013034: 69fb ldr r3, [r7, #28] + 8013036: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8013038: 3301 adds r3, #1 + 801303a: b29a uxth r2, r3 + 801303c: 69fb ldr r3, [r7, #28] + 801303e: 851a strh r2, [r3, #40] ; 0x28 + } + TCP_EVENT_CLOSED(pcb, err); + 8013040: 69fb ldr r3, [r7, #28] + 8013042: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8013046: 2b00 cmp r3, #0 + 8013048: d00b beq.n 8013062 + 801304a: 69fb ldr r3, [r7, #28] + 801304c: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 8013050: 69fb ldr r3, [r7, #28] + 8013052: 6918 ldr r0, [r3, #16] + 8013054: 2300 movs r3, #0 + 8013056: 2200 movs r2, #0 + 8013058: 69f9 ldr r1, [r7, #28] + 801305a: 47a0 blx r4 + 801305c: 4603 mov r3, r0 + 801305e: 74fb strb r3, [r7, #19] + 8013060: e001 b.n 8013066 + 8013062: 2300 movs r3, #0 + 8013064: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 8013066: f997 3013 ldrsb.w r3, [r7, #19] + 801306a: f113 0f0d cmn.w r3, #13 + 801306e: d016 beq.n 801309e + goto aborted; + } + } + } + + tcp_input_pcb = NULL; + 8013070: 4b13 ldr r3, [pc, #76] ; (80130c0 ) + 8013072: 2200 movs r2, #0 + 8013074: 601a str r2, [r3, #0] + if (tcp_input_delayed_close(pcb)) { + 8013076: 69f8 ldr r0, [r7, #28] + 8013078: f000 f88e bl 8013198 + 801307c: 4603 mov r3, r0 + 801307e: 2b00 cmp r3, #0 + 8013080: d128 bne.n 80130d4 + goto aborted; + } + /* Try to send something out. */ + tcp_output(pcb); + 8013082: 69f8 ldr r0, [r7, #28] + 8013084: f002 fac8 bl 8015618 + 8013088: e025 b.n 80130d6 + goto aborted; + 801308a: bf00 nop + 801308c: e023 b.n 80130d6 +#endif /* TCP_INPUT_DEBUG */ + } + } + /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). + Below this line, 'pcb' may not be dereferenced! */ +aborted: + 801308e: bf00 nop + 8013090: e021 b.n 80130d6 + goto aborted; + 8013092: bf00 nop + 8013094: e01f b.n 80130d6 + goto aborted; + 8013096: bf00 nop + 8013098: e01d b.n 80130d6 + goto aborted; + 801309a: bf00 nop + 801309c: e01b b.n 80130d6 + goto aborted; + 801309e: bf00 nop + 80130a0: e019 b.n 80130d6 + 80130a2: bf00 nop + 80130a4: 2000cf48 .word 0x2000cf48 + 80130a8: 2000cf58 .word 0x2000cf58 + 80130ac: 2000cf78 .word 0x2000cf78 + 80130b0: 2000cf75 .word 0x2000cf75 + 80130b4: 2000cf70 .word 0x2000cf70 + 80130b8: 2000cf74 .word 0x2000cf74 + 80130bc: 2000cf72 .word 0x2000cf72 + 80130c0: 2000cf7c .word 0x2000cf7c + 80130c4: 2000cf3c .word 0x2000cf3c + 80130c8: 0801fc88 .word 0x0801fc88 + 80130cc: 0801fe3c .word 0x0801fe3c + 80130d0: 0801fcd4 .word 0x0801fcd4 + goto aborted; + 80130d4: bf00 nop + tcp_input_pcb = NULL; + 80130d6: 4b27 ldr r3, [pc, #156] ; (8013174 ) + 80130d8: 2200 movs r2, #0 + 80130da: 601a str r2, [r3, #0] + recv_data = NULL; + 80130dc: 4b26 ldr r3, [pc, #152] ; (8013178 ) + 80130de: 2200 movs r2, #0 + 80130e0: 601a str r2, [r3, #0] + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) { + 80130e2: 4b26 ldr r3, [pc, #152] ; (801317c ) + 80130e4: 685b ldr r3, [r3, #4] + 80130e6: 2b00 cmp r3, #0 + 80130e8: d03f beq.n 801316a + pbuf_free(inseg.p); + 80130ea: 4b24 ldr r3, [pc, #144] ; (801317c ) + 80130ec: 685b ldr r3, [r3, #4] + 80130ee: 4618 mov r0, r3 + 80130f0: f7fd fc86 bl 8010a00 + inseg.p = NULL; + 80130f4: 4b21 ldr r3, [pc, #132] ; (801317c ) + 80130f6: 2200 movs r2, #0 + 80130f8: 605a str r2, [r3, #4] + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); + return; + 80130fa: e036 b.n 801316a + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + 80130fc: 4b20 ldr r3, [pc, #128] ; (8013180 ) + 80130fe: 681b ldr r3, [r3, #0] + 8013100: 899b ldrh r3, [r3, #12] + 8013102: b29b uxth r3, r3 + 8013104: 4618 mov r0, r3 + 8013106: f7fb f893 bl 800e230 + 801310a: 4603 mov r3, r0 + 801310c: b2db uxtb r3, r3 + 801310e: f003 0304 and.w r3, r3, #4 + 8013112: 2b00 cmp r3, #0 + 8013114: d118 bne.n 8013148 + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013116: 4b1b ldr r3, [pc, #108] ; (8013184 ) + 8013118: 6819 ldr r1, [r3, #0] + 801311a: 4b1b ldr r3, [pc, #108] ; (8013188 ) + 801311c: 881b ldrh r3, [r3, #0] + 801311e: 461a mov r2, r3 + 8013120: 4b1a ldr r3, [pc, #104] ; (801318c ) + 8013122: 681b ldr r3, [r3, #0] + 8013124: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8013126: 4b16 ldr r3, [pc, #88] ; (8013180 ) + 8013128: 681b ldr r3, [r3, #0] + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 801312a: 885b ldrh r3, [r3, #2] + 801312c: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 801312e: 4a14 ldr r2, [pc, #80] ; (8013180 ) + 8013130: 6812 ldr r2, [r2, #0] + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013132: 8812 ldrh r2, [r2, #0] + 8013134: b292 uxth r2, r2 + 8013136: 9202 str r2, [sp, #8] + 8013138: 9301 str r3, [sp, #4] + 801313a: 4b15 ldr r3, [pc, #84] ; (8013190 ) + 801313c: 9300 str r3, [sp, #0] + 801313e: 4b15 ldr r3, [pc, #84] ; (8013194 ) + 8013140: 4602 mov r2, r0 + 8013142: 2000 movs r0, #0 + 8013144: f003 f81c bl 8016180 + pbuf_free(p); + 8013148: 6878 ldr r0, [r7, #4] + 801314a: f7fd fc59 bl 8010a00 + return; + 801314e: e00c b.n 801316a + goto dropped; + 8013150: bf00 nop + 8013152: e006 b.n 8013162 + goto dropped; + 8013154: bf00 nop + 8013156: e004 b.n 8013162 + goto dropped; + 8013158: bf00 nop + 801315a: e002 b.n 8013162 + goto dropped; + 801315c: bf00 nop + 801315e: e000 b.n 8013162 + goto dropped; + 8013160: bf00 nop +dropped: + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + pbuf_free(p); + 8013162: 6878 ldr r0, [r7, #4] + 8013164: f7fd fc4c bl 8010a00 + 8013168: e000 b.n 801316c + return; + 801316a: bf00 nop +} + 801316c: 3724 adds r7, #36 ; 0x24 + 801316e: 46bd mov sp, r7 + 8013170: bd90 pop {r4, r7, pc} + 8013172: bf00 nop + 8013174: 2000cf7c .word 0x2000cf7c + 8013178: 2000cf78 .word 0x2000cf78 + 801317c: 2000cf48 .word 0x2000cf48 + 8013180: 2000cf58 .word 0x2000cf58 + 8013184: 2000cf6c .word 0x2000cf6c + 8013188: 2000cf72 .word 0x2000cf72 + 801318c: 2000cf68 .word 0x2000cf68 + 8013190: 20009680 .word 0x20009680 + 8013194: 20009684 .word 0x20009684 + +08013198 : + * any more. + * @returns 1 if the pcb has been closed and deallocated, 0 otherwise + */ +static int +tcp_input_delayed_close(struct tcp_pcb *pcb) +{ + 8013198: b580 push {r7, lr} + 801319a: b082 sub sp, #8 + 801319c: af00 add r7, sp, #0 + 801319e: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL); + 80131a0: 687b ldr r3, [r7, #4] + 80131a2: 2b00 cmp r3, #0 + 80131a4: d106 bne.n 80131b4 + 80131a6: 4b17 ldr r3, [pc, #92] ; (8013204 ) + 80131a8: f240 225a movw r2, #602 ; 0x25a + 80131ac: 4916 ldr r1, [pc, #88] ; (8013208 ) + 80131ae: 4817 ldr r0, [pc, #92] ; (801320c ) + 80131b0: f008 ff30 bl 801c014 + + if (recv_flags & TF_CLOSED) { + 80131b4: 4b16 ldr r3, [pc, #88] ; (8013210 ) + 80131b6: 781b ldrb r3, [r3, #0] + 80131b8: f003 0310 and.w r3, r3, #16 + 80131bc: 2b00 cmp r3, #0 + 80131be: d01c beq.n 80131fa + /* The connection has been closed and we will deallocate the + PCB. */ + if (!(pcb->flags & TF_RXCLOSED)) { + 80131c0: 687b ldr r3, [r7, #4] + 80131c2: 8b5b ldrh r3, [r3, #26] + 80131c4: f003 0310 and.w r3, r3, #16 + 80131c8: 2b00 cmp r3, #0 + 80131ca: d10d bne.n 80131e8 + /* Connection closed although the application has only shut down the + tx side: call the PCB's err callback and indicate the closure to + ensure the application doesn't continue using the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD); + 80131cc: 687b ldr r3, [r7, #4] + 80131ce: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80131d2: 2b00 cmp r3, #0 + 80131d4: d008 beq.n 80131e8 + 80131d6: 687b ldr r3, [r7, #4] + 80131d8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80131dc: 687a ldr r2, [r7, #4] + 80131de: 6912 ldr r2, [r2, #16] + 80131e0: f06f 010e mvn.w r1, #14 + 80131e4: 4610 mov r0, r2 + 80131e6: 4798 blx r3 + } + tcp_pcb_remove(&tcp_active_pcbs, pcb); + 80131e8: 6879 ldr r1, [r7, #4] + 80131ea: 480a ldr r0, [pc, #40] ; (8013214 ) + 80131ec: f7ff fa50 bl 8012690 + tcp_free(pcb); + 80131f0: 6878 ldr r0, [r7, #4] + 80131f2: f7fe f83d bl 8011270 + return 1; + 80131f6: 2301 movs r3, #1 + 80131f8: e000 b.n 80131fc + } + return 0; + 80131fa: 2300 movs r3, #0 +} + 80131fc: 4618 mov r0, r3 + 80131fe: 3708 adds r7, #8 + 8013200: 46bd mov sp, r7 + 8013202: bd80 pop {r7, pc} + 8013204: 0801fc88 .word 0x0801fc88 + 8013208: 0801fe58 .word 0x0801fe58 + 801320c: 0801fcd4 .word 0x0801fcd4 + 8013210: 2000cf75 .word 0x2000cf75 + 8013214: 2000cf3c .word 0x2000cf3c + +08013218 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + 8013218: b590 push {r4, r7, lr} + 801321a: b08b sub sp, #44 ; 0x2c + 801321c: af04 add r7, sp, #16 + 801321e: 6078 str r0, [r7, #4] + struct tcp_pcb *npcb; + u32_t iss; + err_t rc; + + if (flags & TCP_RST) { + 8013220: 4b6f ldr r3, [pc, #444] ; (80133e0 ) + 8013222: 781b ldrb r3, [r3, #0] + 8013224: f003 0304 and.w r3, r3, #4 + 8013228: 2b00 cmp r3, #0 + 801322a: f040 80d2 bne.w 80133d2 + /* An incoming RST should be ignored. Return. */ + return; + } + + LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL); + 801322e: 687b ldr r3, [r7, #4] + 8013230: 2b00 cmp r3, #0 + 8013232: d106 bne.n 8013242 + 8013234: 4b6b ldr r3, [pc, #428] ; (80133e4 ) + 8013236: f240 2281 movw r2, #641 ; 0x281 + 801323a: 496b ldr r1, [pc, #428] ; (80133e8 ) + 801323c: 486b ldr r0, [pc, #428] ; (80133ec ) + 801323e: f008 fee9 bl 801c014 + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + 8013242: 4b67 ldr r3, [pc, #412] ; (80133e0 ) + 8013244: 781b ldrb r3, [r3, #0] + 8013246: f003 0310 and.w r3, r3, #16 + 801324a: 2b00 cmp r3, #0 + 801324c: d019 beq.n 8013282 + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 801324e: 4b68 ldr r3, [pc, #416] ; (80133f0 ) + 8013250: 6819 ldr r1, [r3, #0] + 8013252: 4b68 ldr r3, [pc, #416] ; (80133f4 ) + 8013254: 881b ldrh r3, [r3, #0] + 8013256: 461a mov r2, r3 + 8013258: 4b67 ldr r3, [pc, #412] ; (80133f8 ) + 801325a: 681b ldr r3, [r3, #0] + 801325c: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 801325e: 4b67 ldr r3, [pc, #412] ; (80133fc ) + 8013260: 681b ldr r3, [r3, #0] + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013262: 885b ldrh r3, [r3, #2] + 8013264: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8013266: 4a65 ldr r2, [pc, #404] ; (80133fc ) + 8013268: 6812 ldr r2, [r2, #0] + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 801326a: 8812 ldrh r2, [r2, #0] + 801326c: b292 uxth r2, r2 + 801326e: 9202 str r2, [sp, #8] + 8013270: 9301 str r3, [sp, #4] + 8013272: 4b63 ldr r3, [pc, #396] ; (8013400 ) + 8013274: 9300 str r3, [sp, #0] + 8013276: 4b63 ldr r3, [pc, #396] ; (8013404 ) + 8013278: 4602 mov r2, r0 + 801327a: 6878 ldr r0, [r7, #4] + 801327c: f002 ff80 bl 8016180 + tcp_abandon(npcb, 0); + return; + } + tcp_output(npcb); + } + return; + 8013280: e0a9 b.n 80133d6 + } else if (flags & TCP_SYN) { + 8013282: 4b57 ldr r3, [pc, #348] ; (80133e0 ) + 8013284: 781b ldrb r3, [r3, #0] + 8013286: f003 0302 and.w r3, r3, #2 + 801328a: 2b00 cmp r3, #0 + 801328c: f000 80a3 beq.w 80133d6 + npcb = tcp_alloc(pcb->prio); + 8013290: 687b ldr r3, [r7, #4] + 8013292: 7d5b ldrb r3, [r3, #21] + 8013294: 4618 mov r0, r3 + 8013296: f7ff f927 bl 80124e8 + 801329a: 6178 str r0, [r7, #20] + if (npcb == NULL) { + 801329c: 697b ldr r3, [r7, #20] + 801329e: 2b00 cmp r3, #0 + 80132a0: d111 bne.n 80132c6 + TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); + 80132a2: 687b ldr r3, [r7, #4] + 80132a4: 699b ldr r3, [r3, #24] + 80132a6: 2b00 cmp r3, #0 + 80132a8: d00a beq.n 80132c0 + 80132aa: 687b ldr r3, [r7, #4] + 80132ac: 699b ldr r3, [r3, #24] + 80132ae: 687a ldr r2, [r7, #4] + 80132b0: 6910 ldr r0, [r2, #16] + 80132b2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80132b6: 2100 movs r1, #0 + 80132b8: 4798 blx r3 + 80132ba: 4603 mov r3, r0 + 80132bc: 73bb strb r3, [r7, #14] + return; + 80132be: e08b b.n 80133d8 + TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); + 80132c0: 23f0 movs r3, #240 ; 0xf0 + 80132c2: 73bb strb r3, [r7, #14] + return; + 80132c4: e088 b.n 80133d8 + ip_addr_copy(npcb->local_ip, *ip_current_dest_addr()); + 80132c6: 4b50 ldr r3, [pc, #320] ; (8013408 ) + 80132c8: 695a ldr r2, [r3, #20] + 80132ca: 697b ldr r3, [r7, #20] + 80132cc: 601a str r2, [r3, #0] + ip_addr_copy(npcb->remote_ip, *ip_current_src_addr()); + 80132ce: 4b4e ldr r3, [pc, #312] ; (8013408 ) + 80132d0: 691a ldr r2, [r3, #16] + 80132d2: 697b ldr r3, [r7, #20] + 80132d4: 605a str r2, [r3, #4] + npcb->local_port = pcb->local_port; + 80132d6: 687b ldr r3, [r7, #4] + 80132d8: 8ada ldrh r2, [r3, #22] + 80132da: 697b ldr r3, [r7, #20] + 80132dc: 82da strh r2, [r3, #22] + npcb->remote_port = tcphdr->src; + 80132de: 4b47 ldr r3, [pc, #284] ; (80133fc ) + 80132e0: 681b ldr r3, [r3, #0] + 80132e2: 881b ldrh r3, [r3, #0] + 80132e4: b29a uxth r2, r3 + 80132e6: 697b ldr r3, [r7, #20] + 80132e8: 831a strh r2, [r3, #24] + npcb->state = SYN_RCVD; + 80132ea: 697b ldr r3, [r7, #20] + 80132ec: 2203 movs r2, #3 + 80132ee: 751a strb r2, [r3, #20] + npcb->rcv_nxt = seqno + 1; + 80132f0: 4b41 ldr r3, [pc, #260] ; (80133f8 ) + 80132f2: 681b ldr r3, [r3, #0] + 80132f4: 1c5a adds r2, r3, #1 + 80132f6: 697b ldr r3, [r7, #20] + 80132f8: 625a str r2, [r3, #36] ; 0x24 + npcb->rcv_ann_right_edge = npcb->rcv_nxt; + 80132fa: 697b ldr r3, [r7, #20] + 80132fc: 6a5a ldr r2, [r3, #36] ; 0x24 + 80132fe: 697b ldr r3, [r7, #20] + 8013300: 62da str r2, [r3, #44] ; 0x2c + iss = tcp_next_iss(npcb); + 8013302: 6978 ldr r0, [r7, #20] + 8013304: f7ff fa58 bl 80127b8 + 8013308: 6138 str r0, [r7, #16] + npcb->snd_wl2 = iss; + 801330a: 697b ldr r3, [r7, #20] + 801330c: 693a ldr r2, [r7, #16] + 801330e: 659a str r2, [r3, #88] ; 0x58 + npcb->snd_nxt = iss; + 8013310: 697b ldr r3, [r7, #20] + 8013312: 693a ldr r2, [r7, #16] + 8013314: 651a str r2, [r3, #80] ; 0x50 + npcb->lastack = iss; + 8013316: 697b ldr r3, [r7, #20] + 8013318: 693a ldr r2, [r7, #16] + 801331a: 645a str r2, [r3, #68] ; 0x44 + npcb->snd_lbb = iss; + 801331c: 697b ldr r3, [r7, #20] + 801331e: 693a ldr r2, [r7, #16] + 8013320: 65da str r2, [r3, #92] ; 0x5c + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + 8013322: 4b35 ldr r3, [pc, #212] ; (80133f8 ) + 8013324: 681b ldr r3, [r3, #0] + 8013326: 1e5a subs r2, r3, #1 + 8013328: 697b ldr r3, [r7, #20] + 801332a: 655a str r2, [r3, #84] ; 0x54 + npcb->callback_arg = pcb->callback_arg; + 801332c: 687b ldr r3, [r7, #4] + 801332e: 691a ldr r2, [r3, #16] + 8013330: 697b ldr r3, [r7, #20] + 8013332: 611a str r2, [r3, #16] + npcb->listener = pcb; + 8013334: 697b ldr r3, [r7, #20] + 8013336: 687a ldr r2, [r7, #4] + 8013338: 67da str r2, [r3, #124] ; 0x7c + npcb->so_options = pcb->so_options & SOF_INHERITED; + 801333a: 687b ldr r3, [r7, #4] + 801333c: 7a5b ldrb r3, [r3, #9] + 801333e: f003 030c and.w r3, r3, #12 + 8013342: b2da uxtb r2, r3 + 8013344: 697b ldr r3, [r7, #20] + 8013346: 725a strb r2, [r3, #9] + npcb->netif_idx = pcb->netif_idx; + 8013348: 687b ldr r3, [r7, #4] + 801334a: 7a1a ldrb r2, [r3, #8] + 801334c: 697b ldr r3, [r7, #20] + 801334e: 721a strb r2, [r3, #8] + TCP_REG_ACTIVE(npcb); + 8013350: 4b2e ldr r3, [pc, #184] ; (801340c ) + 8013352: 681a ldr r2, [r3, #0] + 8013354: 697b ldr r3, [r7, #20] + 8013356: 60da str r2, [r3, #12] + 8013358: 4a2c ldr r2, [pc, #176] ; (801340c ) + 801335a: 697b ldr r3, [r7, #20] + 801335c: 6013 str r3, [r2, #0] + 801335e: f003 f8d1 bl 8016504 + 8013362: 4b2b ldr r3, [pc, #172] ; (8013410 ) + 8013364: 2201 movs r2, #1 + 8013366: 701a strb r2, [r3, #0] + tcp_parseopt(npcb); + 8013368: 6978 ldr r0, [r7, #20] + 801336a: f001 fd8f bl 8014e8c + npcb->snd_wnd = tcphdr->wnd; + 801336e: 4b23 ldr r3, [pc, #140] ; (80133fc ) + 8013370: 681b ldr r3, [r3, #0] + 8013372: 89db ldrh r3, [r3, #14] + 8013374: b29a uxth r2, r3 + 8013376: 697b ldr r3, [r7, #20] + 8013378: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + npcb->snd_wnd_max = npcb->snd_wnd; + 801337c: 697b ldr r3, [r7, #20] + 801337e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 8013382: 697b ldr r3, [r7, #20] + 8013384: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip); + 8013388: 697b ldr r3, [r7, #20] + 801338a: 8e5c ldrh r4, [r3, #50] ; 0x32 + 801338c: 697b ldr r3, [r7, #20] + 801338e: 3304 adds r3, #4 + 8013390: 4618 mov r0, r3 + 8013392: f006 ff73 bl 801a27c + 8013396: 4601 mov r1, r0 + 8013398: 697b ldr r3, [r7, #20] + 801339a: 3304 adds r3, #4 + 801339c: 461a mov r2, r3 + 801339e: 4620 mov r0, r4 + 80133a0: f7ff fa30 bl 8012804 + 80133a4: 4603 mov r3, r0 + 80133a6: 461a mov r2, r3 + 80133a8: 697b ldr r3, [r7, #20] + 80133aa: 865a strh r2, [r3, #50] ; 0x32 + rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); + 80133ac: 2112 movs r1, #18 + 80133ae: 6978 ldr r0, [r7, #20] + 80133b0: f002 f844 bl 801543c + 80133b4: 4603 mov r3, r0 + 80133b6: 73fb strb r3, [r7, #15] + if (rc != ERR_OK) { + 80133b8: f997 300f ldrsb.w r3, [r7, #15] + 80133bc: 2b00 cmp r3, #0 + 80133be: d004 beq.n 80133ca + tcp_abandon(npcb, 0); + 80133c0: 2100 movs r1, #0 + 80133c2: 6978 ldr r0, [r7, #20] + 80133c4: f7fe f97e bl 80116c4 + return; + 80133c8: e006 b.n 80133d8 + tcp_output(npcb); + 80133ca: 6978 ldr r0, [r7, #20] + 80133cc: f002 f924 bl 8015618 + return; + 80133d0: e001 b.n 80133d6 + return; + 80133d2: bf00 nop + 80133d4: e000 b.n 80133d8 + return; + 80133d6: bf00 nop +} + 80133d8: 371c adds r7, #28 + 80133da: 46bd mov sp, r7 + 80133dc: bd90 pop {r4, r7, pc} + 80133de: bf00 nop + 80133e0: 2000cf74 .word 0x2000cf74 + 80133e4: 0801fc88 .word 0x0801fc88 + 80133e8: 0801fe80 .word 0x0801fe80 + 80133ec: 0801fcd4 .word 0x0801fcd4 + 80133f0: 2000cf6c .word 0x2000cf6c + 80133f4: 2000cf72 .word 0x2000cf72 + 80133f8: 2000cf68 .word 0x2000cf68 + 80133fc: 2000cf58 .word 0x2000cf58 + 8013400: 20009680 .word 0x20009680 + 8013404: 20009684 .word 0x20009684 + 8013408: 20009670 .word 0x20009670 + 801340c: 2000cf3c .word 0x2000cf3c + 8013410: 2000cf44 .word 0x2000cf44 + +08013414 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_timewait_input(struct tcp_pcb *pcb) +{ + 8013414: b580 push {r7, lr} + 8013416: b086 sub sp, #24 + 8013418: af04 add r7, sp, #16 + 801341a: 6078 str r0, [r7, #4] + /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ + /* RFC 793 3.9 Event Processing - Segment Arrives: + * - first check sequence number - we skip that one in TIME_WAIT (always + * acceptable since we only send ACKs) + * - second check the RST bit (... return) */ + if (flags & TCP_RST) { + 801341c: 4b2f ldr r3, [pc, #188] ; (80134dc ) + 801341e: 781b ldrb r3, [r3, #0] + 8013420: f003 0304 and.w r3, r3, #4 + 8013424: 2b00 cmp r3, #0 + 8013426: d153 bne.n 80134d0 + return; + } + + LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL); + 8013428: 687b ldr r3, [r7, #4] + 801342a: 2b00 cmp r3, #0 + 801342c: d106 bne.n 801343c + 801342e: 4b2c ldr r3, [pc, #176] ; (80134e0 ) + 8013430: f240 22ee movw r2, #750 ; 0x2ee + 8013434: 492b ldr r1, [pc, #172] ; (80134e4 ) + 8013436: 482c ldr r0, [pc, #176] ; (80134e8 ) + 8013438: f008 fdec bl 801c014 + + /* - fourth, check the SYN bit, */ + if (flags & TCP_SYN) { + 801343c: 4b27 ldr r3, [pc, #156] ; (80134dc ) + 801343e: 781b ldrb r3, [r3, #0] + 8013440: f003 0302 and.w r3, r3, #2 + 8013444: 2b00 cmp r3, #0 + 8013446: d02a beq.n 801349e + /* If an incoming segment is not acceptable, an acknowledgment + should be sent in reply */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) { + 8013448: 4b28 ldr r3, [pc, #160] ; (80134ec ) + 801344a: 681a ldr r2, [r3, #0] + 801344c: 687b ldr r3, [r7, #4] + 801344e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8013450: 1ad3 subs r3, r2, r3 + 8013452: 2b00 cmp r3, #0 + 8013454: db2d blt.n 80134b2 + 8013456: 4b25 ldr r3, [pc, #148] ; (80134ec ) + 8013458: 681a ldr r2, [r3, #0] + 801345a: 687b ldr r3, [r7, #4] + 801345c: 6a5b ldr r3, [r3, #36] ; 0x24 + 801345e: 6879 ldr r1, [r7, #4] + 8013460: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8013462: 440b add r3, r1 + 8013464: 1ad3 subs r3, r2, r3 + 8013466: 2b00 cmp r3, #0 + 8013468: dc23 bgt.n 80134b2 + /* If the SYN is in the window it is an error, send a reset */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 801346a: 4b21 ldr r3, [pc, #132] ; (80134f0 ) + 801346c: 6819 ldr r1, [r3, #0] + 801346e: 4b21 ldr r3, [pc, #132] ; (80134f4 ) + 8013470: 881b ldrh r3, [r3, #0] + 8013472: 461a mov r2, r3 + 8013474: 4b1d ldr r3, [pc, #116] ; (80134ec ) + 8013476: 681b ldr r3, [r3, #0] + 8013478: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 801347a: 4b1f ldr r3, [pc, #124] ; (80134f8 ) + 801347c: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 801347e: 885b ldrh r3, [r3, #2] + 8013480: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8013482: 4a1d ldr r2, [pc, #116] ; (80134f8 ) + 8013484: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013486: 8812 ldrh r2, [r2, #0] + 8013488: b292 uxth r2, r2 + 801348a: 9202 str r2, [sp, #8] + 801348c: 9301 str r3, [sp, #4] + 801348e: 4b1b ldr r3, [pc, #108] ; (80134fc ) + 8013490: 9300 str r3, [sp, #0] + 8013492: 4b1b ldr r3, [pc, #108] ; (8013500 ) + 8013494: 4602 mov r2, r0 + 8013496: 6878 ldr r0, [r7, #4] + 8013498: f002 fe72 bl 8016180 + return; + 801349c: e01b b.n 80134d6 + } + } else if (flags & TCP_FIN) { + 801349e: 4b0f ldr r3, [pc, #60] ; (80134dc ) + 80134a0: 781b ldrb r3, [r3, #0] + 80134a2: f003 0301 and.w r3, r3, #1 + 80134a6: 2b00 cmp r3, #0 + 80134a8: d003 beq.n 80134b2 + /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. + Restart the 2 MSL time-wait timeout.*/ + pcb->tmr = tcp_ticks; + 80134aa: 4b16 ldr r3, [pc, #88] ; (8013504 ) + 80134ac: 681a ldr r2, [r3, #0] + 80134ae: 687b ldr r3, [r7, #4] + 80134b0: 621a str r2, [r3, #32] + } + + if ((tcplen > 0)) { + 80134b2: 4b10 ldr r3, [pc, #64] ; (80134f4 ) + 80134b4: 881b ldrh r3, [r3, #0] + 80134b6: 2b00 cmp r3, #0 + 80134b8: d00c beq.n 80134d4 + /* Acknowledge data, FIN or out-of-window SYN */ + tcp_ack_now(pcb); + 80134ba: 687b ldr r3, [r7, #4] + 80134bc: 8b5b ldrh r3, [r3, #26] + 80134be: f043 0302 orr.w r3, r3, #2 + 80134c2: b29a uxth r2, r3 + 80134c4: 687b ldr r3, [r7, #4] + 80134c6: 835a strh r2, [r3, #26] + tcp_output(pcb); + 80134c8: 6878 ldr r0, [r7, #4] + 80134ca: f002 f8a5 bl 8015618 + } + return; + 80134ce: e001 b.n 80134d4 + return; + 80134d0: bf00 nop + 80134d2: e000 b.n 80134d6 + return; + 80134d4: bf00 nop +} + 80134d6: 3708 adds r7, #8 + 80134d8: 46bd mov sp, r7 + 80134da: bd80 pop {r7, pc} + 80134dc: 2000cf74 .word 0x2000cf74 + 80134e0: 0801fc88 .word 0x0801fc88 + 80134e4: 0801fea0 .word 0x0801fea0 + 80134e8: 0801fcd4 .word 0x0801fcd4 + 80134ec: 2000cf68 .word 0x2000cf68 + 80134f0: 2000cf6c .word 0x2000cf6c + 80134f4: 2000cf72 .word 0x2000cf72 + 80134f8: 2000cf58 .word 0x2000cf58 + 80134fc: 20009680 .word 0x20009680 + 8013500: 20009684 .word 0x20009684 + 8013504: 2000cf30 .word 0x2000cf30 + +08013508 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + 8013508: b590 push {r4, r7, lr} + 801350a: b08d sub sp, #52 ; 0x34 + 801350c: af04 add r7, sp, #16 + 801350e: 6078 str r0, [r7, #4] + struct tcp_seg *rseg; + u8_t acceptable = 0; + 8013510: 2300 movs r3, #0 + 8013512: 76fb strb r3, [r7, #27] + err_t err; + + err = ERR_OK; + 8013514: 2300 movs r3, #0 + 8013516: 76bb strb r3, [r7, #26] + + LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL); + 8013518: 687b ldr r3, [r7, #4] + 801351a: 2b00 cmp r3, #0 + 801351c: d106 bne.n 801352c + 801351e: 4b9d ldr r3, [pc, #628] ; (8013794 ) + 8013520: f44f 7247 mov.w r2, #796 ; 0x31c + 8013524: 499c ldr r1, [pc, #624] ; (8013798 ) + 8013526: 489d ldr r0, [pc, #628] ; (801379c ) + 8013528: f008 fd74 bl 801c014 + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + 801352c: 4b9c ldr r3, [pc, #624] ; (80137a0 ) + 801352e: 781b ldrb r3, [r3, #0] + 8013530: f003 0304 and.w r3, r3, #4 + 8013534: 2b00 cmp r3, #0 + 8013536: d04e beq.n 80135d6 + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + 8013538: 687b ldr r3, [r7, #4] + 801353a: 7d1b ldrb r3, [r3, #20] + 801353c: 2b02 cmp r3, #2 + 801353e: d108 bne.n 8013552 + /* "In the SYN-SENT state (a RST received in response to an initial SYN), + the RST is acceptable if the ACK field acknowledges the SYN." */ + if (ackno == pcb->snd_nxt) { + 8013540: 687b ldr r3, [r7, #4] + 8013542: 6d1a ldr r2, [r3, #80] ; 0x50 + 8013544: 4b97 ldr r3, [pc, #604] ; (80137a4 ) + 8013546: 681b ldr r3, [r3, #0] + 8013548: 429a cmp r2, r3 + 801354a: d123 bne.n 8013594 + acceptable = 1; + 801354c: 2301 movs r3, #1 + 801354e: 76fb strb r3, [r7, #27] + 8013550: e020 b.n 8013594 + } + } else { + /* "In all states except SYN-SENT, all reset (RST) segments are validated + by checking their SEQ-fields." */ + if (seqno == pcb->rcv_nxt) { + 8013552: 687b ldr r3, [r7, #4] + 8013554: 6a5a ldr r2, [r3, #36] ; 0x24 + 8013556: 4b94 ldr r3, [pc, #592] ; (80137a8 ) + 8013558: 681b ldr r3, [r3, #0] + 801355a: 429a cmp r2, r3 + 801355c: d102 bne.n 8013564 + acceptable = 1; + 801355e: 2301 movs r3, #1 + 8013560: 76fb strb r3, [r7, #27] + 8013562: e017 b.n 8013594 + } else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 8013564: 4b90 ldr r3, [pc, #576] ; (80137a8 ) + 8013566: 681a ldr r2, [r3, #0] + 8013568: 687b ldr r3, [r7, #4] + 801356a: 6a5b ldr r3, [r3, #36] ; 0x24 + 801356c: 1ad3 subs r3, r2, r3 + 801356e: 2b00 cmp r3, #0 + 8013570: db10 blt.n 8013594 + 8013572: 4b8d ldr r3, [pc, #564] ; (80137a8 ) + 8013574: 681a ldr r2, [r3, #0] + 8013576: 687b ldr r3, [r7, #4] + 8013578: 6a5b ldr r3, [r3, #36] ; 0x24 + 801357a: 6879 ldr r1, [r7, #4] + 801357c: 8d09 ldrh r1, [r1, #40] ; 0x28 + 801357e: 440b add r3, r1 + 8013580: 1ad3 subs r3, r2, r3 + 8013582: 2b00 cmp r3, #0 + 8013584: dc06 bgt.n 8013594 + pcb->rcv_nxt + pcb->rcv_wnd)) { + /* If the sequence number is inside the window, we send a challenge ACK + and wait for a re-send with matching sequence number. + This follows RFC 5961 section 3.2 and addresses CVE-2004-0230 + (RST spoofing attack), which is present in RFC 793 RST handling. */ + tcp_ack_now(pcb); + 8013586: 687b ldr r3, [r7, #4] + 8013588: 8b5b ldrh r3, [r3, #26] + 801358a: f043 0302 orr.w r3, r3, #2 + 801358e: b29a uxth r2, r3 + 8013590: 687b ldr r3, [r7, #4] + 8013592: 835a strh r2, [r3, #26] + } + } + + if (acceptable) { + 8013594: 7efb ldrb r3, [r7, #27] + 8013596: 2b00 cmp r3, #0 + 8013598: d01b beq.n 80135d2 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + 801359a: 687b ldr r3, [r7, #4] + 801359c: 7d1b ldrb r3, [r3, #20] + 801359e: 2b00 cmp r3, #0 + 80135a0: d106 bne.n 80135b0 + 80135a2: 4b7c ldr r3, [pc, #496] ; (8013794 ) + 80135a4: f44f 724e mov.w r2, #824 ; 0x338 + 80135a8: 4980 ldr r1, [pc, #512] ; (80137ac ) + 80135aa: 487c ldr r0, [pc, #496] ; (801379c ) + 80135ac: f008 fd32 bl 801c014 + recv_flags |= TF_RESET; + 80135b0: 4b7f ldr r3, [pc, #508] ; (80137b0 ) + 80135b2: 781b ldrb r3, [r3, #0] + 80135b4: f043 0308 orr.w r3, r3, #8 + 80135b8: b2da uxtb r2, r3 + 80135ba: 4b7d ldr r3, [pc, #500] ; (80137b0 ) + 80135bc: 701a strb r2, [r3, #0] + tcp_clear_flags(pcb, TF_ACK_DELAY); + 80135be: 687b ldr r3, [r7, #4] + 80135c0: 8b5b ldrh r3, [r3, #26] + 80135c2: f023 0301 bic.w r3, r3, #1 + 80135c6: b29a uxth r2, r3 + 80135c8: 687b ldr r3, [r7, #4] + 80135ca: 835a strh r2, [r3, #26] + return ERR_RST; + 80135cc: f06f 030d mvn.w r3, #13 + 80135d0: e37a b.n 8013cc8 + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + 80135d2: 2300 movs r3, #0 + 80135d4: e378 b.n 8013cc8 + } + } + + if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { + 80135d6: 4b72 ldr r3, [pc, #456] ; (80137a0 ) + 80135d8: 781b ldrb r3, [r3, #0] + 80135da: f003 0302 and.w r3, r3, #2 + 80135de: 2b00 cmp r3, #0 + 80135e0: d010 beq.n 8013604 + 80135e2: 687b ldr r3, [r7, #4] + 80135e4: 7d1b ldrb r3, [r3, #20] + 80135e6: 2b02 cmp r3, #2 + 80135e8: d00c beq.n 8013604 + 80135ea: 687b ldr r3, [r7, #4] + 80135ec: 7d1b ldrb r3, [r3, #20] + 80135ee: 2b03 cmp r3, #3 + 80135f0: d008 beq.n 8013604 + /* Cope with new connection attempt after remote end crashed */ + tcp_ack_now(pcb); + 80135f2: 687b ldr r3, [r7, #4] + 80135f4: 8b5b ldrh r3, [r3, #26] + 80135f6: f043 0302 orr.w r3, r3, #2 + 80135fa: b29a uxth r2, r3 + 80135fc: 687b ldr r3, [r7, #4] + 80135fe: 835a strh r2, [r3, #26] + return ERR_OK; + 8013600: 2300 movs r3, #0 + 8013602: e361 b.n 8013cc8 + } + + if ((pcb->flags & TF_RXCLOSED) == 0) { + 8013604: 687b ldr r3, [r7, #4] + 8013606: 8b5b ldrh r3, [r3, #26] + 8013608: f003 0310 and.w r3, r3, #16 + 801360c: 2b00 cmp r3, #0 + 801360e: d103 bne.n 8013618 + /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ + pcb->tmr = tcp_ticks; + 8013610: 4b68 ldr r3, [pc, #416] ; (80137b4 ) + 8013612: 681a ldr r2, [r3, #0] + 8013614: 687b ldr r3, [r7, #4] + 8013616: 621a str r2, [r3, #32] + } + pcb->keep_cnt_sent = 0; + 8013618: 687b ldr r3, [r7, #4] + 801361a: 2200 movs r2, #0 + 801361c: f883 209b strb.w r2, [r3, #155] ; 0x9b + pcb->persist_probe = 0; + 8013620: 687b ldr r3, [r7, #4] + 8013622: 2200 movs r2, #0 + 8013624: f883 209a strb.w r2, [r3, #154] ; 0x9a + + tcp_parseopt(pcb); + 8013628: 6878 ldr r0, [r7, #4] + 801362a: f001 fc2f bl 8014e8c + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + 801362e: 687b ldr r3, [r7, #4] + 8013630: 7d1b ldrb r3, [r3, #20] + 8013632: 3b02 subs r3, #2 + 8013634: 2b07 cmp r3, #7 + 8013636: f200 8337 bhi.w 8013ca8 + 801363a: a201 add r2, pc, #4 ; (adr r2, 8013640 ) + 801363c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8013640: 08013661 .word 0x08013661 + 8013644: 08013891 .word 0x08013891 + 8013648: 08013a09 .word 0x08013a09 + 801364c: 08013a33 .word 0x08013a33 + 8013650: 08013b57 .word 0x08013b57 + 8013654: 08013a09 .word 0x08013a09 + 8013658: 08013be3 .word 0x08013be3 + 801365c: 08013c73 .word 0x08013c73 + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + 8013660: 4b4f ldr r3, [pc, #316] ; (80137a0 ) + 8013662: 781b ldrb r3, [r3, #0] + 8013664: f003 0310 and.w r3, r3, #16 + 8013668: 2b00 cmp r3, #0 + 801366a: f000 80e4 beq.w 8013836 + 801366e: 4b4c ldr r3, [pc, #304] ; (80137a0 ) + 8013670: 781b ldrb r3, [r3, #0] + 8013672: f003 0302 and.w r3, r3, #2 + 8013676: 2b00 cmp r3, #0 + 8013678: f000 80dd beq.w 8013836 + && (ackno == pcb->lastack + 1)) { + 801367c: 687b ldr r3, [r7, #4] + 801367e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8013680: 1c5a adds r2, r3, #1 + 8013682: 4b48 ldr r3, [pc, #288] ; (80137a4 ) + 8013684: 681b ldr r3, [r3, #0] + 8013686: 429a cmp r2, r3 + 8013688: f040 80d5 bne.w 8013836 + pcb->rcv_nxt = seqno + 1; + 801368c: 4b46 ldr r3, [pc, #280] ; (80137a8 ) + 801368e: 681b ldr r3, [r3, #0] + 8013690: 1c5a adds r2, r3, #1 + 8013692: 687b ldr r3, [r7, #4] + 8013694: 625a str r2, [r3, #36] ; 0x24 + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + 8013696: 687b ldr r3, [r7, #4] + 8013698: 6a5a ldr r2, [r3, #36] ; 0x24 + 801369a: 687b ldr r3, [r7, #4] + 801369c: 62da str r2, [r3, #44] ; 0x2c + pcb->lastack = ackno; + 801369e: 4b41 ldr r3, [pc, #260] ; (80137a4 ) + 80136a0: 681a ldr r2, [r3, #0] + 80136a2: 687b ldr r3, [r7, #4] + 80136a4: 645a str r2, [r3, #68] ; 0x44 + pcb->snd_wnd = tcphdr->wnd; + 80136a6: 4b44 ldr r3, [pc, #272] ; (80137b8 ) + 80136a8: 681b ldr r3, [r3, #0] + 80136aa: 89db ldrh r3, [r3, #14] + 80136ac: b29a uxth r2, r3 + 80136ae: 687b ldr r3, [r7, #4] + 80136b0: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + pcb->snd_wnd_max = pcb->snd_wnd; + 80136b4: 687b ldr r3, [r7, #4] + 80136b6: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 80136ba: 687b ldr r3, [r7, #4] + 80136bc: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + 80136c0: 4b39 ldr r3, [pc, #228] ; (80137a8 ) + 80136c2: 681b ldr r3, [r3, #0] + 80136c4: 1e5a subs r2, r3, #1 + 80136c6: 687b ldr r3, [r7, #4] + 80136c8: 655a str r2, [r3, #84] ; 0x54 + pcb->state = ESTABLISHED; + 80136ca: 687b ldr r3, [r7, #4] + 80136cc: 2204 movs r2, #4 + 80136ce: 751a strb r2, [r3, #20] + +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); + 80136d0: 687b ldr r3, [r7, #4] + 80136d2: 8e5c ldrh r4, [r3, #50] ; 0x32 + 80136d4: 687b ldr r3, [r7, #4] + 80136d6: 3304 adds r3, #4 + 80136d8: 4618 mov r0, r3 + 80136da: f006 fdcf bl 801a27c + 80136de: 4601 mov r1, r0 + 80136e0: 687b ldr r3, [r7, #4] + 80136e2: 3304 adds r3, #4 + 80136e4: 461a mov r2, r3 + 80136e6: 4620 mov r0, r4 + 80136e8: f7ff f88c bl 8012804 + 80136ec: 4603 mov r3, r0 + 80136ee: 461a mov r2, r3 + 80136f0: 687b ldr r3, [r7, #4] + 80136f2: 865a strh r2, [r3, #50] ; 0x32 +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + 80136f4: 687b ldr r3, [r7, #4] + 80136f6: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80136f8: 009a lsls r2, r3, #2 + 80136fa: 687b ldr r3, [r7, #4] + 80136fc: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80136fe: 005b lsls r3, r3, #1 + 8013700: f241 111c movw r1, #4380 ; 0x111c + 8013704: 428b cmp r3, r1 + 8013706: bf38 it cc + 8013708: 460b movcc r3, r1 + 801370a: 429a cmp r2, r3 + 801370c: d204 bcs.n 8013718 + 801370e: 687b ldr r3, [r7, #4] + 8013710: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8013712: 009b lsls r3, r3, #2 + 8013714: b29b uxth r3, r3 + 8013716: e00d b.n 8013734 + 8013718: 687b ldr r3, [r7, #4] + 801371a: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801371c: 005b lsls r3, r3, #1 + 801371e: f241 121c movw r2, #4380 ; 0x111c + 8013722: 4293 cmp r3, r2 + 8013724: d904 bls.n 8013730 + 8013726: 687b ldr r3, [r7, #4] + 8013728: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801372a: 005b lsls r3, r3, #1 + 801372c: b29b uxth r3, r3 + 801372e: e001 b.n 8013734 + 8013730: f241 131c movw r3, #4380 ; 0x111c + 8013734: 687a ldr r2, [r7, #4] + 8013736: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); + 801373a: 687b ldr r3, [r7, #4] + 801373c: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8013740: 2b00 cmp r3, #0 + 8013742: d106 bne.n 8013752 + 8013744: 4b13 ldr r3, [pc, #76] ; (8013794 ) + 8013746: f44f 725b mov.w r2, #876 ; 0x36c + 801374a: 491c ldr r1, [pc, #112] ; (80137bc ) + 801374c: 4813 ldr r0, [pc, #76] ; (801379c ) + 801374e: f008 fc61 bl 801c014 + --pcb->snd_queuelen; + 8013752: 687b ldr r3, [r7, #4] + 8013754: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8013758: 3b01 subs r3, #1 + 801375a: b29a uxth r2, r3 + 801375c: 687b ldr r3, [r7, #4] + 801375e: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + 8013762: 687b ldr r3, [r7, #4] + 8013764: 6f1b ldr r3, [r3, #112] ; 0x70 + 8013766: 61fb str r3, [r7, #28] + if (rseg == NULL) { + 8013768: 69fb ldr r3, [r7, #28] + 801376a: 2b00 cmp r3, #0 + 801376c: d12a bne.n 80137c4 + /* might happen if tcp_output fails in tcp_rexmit_rto() + in which case the segment is on the unsent list */ + rseg = pcb->unsent; + 801376e: 687b ldr r3, [r7, #4] + 8013770: 6edb ldr r3, [r3, #108] ; 0x6c + 8013772: 61fb str r3, [r7, #28] + LWIP_ASSERT("no segment to free", rseg != NULL); + 8013774: 69fb ldr r3, [r7, #28] + 8013776: 2b00 cmp r3, #0 + 8013778: d106 bne.n 8013788 + 801377a: 4b06 ldr r3, [pc, #24] ; (8013794 ) + 801377c: f44f 725d mov.w r2, #884 ; 0x374 + 8013780: 490f ldr r1, [pc, #60] ; (80137c0 ) + 8013782: 4806 ldr r0, [pc, #24] ; (801379c ) + 8013784: f008 fc46 bl 801c014 + pcb->unsent = rseg->next; + 8013788: 69fb ldr r3, [r7, #28] + 801378a: 681a ldr r2, [r3, #0] + 801378c: 687b ldr r3, [r7, #4] + 801378e: 66da str r2, [r3, #108] ; 0x6c + 8013790: e01c b.n 80137cc + 8013792: bf00 nop + 8013794: 0801fc88 .word 0x0801fc88 + 8013798: 0801fec0 .word 0x0801fec0 + 801379c: 0801fcd4 .word 0x0801fcd4 + 80137a0: 2000cf74 .word 0x2000cf74 + 80137a4: 2000cf6c .word 0x2000cf6c + 80137a8: 2000cf68 .word 0x2000cf68 + 80137ac: 0801fedc .word 0x0801fedc + 80137b0: 2000cf75 .word 0x2000cf75 + 80137b4: 2000cf30 .word 0x2000cf30 + 80137b8: 2000cf58 .word 0x2000cf58 + 80137bc: 0801fefc .word 0x0801fefc + 80137c0: 0801ff14 .word 0x0801ff14 + } else { + pcb->unacked = rseg->next; + 80137c4: 69fb ldr r3, [r7, #28] + 80137c6: 681a ldr r2, [r3, #0] + 80137c8: 687b ldr r3, [r7, #4] + 80137ca: 671a str r2, [r3, #112] ; 0x70 + } + tcp_seg_free(rseg); + 80137cc: 69f8 ldr r0, [r7, #28] + 80137ce: f7fe fd22 bl 8012216 + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + 80137d2: 687b ldr r3, [r7, #4] + 80137d4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80137d6: 2b00 cmp r3, #0 + 80137d8: d104 bne.n 80137e4 + pcb->rtime = -1; + 80137da: 687b ldr r3, [r7, #4] + 80137dc: f64f 72ff movw r2, #65535 ; 0xffff + 80137e0: 861a strh r2, [r3, #48] ; 0x30 + 80137e2: e006 b.n 80137f2 + } else { + pcb->rtime = 0; + 80137e4: 687b ldr r3, [r7, #4] + 80137e6: 2200 movs r2, #0 + 80137e8: 861a strh r2, [r3, #48] ; 0x30 + pcb->nrtx = 0; + 80137ea: 687b ldr r3, [r7, #4] + 80137ec: 2200 movs r2, #0 + 80137ee: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + + /* Call the user specified function to call when successfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + 80137f2: 687b ldr r3, [r7, #4] + 80137f4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80137f8: 2b00 cmp r3, #0 + 80137fa: d00a beq.n 8013812 + 80137fc: 687b ldr r3, [r7, #4] + 80137fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8013802: 687a ldr r2, [r7, #4] + 8013804: 6910 ldr r0, [r2, #16] + 8013806: 2200 movs r2, #0 + 8013808: 6879 ldr r1, [r7, #4] + 801380a: 4798 blx r3 + 801380c: 4603 mov r3, r0 + 801380e: 76bb strb r3, [r7, #26] + 8013810: e001 b.n 8013816 + 8013812: 2300 movs r3, #0 + 8013814: 76bb strb r3, [r7, #26] + if (err == ERR_ABRT) { + 8013816: f997 301a ldrsb.w r3, [r7, #26] + 801381a: f113 0f0d cmn.w r3, #13 + 801381e: d102 bne.n 8013826 + return ERR_ABRT; + 8013820: f06f 030c mvn.w r3, #12 + 8013824: e250 b.n 8013cc8 + } + tcp_ack_now(pcb); + 8013826: 687b ldr r3, [r7, #4] + 8013828: 8b5b ldrh r3, [r3, #26] + 801382a: f043 0302 orr.w r3, r3, #2 + 801382e: b29a uxth r2, r3 + 8013830: 687b ldr r3, [r7, #4] + 8013832: 835a strh r2, [r3, #26] + if (pcb->nrtx < TCP_SYNMAXRTX) { + pcb->rtime = 0; + tcp_rexmit_rto(pcb); + } + } + break; + 8013834: e23a b.n 8013cac + else if (flags & TCP_ACK) { + 8013836: 4b98 ldr r3, [pc, #608] ; (8013a98 ) + 8013838: 781b ldrb r3, [r3, #0] + 801383a: f003 0310 and.w r3, r3, #16 + 801383e: 2b00 cmp r3, #0 + 8013840: f000 8234 beq.w 8013cac + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013844: 4b95 ldr r3, [pc, #596] ; (8013a9c ) + 8013846: 6819 ldr r1, [r3, #0] + 8013848: 4b95 ldr r3, [pc, #596] ; (8013aa0 ) + 801384a: 881b ldrh r3, [r3, #0] + 801384c: 461a mov r2, r3 + 801384e: 4b95 ldr r3, [pc, #596] ; (8013aa4 ) + 8013850: 681b ldr r3, [r3, #0] + 8013852: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8013854: 4b94 ldr r3, [pc, #592] ; (8013aa8 ) + 8013856: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013858: 885b ldrh r3, [r3, #2] + 801385a: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 801385c: 4a92 ldr r2, [pc, #584] ; (8013aa8 ) + 801385e: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8013860: 8812 ldrh r2, [r2, #0] + 8013862: b292 uxth r2, r2 + 8013864: 9202 str r2, [sp, #8] + 8013866: 9301 str r3, [sp, #4] + 8013868: 4b90 ldr r3, [pc, #576] ; (8013aac ) + 801386a: 9300 str r3, [sp, #0] + 801386c: 4b90 ldr r3, [pc, #576] ; (8013ab0 ) + 801386e: 4602 mov r2, r0 + 8013870: 6878 ldr r0, [r7, #4] + 8013872: f002 fc85 bl 8016180 + if (pcb->nrtx < TCP_SYNMAXRTX) { + 8013876: 687b ldr r3, [r7, #4] + 8013878: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 801387c: 2b05 cmp r3, #5 + 801387e: f200 8215 bhi.w 8013cac + pcb->rtime = 0; + 8013882: 687b ldr r3, [r7, #4] + 8013884: 2200 movs r2, #0 + 8013886: 861a strh r2, [r3, #48] ; 0x30 + tcp_rexmit_rto(pcb); + 8013888: 6878 ldr r0, [r7, #4] + 801388a: f002 fa4f bl 8015d2c + break; + 801388e: e20d b.n 8013cac + case SYN_RCVD: + if (flags & TCP_ACK) { + 8013890: 4b81 ldr r3, [pc, #516] ; (8013a98 ) + 8013892: 781b ldrb r3, [r3, #0] + 8013894: f003 0310 and.w r3, r3, #16 + 8013898: 2b00 cmp r3, #0 + 801389a: f000 80a1 beq.w 80139e0 + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 801389e: 4b7f ldr r3, [pc, #508] ; (8013a9c ) + 80138a0: 681a ldr r2, [r3, #0] + 80138a2: 687b ldr r3, [r7, #4] + 80138a4: 6c5b ldr r3, [r3, #68] ; 0x44 + 80138a6: 1ad3 subs r3, r2, r3 + 80138a8: 3b01 subs r3, #1 + 80138aa: 2b00 cmp r3, #0 + 80138ac: db7e blt.n 80139ac + 80138ae: 4b7b ldr r3, [pc, #492] ; (8013a9c ) + 80138b0: 681a ldr r2, [r3, #0] + 80138b2: 687b ldr r3, [r7, #4] + 80138b4: 6d1b ldr r3, [r3, #80] ; 0x50 + 80138b6: 1ad3 subs r3, r2, r3 + 80138b8: 2b00 cmp r3, #0 + 80138ba: dc77 bgt.n 80139ac + pcb->state = ESTABLISHED; + 80138bc: 687b ldr r3, [r7, #4] + 80138be: 2204 movs r2, #4 + 80138c0: 751a strb r2, [r3, #20] + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + if (pcb->listener == NULL) { + 80138c2: 687b ldr r3, [r7, #4] + 80138c4: 6fdb ldr r3, [r3, #124] ; 0x7c + 80138c6: 2b00 cmp r3, #0 + 80138c8: d102 bne.n 80138d0 + /* listen pcb might be closed by now */ + err = ERR_VAL; + 80138ca: 23fa movs r3, #250 ; 0xfa + 80138cc: 76bb strb r3, [r7, #26] + 80138ce: e01d b.n 801390c + } else +#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ + { +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL); + 80138d0: 687b ldr r3, [r7, #4] + 80138d2: 6fdb ldr r3, [r3, #124] ; 0x7c + 80138d4: 699b ldr r3, [r3, #24] + 80138d6: 2b00 cmp r3, #0 + 80138d8: d106 bne.n 80138e8 + 80138da: 4b76 ldr r3, [pc, #472] ; (8013ab4 ) + 80138dc: f44f 726a mov.w r2, #936 ; 0x3a8 + 80138e0: 4975 ldr r1, [pc, #468] ; (8013ab8 ) + 80138e2: 4876 ldr r0, [pc, #472] ; (8013abc ) + 80138e4: f008 fb96 bl 801c014 +#endif + tcp_backlog_accepted(pcb); + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err); + 80138e8: 687b ldr r3, [r7, #4] + 80138ea: 6fdb ldr r3, [r3, #124] ; 0x7c + 80138ec: 699b ldr r3, [r3, #24] + 80138ee: 2b00 cmp r3, #0 + 80138f0: d00a beq.n 8013908 + 80138f2: 687b ldr r3, [r7, #4] + 80138f4: 6fdb ldr r3, [r3, #124] ; 0x7c + 80138f6: 699b ldr r3, [r3, #24] + 80138f8: 687a ldr r2, [r7, #4] + 80138fa: 6910 ldr r0, [r2, #16] + 80138fc: 2200 movs r2, #0 + 80138fe: 6879 ldr r1, [r7, #4] + 8013900: 4798 blx r3 + 8013902: 4603 mov r3, r0 + 8013904: 76bb strb r3, [r7, #26] + 8013906: e001 b.n 801390c + 8013908: 23f0 movs r3, #240 ; 0xf0 + 801390a: 76bb strb r3, [r7, #26] + } + if (err != ERR_OK) { + 801390c: f997 301a ldrsb.w r3, [r7, #26] + 8013910: 2b00 cmp r3, #0 + 8013912: d00a beq.n 801392a + /* If the accept function returns with an error, we abort + * the connection. */ + /* Already aborted? */ + if (err != ERR_ABRT) { + 8013914: f997 301a ldrsb.w r3, [r7, #26] + 8013918: f113 0f0d cmn.w r3, #13 + 801391c: d002 beq.n 8013924 + tcp_abort(pcb); + 801391e: 6878 ldr r0, [r7, #4] + 8013920: f7fd ff8e bl 8011840 + } + return ERR_ABRT; + 8013924: f06f 030c mvn.w r3, #12 + 8013928: e1ce b.n 8013cc8 + } + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + 801392a: 6878 ldr r0, [r7, #4] + 801392c: f000 fae0 bl 8013ef0 + + /* Prevent ACK for SYN to generate a sent event */ + if (recv_acked != 0) { + 8013930: 4b63 ldr r3, [pc, #396] ; (8013ac0 ) + 8013932: 881b ldrh r3, [r3, #0] + 8013934: 2b00 cmp r3, #0 + 8013936: d005 beq.n 8013944 + recv_acked--; + 8013938: 4b61 ldr r3, [pc, #388] ; (8013ac0 ) + 801393a: 881b ldrh r3, [r3, #0] + 801393c: 3b01 subs r3, #1 + 801393e: b29a uxth r2, r3 + 8013940: 4b5f ldr r3, [pc, #380] ; (8013ac0 ) + 8013942: 801a strh r2, [r3, #0] + } + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + 8013944: 687b ldr r3, [r7, #4] + 8013946: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8013948: 009a lsls r2, r3, #2 + 801394a: 687b ldr r3, [r7, #4] + 801394c: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801394e: 005b lsls r3, r3, #1 + 8013950: f241 111c movw r1, #4380 ; 0x111c + 8013954: 428b cmp r3, r1 + 8013956: bf38 it cc + 8013958: 460b movcc r3, r1 + 801395a: 429a cmp r2, r3 + 801395c: d204 bcs.n 8013968 + 801395e: 687b ldr r3, [r7, #4] + 8013960: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8013962: 009b lsls r3, r3, #2 + 8013964: b29b uxth r3, r3 + 8013966: e00d b.n 8013984 + 8013968: 687b ldr r3, [r7, #4] + 801396a: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801396c: 005b lsls r3, r3, #1 + 801396e: f241 121c movw r2, #4380 ; 0x111c + 8013972: 4293 cmp r3, r2 + 8013974: d904 bls.n 8013980 + 8013976: 687b ldr r3, [r7, #4] + 8013978: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801397a: 005b lsls r3, r3, #1 + 801397c: b29b uxth r3, r3 + 801397e: e001 b.n 8013984 + 8013980: f241 131c movw r3, #4380 ; 0x111c + 8013984: 687a ldr r2, [r7, #4] + 8013986: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + + if (recv_flags & TF_GOT_FIN) { + 801398a: 4b4e ldr r3, [pc, #312] ; (8013ac4 ) + 801398c: 781b ldrb r3, [r3, #0] + 801398e: f003 0320 and.w r3, r3, #32 + 8013992: 2b00 cmp r3, #0 + 8013994: d037 beq.n 8013a06 + tcp_ack_now(pcb); + 8013996: 687b ldr r3, [r7, #4] + 8013998: 8b5b ldrh r3, [r3, #26] + 801399a: f043 0302 orr.w r3, r3, #2 + 801399e: b29a uxth r2, r3 + 80139a0: 687b ldr r3, [r7, #4] + 80139a2: 835a strh r2, [r3, #26] + pcb->state = CLOSE_WAIT; + 80139a4: 687b ldr r3, [r7, #4] + 80139a6: 2207 movs r2, #7 + 80139a8: 751a strb r2, [r3, #20] + if (recv_flags & TF_GOT_FIN) { + 80139aa: e02c b.n 8013a06 + } + } else { + /* incorrect ACK number, send RST */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80139ac: 4b3b ldr r3, [pc, #236] ; (8013a9c ) + 80139ae: 6819 ldr r1, [r3, #0] + 80139b0: 4b3b ldr r3, [pc, #236] ; (8013aa0 ) + 80139b2: 881b ldrh r3, [r3, #0] + 80139b4: 461a mov r2, r3 + 80139b6: 4b3b ldr r3, [pc, #236] ; (8013aa4 ) + 80139b8: 681b ldr r3, [r3, #0] + 80139ba: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 80139bc: 4b3a ldr r3, [pc, #232] ; (8013aa8 ) + 80139be: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80139c0: 885b ldrh r3, [r3, #2] + 80139c2: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 80139c4: 4a38 ldr r2, [pc, #224] ; (8013aa8 ) + 80139c6: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80139c8: 8812 ldrh r2, [r2, #0] + 80139ca: b292 uxth r2, r2 + 80139cc: 9202 str r2, [sp, #8] + 80139ce: 9301 str r3, [sp, #4] + 80139d0: 4b36 ldr r3, [pc, #216] ; (8013aac ) + 80139d2: 9300 str r3, [sp, #0] + 80139d4: 4b36 ldr r3, [pc, #216] ; (8013ab0 ) + 80139d6: 4602 mov r2, r0 + 80139d8: 6878 ldr r0, [r7, #4] + 80139da: f002 fbd1 bl 8016180 + } + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + /* Looks like another copy of the SYN - retransmit our SYN-ACK */ + tcp_rexmit(pcb); + } + break; + 80139de: e167 b.n 8013cb0 + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + 80139e0: 4b2d ldr r3, [pc, #180] ; (8013a98 ) + 80139e2: 781b ldrb r3, [r3, #0] + 80139e4: f003 0302 and.w r3, r3, #2 + 80139e8: 2b00 cmp r3, #0 + 80139ea: f000 8161 beq.w 8013cb0 + 80139ee: 687b ldr r3, [r7, #4] + 80139f0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80139f2: 1e5a subs r2, r3, #1 + 80139f4: 4b2b ldr r3, [pc, #172] ; (8013aa4 ) + 80139f6: 681b ldr r3, [r3, #0] + 80139f8: 429a cmp r2, r3 + 80139fa: f040 8159 bne.w 8013cb0 + tcp_rexmit(pcb); + 80139fe: 6878 ldr r0, [r7, #4] + 8013a00: f002 f9b6 bl 8015d70 + break; + 8013a04: e154 b.n 8013cb0 + 8013a06: e153 b.n 8013cb0 + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + tcp_receive(pcb); + 8013a08: 6878 ldr r0, [r7, #4] + 8013a0a: f000 fa71 bl 8013ef0 + if (recv_flags & TF_GOT_FIN) { /* passive close */ + 8013a0e: 4b2d ldr r3, [pc, #180] ; (8013ac4 ) + 8013a10: 781b ldrb r3, [r3, #0] + 8013a12: f003 0320 and.w r3, r3, #32 + 8013a16: 2b00 cmp r3, #0 + 8013a18: f000 814c beq.w 8013cb4 + tcp_ack_now(pcb); + 8013a1c: 687b ldr r3, [r7, #4] + 8013a1e: 8b5b ldrh r3, [r3, #26] + 8013a20: f043 0302 orr.w r3, r3, #2 + 8013a24: b29a uxth r2, r3 + 8013a26: 687b ldr r3, [r7, #4] + 8013a28: 835a strh r2, [r3, #26] + pcb->state = CLOSE_WAIT; + 8013a2a: 687b ldr r3, [r7, #4] + 8013a2c: 2207 movs r2, #7 + 8013a2e: 751a strb r2, [r3, #20] + } + break; + 8013a30: e140 b.n 8013cb4 + case FIN_WAIT_1: + tcp_receive(pcb); + 8013a32: 6878 ldr r0, [r7, #4] + 8013a34: f000 fa5c bl 8013ef0 + if (recv_flags & TF_GOT_FIN) { + 8013a38: 4b22 ldr r3, [pc, #136] ; (8013ac4 ) + 8013a3a: 781b ldrb r3, [r3, #0] + 8013a3c: f003 0320 and.w r3, r3, #32 + 8013a40: 2b00 cmp r3, #0 + 8013a42: d071 beq.n 8013b28 + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 8013a44: 4b14 ldr r3, [pc, #80] ; (8013a98 ) + 8013a46: 781b ldrb r3, [r3, #0] + 8013a48: f003 0310 and.w r3, r3, #16 + 8013a4c: 2b00 cmp r3, #0 + 8013a4e: d060 beq.n 8013b12 + 8013a50: 687b ldr r3, [r7, #4] + 8013a52: 6d1a ldr r2, [r3, #80] ; 0x50 + 8013a54: 4b11 ldr r3, [pc, #68] ; (8013a9c ) + 8013a56: 681b ldr r3, [r3, #0] + 8013a58: 429a cmp r2, r3 + 8013a5a: d15a bne.n 8013b12 + pcb->unsent == NULL) { + 8013a5c: 687b ldr r3, [r7, #4] + 8013a5e: 6edb ldr r3, [r3, #108] ; 0x6c + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 8013a60: 2b00 cmp r3, #0 + 8013a62: d156 bne.n 8013b12 + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + 8013a64: 687b ldr r3, [r7, #4] + 8013a66: 8b5b ldrh r3, [r3, #26] + 8013a68: f043 0302 orr.w r3, r3, #2 + 8013a6c: b29a uxth r2, r3 + 8013a6e: 687b ldr r3, [r7, #4] + 8013a70: 835a strh r2, [r3, #26] + tcp_pcb_purge(pcb); + 8013a72: 6878 ldr r0, [r7, #4] + 8013a74: f7fe fdbc bl 80125f0 + TCP_RMV_ACTIVE(pcb); + 8013a78: 4b13 ldr r3, [pc, #76] ; (8013ac8 ) + 8013a7a: 681b ldr r3, [r3, #0] + 8013a7c: 687a ldr r2, [r7, #4] + 8013a7e: 429a cmp r2, r3 + 8013a80: d105 bne.n 8013a8e + 8013a82: 4b11 ldr r3, [pc, #68] ; (8013ac8 ) + 8013a84: 681b ldr r3, [r3, #0] + 8013a86: 68db ldr r3, [r3, #12] + 8013a88: 4a0f ldr r2, [pc, #60] ; (8013ac8 ) + 8013a8a: 6013 str r3, [r2, #0] + 8013a8c: e02e b.n 8013aec + 8013a8e: 4b0e ldr r3, [pc, #56] ; (8013ac8 ) + 8013a90: 681b ldr r3, [r3, #0] + 8013a92: 617b str r3, [r7, #20] + 8013a94: e027 b.n 8013ae6 + 8013a96: bf00 nop + 8013a98: 2000cf74 .word 0x2000cf74 + 8013a9c: 2000cf6c .word 0x2000cf6c + 8013aa0: 2000cf72 .word 0x2000cf72 + 8013aa4: 2000cf68 .word 0x2000cf68 + 8013aa8: 2000cf58 .word 0x2000cf58 + 8013aac: 20009680 .word 0x20009680 + 8013ab0: 20009684 .word 0x20009684 + 8013ab4: 0801fc88 .word 0x0801fc88 + 8013ab8: 0801ff28 .word 0x0801ff28 + 8013abc: 0801fcd4 .word 0x0801fcd4 + 8013ac0: 2000cf70 .word 0x2000cf70 + 8013ac4: 2000cf75 .word 0x2000cf75 + 8013ac8: 2000cf3c .word 0x2000cf3c + 8013acc: 697b ldr r3, [r7, #20] + 8013ace: 68db ldr r3, [r3, #12] + 8013ad0: 687a ldr r2, [r7, #4] + 8013ad2: 429a cmp r2, r3 + 8013ad4: d104 bne.n 8013ae0 + 8013ad6: 687b ldr r3, [r7, #4] + 8013ad8: 68da ldr r2, [r3, #12] + 8013ada: 697b ldr r3, [r7, #20] + 8013adc: 60da str r2, [r3, #12] + 8013ade: e005 b.n 8013aec + 8013ae0: 697b ldr r3, [r7, #20] + 8013ae2: 68db ldr r3, [r3, #12] + 8013ae4: 617b str r3, [r7, #20] + 8013ae6: 697b ldr r3, [r7, #20] + 8013ae8: 2b00 cmp r3, #0 + 8013aea: d1ef bne.n 8013acc + 8013aec: 687b ldr r3, [r7, #4] + 8013aee: 2200 movs r2, #0 + 8013af0: 60da str r2, [r3, #12] + 8013af2: 4b77 ldr r3, [pc, #476] ; (8013cd0 ) + 8013af4: 2201 movs r2, #1 + 8013af6: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 8013af8: 687b ldr r3, [r7, #4] + 8013afa: 220a movs r2, #10 + 8013afc: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 8013afe: 4b75 ldr r3, [pc, #468] ; (8013cd4 ) + 8013b00: 681a ldr r2, [r3, #0] + 8013b02: 687b ldr r3, [r7, #4] + 8013b04: 60da str r2, [r3, #12] + 8013b06: 4a73 ldr r2, [pc, #460] ; (8013cd4 ) + 8013b08: 687b ldr r3, [r7, #4] + 8013b0a: 6013 str r3, [r2, #0] + 8013b0c: f002 fcfa bl 8016504 + } + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + pcb->unsent == NULL) { + pcb->state = FIN_WAIT_2; + } + break; + 8013b10: e0d2 b.n 8013cb8 + tcp_ack_now(pcb); + 8013b12: 687b ldr r3, [r7, #4] + 8013b14: 8b5b ldrh r3, [r3, #26] + 8013b16: f043 0302 orr.w r3, r3, #2 + 8013b1a: b29a uxth r2, r3 + 8013b1c: 687b ldr r3, [r7, #4] + 8013b1e: 835a strh r2, [r3, #26] + pcb->state = CLOSING; + 8013b20: 687b ldr r3, [r7, #4] + 8013b22: 2208 movs r2, #8 + 8013b24: 751a strb r2, [r3, #20] + break; + 8013b26: e0c7 b.n 8013cb8 + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 8013b28: 4b6b ldr r3, [pc, #428] ; (8013cd8 ) + 8013b2a: 781b ldrb r3, [r3, #0] + 8013b2c: f003 0310 and.w r3, r3, #16 + 8013b30: 2b00 cmp r3, #0 + 8013b32: f000 80c1 beq.w 8013cb8 + 8013b36: 687b ldr r3, [r7, #4] + 8013b38: 6d1a ldr r2, [r3, #80] ; 0x50 + 8013b3a: 4b68 ldr r3, [pc, #416] ; (8013cdc ) + 8013b3c: 681b ldr r3, [r3, #0] + 8013b3e: 429a cmp r2, r3 + 8013b40: f040 80ba bne.w 8013cb8 + pcb->unsent == NULL) { + 8013b44: 687b ldr r3, [r7, #4] + 8013b46: 6edb ldr r3, [r3, #108] ; 0x6c + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 8013b48: 2b00 cmp r3, #0 + 8013b4a: f040 80b5 bne.w 8013cb8 + pcb->state = FIN_WAIT_2; + 8013b4e: 687b ldr r3, [r7, #4] + 8013b50: 2206 movs r2, #6 + 8013b52: 751a strb r2, [r3, #20] + break; + 8013b54: e0b0 b.n 8013cb8 + case FIN_WAIT_2: + tcp_receive(pcb); + 8013b56: 6878 ldr r0, [r7, #4] + 8013b58: f000 f9ca bl 8013ef0 + if (recv_flags & TF_GOT_FIN) { + 8013b5c: 4b60 ldr r3, [pc, #384] ; (8013ce0 ) + 8013b5e: 781b ldrb r3, [r3, #0] + 8013b60: f003 0320 and.w r3, r3, #32 + 8013b64: 2b00 cmp r3, #0 + 8013b66: f000 80a9 beq.w 8013cbc + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + 8013b6a: 687b ldr r3, [r7, #4] + 8013b6c: 8b5b ldrh r3, [r3, #26] + 8013b6e: f043 0302 orr.w r3, r3, #2 + 8013b72: b29a uxth r2, r3 + 8013b74: 687b ldr r3, [r7, #4] + 8013b76: 835a strh r2, [r3, #26] + tcp_pcb_purge(pcb); + 8013b78: 6878 ldr r0, [r7, #4] + 8013b7a: f7fe fd39 bl 80125f0 + TCP_RMV_ACTIVE(pcb); + 8013b7e: 4b59 ldr r3, [pc, #356] ; (8013ce4 ) + 8013b80: 681b ldr r3, [r3, #0] + 8013b82: 687a ldr r2, [r7, #4] + 8013b84: 429a cmp r2, r3 + 8013b86: d105 bne.n 8013b94 + 8013b88: 4b56 ldr r3, [pc, #344] ; (8013ce4 ) + 8013b8a: 681b ldr r3, [r3, #0] + 8013b8c: 68db ldr r3, [r3, #12] + 8013b8e: 4a55 ldr r2, [pc, #340] ; (8013ce4 ) + 8013b90: 6013 str r3, [r2, #0] + 8013b92: e013 b.n 8013bbc + 8013b94: 4b53 ldr r3, [pc, #332] ; (8013ce4 ) + 8013b96: 681b ldr r3, [r3, #0] + 8013b98: 613b str r3, [r7, #16] + 8013b9a: e00c b.n 8013bb6 + 8013b9c: 693b ldr r3, [r7, #16] + 8013b9e: 68db ldr r3, [r3, #12] + 8013ba0: 687a ldr r2, [r7, #4] + 8013ba2: 429a cmp r2, r3 + 8013ba4: d104 bne.n 8013bb0 + 8013ba6: 687b ldr r3, [r7, #4] + 8013ba8: 68da ldr r2, [r3, #12] + 8013baa: 693b ldr r3, [r7, #16] + 8013bac: 60da str r2, [r3, #12] + 8013bae: e005 b.n 8013bbc + 8013bb0: 693b ldr r3, [r7, #16] + 8013bb2: 68db ldr r3, [r3, #12] + 8013bb4: 613b str r3, [r7, #16] + 8013bb6: 693b ldr r3, [r7, #16] + 8013bb8: 2b00 cmp r3, #0 + 8013bba: d1ef bne.n 8013b9c + 8013bbc: 687b ldr r3, [r7, #4] + 8013bbe: 2200 movs r2, #0 + 8013bc0: 60da str r2, [r3, #12] + 8013bc2: 4b43 ldr r3, [pc, #268] ; (8013cd0 ) + 8013bc4: 2201 movs r2, #1 + 8013bc6: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 8013bc8: 687b ldr r3, [r7, #4] + 8013bca: 220a movs r2, #10 + 8013bcc: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 8013bce: 4b41 ldr r3, [pc, #260] ; (8013cd4 ) + 8013bd0: 681a ldr r2, [r3, #0] + 8013bd2: 687b ldr r3, [r7, #4] + 8013bd4: 60da str r2, [r3, #12] + 8013bd6: 4a3f ldr r2, [pc, #252] ; (8013cd4 ) + 8013bd8: 687b ldr r3, [r7, #4] + 8013bda: 6013 str r3, [r2, #0] + 8013bdc: f002 fc92 bl 8016504 + } + break; + 8013be0: e06c b.n 8013cbc + case CLOSING: + tcp_receive(pcb); + 8013be2: 6878 ldr r0, [r7, #4] + 8013be4: f000 f984 bl 8013ef0 + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + 8013be8: 4b3b ldr r3, [pc, #236] ; (8013cd8 ) + 8013bea: 781b ldrb r3, [r3, #0] + 8013bec: f003 0310 and.w r3, r3, #16 + 8013bf0: 2b00 cmp r3, #0 + 8013bf2: d065 beq.n 8013cc0 + 8013bf4: 687b ldr r3, [r7, #4] + 8013bf6: 6d1a ldr r2, [r3, #80] ; 0x50 + 8013bf8: 4b38 ldr r3, [pc, #224] ; (8013cdc ) + 8013bfa: 681b ldr r3, [r3, #0] + 8013bfc: 429a cmp r2, r3 + 8013bfe: d15f bne.n 8013cc0 + 8013c00: 687b ldr r3, [r7, #4] + 8013c02: 6edb ldr r3, [r3, #108] ; 0x6c + 8013c04: 2b00 cmp r3, #0 + 8013c06: d15b bne.n 8013cc0 + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_pcb_purge(pcb); + 8013c08: 6878 ldr r0, [r7, #4] + 8013c0a: f7fe fcf1 bl 80125f0 + TCP_RMV_ACTIVE(pcb); + 8013c0e: 4b35 ldr r3, [pc, #212] ; (8013ce4 ) + 8013c10: 681b ldr r3, [r3, #0] + 8013c12: 687a ldr r2, [r7, #4] + 8013c14: 429a cmp r2, r3 + 8013c16: d105 bne.n 8013c24 + 8013c18: 4b32 ldr r3, [pc, #200] ; (8013ce4 ) + 8013c1a: 681b ldr r3, [r3, #0] + 8013c1c: 68db ldr r3, [r3, #12] + 8013c1e: 4a31 ldr r2, [pc, #196] ; (8013ce4 ) + 8013c20: 6013 str r3, [r2, #0] + 8013c22: e013 b.n 8013c4c + 8013c24: 4b2f ldr r3, [pc, #188] ; (8013ce4 ) + 8013c26: 681b ldr r3, [r3, #0] + 8013c28: 60fb str r3, [r7, #12] + 8013c2a: e00c b.n 8013c46 + 8013c2c: 68fb ldr r3, [r7, #12] + 8013c2e: 68db ldr r3, [r3, #12] + 8013c30: 687a ldr r2, [r7, #4] + 8013c32: 429a cmp r2, r3 + 8013c34: d104 bne.n 8013c40 + 8013c36: 687b ldr r3, [r7, #4] + 8013c38: 68da ldr r2, [r3, #12] + 8013c3a: 68fb ldr r3, [r7, #12] + 8013c3c: 60da str r2, [r3, #12] + 8013c3e: e005 b.n 8013c4c + 8013c40: 68fb ldr r3, [r7, #12] + 8013c42: 68db ldr r3, [r3, #12] + 8013c44: 60fb str r3, [r7, #12] + 8013c46: 68fb ldr r3, [r7, #12] + 8013c48: 2b00 cmp r3, #0 + 8013c4a: d1ef bne.n 8013c2c + 8013c4c: 687b ldr r3, [r7, #4] + 8013c4e: 2200 movs r2, #0 + 8013c50: 60da str r2, [r3, #12] + 8013c52: 4b1f ldr r3, [pc, #124] ; (8013cd0 ) + 8013c54: 2201 movs r2, #1 + 8013c56: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 8013c58: 687b ldr r3, [r7, #4] + 8013c5a: 220a movs r2, #10 + 8013c5c: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 8013c5e: 4b1d ldr r3, [pc, #116] ; (8013cd4 ) + 8013c60: 681a ldr r2, [r3, #0] + 8013c62: 687b ldr r3, [r7, #4] + 8013c64: 60da str r2, [r3, #12] + 8013c66: 4a1b ldr r2, [pc, #108] ; (8013cd4 ) + 8013c68: 687b ldr r3, [r7, #4] + 8013c6a: 6013 str r3, [r2, #0] + 8013c6c: f002 fc4a bl 8016504 + } + break; + 8013c70: e026 b.n 8013cc0 + case LAST_ACK: + tcp_receive(pcb); + 8013c72: 6878 ldr r0, [r7, #4] + 8013c74: f000 f93c bl 8013ef0 + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + 8013c78: 4b17 ldr r3, [pc, #92] ; (8013cd8 ) + 8013c7a: 781b ldrb r3, [r3, #0] + 8013c7c: f003 0310 and.w r3, r3, #16 + 8013c80: 2b00 cmp r3, #0 + 8013c82: d01f beq.n 8013cc4 + 8013c84: 687b ldr r3, [r7, #4] + 8013c86: 6d1a ldr r2, [r3, #80] ; 0x50 + 8013c88: 4b14 ldr r3, [pc, #80] ; (8013cdc ) + 8013c8a: 681b ldr r3, [r3, #0] + 8013c8c: 429a cmp r2, r3 + 8013c8e: d119 bne.n 8013cc4 + 8013c90: 687b ldr r3, [r7, #4] + 8013c92: 6edb ldr r3, [r3, #108] ; 0x6c + 8013c94: 2b00 cmp r3, #0 + 8013c96: d115 bne.n 8013cc4 + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ + recv_flags |= TF_CLOSED; + 8013c98: 4b11 ldr r3, [pc, #68] ; (8013ce0 ) + 8013c9a: 781b ldrb r3, [r3, #0] + 8013c9c: f043 0310 orr.w r3, r3, #16 + 8013ca0: b2da uxtb r2, r3 + 8013ca2: 4b0f ldr r3, [pc, #60] ; (8013ce0 ) + 8013ca4: 701a strb r2, [r3, #0] + } + break; + 8013ca6: e00d b.n 8013cc4 + default: + break; + 8013ca8: bf00 nop + 8013caa: e00c b.n 8013cc6 + break; + 8013cac: bf00 nop + 8013cae: e00a b.n 8013cc6 + break; + 8013cb0: bf00 nop + 8013cb2: e008 b.n 8013cc6 + break; + 8013cb4: bf00 nop + 8013cb6: e006 b.n 8013cc6 + break; + 8013cb8: bf00 nop + 8013cba: e004 b.n 8013cc6 + break; + 8013cbc: bf00 nop + 8013cbe: e002 b.n 8013cc6 + break; + 8013cc0: bf00 nop + 8013cc2: e000 b.n 8013cc6 + break; + 8013cc4: bf00 nop + } + return ERR_OK; + 8013cc6: 2300 movs r3, #0 +} + 8013cc8: 4618 mov r0, r3 + 8013cca: 3724 adds r7, #36 ; 0x24 + 8013ccc: 46bd mov sp, r7 + 8013cce: bd90 pop {r4, r7, pc} + 8013cd0: 2000cf44 .word 0x2000cf44 + 8013cd4: 2000cf40 .word 0x2000cf40 + 8013cd8: 2000cf74 .word 0x2000cf74 + 8013cdc: 2000cf6c .word 0x2000cf6c + 8013ce0: 2000cf75 .word 0x2000cf75 + 8013ce4: 2000cf3c .word 0x2000cf3c + +08013ce8 : + * + * Called from tcp_receive() + */ +static void +tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) +{ + 8013ce8: b590 push {r4, r7, lr} + 8013cea: b085 sub sp, #20 + 8013cec: af00 add r7, sp, #0 + 8013cee: 6078 str r0, [r7, #4] + 8013cf0: 6039 str r1, [r7, #0] + struct tcp_seg *old_seg; + + LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL); + 8013cf2: 687b ldr r3, [r7, #4] + 8013cf4: 2b00 cmp r3, #0 + 8013cf6: d106 bne.n 8013d06 + 8013cf8: 4b3b ldr r3, [pc, #236] ; (8013de8 ) + 8013cfa: f240 421f movw r2, #1055 ; 0x41f + 8013cfe: 493b ldr r1, [pc, #236] ; (8013dec ) + 8013d00: 483b ldr r0, [pc, #236] ; (8013df0 ) + 8013d02: f008 f987 bl 801c014 + + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + 8013d06: 687b ldr r3, [r7, #4] + 8013d08: 68db ldr r3, [r3, #12] + 8013d0a: 899b ldrh r3, [r3, #12] + 8013d0c: b29b uxth r3, r3 + 8013d0e: 4618 mov r0, r3 + 8013d10: f7fa fa8e bl 800e230 + 8013d14: 4603 mov r3, r0 + 8013d16: b2db uxtb r3, r3 + 8013d18: f003 0301 and.w r3, r3, #1 + 8013d1c: 2b00 cmp r3, #0 + 8013d1e: d028 beq.n 8013d72 + /* received segment overlaps all following segments */ + tcp_segs_free(next); + 8013d20: 6838 ldr r0, [r7, #0] + 8013d22: f7fe fa63 bl 80121ec + next = NULL; + 8013d26: 2300 movs r3, #0 + 8013d28: 603b str r3, [r7, #0] + 8013d2a: e056 b.n 8013dda + oos queue may have segments with FIN flag */ + while (next && + TCP_SEQ_GEQ((seqno + cseg->len), + (next->tcphdr->seqno + next->len))) { + /* cseg with FIN already processed */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + 8013d2c: 683b ldr r3, [r7, #0] + 8013d2e: 68db ldr r3, [r3, #12] + 8013d30: 899b ldrh r3, [r3, #12] + 8013d32: b29b uxth r3, r3 + 8013d34: 4618 mov r0, r3 + 8013d36: f7fa fa7b bl 800e230 + 8013d3a: 4603 mov r3, r0 + 8013d3c: b2db uxtb r3, r3 + 8013d3e: f003 0301 and.w r3, r3, #1 + 8013d42: 2b00 cmp r3, #0 + 8013d44: d00d beq.n 8013d62 + TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); + 8013d46: 687b ldr r3, [r7, #4] + 8013d48: 68db ldr r3, [r3, #12] + 8013d4a: 899b ldrh r3, [r3, #12] + 8013d4c: b29c uxth r4, r3 + 8013d4e: 2001 movs r0, #1 + 8013d50: f7fa fa6e bl 800e230 + 8013d54: 4603 mov r3, r0 + 8013d56: 461a mov r2, r3 + 8013d58: 687b ldr r3, [r7, #4] + 8013d5a: 68db ldr r3, [r3, #12] + 8013d5c: 4322 orrs r2, r4 + 8013d5e: b292 uxth r2, r2 + 8013d60: 819a strh r2, [r3, #12] + } + old_seg = next; + 8013d62: 683b ldr r3, [r7, #0] + 8013d64: 60fb str r3, [r7, #12] + next = next->next; + 8013d66: 683b ldr r3, [r7, #0] + 8013d68: 681b ldr r3, [r3, #0] + 8013d6a: 603b str r3, [r7, #0] + tcp_seg_free(old_seg); + 8013d6c: 68f8 ldr r0, [r7, #12] + 8013d6e: f7fe fa52 bl 8012216 + while (next && + 8013d72: 683b ldr r3, [r7, #0] + 8013d74: 2b00 cmp r3, #0 + 8013d76: d00e beq.n 8013d96 + TCP_SEQ_GEQ((seqno + cseg->len), + 8013d78: 687b ldr r3, [r7, #4] + 8013d7a: 891b ldrh r3, [r3, #8] + 8013d7c: 461a mov r2, r3 + 8013d7e: 4b1d ldr r3, [pc, #116] ; (8013df4 ) + 8013d80: 681b ldr r3, [r3, #0] + 8013d82: 441a add r2, r3 + 8013d84: 683b ldr r3, [r7, #0] + 8013d86: 68db ldr r3, [r3, #12] + 8013d88: 685b ldr r3, [r3, #4] + 8013d8a: 6839 ldr r1, [r7, #0] + 8013d8c: 8909 ldrh r1, [r1, #8] + 8013d8e: 440b add r3, r1 + 8013d90: 1ad3 subs r3, r2, r3 + while (next && + 8013d92: 2b00 cmp r3, #0 + 8013d94: daca bge.n 8013d2c + } + if (next && + 8013d96: 683b ldr r3, [r7, #0] + 8013d98: 2b00 cmp r3, #0 + 8013d9a: d01e beq.n 8013dda + TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { + 8013d9c: 687b ldr r3, [r7, #4] + 8013d9e: 891b ldrh r3, [r3, #8] + 8013da0: 461a mov r2, r3 + 8013da2: 4b14 ldr r3, [pc, #80] ; (8013df4 ) + 8013da4: 681b ldr r3, [r3, #0] + 8013da6: 441a add r2, r3 + 8013da8: 683b ldr r3, [r7, #0] + 8013daa: 68db ldr r3, [r3, #12] + 8013dac: 685b ldr r3, [r3, #4] + 8013dae: 1ad3 subs r3, r2, r3 + if (next && + 8013db0: 2b00 cmp r3, #0 + 8013db2: dd12 ble.n 8013dda + /* We need to trim the incoming segment. */ + cseg->len = (u16_t)(next->tcphdr->seqno - seqno); + 8013db4: 683b ldr r3, [r7, #0] + 8013db6: 68db ldr r3, [r3, #12] + 8013db8: 685b ldr r3, [r3, #4] + 8013dba: b29a uxth r2, r3 + 8013dbc: 4b0d ldr r3, [pc, #52] ; (8013df4 ) + 8013dbe: 681b ldr r3, [r3, #0] + 8013dc0: b29b uxth r3, r3 + 8013dc2: 1ad3 subs r3, r2, r3 + 8013dc4: b29a uxth r2, r3 + 8013dc6: 687b ldr r3, [r7, #4] + 8013dc8: 811a strh r2, [r3, #8] + pbuf_realloc(cseg->p, cseg->len); + 8013dca: 687b ldr r3, [r7, #4] + 8013dcc: 685a ldr r2, [r3, #4] + 8013dce: 687b ldr r3, [r7, #4] + 8013dd0: 891b ldrh r3, [r3, #8] + 8013dd2: 4619 mov r1, r3 + 8013dd4: 4610 mov r0, r2 + 8013dd6: f7fc fc8d bl 80106f4 + } + } + cseg->next = next; + 8013dda: 687b ldr r3, [r7, #4] + 8013ddc: 683a ldr r2, [r7, #0] + 8013dde: 601a str r2, [r3, #0] +} + 8013de0: bf00 nop + 8013de2: 3714 adds r7, #20 + 8013de4: 46bd mov sp, r7 + 8013de6: bd90 pop {r4, r7, pc} + 8013de8: 0801fc88 .word 0x0801fc88 + 8013dec: 0801ff48 .word 0x0801ff48 + 8013df0: 0801fcd4 .word 0x0801fcd4 + 8013df4: 2000cf68 .word 0x2000cf68 + +08013df8 : + +/** Remove segments from a list if the incoming ACK acknowledges them */ +static struct tcp_seg * +tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name, + struct tcp_seg *dbg_other_seg_list) +{ + 8013df8: b5b0 push {r4, r5, r7, lr} + 8013dfa: b086 sub sp, #24 + 8013dfc: af00 add r7, sp, #0 + 8013dfe: 60f8 str r0, [r7, #12] + 8013e00: 60b9 str r1, [r7, #8] + 8013e02: 607a str r2, [r7, #4] + 8013e04: 603b str r3, [r7, #0] + u16_t clen; + + LWIP_UNUSED_ARG(dbg_list_name); + LWIP_UNUSED_ARG(dbg_other_seg_list); + + while (seg_list != NULL && + 8013e06: e03e b.n 8013e86 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n", + lwip_ntohl(seg_list->tcphdr->seqno), + lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list), + dbg_list_name)); + + next = seg_list; + 8013e08: 68bb ldr r3, [r7, #8] + 8013e0a: 617b str r3, [r7, #20] + seg_list = seg_list->next; + 8013e0c: 68bb ldr r3, [r7, #8] + 8013e0e: 681b ldr r3, [r3, #0] + 8013e10: 60bb str r3, [r7, #8] + + clen = pbuf_clen(next->p); + 8013e12: 697b ldr r3, [r7, #20] + 8013e14: 685b ldr r3, [r3, #4] + 8013e16: 4618 mov r0, r3 + 8013e18: f7fc fe80 bl 8010b1c + 8013e1c: 4603 mov r3, r0 + 8013e1e: 827b strh r3, [r7, #18] + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", + (tcpwnd_size_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen)); + 8013e20: 68fb ldr r3, [r7, #12] + 8013e22: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8013e26: 8a7a ldrh r2, [r7, #18] + 8013e28: 429a cmp r2, r3 + 8013e2a: d906 bls.n 8013e3a + 8013e2c: 4b2a ldr r3, [pc, #168] ; (8013ed8 ) + 8013e2e: f240 4257 movw r2, #1111 ; 0x457 + 8013e32: 492a ldr r1, [pc, #168] ; (8013edc ) + 8013e34: 482a ldr r0, [pc, #168] ; (8013ee0 ) + 8013e36: f008 f8ed bl 801c014 + + pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen); + 8013e3a: 68fb ldr r3, [r7, #12] + 8013e3c: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66 + 8013e40: 8a7b ldrh r3, [r7, #18] + 8013e42: 1ad3 subs r3, r2, r3 + 8013e44: b29a uxth r2, r3 + 8013e46: 68fb ldr r3, [r7, #12] + 8013e48: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + recv_acked = (tcpwnd_size_t)(recv_acked + next->len); + 8013e4c: 697b ldr r3, [r7, #20] + 8013e4e: 891a ldrh r2, [r3, #8] + 8013e50: 4b24 ldr r3, [pc, #144] ; (8013ee4 ) + 8013e52: 881b ldrh r3, [r3, #0] + 8013e54: 4413 add r3, r2 + 8013e56: b29a uxth r2, r3 + 8013e58: 4b22 ldr r3, [pc, #136] ; (8013ee4 ) + 8013e5a: 801a strh r2, [r3, #0] + tcp_seg_free(next); + 8013e5c: 6978 ldr r0, [r7, #20] + 8013e5e: f7fe f9da bl 8012216 + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n", + (tcpwnd_size_t)pcb->snd_queuelen, + dbg_list_name)); + if (pcb->snd_queuelen != 0) { + 8013e62: 68fb ldr r3, [r7, #12] + 8013e64: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8013e68: 2b00 cmp r3, #0 + 8013e6a: d00c beq.n 8013e86 + LWIP_ASSERT("tcp_receive: valid queue length", + 8013e6c: 68bb ldr r3, [r7, #8] + 8013e6e: 2b00 cmp r3, #0 + 8013e70: d109 bne.n 8013e86 + 8013e72: 683b ldr r3, [r7, #0] + 8013e74: 2b00 cmp r3, #0 + 8013e76: d106 bne.n 8013e86 + 8013e78: 4b17 ldr r3, [pc, #92] ; (8013ed8 ) + 8013e7a: f240 4261 movw r2, #1121 ; 0x461 + 8013e7e: 491a ldr r1, [pc, #104] ; (8013ee8 ) + 8013e80: 4817 ldr r0, [pc, #92] ; (8013ee0 ) + 8013e82: f008 f8c7 bl 801c014 + while (seg_list != NULL && + 8013e86: 68bb ldr r3, [r7, #8] + 8013e88: 2b00 cmp r3, #0 + 8013e8a: d020 beq.n 8013ece + TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) + + 8013e8c: 68bb ldr r3, [r7, #8] + 8013e8e: 68db ldr r3, [r3, #12] + 8013e90: 685b ldr r3, [r3, #4] + 8013e92: 4618 mov r0, r3 + 8013e94: f7fa f9e1 bl 800e25a + 8013e98: 4604 mov r4, r0 + 8013e9a: 68bb ldr r3, [r7, #8] + 8013e9c: 891b ldrh r3, [r3, #8] + 8013e9e: 461d mov r5, r3 + 8013ea0: 68bb ldr r3, [r7, #8] + 8013ea2: 68db ldr r3, [r3, #12] + 8013ea4: 899b ldrh r3, [r3, #12] + 8013ea6: b29b uxth r3, r3 + 8013ea8: 4618 mov r0, r3 + 8013eaa: f7fa f9c1 bl 800e230 + 8013eae: 4603 mov r3, r0 + 8013eb0: b2db uxtb r3, r3 + 8013eb2: f003 0303 and.w r3, r3, #3 + 8013eb6: 2b00 cmp r3, #0 + 8013eb8: d001 beq.n 8013ebe + 8013eba: 2301 movs r3, #1 + 8013ebc: e000 b.n 8013ec0 + 8013ebe: 2300 movs r3, #0 + 8013ec0: 442b add r3, r5 + 8013ec2: 18e2 adds r2, r4, r3 + 8013ec4: 4b09 ldr r3, [pc, #36] ; (8013eec ) + 8013ec6: 681b ldr r3, [r3, #0] + 8013ec8: 1ad3 subs r3, r2, r3 + while (seg_list != NULL && + 8013eca: 2b00 cmp r3, #0 + 8013ecc: dd9c ble.n 8013e08 + seg_list != NULL || dbg_other_seg_list != NULL); + } + } + return seg_list; + 8013ece: 68bb ldr r3, [r7, #8] +} + 8013ed0: 4618 mov r0, r3 + 8013ed2: 3718 adds r7, #24 + 8013ed4: 46bd mov sp, r7 + 8013ed6: bdb0 pop {r4, r5, r7, pc} + 8013ed8: 0801fc88 .word 0x0801fc88 + 8013edc: 0801ff70 .word 0x0801ff70 + 8013ee0: 0801fcd4 .word 0x0801fcd4 + 8013ee4: 2000cf70 .word 0x2000cf70 + 8013ee8: 0801ff98 .word 0x0801ff98 + 8013eec: 2000cf6c .word 0x2000cf6c + +08013ef0 : + * + * Called from tcp_process(). + */ +static void +tcp_receive(struct tcp_pcb *pcb) +{ + 8013ef0: b5b0 push {r4, r5, r7, lr} + 8013ef2: b094 sub sp, #80 ; 0x50 + 8013ef4: af00 add r7, sp, #0 + 8013ef6: 6078 str r0, [r7, #4] + s16_t m; + u32_t right_wnd_edge; + int found_dupack = 0; + 8013ef8: 2300 movs r3, #0 + 8013efa: 64bb str r3, [r7, #72] ; 0x48 + + LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL); + 8013efc: 687b ldr r3, [r7, #4] + 8013efe: 2b00 cmp r3, #0 + 8013f00: d106 bne.n 8013f10 + 8013f02: 4b91 ldr r3, [pc, #580] ; (8014148 ) + 8013f04: f240 427b movw r2, #1147 ; 0x47b + 8013f08: 4990 ldr r1, [pc, #576] ; (801414c ) + 8013f0a: 4891 ldr r0, [pc, #580] ; (8014150 ) + 8013f0c: f008 f882 bl 801c014 + LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED); + 8013f10: 687b ldr r3, [r7, #4] + 8013f12: 7d1b ldrb r3, [r3, #20] + 8013f14: 2b03 cmp r3, #3 + 8013f16: d806 bhi.n 8013f26 + 8013f18: 4b8b ldr r3, [pc, #556] ; (8014148 ) + 8013f1a: f240 427c movw r2, #1148 ; 0x47c + 8013f1e: 498d ldr r1, [pc, #564] ; (8014154 ) + 8013f20: 488b ldr r0, [pc, #556] ; (8014150 ) + 8013f22: f008 f877 bl 801c014 + + if (flags & TCP_ACK) { + 8013f26: 4b8c ldr r3, [pc, #560] ; (8014158 ) + 8013f28: 781b ldrb r3, [r3, #0] + 8013f2a: f003 0310 and.w r3, r3, #16 + 8013f2e: 2b00 cmp r3, #0 + 8013f30: f000 8264 beq.w 80143fc + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; + 8013f34: 687b ldr r3, [r7, #4] + 8013f36: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8013f3a: 461a mov r2, r3 + 8013f3c: 687b ldr r3, [r7, #4] + 8013f3e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8013f40: 4413 add r3, r2 + 8013f42: 633b str r3, [r7, #48] ; 0x30 + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + 8013f44: 687b ldr r3, [r7, #4] + 8013f46: 6d5a ldr r2, [r3, #84] ; 0x54 + 8013f48: 4b84 ldr r3, [pc, #528] ; (801415c ) + 8013f4a: 681b ldr r3, [r3, #0] + 8013f4c: 1ad3 subs r3, r2, r3 + 8013f4e: 2b00 cmp r3, #0 + 8013f50: db1b blt.n 8013f8a + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 8013f52: 687b ldr r3, [r7, #4] + 8013f54: 6d5a ldr r2, [r3, #84] ; 0x54 + 8013f56: 4b81 ldr r3, [pc, #516] ; (801415c ) + 8013f58: 681b ldr r3, [r3, #0] + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + 8013f5a: 429a cmp r2, r3 + 8013f5c: d106 bne.n 8013f6c + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 8013f5e: 687b ldr r3, [r7, #4] + 8013f60: 6d9a ldr r2, [r3, #88] ; 0x58 + 8013f62: 4b7f ldr r3, [pc, #508] ; (8014160 ) + 8013f64: 681b ldr r3, [r3, #0] + 8013f66: 1ad3 subs r3, r2, r3 + 8013f68: 2b00 cmp r3, #0 + 8013f6a: db0e blt.n 8013f8a + (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { + 8013f6c: 687b ldr r3, [r7, #4] + 8013f6e: 6d9a ldr r2, [r3, #88] ; 0x58 + 8013f70: 4b7b ldr r3, [pc, #492] ; (8014160 ) + 8013f72: 681b ldr r3, [r3, #0] + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 8013f74: 429a cmp r2, r3 + 8013f76: d125 bne.n 8013fc4 + (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { + 8013f78: 4b7a ldr r3, [pc, #488] ; (8014164 ) + 8013f7a: 681b ldr r3, [r3, #0] + 8013f7c: 89db ldrh r3, [r3, #14] + 8013f7e: b29a uxth r2, r3 + 8013f80: 687b ldr r3, [r7, #4] + 8013f82: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8013f86: 429a cmp r2, r3 + 8013f88: d91c bls.n 8013fc4 + pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd); + 8013f8a: 4b76 ldr r3, [pc, #472] ; (8014164 ) + 8013f8c: 681b ldr r3, [r3, #0] + 8013f8e: 89db ldrh r3, [r3, #14] + 8013f90: b29a uxth r2, r3 + 8013f92: 687b ldr r3, [r7, #4] + 8013f94: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + /* keep track of the biggest window announced by the remote host to calculate + the maximum segment size */ + if (pcb->snd_wnd_max < pcb->snd_wnd) { + 8013f98: 687b ldr r3, [r7, #4] + 8013f9a: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62 + 8013f9e: 687b ldr r3, [r7, #4] + 8013fa0: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8013fa4: 429a cmp r2, r3 + 8013fa6: d205 bcs.n 8013fb4 + pcb->snd_wnd_max = pcb->snd_wnd; + 8013fa8: 687b ldr r3, [r7, #4] + 8013faa: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 8013fae: 687b ldr r3, [r7, #4] + 8013fb0: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + } + pcb->snd_wl1 = seqno; + 8013fb4: 4b69 ldr r3, [pc, #420] ; (801415c ) + 8013fb6: 681a ldr r2, [r3, #0] + 8013fb8: 687b ldr r3, [r7, #4] + 8013fba: 655a str r2, [r3, #84] ; 0x54 + pcb->snd_wl2 = ackno; + 8013fbc: 4b68 ldr r3, [pc, #416] ; (8014160 ) + 8013fbe: 681a ldr r2, [r3, #0] + 8013fc0: 687b ldr r3, [r7, #4] + 8013fc2: 659a str r2, [r3, #88] ; 0x58 + * If it only passes 1, should reset dupack counter + * + */ + + /* Clause 1 */ + if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { + 8013fc4: 4b66 ldr r3, [pc, #408] ; (8014160 ) + 8013fc6: 681a ldr r2, [r3, #0] + 8013fc8: 687b ldr r3, [r7, #4] + 8013fca: 6c5b ldr r3, [r3, #68] ; 0x44 + 8013fcc: 1ad3 subs r3, r2, r3 + 8013fce: 2b00 cmp r3, #0 + 8013fd0: dc58 bgt.n 8014084 + /* Clause 2 */ + if (tcplen == 0) { + 8013fd2: 4b65 ldr r3, [pc, #404] ; (8014168 ) + 8013fd4: 881b ldrh r3, [r3, #0] + 8013fd6: 2b00 cmp r3, #0 + 8013fd8: d14b bne.n 8014072 + /* Clause 3 */ + if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) { + 8013fda: 687b ldr r3, [r7, #4] + 8013fdc: 6d9b ldr r3, [r3, #88] ; 0x58 + 8013fde: 687a ldr r2, [r7, #4] + 8013fe0: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60 + 8013fe4: 4413 add r3, r2 + 8013fe6: 6b3a ldr r2, [r7, #48] ; 0x30 + 8013fe8: 429a cmp r2, r3 + 8013fea: d142 bne.n 8014072 + /* Clause 4 */ + if (pcb->rtime >= 0) { + 8013fec: 687b ldr r3, [r7, #4] + 8013fee: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 8013ff2: 2b00 cmp r3, #0 + 8013ff4: db3d blt.n 8014072 + /* Clause 5 */ + if (pcb->lastack == ackno) { + 8013ff6: 687b ldr r3, [r7, #4] + 8013ff8: 6c5a ldr r2, [r3, #68] ; 0x44 + 8013ffa: 4b59 ldr r3, [pc, #356] ; (8014160 ) + 8013ffc: 681b ldr r3, [r3, #0] + 8013ffe: 429a cmp r2, r3 + 8014000: d137 bne.n 8014072 + found_dupack = 1; + 8014002: 2301 movs r3, #1 + 8014004: 64bb str r3, [r7, #72] ; 0x48 + if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) { + 8014006: 687b ldr r3, [r7, #4] + 8014008: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 801400c: 2bff cmp r3, #255 ; 0xff + 801400e: d007 beq.n 8014020 + ++pcb->dupacks; + 8014010: 687b ldr r3, [r7, #4] + 8014012: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 8014016: 3301 adds r3, #1 + 8014018: b2da uxtb r2, r3 + 801401a: 687b ldr r3, [r7, #4] + 801401c: f883 2043 strb.w r2, [r3, #67] ; 0x43 + } + if (pcb->dupacks > 3) { + 8014020: 687b ldr r3, [r7, #4] + 8014022: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 8014026: 2b03 cmp r3, #3 + 8014028: d91b bls.n 8014062 + /* Inflate the congestion window */ + TCP_WND_INC(pcb->cwnd, pcb->mss); + 801402a: 687b ldr r3, [r7, #4] + 801402c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 8014030: 687b ldr r3, [r7, #4] + 8014032: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8014034: 4413 add r3, r2 + 8014036: b29a uxth r2, r3 + 8014038: 687b ldr r3, [r7, #4] + 801403a: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 801403e: 429a cmp r2, r3 + 8014040: d30a bcc.n 8014058 + 8014042: 687b ldr r3, [r7, #4] + 8014044: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 8014048: 687b ldr r3, [r7, #4] + 801404a: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801404c: 4413 add r3, r2 + 801404e: b29a uxth r2, r3 + 8014050: 687b ldr r3, [r7, #4] + 8014052: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 8014056: e004 b.n 8014062 + 8014058: 687b ldr r3, [r7, #4] + 801405a: f64f 72ff movw r2, #65535 ; 0xffff + 801405e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + } + if (pcb->dupacks >= 3) { + 8014062: 687b ldr r3, [r7, #4] + 8014064: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 8014068: 2b02 cmp r3, #2 + 801406a: d902 bls.n 8014072 + /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */ + tcp_rexmit_fast(pcb); + 801406c: 6878 ldr r0, [r7, #4] + 801406e: f001 feeb bl 8015e48 + } + } + } + /* If Clause (1) or more is true, but not a duplicate ack, reset + * count of consecutive duplicate acks */ + if (!found_dupack) { + 8014072: 6cbb ldr r3, [r7, #72] ; 0x48 + 8014074: 2b00 cmp r3, #0 + 8014076: f040 8161 bne.w 801433c + pcb->dupacks = 0; + 801407a: 687b ldr r3, [r7, #4] + 801407c: 2200 movs r2, #0 + 801407e: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 8014082: e15b b.n 801433c + } + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 8014084: 4b36 ldr r3, [pc, #216] ; (8014160 ) + 8014086: 681a ldr r2, [r3, #0] + 8014088: 687b ldr r3, [r7, #4] + 801408a: 6c5b ldr r3, [r3, #68] ; 0x44 + 801408c: 1ad3 subs r3, r2, r3 + 801408e: 3b01 subs r3, #1 + 8014090: 2b00 cmp r3, #0 + 8014092: f2c0 814e blt.w 8014332 + 8014096: 4b32 ldr r3, [pc, #200] ; (8014160 ) + 8014098: 681a ldr r2, [r3, #0] + 801409a: 687b ldr r3, [r7, #4] + 801409c: 6d1b ldr r3, [r3, #80] ; 0x50 + 801409e: 1ad3 subs r3, r2, r3 + 80140a0: 2b00 cmp r3, #0 + 80140a2: f300 8146 bgt.w 8014332 + tcpwnd_size_t acked; + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + 80140a6: 687b ldr r3, [r7, #4] + 80140a8: 8b5b ldrh r3, [r3, #26] + 80140aa: f003 0304 and.w r3, r3, #4 + 80140ae: 2b00 cmp r3, #0 + 80140b0: d010 beq.n 80140d4 + tcp_clear_flags(pcb, TF_INFR); + 80140b2: 687b ldr r3, [r7, #4] + 80140b4: 8b5b ldrh r3, [r3, #26] + 80140b6: f023 0304 bic.w r3, r3, #4 + 80140ba: b29a uxth r2, r3 + 80140bc: 687b ldr r3, [r7, #4] + 80140be: 835a strh r2, [r3, #26] + pcb->cwnd = pcb->ssthresh; + 80140c0: 687b ldr r3, [r7, #4] + 80140c2: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 80140c6: 687b ldr r3, [r7, #4] + 80140c8: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->bytes_acked = 0; + 80140cc: 687b ldr r3, [r7, #4] + 80140ce: 2200 movs r2, #0 + 80140d0: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + 80140d4: 687b ldr r3, [r7, #4] + 80140d6: 2200 movs r2, #0 + 80140d8: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Reset the retransmission time-out. */ + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + 80140dc: 687b ldr r3, [r7, #4] + 80140de: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 80140e2: 10db asrs r3, r3, #3 + 80140e4: b21b sxth r3, r3 + 80140e6: b29a uxth r2, r3 + 80140e8: 687b ldr r3, [r7, #4] + 80140ea: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 80140ee: b29b uxth r3, r3 + 80140f0: 4413 add r3, r2 + 80140f2: b29b uxth r3, r3 + 80140f4: b21a sxth r2, r3 + 80140f6: 687b ldr r3, [r7, #4] + 80140f8: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /* Record how much data this ACK acks */ + acked = (tcpwnd_size_t)(ackno - pcb->lastack); + 80140fc: 4b18 ldr r3, [pc, #96] ; (8014160 ) + 80140fe: 681b ldr r3, [r3, #0] + 8014100: b29a uxth r2, r3 + 8014102: 687b ldr r3, [r7, #4] + 8014104: 6c5b ldr r3, [r3, #68] ; 0x44 + 8014106: b29b uxth r3, r3 + 8014108: 1ad3 subs r3, r2, r3 + 801410a: 85fb strh r3, [r7, #46] ; 0x2e + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + 801410c: 687b ldr r3, [r7, #4] + 801410e: 2200 movs r2, #0 + 8014110: f883 2043 strb.w r2, [r3, #67] ; 0x43 + pcb->lastack = ackno; + 8014114: 4b12 ldr r3, [pc, #72] ; (8014160 ) + 8014116: 681a ldr r2, [r3, #0] + 8014118: 687b ldr r3, [r7, #4] + 801411a: 645a str r2, [r3, #68] ; 0x44 + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + 801411c: 687b ldr r3, [r7, #4] + 801411e: 7d1b ldrb r3, [r3, #20] + 8014120: 2b03 cmp r3, #3 + 8014122: f240 8097 bls.w 8014254 + if (pcb->cwnd < pcb->ssthresh) { + 8014126: 687b ldr r3, [r7, #4] + 8014128: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 801412c: 687b ldr r3, [r7, #4] + 801412e: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a + 8014132: 429a cmp r2, r3 + 8014134: d245 bcs.n 80141c2 + tcpwnd_size_t increase; + /* limit to 1 SMSS segment during period following RTO */ + u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2; + 8014136: 687b ldr r3, [r7, #4] + 8014138: 8b5b ldrh r3, [r3, #26] + 801413a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 801413e: 2b00 cmp r3, #0 + 8014140: d014 beq.n 801416c + 8014142: 2301 movs r3, #1 + 8014144: e013 b.n 801416e + 8014146: bf00 nop + 8014148: 0801fc88 .word 0x0801fc88 + 801414c: 0801ffb8 .word 0x0801ffb8 + 8014150: 0801fcd4 .word 0x0801fcd4 + 8014154: 0801ffd4 .word 0x0801ffd4 + 8014158: 2000cf74 .word 0x2000cf74 + 801415c: 2000cf68 .word 0x2000cf68 + 8014160: 2000cf6c .word 0x2000cf6c + 8014164: 2000cf58 .word 0x2000cf58 + 8014168: 2000cf72 .word 0x2000cf72 + 801416c: 2302 movs r3, #2 + 801416e: f887 302d strb.w r3, [r7, #45] ; 0x2d + /* RFC 3465, section 2.2 Slow Start */ + increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss)); + 8014172: f897 302d ldrb.w r3, [r7, #45] ; 0x2d + 8014176: b29a uxth r2, r3 + 8014178: 687b ldr r3, [r7, #4] + 801417a: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801417c: fb12 f303 smulbb r3, r2, r3 + 8014180: b29b uxth r3, r3 + 8014182: 8dfa ldrh r2, [r7, #46] ; 0x2e + 8014184: 4293 cmp r3, r2 + 8014186: bf28 it cs + 8014188: 4613 movcs r3, r2 + 801418a: 857b strh r3, [r7, #42] ; 0x2a + TCP_WND_INC(pcb->cwnd, increase); + 801418c: 687b ldr r3, [r7, #4] + 801418e: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 8014192: 8d7b ldrh r3, [r7, #42] ; 0x2a + 8014194: 4413 add r3, r2 + 8014196: b29a uxth r2, r3 + 8014198: 687b ldr r3, [r7, #4] + 801419a: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 801419e: 429a cmp r2, r3 + 80141a0: d309 bcc.n 80141b6 + 80141a2: 687b ldr r3, [r7, #4] + 80141a4: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 80141a8: 8d7b ldrh r3, [r7, #42] ; 0x2a + 80141aa: 4413 add r3, r2 + 80141ac: b29a uxth r2, r3 + 80141ae: 687b ldr r3, [r7, #4] + 80141b0: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 80141b4: e04e b.n 8014254 + 80141b6: 687b ldr r3, [r7, #4] + 80141b8: f64f 72ff movw r2, #65535 ; 0xffff + 80141bc: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 80141c0: e048 b.n 8014254 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); + } else { + /* RFC 3465, section 2.1 Congestion Avoidance */ + TCP_WND_INC(pcb->bytes_acked, acked); + 80141c2: 687b ldr r3, [r7, #4] + 80141c4: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 80141c8: 8dfb ldrh r3, [r7, #46] ; 0x2e + 80141ca: 4413 add r3, r2 + 80141cc: b29a uxth r2, r3 + 80141ce: 687b ldr r3, [r7, #4] + 80141d0: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a + 80141d4: 429a cmp r2, r3 + 80141d6: d309 bcc.n 80141ec + 80141d8: 687b ldr r3, [r7, #4] + 80141da: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 80141de: 8dfb ldrh r3, [r7, #46] ; 0x2e + 80141e0: 4413 add r3, r2 + 80141e2: b29a uxth r2, r3 + 80141e4: 687b ldr r3, [r7, #4] + 80141e6: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + 80141ea: e004 b.n 80141f6 + 80141ec: 687b ldr r3, [r7, #4] + 80141ee: f64f 72ff movw r2, #65535 ; 0xffff + 80141f2: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + if (pcb->bytes_acked >= pcb->cwnd) { + 80141f6: 687b ldr r3, [r7, #4] + 80141f8: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 80141fc: 687b ldr r3, [r7, #4] + 80141fe: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 8014202: 429a cmp r2, r3 + 8014204: d326 bcc.n 8014254 + pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd); + 8014206: 687b ldr r3, [r7, #4] + 8014208: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 801420c: 687b ldr r3, [r7, #4] + 801420e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 8014212: 1ad3 subs r3, r2, r3 + 8014214: b29a uxth r2, r3 + 8014216: 687b ldr r3, [r7, #4] + 8014218: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + TCP_WND_INC(pcb->cwnd, pcb->mss); + 801421c: 687b ldr r3, [r7, #4] + 801421e: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 8014222: 687b ldr r3, [r7, #4] + 8014224: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8014226: 4413 add r3, r2 + 8014228: b29a uxth r2, r3 + 801422a: 687b ldr r3, [r7, #4] + 801422c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 8014230: 429a cmp r2, r3 + 8014232: d30a bcc.n 801424a + 8014234: 687b ldr r3, [r7, #4] + 8014236: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 801423a: 687b ldr r3, [r7, #4] + 801423c: 8e5b ldrh r3, [r3, #50] ; 0x32 + 801423e: 4413 add r3, r2 + 8014240: b29a uxth r2, r3 + 8014242: 687b ldr r3, [r7, #4] + 8014244: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 8014248: e004 b.n 8014254 + 801424a: 687b ldr r3, [r7, #4] + 801424c: f64f 72ff movw r2, #65535 ; 0xffff + 8014250: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->unacked != NULL ? + lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowledges them. */ + pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent); + 8014254: 687b ldr r3, [r7, #4] + 8014256: 6f19 ldr r1, [r3, #112] ; 0x70 + 8014258: 687b ldr r3, [r7, #4] + 801425a: 6edb ldr r3, [r3, #108] ; 0x6c + 801425c: 4a98 ldr r2, [pc, #608] ; (80144c0 ) + 801425e: 6878 ldr r0, [r7, #4] + 8014260: f7ff fdca bl 8013df8 + 8014264: 4602 mov r2, r0 + 8014266: 687b ldr r3, [r7, #4] + 8014268: 671a str r2, [r3, #112] ; 0x70 + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked); + 801426a: 687b ldr r3, [r7, #4] + 801426c: 6ed9 ldr r1, [r3, #108] ; 0x6c + 801426e: 687b ldr r3, [r7, #4] + 8014270: 6f1b ldr r3, [r3, #112] ; 0x70 + 8014272: 4a94 ldr r2, [pc, #592] ; (80144c4 ) + 8014274: 6878 ldr r0, [r7, #4] + 8014276: f7ff fdbf bl 8013df8 + 801427a: 4602 mov r2, r0 + 801427c: 687b ldr r3, [r7, #4] + 801427e: 66da str r2, [r3, #108] ; 0x6c + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + 8014280: 687b ldr r3, [r7, #4] + 8014282: 6f1b ldr r3, [r3, #112] ; 0x70 + 8014284: 2b00 cmp r3, #0 + 8014286: d104 bne.n 8014292 + pcb->rtime = -1; + 8014288: 687b ldr r3, [r7, #4] + 801428a: f64f 72ff movw r2, #65535 ; 0xffff + 801428e: 861a strh r2, [r3, #48] ; 0x30 + 8014290: e002 b.n 8014298 + } else { + pcb->rtime = 0; + 8014292: 687b ldr r3, [r7, #4] + 8014294: 2200 movs r2, #0 + 8014296: 861a strh r2, [r3, #48] ; 0x30 + } + + pcb->polltmr = 0; + 8014298: 687b ldr r3, [r7, #4] + 801429a: 2200 movs r2, #0 + 801429c: 771a strb r2, [r3, #28] + +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + 801429e: 687b ldr r3, [r7, #4] + 80142a0: 6edb ldr r3, [r3, #108] ; 0x6c + 80142a2: 2b00 cmp r3, #0 + 80142a4: d103 bne.n 80142ae + pcb->unsent_oversize = 0; + 80142a6: 687b ldr r3, [r7, #4] + 80142a8: 2200 movs r2, #0 + 80142aa: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + /* Inform neighbor reachability of forward progress. */ + nd6_reachability_hint(ip6_current_src_addr()); + } +#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ + + pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked); + 80142ae: 687b ldr r3, [r7, #4] + 80142b0: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64 + 80142b4: 4b84 ldr r3, [pc, #528] ; (80144c8 ) + 80142b6: 881b ldrh r3, [r3, #0] + 80142b8: 4413 add r3, r2 + 80142ba: b29a uxth r2, r3 + 80142bc: 687b ldr r3, [r7, #4] + 80142be: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 + /* check if this ACK ends our retransmission of in-flight data */ + if (pcb->flags & TF_RTO) { + 80142c2: 687b ldr r3, [r7, #4] + 80142c4: 8b5b ldrh r3, [r3, #26] + 80142c6: f403 6300 and.w r3, r3, #2048 ; 0x800 + 80142ca: 2b00 cmp r3, #0 + 80142cc: d035 beq.n 801433a + /* RTO is done if + 1) both queues are empty or + 2) unacked is empty and unsent head contains data not part of RTO or + 3) unacked head contains data not part of RTO */ + if (pcb->unacked == NULL) { + 80142ce: 687b ldr r3, [r7, #4] + 80142d0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80142d2: 2b00 cmp r3, #0 + 80142d4: d118 bne.n 8014308 + if ((pcb->unsent == NULL) || + 80142d6: 687b ldr r3, [r7, #4] + 80142d8: 6edb ldr r3, [r3, #108] ; 0x6c + 80142da: 2b00 cmp r3, #0 + 80142dc: d00c beq.n 80142f8 + (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) { + 80142de: 687b ldr r3, [r7, #4] + 80142e0: 6cdc ldr r4, [r3, #76] ; 0x4c + 80142e2: 687b ldr r3, [r7, #4] + 80142e4: 6edb ldr r3, [r3, #108] ; 0x6c + 80142e6: 68db ldr r3, [r3, #12] + 80142e8: 685b ldr r3, [r3, #4] + 80142ea: 4618 mov r0, r3 + 80142ec: f7f9 ffb5 bl 800e25a + 80142f0: 4603 mov r3, r0 + 80142f2: 1ae3 subs r3, r4, r3 + if ((pcb->unsent == NULL) || + 80142f4: 2b00 cmp r3, #0 + 80142f6: dc20 bgt.n 801433a + tcp_clear_flags(pcb, TF_RTO); + 80142f8: 687b ldr r3, [r7, #4] + 80142fa: 8b5b ldrh r3, [r3, #26] + 80142fc: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8014300: b29a uxth r2, r3 + 8014302: 687b ldr r3, [r7, #4] + 8014304: 835a strh r2, [r3, #26] + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 8014306: e018 b.n 801433a + } + } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) { + 8014308: 687b ldr r3, [r7, #4] + 801430a: 6cdc ldr r4, [r3, #76] ; 0x4c + 801430c: 687b ldr r3, [r7, #4] + 801430e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8014310: 68db ldr r3, [r3, #12] + 8014312: 685b ldr r3, [r3, #4] + 8014314: 4618 mov r0, r3 + 8014316: f7f9 ffa0 bl 800e25a + 801431a: 4603 mov r3, r0 + 801431c: 1ae3 subs r3, r4, r3 + 801431e: 2b00 cmp r3, #0 + 8014320: dc0b bgt.n 801433a + tcp_clear_flags(pcb, TF_RTO); + 8014322: 687b ldr r3, [r7, #4] + 8014324: 8b5b ldrh r3, [r3, #26] + 8014326: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 801432a: b29a uxth r2, r3 + 801432c: 687b ldr r3, [r7, #4] + 801432e: 835a strh r2, [r3, #26] + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 8014330: e003 b.n 801433a + } + } + /* End of ACK for new data processing. */ + } else { + /* Out of sequence ACK, didn't really ack anything */ + tcp_send_empty_ack(pcb); + 8014332: 6878 ldr r0, [r7, #4] + 8014334: f001 ff76 bl 8016224 + 8014338: e000 b.n 801433c + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 801433a: bf00 nop + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + 801433c: 687b ldr r3, [r7, #4] + 801433e: 6b5b ldr r3, [r3, #52] ; 0x34 + 8014340: 2b00 cmp r3, #0 + 8014342: d05b beq.n 80143fc + 8014344: 687b ldr r3, [r7, #4] + 8014346: 6b9a ldr r2, [r3, #56] ; 0x38 + 8014348: 4b60 ldr r3, [pc, #384] ; (80144cc ) + 801434a: 681b ldr r3, [r3, #0] + 801434c: 1ad3 subs r3, r2, r3 + 801434e: 2b00 cmp r3, #0 + 8014350: da54 bge.n 80143fc + /* diff between this shouldn't exceed 32K since this are tcp timer ticks + and a round-trip shouldn't be that long... */ + m = (s16_t)(tcp_ticks - pcb->rttest); + 8014352: 4b5f ldr r3, [pc, #380] ; (80144d0 ) + 8014354: 681b ldr r3, [r3, #0] + 8014356: b29a uxth r2, r3 + 8014358: 687b ldr r3, [r7, #4] + 801435a: 6b5b ldr r3, [r3, #52] ; 0x34 + 801435c: b29b uxth r3, r3 + 801435e: 1ad3 subs r3, r2, r3 + 8014360: b29b uxth r3, r3 + 8014362: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, (u16_t)(m * TCP_SLOW_INTERVAL))); + + /* This is taken directly from VJs original code in his paper */ + m = (s16_t)(m - (pcb->sa >> 3)); + 8014366: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e + 801436a: 687b ldr r3, [r7, #4] + 801436c: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 8014370: 10db asrs r3, r3, #3 + 8014372: b21b sxth r3, r3 + 8014374: b29b uxth r3, r3 + 8014376: 1ad3 subs r3, r2, r3 + 8014378: b29b uxth r3, r3 + 801437a: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + pcb->sa = (s16_t)(pcb->sa + m); + 801437e: 687b ldr r3, [r7, #4] + 8014380: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 8014384: b29a uxth r2, r3 + 8014386: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 801438a: 4413 add r3, r2 + 801438c: b29b uxth r3, r3 + 801438e: b21a sxth r2, r3 + 8014390: 687b ldr r3, [r7, #4] + 8014392: 879a strh r2, [r3, #60] ; 0x3c + if (m < 0) { + 8014394: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e + 8014398: 2b00 cmp r3, #0 + 801439a: da05 bge.n 80143a8 + m = (s16_t) - m; + 801439c: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 80143a0: 425b negs r3, r3 + 80143a2: b29b uxth r3, r3 + 80143a4: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + } + m = (s16_t)(m - (pcb->sv >> 2)); + 80143a8: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e + 80143ac: 687b ldr r3, [r7, #4] + 80143ae: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 80143b2: 109b asrs r3, r3, #2 + 80143b4: b21b sxth r3, r3 + 80143b6: b29b uxth r3, r3 + 80143b8: 1ad3 subs r3, r2, r3 + 80143ba: b29b uxth r3, r3 + 80143bc: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + pcb->sv = (s16_t)(pcb->sv + m); + 80143c0: 687b ldr r3, [r7, #4] + 80143c2: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 80143c6: b29a uxth r2, r3 + 80143c8: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 80143cc: 4413 add r3, r2 + 80143ce: b29b uxth r3, r3 + 80143d0: b21a sxth r2, r3 + 80143d2: 687b ldr r3, [r7, #4] + 80143d4: 87da strh r2, [r3, #62] ; 0x3e + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + 80143d6: 687b ldr r3, [r7, #4] + 80143d8: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 80143dc: 10db asrs r3, r3, #3 + 80143de: b21b sxth r3, r3 + 80143e0: b29a uxth r2, r3 + 80143e2: 687b ldr r3, [r7, #4] + 80143e4: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 80143e8: b29b uxth r3, r3 + 80143ea: 4413 add r3, r2 + 80143ec: b29b uxth r3, r3 + 80143ee: b21a sxth r2, r3 + 80143f0: 687b ldr r3, [r7, #4] + 80143f2: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", + pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL))); + + pcb->rttest = 0; + 80143f6: 687b ldr r3, [r7, #4] + 80143f8: 2200 movs r2, #0 + 80143fa: 635a str r2, [r3, #52] ; 0x34 + + /* If the incoming segment contains data, we must process it + further unless the pcb already received a FIN. + (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING, + LAST-ACK and TIME-WAIT: "Ignore the segment text.") */ + if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) { + 80143fc: 4b35 ldr r3, [pc, #212] ; (80144d4 ) + 80143fe: 881b ldrh r3, [r3, #0] + 8014400: 2b00 cmp r3, #0 + 8014402: f000 84e2 beq.w 8014dca + 8014406: 687b ldr r3, [r7, #4] + 8014408: 7d1b ldrb r3, [r3, #20] + 801440a: 2b06 cmp r3, #6 + 801440c: f200 84dd bhi.w 8014dca + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { + 8014410: 687b ldr r3, [r7, #4] + 8014412: 6a5a ldr r2, [r3, #36] ; 0x24 + 8014414: 4b30 ldr r3, [pc, #192] ; (80144d8 ) + 8014416: 681b ldr r3, [r3, #0] + 8014418: 1ad3 subs r3, r2, r3 + 801441a: 3b01 subs r3, #1 + 801441c: 2b00 cmp r3, #0 + 801441e: f2c0 808f blt.w 8014540 + 8014422: 687b ldr r3, [r7, #4] + 8014424: 6a5a ldr r2, [r3, #36] ; 0x24 + 8014426: 4b2b ldr r3, [pc, #172] ; (80144d4 ) + 8014428: 881b ldrh r3, [r3, #0] + 801442a: 4619 mov r1, r3 + 801442c: 4b2a ldr r3, [pc, #168] ; (80144d8 ) + 801442e: 681b ldr r3, [r3, #0] + 8014430: 440b add r3, r1 + 8014432: 1ad3 subs r3, r2, r3 + 8014434: 3301 adds r3, #1 + 8014436: 2b00 cmp r3, #0 + 8014438: f300 8082 bgt.w 8014540 + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + struct pbuf *p = inseg.p; + 801443c: 4b27 ldr r3, [pc, #156] ; (80144dc ) + 801443e: 685b ldr r3, [r3, #4] + 8014440: 647b str r3, [r7, #68] ; 0x44 + u32_t off32 = pcb->rcv_nxt - seqno; + 8014442: 687b ldr r3, [r7, #4] + 8014444: 6a5a ldr r2, [r3, #36] ; 0x24 + 8014446: 4b24 ldr r3, [pc, #144] ; (80144d8 ) + 8014448: 681b ldr r3, [r3, #0] + 801444a: 1ad3 subs r3, r2, r3 + 801444c: 627b str r3, [r7, #36] ; 0x24 + u16_t new_tot_len, off; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + 801444e: 4b23 ldr r3, [pc, #140] ; (80144dc ) + 8014450: 685b ldr r3, [r3, #4] + 8014452: 2b00 cmp r3, #0 + 8014454: d106 bne.n 8014464 + 8014456: 4b22 ldr r3, [pc, #136] ; (80144e0 ) + 8014458: f240 5294 movw r2, #1428 ; 0x594 + 801445c: 4921 ldr r1, [pc, #132] ; (80144e4 ) + 801445e: 4822 ldr r0, [pc, #136] ; (80144e8 ) + 8014460: f007 fdd8 bl 801c014 + LWIP_ASSERT("insane offset!", (off32 < 0xffff)); + 8014464: 6a7b ldr r3, [r7, #36] ; 0x24 + 8014466: f64f 72fe movw r2, #65534 ; 0xfffe + 801446a: 4293 cmp r3, r2 + 801446c: d906 bls.n 801447c + 801446e: 4b1c ldr r3, [pc, #112] ; (80144e0 ) + 8014470: f240 5295 movw r2, #1429 ; 0x595 + 8014474: 491d ldr r1, [pc, #116] ; (80144ec ) + 8014476: 481c ldr r0, [pc, #112] ; (80144e8 ) + 8014478: f007 fdcc bl 801c014 + off = (u16_t)off32; + 801447c: 6a7b ldr r3, [r7, #36] ; 0x24 + 801447e: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); + 8014482: 4b16 ldr r3, [pc, #88] ; (80144dc ) + 8014484: 685b ldr r3, [r3, #4] + 8014486: 891b ldrh r3, [r3, #8] + 8014488: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 801448c: 429a cmp r2, r3 + 801448e: d906 bls.n 801449e + 8014490: 4b13 ldr r3, [pc, #76] ; (80144e0 ) + 8014492: f240 5297 movw r2, #1431 ; 0x597 + 8014496: 4916 ldr r1, [pc, #88] ; (80144f0 ) + 8014498: 4813 ldr r0, [pc, #76] ; (80144e8 ) + 801449a: f007 fdbb bl 801c014 + inseg.len -= off; + 801449e: 4b0f ldr r3, [pc, #60] ; (80144dc ) + 80144a0: 891a ldrh r2, [r3, #8] + 80144a2: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 80144a6: 1ad3 subs r3, r2, r3 + 80144a8: b29a uxth r2, r3 + 80144aa: 4b0c ldr r3, [pc, #48] ; (80144dc ) + 80144ac: 811a strh r2, [r3, #8] + new_tot_len = (u16_t)(inseg.p->tot_len - off); + 80144ae: 4b0b ldr r3, [pc, #44] ; (80144dc ) + 80144b0: 685b ldr r3, [r3, #4] + 80144b2: 891a ldrh r2, [r3, #8] + 80144b4: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 80144b8: 1ad3 subs r3, r2, r3 + 80144ba: 847b strh r3, [r7, #34] ; 0x22 + while (p->len < off) { + 80144bc: e02a b.n 8014514 + 80144be: bf00 nop + 80144c0: 0801fff0 .word 0x0801fff0 + 80144c4: 0801fff8 .word 0x0801fff8 + 80144c8: 2000cf70 .word 0x2000cf70 + 80144cc: 2000cf6c .word 0x2000cf6c + 80144d0: 2000cf30 .word 0x2000cf30 + 80144d4: 2000cf72 .word 0x2000cf72 + 80144d8: 2000cf68 .word 0x2000cf68 + 80144dc: 2000cf48 .word 0x2000cf48 + 80144e0: 0801fc88 .word 0x0801fc88 + 80144e4: 08020000 .word 0x08020000 + 80144e8: 0801fcd4 .word 0x0801fcd4 + 80144ec: 08020010 .word 0x08020010 + 80144f0: 08020020 .word 0x08020020 + off -= p->len; + 80144f4: 6c7b ldr r3, [r7, #68] ; 0x44 + 80144f6: 895b ldrh r3, [r3, #10] + 80144f8: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 80144fc: 1ad3 subs r3, r2, r3 + 80144fe: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + /* all pbufs up to and including this one have len==0, so tot_len is equal */ + p->tot_len = new_tot_len; + 8014502: 6c7b ldr r3, [r7, #68] ; 0x44 + 8014504: 8c7a ldrh r2, [r7, #34] ; 0x22 + 8014506: 811a strh r2, [r3, #8] + p->len = 0; + 8014508: 6c7b ldr r3, [r7, #68] ; 0x44 + 801450a: 2200 movs r2, #0 + 801450c: 815a strh r2, [r3, #10] + p = p->next; + 801450e: 6c7b ldr r3, [r7, #68] ; 0x44 + 8014510: 681b ldr r3, [r3, #0] + 8014512: 647b str r3, [r7, #68] ; 0x44 + while (p->len < off) { + 8014514: 6c7b ldr r3, [r7, #68] ; 0x44 + 8014516: 895b ldrh r3, [r3, #10] + 8014518: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 801451c: 429a cmp r2, r3 + 801451e: d8e9 bhi.n 80144f4 + } + /* cannot fail... */ + pbuf_remove_header(p, off); + 8014520: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 8014524: 4619 mov r1, r3 + 8014526: 6c78 ldr r0, [r7, #68] ; 0x44 + 8014528: f7fc f9e4 bl 80108f4 + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + 801452c: 687b ldr r3, [r7, #4] + 801452e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014530: 4a91 ldr r2, [pc, #580] ; (8014778 ) + 8014532: 6013 str r3, [r2, #0] + 8014534: 4b91 ldr r3, [pc, #580] ; (801477c ) + 8014536: 68db ldr r3, [r3, #12] + 8014538: 4a8f ldr r2, [pc, #572] ; (8014778 ) + 801453a: 6812 ldr r2, [r2, #0] + 801453c: 605a str r2, [r3, #4] + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { + 801453e: e00d b.n 801455c + } else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + 8014540: 4b8d ldr r3, [pc, #564] ; (8014778 ) + 8014542: 681a ldr r2, [r3, #0] + 8014544: 687b ldr r3, [r7, #4] + 8014546: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014548: 1ad3 subs r3, r2, r3 + 801454a: 2b00 cmp r3, #0 + 801454c: da06 bge.n 801455c + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + 801454e: 687b ldr r3, [r7, #4] + 8014550: 8b5b ldrh r3, [r3, #26] + 8014552: f043 0302 orr.w r3, r3, #2 + 8014556: b29a uxth r2, r3 + 8014558: 687b ldr r3, [r7, #4] + 801455a: 835a strh r2, [r3, #26] + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 801455c: 4b86 ldr r3, [pc, #536] ; (8014778 ) + 801455e: 681a ldr r2, [r3, #0] + 8014560: 687b ldr r3, [r7, #4] + 8014562: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014564: 1ad3 subs r3, r2, r3 + 8014566: 2b00 cmp r3, #0 + 8014568: f2c0 842a blt.w 8014dc0 + 801456c: 4b82 ldr r3, [pc, #520] ; (8014778 ) + 801456e: 681a ldr r2, [r3, #0] + 8014570: 687b ldr r3, [r7, #4] + 8014572: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014574: 6879 ldr r1, [r7, #4] + 8014576: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8014578: 440b add r3, r1 + 801457a: 1ad3 subs r3, r2, r3 + 801457c: 3301 adds r3, #1 + 801457e: 2b00 cmp r3, #0 + 8014580: f300 841e bgt.w 8014dc0 + pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + if (pcb->rcv_nxt == seqno) { + 8014584: 687b ldr r3, [r7, #4] + 8014586: 6a5a ldr r2, [r3, #36] ; 0x24 + 8014588: 4b7b ldr r3, [pc, #492] ; (8014778 ) + 801458a: 681b ldr r3, [r3, #0] + 801458c: 429a cmp r2, r3 + 801458e: f040 829a bne.w 8014ac6 + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + tcplen = TCP_TCPLEN(&inseg); + 8014592: 4b7a ldr r3, [pc, #488] ; (801477c ) + 8014594: 891c ldrh r4, [r3, #8] + 8014596: 4b79 ldr r3, [pc, #484] ; (801477c ) + 8014598: 68db ldr r3, [r3, #12] + 801459a: 899b ldrh r3, [r3, #12] + 801459c: b29b uxth r3, r3 + 801459e: 4618 mov r0, r3 + 80145a0: f7f9 fe46 bl 800e230 + 80145a4: 4603 mov r3, r0 + 80145a6: b2db uxtb r3, r3 + 80145a8: f003 0303 and.w r3, r3, #3 + 80145ac: 2b00 cmp r3, #0 + 80145ae: d001 beq.n 80145b4 + 80145b0: 2301 movs r3, #1 + 80145b2: e000 b.n 80145b6 + 80145b4: 2300 movs r3, #0 + 80145b6: 4423 add r3, r4 + 80145b8: b29a uxth r2, r3 + 80145ba: 4b71 ldr r3, [pc, #452] ; (8014780 ) + 80145bc: 801a strh r2, [r3, #0] + + if (tcplen > pcb->rcv_wnd) { + 80145be: 687b ldr r3, [r7, #4] + 80145c0: 8d1a ldrh r2, [r3, #40] ; 0x28 + 80145c2: 4b6f ldr r3, [pc, #444] ; (8014780 ) + 80145c4: 881b ldrh r3, [r3, #0] + 80145c6: 429a cmp r2, r3 + 80145c8: d275 bcs.n 80146b6 + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 80145ca: 4b6c ldr r3, [pc, #432] ; (801477c ) + 80145cc: 68db ldr r3, [r3, #12] + 80145ce: 899b ldrh r3, [r3, #12] + 80145d0: b29b uxth r3, r3 + 80145d2: 4618 mov r0, r3 + 80145d4: f7f9 fe2c bl 800e230 + 80145d8: 4603 mov r3, r0 + 80145da: b2db uxtb r3, r3 + 80145dc: f003 0301 and.w r3, r3, #1 + 80145e0: 2b00 cmp r3, #0 + 80145e2: d01f beq.n 8014624 + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN); + 80145e4: 4b65 ldr r3, [pc, #404] ; (801477c ) + 80145e6: 68db ldr r3, [r3, #12] + 80145e8: 899b ldrh r3, [r3, #12] + 80145ea: b29b uxth r3, r3 + 80145ec: b21b sxth r3, r3 + 80145ee: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 80145f2: b21c sxth r4, r3 + 80145f4: 4b61 ldr r3, [pc, #388] ; (801477c ) + 80145f6: 68db ldr r3, [r3, #12] + 80145f8: 899b ldrh r3, [r3, #12] + 80145fa: b29b uxth r3, r3 + 80145fc: 4618 mov r0, r3 + 80145fe: f7f9 fe17 bl 800e230 + 8014602: 4603 mov r3, r0 + 8014604: b2db uxtb r3, r3 + 8014606: b29b uxth r3, r3 + 8014608: f003 033e and.w r3, r3, #62 ; 0x3e + 801460c: b29b uxth r3, r3 + 801460e: 4618 mov r0, r3 + 8014610: f7f9 fe0e bl 800e230 + 8014614: 4603 mov r3, r0 + 8014616: b21b sxth r3, r3 + 8014618: 4323 orrs r3, r4 + 801461a: b21a sxth r2, r3 + 801461c: 4b57 ldr r3, [pc, #348] ; (801477c ) + 801461e: 68db ldr r3, [r3, #12] + 8014620: b292 uxth r2, r2 + 8014622: 819a strh r2, [r3, #12] + } + /* Adjust length of segment to fit in the window. */ + TCPWND_CHECK16(pcb->rcv_wnd); + inseg.len = (u16_t)pcb->rcv_wnd; + 8014624: 687b ldr r3, [r7, #4] + 8014626: 8d1a ldrh r2, [r3, #40] ; 0x28 + 8014628: 4b54 ldr r3, [pc, #336] ; (801477c ) + 801462a: 811a strh r2, [r3, #8] + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + 801462c: 4b53 ldr r3, [pc, #332] ; (801477c ) + 801462e: 68db ldr r3, [r3, #12] + 8014630: 899b ldrh r3, [r3, #12] + 8014632: b29b uxth r3, r3 + 8014634: 4618 mov r0, r3 + 8014636: f7f9 fdfb bl 800e230 + 801463a: 4603 mov r3, r0 + 801463c: b2db uxtb r3, r3 + 801463e: f003 0302 and.w r3, r3, #2 + 8014642: 2b00 cmp r3, #0 + 8014644: d005 beq.n 8014652 + inseg.len -= 1; + 8014646: 4b4d ldr r3, [pc, #308] ; (801477c ) + 8014648: 891b ldrh r3, [r3, #8] + 801464a: 3b01 subs r3, #1 + 801464c: b29a uxth r2, r3 + 801464e: 4b4b ldr r3, [pc, #300] ; (801477c ) + 8014650: 811a strh r2, [r3, #8] + } + pbuf_realloc(inseg.p, inseg.len); + 8014652: 4b4a ldr r3, [pc, #296] ; (801477c ) + 8014654: 685b ldr r3, [r3, #4] + 8014656: 4a49 ldr r2, [pc, #292] ; (801477c ) + 8014658: 8912 ldrh r2, [r2, #8] + 801465a: 4611 mov r1, r2 + 801465c: 4618 mov r0, r3 + 801465e: f7fc f849 bl 80106f4 + tcplen = TCP_TCPLEN(&inseg); + 8014662: 4b46 ldr r3, [pc, #280] ; (801477c ) + 8014664: 891c ldrh r4, [r3, #8] + 8014666: 4b45 ldr r3, [pc, #276] ; (801477c ) + 8014668: 68db ldr r3, [r3, #12] + 801466a: 899b ldrh r3, [r3, #12] + 801466c: b29b uxth r3, r3 + 801466e: 4618 mov r0, r3 + 8014670: f7f9 fdde bl 800e230 + 8014674: 4603 mov r3, r0 + 8014676: b2db uxtb r3, r3 + 8014678: f003 0303 and.w r3, r3, #3 + 801467c: 2b00 cmp r3, #0 + 801467e: d001 beq.n 8014684 + 8014680: 2301 movs r3, #1 + 8014682: e000 b.n 8014686 + 8014684: 2300 movs r3, #0 + 8014686: 4423 add r3, r4 + 8014688: b29a uxth r2, r3 + 801468a: 4b3d ldr r3, [pc, #244] ; (8014780 ) + 801468c: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + 801468e: 4b3c ldr r3, [pc, #240] ; (8014780 ) + 8014690: 881b ldrh r3, [r3, #0] + 8014692: 461a mov r2, r3 + 8014694: 4b38 ldr r3, [pc, #224] ; (8014778 ) + 8014696: 681b ldr r3, [r3, #0] + 8014698: 441a add r2, r3 + 801469a: 687b ldr r3, [r7, #4] + 801469c: 6a5b ldr r3, [r3, #36] ; 0x24 + 801469e: 6879 ldr r1, [r7, #4] + 80146a0: 8d09 ldrh r1, [r1, #40] ; 0x28 + 80146a2: 440b add r3, r1 + 80146a4: 429a cmp r2, r3 + 80146a6: d006 beq.n 80146b6 + 80146a8: 4b36 ldr r3, [pc, #216] ; (8014784 ) + 80146aa: f240 52cb movw r2, #1483 ; 0x5cb + 80146ae: 4936 ldr r1, [pc, #216] ; (8014788 ) + 80146b0: 4836 ldr r0, [pc, #216] ; (801478c ) + 80146b2: f007 fcaf bl 801c014 + } +#if TCP_QUEUE_OOSEQ + /* Received in-sequence data, adjust ooseq data if: + - FIN has been received or + - inseq overlaps with ooseq */ + if (pcb->ooseq != NULL) { + 80146b6: 687b ldr r3, [r7, #4] + 80146b8: 6f5b ldr r3, [r3, #116] ; 0x74 + 80146ba: 2b00 cmp r3, #0 + 80146bc: f000 80e7 beq.w 801488e + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 80146c0: 4b2e ldr r3, [pc, #184] ; (801477c ) + 80146c2: 68db ldr r3, [r3, #12] + 80146c4: 899b ldrh r3, [r3, #12] + 80146c6: b29b uxth r3, r3 + 80146c8: 4618 mov r0, r3 + 80146ca: f7f9 fdb1 bl 800e230 + 80146ce: 4603 mov r3, r0 + 80146d0: b2db uxtb r3, r3 + 80146d2: f003 0301 and.w r3, r3, #1 + 80146d6: 2b00 cmp r3, #0 + 80146d8: d010 beq.n 80146fc + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: received in-order FIN, binning ooseq queue\n")); + /* Received in-order FIN means anything that was received + * out of order must now have been received in-order, so + * bin the ooseq queue */ + while (pcb->ooseq != NULL) { + 80146da: e00a b.n 80146f2 + struct tcp_seg *old_ooseq = pcb->ooseq; + 80146dc: 687b ldr r3, [r7, #4] + 80146de: 6f5b ldr r3, [r3, #116] ; 0x74 + 80146e0: 60fb str r3, [r7, #12] + pcb->ooseq = pcb->ooseq->next; + 80146e2: 687b ldr r3, [r7, #4] + 80146e4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80146e6: 681a ldr r2, [r3, #0] + 80146e8: 687b ldr r3, [r7, #4] + 80146ea: 675a str r2, [r3, #116] ; 0x74 + tcp_seg_free(old_ooseq); + 80146ec: 68f8 ldr r0, [r7, #12] + 80146ee: f7fd fd92 bl 8012216 + while (pcb->ooseq != NULL) { + 80146f2: 687b ldr r3, [r7, #4] + 80146f4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80146f6: 2b00 cmp r3, #0 + 80146f8: d1f0 bne.n 80146dc + 80146fa: e0c8 b.n 801488e + } + } else { + struct tcp_seg *next = pcb->ooseq; + 80146fc: 687b ldr r3, [r7, #4] + 80146fe: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014700: 63fb str r3, [r7, #60] ; 0x3c + /* Remove all segments on ooseq that are covered by inseg already. + * FIN is copied from ooseq to inseg if present. */ + while (next && + 8014702: e052 b.n 80147aa + TCP_SEQ_GEQ(seqno + tcplen, + next->tcphdr->seqno + next->len)) { + struct tcp_seg *tmp; + /* inseg cannot have FIN here (already processed above) */ + if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && + 8014704: 6bfb ldr r3, [r7, #60] ; 0x3c + 8014706: 68db ldr r3, [r3, #12] + 8014708: 899b ldrh r3, [r3, #12] + 801470a: b29b uxth r3, r3 + 801470c: 4618 mov r0, r3 + 801470e: f7f9 fd8f bl 800e230 + 8014712: 4603 mov r3, r0 + 8014714: b2db uxtb r3, r3 + 8014716: f003 0301 and.w r3, r3, #1 + 801471a: 2b00 cmp r3, #0 + 801471c: d03d beq.n 801479a + (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { + 801471e: 4b17 ldr r3, [pc, #92] ; (801477c ) + 8014720: 68db ldr r3, [r3, #12] + 8014722: 899b ldrh r3, [r3, #12] + 8014724: b29b uxth r3, r3 + 8014726: 4618 mov r0, r3 + 8014728: f7f9 fd82 bl 800e230 + 801472c: 4603 mov r3, r0 + 801472e: b2db uxtb r3, r3 + 8014730: f003 0302 and.w r3, r3, #2 + if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && + 8014734: 2b00 cmp r3, #0 + 8014736: d130 bne.n 801479a + TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); + 8014738: 4b10 ldr r3, [pc, #64] ; (801477c ) + 801473a: 68db ldr r3, [r3, #12] + 801473c: 899b ldrh r3, [r3, #12] + 801473e: b29c uxth r4, r3 + 8014740: 2001 movs r0, #1 + 8014742: f7f9 fd75 bl 800e230 + 8014746: 4603 mov r3, r0 + 8014748: 461a mov r2, r3 + 801474a: 4b0c ldr r3, [pc, #48] ; (801477c ) + 801474c: 68db ldr r3, [r3, #12] + 801474e: 4322 orrs r2, r4 + 8014750: b292 uxth r2, r2 + 8014752: 819a strh r2, [r3, #12] + tcplen = TCP_TCPLEN(&inseg); + 8014754: 4b09 ldr r3, [pc, #36] ; (801477c ) + 8014756: 891c ldrh r4, [r3, #8] + 8014758: 4b08 ldr r3, [pc, #32] ; (801477c ) + 801475a: 68db ldr r3, [r3, #12] + 801475c: 899b ldrh r3, [r3, #12] + 801475e: b29b uxth r3, r3 + 8014760: 4618 mov r0, r3 + 8014762: f7f9 fd65 bl 800e230 + 8014766: 4603 mov r3, r0 + 8014768: b2db uxtb r3, r3 + 801476a: f003 0303 and.w r3, r3, #3 + 801476e: 2b00 cmp r3, #0 + 8014770: d00e beq.n 8014790 + 8014772: 2301 movs r3, #1 + 8014774: e00d b.n 8014792 + 8014776: bf00 nop + 8014778: 2000cf68 .word 0x2000cf68 + 801477c: 2000cf48 .word 0x2000cf48 + 8014780: 2000cf72 .word 0x2000cf72 + 8014784: 0801fc88 .word 0x0801fc88 + 8014788: 08020030 .word 0x08020030 + 801478c: 0801fcd4 .word 0x0801fcd4 + 8014790: 2300 movs r3, #0 + 8014792: 4423 add r3, r4 + 8014794: b29a uxth r2, r3 + 8014796: 4b98 ldr r3, [pc, #608] ; (80149f8 ) + 8014798: 801a strh r2, [r3, #0] + } + tmp = next; + 801479a: 6bfb ldr r3, [r7, #60] ; 0x3c + 801479c: 613b str r3, [r7, #16] + next = next->next; + 801479e: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147a0: 681b ldr r3, [r3, #0] + 80147a2: 63fb str r3, [r7, #60] ; 0x3c + tcp_seg_free(tmp); + 80147a4: 6938 ldr r0, [r7, #16] + 80147a6: f7fd fd36 bl 8012216 + while (next && + 80147aa: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147ac: 2b00 cmp r3, #0 + 80147ae: d00e beq.n 80147ce + TCP_SEQ_GEQ(seqno + tcplen, + 80147b0: 4b91 ldr r3, [pc, #580] ; (80149f8 ) + 80147b2: 881b ldrh r3, [r3, #0] + 80147b4: 461a mov r2, r3 + 80147b6: 4b91 ldr r3, [pc, #580] ; (80149fc ) + 80147b8: 681b ldr r3, [r3, #0] + 80147ba: 441a add r2, r3 + 80147bc: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147be: 68db ldr r3, [r3, #12] + 80147c0: 685b ldr r3, [r3, #4] + 80147c2: 6bf9 ldr r1, [r7, #60] ; 0x3c + 80147c4: 8909 ldrh r1, [r1, #8] + 80147c6: 440b add r3, r1 + 80147c8: 1ad3 subs r3, r2, r3 + while (next && + 80147ca: 2b00 cmp r3, #0 + 80147cc: da9a bge.n 8014704 + } + /* Now trim right side of inseg if it overlaps with the first + * segment on ooseq */ + if (next && + 80147ce: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147d0: 2b00 cmp r3, #0 + 80147d2: d059 beq.n 8014888 + TCP_SEQ_GT(seqno + tcplen, + 80147d4: 4b88 ldr r3, [pc, #544] ; (80149f8 ) + 80147d6: 881b ldrh r3, [r3, #0] + 80147d8: 461a mov r2, r3 + 80147da: 4b88 ldr r3, [pc, #544] ; (80149fc ) + 80147dc: 681b ldr r3, [r3, #0] + 80147de: 441a add r2, r3 + 80147e0: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147e2: 68db ldr r3, [r3, #12] + 80147e4: 685b ldr r3, [r3, #4] + 80147e6: 1ad3 subs r3, r2, r3 + if (next && + 80147e8: 2b00 cmp r3, #0 + 80147ea: dd4d ble.n 8014888 + next->tcphdr->seqno)) { + /* inseg cannot have FIN here (already processed above) */ + inseg.len = (u16_t)(next->tcphdr->seqno - seqno); + 80147ec: 6bfb ldr r3, [r7, #60] ; 0x3c + 80147ee: 68db ldr r3, [r3, #12] + 80147f0: 685b ldr r3, [r3, #4] + 80147f2: b29a uxth r2, r3 + 80147f4: 4b81 ldr r3, [pc, #516] ; (80149fc ) + 80147f6: 681b ldr r3, [r3, #0] + 80147f8: b29b uxth r3, r3 + 80147fa: 1ad3 subs r3, r2, r3 + 80147fc: b29a uxth r2, r3 + 80147fe: 4b80 ldr r3, [pc, #512] ; (8014a00 ) + 8014800: 811a strh r2, [r3, #8] + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + 8014802: 4b7f ldr r3, [pc, #508] ; (8014a00 ) + 8014804: 68db ldr r3, [r3, #12] + 8014806: 899b ldrh r3, [r3, #12] + 8014808: b29b uxth r3, r3 + 801480a: 4618 mov r0, r3 + 801480c: f7f9 fd10 bl 800e230 + 8014810: 4603 mov r3, r0 + 8014812: b2db uxtb r3, r3 + 8014814: f003 0302 and.w r3, r3, #2 + 8014818: 2b00 cmp r3, #0 + 801481a: d005 beq.n 8014828 + inseg.len -= 1; + 801481c: 4b78 ldr r3, [pc, #480] ; (8014a00 ) + 801481e: 891b ldrh r3, [r3, #8] + 8014820: 3b01 subs r3, #1 + 8014822: b29a uxth r2, r3 + 8014824: 4b76 ldr r3, [pc, #472] ; (8014a00 ) + 8014826: 811a strh r2, [r3, #8] + } + pbuf_realloc(inseg.p, inseg.len); + 8014828: 4b75 ldr r3, [pc, #468] ; (8014a00 ) + 801482a: 685b ldr r3, [r3, #4] + 801482c: 4a74 ldr r2, [pc, #464] ; (8014a00 ) + 801482e: 8912 ldrh r2, [r2, #8] + 8014830: 4611 mov r1, r2 + 8014832: 4618 mov r0, r3 + 8014834: f7fb ff5e bl 80106f4 + tcplen = TCP_TCPLEN(&inseg); + 8014838: 4b71 ldr r3, [pc, #452] ; (8014a00 ) + 801483a: 891c ldrh r4, [r3, #8] + 801483c: 4b70 ldr r3, [pc, #448] ; (8014a00 ) + 801483e: 68db ldr r3, [r3, #12] + 8014840: 899b ldrh r3, [r3, #12] + 8014842: b29b uxth r3, r3 + 8014844: 4618 mov r0, r3 + 8014846: f7f9 fcf3 bl 800e230 + 801484a: 4603 mov r3, r0 + 801484c: b2db uxtb r3, r3 + 801484e: f003 0303 and.w r3, r3, #3 + 8014852: 2b00 cmp r3, #0 + 8014854: d001 beq.n 801485a + 8014856: 2301 movs r3, #1 + 8014858: e000 b.n 801485c + 801485a: 2300 movs r3, #0 + 801485c: 4423 add r3, r4 + 801485e: b29a uxth r2, r3 + 8014860: 4b65 ldr r3, [pc, #404] ; (80149f8 ) + 8014862: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", + 8014864: 4b64 ldr r3, [pc, #400] ; (80149f8 ) + 8014866: 881b ldrh r3, [r3, #0] + 8014868: 461a mov r2, r3 + 801486a: 4b64 ldr r3, [pc, #400] ; (80149fc ) + 801486c: 681b ldr r3, [r3, #0] + 801486e: 441a add r2, r3 + 8014870: 6bfb ldr r3, [r7, #60] ; 0x3c + 8014872: 68db ldr r3, [r3, #12] + 8014874: 685b ldr r3, [r3, #4] + 8014876: 429a cmp r2, r3 + 8014878: d006 beq.n 8014888 + 801487a: 4b62 ldr r3, [pc, #392] ; (8014a04 ) + 801487c: f240 52fc movw r2, #1532 ; 0x5fc + 8014880: 4961 ldr r1, [pc, #388] ; (8014a08 ) + 8014882: 4862 ldr r0, [pc, #392] ; (8014a0c ) + 8014884: f007 fbc6 bl 801c014 + (seqno + tcplen) == next->tcphdr->seqno); + } + pcb->ooseq = next; + 8014888: 687b ldr r3, [r7, #4] + 801488a: 6bfa ldr r2, [r7, #60] ; 0x3c + 801488c: 675a str r2, [r3, #116] ; 0x74 + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + pcb->rcv_nxt = seqno + tcplen; + 801488e: 4b5a ldr r3, [pc, #360] ; (80149f8 ) + 8014890: 881b ldrh r3, [r3, #0] + 8014892: 461a mov r2, r3 + 8014894: 4b59 ldr r3, [pc, #356] ; (80149fc ) + 8014896: 681b ldr r3, [r3, #0] + 8014898: 441a add r2, r3 + 801489a: 687b ldr r3, [r7, #4] + 801489c: 625a str r2, [r3, #36] ; 0x24 + + /* Update the receiver's (our) window. */ + LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); + 801489e: 687b ldr r3, [r7, #4] + 80148a0: 8d1a ldrh r2, [r3, #40] ; 0x28 + 80148a2: 4b55 ldr r3, [pc, #340] ; (80149f8 ) + 80148a4: 881b ldrh r3, [r3, #0] + 80148a6: 429a cmp r2, r3 + 80148a8: d206 bcs.n 80148b8 + 80148aa: 4b56 ldr r3, [pc, #344] ; (8014a04 ) + 80148ac: f240 6207 movw r2, #1543 ; 0x607 + 80148b0: 4957 ldr r1, [pc, #348] ; (8014a10 ) + 80148b2: 4856 ldr r0, [pc, #344] ; (8014a0c ) + 80148b4: f007 fbae bl 801c014 + pcb->rcv_wnd -= tcplen; + 80148b8: 687b ldr r3, [r7, #4] + 80148ba: 8d1a ldrh r2, [r3, #40] ; 0x28 + 80148bc: 4b4e ldr r3, [pc, #312] ; (80149f8 ) + 80148be: 881b ldrh r3, [r3, #0] + 80148c0: 1ad3 subs r3, r2, r3 + 80148c2: b29a uxth r2, r3 + 80148c4: 687b ldr r3, [r7, #4] + 80148c6: 851a strh r2, [r3, #40] ; 0x28 + + tcp_update_rcv_ann_wnd(pcb); + 80148c8: 6878 ldr r0, [r7, #4] + 80148ca: f7fc ffc5 bl 8011858 + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + 80148ce: 4b4c ldr r3, [pc, #304] ; (8014a00 ) + 80148d0: 685b ldr r3, [r3, #4] + 80148d2: 891b ldrh r3, [r3, #8] + 80148d4: 2b00 cmp r3, #0 + 80148d6: d006 beq.n 80148e6 + recv_data = inseg.p; + 80148d8: 4b49 ldr r3, [pc, #292] ; (8014a00 ) + 80148da: 685b ldr r3, [r3, #4] + 80148dc: 4a4d ldr r2, [pc, #308] ; (8014a14 ) + 80148de: 6013 str r3, [r2, #0] + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + 80148e0: 4b47 ldr r3, [pc, #284] ; (8014a00 ) + 80148e2: 2200 movs r2, #0 + 80148e4: 605a str r2, [r3, #4] + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 80148e6: 4b46 ldr r3, [pc, #280] ; (8014a00 ) + 80148e8: 68db ldr r3, [r3, #12] + 80148ea: 899b ldrh r3, [r3, #12] + 80148ec: b29b uxth r3, r3 + 80148ee: 4618 mov r0, r3 + 80148f0: f7f9 fc9e bl 800e230 + 80148f4: 4603 mov r3, r0 + 80148f6: b2db uxtb r3, r3 + 80148f8: f003 0301 and.w r3, r3, #1 + 80148fc: 2b00 cmp r3, #0 + 80148fe: f000 80b8 beq.w 8014a72 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags |= TF_GOT_FIN; + 8014902: 4b45 ldr r3, [pc, #276] ; (8014a18 ) + 8014904: 781b ldrb r3, [r3, #0] + 8014906: f043 0320 orr.w r3, r3, #32 + 801490a: b2da uxtb r2, r3 + 801490c: 4b42 ldr r3, [pc, #264] ; (8014a18 ) + 801490e: 701a strb r2, [r3, #0] + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + are now in sequence. */ + while (pcb->ooseq != NULL && + 8014910: e0af b.n 8014a72 + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + struct tcp_seg *cseg = pcb->ooseq; + 8014912: 687b ldr r3, [r7, #4] + 8014914: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014916: 60bb str r3, [r7, #8] + seqno = pcb->ooseq->tcphdr->seqno; + 8014918: 687b ldr r3, [r7, #4] + 801491a: 6f5b ldr r3, [r3, #116] ; 0x74 + 801491c: 68db ldr r3, [r3, #12] + 801491e: 685b ldr r3, [r3, #4] + 8014920: 4a36 ldr r2, [pc, #216] ; (80149fc ) + 8014922: 6013 str r3, [r2, #0] + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + 8014924: 68bb ldr r3, [r7, #8] + 8014926: 891b ldrh r3, [r3, #8] + 8014928: 461c mov r4, r3 + 801492a: 68bb ldr r3, [r7, #8] + 801492c: 68db ldr r3, [r3, #12] + 801492e: 899b ldrh r3, [r3, #12] + 8014930: b29b uxth r3, r3 + 8014932: 4618 mov r0, r3 + 8014934: f7f9 fc7c bl 800e230 + 8014938: 4603 mov r3, r0 + 801493a: b2db uxtb r3, r3 + 801493c: f003 0303 and.w r3, r3, #3 + 8014940: 2b00 cmp r3, #0 + 8014942: d001 beq.n 8014948 + 8014944: 2301 movs r3, #1 + 8014946: e000 b.n 801494a + 8014948: 2300 movs r3, #0 + 801494a: 191a adds r2, r3, r4 + 801494c: 687b ldr r3, [r7, #4] + 801494e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014950: 441a add r2, r3 + 8014952: 687b ldr r3, [r7, #4] + 8014954: 625a str r2, [r3, #36] ; 0x24 + LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", + 8014956: 687b ldr r3, [r7, #4] + 8014958: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801495a: 461c mov r4, r3 + 801495c: 68bb ldr r3, [r7, #8] + 801495e: 891b ldrh r3, [r3, #8] + 8014960: 461d mov r5, r3 + 8014962: 68bb ldr r3, [r7, #8] + 8014964: 68db ldr r3, [r3, #12] + 8014966: 899b ldrh r3, [r3, #12] + 8014968: b29b uxth r3, r3 + 801496a: 4618 mov r0, r3 + 801496c: f7f9 fc60 bl 800e230 + 8014970: 4603 mov r3, r0 + 8014972: b2db uxtb r3, r3 + 8014974: f003 0303 and.w r3, r3, #3 + 8014978: 2b00 cmp r3, #0 + 801497a: d001 beq.n 8014980 + 801497c: 2301 movs r3, #1 + 801497e: e000 b.n 8014982 + 8014980: 2300 movs r3, #0 + 8014982: 442b add r3, r5 + 8014984: 429c cmp r4, r3 + 8014986: d206 bcs.n 8014996 + 8014988: 4b1e ldr r3, [pc, #120] ; (8014a04 ) + 801498a: f240 622b movw r2, #1579 ; 0x62b + 801498e: 4923 ldr r1, [pc, #140] ; (8014a1c ) + 8014990: 481e ldr r0, [pc, #120] ; (8014a0c ) + 8014992: f007 fb3f bl 801c014 + pcb->rcv_wnd >= TCP_TCPLEN(cseg)); + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + 8014996: 68bb ldr r3, [r7, #8] + 8014998: 891b ldrh r3, [r3, #8] + 801499a: 461c mov r4, r3 + 801499c: 68bb ldr r3, [r7, #8] + 801499e: 68db ldr r3, [r3, #12] + 80149a0: 899b ldrh r3, [r3, #12] + 80149a2: b29b uxth r3, r3 + 80149a4: 4618 mov r0, r3 + 80149a6: f7f9 fc43 bl 800e230 + 80149aa: 4603 mov r3, r0 + 80149ac: b2db uxtb r3, r3 + 80149ae: f003 0303 and.w r3, r3, #3 + 80149b2: 2b00 cmp r3, #0 + 80149b4: d001 beq.n 80149ba + 80149b6: 2301 movs r3, #1 + 80149b8: e000 b.n 80149bc + 80149ba: 2300 movs r3, #0 + 80149bc: 1919 adds r1, r3, r4 + 80149be: 687b ldr r3, [r7, #4] + 80149c0: 8d1a ldrh r2, [r3, #40] ; 0x28 + 80149c2: b28b uxth r3, r1 + 80149c4: 1ad3 subs r3, r2, r3 + 80149c6: b29a uxth r2, r3 + 80149c8: 687b ldr r3, [r7, #4] + 80149ca: 851a strh r2, [r3, #40] ; 0x28 + + tcp_update_rcv_ann_wnd(pcb); + 80149cc: 6878 ldr r0, [r7, #4] + 80149ce: f7fc ff43 bl 8011858 + + if (cseg->p->tot_len > 0) { + 80149d2: 68bb ldr r3, [r7, #8] + 80149d4: 685b ldr r3, [r3, #4] + 80149d6: 891b ldrh r3, [r3, #8] + 80149d8: 2b00 cmp r3, #0 + 80149da: d028 beq.n 8014a2e + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + /* With window scaling, this can overflow recv_data->tot_len, but + that's not a problem since we explicitly fix that before passing + recv_data to the application. */ + if (recv_data) { + 80149dc: 4b0d ldr r3, [pc, #52] ; (8014a14 ) + 80149de: 681b ldr r3, [r3, #0] + 80149e0: 2b00 cmp r3, #0 + 80149e2: d01d beq.n 8014a20 + pbuf_cat(recv_data, cseg->p); + 80149e4: 4b0b ldr r3, [pc, #44] ; (8014a14 ) + 80149e6: 681a ldr r2, [r3, #0] + 80149e8: 68bb ldr r3, [r7, #8] + 80149ea: 685b ldr r3, [r3, #4] + 80149ec: 4619 mov r1, r3 + 80149ee: 4610 mov r0, r2 + 80149f0: f7fc f8d4 bl 8010b9c + 80149f4: e018 b.n 8014a28 + 80149f6: bf00 nop + 80149f8: 2000cf72 .word 0x2000cf72 + 80149fc: 2000cf68 .word 0x2000cf68 + 8014a00: 2000cf48 .word 0x2000cf48 + 8014a04: 0801fc88 .word 0x0801fc88 + 8014a08: 08020068 .word 0x08020068 + 8014a0c: 0801fcd4 .word 0x0801fcd4 + 8014a10: 080200a4 .word 0x080200a4 + 8014a14: 2000cf78 .word 0x2000cf78 + 8014a18: 2000cf75 .word 0x2000cf75 + 8014a1c: 080200c4 .word 0x080200c4 + } else { + recv_data = cseg->p; + 8014a20: 68bb ldr r3, [r7, #8] + 8014a22: 685b ldr r3, [r3, #4] + 8014a24: 4a70 ldr r2, [pc, #448] ; (8014be8 ) + 8014a26: 6013 str r3, [r2, #0] + } + cseg->p = NULL; + 8014a28: 68bb ldr r3, [r7, #8] + 8014a2a: 2200 movs r2, #0 + 8014a2c: 605a str r2, [r3, #4] + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + 8014a2e: 68bb ldr r3, [r7, #8] + 8014a30: 68db ldr r3, [r3, #12] + 8014a32: 899b ldrh r3, [r3, #12] + 8014a34: b29b uxth r3, r3 + 8014a36: 4618 mov r0, r3 + 8014a38: f7f9 fbfa bl 800e230 + 8014a3c: 4603 mov r3, r0 + 8014a3e: b2db uxtb r3, r3 + 8014a40: f003 0301 and.w r3, r3, #1 + 8014a44: 2b00 cmp r3, #0 + 8014a46: d00d beq.n 8014a64 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags |= TF_GOT_FIN; + 8014a48: 4b68 ldr r3, [pc, #416] ; (8014bec ) + 8014a4a: 781b ldrb r3, [r3, #0] + 8014a4c: f043 0320 orr.w r3, r3, #32 + 8014a50: b2da uxtb r2, r3 + 8014a52: 4b66 ldr r3, [pc, #408] ; (8014bec ) + 8014a54: 701a strb r2, [r3, #0] + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + 8014a56: 687b ldr r3, [r7, #4] + 8014a58: 7d1b ldrb r3, [r3, #20] + 8014a5a: 2b04 cmp r3, #4 + 8014a5c: d102 bne.n 8014a64 + pcb->state = CLOSE_WAIT; + 8014a5e: 687b ldr r3, [r7, #4] + 8014a60: 2207 movs r2, #7 + 8014a62: 751a strb r2, [r3, #20] + } + } + + pcb->ooseq = cseg->next; + 8014a64: 68bb ldr r3, [r7, #8] + 8014a66: 681a ldr r2, [r3, #0] + 8014a68: 687b ldr r3, [r7, #4] + 8014a6a: 675a str r2, [r3, #116] ; 0x74 + tcp_seg_free(cseg); + 8014a6c: 68b8 ldr r0, [r7, #8] + 8014a6e: f7fd fbd2 bl 8012216 + while (pcb->ooseq != NULL && + 8014a72: 687b ldr r3, [r7, #4] + 8014a74: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014a76: 2b00 cmp r3, #0 + 8014a78: d008 beq.n 8014a8c + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + 8014a7a: 687b ldr r3, [r7, #4] + 8014a7c: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014a7e: 68db ldr r3, [r3, #12] + 8014a80: 685a ldr r2, [r3, #4] + 8014a82: 687b ldr r3, [r7, #4] + 8014a84: 6a5b ldr r3, [r3, #36] ; 0x24 + while (pcb->ooseq != NULL && + 8014a86: 429a cmp r2, r3 + 8014a88: f43f af43 beq.w 8014912 +#endif /* LWIP_TCP_SACK_OUT */ +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + 8014a8c: 687b ldr r3, [r7, #4] + 8014a8e: 8b5b ldrh r3, [r3, #26] + 8014a90: f003 0301 and.w r3, r3, #1 + 8014a94: 2b00 cmp r3, #0 + 8014a96: d00e beq.n 8014ab6 + 8014a98: 687b ldr r3, [r7, #4] + 8014a9a: 8b5b ldrh r3, [r3, #26] + 8014a9c: f023 0301 bic.w r3, r3, #1 + 8014aa0: b29a uxth r2, r3 + 8014aa2: 687b ldr r3, [r7, #4] + 8014aa4: 835a strh r2, [r3, #26] + 8014aa6: 687b ldr r3, [r7, #4] + 8014aa8: 8b5b ldrh r3, [r3, #26] + 8014aaa: f043 0302 orr.w r3, r3, #2 + 8014aae: b29a uxth r2, r3 + 8014ab0: 687b ldr r3, [r7, #4] + 8014ab2: 835a strh r2, [r3, #26] + if (pcb->rcv_nxt == seqno) { + 8014ab4: e188 b.n 8014dc8 + tcp_ack(pcb); + 8014ab6: 687b ldr r3, [r7, #4] + 8014ab8: 8b5b ldrh r3, [r3, #26] + 8014aba: f043 0301 orr.w r3, r3, #1 + 8014abe: b29a uxth r2, r3 + 8014ac0: 687b ldr r3, [r7, #4] + 8014ac2: 835a strh r2, [r3, #26] + if (pcb->rcv_nxt == seqno) { + 8014ac4: e180 b.n 8014dc8 + } else { + /* We get here if the incoming segment is out-of-sequence. */ + +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + 8014ac6: 687b ldr r3, [r7, #4] + 8014ac8: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014aca: 2b00 cmp r3, #0 + 8014acc: d106 bne.n 8014adc + pcb->ooseq = tcp_seg_copy(&inseg); + 8014ace: 4848 ldr r0, [pc, #288] ; (8014bf0 ) + 8014ad0: f7fd fbba bl 8012248 + 8014ad4: 4602 mov r2, r0 + 8014ad6: 687b ldr r3, [r7, #4] + 8014ad8: 675a str r2, [r3, #116] ; 0x74 + 8014ada: e16d b.n 8014db8 +#if LWIP_TCP_SACK_OUT + /* This is the left edge of the lowest possible SACK range. + It may start before the newly received segment (possibly adjusted below). */ + u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno; +#endif /* LWIP_TCP_SACK_OUT */ + struct tcp_seg *next, *prev = NULL; + 8014adc: 2300 movs r3, #0 + 8014ade: 637b str r3, [r7, #52] ; 0x34 + for (next = pcb->ooseq; next != NULL; next = next->next) { + 8014ae0: 687b ldr r3, [r7, #4] + 8014ae2: 6f5b ldr r3, [r3, #116] ; 0x74 + 8014ae4: 63bb str r3, [r7, #56] ; 0x38 + 8014ae6: e157 b.n 8014d98 + if (seqno == next->tcphdr->seqno) { + 8014ae8: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014aea: 68db ldr r3, [r3, #12] + 8014aec: 685a ldr r2, [r3, #4] + 8014aee: 4b41 ldr r3, [pc, #260] ; (8014bf4 ) + 8014af0: 681b ldr r3, [r3, #0] + 8014af2: 429a cmp r2, r3 + 8014af4: d11d bne.n 8014b32 + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + 8014af6: 4b3e ldr r3, [pc, #248] ; (8014bf0 ) + 8014af8: 891a ldrh r2, [r3, #8] + 8014afa: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014afc: 891b ldrh r3, [r3, #8] + 8014afe: 429a cmp r2, r3 + 8014b00: f240 814f bls.w 8014da2 + /* The incoming segment is larger than the old + segment. We replace some segments with the new + one. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 8014b04: 483a ldr r0, [pc, #232] ; (8014bf0 ) + 8014b06: f7fd fb9f bl 8012248 + 8014b0a: 6178 str r0, [r7, #20] + if (cseg != NULL) { + 8014b0c: 697b ldr r3, [r7, #20] + 8014b0e: 2b00 cmp r3, #0 + 8014b10: f000 8149 beq.w 8014da6 + if (prev != NULL) { + 8014b14: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014b16: 2b00 cmp r3, #0 + 8014b18: d003 beq.n 8014b22 + prev->next = cseg; + 8014b1a: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014b1c: 697a ldr r2, [r7, #20] + 8014b1e: 601a str r2, [r3, #0] + 8014b20: e002 b.n 8014b28 + } else { + pcb->ooseq = cseg; + 8014b22: 687b ldr r3, [r7, #4] + 8014b24: 697a ldr r2, [r7, #20] + 8014b26: 675a str r2, [r3, #116] ; 0x74 + } + tcp_oos_insert_segment(cseg, next); + 8014b28: 6bb9 ldr r1, [r7, #56] ; 0x38 + 8014b2a: 6978 ldr r0, [r7, #20] + 8014b2c: f7ff f8dc bl 8013ce8 + } + break; + 8014b30: e139 b.n 8014da6 + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + 8014b32: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014b34: 2b00 cmp r3, #0 + 8014b36: d117 bne.n 8014b68 + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + 8014b38: 4b2e ldr r3, [pc, #184] ; (8014bf4 ) + 8014b3a: 681a ldr r2, [r3, #0] + 8014b3c: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014b3e: 68db ldr r3, [r3, #12] + 8014b40: 685b ldr r3, [r3, #4] + 8014b42: 1ad3 subs r3, r2, r3 + 8014b44: 2b00 cmp r3, #0 + 8014b46: da57 bge.n 8014bf8 + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 8014b48: 4829 ldr r0, [pc, #164] ; (8014bf0 ) + 8014b4a: f7fd fb7d bl 8012248 + 8014b4e: 61b8 str r0, [r7, #24] + if (cseg != NULL) { + 8014b50: 69bb ldr r3, [r7, #24] + 8014b52: 2b00 cmp r3, #0 + 8014b54: f000 8129 beq.w 8014daa + pcb->ooseq = cseg; + 8014b58: 687b ldr r3, [r7, #4] + 8014b5a: 69ba ldr r2, [r7, #24] + 8014b5c: 675a str r2, [r3, #116] ; 0x74 + tcp_oos_insert_segment(cseg, next); + 8014b5e: 6bb9 ldr r1, [r7, #56] ; 0x38 + 8014b60: 69b8 ldr r0, [r7, #24] + 8014b62: f7ff f8c1 bl 8013ce8 + } + break; + 8014b66: e120 b.n 8014daa + } + } else { + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) { + 8014b68: 4b22 ldr r3, [pc, #136] ; (8014bf4 ) + 8014b6a: 681a ldr r2, [r3, #0] + 8014b6c: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014b6e: 68db ldr r3, [r3, #12] + 8014b70: 685b ldr r3, [r3, #4] + 8014b72: 1ad3 subs r3, r2, r3 + 8014b74: 3b01 subs r3, #1 + 8014b76: 2b00 cmp r3, #0 + 8014b78: db3e blt.n 8014bf8 + 8014b7a: 4b1e ldr r3, [pc, #120] ; (8014bf4 ) + 8014b7c: 681a ldr r2, [r3, #0] + 8014b7e: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014b80: 68db ldr r3, [r3, #12] + 8014b82: 685b ldr r3, [r3, #4] + 8014b84: 1ad3 subs r3, r2, r3 + 8014b86: 3301 adds r3, #1 + 8014b88: 2b00 cmp r3, #0 + 8014b8a: dc35 bgt.n 8014bf8 + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim trim the previous + segment, delete next segments that included in received segment + and trim received, if needed. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 8014b8c: 4818 ldr r0, [pc, #96] ; (8014bf0 ) + 8014b8e: f7fd fb5b bl 8012248 + 8014b92: 61f8 str r0, [r7, #28] + if (cseg != NULL) { + 8014b94: 69fb ldr r3, [r7, #28] + 8014b96: 2b00 cmp r3, #0 + 8014b98: f000 8109 beq.w 8014dae + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + 8014b9c: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014b9e: 68db ldr r3, [r3, #12] + 8014ba0: 685b ldr r3, [r3, #4] + 8014ba2: 6b7a ldr r2, [r7, #52] ; 0x34 + 8014ba4: 8912 ldrh r2, [r2, #8] + 8014ba6: 441a add r2, r3 + 8014ba8: 4b12 ldr r3, [pc, #72] ; (8014bf4 ) + 8014baa: 681b ldr r3, [r3, #0] + 8014bac: 1ad3 subs r3, r2, r3 + 8014bae: 2b00 cmp r3, #0 + 8014bb0: dd12 ble.n 8014bd8 + /* We need to trim the prev segment. */ + prev->len = (u16_t)(seqno - prev->tcphdr->seqno); + 8014bb2: 4b10 ldr r3, [pc, #64] ; (8014bf4 ) + 8014bb4: 681b ldr r3, [r3, #0] + 8014bb6: b29a uxth r2, r3 + 8014bb8: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014bba: 68db ldr r3, [r3, #12] + 8014bbc: 685b ldr r3, [r3, #4] + 8014bbe: b29b uxth r3, r3 + 8014bc0: 1ad3 subs r3, r2, r3 + 8014bc2: b29a uxth r2, r3 + 8014bc4: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014bc6: 811a strh r2, [r3, #8] + pbuf_realloc(prev->p, prev->len); + 8014bc8: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014bca: 685a ldr r2, [r3, #4] + 8014bcc: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014bce: 891b ldrh r3, [r3, #8] + 8014bd0: 4619 mov r1, r3 + 8014bd2: 4610 mov r0, r2 + 8014bd4: f7fb fd8e bl 80106f4 + } + prev->next = cseg; + 8014bd8: 6b7b ldr r3, [r7, #52] ; 0x34 + 8014bda: 69fa ldr r2, [r7, #28] + 8014bdc: 601a str r2, [r3, #0] + tcp_oos_insert_segment(cseg, next); + 8014bde: 6bb9 ldr r1, [r7, #56] ; 0x38 + 8014be0: 69f8 ldr r0, [r7, #28] + 8014be2: f7ff f881 bl 8013ce8 + } + break; + 8014be6: e0e2 b.n 8014dae + 8014be8: 2000cf78 .word 0x2000cf78 + 8014bec: 2000cf75 .word 0x2000cf75 + 8014bf0: 2000cf48 .word 0x2000cf48 + 8014bf4: 2000cf68 .word 0x2000cf68 +#endif /* LWIP_TCP_SACK_OUT */ + + /* We don't use 'prev' below, so let's set it to current 'next'. + This way even if we break the loop below, 'prev' will be pointing + at the segment right in front of the newly added one. */ + prev = next; + 8014bf8: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014bfa: 637b str r3, [r7, #52] ; 0x34 + + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + 8014bfc: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014bfe: 681b ldr r3, [r3, #0] + 8014c00: 2b00 cmp r3, #0 + 8014c02: f040 80c6 bne.w 8014d92 + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + 8014c06: 4b80 ldr r3, [pc, #512] ; (8014e08 ) + 8014c08: 681a ldr r2, [r3, #0] + 8014c0a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c0c: 68db ldr r3, [r3, #12] + 8014c0e: 685b ldr r3, [r3, #4] + 8014c10: 1ad3 subs r3, r2, r3 + if (next->next == NULL && + 8014c12: 2b00 cmp r3, #0 + 8014c14: f340 80bd ble.w 8014d92 + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + 8014c18: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c1a: 68db ldr r3, [r3, #12] + 8014c1c: 899b ldrh r3, [r3, #12] + 8014c1e: b29b uxth r3, r3 + 8014c20: 4618 mov r0, r3 + 8014c22: f7f9 fb05 bl 800e230 + 8014c26: 4603 mov r3, r0 + 8014c28: b2db uxtb r3, r3 + 8014c2a: f003 0301 and.w r3, r3, #1 + 8014c2e: 2b00 cmp r3, #0 + 8014c30: f040 80bf bne.w 8014db2 + /* segment "next" already contains all data */ + break; + } + next->next = tcp_seg_copy(&inseg); + 8014c34: 4875 ldr r0, [pc, #468] ; (8014e0c ) + 8014c36: f7fd fb07 bl 8012248 + 8014c3a: 4602 mov r2, r0 + 8014c3c: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c3e: 601a str r2, [r3, #0] + if (next->next != NULL) { + 8014c40: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c42: 681b ldr r3, [r3, #0] + 8014c44: 2b00 cmp r3, #0 + 8014c46: f000 80b6 beq.w 8014db6 + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + 8014c4a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c4c: 68db ldr r3, [r3, #12] + 8014c4e: 685b ldr r3, [r3, #4] + 8014c50: 6bba ldr r2, [r7, #56] ; 0x38 + 8014c52: 8912 ldrh r2, [r2, #8] + 8014c54: 441a add r2, r3 + 8014c56: 4b6c ldr r3, [pc, #432] ; (8014e08 ) + 8014c58: 681b ldr r3, [r3, #0] + 8014c5a: 1ad3 subs r3, r2, r3 + 8014c5c: 2b00 cmp r3, #0 + 8014c5e: dd12 ble.n 8014c86 + /* We need to trim the last segment. */ + next->len = (u16_t)(seqno - next->tcphdr->seqno); + 8014c60: 4b69 ldr r3, [pc, #420] ; (8014e08 ) + 8014c62: 681b ldr r3, [r3, #0] + 8014c64: b29a uxth r2, r3 + 8014c66: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c68: 68db ldr r3, [r3, #12] + 8014c6a: 685b ldr r3, [r3, #4] + 8014c6c: b29b uxth r3, r3 + 8014c6e: 1ad3 subs r3, r2, r3 + 8014c70: b29a uxth r2, r3 + 8014c72: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c74: 811a strh r2, [r3, #8] + pbuf_realloc(next->p, next->len); + 8014c76: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c78: 685a ldr r2, [r3, #4] + 8014c7a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014c7c: 891b ldrh r3, [r3, #8] + 8014c7e: 4619 mov r1, r3 + 8014c80: 4610 mov r0, r2 + 8014c82: f7fb fd37 bl 80106f4 + } + /* check if the remote side overruns our receive window */ + if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) { + 8014c86: 4b62 ldr r3, [pc, #392] ; (8014e10 ) + 8014c88: 881b ldrh r3, [r3, #0] + 8014c8a: 461a mov r2, r3 + 8014c8c: 4b5e ldr r3, [pc, #376] ; (8014e08 ) + 8014c8e: 681b ldr r3, [r3, #0] + 8014c90: 441a add r2, r3 + 8014c92: 687b ldr r3, [r7, #4] + 8014c94: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014c96: 6879 ldr r1, [r7, #4] + 8014c98: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8014c9a: 440b add r3, r1 + 8014c9c: 1ad3 subs r3, r2, r3 + 8014c9e: 2b00 cmp r3, #0 + 8014ca0: f340 8089 ble.w 8014db6 + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { + 8014ca4: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014ca6: 681b ldr r3, [r3, #0] + 8014ca8: 68db ldr r3, [r3, #12] + 8014caa: 899b ldrh r3, [r3, #12] + 8014cac: b29b uxth r3, r3 + 8014cae: 4618 mov r0, r3 + 8014cb0: f7f9 fabe bl 800e230 + 8014cb4: 4603 mov r3, r0 + 8014cb6: b2db uxtb r3, r3 + 8014cb8: f003 0301 and.w r3, r3, #1 + 8014cbc: 2b00 cmp r3, #0 + 8014cbe: d022 beq.n 8014d06 + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN); + 8014cc0: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014cc2: 681b ldr r3, [r3, #0] + 8014cc4: 68db ldr r3, [r3, #12] + 8014cc6: 899b ldrh r3, [r3, #12] + 8014cc8: b29b uxth r3, r3 + 8014cca: b21b sxth r3, r3 + 8014ccc: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 8014cd0: b21c sxth r4, r3 + 8014cd2: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014cd4: 681b ldr r3, [r3, #0] + 8014cd6: 68db ldr r3, [r3, #12] + 8014cd8: 899b ldrh r3, [r3, #12] + 8014cda: b29b uxth r3, r3 + 8014cdc: 4618 mov r0, r3 + 8014cde: f7f9 faa7 bl 800e230 + 8014ce2: 4603 mov r3, r0 + 8014ce4: b2db uxtb r3, r3 + 8014ce6: b29b uxth r3, r3 + 8014ce8: f003 033e and.w r3, r3, #62 ; 0x3e + 8014cec: b29b uxth r3, r3 + 8014cee: 4618 mov r0, r3 + 8014cf0: f7f9 fa9e bl 800e230 + 8014cf4: 4603 mov r3, r0 + 8014cf6: b21b sxth r3, r3 + 8014cf8: 4323 orrs r3, r4 + 8014cfa: b21a sxth r2, r3 + 8014cfc: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014cfe: 681b ldr r3, [r3, #0] + 8014d00: 68db ldr r3, [r3, #12] + 8014d02: b292 uxth r2, r2 + 8014d04: 819a strh r2, [r3, #12] + } + /* Adjust length of segment to fit in the window. */ + next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno); + 8014d06: 687b ldr r3, [r7, #4] + 8014d08: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014d0a: b29a uxth r2, r3 + 8014d0c: 687b ldr r3, [r7, #4] + 8014d0e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8014d10: 4413 add r3, r2 + 8014d12: b299 uxth r1, r3 + 8014d14: 4b3c ldr r3, [pc, #240] ; (8014e08 ) + 8014d16: 681b ldr r3, [r3, #0] + 8014d18: b29a uxth r2, r3 + 8014d1a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d1c: 681b ldr r3, [r3, #0] + 8014d1e: 1a8a subs r2, r1, r2 + 8014d20: b292 uxth r2, r2 + 8014d22: 811a strh r2, [r3, #8] + pbuf_realloc(next->next->p, next->next->len); + 8014d24: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d26: 681b ldr r3, [r3, #0] + 8014d28: 685a ldr r2, [r3, #4] + 8014d2a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d2c: 681b ldr r3, [r3, #0] + 8014d2e: 891b ldrh r3, [r3, #8] + 8014d30: 4619 mov r1, r3 + 8014d32: 4610 mov r0, r2 + 8014d34: f7fb fcde bl 80106f4 + tcplen = TCP_TCPLEN(next->next); + 8014d38: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d3a: 681b ldr r3, [r3, #0] + 8014d3c: 891c ldrh r4, [r3, #8] + 8014d3e: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d40: 681b ldr r3, [r3, #0] + 8014d42: 68db ldr r3, [r3, #12] + 8014d44: 899b ldrh r3, [r3, #12] + 8014d46: b29b uxth r3, r3 + 8014d48: 4618 mov r0, r3 + 8014d4a: f7f9 fa71 bl 800e230 + 8014d4e: 4603 mov r3, r0 + 8014d50: b2db uxtb r3, r3 + 8014d52: f003 0303 and.w r3, r3, #3 + 8014d56: 2b00 cmp r3, #0 + 8014d58: d001 beq.n 8014d5e + 8014d5a: 2301 movs r3, #1 + 8014d5c: e000 b.n 8014d60 + 8014d5e: 2300 movs r3, #0 + 8014d60: 4423 add r3, r4 + 8014d62: b29a uxth r2, r3 + 8014d64: 4b2a ldr r3, [pc, #168] ; (8014e10 ) + 8014d66: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + 8014d68: 4b29 ldr r3, [pc, #164] ; (8014e10 ) + 8014d6a: 881b ldrh r3, [r3, #0] + 8014d6c: 461a mov r2, r3 + 8014d6e: 4b26 ldr r3, [pc, #152] ; (8014e08 ) + 8014d70: 681b ldr r3, [r3, #0] + 8014d72: 441a add r2, r3 + 8014d74: 687b ldr r3, [r7, #4] + 8014d76: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014d78: 6879 ldr r1, [r7, #4] + 8014d7a: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8014d7c: 440b add r3, r1 + 8014d7e: 429a cmp r2, r3 + 8014d80: d019 beq.n 8014db6 + 8014d82: 4b24 ldr r3, [pc, #144] ; (8014e14 ) + 8014d84: f44f 62df mov.w r2, #1784 ; 0x6f8 + 8014d88: 4923 ldr r1, [pc, #140] ; (8014e18 ) + 8014d8a: 4824 ldr r0, [pc, #144] ; (8014e1c ) + 8014d8c: f007 f942 bl 801c014 + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } + } + break; + 8014d90: e011 b.n 8014db6 + for (next = pcb->ooseq; next != NULL; next = next->next) { + 8014d92: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d94: 681b ldr r3, [r3, #0] + 8014d96: 63bb str r3, [r7, #56] ; 0x38 + 8014d98: 6bbb ldr r3, [r7, #56] ; 0x38 + 8014d9a: 2b00 cmp r3, #0 + 8014d9c: f47f aea4 bne.w 8014ae8 + 8014da0: e00a b.n 8014db8 + break; + 8014da2: bf00 nop + 8014da4: e008 b.n 8014db8 + break; + 8014da6: bf00 nop + 8014da8: e006 b.n 8014db8 + break; + 8014daa: bf00 nop + 8014dac: e004 b.n 8014db8 + break; + 8014dae: bf00 nop + 8014db0: e002 b.n 8014db8 + break; + 8014db2: bf00 nop + 8014db4: e000 b.n 8014db8 + break; + 8014db6: bf00 nop +#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ +#endif /* TCP_QUEUE_OOSEQ */ + + /* We send the ACK packet after we've (potentially) dealt with SACKs, + so they can be included in the acknowledgment. */ + tcp_send_empty_ack(pcb); + 8014db8: 6878 ldr r0, [r7, #4] + 8014dba: f001 fa33 bl 8016224 + if (pcb->rcv_nxt == seqno) { + 8014dbe: e003 b.n 8014dc8 + } + } else { + /* The incoming segment is not within the window. */ + tcp_send_empty_ack(pcb); + 8014dc0: 6878 ldr r0, [r7, #4] + 8014dc2: f001 fa2f bl 8016224 + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 8014dc6: e01a b.n 8014dfe + 8014dc8: e019 b.n 8014dfe + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + 8014dca: 4b0f ldr r3, [pc, #60] ; (8014e08 ) + 8014dcc: 681a ldr r2, [r3, #0] + 8014dce: 687b ldr r3, [r7, #4] + 8014dd0: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014dd2: 1ad3 subs r3, r2, r3 + 8014dd4: 2b00 cmp r3, #0 + 8014dd6: db0a blt.n 8014dee + 8014dd8: 4b0b ldr r3, [pc, #44] ; (8014e08 ) + 8014dda: 681a ldr r2, [r3, #0] + 8014ddc: 687b ldr r3, [r7, #4] + 8014dde: 6a5b ldr r3, [r3, #36] ; 0x24 + 8014de0: 6879 ldr r1, [r7, #4] + 8014de2: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8014de4: 440b add r3, r1 + 8014de6: 1ad3 subs r3, r2, r3 + 8014de8: 3301 adds r3, #1 + 8014dea: 2b00 cmp r3, #0 + 8014dec: dd07 ble.n 8014dfe + tcp_ack_now(pcb); + 8014dee: 687b ldr r3, [r7, #4] + 8014df0: 8b5b ldrh r3, [r3, #26] + 8014df2: f043 0302 orr.w r3, r3, #2 + 8014df6: b29a uxth r2, r3 + 8014df8: 687b ldr r3, [r7, #4] + 8014dfa: 835a strh r2, [r3, #26] + } + } +} + 8014dfc: e7ff b.n 8014dfe + 8014dfe: bf00 nop + 8014e00: 3750 adds r7, #80 ; 0x50 + 8014e02: 46bd mov sp, r7 + 8014e04: bdb0 pop {r4, r5, r7, pc} + 8014e06: bf00 nop + 8014e08: 2000cf68 .word 0x2000cf68 + 8014e0c: 2000cf48 .word 0x2000cf48 + 8014e10: 2000cf72 .word 0x2000cf72 + 8014e14: 0801fc88 .word 0x0801fc88 + 8014e18: 08020030 .word 0x08020030 + 8014e1c: 0801fcd4 .word 0x0801fcd4 + +08014e20 : + +static u8_t +tcp_get_next_optbyte(void) +{ + 8014e20: b480 push {r7} + 8014e22: b083 sub sp, #12 + 8014e24: af00 add r7, sp, #0 + u16_t optidx = tcp_optidx++; + 8014e26: 4b15 ldr r3, [pc, #84] ; (8014e7c ) + 8014e28: 881b ldrh r3, [r3, #0] + 8014e2a: 1c5a adds r2, r3, #1 + 8014e2c: b291 uxth r1, r2 + 8014e2e: 4a13 ldr r2, [pc, #76] ; (8014e7c ) + 8014e30: 8011 strh r1, [r2, #0] + 8014e32: 80fb strh r3, [r7, #6] + if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) { + 8014e34: 4b12 ldr r3, [pc, #72] ; (8014e80 ) + 8014e36: 681b ldr r3, [r3, #0] + 8014e38: 2b00 cmp r3, #0 + 8014e3a: d004 beq.n 8014e46 + 8014e3c: 4b11 ldr r3, [pc, #68] ; (8014e84 ) + 8014e3e: 881b ldrh r3, [r3, #0] + 8014e40: 88fa ldrh r2, [r7, #6] + 8014e42: 429a cmp r2, r3 + 8014e44: d208 bcs.n 8014e58 + u8_t *opts = (u8_t *)tcphdr + TCP_HLEN; + 8014e46: 4b10 ldr r3, [pc, #64] ; (8014e88 ) + 8014e48: 681b ldr r3, [r3, #0] + 8014e4a: 3314 adds r3, #20 + 8014e4c: 603b str r3, [r7, #0] + return opts[optidx]; + 8014e4e: 88fb ldrh r3, [r7, #6] + 8014e50: 683a ldr r2, [r7, #0] + 8014e52: 4413 add r3, r2 + 8014e54: 781b ldrb r3, [r3, #0] + 8014e56: e00b b.n 8014e70 + } else { + u8_t idx = (u8_t)(optidx - tcphdr_opt1len); + 8014e58: 88fb ldrh r3, [r7, #6] + 8014e5a: b2da uxtb r2, r3 + 8014e5c: 4b09 ldr r3, [pc, #36] ; (8014e84 ) + 8014e5e: 881b ldrh r3, [r3, #0] + 8014e60: b2db uxtb r3, r3 + 8014e62: 1ad3 subs r3, r2, r3 + 8014e64: 717b strb r3, [r7, #5] + return tcphdr_opt2[idx]; + 8014e66: 4b06 ldr r3, [pc, #24] ; (8014e80 ) + 8014e68: 681a ldr r2, [r3, #0] + 8014e6a: 797b ldrb r3, [r7, #5] + 8014e6c: 4413 add r3, r2 + 8014e6e: 781b ldrb r3, [r3, #0] + } +} + 8014e70: 4618 mov r0, r3 + 8014e72: 370c adds r7, #12 + 8014e74: 46bd mov sp, r7 + 8014e76: f85d 7b04 ldr.w r7, [sp], #4 + 8014e7a: 4770 bx lr + 8014e7c: 2000cf64 .word 0x2000cf64 + 8014e80: 2000cf60 .word 0x2000cf60 + 8014e84: 2000cf5e .word 0x2000cf5e + 8014e88: 2000cf58 .word 0x2000cf58 + +08014e8c : + * + * @param pcb the tcp_pcb for which a segment arrived + */ +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + 8014e8c: b580 push {r7, lr} + 8014e8e: b084 sub sp, #16 + 8014e90: af00 add r7, sp, #0 + 8014e92: 6078 str r0, [r7, #4] + u16_t mss; +#if LWIP_TCP_TIMESTAMPS + u32_t tsval; +#endif + + LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL); + 8014e94: 687b ldr r3, [r7, #4] + 8014e96: 2b00 cmp r3, #0 + 8014e98: d106 bne.n 8014ea8 + 8014e9a: 4b32 ldr r3, [pc, #200] ; (8014f64 ) + 8014e9c: f240 727d movw r2, #1917 ; 0x77d + 8014ea0: 4931 ldr r1, [pc, #196] ; (8014f68 ) + 8014ea2: 4832 ldr r0, [pc, #200] ; (8014f6c ) + 8014ea4: f007 f8b6 bl 801c014 + + /* Parse the TCP MSS option, if present. */ + if (tcphdr_optlen != 0) { + 8014ea8: 4b31 ldr r3, [pc, #196] ; (8014f70 ) + 8014eaa: 881b ldrh r3, [r3, #0] + 8014eac: 2b00 cmp r3, #0 + 8014eae: d055 beq.n 8014f5c + for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { + 8014eb0: 4b30 ldr r3, [pc, #192] ; (8014f74 ) + 8014eb2: 2200 movs r2, #0 + 8014eb4: 801a strh r2, [r3, #0] + 8014eb6: e045 b.n 8014f44 + u8_t opt = tcp_get_next_optbyte(); + 8014eb8: f7ff ffb2 bl 8014e20 + 8014ebc: 4603 mov r3, r0 + 8014ebe: 73fb strb r3, [r7, #15] + switch (opt) { + 8014ec0: 7bfb ldrb r3, [r7, #15] + 8014ec2: 2b02 cmp r3, #2 + 8014ec4: d006 beq.n 8014ed4 + 8014ec6: 2b02 cmp r3, #2 + 8014ec8: dc2b bgt.n 8014f22 + 8014eca: 2b00 cmp r3, #0 + 8014ecc: d041 beq.n 8014f52 + 8014ece: 2b01 cmp r3, #1 + 8014ed0: d127 bne.n 8014f22 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); + return; + case LWIP_TCP_OPT_NOP: + /* NOP option. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); + break; + 8014ed2: e037 b.n 8014f44 + case LWIP_TCP_OPT_MSS: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) { + 8014ed4: f7ff ffa4 bl 8014e20 + 8014ed8: 4603 mov r3, r0 + 8014eda: 2b04 cmp r3, #4 + 8014edc: d13b bne.n 8014f56 + 8014ede: 4b25 ldr r3, [pc, #148] ; (8014f74 ) + 8014ee0: 881b ldrh r3, [r3, #0] + 8014ee2: 3301 adds r3, #1 + 8014ee4: 4a22 ldr r2, [pc, #136] ; (8014f70 ) + 8014ee6: 8812 ldrh r2, [r2, #0] + 8014ee8: 4293 cmp r3, r2 + 8014eea: da34 bge.n 8014f56 + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An MSS option with the right option length. */ + mss = (u16_t)(tcp_get_next_optbyte() << 8); + 8014eec: f7ff ff98 bl 8014e20 + 8014ef0: 4603 mov r3, r0 + 8014ef2: b29b uxth r3, r3 + 8014ef4: 021b lsls r3, r3, #8 + 8014ef6: 81bb strh r3, [r7, #12] + mss |= tcp_get_next_optbyte(); + 8014ef8: f7ff ff92 bl 8014e20 + 8014efc: 4603 mov r3, r0 + 8014efe: b29a uxth r2, r3 + 8014f00: 89bb ldrh r3, [r7, #12] + 8014f02: 4313 orrs r3, r2 + 8014f04: 81bb strh r3, [r7, #12] + /* Limit the mss to the configured TCP_MSS and prevent division by zero */ + pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; + 8014f06: 89bb ldrh r3, [r7, #12] + 8014f08: f5b3 7f06 cmp.w r3, #536 ; 0x218 + 8014f0c: d804 bhi.n 8014f18 + 8014f0e: 89bb ldrh r3, [r7, #12] + 8014f10: 2b00 cmp r3, #0 + 8014f12: d001 beq.n 8014f18 + 8014f14: 89ba ldrh r2, [r7, #12] + 8014f16: e001 b.n 8014f1c + 8014f18: f44f 7206 mov.w r2, #536 ; 0x218 + 8014f1c: 687b ldr r3, [r7, #4] + 8014f1e: 865a strh r2, [r3, #50] ; 0x32 + break; + 8014f20: e010 b.n 8014f44 + } + break; +#endif /* LWIP_TCP_SACK_OUT */ + default: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); + data = tcp_get_next_optbyte(); + 8014f22: f7ff ff7d bl 8014e20 + 8014f26: 4603 mov r3, r0 + 8014f28: 72fb strb r3, [r7, #11] + if (data < 2) { + 8014f2a: 7afb ldrb r3, [r7, #11] + 8014f2c: 2b01 cmp r3, #1 + 8014f2e: d914 bls.n 8014f5a + and we don't process them further. */ + return; + } + /* All other options have a length field, so that we easily + can skip past them. */ + tcp_optidx += data - 2; + 8014f30: 7afb ldrb r3, [r7, #11] + 8014f32: b29a uxth r2, r3 + 8014f34: 4b0f ldr r3, [pc, #60] ; (8014f74 ) + 8014f36: 881b ldrh r3, [r3, #0] + 8014f38: 4413 add r3, r2 + 8014f3a: b29b uxth r3, r3 + 8014f3c: 3b02 subs r3, #2 + 8014f3e: b29a uxth r2, r3 + 8014f40: 4b0c ldr r3, [pc, #48] ; (8014f74 ) + 8014f42: 801a strh r2, [r3, #0] + for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { + 8014f44: 4b0b ldr r3, [pc, #44] ; (8014f74 ) + 8014f46: 881a ldrh r2, [r3, #0] + 8014f48: 4b09 ldr r3, [pc, #36] ; (8014f70 ) + 8014f4a: 881b ldrh r3, [r3, #0] + 8014f4c: 429a cmp r2, r3 + 8014f4e: d3b3 bcc.n 8014eb8 + 8014f50: e004 b.n 8014f5c + return; + 8014f52: bf00 nop + 8014f54: e002 b.n 8014f5c + return; + 8014f56: bf00 nop + 8014f58: e000 b.n 8014f5c + return; + 8014f5a: bf00 nop + } + } + } +} + 8014f5c: 3710 adds r7, #16 + 8014f5e: 46bd mov sp, r7 + 8014f60: bd80 pop {r7, pc} + 8014f62: bf00 nop + 8014f64: 0801fc88 .word 0x0801fc88 + 8014f68: 080200ec .word 0x080200ec + 8014f6c: 0801fcd4 .word 0x0801fcd4 + 8014f70: 2000cf5c .word 0x2000cf5c + 8014f74: 2000cf64 .word 0x2000cf64 + +08014f78 : + +void +tcp_trigger_input_pcb_close(void) +{ + 8014f78: b480 push {r7} + 8014f7a: af00 add r7, sp, #0 + recv_flags |= TF_CLOSED; + 8014f7c: 4b05 ldr r3, [pc, #20] ; (8014f94 ) + 8014f7e: 781b ldrb r3, [r3, #0] + 8014f80: f043 0310 orr.w r3, r3, #16 + 8014f84: b2da uxtb r2, r3 + 8014f86: 4b03 ldr r3, [pc, #12] ; (8014f94 ) + 8014f88: 701a strb r2, [r3, #0] +} + 8014f8a: bf00 nop + 8014f8c: 46bd mov sp, r7 + 8014f8e: f85d 7b04 ldr.w r7, [sp], #4 + 8014f92: 4770 bx lr + 8014f94: 2000cf75 .word 0x2000cf75 + +08014f98 : +static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif); + +/* tcp_route: common code that returns a fixed bound netif or calls ip_route */ +static struct netif * +tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst) +{ + 8014f98: b580 push {r7, lr} + 8014f9a: b084 sub sp, #16 + 8014f9c: af00 add r7, sp, #0 + 8014f9e: 60f8 str r0, [r7, #12] + 8014fa0: 60b9 str r1, [r7, #8] + 8014fa2: 607a str r2, [r7, #4] + LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */ + + if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) { + 8014fa4: 68fb ldr r3, [r7, #12] + 8014fa6: 2b00 cmp r3, #0 + 8014fa8: d00a beq.n 8014fc0 + 8014faa: 68fb ldr r3, [r7, #12] + 8014fac: 7a1b ldrb r3, [r3, #8] + 8014fae: 2b00 cmp r3, #0 + 8014fb0: d006 beq.n 8014fc0 + return netif_get_by_index(pcb->netif_idx); + 8014fb2: 68fb ldr r3, [r7, #12] + 8014fb4: 7a1b ldrb r3, [r3, #8] + 8014fb6: 4618 mov r0, r3 + 8014fb8: f7fb f994 bl 80102e4 + 8014fbc: 4603 mov r3, r0 + 8014fbe: e003 b.n 8014fc8 + } else { + return ip_route(src, dst); + 8014fc0: 6878 ldr r0, [r7, #4] + 8014fc2: f005 f95b bl 801a27c + 8014fc6: 4603 mov r3, r0 + } +} + 8014fc8: 4618 mov r0, r3 + 8014fca: 3710 adds r7, #16 + 8014fcc: 46bd mov sp, r7 + 8014fce: bd80 pop {r7, pc} + +08014fd0 : + * The TCP header is filled in except ackno and wnd. + * p is freed on failure. + */ +static struct tcp_seg * +tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags) +{ + 8014fd0: b590 push {r4, r7, lr} + 8014fd2: b087 sub sp, #28 + 8014fd4: af00 add r7, sp, #0 + 8014fd6: 60f8 str r0, [r7, #12] + 8014fd8: 60b9 str r1, [r7, #8] + 8014fda: 603b str r3, [r7, #0] + 8014fdc: 4613 mov r3, r2 + 8014fde: 71fb strb r3, [r7, #7] + struct tcp_seg *seg; + u8_t optlen; + + LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL); + 8014fe0: 68fb ldr r3, [r7, #12] + 8014fe2: 2b00 cmp r3, #0 + 8014fe4: d105 bne.n 8014ff2 + 8014fe6: 4b44 ldr r3, [pc, #272] ; (80150f8 ) + 8014fe8: 22a3 movs r2, #163 ; 0xa3 + 8014fea: 4944 ldr r1, [pc, #272] ; (80150fc ) + 8014fec: 4844 ldr r0, [pc, #272] ; (8015100 ) + 8014fee: f007 f811 bl 801c014 + LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL); + 8014ff2: 68bb ldr r3, [r7, #8] + 8014ff4: 2b00 cmp r3, #0 + 8014ff6: d105 bne.n 8015004 + 8014ff8: 4b3f ldr r3, [pc, #252] ; (80150f8 ) + 8014ffa: 22a4 movs r2, #164 ; 0xa4 + 8014ffc: 4941 ldr r1, [pc, #260] ; (8015104 ) + 8014ffe: 4840 ldr r0, [pc, #256] ; (8015100 ) + 8015000: f007 f808 bl 801c014 + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 8015004: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 8015008: 009b lsls r3, r3, #2 + 801500a: b2db uxtb r3, r3 + 801500c: f003 0304 and.w r3, r3, #4 + 8015010: 75fb strb r3, [r7, #23] + + if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { + 8015012: 2003 movs r0, #3 + 8015014: f7fa fdce bl 800fbb4 + 8015018: 6138 str r0, [r7, #16] + 801501a: 693b ldr r3, [r7, #16] + 801501c: 2b00 cmp r3, #0 + 801501e: d104 bne.n 801502a + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n")); + pbuf_free(p); + 8015020: 68b8 ldr r0, [r7, #8] + 8015022: f7fb fced bl 8010a00 + return NULL; + 8015026: 2300 movs r3, #0 + 8015028: e061 b.n 80150ee + } + seg->flags = optflags; + 801502a: 693b ldr r3, [r7, #16] + 801502c: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 + 8015030: 729a strb r2, [r3, #10] + seg->next = NULL; + 8015032: 693b ldr r3, [r7, #16] + 8015034: 2200 movs r2, #0 + 8015036: 601a str r2, [r3, #0] + seg->p = p; + 8015038: 693b ldr r3, [r7, #16] + 801503a: 68ba ldr r2, [r7, #8] + 801503c: 605a str r2, [r3, #4] + LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen); + 801503e: 68bb ldr r3, [r7, #8] + 8015040: 891a ldrh r2, [r3, #8] + 8015042: 7dfb ldrb r3, [r7, #23] + 8015044: b29b uxth r3, r3 + 8015046: 429a cmp r2, r3 + 8015048: d205 bcs.n 8015056 + 801504a: 4b2b ldr r3, [pc, #172] ; (80150f8 ) + 801504c: 22b0 movs r2, #176 ; 0xb0 + 801504e: 492e ldr r1, [pc, #184] ; (8015108 ) + 8015050: 482b ldr r0, [pc, #172] ; (8015100 ) + 8015052: f006 ffdf bl 801c014 + seg->len = p->tot_len - optlen; + 8015056: 68bb ldr r3, [r7, #8] + 8015058: 891a ldrh r2, [r3, #8] + 801505a: 7dfb ldrb r3, [r7, #23] + 801505c: b29b uxth r3, r3 + 801505e: 1ad3 subs r3, r2, r3 + 8015060: b29a uxth r2, r3 + 8015062: 693b ldr r3, [r7, #16] + 8015064: 811a strh r2, [r3, #8] + LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", + (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* build TCP header */ + if (pbuf_add_header(p, TCP_HLEN)) { + 8015066: 2114 movs r1, #20 + 8015068: 68b8 ldr r0, [r7, #8] + 801506a: f7fb fc33 bl 80108d4 + 801506e: 4603 mov r3, r0 + 8015070: 2b00 cmp r3, #0 + 8015072: d004 beq.n 801507e + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + tcp_seg_free(seg); + 8015074: 6938 ldr r0, [r7, #16] + 8015076: f7fd f8ce bl 8012216 + return NULL; + 801507a: 2300 movs r3, #0 + 801507c: e037 b.n 80150ee + } + seg->tcphdr = (struct tcp_hdr *)seg->p->payload; + 801507e: 693b ldr r3, [r7, #16] + 8015080: 685b ldr r3, [r3, #4] + 8015082: 685a ldr r2, [r3, #4] + 8015084: 693b ldr r3, [r7, #16] + 8015086: 60da str r2, [r3, #12] + seg->tcphdr->src = lwip_htons(pcb->local_port); + 8015088: 68fb ldr r3, [r7, #12] + 801508a: 8ada ldrh r2, [r3, #22] + 801508c: 693b ldr r3, [r7, #16] + 801508e: 68dc ldr r4, [r3, #12] + 8015090: 4610 mov r0, r2 + 8015092: f7f9 f8cd bl 800e230 + 8015096: 4603 mov r3, r0 + 8015098: 8023 strh r3, [r4, #0] + seg->tcphdr->dest = lwip_htons(pcb->remote_port); + 801509a: 68fb ldr r3, [r7, #12] + 801509c: 8b1a ldrh r2, [r3, #24] + 801509e: 693b ldr r3, [r7, #16] + 80150a0: 68dc ldr r4, [r3, #12] + 80150a2: 4610 mov r0, r2 + 80150a4: f7f9 f8c4 bl 800e230 + 80150a8: 4603 mov r3, r0 + 80150aa: 8063 strh r3, [r4, #2] + seg->tcphdr->seqno = lwip_htonl(seqno); + 80150ac: 693b ldr r3, [r7, #16] + 80150ae: 68dc ldr r4, [r3, #12] + 80150b0: 6838 ldr r0, [r7, #0] + 80150b2: f7f9 f8d2 bl 800e25a + 80150b6: 4603 mov r3, r0 + 80150b8: 6063 str r3, [r4, #4] + /* ackno is set in tcp_output */ + TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags); + 80150ba: 7dfb ldrb r3, [r7, #23] + 80150bc: 089b lsrs r3, r3, #2 + 80150be: b2db uxtb r3, r3 + 80150c0: b29b uxth r3, r3 + 80150c2: 3305 adds r3, #5 + 80150c4: b29b uxth r3, r3 + 80150c6: 031b lsls r3, r3, #12 + 80150c8: b29a uxth r2, r3 + 80150ca: 79fb ldrb r3, [r7, #7] + 80150cc: b29b uxth r3, r3 + 80150ce: 4313 orrs r3, r2 + 80150d0: b29a uxth r2, r3 + 80150d2: 693b ldr r3, [r7, #16] + 80150d4: 68dc ldr r4, [r3, #12] + 80150d6: 4610 mov r0, r2 + 80150d8: f7f9 f8aa bl 800e230 + 80150dc: 4603 mov r3, r0 + 80150de: 81a3 strh r3, [r4, #12] + /* wnd and chksum are set in tcp_output */ + seg->tcphdr->urgp = 0; + 80150e0: 693b ldr r3, [r7, #16] + 80150e2: 68db ldr r3, [r3, #12] + 80150e4: 2200 movs r2, #0 + 80150e6: 749a strb r2, [r3, #18] + 80150e8: 2200 movs r2, #0 + 80150ea: 74da strb r2, [r3, #19] + return seg; + 80150ec: 693b ldr r3, [r7, #16] +} + 80150ee: 4618 mov r0, r3 + 80150f0: 371c adds r7, #28 + 80150f2: 46bd mov sp, r7 + 80150f4: bd90 pop {r4, r7, pc} + 80150f6: bf00 nop + 80150f8: 08020108 .word 0x08020108 + 80150fc: 0802013c .word 0x0802013c + 8015100: 0802015c .word 0x0802015c + 8015104: 08020184 .word 0x08020184 + 8015108: 080201a8 .word 0x080201a8 + +0801510c : + * @param pcb the tcp_pcb for which to split the unsent head + * @param split the amount of payload to remain in the head + */ +err_t +tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split) +{ + 801510c: b590 push {r4, r7, lr} + 801510e: b08b sub sp, #44 ; 0x2c + 8015110: af02 add r7, sp, #8 + 8015112: 6078 str r0, [r7, #4] + 8015114: 460b mov r3, r1 + 8015116: 807b strh r3, [r7, #2] + struct tcp_seg *seg = NULL, *useg = NULL; + 8015118: 2300 movs r3, #0 + 801511a: 61fb str r3, [r7, #28] + 801511c: 2300 movs r3, #0 + 801511e: 617b str r3, [r7, #20] + struct pbuf *p = NULL; + 8015120: 2300 movs r3, #0 + 8015122: 613b str r3, [r7, #16] + u16_t chksum = 0; + u8_t chksum_swapped = 0; + struct pbuf *q; +#endif /* TCP_CHECKSUM_ON_COPY */ + + LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL); + 8015124: 687b ldr r3, [r7, #4] + 8015126: 2b00 cmp r3, #0 + 8015128: d106 bne.n 8015138 + 801512a: 4b95 ldr r3, [pc, #596] ; (8015380 ) + 801512c: f240 324b movw r2, #843 ; 0x34b + 8015130: 4994 ldr r1, [pc, #592] ; (8015384 ) + 8015132: 4895 ldr r0, [pc, #596] ; (8015388 ) + 8015134: f006 ff6e bl 801c014 + + useg = pcb->unsent; + 8015138: 687b ldr r3, [r7, #4] + 801513a: 6edb ldr r3, [r3, #108] ; 0x6c + 801513c: 617b str r3, [r7, #20] + if (useg == NULL) { + 801513e: 697b ldr r3, [r7, #20] + 8015140: 2b00 cmp r3, #0 + 8015142: d102 bne.n 801514a + return ERR_MEM; + 8015144: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8015148: e116 b.n 8015378 + } + + if (split == 0) { + 801514a: 887b ldrh r3, [r7, #2] + 801514c: 2b00 cmp r3, #0 + 801514e: d109 bne.n 8015164 + LWIP_ASSERT("Can't split segment into length 0", 0); + 8015150: 4b8b ldr r3, [pc, #556] ; (8015380 ) + 8015152: f240 3253 movw r2, #851 ; 0x353 + 8015156: 498d ldr r1, [pc, #564] ; (801538c ) + 8015158: 488b ldr r0, [pc, #556] ; (8015388 ) + 801515a: f006 ff5b bl 801c014 + return ERR_VAL; + 801515e: f06f 0305 mvn.w r3, #5 + 8015162: e109 b.n 8015378 + } + + if (useg->len <= split) { + 8015164: 697b ldr r3, [r7, #20] + 8015166: 891b ldrh r3, [r3, #8] + 8015168: 887a ldrh r2, [r7, #2] + 801516a: 429a cmp r2, r3 + 801516c: d301 bcc.n 8015172 + return ERR_OK; + 801516e: 2300 movs r3, #0 + 8015170: e102 b.n 8015378 + } + + LWIP_ASSERT("split <= mss", split <= pcb->mss); + 8015172: 687b ldr r3, [r7, #4] + 8015174: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8015176: 887a ldrh r2, [r7, #2] + 8015178: 429a cmp r2, r3 + 801517a: d906 bls.n 801518a + 801517c: 4b80 ldr r3, [pc, #512] ; (8015380 ) + 801517e: f240 325b movw r2, #859 ; 0x35b + 8015182: 4983 ldr r1, [pc, #524] ; (8015390 ) + 8015184: 4880 ldr r0, [pc, #512] ; (8015388 ) + 8015186: f006 ff45 bl 801c014 + LWIP_ASSERT("useg->len > 0", useg->len > 0); + 801518a: 697b ldr r3, [r7, #20] + 801518c: 891b ldrh r3, [r3, #8] + 801518e: 2b00 cmp r3, #0 + 8015190: d106 bne.n 80151a0 + 8015192: 4b7b ldr r3, [pc, #492] ; (8015380 ) + 8015194: f44f 7257 mov.w r2, #860 ; 0x35c + 8015198: 497e ldr r1, [pc, #504] ; (8015394 ) + 801519a: 487b ldr r0, [pc, #492] ; (8015388 ) + 801519c: f006 ff3a bl 801c014 + * to split this packet so we may actually exceed the max value by + * one! + */ + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen)); + + optflags = useg->flags; + 80151a0: 697b ldr r3, [r7, #20] + 80151a2: 7a9b ldrb r3, [r3, #10] + 80151a4: 73fb strb r3, [r7, #15] +#if TCP_CHECKSUM_ON_COPY + /* Remove since checksum is not stored until after tcp_create_segment() */ + optflags &= ~TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + optlen = LWIP_TCP_OPT_LENGTH(optflags); + 80151a6: 7bfb ldrb r3, [r7, #15] + 80151a8: 009b lsls r3, r3, #2 + 80151aa: b2db uxtb r3, r3 + 80151ac: f003 0304 and.w r3, r3, #4 + 80151b0: 73bb strb r3, [r7, #14] + remainder = useg->len - split; + 80151b2: 697b ldr r3, [r7, #20] + 80151b4: 891a ldrh r2, [r3, #8] + 80151b6: 887b ldrh r3, [r7, #2] + 80151b8: 1ad3 subs r3, r2, r3 + 80151ba: 81bb strh r3, [r7, #12] + + /* Create new pbuf for the remainder of the split */ + p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM); + 80151bc: 7bbb ldrb r3, [r7, #14] + 80151be: b29a uxth r2, r3 + 80151c0: 89bb ldrh r3, [r7, #12] + 80151c2: 4413 add r3, r2 + 80151c4: b29b uxth r3, r3 + 80151c6: f44f 7220 mov.w r2, #640 ; 0x280 + 80151ca: 4619 mov r1, r3 + 80151cc: 2036 movs r0, #54 ; 0x36 + 80151ce: f7fb f933 bl 8010438 + 80151d2: 6138 str r0, [r7, #16] + if (p == NULL) { + 80151d4: 693b ldr r3, [r7, #16] + 80151d6: 2b00 cmp r3, #0 + 80151d8: f000 80b7 beq.w 801534a + ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder)); + goto memerr; + } + + /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */ + offset = useg->p->tot_len - useg->len + split; + 80151dc: 697b ldr r3, [r7, #20] + 80151de: 685b ldr r3, [r3, #4] + 80151e0: 891a ldrh r2, [r3, #8] + 80151e2: 697b ldr r3, [r7, #20] + 80151e4: 891b ldrh r3, [r3, #8] + 80151e6: 1ad3 subs r3, r2, r3 + 80151e8: b29a uxth r2, r3 + 80151ea: 887b ldrh r3, [r7, #2] + 80151ec: 4413 add r3, r2 + 80151ee: 817b strh r3, [r7, #10] + /* Copy remainder into new pbuf, headers and options will not be filled out */ + if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) { + 80151f0: 697b ldr r3, [r7, #20] + 80151f2: 6858 ldr r0, [r3, #4] + 80151f4: 693b ldr r3, [r7, #16] + 80151f6: 685a ldr r2, [r3, #4] + 80151f8: 7bbb ldrb r3, [r7, #14] + 80151fa: 18d1 adds r1, r2, r3 + 80151fc: 897b ldrh r3, [r7, #10] + 80151fe: 89ba ldrh r2, [r7, #12] + 8015200: f7fb fe04 bl 8010e0c + 8015204: 4603 mov r3, r0 + 8015206: 461a mov r2, r3 + 8015208: 89bb ldrh r3, [r7, #12] + 801520a: 4293 cmp r3, r2 + 801520c: f040 809f bne.w 801534e +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Options are created when calling tcp_output() */ + + /* Migrate flags from original segment */ + split_flags = TCPH_FLAGS(useg->tcphdr); + 8015210: 697b ldr r3, [r7, #20] + 8015212: 68db ldr r3, [r3, #12] + 8015214: 899b ldrh r3, [r3, #12] + 8015216: b29b uxth r3, r3 + 8015218: 4618 mov r0, r3 + 801521a: f7f9 f809 bl 800e230 + 801521e: 4603 mov r3, r0 + 8015220: b2db uxtb r3, r3 + 8015222: f003 033f and.w r3, r3, #63 ; 0x3f + 8015226: 76fb strb r3, [r7, #27] + remainder_flags = 0; /* ACK added in tcp_output() */ + 8015228: 2300 movs r3, #0 + 801522a: 76bb strb r3, [r7, #26] + + if (split_flags & TCP_PSH) { + 801522c: 7efb ldrb r3, [r7, #27] + 801522e: f003 0308 and.w r3, r3, #8 + 8015232: 2b00 cmp r3, #0 + 8015234: d007 beq.n 8015246 + split_flags &= ~TCP_PSH; + 8015236: 7efb ldrb r3, [r7, #27] + 8015238: f023 0308 bic.w r3, r3, #8 + 801523c: 76fb strb r3, [r7, #27] + remainder_flags |= TCP_PSH; + 801523e: 7ebb ldrb r3, [r7, #26] + 8015240: f043 0308 orr.w r3, r3, #8 + 8015244: 76bb strb r3, [r7, #26] + } + if (split_flags & TCP_FIN) { + 8015246: 7efb ldrb r3, [r7, #27] + 8015248: f003 0301 and.w r3, r3, #1 + 801524c: 2b00 cmp r3, #0 + 801524e: d007 beq.n 8015260 + split_flags &= ~TCP_FIN; + 8015250: 7efb ldrb r3, [r7, #27] + 8015252: f023 0301 bic.w r3, r3, #1 + 8015256: 76fb strb r3, [r7, #27] + remainder_flags |= TCP_FIN; + 8015258: 7ebb ldrb r3, [r7, #26] + 801525a: f043 0301 orr.w r3, r3, #1 + 801525e: 76bb strb r3, [r7, #26] + } + /* SYN should be left on split, RST should not be present with data */ + + seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags); + 8015260: 697b ldr r3, [r7, #20] + 8015262: 68db ldr r3, [r3, #12] + 8015264: 685b ldr r3, [r3, #4] + 8015266: 4618 mov r0, r3 + 8015268: f7f8 fff7 bl 800e25a + 801526c: 4602 mov r2, r0 + 801526e: 887b ldrh r3, [r7, #2] + 8015270: 18d1 adds r1, r2, r3 + 8015272: 7eba ldrb r2, [r7, #26] + 8015274: 7bfb ldrb r3, [r7, #15] + 8015276: 9300 str r3, [sp, #0] + 8015278: 460b mov r3, r1 + 801527a: 6939 ldr r1, [r7, #16] + 801527c: 6878 ldr r0, [r7, #4] + 801527e: f7ff fea7 bl 8014fd0 + 8015282: 61f8 str r0, [r7, #28] + if (seg == NULL) { + 8015284: 69fb ldr r3, [r7, #28] + 8015286: 2b00 cmp r3, #0 + 8015288: d063 beq.n 8015352 + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Remove this segment from the queue since trimming it may free pbufs */ + pcb->snd_queuelen -= pbuf_clen(useg->p); + 801528a: 697b ldr r3, [r7, #20] + 801528c: 685b ldr r3, [r3, #4] + 801528e: 4618 mov r0, r3 + 8015290: f7fb fc44 bl 8010b1c + 8015294: 4603 mov r3, r0 + 8015296: 461a mov r2, r3 + 8015298: 687b ldr r3, [r7, #4] + 801529a: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 801529e: 1a9b subs r3, r3, r2 + 80152a0: b29a uxth r2, r3 + 80152a2: 687b ldr r3, [r7, #4] + 80152a4: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + + /* Trim the original pbuf into our split size. At this point our remainder segment must be setup + successfully because we are modifying the original segment */ + pbuf_realloc(useg->p, useg->p->tot_len - remainder); + 80152a8: 697b ldr r3, [r7, #20] + 80152aa: 6858 ldr r0, [r3, #4] + 80152ac: 697b ldr r3, [r7, #20] + 80152ae: 685b ldr r3, [r3, #4] + 80152b0: 891a ldrh r2, [r3, #8] + 80152b2: 89bb ldrh r3, [r7, #12] + 80152b4: 1ad3 subs r3, r2, r3 + 80152b6: b29b uxth r3, r3 + 80152b8: 4619 mov r1, r3 + 80152ba: f7fb fa1b bl 80106f4 + useg->len -= remainder; + 80152be: 697b ldr r3, [r7, #20] + 80152c0: 891a ldrh r2, [r3, #8] + 80152c2: 89bb ldrh r3, [r7, #12] + 80152c4: 1ad3 subs r3, r2, r3 + 80152c6: b29a uxth r2, r3 + 80152c8: 697b ldr r3, [r7, #20] + 80152ca: 811a strh r2, [r3, #8] + TCPH_SET_FLAG(useg->tcphdr, split_flags); + 80152cc: 697b ldr r3, [r7, #20] + 80152ce: 68db ldr r3, [r3, #12] + 80152d0: 899b ldrh r3, [r3, #12] + 80152d2: b29c uxth r4, r3 + 80152d4: 7efb ldrb r3, [r7, #27] + 80152d6: b29b uxth r3, r3 + 80152d8: 4618 mov r0, r3 + 80152da: f7f8 ffa9 bl 800e230 + 80152de: 4603 mov r3, r0 + 80152e0: 461a mov r2, r3 + 80152e2: 697b ldr r3, [r7, #20] + 80152e4: 68db ldr r3, [r3, #12] + 80152e6: 4322 orrs r2, r4 + 80152e8: b292 uxth r2, r2 + 80152ea: 819a strh r2, [r3, #12] + /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */ + useg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ + + /* Add back to the queue with new trimmed pbuf */ + pcb->snd_queuelen += pbuf_clen(useg->p); + 80152ec: 697b ldr r3, [r7, #20] + 80152ee: 685b ldr r3, [r3, #4] + 80152f0: 4618 mov r0, r3 + 80152f2: f7fb fc13 bl 8010b1c + 80152f6: 4603 mov r3, r0 + 80152f8: 461a mov r2, r3 + 80152fa: 687b ldr r3, [r7, #4] + 80152fc: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8015300: 4413 add r3, r2 + 8015302: b29a uxth r2, r3 + 8015304: 687b ldr r3, [r7, #4] + 8015306: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Update number of segments on the queues. Note that length now may + * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf + * because the total amount of data is constant when packet is split */ + pcb->snd_queuelen += pbuf_clen(seg->p); + 801530a: 69fb ldr r3, [r7, #28] + 801530c: 685b ldr r3, [r3, #4] + 801530e: 4618 mov r0, r3 + 8015310: f7fb fc04 bl 8010b1c + 8015314: 4603 mov r3, r0 + 8015316: 461a mov r2, r3 + 8015318: 687b ldr r3, [r7, #4] + 801531a: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 801531e: 4413 add r3, r2 + 8015320: b29a uxth r2, r3 + 8015322: 687b ldr r3, [r7, #4] + 8015324: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + + /* Finally insert remainder into queue after split (which stays head) */ + seg->next = useg->next; + 8015328: 697b ldr r3, [r7, #20] + 801532a: 681a ldr r2, [r3, #0] + 801532c: 69fb ldr r3, [r7, #28] + 801532e: 601a str r2, [r3, #0] + useg->next = seg; + 8015330: 697b ldr r3, [r7, #20] + 8015332: 69fa ldr r2, [r7, #28] + 8015334: 601a str r2, [r3, #0] + +#if TCP_OVERSIZE + /* If remainder is last segment on the unsent, ensure we clear the oversize amount + * because the remainder is always sized to the exact remaining amount */ + if (seg->next == NULL) { + 8015336: 69fb ldr r3, [r7, #28] + 8015338: 681b ldr r3, [r3, #0] + 801533a: 2b00 cmp r3, #0 + 801533c: d103 bne.n 8015346 + pcb->unsent_oversize = 0; + 801533e: 687b ldr r3, [r7, #4] + 8015340: 2200 movs r2, #0 + 8015342: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + } +#endif /* TCP_OVERSIZE */ + + return ERR_OK; + 8015346: 2300 movs r3, #0 + 8015348: e016 b.n 8015378 + goto memerr; + 801534a: bf00 nop + 801534c: e002 b.n 8015354 + goto memerr; + 801534e: bf00 nop + 8015350: e000 b.n 8015354 + goto memerr; + 8015352: bf00 nop +memerr: + TCP_STATS_INC(tcp.memerr); + + LWIP_ASSERT("seg == NULL", seg == NULL); + 8015354: 69fb ldr r3, [r7, #28] + 8015356: 2b00 cmp r3, #0 + 8015358: d006 beq.n 8015368 + 801535a: 4b09 ldr r3, [pc, #36] ; (8015380 ) + 801535c: f44f 7276 mov.w r2, #984 ; 0x3d8 + 8015360: 490d ldr r1, [pc, #52] ; (8015398 ) + 8015362: 4809 ldr r0, [pc, #36] ; (8015388 ) + 8015364: f006 fe56 bl 801c014 + if (p != NULL) { + 8015368: 693b ldr r3, [r7, #16] + 801536a: 2b00 cmp r3, #0 + 801536c: d002 beq.n 8015374 + pbuf_free(p); + 801536e: 6938 ldr r0, [r7, #16] + 8015370: f7fb fb46 bl 8010a00 + } + + return ERR_MEM; + 8015374: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 8015378: 4618 mov r0, r3 + 801537a: 3724 adds r7, #36 ; 0x24 + 801537c: 46bd mov sp, r7 + 801537e: bd90 pop {r4, r7, pc} + 8015380: 08020108 .word 0x08020108 + 8015384: 0802049c .word 0x0802049c + 8015388: 0802015c .word 0x0802015c + 801538c: 080204c0 .word 0x080204c0 + 8015390: 080204e4 .word 0x080204e4 + 8015394: 080204f4 .word 0x080204f4 + 8015398: 08020504 .word 0x08020504 + +0801539c : + * @param pcb the tcp_pcb over which to send a segment + * @return ERR_OK if sent, another err_t otherwise + */ +err_t +tcp_send_fin(struct tcp_pcb *pcb) +{ + 801539c: b590 push {r4, r7, lr} + 801539e: b085 sub sp, #20 + 80153a0: af00 add r7, sp, #0 + 80153a2: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL); + 80153a4: 687b ldr r3, [r7, #4] + 80153a6: 2b00 cmp r3, #0 + 80153a8: d106 bne.n 80153b8 + 80153aa: 4b21 ldr r3, [pc, #132] ; (8015430 ) + 80153ac: f240 32eb movw r2, #1003 ; 0x3eb + 80153b0: 4920 ldr r1, [pc, #128] ; (8015434 ) + 80153b2: 4821 ldr r0, [pc, #132] ; (8015438 ) + 80153b4: f006 fe2e bl 801c014 + + /* first, try to add the fin to the last unsent segment */ + if (pcb->unsent != NULL) { + 80153b8: 687b ldr r3, [r7, #4] + 80153ba: 6edb ldr r3, [r3, #108] ; 0x6c + 80153bc: 2b00 cmp r3, #0 + 80153be: d02e beq.n 801541e + struct tcp_seg *last_unsent; + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 80153c0: 687b ldr r3, [r7, #4] + 80153c2: 6edb ldr r3, [r3, #108] ; 0x6c + 80153c4: 60fb str r3, [r7, #12] + 80153c6: e002 b.n 80153ce + last_unsent = last_unsent->next); + 80153c8: 68fb ldr r3, [r7, #12] + 80153ca: 681b ldr r3, [r3, #0] + 80153cc: 60fb str r3, [r7, #12] + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 80153ce: 68fb ldr r3, [r7, #12] + 80153d0: 681b ldr r3, [r3, #0] + 80153d2: 2b00 cmp r3, #0 + 80153d4: d1f8 bne.n 80153c8 + + if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { + 80153d6: 68fb ldr r3, [r7, #12] + 80153d8: 68db ldr r3, [r3, #12] + 80153da: 899b ldrh r3, [r3, #12] + 80153dc: b29b uxth r3, r3 + 80153de: 4618 mov r0, r3 + 80153e0: f7f8 ff26 bl 800e230 + 80153e4: 4603 mov r3, r0 + 80153e6: b2db uxtb r3, r3 + 80153e8: f003 0307 and.w r3, r3, #7 + 80153ec: 2b00 cmp r3, #0 + 80153ee: d116 bne.n 801541e + /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ + TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); + 80153f0: 68fb ldr r3, [r7, #12] + 80153f2: 68db ldr r3, [r3, #12] + 80153f4: 899b ldrh r3, [r3, #12] + 80153f6: b29c uxth r4, r3 + 80153f8: 2001 movs r0, #1 + 80153fa: f7f8 ff19 bl 800e230 + 80153fe: 4603 mov r3, r0 + 8015400: 461a mov r2, r3 + 8015402: 68fb ldr r3, [r7, #12] + 8015404: 68db ldr r3, [r3, #12] + 8015406: 4322 orrs r2, r4 + 8015408: b292 uxth r2, r2 + 801540a: 819a strh r2, [r3, #12] + tcp_set_flags(pcb, TF_FIN); + 801540c: 687b ldr r3, [r7, #4] + 801540e: 8b5b ldrh r3, [r3, #26] + 8015410: f043 0320 orr.w r3, r3, #32 + 8015414: b29a uxth r2, r3 + 8015416: 687b ldr r3, [r7, #4] + 8015418: 835a strh r2, [r3, #26] + return ERR_OK; + 801541a: 2300 movs r3, #0 + 801541c: e004 b.n 8015428 + } + } + /* no data, no length, flags, copy=1, no optdata */ + return tcp_enqueue_flags(pcb, TCP_FIN); + 801541e: 2101 movs r1, #1 + 8015420: 6878 ldr r0, [r7, #4] + 8015422: f000 f80b bl 801543c + 8015426: 4603 mov r3, r0 +} + 8015428: 4618 mov r0, r3 + 801542a: 3714 adds r7, #20 + 801542c: 46bd mov sp, r7 + 801542e: bd90 pop {r4, r7, pc} + 8015430: 08020108 .word 0x08020108 + 8015434: 08020510 .word 0x08020510 + 8015438: 0802015c .word 0x0802015c + +0801543c : + * @param pcb Protocol control block for the TCP connection. + * @param flags TCP header flags to set in the outgoing segment. + */ +err_t +tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) +{ + 801543c: b580 push {r7, lr} + 801543e: b08a sub sp, #40 ; 0x28 + 8015440: af02 add r7, sp, #8 + 8015442: 6078 str r0, [r7, #4] + 8015444: 460b mov r3, r1 + 8015446: 70fb strb r3, [r7, #3] + struct pbuf *p; + struct tcp_seg *seg; + u8_t optflags = 0; + 8015448: 2300 movs r3, #0 + 801544a: 77fb strb r3, [r7, #31] + u8_t optlen = 0; + 801544c: 2300 movs r3, #0 + 801544e: 75fb strb r3, [r7, #23] + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", + 8015450: 78fb ldrb r3, [r7, #3] + 8015452: f003 0303 and.w r3, r3, #3 + 8015456: 2b00 cmp r3, #0 + 8015458: d106 bne.n 8015468 + 801545a: 4b67 ldr r3, [pc, #412] ; (80155f8 ) + 801545c: f240 4211 movw r2, #1041 ; 0x411 + 8015460: 4966 ldr r1, [pc, #408] ; (80155fc ) + 8015462: 4867 ldr r0, [pc, #412] ; (8015600 ) + 8015464: f006 fdd6 bl 801c014 + (flags & (TCP_SYN | TCP_FIN)) != 0); + LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL); + 8015468: 687b ldr r3, [r7, #4] + 801546a: 2b00 cmp r3, #0 + 801546c: d106 bne.n 801547c + 801546e: 4b62 ldr r3, [pc, #392] ; (80155f8 ) + 8015470: f240 4213 movw r2, #1043 ; 0x413 + 8015474: 4963 ldr r1, [pc, #396] ; (8015604 ) + 8015476: 4862 ldr r0, [pc, #392] ; (8015600 ) + 8015478: f006 fdcc bl 801c014 + + /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */ + + /* Get options for this segment. This is a special case since this is the + only place where a SYN can be sent. */ + if (flags & TCP_SYN) { + 801547c: 78fb ldrb r3, [r7, #3] + 801547e: f003 0302 and.w r3, r3, #2 + 8015482: 2b00 cmp r3, #0 + 8015484: d001 beq.n 801548a + optflags = TF_SEG_OPTS_MSS; + 8015486: 2301 movs r3, #1 + 8015488: 77fb strb r3, [r7, #31] + /* Make sure the timestamp option is only included in data segments if we + agreed about it with the remote host (and in active open SYN segments). */ + optflags |= TF_SEG_OPTS_TS; + } +#endif /* LWIP_TCP_TIMESTAMPS */ + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 801548a: 7ffb ldrb r3, [r7, #31] + 801548c: 009b lsls r3, r3, #2 + 801548e: b2db uxtb r3, r3 + 8015490: f003 0304 and.w r3, r3, #4 + 8015494: 75fb strb r3, [r7, #23] + + /* Allocate pbuf with room for TCP header + options */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + 8015496: 7dfb ldrb r3, [r7, #23] + 8015498: b29b uxth r3, r3 + 801549a: f44f 7220 mov.w r2, #640 ; 0x280 + 801549e: 4619 mov r1, r3 + 80154a0: 2036 movs r0, #54 ; 0x36 + 80154a2: f7fa ffc9 bl 8010438 + 80154a6: 6138 str r0, [r7, #16] + 80154a8: 693b ldr r3, [r7, #16] + 80154aa: 2b00 cmp r3, #0 + 80154ac: d109 bne.n 80154c2 + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 80154ae: 687b ldr r3, [r7, #4] + 80154b0: 8b5b ldrh r3, [r3, #26] + 80154b2: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80154b6: b29a uxth r2, r3 + 80154b8: 687b ldr r3, [r7, #4] + 80154ba: 835a strh r2, [r3, #26] + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + 80154bc: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80154c0: e095 b.n 80155ee + } + LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", + 80154c2: 693b ldr r3, [r7, #16] + 80154c4: 895a ldrh r2, [r3, #10] + 80154c6: 7dfb ldrb r3, [r7, #23] + 80154c8: b29b uxth r3, r3 + 80154ca: 429a cmp r2, r3 + 80154cc: d206 bcs.n 80154dc + 80154ce: 4b4a ldr r3, [pc, #296] ; (80155f8 ) + 80154d0: f240 4239 movw r2, #1081 ; 0x439 + 80154d4: 494c ldr r1, [pc, #304] ; (8015608 ) + 80154d6: 484a ldr r0, [pc, #296] ; (8015600 ) + 80154d8: f006 fd9c bl 801c014 + (p->len >= optlen)); + + /* Allocate memory for tcp_seg, and fill in fields. */ + if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { + 80154dc: 687b ldr r3, [r7, #4] + 80154de: 6dd9 ldr r1, [r3, #92] ; 0x5c + 80154e0: 78fa ldrb r2, [r7, #3] + 80154e2: 7ffb ldrb r3, [r7, #31] + 80154e4: 9300 str r3, [sp, #0] + 80154e6: 460b mov r3, r1 + 80154e8: 6939 ldr r1, [r7, #16] + 80154ea: 6878 ldr r0, [r7, #4] + 80154ec: f7ff fd70 bl 8014fd0 + 80154f0: 60f8 str r0, [r7, #12] + 80154f2: 68fb ldr r3, [r7, #12] + 80154f4: 2b00 cmp r3, #0 + 80154f6: d109 bne.n 801550c + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 80154f8: 687b ldr r3, [r7, #4] + 80154fa: 8b5b ldrh r3, [r3, #26] + 80154fc: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8015500: b29a uxth r2, r3 + 8015502: 687b ldr r3, [r7, #4] + 8015504: 835a strh r2, [r3, #26] + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + 8015506: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801550a: e070 b.n 80155ee + } + LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0); + 801550c: 68fb ldr r3, [r7, #12] + 801550e: 68db ldr r3, [r3, #12] + 8015510: f003 0303 and.w r3, r3, #3 + 8015514: 2b00 cmp r3, #0 + 8015516: d006 beq.n 8015526 + 8015518: 4b37 ldr r3, [pc, #220] ; (80155f8 ) + 801551a: f240 4242 movw r2, #1090 ; 0x442 + 801551e: 493b ldr r1, [pc, #236] ; (801560c ) + 8015520: 4837 ldr r0, [pc, #220] ; (8015600 ) + 8015522: f006 fd77 bl 801c014 + LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); + 8015526: 68fb ldr r3, [r7, #12] + 8015528: 891b ldrh r3, [r3, #8] + 801552a: 2b00 cmp r3, #0 + 801552c: d006 beq.n 801553c + 801552e: 4b32 ldr r3, [pc, #200] ; (80155f8 ) + 8015530: f240 4243 movw r2, #1091 ; 0x443 + 8015534: 4936 ldr r1, [pc, #216] ; (8015610 ) + 8015536: 4832 ldr r0, [pc, #200] ; (8015600 ) + 8015538: f006 fd6c bl 801c014 + lwip_ntohl(seg->tcphdr->seqno), + lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + /* Now append seg to pcb->unsent queue */ + if (pcb->unsent == NULL) { + 801553c: 687b ldr r3, [r7, #4] + 801553e: 6edb ldr r3, [r3, #108] ; 0x6c + 8015540: 2b00 cmp r3, #0 + 8015542: d103 bne.n 801554c + pcb->unsent = seg; + 8015544: 687b ldr r3, [r7, #4] + 8015546: 68fa ldr r2, [r7, #12] + 8015548: 66da str r2, [r3, #108] ; 0x6c + 801554a: e00d b.n 8015568 + } else { + struct tcp_seg *useg; + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + 801554c: 687b ldr r3, [r7, #4] + 801554e: 6edb ldr r3, [r3, #108] ; 0x6c + 8015550: 61bb str r3, [r7, #24] + 8015552: e002 b.n 801555a + 8015554: 69bb ldr r3, [r7, #24] + 8015556: 681b ldr r3, [r3, #0] + 8015558: 61bb str r3, [r7, #24] + 801555a: 69bb ldr r3, [r7, #24] + 801555c: 681b ldr r3, [r3, #0] + 801555e: 2b00 cmp r3, #0 + 8015560: d1f8 bne.n 8015554 + useg->next = seg; + 8015562: 69bb ldr r3, [r7, #24] + 8015564: 68fa ldr r2, [r7, #12] + 8015566: 601a str r2, [r3, #0] + } +#if TCP_OVERSIZE + /* The new unsent tail has no space */ + pcb->unsent_oversize = 0; + 8015568: 687b ldr r3, [r7, #4] + 801556a: 2200 movs r2, #0 + 801556c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +#endif /* TCP_OVERSIZE */ + + /* SYN and FIN bump the sequence number */ + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + 8015570: 78fb ldrb r3, [r7, #3] + 8015572: f003 0302 and.w r3, r3, #2 + 8015576: 2b00 cmp r3, #0 + 8015578: d104 bne.n 8015584 + 801557a: 78fb ldrb r3, [r7, #3] + 801557c: f003 0301 and.w r3, r3, #1 + 8015580: 2b00 cmp r3, #0 + 8015582: d004 beq.n 801558e + pcb->snd_lbb++; + 8015584: 687b ldr r3, [r7, #4] + 8015586: 6ddb ldr r3, [r3, #92] ; 0x5c + 8015588: 1c5a adds r2, r3, #1 + 801558a: 687b ldr r3, [r7, #4] + 801558c: 65da str r2, [r3, #92] ; 0x5c + /* optlen does not influence snd_buf */ + } + if (flags & TCP_FIN) { + 801558e: 78fb ldrb r3, [r7, #3] + 8015590: f003 0301 and.w r3, r3, #1 + 8015594: 2b00 cmp r3, #0 + 8015596: d006 beq.n 80155a6 + tcp_set_flags(pcb, TF_FIN); + 8015598: 687b ldr r3, [r7, #4] + 801559a: 8b5b ldrh r3, [r3, #26] + 801559c: f043 0320 orr.w r3, r3, #32 + 80155a0: b29a uxth r2, r3 + 80155a2: 687b ldr r3, [r7, #4] + 80155a4: 835a strh r2, [r3, #26] + } + + /* update number of segments on the queues */ + pcb->snd_queuelen += pbuf_clen(seg->p); + 80155a6: 68fb ldr r3, [r7, #12] + 80155a8: 685b ldr r3, [r3, #4] + 80155aa: 4618 mov r0, r3 + 80155ac: f7fb fab6 bl 8010b1c + 80155b0: 4603 mov r3, r0 + 80155b2: 461a mov r2, r3 + 80155b4: 687b ldr r3, [r7, #4] + 80155b6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 80155ba: 4413 add r3, r2 + 80155bc: b29a uxth r2, r3 + 80155be: 687b ldr r3, [r7, #4] + 80155c0: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + 80155c4: 687b ldr r3, [r7, #4] + 80155c6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 80155ca: 2b00 cmp r3, #0 + 80155cc: d00e beq.n 80155ec + LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", + 80155ce: 687b ldr r3, [r7, #4] + 80155d0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80155d2: 2b00 cmp r3, #0 + 80155d4: d10a bne.n 80155ec + 80155d6: 687b ldr r3, [r7, #4] + 80155d8: 6edb ldr r3, [r3, #108] ; 0x6c + 80155da: 2b00 cmp r3, #0 + 80155dc: d106 bne.n 80155ec + 80155de: 4b06 ldr r3, [pc, #24] ; (80155f8 ) + 80155e0: f240 4265 movw r2, #1125 ; 0x465 + 80155e4: 490b ldr r1, [pc, #44] ; (8015614 ) + 80155e6: 4806 ldr r0, [pc, #24] ; (8015600 ) + 80155e8: f006 fd14 bl 801c014 + pcb->unacked != NULL || pcb->unsent != NULL); + } + + return ERR_OK; + 80155ec: 2300 movs r3, #0 +} + 80155ee: 4618 mov r0, r3 + 80155f0: 3720 adds r7, #32 + 80155f2: 46bd mov sp, r7 + 80155f4: bd80 pop {r7, pc} + 80155f6: bf00 nop + 80155f8: 08020108 .word 0x08020108 + 80155fc: 0802052c .word 0x0802052c + 8015600: 0802015c .word 0x0802015c + 8015604: 08020584 .word 0x08020584 + 8015608: 080205a4 .word 0x080205a4 + 801560c: 080205e0 .word 0x080205e0 + 8015610: 080205f8 .word 0x080205f8 + 8015614: 08020624 .word 0x08020624 + +08015618 : + * @return ERR_OK if data has been sent or nothing to send + * another err_t on error + */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + 8015618: b5b0 push {r4, r5, r7, lr} + 801561a: b08a sub sp, #40 ; 0x28 + 801561c: af00 add r7, sp, #0 + 801561e: 6078 str r0, [r7, #4] + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL); + 8015620: 687b ldr r3, [r7, #4] + 8015622: 2b00 cmp r3, #0 + 8015624: d106 bne.n 8015634 + 8015626: 4b8a ldr r3, [pc, #552] ; (8015850 ) + 8015628: f240 42e1 movw r2, #1249 ; 0x4e1 + 801562c: 4989 ldr r1, [pc, #548] ; (8015854 ) + 801562e: 488a ldr r0, [pc, #552] ; (8015858 ) + 8015630: f006 fcf0 bl 801c014 + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_output for listen-pcbs", + 8015634: 687b ldr r3, [r7, #4] + 8015636: 7d1b ldrb r3, [r3, #20] + 8015638: 2b01 cmp r3, #1 + 801563a: d106 bne.n 801564a + 801563c: 4b84 ldr r3, [pc, #528] ; (8015850 ) + 801563e: f240 42e3 movw r2, #1251 ; 0x4e3 + 8015642: 4986 ldr r1, [pc, #536] ; (801585c ) + 8015644: 4884 ldr r0, [pc, #528] ; (8015858 ) + 8015646: f006 fce5 bl 801c014 + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + 801564a: 4b85 ldr r3, [pc, #532] ; (8015860 ) + 801564c: 681b ldr r3, [r3, #0] + 801564e: 687a ldr r2, [r7, #4] + 8015650: 429a cmp r2, r3 + 8015652: d101 bne.n 8015658 + return ERR_OK; + 8015654: 2300 movs r3, #0 + 8015656: e1ce b.n 80159f6 + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + 8015658: 687b ldr r3, [r7, #4] + 801565a: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 801565e: 687b ldr r3, [r7, #4] + 8015660: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8015664: 4293 cmp r3, r2 + 8015666: bf28 it cs + 8015668: 4613 movcs r3, r2 + 801566a: b29b uxth r3, r3 + 801566c: 61bb str r3, [r7, #24] + + seg = pcb->unsent; + 801566e: 687b ldr r3, [r7, #4] + 8015670: 6edb ldr r3, [r3, #108] ; 0x6c + 8015672: 627b str r3, [r7, #36] ; 0x24 + + if (seg == NULL) { + 8015674: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015676: 2b00 cmp r3, #0 + 8015678: d10b bne.n 8015692 + ", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); + + /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct + * an empty ACK segment and send it. */ + if (pcb->flags & TF_ACK_NOW) { + 801567a: 687b ldr r3, [r7, #4] + 801567c: 8b5b ldrh r3, [r3, #26] + 801567e: f003 0302 and.w r3, r3, #2 + 8015682: 2b00 cmp r3, #0 + 8015684: f000 81aa beq.w 80159dc + return tcp_send_empty_ack(pcb); + 8015688: 6878 ldr r0, [r7, #4] + 801568a: f000 fdcb bl 8016224 + 801568e: 4603 mov r3, r0 + 8015690: e1b1 b.n 80159f6 + pcb->snd_wnd, pcb->cwnd, wnd, + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack)); + } + + netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip); + 8015692: 6879 ldr r1, [r7, #4] + 8015694: 687b ldr r3, [r7, #4] + 8015696: 3304 adds r3, #4 + 8015698: 461a mov r2, r3 + 801569a: 6878 ldr r0, [r7, #4] + 801569c: f7ff fc7c bl 8014f98 + 80156a0: 6178 str r0, [r7, #20] + if (netif == NULL) { + 80156a2: 697b ldr r3, [r7, #20] + 80156a4: 2b00 cmp r3, #0 + 80156a6: d102 bne.n 80156ae + return ERR_RTE; + 80156a8: f06f 0303 mvn.w r3, #3 + 80156ac: e1a3 b.n 80159f6 + } + + /* If we don't have a local IP address, we get one from netif */ + if (ip_addr_isany(&pcb->local_ip)) { + 80156ae: 687b ldr r3, [r7, #4] + 80156b0: 2b00 cmp r3, #0 + 80156b2: d003 beq.n 80156bc + 80156b4: 687b ldr r3, [r7, #4] + 80156b6: 681b ldr r3, [r3, #0] + 80156b8: 2b00 cmp r3, #0 + 80156ba: d111 bne.n 80156e0 + const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip); + 80156bc: 697b ldr r3, [r7, #20] + 80156be: 2b00 cmp r3, #0 + 80156c0: d002 beq.n 80156c8 + 80156c2: 697b ldr r3, [r7, #20] + 80156c4: 3304 adds r3, #4 + 80156c6: e000 b.n 80156ca + 80156c8: 2300 movs r3, #0 + 80156ca: 613b str r3, [r7, #16] + if (local_ip == NULL) { + 80156cc: 693b ldr r3, [r7, #16] + 80156ce: 2b00 cmp r3, #0 + 80156d0: d102 bne.n 80156d8 + return ERR_RTE; + 80156d2: f06f 0303 mvn.w r3, #3 + 80156d6: e18e b.n 80159f6 + } + ip_addr_copy(pcb->local_ip, *local_ip); + 80156d8: 693b ldr r3, [r7, #16] + 80156da: 681a ldr r2, [r3, #0] + 80156dc: 687b ldr r3, [r7, #4] + 80156de: 601a str r2, [r3, #0] + } + + /* Handle the current segment not fitting within the window */ + if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) { + 80156e0: 6a7b ldr r3, [r7, #36] ; 0x24 + 80156e2: 68db ldr r3, [r3, #12] + 80156e4: 685b ldr r3, [r3, #4] + 80156e6: 4618 mov r0, r3 + 80156e8: f7f8 fdb7 bl 800e25a + 80156ec: 4602 mov r2, r0 + 80156ee: 687b ldr r3, [r7, #4] + 80156f0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80156f2: 1ad3 subs r3, r2, r3 + 80156f4: 6a7a ldr r2, [r7, #36] ; 0x24 + 80156f6: 8912 ldrh r2, [r2, #8] + 80156f8: 4413 add r3, r2 + 80156fa: 69ba ldr r2, [r7, #24] + 80156fc: 429a cmp r2, r3 + 80156fe: d227 bcs.n 8015750 + * within the remaining (could be 0) send window and RTO timer is not running (we + * have no in-flight data). If window is still too small after persist timer fires, + * then we split the segment. We don't consider the congestion window since a cwnd + * smaller than 1 SMSS implies in-flight data + */ + if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) { + 8015700: 687b ldr r3, [r7, #4] + 8015702: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8015706: 461a mov r2, r3 + 8015708: 69bb ldr r3, [r7, #24] + 801570a: 4293 cmp r3, r2 + 801570c: d114 bne.n 8015738 + 801570e: 687b ldr r3, [r7, #4] + 8015710: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015712: 2b00 cmp r3, #0 + 8015714: d110 bne.n 8015738 + 8015716: 687b ldr r3, [r7, #4] + 8015718: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 801571c: 2b00 cmp r3, #0 + 801571e: d10b bne.n 8015738 + pcb->persist_cnt = 0; + 8015720: 687b ldr r3, [r7, #4] + 8015722: 2200 movs r2, #0 + 8015724: f883 2098 strb.w r2, [r3, #152] ; 0x98 + pcb->persist_backoff = 1; + 8015728: 687b ldr r3, [r7, #4] + 801572a: 2201 movs r2, #1 + 801572c: f883 2099 strb.w r2, [r3, #153] ; 0x99 + pcb->persist_probe = 0; + 8015730: 687b ldr r3, [r7, #4] + 8015732: 2200 movs r2, #0 + 8015734: f883 209a strb.w r2, [r3, #154] ; 0x9a + } + /* We need an ACK, but can't send data now, so send an empty ACK */ + if (pcb->flags & TF_ACK_NOW) { + 8015738: 687b ldr r3, [r7, #4] + 801573a: 8b5b ldrh r3, [r3, #26] + 801573c: f003 0302 and.w r3, r3, #2 + 8015740: 2b00 cmp r3, #0 + 8015742: f000 814d beq.w 80159e0 + return tcp_send_empty_ack(pcb); + 8015746: 6878 ldr r0, [r7, #4] + 8015748: f000 fd6c bl 8016224 + 801574c: 4603 mov r3, r0 + 801574e: e152 b.n 80159f6 + } + goto output_done; + } + /* Stop persist timer, above conditions are not active */ + pcb->persist_backoff = 0; + 8015750: 687b ldr r3, [r7, #4] + 8015752: 2200 movs r2, #0 + 8015754: f883 2099 strb.w r2, [r3, #153] ; 0x99 + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + 8015758: 687b ldr r3, [r7, #4] + 801575a: 6f1b ldr r3, [r3, #112] ; 0x70 + 801575c: 623b str r3, [r7, #32] + if (useg != NULL) { + 801575e: 6a3b ldr r3, [r7, #32] + 8015760: 2b00 cmp r3, #0 + 8015762: f000 811c beq.w 801599e + for (; useg->next != NULL; useg = useg->next); + 8015766: e002 b.n 801576e + 8015768: 6a3b ldr r3, [r7, #32] + 801576a: 681b ldr r3, [r3, #0] + 801576c: 623b str r3, [r7, #32] + 801576e: 6a3b ldr r3, [r7, #32] + 8015770: 681b ldr r3, [r3, #0] + 8015772: 2b00 cmp r3, #0 + 8015774: d1f8 bne.n 8015768 + } + /* data available and window allows it to be sent? */ + while (seg != NULL && + 8015776: e112 b.n 801599e + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + LWIP_ASSERT("RST not expected here!", + 8015778: 6a7b ldr r3, [r7, #36] ; 0x24 + 801577a: 68db ldr r3, [r3, #12] + 801577c: 899b ldrh r3, [r3, #12] + 801577e: b29b uxth r3, r3 + 8015780: 4618 mov r0, r3 + 8015782: f7f8 fd55 bl 800e230 + 8015786: 4603 mov r3, r0 + 8015788: b2db uxtb r3, r3 + 801578a: f003 0304 and.w r3, r3, #4 + 801578e: 2b00 cmp r3, #0 + 8015790: d006 beq.n 80157a0 + 8015792: 4b2f ldr r3, [pc, #188] ; (8015850 ) + 8015794: f240 5236 movw r2, #1334 ; 0x536 + 8015798: 4932 ldr r1, [pc, #200] ; (8015864 ) + 801579a: 482f ldr r0, [pc, #188] ; (8015858 ) + 801579c: f006 fc3a bl 801c014 + * - if tcp_write had a memory error before (prevent delayed ACK timeout) or + * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - + * either seg->next != NULL or pcb->unacked == NULL; + * RST is no sent using tcp_write/tcp_output. + */ + if ((tcp_do_output_nagle(pcb) == 0) && + 80157a0: 687b ldr r3, [r7, #4] + 80157a2: 6f1b ldr r3, [r3, #112] ; 0x70 + 80157a4: 2b00 cmp r3, #0 + 80157a6: d01f beq.n 80157e8 + 80157a8: 687b ldr r3, [r7, #4] + 80157aa: 8b5b ldrh r3, [r3, #26] + 80157ac: f003 0344 and.w r3, r3, #68 ; 0x44 + 80157b0: 2b00 cmp r3, #0 + 80157b2: d119 bne.n 80157e8 + 80157b4: 687b ldr r3, [r7, #4] + 80157b6: 6edb ldr r3, [r3, #108] ; 0x6c + 80157b8: 2b00 cmp r3, #0 + 80157ba: d00b beq.n 80157d4 + 80157bc: 687b ldr r3, [r7, #4] + 80157be: 6edb ldr r3, [r3, #108] ; 0x6c + 80157c0: 681b ldr r3, [r3, #0] + 80157c2: 2b00 cmp r3, #0 + 80157c4: d110 bne.n 80157e8 + 80157c6: 687b ldr r3, [r7, #4] + 80157c8: 6edb ldr r3, [r3, #108] ; 0x6c + 80157ca: 891a ldrh r2, [r3, #8] + 80157cc: 687b ldr r3, [r7, #4] + 80157ce: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80157d0: 429a cmp r2, r3 + 80157d2: d209 bcs.n 80157e8 + 80157d4: 687b ldr r3, [r7, #4] + 80157d6: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 + 80157da: 2b00 cmp r3, #0 + 80157dc: d004 beq.n 80157e8 + 80157de: 687b ldr r3, [r7, #4] + 80157e0: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 80157e4: 2b08 cmp r3, #8 + 80157e6: d901 bls.n 80157ec + 80157e8: 2301 movs r3, #1 + 80157ea: e000 b.n 80157ee + 80157ec: 2300 movs r3, #0 + 80157ee: 2b00 cmp r3, #0 + 80157f0: d106 bne.n 8015800 + ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) { + 80157f2: 687b ldr r3, [r7, #4] + 80157f4: 8b5b ldrh r3, [r3, #26] + 80157f6: f003 03a0 and.w r3, r3, #160 ; 0xa0 + if ((tcp_do_output_nagle(pcb) == 0) && + 80157fa: 2b00 cmp r3, #0 + 80157fc: f000 80e4 beq.w 80159c8 + pcb->lastack, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + if (pcb->state != SYN_SENT) { + 8015800: 687b ldr r3, [r7, #4] + 8015802: 7d1b ldrb r3, [r3, #20] + 8015804: 2b02 cmp r3, #2 + 8015806: d00d beq.n 8015824 + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + 8015808: 6a7b ldr r3, [r7, #36] ; 0x24 + 801580a: 68db ldr r3, [r3, #12] + 801580c: 899b ldrh r3, [r3, #12] + 801580e: b29c uxth r4, r3 + 8015810: 2010 movs r0, #16 + 8015812: f7f8 fd0d bl 800e230 + 8015816: 4603 mov r3, r0 + 8015818: 461a mov r2, r3 + 801581a: 6a7b ldr r3, [r7, #36] ; 0x24 + 801581c: 68db ldr r3, [r3, #12] + 801581e: 4322 orrs r2, r4 + 8015820: b292 uxth r2, r2 + 8015822: 819a strh r2, [r3, #12] + } + + err = tcp_output_segment(seg, pcb, netif); + 8015824: 697a ldr r2, [r7, #20] + 8015826: 6879 ldr r1, [r7, #4] + 8015828: 6a78 ldr r0, [r7, #36] ; 0x24 + 801582a: f000 f909 bl 8015a40 + 801582e: 4603 mov r3, r0 + 8015830: 73fb strb r3, [r7, #15] + if (err != ERR_OK) { + 8015832: f997 300f ldrsb.w r3, [r7, #15] + 8015836: 2b00 cmp r3, #0 + 8015838: d016 beq.n 8015868 + /* segment could not be sent, for whatever reason */ + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 801583a: 687b ldr r3, [r7, #4] + 801583c: 8b5b ldrh r3, [r3, #26] + 801583e: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8015842: b29a uxth r2, r3 + 8015844: 687b ldr r3, [r7, #4] + 8015846: 835a strh r2, [r3, #26] + return err; + 8015848: f997 300f ldrsb.w r3, [r7, #15] + 801584c: e0d3 b.n 80159f6 + 801584e: bf00 nop + 8015850: 08020108 .word 0x08020108 + 8015854: 0802064c .word 0x0802064c + 8015858: 0802015c .word 0x0802015c + 801585c: 08020664 .word 0x08020664 + 8015860: 2000cf7c .word 0x2000cf7c + 8015864: 0802068c .word 0x0802068c + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ + pcb->unsent = seg->next; + 8015868: 6a7b ldr r3, [r7, #36] ; 0x24 + 801586a: 681a ldr r2, [r3, #0] + 801586c: 687b ldr r3, [r7, #4] + 801586e: 66da str r2, [r3, #108] ; 0x6c + if (pcb->state != SYN_SENT) { + 8015870: 687b ldr r3, [r7, #4] + 8015872: 7d1b ldrb r3, [r3, #20] + 8015874: 2b02 cmp r3, #2 + 8015876: d006 beq.n 8015886 + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 8015878: 687b ldr r3, [r7, #4] + 801587a: 8b5b ldrh r3, [r3, #26] + 801587c: f023 0303 bic.w r3, r3, #3 + 8015880: b29a uxth r2, r3 + 8015882: 687b ldr r3, [r7, #4] + 8015884: 835a strh r2, [r3, #26] + } + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + 8015886: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015888: 68db ldr r3, [r3, #12] + 801588a: 685b ldr r3, [r3, #4] + 801588c: 4618 mov r0, r3 + 801588e: f7f8 fce4 bl 800e25a + 8015892: 4604 mov r4, r0 + 8015894: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015896: 891b ldrh r3, [r3, #8] + 8015898: 461d mov r5, r3 + 801589a: 6a7b ldr r3, [r7, #36] ; 0x24 + 801589c: 68db ldr r3, [r3, #12] + 801589e: 899b ldrh r3, [r3, #12] + 80158a0: b29b uxth r3, r3 + 80158a2: 4618 mov r0, r3 + 80158a4: f7f8 fcc4 bl 800e230 + 80158a8: 4603 mov r3, r0 + 80158aa: b2db uxtb r3, r3 + 80158ac: f003 0303 and.w r3, r3, #3 + 80158b0: 2b00 cmp r3, #0 + 80158b2: d001 beq.n 80158b8 + 80158b4: 2301 movs r3, #1 + 80158b6: e000 b.n 80158ba + 80158b8: 2300 movs r3, #0 + 80158ba: 442b add r3, r5 + 80158bc: 4423 add r3, r4 + 80158be: 60bb str r3, [r7, #8] + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + 80158c0: 687b ldr r3, [r7, #4] + 80158c2: 6d1a ldr r2, [r3, #80] ; 0x50 + 80158c4: 68bb ldr r3, [r7, #8] + 80158c6: 1ad3 subs r3, r2, r3 + 80158c8: 2b00 cmp r3, #0 + 80158ca: da02 bge.n 80158d2 + pcb->snd_nxt = snd_nxt; + 80158cc: 687b ldr r3, [r7, #4] + 80158ce: 68ba ldr r2, [r7, #8] + 80158d0: 651a str r2, [r3, #80] ; 0x50 + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + 80158d2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80158d4: 891b ldrh r3, [r3, #8] + 80158d6: 461c mov r4, r3 + 80158d8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80158da: 68db ldr r3, [r3, #12] + 80158dc: 899b ldrh r3, [r3, #12] + 80158de: b29b uxth r3, r3 + 80158e0: 4618 mov r0, r3 + 80158e2: f7f8 fca5 bl 800e230 + 80158e6: 4603 mov r3, r0 + 80158e8: b2db uxtb r3, r3 + 80158ea: f003 0303 and.w r3, r3, #3 + 80158ee: 2b00 cmp r3, #0 + 80158f0: d001 beq.n 80158f6 + 80158f2: 2301 movs r3, #1 + 80158f4: e000 b.n 80158f8 + 80158f6: 2300 movs r3, #0 + 80158f8: 4423 add r3, r4 + 80158fa: 2b00 cmp r3, #0 + 80158fc: d049 beq.n 8015992 + seg->next = NULL; + 80158fe: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015900: 2200 movs r2, #0 + 8015902: 601a str r2, [r3, #0] + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + 8015904: 687b ldr r3, [r7, #4] + 8015906: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015908: 2b00 cmp r3, #0 + 801590a: d105 bne.n 8015918 + pcb->unacked = seg; + 801590c: 687b ldr r3, [r7, #4] + 801590e: 6a7a ldr r2, [r7, #36] ; 0x24 + 8015910: 671a str r2, [r3, #112] ; 0x70 + useg = seg; + 8015912: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015914: 623b str r3, [r7, #32] + 8015916: e03f b.n 8015998 + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather somewhere before it. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) { + 8015918: 6a7b ldr r3, [r7, #36] ; 0x24 + 801591a: 68db ldr r3, [r3, #12] + 801591c: 685b ldr r3, [r3, #4] + 801591e: 4618 mov r0, r3 + 8015920: f7f8 fc9b bl 800e25a + 8015924: 4604 mov r4, r0 + 8015926: 6a3b ldr r3, [r7, #32] + 8015928: 68db ldr r3, [r3, #12] + 801592a: 685b ldr r3, [r3, #4] + 801592c: 4618 mov r0, r3 + 801592e: f7f8 fc94 bl 800e25a + 8015932: 4603 mov r3, r0 + 8015934: 1ae3 subs r3, r4, r3 + 8015936: 2b00 cmp r3, #0 + 8015938: da24 bge.n 8015984 + /* add segment to before tail of unacked list, keeping the list sorted */ + struct tcp_seg **cur_seg = &(pcb->unacked); + 801593a: 687b ldr r3, [r7, #4] + 801593c: 3370 adds r3, #112 ; 0x70 + 801593e: 61fb str r3, [r7, #28] + while (*cur_seg && + 8015940: e002 b.n 8015948 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + 8015942: 69fb ldr r3, [r7, #28] + 8015944: 681b ldr r3, [r3, #0] + 8015946: 61fb str r3, [r7, #28] + while (*cur_seg && + 8015948: 69fb ldr r3, [r7, #28] + 801594a: 681b ldr r3, [r3, #0] + 801594c: 2b00 cmp r3, #0 + 801594e: d011 beq.n 8015974 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + 8015950: 69fb ldr r3, [r7, #28] + 8015952: 681b ldr r3, [r3, #0] + 8015954: 68db ldr r3, [r3, #12] + 8015956: 685b ldr r3, [r3, #4] + 8015958: 4618 mov r0, r3 + 801595a: f7f8 fc7e bl 800e25a + 801595e: 4604 mov r4, r0 + 8015960: 6a7b ldr r3, [r7, #36] ; 0x24 + 8015962: 68db ldr r3, [r3, #12] + 8015964: 685b ldr r3, [r3, #4] + 8015966: 4618 mov r0, r3 + 8015968: f7f8 fc77 bl 800e25a + 801596c: 4603 mov r3, r0 + 801596e: 1ae3 subs r3, r4, r3 + while (*cur_seg && + 8015970: 2b00 cmp r3, #0 + 8015972: dbe6 blt.n 8015942 + } + seg->next = (*cur_seg); + 8015974: 69fb ldr r3, [r7, #28] + 8015976: 681a ldr r2, [r3, #0] + 8015978: 6a7b ldr r3, [r7, #36] ; 0x24 + 801597a: 601a str r2, [r3, #0] + (*cur_seg) = seg; + 801597c: 69fb ldr r3, [r7, #28] + 801597e: 6a7a ldr r2, [r7, #36] ; 0x24 + 8015980: 601a str r2, [r3, #0] + 8015982: e009 b.n 8015998 + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + 8015984: 6a3b ldr r3, [r7, #32] + 8015986: 6a7a ldr r2, [r7, #36] ; 0x24 + 8015988: 601a str r2, [r3, #0] + useg = useg->next; + 801598a: 6a3b ldr r3, [r7, #32] + 801598c: 681b ldr r3, [r3, #0] + 801598e: 623b str r3, [r7, #32] + 8015990: e002 b.n 8015998 + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + 8015992: 6a78 ldr r0, [r7, #36] ; 0x24 + 8015994: f7fc fc3f bl 8012216 + } + seg = pcb->unsent; + 8015998: 687b ldr r3, [r7, #4] + 801599a: 6edb ldr r3, [r3, #108] ; 0x6c + 801599c: 627b str r3, [r7, #36] ; 0x24 + while (seg != NULL && + 801599e: 6a7b ldr r3, [r7, #36] ; 0x24 + 80159a0: 2b00 cmp r3, #0 + 80159a2: d012 beq.n 80159ca + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + 80159a4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80159a6: 68db ldr r3, [r3, #12] + 80159a8: 685b ldr r3, [r3, #4] + 80159aa: 4618 mov r0, r3 + 80159ac: f7f8 fc55 bl 800e25a + 80159b0: 4602 mov r2, r0 + 80159b2: 687b ldr r3, [r7, #4] + 80159b4: 6c5b ldr r3, [r3, #68] ; 0x44 + 80159b6: 1ad3 subs r3, r2, r3 + 80159b8: 6a7a ldr r2, [r7, #36] ; 0x24 + 80159ba: 8912 ldrh r2, [r2, #8] + 80159bc: 4413 add r3, r2 + while (seg != NULL && + 80159be: 69ba ldr r2, [r7, #24] + 80159c0: 429a cmp r2, r3 + 80159c2: f4bf aed9 bcs.w 8015778 + 80159c6: e000 b.n 80159ca + break; + 80159c8: bf00 nop + } +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + 80159ca: 687b ldr r3, [r7, #4] + 80159cc: 6edb ldr r3, [r3, #108] ; 0x6c + 80159ce: 2b00 cmp r3, #0 + 80159d0: d108 bne.n 80159e4 + /* last unsent has been removed, reset unsent_oversize */ + pcb->unsent_oversize = 0; + 80159d2: 687b ldr r3, [r7, #4] + 80159d4: 2200 movs r2, #0 + 80159d6: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + 80159da: e004 b.n 80159e6 + goto output_done; + 80159dc: bf00 nop + 80159de: e002 b.n 80159e6 + goto output_done; + 80159e0: bf00 nop + 80159e2: e000 b.n 80159e6 + } +#endif /* TCP_OVERSIZE */ + +output_done: + 80159e4: bf00 nop + tcp_clear_flags(pcb, TF_NAGLEMEMERR); + 80159e6: 687b ldr r3, [r7, #4] + 80159e8: 8b5b ldrh r3, [r3, #26] + 80159ea: f023 0380 bic.w r3, r3, #128 ; 0x80 + 80159ee: b29a uxth r2, r3 + 80159f0: 687b ldr r3, [r7, #4] + 80159f2: 835a strh r2, [r3, #26] + return ERR_OK; + 80159f4: 2300 movs r3, #0 +} + 80159f6: 4618 mov r0, r3 + 80159f8: 3728 adds r7, #40 ; 0x28 + 80159fa: 46bd mov sp, r7 + 80159fc: bdb0 pop {r4, r5, r7, pc} + 80159fe: bf00 nop + +08015a00 : + * @arg seg the tcp segment to check + * @return 1 if ref != 1, 0 if ref == 1 + */ +static int +tcp_output_segment_busy(const struct tcp_seg *seg) +{ + 8015a00: b580 push {r7, lr} + 8015a02: b082 sub sp, #8 + 8015a04: af00 add r7, sp, #0 + 8015a06: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL); + 8015a08: 687b ldr r3, [r7, #4] + 8015a0a: 2b00 cmp r3, #0 + 8015a0c: d106 bne.n 8015a1c + 8015a0e: 4b09 ldr r3, [pc, #36] ; (8015a34 ) + 8015a10: f240 529a movw r2, #1434 ; 0x59a + 8015a14: 4908 ldr r1, [pc, #32] ; (8015a38 ) + 8015a16: 4809 ldr r0, [pc, #36] ; (8015a3c ) + 8015a18: f006 fafc bl 801c014 + + /* We only need to check the first pbuf here: + If a pbuf is queued for transmission, a driver calls pbuf_ref(), + which only changes the ref count of the first pbuf */ + if (seg->p->ref != 1) { + 8015a1c: 687b ldr r3, [r7, #4] + 8015a1e: 685b ldr r3, [r3, #4] + 8015a20: 7b9b ldrb r3, [r3, #14] + 8015a22: 2b01 cmp r3, #1 + 8015a24: d001 beq.n 8015a2a + /* other reference found */ + return 1; + 8015a26: 2301 movs r3, #1 + 8015a28: e000 b.n 8015a2c + } + /* no other references found */ + return 0; + 8015a2a: 2300 movs r3, #0 +} + 8015a2c: 4618 mov r0, r3 + 8015a2e: 3708 adds r7, #8 + 8015a30: 46bd mov sp, r7 + 8015a32: bd80 pop {r7, pc} + 8015a34: 08020108 .word 0x08020108 + 8015a38: 080206a4 .word 0x080206a4 + 8015a3c: 0802015c .word 0x0802015c + +08015a40 : + * @param pcb the tcp_pcb for the TCP connection used to send the segment + * @param netif the netif used to send the segment + */ +static err_t +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif) +{ + 8015a40: b5b0 push {r4, r5, r7, lr} + 8015a42: b08c sub sp, #48 ; 0x30 + 8015a44: af04 add r7, sp, #16 + 8015a46: 60f8 str r0, [r7, #12] + 8015a48: 60b9 str r1, [r7, #8] + 8015a4a: 607a str r2, [r7, #4] + u32_t *opts; +#if TCP_CHECKSUM_ON_COPY + int seg_chksum_was_swapped = 0; +#endif + + LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL); + 8015a4c: 68fb ldr r3, [r7, #12] + 8015a4e: 2b00 cmp r3, #0 + 8015a50: d106 bne.n 8015a60 + 8015a52: 4b63 ldr r3, [pc, #396] ; (8015be0 ) + 8015a54: f44f 62b7 mov.w r2, #1464 ; 0x5b8 + 8015a58: 4962 ldr r1, [pc, #392] ; (8015be4 ) + 8015a5a: 4863 ldr r0, [pc, #396] ; (8015be8 ) + 8015a5c: f006 fada bl 801c014 + LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL); + 8015a60: 68bb ldr r3, [r7, #8] + 8015a62: 2b00 cmp r3, #0 + 8015a64: d106 bne.n 8015a74 + 8015a66: 4b5e ldr r3, [pc, #376] ; (8015be0 ) + 8015a68: f240 52b9 movw r2, #1465 ; 0x5b9 + 8015a6c: 495f ldr r1, [pc, #380] ; (8015bec ) + 8015a6e: 485e ldr r0, [pc, #376] ; (8015be8 ) + 8015a70: f006 fad0 bl 801c014 + LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL); + 8015a74: 687b ldr r3, [r7, #4] + 8015a76: 2b00 cmp r3, #0 + 8015a78: d106 bne.n 8015a88 + 8015a7a: 4b59 ldr r3, [pc, #356] ; (8015be0 ) + 8015a7c: f240 52ba movw r2, #1466 ; 0x5ba + 8015a80: 495b ldr r1, [pc, #364] ; (8015bf0 ) + 8015a82: 4859 ldr r0, [pc, #356] ; (8015be8 ) + 8015a84: f006 fac6 bl 801c014 + + if (tcp_output_segment_busy(seg)) { + 8015a88: 68f8 ldr r0, [r7, #12] + 8015a8a: f7ff ffb9 bl 8015a00 + 8015a8e: 4603 mov r3, r0 + 8015a90: 2b00 cmp r3, #0 + 8015a92: d001 beq.n 8015a98 + /* This should not happen: rexmit functions should have checked this. + However, since this function modifies p->len, we must not continue in this case. */ + LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n")); + return ERR_OK; + 8015a94: 2300 movs r3, #0 + 8015a96: e09f b.n 8015bd8 + } + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); + 8015a98: 68bb ldr r3, [r7, #8] + 8015a9a: 6a5a ldr r2, [r3, #36] ; 0x24 + 8015a9c: 68fb ldr r3, [r7, #12] + 8015a9e: 68dc ldr r4, [r3, #12] + 8015aa0: 4610 mov r0, r2 + 8015aa2: f7f8 fbda bl 800e25a + 8015aa6: 4603 mov r3, r0 + 8015aa8: 60a3 str r3, [r4, #8] + the window scale option) is never scaled. */ + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd)); + } else +#endif /* LWIP_WND_SCALE */ + { + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + 8015aaa: 68bb ldr r3, [r7, #8] + 8015aac: 8d5a ldrh r2, [r3, #42] ; 0x2a + 8015aae: 68fb ldr r3, [r7, #12] + 8015ab0: 68dc ldr r4, [r3, #12] + 8015ab2: 4610 mov r0, r2 + 8015ab4: f7f8 fbbc bl 800e230 + 8015ab8: 4603 mov r3, r0 + 8015aba: 81e3 strh r3, [r4, #14] + } + + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + 8015abc: 68bb ldr r3, [r7, #8] + 8015abe: 6a5b ldr r3, [r3, #36] ; 0x24 + 8015ac0: 68ba ldr r2, [r7, #8] + 8015ac2: 8d52 ldrh r2, [r2, #42] ; 0x2a + 8015ac4: 441a add r2, r3 + 8015ac6: 68bb ldr r3, [r7, #8] + 8015ac8: 62da str r2, [r3, #44] ; 0x2c + + /* Add any requested options. NB MSS option is only set on SYN + packets, so ignore it here */ + /* cast through void* to get rid of alignment warnings */ + opts = (u32_t *)(void *)(seg->tcphdr + 1); + 8015aca: 68fb ldr r3, [r7, #12] + 8015acc: 68db ldr r3, [r3, #12] + 8015ace: 3314 adds r3, #20 + 8015ad0: 61fb str r3, [r7, #28] + if (seg->flags & TF_SEG_OPTS_MSS) { + 8015ad2: 68fb ldr r3, [r7, #12] + 8015ad4: 7a9b ldrb r3, [r3, #10] + 8015ad6: f003 0301 and.w r3, r3, #1 + 8015ada: 2b00 cmp r3, #0 + 8015adc: d015 beq.n 8015b0a + u16_t mss; +#if TCP_CALCULATE_EFF_SEND_MSS + mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip); + 8015ade: 68bb ldr r3, [r7, #8] + 8015ae0: 3304 adds r3, #4 + 8015ae2: 461a mov r2, r3 + 8015ae4: 6879 ldr r1, [r7, #4] + 8015ae6: f44f 7006 mov.w r0, #536 ; 0x218 + 8015aea: f7fc fe8b bl 8012804 + 8015aee: 4603 mov r3, r0 + 8015af0: 837b strh r3, [r7, #26] +#else /* TCP_CALCULATE_EFF_SEND_MSS */ + mss = TCP_MSS; +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + *opts = TCP_BUILD_MSS_OPTION(mss); + 8015af2: 8b7b ldrh r3, [r7, #26] + 8015af4: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000 + 8015af8: 4618 mov r0, r3 + 8015afa: f7f8 fbae bl 800e25a + 8015afe: 4602 mov r2, r0 + 8015b00: 69fb ldr r3, [r7, #28] + 8015b02: 601a str r2, [r3, #0] + opts += 1; + 8015b04: 69fb ldr r3, [r7, #28] + 8015b06: 3304 adds r3, #4 + 8015b08: 61fb str r3, [r7, #28] + } +#endif + + /* Set retransmission timer running if it is not currently enabled + This must be set before checking the route. */ + if (pcb->rtime < 0) { + 8015b0a: 68bb ldr r3, [r7, #8] + 8015b0c: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 8015b10: 2b00 cmp r3, #0 + 8015b12: da02 bge.n 8015b1a + pcb->rtime = 0; + 8015b14: 68bb ldr r3, [r7, #8] + 8015b16: 2200 movs r2, #0 + 8015b18: 861a strh r2, [r3, #48] ; 0x30 + } + + if (pcb->rttest == 0) { + 8015b1a: 68bb ldr r3, [r7, #8] + 8015b1c: 6b5b ldr r3, [r3, #52] ; 0x34 + 8015b1e: 2b00 cmp r3, #0 + 8015b20: d10c bne.n 8015b3c + pcb->rttest = tcp_ticks; + 8015b22: 4b34 ldr r3, [pc, #208] ; (8015bf4 ) + 8015b24: 681a ldr r2, [r3, #0] + 8015b26: 68bb ldr r3, [r7, #8] + 8015b28: 635a str r2, [r3, #52] ; 0x34 + pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno); + 8015b2a: 68fb ldr r3, [r7, #12] + 8015b2c: 68db ldr r3, [r3, #12] + 8015b2e: 685b ldr r3, [r3, #4] + 8015b30: 4618 mov r0, r3 + 8015b32: f7f8 fb92 bl 800e25a + 8015b36: 4602 mov r2, r0 + 8015b38: 68bb ldr r3, [r7, #8] + 8015b3a: 639a str r2, [r3, #56] ; 0x38 + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + 8015b3c: 68fb ldr r3, [r7, #12] + 8015b3e: 68da ldr r2, [r3, #12] + 8015b40: 68fb ldr r3, [r7, #12] + 8015b42: 685b ldr r3, [r3, #4] + 8015b44: 685b ldr r3, [r3, #4] + 8015b46: 1ad3 subs r3, r2, r3 + 8015b48: 833b strh r3, [r7, #24] + if (len == 0) { + /** Exclude retransmitted segments from this count. */ + MIB2_STATS_INC(mib2.tcpoutsegs); + } + + seg->p->len -= len; + 8015b4a: 68fb ldr r3, [r7, #12] + 8015b4c: 685b ldr r3, [r3, #4] + 8015b4e: 8959 ldrh r1, [r3, #10] + 8015b50: 68fb ldr r3, [r7, #12] + 8015b52: 685b ldr r3, [r3, #4] + 8015b54: 8b3a ldrh r2, [r7, #24] + 8015b56: 1a8a subs r2, r1, r2 + 8015b58: b292 uxth r2, r2 + 8015b5a: 815a strh r2, [r3, #10] + seg->p->tot_len -= len; + 8015b5c: 68fb ldr r3, [r7, #12] + 8015b5e: 685b ldr r3, [r3, #4] + 8015b60: 8919 ldrh r1, [r3, #8] + 8015b62: 68fb ldr r3, [r7, #12] + 8015b64: 685b ldr r3, [r3, #4] + 8015b66: 8b3a ldrh r2, [r7, #24] + 8015b68: 1a8a subs r2, r1, r2 + 8015b6a: b292 uxth r2, r2 + 8015b6c: 811a strh r2, [r3, #8] + + seg->p->payload = seg->tcphdr; + 8015b6e: 68fb ldr r3, [r7, #12] + 8015b70: 685b ldr r3, [r3, #4] + 8015b72: 68fa ldr r2, [r7, #12] + 8015b74: 68d2 ldr r2, [r2, #12] + 8015b76: 605a str r2, [r3, #4] + + seg->tcphdr->chksum = 0; + 8015b78: 68fb ldr r3, [r7, #12] + 8015b7a: 68db ldr r3, [r3, #12] + 8015b7c: 2200 movs r2, #0 + 8015b7e: 741a strb r2, [r3, #16] + 8015b80: 2200 movs r2, #0 + 8015b82: 745a strb r2, [r3, #17] + +#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts); +#endif + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb)); + 8015b84: 68fb ldr r3, [r7, #12] + 8015b86: 68db ldr r3, [r3, #12] + 8015b88: f103 0214 add.w r2, r3, #20 + 8015b8c: 68fb ldr r3, [r7, #12] + 8015b8e: 7a9b ldrb r3, [r3, #10] + 8015b90: 009b lsls r3, r3, #2 + 8015b92: f003 0304 and.w r3, r3, #4 + 8015b96: 4413 add r3, r2 + 8015b98: 69fa ldr r2, [r7, #28] + 8015b9a: 429a cmp r2, r3 + 8015b9c: d006 beq.n 8015bac + 8015b9e: 4b10 ldr r3, [pc, #64] ; (8015be0 ) + 8015ba0: f240 621c movw r2, #1564 ; 0x61c + 8015ba4: 4914 ldr r1, [pc, #80] ; (8015bf8 ) + 8015ba6: 4810 ldr r0, [pc, #64] ; (8015be8 ) + 8015ba8: f006 fa34 bl 801c014 + } +#endif /* CHECKSUM_GEN_TCP */ + TCP_STATS_INC(tcp.xmit); + + NETIF_SET_HINTS(netif, &(pcb->netif_hints)); + err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, + 8015bac: 68fb ldr r3, [r7, #12] + 8015bae: 6858 ldr r0, [r3, #4] + 8015bb0: 68b9 ldr r1, [r7, #8] + 8015bb2: 68bb ldr r3, [r7, #8] + 8015bb4: 1d1c adds r4, r3, #4 + 8015bb6: 68bb ldr r3, [r7, #8] + 8015bb8: 7add ldrb r5, [r3, #11] + 8015bba: 68bb ldr r3, [r7, #8] + 8015bbc: 7a9b ldrb r3, [r3, #10] + 8015bbe: 687a ldr r2, [r7, #4] + 8015bc0: 9202 str r2, [sp, #8] + 8015bc2: 2206 movs r2, #6 + 8015bc4: 9201 str r2, [sp, #4] + 8015bc6: 9300 str r3, [sp, #0] + 8015bc8: 462b mov r3, r5 + 8015bca: 4622 mov r2, r4 + 8015bcc: f004 fd32 bl 801a634 + 8015bd0: 4603 mov r3, r0 + 8015bd2: 75fb strb r3, [r7, #23] + seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); + seg->chksum_swapped = 1; + } +#endif + + return err; + 8015bd4: f997 3017 ldrsb.w r3, [r7, #23] +} + 8015bd8: 4618 mov r0, r3 + 8015bda: 3720 adds r7, #32 + 8015bdc: 46bd mov sp, r7 + 8015bde: bdb0 pop {r4, r5, r7, pc} + 8015be0: 08020108 .word 0x08020108 + 8015be4: 080206cc .word 0x080206cc + 8015be8: 0802015c .word 0x0802015c + 8015bec: 080206ec .word 0x080206ec + 8015bf0: 0802070c .word 0x0802070c + 8015bf4: 2000cf30 .word 0x2000cf30 + 8015bf8: 08020730 .word 0x08020730 + +08015bfc : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +err_t +tcp_rexmit_rto_prepare(struct tcp_pcb *pcb) +{ + 8015bfc: b5b0 push {r4, r5, r7, lr} + 8015bfe: b084 sub sp, #16 + 8015c00: af00 add r7, sp, #0 + 8015c02: 6078 str r0, [r7, #4] + struct tcp_seg *seg; + + LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL); + 8015c04: 687b ldr r3, [r7, #4] + 8015c06: 2b00 cmp r3, #0 + 8015c08: d106 bne.n 8015c18 + 8015c0a: 4b31 ldr r3, [pc, #196] ; (8015cd0 ) + 8015c0c: f240 6263 movw r2, #1635 ; 0x663 + 8015c10: 4930 ldr r1, [pc, #192] ; (8015cd4 ) + 8015c12: 4831 ldr r0, [pc, #196] ; (8015cd8 ) + 8015c14: f006 f9fe bl 801c014 + + if (pcb->unacked == NULL) { + 8015c18: 687b ldr r3, [r7, #4] + 8015c1a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015c1c: 2b00 cmp r3, #0 + 8015c1e: d102 bne.n 8015c26 + return ERR_VAL; + 8015c20: f06f 0305 mvn.w r3, #5 + 8015c24: e050 b.n 8015cc8 + + /* Move all unacked segments to the head of the unsent queue. + However, give up if any of the unsent pbufs are still referenced by the + netif driver due to deferred transmission. No point loading the link further + if it is struggling to flush its buffered writes. */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { + 8015c26: 687b ldr r3, [r7, #4] + 8015c28: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015c2a: 60fb str r3, [r7, #12] + 8015c2c: e00b b.n 8015c46 + if (tcp_output_segment_busy(seg)) { + 8015c2e: 68f8 ldr r0, [r7, #12] + 8015c30: f7ff fee6 bl 8015a00 + 8015c34: 4603 mov r3, r0 + 8015c36: 2b00 cmp r3, #0 + 8015c38: d002 beq.n 8015c40 + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + 8015c3a: f06f 0305 mvn.w r3, #5 + 8015c3e: e043 b.n 8015cc8 + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { + 8015c40: 68fb ldr r3, [r7, #12] + 8015c42: 681b ldr r3, [r3, #0] + 8015c44: 60fb str r3, [r7, #12] + 8015c46: 68fb ldr r3, [r7, #12] + 8015c48: 681b ldr r3, [r3, #0] + 8015c4a: 2b00 cmp r3, #0 + 8015c4c: d1ef bne.n 8015c2e + } + } + if (tcp_output_segment_busy(seg)) { + 8015c4e: 68f8 ldr r0, [r7, #12] + 8015c50: f7ff fed6 bl 8015a00 + 8015c54: 4603 mov r3, r0 + 8015c56: 2b00 cmp r3, #0 + 8015c58: d002 beq.n 8015c60 + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + 8015c5a: f06f 0305 mvn.w r3, #5 + 8015c5e: e033 b.n 8015cc8 + } + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + 8015c60: 687b ldr r3, [r7, #4] + 8015c62: 6eda ldr r2, [r3, #108] ; 0x6c + 8015c64: 68fb ldr r3, [r7, #12] + 8015c66: 601a str r2, [r3, #0] + if (pcb->unsent == NULL) { + pcb->unsent_oversize = seg->oversize_left; + } +#endif /* TCP_OVERSIZE_DBGCHECK */ + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + 8015c68: 687b ldr r3, [r7, #4] + 8015c6a: 6f1a ldr r2, [r3, #112] ; 0x70 + 8015c6c: 687b ldr r3, [r7, #4] + 8015c6e: 66da str r2, [r3, #108] ; 0x6c + /* unacked queue is now empty */ + pcb->unacked = NULL; + 8015c70: 687b ldr r3, [r7, #4] + 8015c72: 2200 movs r2, #0 + 8015c74: 671a str r2, [r3, #112] ; 0x70 + + /* Mark RTO in-progress */ + tcp_set_flags(pcb, TF_RTO); + 8015c76: 687b ldr r3, [r7, #4] + 8015c78: 8b5b ldrh r3, [r3, #26] + 8015c7a: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8015c7e: b29a uxth r2, r3 + 8015c80: 687b ldr r3, [r7, #4] + 8015c82: 835a strh r2, [r3, #26] + /* Record the next byte following retransmit */ + pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + 8015c84: 68fb ldr r3, [r7, #12] + 8015c86: 68db ldr r3, [r3, #12] + 8015c88: 685b ldr r3, [r3, #4] + 8015c8a: 4618 mov r0, r3 + 8015c8c: f7f8 fae5 bl 800e25a + 8015c90: 4604 mov r4, r0 + 8015c92: 68fb ldr r3, [r7, #12] + 8015c94: 891b ldrh r3, [r3, #8] + 8015c96: 461d mov r5, r3 + 8015c98: 68fb ldr r3, [r7, #12] + 8015c9a: 68db ldr r3, [r3, #12] + 8015c9c: 899b ldrh r3, [r3, #12] + 8015c9e: b29b uxth r3, r3 + 8015ca0: 4618 mov r0, r3 + 8015ca2: f7f8 fac5 bl 800e230 + 8015ca6: 4603 mov r3, r0 + 8015ca8: b2db uxtb r3, r3 + 8015caa: f003 0303 and.w r3, r3, #3 + 8015cae: 2b00 cmp r3, #0 + 8015cb0: d001 beq.n 8015cb6 + 8015cb2: 2301 movs r3, #1 + 8015cb4: e000 b.n 8015cb8 + 8015cb6: 2300 movs r3, #0 + 8015cb8: 442b add r3, r5 + 8015cba: 18e2 adds r2, r4, r3 + 8015cbc: 687b ldr r3, [r7, #4] + 8015cbe: 64da str r2, [r3, #76] ; 0x4c + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + 8015cc0: 687b ldr r3, [r7, #4] + 8015cc2: 2200 movs r2, #0 + 8015cc4: 635a str r2, [r3, #52] ; 0x34 + + return ERR_OK; + 8015cc6: 2300 movs r3, #0 +} + 8015cc8: 4618 mov r0, r3 + 8015cca: 3710 adds r7, #16 + 8015ccc: 46bd mov sp, r7 + 8015cce: bdb0 pop {r4, r5, r7, pc} + 8015cd0: 08020108 .word 0x08020108 + 8015cd4: 08020744 .word 0x08020744 + 8015cd8: 0802015c .word 0x0802015c + +08015cdc : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto_commit(struct tcp_pcb *pcb) +{ + 8015cdc: b580 push {r7, lr} + 8015cde: b082 sub sp, #8 + 8015ce0: af00 add r7, sp, #0 + 8015ce2: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL); + 8015ce4: 687b ldr r3, [r7, #4] + 8015ce6: 2b00 cmp r3, #0 + 8015ce8: d106 bne.n 8015cf8 + 8015cea: 4b0d ldr r3, [pc, #52] ; (8015d20 ) + 8015cec: f44f 62d3 mov.w r2, #1688 ; 0x698 + 8015cf0: 490c ldr r1, [pc, #48] ; (8015d24 ) + 8015cf2: 480d ldr r0, [pc, #52] ; (8015d28 ) + 8015cf4: f006 f98e bl 801c014 + + /* increment number of retransmissions */ + if (pcb->nrtx < 0xFF) { + 8015cf8: 687b ldr r3, [r7, #4] + 8015cfa: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8015cfe: 2bff cmp r3, #255 ; 0xff + 8015d00: d007 beq.n 8015d12 + ++pcb->nrtx; + 8015d02: 687b ldr r3, [r7, #4] + 8015d04: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8015d08: 3301 adds r3, #1 + 8015d0a: b2da uxtb r2, r3 + 8015d0c: 687b ldr r3, [r7, #4] + 8015d0e: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + /* Do the actual retransmission */ + tcp_output(pcb); + 8015d12: 6878 ldr r0, [r7, #4] + 8015d14: f7ff fc80 bl 8015618 +} + 8015d18: bf00 nop + 8015d1a: 3708 adds r7, #8 + 8015d1c: 46bd mov sp, r7 + 8015d1e: bd80 pop {r7, pc} + 8015d20: 08020108 .word 0x08020108 + 8015d24: 08020768 .word 0x08020768 + 8015d28: 0802015c .word 0x0802015c + +08015d2c : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + 8015d2c: b580 push {r7, lr} + 8015d2e: b082 sub sp, #8 + 8015d30: af00 add r7, sp, #0 + 8015d32: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL); + 8015d34: 687b ldr r3, [r7, #4] + 8015d36: 2b00 cmp r3, #0 + 8015d38: d106 bne.n 8015d48 + 8015d3a: 4b0a ldr r3, [pc, #40] ; (8015d64 ) + 8015d3c: f240 62ad movw r2, #1709 ; 0x6ad + 8015d40: 4909 ldr r1, [pc, #36] ; (8015d68 ) + 8015d42: 480a ldr r0, [pc, #40] ; (8015d6c ) + 8015d44: f006 f966 bl 801c014 + + if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) { + 8015d48: 6878 ldr r0, [r7, #4] + 8015d4a: f7ff ff57 bl 8015bfc + 8015d4e: 4603 mov r3, r0 + 8015d50: 2b00 cmp r3, #0 + 8015d52: d102 bne.n 8015d5a + tcp_rexmit_rto_commit(pcb); + 8015d54: 6878 ldr r0, [r7, #4] + 8015d56: f7ff ffc1 bl 8015cdc + } +} + 8015d5a: bf00 nop + 8015d5c: 3708 adds r7, #8 + 8015d5e: 46bd mov sp, r7 + 8015d60: bd80 pop {r7, pc} + 8015d62: bf00 nop + 8015d64: 08020108 .word 0x08020108 + 8015d68: 0802078c .word 0x0802078c + 8015d6c: 0802015c .word 0x0802015c + +08015d70 : + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +err_t +tcp_rexmit(struct tcp_pcb *pcb) +{ + 8015d70: b590 push {r4, r7, lr} + 8015d72: b085 sub sp, #20 + 8015d74: af00 add r7, sp, #0 + 8015d76: 6078 str r0, [r7, #4] + struct tcp_seg *seg; + struct tcp_seg **cur_seg; + + LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL); + 8015d78: 687b ldr r3, [r7, #4] + 8015d7a: 2b00 cmp r3, #0 + 8015d7c: d106 bne.n 8015d8c + 8015d7e: 4b2f ldr r3, [pc, #188] ; (8015e3c ) + 8015d80: f240 62c1 movw r2, #1729 ; 0x6c1 + 8015d84: 492e ldr r1, [pc, #184] ; (8015e40 ) + 8015d86: 482f ldr r0, [pc, #188] ; (8015e44 ) + 8015d88: f006 f944 bl 801c014 + + if (pcb->unacked == NULL) { + 8015d8c: 687b ldr r3, [r7, #4] + 8015d8e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015d90: 2b00 cmp r3, #0 + 8015d92: d102 bne.n 8015d9a + return ERR_VAL; + 8015d94: f06f 0305 mvn.w r3, #5 + 8015d98: e04c b.n 8015e34 + } + + seg = pcb->unacked; + 8015d9a: 687b ldr r3, [r7, #4] + 8015d9c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015d9e: 60bb str r3, [r7, #8] + + /* Give up if the segment is still referenced by the netif driver + due to deferred transmission. */ + if (tcp_output_segment_busy(seg)) { + 8015da0: 68b8 ldr r0, [r7, #8] + 8015da2: f7ff fe2d bl 8015a00 + 8015da6: 4603 mov r3, r0 + 8015da8: 2b00 cmp r3, #0 + 8015daa: d002 beq.n 8015db2 + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n")); + return ERR_VAL; + 8015dac: f06f 0305 mvn.w r3, #5 + 8015db0: e040 b.n 8015e34 + } + + /* Move the first unacked segment to the unsent queue */ + /* Keep the unsent queue sorted. */ + pcb->unacked = seg->next; + 8015db2: 68bb ldr r3, [r7, #8] + 8015db4: 681a ldr r2, [r3, #0] + 8015db6: 687b ldr r3, [r7, #4] + 8015db8: 671a str r2, [r3, #112] ; 0x70 + + cur_seg = &(pcb->unsent); + 8015dba: 687b ldr r3, [r7, #4] + 8015dbc: 336c adds r3, #108 ; 0x6c + 8015dbe: 60fb str r3, [r7, #12] + while (*cur_seg && + 8015dc0: e002 b.n 8015dc8 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + 8015dc2: 68fb ldr r3, [r7, #12] + 8015dc4: 681b ldr r3, [r3, #0] + 8015dc6: 60fb str r3, [r7, #12] + while (*cur_seg && + 8015dc8: 68fb ldr r3, [r7, #12] + 8015dca: 681b ldr r3, [r3, #0] + 8015dcc: 2b00 cmp r3, #0 + 8015dce: d011 beq.n 8015df4 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + 8015dd0: 68fb ldr r3, [r7, #12] + 8015dd2: 681b ldr r3, [r3, #0] + 8015dd4: 68db ldr r3, [r3, #12] + 8015dd6: 685b ldr r3, [r3, #4] + 8015dd8: 4618 mov r0, r3 + 8015dda: f7f8 fa3e bl 800e25a + 8015dde: 4604 mov r4, r0 + 8015de0: 68bb ldr r3, [r7, #8] + 8015de2: 68db ldr r3, [r3, #12] + 8015de4: 685b ldr r3, [r3, #4] + 8015de6: 4618 mov r0, r3 + 8015de8: f7f8 fa37 bl 800e25a + 8015dec: 4603 mov r3, r0 + 8015dee: 1ae3 subs r3, r4, r3 + while (*cur_seg && + 8015df0: 2b00 cmp r3, #0 + 8015df2: dbe6 blt.n 8015dc2 + } + seg->next = *cur_seg; + 8015df4: 68fb ldr r3, [r7, #12] + 8015df6: 681a ldr r2, [r3, #0] + 8015df8: 68bb ldr r3, [r7, #8] + 8015dfa: 601a str r2, [r3, #0] + *cur_seg = seg; + 8015dfc: 68fb ldr r3, [r7, #12] + 8015dfe: 68ba ldr r2, [r7, #8] + 8015e00: 601a str r2, [r3, #0] +#if TCP_OVERSIZE + if (seg->next == NULL) { + 8015e02: 68bb ldr r3, [r7, #8] + 8015e04: 681b ldr r3, [r3, #0] + 8015e06: 2b00 cmp r3, #0 + 8015e08: d103 bne.n 8015e12 + /* the retransmitted segment is last in unsent, so reset unsent_oversize */ + pcb->unsent_oversize = 0; + 8015e0a: 687b ldr r3, [r7, #4] + 8015e0c: 2200 movs r2, #0 + 8015e0e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + } +#endif /* TCP_OVERSIZE */ + + if (pcb->nrtx < 0xFF) { + 8015e12: 687b ldr r3, [r7, #4] + 8015e14: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8015e18: 2bff cmp r3, #255 ; 0xff + 8015e1a: d007 beq.n 8015e2c + ++pcb->nrtx; + 8015e1c: 687b ldr r3, [r7, #4] + 8015e1e: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8015e22: 3301 adds r3, #1 + 8015e24: b2da uxtb r2, r3 + 8015e26: 687b ldr r3, [r7, #4] + 8015e28: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + 8015e2c: 687b ldr r3, [r7, #4] + 8015e2e: 2200 movs r2, #0 + 8015e30: 635a str r2, [r3, #52] ; 0x34 + + /* Do the actual retransmission. */ + MIB2_STATS_INC(mib2.tcpretranssegs); + /* No need to call tcp_output: we are always called from tcp_input() + and thus tcp_output directly returns. */ + return ERR_OK; + 8015e32: 2300 movs r3, #0 +} + 8015e34: 4618 mov r0, r3 + 8015e36: 3714 adds r7, #20 + 8015e38: 46bd mov sp, r7 + 8015e3a: bd90 pop {r4, r7, pc} + 8015e3c: 08020108 .word 0x08020108 + 8015e40: 080207a8 .word 0x080207a8 + 8015e44: 0802015c .word 0x0802015c + +08015e48 : + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit_fast(struct tcp_pcb *pcb) +{ + 8015e48: b580 push {r7, lr} + 8015e4a: b082 sub sp, #8 + 8015e4c: af00 add r7, sp, #0 + 8015e4e: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL); + 8015e50: 687b ldr r3, [r7, #4] + 8015e52: 2b00 cmp r3, #0 + 8015e54: d106 bne.n 8015e64 + 8015e56: 4b2a ldr r3, [pc, #168] ; (8015f00 ) + 8015e58: f240 62f9 movw r2, #1785 ; 0x6f9 + 8015e5c: 4929 ldr r1, [pc, #164] ; (8015f04 ) + 8015e5e: 482a ldr r0, [pc, #168] ; (8015f08 ) + 8015e60: f006 f8d8 bl 801c014 + + if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { + 8015e64: 687b ldr r3, [r7, #4] + 8015e66: 6f1b ldr r3, [r3, #112] ; 0x70 + 8015e68: 2b00 cmp r3, #0 + 8015e6a: d045 beq.n 8015ef8 + 8015e6c: 687b ldr r3, [r7, #4] + 8015e6e: 8b5b ldrh r3, [r3, #26] + 8015e70: f003 0304 and.w r3, r3, #4 + 8015e74: 2b00 cmp r3, #0 + 8015e76: d13f bne.n 8015ef8 + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: dupacks %"U16_F" (%"U32_F + "), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + lwip_ntohl(pcb->unacked->tcphdr->seqno))); + if (tcp_rexmit(pcb) == ERR_OK) { + 8015e78: 6878 ldr r0, [r7, #4] + 8015e7a: f7ff ff79 bl 8015d70 + 8015e7e: 4603 mov r3, r0 + 8015e80: 2b00 cmp r3, #0 + 8015e82: d139 bne.n 8015ef8 + /* Set ssthresh to half of the minimum of the current + * cwnd and the advertised window */ + pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2; + 8015e84: 687b ldr r3, [r7, #4] + 8015e86: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 8015e8a: 687b ldr r3, [r7, #4] + 8015e8c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 8015e90: 4293 cmp r3, r2 + 8015e92: bf28 it cs + 8015e94: 4613 movcs r3, r2 + 8015e96: b29b uxth r3, r3 + 8015e98: 2b00 cmp r3, #0 + 8015e9a: da00 bge.n 8015e9e + 8015e9c: 3301 adds r3, #1 + 8015e9e: 105b asrs r3, r3, #1 + 8015ea0: b29a uxth r2, r3 + 8015ea2: 687b ldr r3, [r7, #4] + 8015ea4: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + + /* The minimum value for ssthresh should be 2 MSS */ + if (pcb->ssthresh < (2U * pcb->mss)) { + 8015ea8: 687b ldr r3, [r7, #4] + 8015eaa: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a + 8015eae: 461a mov r2, r3 + 8015eb0: 687b ldr r3, [r7, #4] + 8015eb2: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8015eb4: 005b lsls r3, r3, #1 + 8015eb6: 429a cmp r2, r3 + 8015eb8: d206 bcs.n 8015ec8 + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F + " should be min 2 mss %"U16_F"...\n", + pcb->ssthresh, (u16_t)(2 * pcb->mss))); + pcb->ssthresh = 2 * pcb->mss; + 8015eba: 687b ldr r3, [r7, #4] + 8015ebc: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8015ebe: 005b lsls r3, r3, #1 + 8015ec0: b29a uxth r2, r3 + 8015ec2: 687b ldr r3, [r7, #4] + 8015ec4: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + } + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + 8015ec8: 687b ldr r3, [r7, #4] + 8015eca: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 8015ece: 687b ldr r3, [r7, #4] + 8015ed0: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8015ed2: 4619 mov r1, r3 + 8015ed4: 0049 lsls r1, r1, #1 + 8015ed6: 440b add r3, r1 + 8015ed8: b29b uxth r3, r3 + 8015eda: 4413 add r3, r2 + 8015edc: b29a uxth r2, r3 + 8015ede: 687b ldr r3, [r7, #4] + 8015ee0: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + tcp_set_flags(pcb, TF_INFR); + 8015ee4: 687b ldr r3, [r7, #4] + 8015ee6: 8b5b ldrh r3, [r3, #26] + 8015ee8: f043 0304 orr.w r3, r3, #4 + 8015eec: b29a uxth r2, r3 + 8015eee: 687b ldr r3, [r7, #4] + 8015ef0: 835a strh r2, [r3, #26] + + /* Reset the retransmission timer to prevent immediate rto retransmissions */ + pcb->rtime = 0; + 8015ef2: 687b ldr r3, [r7, #4] + 8015ef4: 2200 movs r2, #0 + 8015ef6: 861a strh r2, [r3, #48] ; 0x30 + } + } +} + 8015ef8: bf00 nop + 8015efa: 3708 adds r7, #8 + 8015efc: 46bd mov sp, r7 + 8015efe: bd80 pop {r7, pc} + 8015f00: 08020108 .word 0x08020108 + 8015f04: 080207c0 .word 0x080207c0 + 8015f08: 0802015c .word 0x0802015c + +08015f0c : + +static struct pbuf * +tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */, + u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd) +{ + 8015f0c: b580 push {r7, lr} + 8015f0e: b086 sub sp, #24 + 8015f10: af00 add r7, sp, #0 + 8015f12: 60f8 str r0, [r7, #12] + 8015f14: 607b str r3, [r7, #4] + 8015f16: 460b mov r3, r1 + 8015f18: 817b strh r3, [r7, #10] + 8015f1a: 4613 mov r3, r2 + 8015f1c: 813b strh r3, [r7, #8] + struct tcp_hdr *tcphdr; + struct pbuf *p; + + p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); + 8015f1e: 897a ldrh r2, [r7, #10] + 8015f20: 893b ldrh r3, [r7, #8] + 8015f22: 4413 add r3, r2 + 8015f24: b29b uxth r3, r3 + 8015f26: 3314 adds r3, #20 + 8015f28: b29b uxth r3, r3 + 8015f2a: f44f 7220 mov.w r2, #640 ; 0x280 + 8015f2e: 4619 mov r1, r3 + 8015f30: 2022 movs r0, #34 ; 0x22 + 8015f32: f7fa fa81 bl 8010438 + 8015f36: 6178 str r0, [r7, #20] + if (p != NULL) { + 8015f38: 697b ldr r3, [r7, #20] + 8015f3a: 2b00 cmp r3, #0 + 8015f3c: d04d beq.n 8015fda + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + 8015f3e: 897b ldrh r3, [r7, #10] + 8015f40: 3313 adds r3, #19 + 8015f42: 697a ldr r2, [r7, #20] + 8015f44: 8952 ldrh r2, [r2, #10] + 8015f46: 4293 cmp r3, r2 + 8015f48: db06 blt.n 8015f58 + 8015f4a: 4b26 ldr r3, [pc, #152] ; (8015fe4 ) + 8015f4c: f240 7223 movw r2, #1827 ; 0x723 + 8015f50: 4925 ldr r1, [pc, #148] ; (8015fe8 ) + 8015f52: 4826 ldr r0, [pc, #152] ; (8015fec ) + 8015f54: f006 f85e bl 801c014 + (p->len >= TCP_HLEN + optlen)); + tcphdr = (struct tcp_hdr *)p->payload; + 8015f58: 697b ldr r3, [r7, #20] + 8015f5a: 685b ldr r3, [r3, #4] + 8015f5c: 613b str r3, [r7, #16] + tcphdr->src = lwip_htons(src_port); + 8015f5e: 8c3b ldrh r3, [r7, #32] + 8015f60: 4618 mov r0, r3 + 8015f62: f7f8 f965 bl 800e230 + 8015f66: 4603 mov r3, r0 + 8015f68: 461a mov r2, r3 + 8015f6a: 693b ldr r3, [r7, #16] + 8015f6c: 801a strh r2, [r3, #0] + tcphdr->dest = lwip_htons(dst_port); + 8015f6e: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8015f70: 4618 mov r0, r3 + 8015f72: f7f8 f95d bl 800e230 + 8015f76: 4603 mov r3, r0 + 8015f78: 461a mov r2, r3 + 8015f7a: 693b ldr r3, [r7, #16] + 8015f7c: 805a strh r2, [r3, #2] + tcphdr->seqno = seqno_be; + 8015f7e: 693b ldr r3, [r7, #16] + 8015f80: 687a ldr r2, [r7, #4] + 8015f82: 605a str r2, [r3, #4] + tcphdr->ackno = lwip_htonl(ackno); + 8015f84: 68f8 ldr r0, [r7, #12] + 8015f86: f7f8 f968 bl 800e25a + 8015f8a: 4602 mov r2, r0 + 8015f8c: 693b ldr r3, [r7, #16] + 8015f8e: 609a str r2, [r3, #8] + TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags); + 8015f90: 897b ldrh r3, [r7, #10] + 8015f92: 089b lsrs r3, r3, #2 + 8015f94: b29b uxth r3, r3 + 8015f96: 3305 adds r3, #5 + 8015f98: b29b uxth r3, r3 + 8015f9a: 031b lsls r3, r3, #12 + 8015f9c: b29a uxth r2, r3 + 8015f9e: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 8015fa2: b29b uxth r3, r3 + 8015fa4: 4313 orrs r3, r2 + 8015fa6: b29b uxth r3, r3 + 8015fa8: 4618 mov r0, r3 + 8015faa: f7f8 f941 bl 800e230 + 8015fae: 4603 mov r3, r0 + 8015fb0: 461a mov r2, r3 + 8015fb2: 693b ldr r3, [r7, #16] + 8015fb4: 819a strh r2, [r3, #12] + tcphdr->wnd = lwip_htons(wnd); + 8015fb6: 8dbb ldrh r3, [r7, #44] ; 0x2c + 8015fb8: 4618 mov r0, r3 + 8015fba: f7f8 f939 bl 800e230 + 8015fbe: 4603 mov r3, r0 + 8015fc0: 461a mov r2, r3 + 8015fc2: 693b ldr r3, [r7, #16] + 8015fc4: 81da strh r2, [r3, #14] + tcphdr->chksum = 0; + 8015fc6: 693b ldr r3, [r7, #16] + 8015fc8: 2200 movs r2, #0 + 8015fca: 741a strb r2, [r3, #16] + 8015fcc: 2200 movs r2, #0 + 8015fce: 745a strb r2, [r3, #17] + tcphdr->urgp = 0; + 8015fd0: 693b ldr r3, [r7, #16] + 8015fd2: 2200 movs r2, #0 + 8015fd4: 749a strb r2, [r3, #18] + 8015fd6: 2200 movs r2, #0 + 8015fd8: 74da strb r2, [r3, #19] + } + return p; + 8015fda: 697b ldr r3, [r7, #20] +} + 8015fdc: 4618 mov r0, r3 + 8015fde: 3718 adds r7, #24 + 8015fe0: 46bd mov sp, r7 + 8015fe2: bd80 pop {r7, pc} + 8015fe4: 08020108 .word 0x08020108 + 8015fe8: 080207e0 .word 0x080207e0 + 8015fec: 0802015c .word 0x0802015c + +08015ff0 : + * @return pbuf with p->payload being the tcp_hdr + */ +static struct pbuf * +tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */) +{ + 8015ff0: b5b0 push {r4, r5, r7, lr} + 8015ff2: b08a sub sp, #40 ; 0x28 + 8015ff4: af04 add r7, sp, #16 + 8015ff6: 60f8 str r0, [r7, #12] + 8015ff8: 607b str r3, [r7, #4] + 8015ffa: 460b mov r3, r1 + 8015ffc: 817b strh r3, [r7, #10] + 8015ffe: 4613 mov r3, r2 + 8016000: 813b strh r3, [r7, #8] + struct pbuf *p; + + LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL); + 8016002: 68fb ldr r3, [r7, #12] + 8016004: 2b00 cmp r3, #0 + 8016006: d106 bne.n 8016016 + 8016008: 4b15 ldr r3, [pc, #84] ; (8016060 ) + 801600a: f240 7242 movw r2, #1858 ; 0x742 + 801600e: 4915 ldr r1, [pc, #84] ; (8016064 ) + 8016010: 4815 ldr r0, [pc, #84] ; (8016068 ) + 8016012: f005 ffff bl 801c014 + + p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen, + 8016016: 68fb ldr r3, [r7, #12] + 8016018: 6a58 ldr r0, [r3, #36] ; 0x24 + 801601a: 68fb ldr r3, [r7, #12] + 801601c: 8adb ldrh r3, [r3, #22] + 801601e: 68fa ldr r2, [r7, #12] + 8016020: 8b12 ldrh r2, [r2, #24] + 8016022: 68f9 ldr r1, [r7, #12] + 8016024: 8d49 ldrh r1, [r1, #42] ; 0x2a + 8016026: 893d ldrh r5, [r7, #8] + 8016028: 897c ldrh r4, [r7, #10] + 801602a: 9103 str r1, [sp, #12] + 801602c: 2110 movs r1, #16 + 801602e: 9102 str r1, [sp, #8] + 8016030: 9201 str r2, [sp, #4] + 8016032: 9300 str r3, [sp, #0] + 8016034: 687b ldr r3, [r7, #4] + 8016036: 462a mov r2, r5 + 8016038: 4621 mov r1, r4 + 801603a: f7ff ff67 bl 8015f0c + 801603e: 6178 str r0, [r7, #20] + seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK, + TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + if (p != NULL) { + 8016040: 697b ldr r3, [r7, #20] + 8016042: 2b00 cmp r3, #0 + 8016044: d006 beq.n 8016054 + /* If we're sending a packet, update the announced right window edge */ + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + 8016046: 68fb ldr r3, [r7, #12] + 8016048: 6a5b ldr r3, [r3, #36] ; 0x24 + 801604a: 68fa ldr r2, [r7, #12] + 801604c: 8d52 ldrh r2, [r2, #42] ; 0x2a + 801604e: 441a add r2, r3 + 8016050: 68fb ldr r3, [r7, #12] + 8016052: 62da str r2, [r3, #44] ; 0x2c + } + return p; + 8016054: 697b ldr r3, [r7, #20] +} + 8016056: 4618 mov r0, r3 + 8016058: 3718 adds r7, #24 + 801605a: 46bd mov sp, r7 + 801605c: bdb0 pop {r4, r5, r7, pc} + 801605e: bf00 nop + 8016060: 08020108 .word 0x08020108 + 8016064: 08020810 .word 0x08020810 + 8016068: 0802015c .word 0x0802015c + +0801606c : + +/* Fill in options for control segments */ +static void +tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks) +{ + 801606c: b580 push {r7, lr} + 801606e: b088 sub sp, #32 + 8016070: af00 add r7, sp, #0 + 8016072: 60f8 str r0, [r7, #12] + 8016074: 60b9 str r1, [r7, #8] + 8016076: 4611 mov r1, r2 + 8016078: 461a mov r2, r3 + 801607a: 460b mov r3, r1 + 801607c: 71fb strb r3, [r7, #7] + 801607e: 4613 mov r3, r2 + 8016080: 71bb strb r3, [r7, #6] + struct tcp_hdr *tcphdr; + u32_t *opts; + u16_t sacks_len = 0; + 8016082: 2300 movs r3, #0 + 8016084: 83fb strh r3, [r7, #30] + + LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL); + 8016086: 68bb ldr r3, [r7, #8] + 8016088: 2b00 cmp r3, #0 + 801608a: d106 bne.n 801609a + 801608c: 4b13 ldr r3, [pc, #76] ; (80160dc ) + 801608e: f240 7256 movw r2, #1878 ; 0x756 + 8016092: 4913 ldr r1, [pc, #76] ; (80160e0 ) + 8016094: 4813 ldr r0, [pc, #76] ; (80160e4 ) + 8016096: f005 ffbd bl 801c014 + + tcphdr = (struct tcp_hdr *)p->payload; + 801609a: 68bb ldr r3, [r7, #8] + 801609c: 685b ldr r3, [r3, #4] + 801609e: 61bb str r3, [r7, #24] + opts = (u32_t *)(void *)(tcphdr + 1); + 80160a0: 69bb ldr r3, [r7, #24] + 80160a2: 3314 adds r3, #20 + 80160a4: 617b str r3, [r7, #20] + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts); +#endif + + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(sacks_len); + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb)); + 80160a6: 69bb ldr r3, [r7, #24] + 80160a8: f103 0214 add.w r2, r3, #20 + 80160ac: 8bfb ldrh r3, [r7, #30] + 80160ae: 009b lsls r3, r3, #2 + 80160b0: 4619 mov r1, r3 + 80160b2: 79fb ldrb r3, [r7, #7] + 80160b4: 009b lsls r3, r3, #2 + 80160b6: f003 0304 and.w r3, r3, #4 + 80160ba: 440b add r3, r1 + 80160bc: 4413 add r3, r2 + 80160be: 697a ldr r2, [r7, #20] + 80160c0: 429a cmp r2, r3 + 80160c2: d006 beq.n 80160d2 + 80160c4: 4b05 ldr r3, [pc, #20] ; (80160dc ) + 80160c6: f240 7275 movw r2, #1909 ; 0x775 + 80160ca: 4907 ldr r1, [pc, #28] ; (80160e8 ) + 80160cc: 4805 ldr r0, [pc, #20] ; (80160e4 ) + 80160ce: f005 ffa1 bl 801c014 + LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */ + LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */ +} + 80160d2: bf00 nop + 80160d4: 3720 adds r7, #32 + 80160d6: 46bd mov sp, r7 + 80160d8: bd80 pop {r7, pc} + 80160da: bf00 nop + 80160dc: 08020108 .word 0x08020108 + 80160e0: 08020838 .word 0x08020838 + 80160e4: 0802015c .word 0x0802015c + 80160e8: 08020730 .word 0x08020730 + +080160ec : + * header checksum and calling ip_output_if while handling netif hints and stats. + */ +static err_t +tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p, + const ip_addr_t *src, const ip_addr_t *dst) +{ + 80160ec: b580 push {r7, lr} + 80160ee: b08a sub sp, #40 ; 0x28 + 80160f0: af04 add r7, sp, #16 + 80160f2: 60f8 str r0, [r7, #12] + 80160f4: 60b9 str r1, [r7, #8] + 80160f6: 607a str r2, [r7, #4] + 80160f8: 603b str r3, [r7, #0] + err_t err; + struct netif *netif; + + LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL); + 80160fa: 68bb ldr r3, [r7, #8] + 80160fc: 2b00 cmp r3, #0 + 80160fe: d106 bne.n 801610e + 8016100: 4b1c ldr r3, [pc, #112] ; (8016174 ) + 8016102: f240 7287 movw r2, #1927 ; 0x787 + 8016106: 491c ldr r1, [pc, #112] ; (8016178 ) + 8016108: 481c ldr r0, [pc, #112] ; (801617c ) + 801610a: f005 ff83 bl 801c014 + + netif = tcp_route(pcb, src, dst); + 801610e: 683a ldr r2, [r7, #0] + 8016110: 6879 ldr r1, [r7, #4] + 8016112: 68f8 ldr r0, [r7, #12] + 8016114: f7fe ff40 bl 8014f98 + 8016118: 6138 str r0, [r7, #16] + if (netif == NULL) { + 801611a: 693b ldr r3, [r7, #16] + 801611c: 2b00 cmp r3, #0 + 801611e: d102 bne.n 8016126 + err = ERR_RTE; + 8016120: 23fc movs r3, #252 ; 0xfc + 8016122: 75fb strb r3, [r7, #23] + 8016124: e01c b.n 8016160 + struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, + src, dst); + } +#endif + if (pcb != NULL) { + 8016126: 68fb ldr r3, [r7, #12] + 8016128: 2b00 cmp r3, #0 + 801612a: d006 beq.n 801613a + NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints))); + ttl = pcb->ttl; + 801612c: 68fb ldr r3, [r7, #12] + 801612e: 7adb ldrb r3, [r3, #11] + 8016130: 75bb strb r3, [r7, #22] + tos = pcb->tos; + 8016132: 68fb ldr r3, [r7, #12] + 8016134: 7a9b ldrb r3, [r3, #10] + 8016136: 757b strb r3, [r7, #21] + 8016138: e003 b.n 8016142 + } else { + /* Send output with hardcoded TTL/HL since we have no access to the pcb */ + ttl = TCP_TTL; + 801613a: 23ff movs r3, #255 ; 0xff + 801613c: 75bb strb r3, [r7, #22] + tos = 0; + 801613e: 2300 movs r3, #0 + 8016140: 757b strb r3, [r7, #21] + } + TCP_STATS_INC(tcp.xmit); + err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif); + 8016142: 7dba ldrb r2, [r7, #22] + 8016144: 693b ldr r3, [r7, #16] + 8016146: 9302 str r3, [sp, #8] + 8016148: 2306 movs r3, #6 + 801614a: 9301 str r3, [sp, #4] + 801614c: 7d7b ldrb r3, [r7, #21] + 801614e: 9300 str r3, [sp, #0] + 8016150: 4613 mov r3, r2 + 8016152: 683a ldr r2, [r7, #0] + 8016154: 6879 ldr r1, [r7, #4] + 8016156: 68b8 ldr r0, [r7, #8] + 8016158: f004 fa6c bl 801a634 + 801615c: 4603 mov r3, r0 + 801615e: 75fb strb r3, [r7, #23] + NETIF_RESET_HINTS(netif); + } + pbuf_free(p); + 8016160: 68b8 ldr r0, [r7, #8] + 8016162: f7fa fc4d bl 8010a00 + return err; + 8016166: f997 3017 ldrsb.w r3, [r7, #23] +} + 801616a: 4618 mov r0, r3 + 801616c: 3718 adds r7, #24 + 801616e: 46bd mov sp, r7 + 8016170: bd80 pop {r7, pc} + 8016172: bf00 nop + 8016174: 08020108 .word 0x08020108 + 8016178: 08020860 .word 0x08020860 + 801617c: 0802015c .word 0x0802015c + +08016180 : + */ +void +tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno, + const ip_addr_t *local_ip, const ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port) +{ + 8016180: b590 push {r4, r7, lr} + 8016182: b08b sub sp, #44 ; 0x2c + 8016184: af04 add r7, sp, #16 + 8016186: 60f8 str r0, [r7, #12] + 8016188: 60b9 str r1, [r7, #8] + 801618a: 607a str r2, [r7, #4] + 801618c: 603b str r3, [r7, #0] + struct pbuf *p; + u16_t wnd; + u8_t optlen; + + LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL); + 801618e: 683b ldr r3, [r7, #0] + 8016190: 2b00 cmp r3, #0 + 8016192: d106 bne.n 80161a2 + 8016194: 4b1f ldr r3, [pc, #124] ; (8016214 ) + 8016196: f240 72c4 movw r2, #1988 ; 0x7c4 + 801619a: 491f ldr r1, [pc, #124] ; (8016218 ) + 801619c: 481f ldr r0, [pc, #124] ; (801621c ) + 801619e: f005 ff39 bl 801c014 + LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL); + 80161a2: 6abb ldr r3, [r7, #40] ; 0x28 + 80161a4: 2b00 cmp r3, #0 + 80161a6: d106 bne.n 80161b6 + 80161a8: 4b1a ldr r3, [pc, #104] ; (8016214 ) + 80161aa: f240 72c5 movw r2, #1989 ; 0x7c5 + 80161ae: 491c ldr r1, [pc, #112] ; (8016220 ) + 80161b0: 481a ldr r0, [pc, #104] ; (801621c ) + 80161b2: f005 ff2f bl 801c014 + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 80161b6: 2300 movs r3, #0 + 80161b8: 75fb strb r3, [r7, #23] + +#if LWIP_WND_SCALE + wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF)); +#else + wnd = PP_HTONS(TCP_WND); + 80161ba: f246 0308 movw r3, #24584 ; 0x6008 + 80161be: 82bb strh r3, [r7, #20] +#endif + + p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port, + 80161c0: 7dfb ldrb r3, [r7, #23] + 80161c2: b29c uxth r4, r3 + 80161c4: 68b8 ldr r0, [r7, #8] + 80161c6: f7f8 f848 bl 800e25a + 80161ca: 4602 mov r2, r0 + 80161cc: 8abb ldrh r3, [r7, #20] + 80161ce: 9303 str r3, [sp, #12] + 80161d0: 2314 movs r3, #20 + 80161d2: 9302 str r3, [sp, #8] + 80161d4: 8e3b ldrh r3, [r7, #48] ; 0x30 + 80161d6: 9301 str r3, [sp, #4] + 80161d8: 8dbb ldrh r3, [r7, #44] ; 0x2c + 80161da: 9300 str r3, [sp, #0] + 80161dc: 4613 mov r3, r2 + 80161de: 2200 movs r2, #0 + 80161e0: 4621 mov r1, r4 + 80161e2: 6878 ldr r0, [r7, #4] + 80161e4: f7ff fe92 bl 8015f0c + 80161e8: 6138 str r0, [r7, #16] + remote_port, TCP_RST | TCP_ACK, wnd); + if (p == NULL) { + 80161ea: 693b ldr r3, [r7, #16] + 80161ec: 2b00 cmp r3, #0 + 80161ee: d00c beq.n 801620a + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + tcp_output_fill_options(pcb, p, 0, optlen); + 80161f0: 7dfb ldrb r3, [r7, #23] + 80161f2: 2200 movs r2, #0 + 80161f4: 6939 ldr r1, [r7, #16] + 80161f6: 68f8 ldr r0, [r7, #12] + 80161f8: f7ff ff38 bl 801606c + + MIB2_STATS_INC(mib2.tcpoutrsts); + + tcp_output_control_segment(pcb, p, local_ip, remote_ip); + 80161fc: 6abb ldr r3, [r7, #40] ; 0x28 + 80161fe: 683a ldr r2, [r7, #0] + 8016200: 6939 ldr r1, [r7, #16] + 8016202: 68f8 ldr r0, [r7, #12] + 8016204: f7ff ff72 bl 80160ec + 8016208: e000 b.n 801620c + return; + 801620a: bf00 nop + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + 801620c: 371c adds r7, #28 + 801620e: 46bd mov sp, r7 + 8016210: bd90 pop {r4, r7, pc} + 8016212: bf00 nop + 8016214: 08020108 .word 0x08020108 + 8016218: 0802088c .word 0x0802088c + 801621c: 0802015c .word 0x0802015c + 8016220: 080208a8 .word 0x080208a8 + +08016224 : + * + * @param pcb Protocol control block for the TCP connection to send the ACK + */ +err_t +tcp_send_empty_ack(struct tcp_pcb *pcb) +{ + 8016224: b590 push {r4, r7, lr} + 8016226: b087 sub sp, #28 + 8016228: af00 add r7, sp, #0 + 801622a: 6078 str r0, [r7, #4] + err_t err; + struct pbuf *p; + u8_t optlen, optflags = 0; + 801622c: 2300 movs r3, #0 + 801622e: 75fb strb r3, [r7, #23] + u8_t num_sacks = 0; + 8016230: 2300 movs r3, #0 + 8016232: 75bb strb r3, [r7, #22] + + LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL); + 8016234: 687b ldr r3, [r7, #4] + 8016236: 2b00 cmp r3, #0 + 8016238: d106 bne.n 8016248 + 801623a: 4b28 ldr r3, [pc, #160] ; (80162dc ) + 801623c: f240 72ea movw r2, #2026 ; 0x7ea + 8016240: 4927 ldr r1, [pc, #156] ; (80162e0 ) + 8016242: 4828 ldr r0, [pc, #160] ; (80162e4 ) + 8016244: f005 fee6 bl 801c014 +#if LWIP_TCP_TIMESTAMPS + if (pcb->flags & TF_TIMESTAMP) { + optflags = TF_SEG_OPTS_TS; + } +#endif + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 8016248: 7dfb ldrb r3, [r7, #23] + 801624a: 009b lsls r3, r3, #2 + 801624c: b2db uxtb r3, r3 + 801624e: f003 0304 and.w r3, r3, #4 + 8016252: 757b strb r3, [r7, #21] + if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) { + optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */ + } +#endif + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt)); + 8016254: 7d7b ldrb r3, [r7, #21] + 8016256: b29c uxth r4, r3 + 8016258: 687b ldr r3, [r7, #4] + 801625a: 6d1b ldr r3, [r3, #80] ; 0x50 + 801625c: 4618 mov r0, r3 + 801625e: f7f7 fffc bl 800e25a + 8016262: 4603 mov r3, r0 + 8016264: 2200 movs r2, #0 + 8016266: 4621 mov r1, r4 + 8016268: 6878 ldr r0, [r7, #4] + 801626a: f7ff fec1 bl 8015ff0 + 801626e: 6138 str r0, [r7, #16] + if (p == NULL) { + 8016270: 693b ldr r3, [r7, #16] + 8016272: 2b00 cmp r3, #0 + 8016274: d109 bne.n 801628a + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 8016276: 687b ldr r3, [r7, #4] + 8016278: 8b5b ldrh r3, [r3, #26] + 801627a: f043 0303 orr.w r3, r3, #3 + 801627e: b29a uxth r2, r3 + 8016280: 687b ldr r3, [r7, #4] + 8016282: 835a strh r2, [r3, #26] + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + 8016284: f06f 0301 mvn.w r3, #1 + 8016288: e023 b.n 80162d2 + } + tcp_output_fill_options(pcb, p, optflags, num_sacks); + 801628a: 7dbb ldrb r3, [r7, #22] + 801628c: 7dfa ldrb r2, [r7, #23] + 801628e: 6939 ldr r1, [r7, #16] + 8016290: 6878 ldr r0, [r7, #4] + 8016292: f7ff feeb bl 801606c + pcb->ts_lastacksent = pcb->rcv_nxt; +#endif + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 8016296: 687a ldr r2, [r7, #4] + 8016298: 687b ldr r3, [r7, #4] + 801629a: 3304 adds r3, #4 + 801629c: 6939 ldr r1, [r7, #16] + 801629e: 6878 ldr r0, [r7, #4] + 80162a0: f7ff ff24 bl 80160ec + 80162a4: 4603 mov r3, r0 + 80162a6: 73fb strb r3, [r7, #15] + if (err != ERR_OK) { + 80162a8: f997 300f ldrsb.w r3, [r7, #15] + 80162ac: 2b00 cmp r3, #0 + 80162ae: d007 beq.n 80162c0 + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 80162b0: 687b ldr r3, [r7, #4] + 80162b2: 8b5b ldrh r3, [r3, #26] + 80162b4: f043 0303 orr.w r3, r3, #3 + 80162b8: b29a uxth r2, r3 + 80162ba: 687b ldr r3, [r7, #4] + 80162bc: 835a strh r2, [r3, #26] + 80162be: e006 b.n 80162ce + } else { + /* remove ACK flags from the PCB, as we sent an empty ACK now */ + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 80162c0: 687b ldr r3, [r7, #4] + 80162c2: 8b5b ldrh r3, [r3, #26] + 80162c4: f023 0303 bic.w r3, r3, #3 + 80162c8: b29a uxth r2, r3 + 80162ca: 687b ldr r3, [r7, #4] + 80162cc: 835a strh r2, [r3, #26] + } + + return err; + 80162ce: f997 300f ldrsb.w r3, [r7, #15] +} + 80162d2: 4618 mov r0, r3 + 80162d4: 371c adds r7, #28 + 80162d6: 46bd mov sp, r7 + 80162d8: bd90 pop {r4, r7, pc} + 80162da: bf00 nop + 80162dc: 08020108 .word 0x08020108 + 80162e0: 080208c4 .word 0x080208c4 + 80162e4: 0802015c .word 0x0802015c + +080162e8 : + * + * @param pcb the tcp_pcb for which to send a keepalive packet + */ +err_t +tcp_keepalive(struct tcp_pcb *pcb) +{ + 80162e8: b590 push {r4, r7, lr} + 80162ea: b087 sub sp, #28 + 80162ec: af00 add r7, sp, #0 + 80162ee: 6078 str r0, [r7, #4] + err_t err; + struct pbuf *p; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 80162f0: 2300 movs r3, #0 + 80162f2: 75fb strb r3, [r7, #23] + + LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL); + 80162f4: 687b ldr r3, [r7, #4] + 80162f6: 2b00 cmp r3, #0 + 80162f8: d106 bne.n 8016308 + 80162fa: 4b18 ldr r3, [pc, #96] ; (801635c ) + 80162fc: f640 0224 movw r2, #2084 ; 0x824 + 8016300: 4917 ldr r1, [pc, #92] ; (8016360 ) + 8016302: 4818 ldr r0, [pc, #96] ; (8016364 ) + 8016304: f005 fe86 bl 801c014 + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1)); + 8016308: 7dfb ldrb r3, [r7, #23] + 801630a: b29c uxth r4, r3 + 801630c: 687b ldr r3, [r7, #4] + 801630e: 6d1b ldr r3, [r3, #80] ; 0x50 + 8016310: 3b01 subs r3, #1 + 8016312: 4618 mov r0, r3 + 8016314: f7f7 ffa1 bl 800e25a + 8016318: 4603 mov r3, r0 + 801631a: 2200 movs r2, #0 + 801631c: 4621 mov r1, r4 + 801631e: 6878 ldr r0, [r7, #4] + 8016320: f7ff fe66 bl 8015ff0 + 8016324: 6138 str r0, [r7, #16] + if (p == NULL) { + 8016326: 693b ldr r3, [r7, #16] + 8016328: 2b00 cmp r3, #0 + 801632a: d102 bne.n 8016332 + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_keepalive: could not allocate memory for pbuf\n")); + return ERR_MEM; + 801632c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8016330: e010 b.n 8016354 + } + tcp_output_fill_options(pcb, p, 0, optlen); + 8016332: 7dfb ldrb r3, [r7, #23] + 8016334: 2200 movs r2, #0 + 8016336: 6939 ldr r1, [r7, #16] + 8016338: 6878 ldr r0, [r7, #4] + 801633a: f7ff fe97 bl 801606c + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 801633e: 687a ldr r2, [r7, #4] + 8016340: 687b ldr r3, [r7, #4] + 8016342: 3304 adds r3, #4 + 8016344: 6939 ldr r1, [r7, #16] + 8016346: 6878 ldr r0, [r7, #4] + 8016348: f7ff fed0 bl 80160ec + 801634c: 4603 mov r3, r0 + 801634e: 73fb strb r3, [r7, #15] + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; + 8016350: f997 300f ldrsb.w r3, [r7, #15] +} + 8016354: 4618 mov r0, r3 + 8016356: 371c adds r7, #28 + 8016358: 46bd mov sp, r7 + 801635a: bd90 pop {r4, r7, pc} + 801635c: 08020108 .word 0x08020108 + 8016360: 080208e4 .word 0x080208e4 + 8016364: 0802015c .word 0x0802015c + +08016368 : + * + * @param pcb the tcp_pcb for which to send a zero-window probe packet + */ +err_t +tcp_zero_window_probe(struct tcp_pcb *pcb) +{ + 8016368: b590 push {r4, r7, lr} + 801636a: b08b sub sp, #44 ; 0x2c + 801636c: af00 add r7, sp, #0 + 801636e: 6078 str r0, [r7, #4] + struct tcp_hdr *tcphdr; + struct tcp_seg *seg; + u16_t len; + u8_t is_fin; + u32_t snd_nxt; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 8016370: 2300 movs r3, #0 + 8016372: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL); + 8016376: 687b ldr r3, [r7, #4] + 8016378: 2b00 cmp r3, #0 + 801637a: d106 bne.n 801638a + 801637c: 4b4c ldr r3, [pc, #304] ; (80164b0 ) + 801637e: f640 024f movw r2, #2127 ; 0x84f + 8016382: 494c ldr r1, [pc, #304] ; (80164b4 ) + 8016384: 484c ldr r0, [pc, #304] ; (80164b8 ) + 8016386: f005 fe45 bl 801c014 + ("tcp_zero_window_probe: tcp_ticks %"U32_F + " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + /* Only consider unsent, persist timer should be off when there is data in-flight */ + seg = pcb->unsent; + 801638a: 687b ldr r3, [r7, #4] + 801638c: 6edb ldr r3, [r3, #108] ; 0x6c + 801638e: 623b str r3, [r7, #32] + if (seg == NULL) { + 8016390: 6a3b ldr r3, [r7, #32] + 8016392: 2b00 cmp r3, #0 + 8016394: d101 bne.n 801639a + /* Not expected, persist timer should be off when the send buffer is empty */ + return ERR_OK; + 8016396: 2300 movs r3, #0 + 8016398: e086 b.n 80164a8 + + /* increment probe count. NOTE: we record probe even if it fails + to actually transmit due to an error. This ensures memory exhaustion/ + routing problem doesn't leave a zero-window pcb as an indefinite zombie. + RTO mechanism has similar behavior, see pcb->nrtx */ + if (pcb->persist_probe < 0xFF) { + 801639a: 687b ldr r3, [r7, #4] + 801639c: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 80163a0: 2bff cmp r3, #255 ; 0xff + 80163a2: d007 beq.n 80163b4 + ++pcb->persist_probe; + 80163a4: 687b ldr r3, [r7, #4] + 80163a6: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 80163aa: 3301 adds r3, #1 + 80163ac: b2da uxtb r2, r3 + 80163ae: 687b ldr r3, [r7, #4] + 80163b0: f883 209a strb.w r2, [r3, #154] ; 0x9a + } + + is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); + 80163b4: 6a3b ldr r3, [r7, #32] + 80163b6: 68db ldr r3, [r3, #12] + 80163b8: 899b ldrh r3, [r3, #12] + 80163ba: b29b uxth r3, r3 + 80163bc: 4618 mov r0, r3 + 80163be: f7f7 ff37 bl 800e230 + 80163c2: 4603 mov r3, r0 + 80163c4: b2db uxtb r3, r3 + 80163c6: f003 0301 and.w r3, r3, #1 + 80163ca: 2b00 cmp r3, #0 + 80163cc: d005 beq.n 80163da + 80163ce: 6a3b ldr r3, [r7, #32] + 80163d0: 891b ldrh r3, [r3, #8] + 80163d2: 2b00 cmp r3, #0 + 80163d4: d101 bne.n 80163da + 80163d6: 2301 movs r3, #1 + 80163d8: e000 b.n 80163dc + 80163da: 2300 movs r3, #0 + 80163dc: 77fb strb r3, [r7, #31] + /* we want to send one seqno: either FIN or data (no options) */ + len = is_fin ? 0 : 1; + 80163de: 7ffb ldrb r3, [r7, #31] + 80163e0: 2b00 cmp r3, #0 + 80163e2: bf0c ite eq + 80163e4: 2301 moveq r3, #1 + 80163e6: 2300 movne r3, #0 + 80163e8: b2db uxtb r3, r3 + 80163ea: 83bb strh r3, [r7, #28] + + p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno); + 80163ec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80163f0: b299 uxth r1, r3 + 80163f2: 6a3b ldr r3, [r7, #32] + 80163f4: 68db ldr r3, [r3, #12] + 80163f6: 685b ldr r3, [r3, #4] + 80163f8: 8bba ldrh r2, [r7, #28] + 80163fa: 6878 ldr r0, [r7, #4] + 80163fc: f7ff fdf8 bl 8015ff0 + 8016400: 61b8 str r0, [r7, #24] + if (p == NULL) { + 8016402: 69bb ldr r3, [r7, #24] + 8016404: 2b00 cmp r3, #0 + 8016406: d102 bne.n 801640e + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); + return ERR_MEM; + 8016408: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801640c: e04c b.n 80164a8 + } + tcphdr = (struct tcp_hdr *)p->payload; + 801640e: 69bb ldr r3, [r7, #24] + 8016410: 685b ldr r3, [r3, #4] + 8016412: 617b str r3, [r7, #20] + + if (is_fin) { + 8016414: 7ffb ldrb r3, [r7, #31] + 8016416: 2b00 cmp r3, #0 + 8016418: d011 beq.n 801643e + /* FIN segment, no data */ + TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); + 801641a: 697b ldr r3, [r7, #20] + 801641c: 899b ldrh r3, [r3, #12] + 801641e: b29b uxth r3, r3 + 8016420: b21b sxth r3, r3 + 8016422: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 8016426: b21c sxth r4, r3 + 8016428: 2011 movs r0, #17 + 801642a: f7f7 ff01 bl 800e230 + 801642e: 4603 mov r3, r0 + 8016430: b21b sxth r3, r3 + 8016432: 4323 orrs r3, r4 + 8016434: b21b sxth r3, r3 + 8016436: b29a uxth r2, r3 + 8016438: 697b ldr r3, [r7, #20] + 801643a: 819a strh r2, [r3, #12] + 801643c: e010 b.n 8016460 + } else { + /* Data segment, copy in one byte from the head of the unacked queue */ + char *d = ((char *)p->payload + TCP_HLEN); + 801643e: 69bb ldr r3, [r7, #24] + 8016440: 685b ldr r3, [r3, #4] + 8016442: 3314 adds r3, #20 + 8016444: 613b str r3, [r7, #16] + /* Depending on whether the segment has already been sent (unacked) or not + (unsent), seg->p->payload points to the IP header or TCP header. + Ensure we copy the first TCP data byte: */ + pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len); + 8016446: 6a3b ldr r3, [r7, #32] + 8016448: 6858 ldr r0, [r3, #4] + 801644a: 6a3b ldr r3, [r7, #32] + 801644c: 685b ldr r3, [r3, #4] + 801644e: 891a ldrh r2, [r3, #8] + 8016450: 6a3b ldr r3, [r7, #32] + 8016452: 891b ldrh r3, [r3, #8] + 8016454: 1ad3 subs r3, r2, r3 + 8016456: b29b uxth r3, r3 + 8016458: 2201 movs r2, #1 + 801645a: 6939 ldr r1, [r7, #16] + 801645c: f7fa fcd6 bl 8010e0c + } + + /* The byte may be acknowledged without the window being opened. */ + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1; + 8016460: 6a3b ldr r3, [r7, #32] + 8016462: 68db ldr r3, [r3, #12] + 8016464: 685b ldr r3, [r3, #4] + 8016466: 4618 mov r0, r3 + 8016468: f7f7 fef7 bl 800e25a + 801646c: 4603 mov r3, r0 + 801646e: 3301 adds r3, #1 + 8016470: 60fb str r3, [r7, #12] + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + 8016472: 687b ldr r3, [r7, #4] + 8016474: 6d1a ldr r2, [r3, #80] ; 0x50 + 8016476: 68fb ldr r3, [r7, #12] + 8016478: 1ad3 subs r3, r2, r3 + 801647a: 2b00 cmp r3, #0 + 801647c: da02 bge.n 8016484 + pcb->snd_nxt = snd_nxt; + 801647e: 687b ldr r3, [r7, #4] + 8016480: 68fa ldr r2, [r7, #12] + 8016482: 651a str r2, [r3, #80] ; 0x50 + } + tcp_output_fill_options(pcb, p, 0, optlen); + 8016484: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8016488: 2200 movs r2, #0 + 801648a: 69b9 ldr r1, [r7, #24] + 801648c: 6878 ldr r0, [r7, #4] + 801648e: f7ff fded bl 801606c + + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 8016492: 687a ldr r2, [r7, #4] + 8016494: 687b ldr r3, [r7, #4] + 8016496: 3304 adds r3, #4 + 8016498: 69b9 ldr r1, [r7, #24] + 801649a: 6878 ldr r0, [r7, #4] + 801649c: f7ff fe26 bl 80160ec + 80164a0: 4603 mov r3, r0 + 80164a2: 72fb strb r3, [r7, #11] + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F + " ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; + 80164a4: f997 300b ldrsb.w r3, [r7, #11] +} + 80164a8: 4618 mov r0, r3 + 80164aa: 372c adds r7, #44 ; 0x2c + 80164ac: 46bd mov sp, r7 + 80164ae: bd90 pop {r4, r7, pc} + 80164b0: 08020108 .word 0x08020108 + 80164b4: 08020900 .word 0x08020900 + 80164b8: 0802015c .word 0x0802015c + +080164bc : + * + * @param arg unused argument + */ +static void +tcpip_tcp_timer(void *arg) +{ + 80164bc: b580 push {r7, lr} + 80164be: b082 sub sp, #8 + 80164c0: af00 add r7, sp, #0 + 80164c2: 6078 str r0, [r7, #4] + LWIP_UNUSED_ARG(arg); + + /* call TCP timer handler */ + tcp_tmr(); + 80164c4: f7fa ff0c bl 80112e0 + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + 80164c8: 4b0a ldr r3, [pc, #40] ; (80164f4 ) + 80164ca: 681b ldr r3, [r3, #0] + 80164cc: 2b00 cmp r3, #0 + 80164ce: d103 bne.n 80164d8 + 80164d0: 4b09 ldr r3, [pc, #36] ; (80164f8 ) + 80164d2: 681b ldr r3, [r3, #0] + 80164d4: 2b00 cmp r3, #0 + 80164d6: d005 beq.n 80164e4 + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + 80164d8: 2200 movs r2, #0 + 80164da: 4908 ldr r1, [pc, #32] ; (80164fc ) + 80164dc: 20fa movs r0, #250 ; 0xfa + 80164de: f000 f8f3 bl 80166c8 + 80164e2: e003 b.n 80164ec + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + 80164e4: 4b06 ldr r3, [pc, #24] ; (8016500 ) + 80164e6: 2200 movs r2, #0 + 80164e8: 601a str r2, [r3, #0] + } +} + 80164ea: bf00 nop + 80164ec: bf00 nop + 80164ee: 3708 adds r7, #8 + 80164f0: 46bd mov sp, r7 + 80164f2: bd80 pop {r7, pc} + 80164f4: 2000cf3c .word 0x2000cf3c + 80164f8: 2000cf40 .word 0x2000cf40 + 80164fc: 080164bd .word 0x080164bd + 8016500: 2000cf88 .word 0x2000cf88 + +08016504 : + * the reason is to have the TCP timer only running when + * there are active (or time-wait) PCBs. + */ +void +tcp_timer_needed(void) +{ + 8016504: b580 push {r7, lr} + 8016506: af00 add r7, sp, #0 + LWIP_ASSERT_CORE_LOCKED(); + + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + 8016508: 4b0a ldr r3, [pc, #40] ; (8016534 ) + 801650a: 681b ldr r3, [r3, #0] + 801650c: 2b00 cmp r3, #0 + 801650e: d10f bne.n 8016530 + 8016510: 4b09 ldr r3, [pc, #36] ; (8016538 ) + 8016512: 681b ldr r3, [r3, #0] + 8016514: 2b00 cmp r3, #0 + 8016516: d103 bne.n 8016520 + 8016518: 4b08 ldr r3, [pc, #32] ; (801653c ) + 801651a: 681b ldr r3, [r3, #0] + 801651c: 2b00 cmp r3, #0 + 801651e: d007 beq.n 8016530 + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + 8016520: 4b04 ldr r3, [pc, #16] ; (8016534 ) + 8016522: 2201 movs r2, #1 + 8016524: 601a str r2, [r3, #0] + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + 8016526: 2200 movs r2, #0 + 8016528: 4905 ldr r1, [pc, #20] ; (8016540 ) + 801652a: 20fa movs r0, #250 ; 0xfa + 801652c: f000 f8cc bl 80166c8 + } +} + 8016530: bf00 nop + 8016532: bd80 pop {r7, pc} + 8016534: 2000cf88 .word 0x2000cf88 + 8016538: 2000cf3c .word 0x2000cf3c + 801653c: 2000cf40 .word 0x2000cf40 + 8016540: 080164bd .word 0x080164bd + +08016544 : +#if LWIP_DEBUG_TIMERNAMES +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg) +#endif +{ + 8016544: b580 push {r7, lr} + 8016546: b086 sub sp, #24 + 8016548: af00 add r7, sp, #0 + 801654a: 60f8 str r0, [r7, #12] + 801654c: 60b9 str r1, [r7, #8] + 801654e: 607a str r2, [r7, #4] + struct sys_timeo *timeout, *t; + + timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); + 8016550: 200a movs r0, #10 + 8016552: f7f9 fb2f bl 800fbb4 + 8016556: 6138 str r0, [r7, #16] + if (timeout == NULL) { + 8016558: 693b ldr r3, [r7, #16] + 801655a: 2b00 cmp r3, #0 + 801655c: d109 bne.n 8016572 + LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); + 801655e: 693b ldr r3, [r7, #16] + 8016560: 2b00 cmp r3, #0 + 8016562: d151 bne.n 8016608 + 8016564: 4b2a ldr r3, [pc, #168] ; (8016610 ) + 8016566: 22be movs r2, #190 ; 0xbe + 8016568: 492a ldr r1, [pc, #168] ; (8016614 ) + 801656a: 482b ldr r0, [pc, #172] ; (8016618 ) + 801656c: f005 fd52 bl 801c014 + return; + 8016570: e04a b.n 8016608 + } + + timeout->next = NULL; + 8016572: 693b ldr r3, [r7, #16] + 8016574: 2200 movs r2, #0 + 8016576: 601a str r2, [r3, #0] + timeout->h = handler; + 8016578: 693b ldr r3, [r7, #16] + 801657a: 68ba ldr r2, [r7, #8] + 801657c: 609a str r2, [r3, #8] + timeout->arg = arg; + 801657e: 693b ldr r3, [r7, #16] + 8016580: 687a ldr r2, [r7, #4] + 8016582: 60da str r2, [r3, #12] + timeout->time = abs_time; + 8016584: 693b ldr r3, [r7, #16] + 8016586: 68fa ldr r2, [r7, #12] + 8016588: 605a str r2, [r3, #4] + timeout->handler_name = handler_name; + LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n", + (void *)timeout, abs_time, handler_name, (void *)arg)); +#endif /* LWIP_DEBUG_TIMERNAMES */ + + if (next_timeout == NULL) { + 801658a: 4b24 ldr r3, [pc, #144] ; (801661c ) + 801658c: 681b ldr r3, [r3, #0] + 801658e: 2b00 cmp r3, #0 + 8016590: d103 bne.n 801659a + next_timeout = timeout; + 8016592: 4a22 ldr r2, [pc, #136] ; (801661c ) + 8016594: 693b ldr r3, [r7, #16] + 8016596: 6013 str r3, [r2, #0] + return; + 8016598: e037 b.n 801660a + } + if (TIME_LESS_THAN(timeout->time, next_timeout->time)) { + 801659a: 693b ldr r3, [r7, #16] + 801659c: 685a ldr r2, [r3, #4] + 801659e: 4b1f ldr r3, [pc, #124] ; (801661c ) + 80165a0: 681b ldr r3, [r3, #0] + 80165a2: 685b ldr r3, [r3, #4] + 80165a4: 1ad3 subs r3, r2, r3 + 80165a6: 0fdb lsrs r3, r3, #31 + 80165a8: f003 0301 and.w r3, r3, #1 + 80165ac: b2db uxtb r3, r3 + 80165ae: 2b00 cmp r3, #0 + 80165b0: d007 beq.n 80165c2 + timeout->next = next_timeout; + 80165b2: 4b1a ldr r3, [pc, #104] ; (801661c ) + 80165b4: 681a ldr r2, [r3, #0] + 80165b6: 693b ldr r3, [r7, #16] + 80165b8: 601a str r2, [r3, #0] + next_timeout = timeout; + 80165ba: 4a18 ldr r2, [pc, #96] ; (801661c ) + 80165bc: 693b ldr r3, [r7, #16] + 80165be: 6013 str r3, [r2, #0] + 80165c0: e023 b.n 801660a + } else { + for (t = next_timeout; t != NULL; t = t->next) { + 80165c2: 4b16 ldr r3, [pc, #88] ; (801661c ) + 80165c4: 681b ldr r3, [r3, #0] + 80165c6: 617b str r3, [r7, #20] + 80165c8: e01a b.n 8016600 + if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) { + 80165ca: 697b ldr r3, [r7, #20] + 80165cc: 681b ldr r3, [r3, #0] + 80165ce: 2b00 cmp r3, #0 + 80165d0: d00b beq.n 80165ea + 80165d2: 693b ldr r3, [r7, #16] + 80165d4: 685a ldr r2, [r3, #4] + 80165d6: 697b ldr r3, [r7, #20] + 80165d8: 681b ldr r3, [r3, #0] + 80165da: 685b ldr r3, [r3, #4] + 80165dc: 1ad3 subs r3, r2, r3 + 80165de: 0fdb lsrs r3, r3, #31 + 80165e0: f003 0301 and.w r3, r3, #1 + 80165e4: b2db uxtb r3, r3 + 80165e6: 2b00 cmp r3, #0 + 80165e8: d007 beq.n 80165fa + timeout->next = t->next; + 80165ea: 697b ldr r3, [r7, #20] + 80165ec: 681a ldr r2, [r3, #0] + 80165ee: 693b ldr r3, [r7, #16] + 80165f0: 601a str r2, [r3, #0] + t->next = timeout; + 80165f2: 697b ldr r3, [r7, #20] + 80165f4: 693a ldr r2, [r7, #16] + 80165f6: 601a str r2, [r3, #0] + break; + 80165f8: e007 b.n 801660a + for (t = next_timeout; t != NULL; t = t->next) { + 80165fa: 697b ldr r3, [r7, #20] + 80165fc: 681b ldr r3, [r3, #0] + 80165fe: 617b str r3, [r7, #20] + 8016600: 697b ldr r3, [r7, #20] + 8016602: 2b00 cmp r3, #0 + 8016604: d1e1 bne.n 80165ca + 8016606: e000 b.n 801660a + return; + 8016608: bf00 nop + } + } + } +} + 801660a: 3718 adds r7, #24 + 801660c: 46bd mov sp, r7 + 801660e: bd80 pop {r7, pc} + 8016610: 08020924 .word 0x08020924 + 8016614: 08020958 .word 0x08020958 + 8016618: 08020998 .word 0x08020998 + 801661c: 2000cf80 .word 0x2000cf80 + +08016620 : +#if !LWIP_TESTMODE +static +#endif +void +lwip_cyclic_timer(void *arg) +{ + 8016620: b580 push {r7, lr} + 8016622: b086 sub sp, #24 + 8016624: af00 add r7, sp, #0 + 8016626: 6078 str r0, [r7, #4] + u32_t now; + u32_t next_timeout_time; + const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg; + 8016628: 687b ldr r3, [r7, #4] + 801662a: 617b str r3, [r7, #20] + +#if LWIP_DEBUG_TIMERNAMES + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); +#endif + cyclic->handler(); + 801662c: 697b ldr r3, [r7, #20] + 801662e: 685b ldr r3, [r3, #4] + 8016630: 4798 blx r3 + + now = sys_now(); + 8016632: f7f4 faff bl 800ac34 + 8016636: 6138 str r0, [r7, #16] + next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */ + 8016638: 697b ldr r3, [r7, #20] + 801663a: 681a ldr r2, [r3, #0] + 801663c: 4b0f ldr r3, [pc, #60] ; (801667c ) + 801663e: 681b ldr r3, [r3, #0] + 8016640: 4413 add r3, r2 + 8016642: 60fb str r3, [r7, #12] + if (TIME_LESS_THAN(next_timeout_time, now)) { + 8016644: 68fa ldr r2, [r7, #12] + 8016646: 693b ldr r3, [r7, #16] + 8016648: 1ad3 subs r3, r2, r3 + 801664a: 0fdb lsrs r3, r3, #31 + 801664c: f003 0301 and.w r3, r3, #1 + 8016650: b2db uxtb r3, r3 + 8016652: 2b00 cmp r3, #0 + 8016654: d009 beq.n 801666a + /* timer would immediately expire again -> "overload" -> restart without any correction */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg); + 8016656: 697b ldr r3, [r7, #20] + 8016658: 681a ldr r2, [r3, #0] + 801665a: 693b ldr r3, [r7, #16] + 801665c: 4413 add r3, r2 + 801665e: 687a ldr r2, [r7, #4] + 8016660: 4907 ldr r1, [pc, #28] ; (8016680 ) + 8016662: 4618 mov r0, r3 + 8016664: f7ff ff6e bl 8016544 + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); +#endif + } +} + 8016668: e004 b.n 8016674 + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); + 801666a: 687a ldr r2, [r7, #4] + 801666c: 4904 ldr r1, [pc, #16] ; (8016680 ) + 801666e: 68f8 ldr r0, [r7, #12] + 8016670: f7ff ff68 bl 8016544 +} + 8016674: bf00 nop + 8016676: 3718 adds r7, #24 + 8016678: 46bd mov sp, r7 + 801667a: bd80 pop {r7, pc} + 801667c: 2000cf84 .word 0x2000cf84 + 8016680: 08016621 .word 0x08016621 + +08016684 : + +/** Initialize this module */ +void sys_timeouts_init(void) +{ + 8016684: b580 push {r7, lr} + 8016686: b082 sub sp, #8 + 8016688: af00 add r7, sp, #0 + size_t i; + /* tcp_tmr() at index 0 is started on demand */ + for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { + 801668a: 2301 movs r3, #1 + 801668c: 607b str r3, [r7, #4] + 801668e: e00e b.n 80166ae + /* we have to cast via size_t to get rid of const warning + (this is OK as cyclic_timer() casts back to const* */ + sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i])); + 8016690: 4a0b ldr r2, [pc, #44] ; (80166c0 ) + 8016692: 687b ldr r3, [r7, #4] + 8016694: f852 0033 ldr.w r0, [r2, r3, lsl #3] + 8016698: 687b ldr r3, [r7, #4] + 801669a: 00db lsls r3, r3, #3 + 801669c: 4a08 ldr r2, [pc, #32] ; (80166c0 ) + 801669e: 4413 add r3, r2 + 80166a0: 461a mov r2, r3 + 80166a2: 4908 ldr r1, [pc, #32] ; (80166c4 ) + 80166a4: f000 f810 bl 80166c8 + for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { + 80166a8: 687b ldr r3, [r7, #4] + 80166aa: 3301 adds r3, #1 + 80166ac: 607b str r3, [r7, #4] + 80166ae: 687b ldr r3, [r7, #4] + 80166b0: 2b05 cmp r3, #5 + 80166b2: d9ed bls.n 8016690 + } +} + 80166b4: bf00 nop + 80166b6: bf00 nop + 80166b8: 3708 adds r7, #8 + 80166ba: 46bd mov sp, r7 + 80166bc: bd80 pop {r7, pc} + 80166be: bf00 nop + 80166c0: 080238e4 .word 0x080238e4 + 80166c4: 08016621 .word 0x08016621 + +080166c8 : +sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +void +sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) +#endif /* LWIP_DEBUG_TIMERNAMES */ +{ + 80166c8: b580 push {r7, lr} + 80166ca: b086 sub sp, #24 + 80166cc: af00 add r7, sp, #0 + 80166ce: 60f8 str r0, [r7, #12] + 80166d0: 60b9 str r1, [r7, #8] + 80166d2: 607a str r2, [r7, #4] + u32_t next_timeout_time; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4)); + 80166d4: 68fb ldr r3, [r7, #12] + 80166d6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 80166da: d306 bcc.n 80166ea + 80166dc: 4b0a ldr r3, [pc, #40] ; (8016708 ) + 80166de: f240 1229 movw r2, #297 ; 0x129 + 80166e2: 490a ldr r1, [pc, #40] ; (801670c ) + 80166e4: 480a ldr r0, [pc, #40] ; (8016710 ) + 80166e6: f005 fc95 bl 801c014 + + next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ + 80166ea: f7f4 faa3 bl 800ac34 + 80166ee: 4602 mov r2, r0 + 80166f0: 68fb ldr r3, [r7, #12] + 80166f2: 4413 add r3, r2 + 80166f4: 617b str r3, [r7, #20] + +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, handler, arg, handler_name); +#else + sys_timeout_abs(next_timeout_time, handler, arg); + 80166f6: 687a ldr r2, [r7, #4] + 80166f8: 68b9 ldr r1, [r7, #8] + 80166fa: 6978 ldr r0, [r7, #20] + 80166fc: f7ff ff22 bl 8016544 +#endif +} + 8016700: bf00 nop + 8016702: 3718 adds r7, #24 + 8016704: 46bd mov sp, r7 + 8016706: bd80 pop {r7, pc} + 8016708: 08020924 .word 0x08020924 + 801670c: 080209c0 .word 0x080209c0 + 8016710: 08020998 .word 0x08020998 + +08016714 : + * + * Must be called periodically from your main loop. + */ +void +sys_check_timeouts(void) +{ + 8016714: b580 push {r7, lr} + 8016716: b084 sub sp, #16 + 8016718: af00 add r7, sp, #0 + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Process only timers expired at the start of the function. */ + now = sys_now(); + 801671a: f7f4 fa8b bl 800ac34 + 801671e: 60f8 str r0, [r7, #12] + sys_timeout_handler handler; + void *arg; + + PBUF_CHECK_FREE_OOSEQ(); + + tmptimeout = next_timeout; + 8016720: 4b17 ldr r3, [pc, #92] ; (8016780 ) + 8016722: 681b ldr r3, [r3, #0] + 8016724: 60bb str r3, [r7, #8] + if (tmptimeout == NULL) { + 8016726: 68bb ldr r3, [r7, #8] + 8016728: 2b00 cmp r3, #0 + 801672a: d022 beq.n 8016772 + return; + } + + if (TIME_LESS_THAN(now, tmptimeout->time)) { + 801672c: 68bb ldr r3, [r7, #8] + 801672e: 685b ldr r3, [r3, #4] + 8016730: 68fa ldr r2, [r7, #12] + 8016732: 1ad3 subs r3, r2, r3 + 8016734: 0fdb lsrs r3, r3, #31 + 8016736: f003 0301 and.w r3, r3, #1 + 801673a: b2db uxtb r3, r3 + 801673c: 2b00 cmp r3, #0 + 801673e: d11a bne.n 8016776 + return; + } + + /* Timeout has expired */ + next_timeout = tmptimeout->next; + 8016740: 68bb ldr r3, [r7, #8] + 8016742: 681b ldr r3, [r3, #0] + 8016744: 4a0e ldr r2, [pc, #56] ; (8016780 ) + 8016746: 6013 str r3, [r2, #0] + handler = tmptimeout->h; + 8016748: 68bb ldr r3, [r7, #8] + 801674a: 689b ldr r3, [r3, #8] + 801674c: 607b str r3, [r7, #4] + arg = tmptimeout->arg; + 801674e: 68bb ldr r3, [r7, #8] + 8016750: 68db ldr r3, [r3, #12] + 8016752: 603b str r3, [r7, #0] + current_timeout_due_time = tmptimeout->time; + 8016754: 68bb ldr r3, [r7, #8] + 8016756: 685b ldr r3, [r3, #4] + 8016758: 4a0a ldr r2, [pc, #40] ; (8016784 ) + 801675a: 6013 str r3, [r2, #0] + if (handler != NULL) { + LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n", + tmptimeout->handler_name, sys_now() - tmptimeout->time, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + 801675c: 68b9 ldr r1, [r7, #8] + 801675e: 200a movs r0, #10 + 8016760: f7f9 fa9e bl 800fca0 + if (handler != NULL) { + 8016764: 687b ldr r3, [r7, #4] + 8016766: 2b00 cmp r3, #0 + 8016768: d0da beq.n 8016720 + handler(arg); + 801676a: 687b ldr r3, [r7, #4] + 801676c: 6838 ldr r0, [r7, #0] + 801676e: 4798 blx r3 + do { + 8016770: e7d6 b.n 8016720 + return; + 8016772: bf00 nop + 8016774: e000 b.n 8016778 + return; + 8016776: bf00 nop + } + LWIP_TCPIP_THREAD_ALIVE(); + + /* Repeat until all expired timers have been called */ + } while (1); +} + 8016778: 3710 adds r7, #16 + 801677a: 46bd mov sp, r7 + 801677c: bd80 pop {r7, pc} + 801677e: bf00 nop + 8016780: 2000cf80 .word 0x2000cf80 + 8016784: 2000cf84 .word 0x2000cf84 + +08016788 : +/** Return the time left before the next timeout is due. If no timeouts are + * enqueued, returns 0xffffffff + */ +u32_t +sys_timeouts_sleeptime(void) +{ + 8016788: b580 push {r7, lr} + 801678a: b082 sub sp, #8 + 801678c: af00 add r7, sp, #0 + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + if (next_timeout == NULL) { + 801678e: 4b16 ldr r3, [pc, #88] ; (80167e8 ) + 8016790: 681b ldr r3, [r3, #0] + 8016792: 2b00 cmp r3, #0 + 8016794: d102 bne.n 801679c + return SYS_TIMEOUTS_SLEEPTIME_INFINITE; + 8016796: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801679a: e020 b.n 80167de + } + now = sys_now(); + 801679c: f7f4 fa4a bl 800ac34 + 80167a0: 6078 str r0, [r7, #4] + if (TIME_LESS_THAN(next_timeout->time, now)) { + 80167a2: 4b11 ldr r3, [pc, #68] ; (80167e8 ) + 80167a4: 681b ldr r3, [r3, #0] + 80167a6: 685a ldr r2, [r3, #4] + 80167a8: 687b ldr r3, [r7, #4] + 80167aa: 1ad3 subs r3, r2, r3 + 80167ac: 0fdb lsrs r3, r3, #31 + 80167ae: f003 0301 and.w r3, r3, #1 + 80167b2: b2db uxtb r3, r3 + 80167b4: 2b00 cmp r3, #0 + 80167b6: d001 beq.n 80167bc + return 0; + 80167b8: 2300 movs r3, #0 + 80167ba: e010 b.n 80167de + } else { + u32_t ret = (u32_t)(next_timeout->time - now); + 80167bc: 4b0a ldr r3, [pc, #40] ; (80167e8 ) + 80167be: 681b ldr r3, [r3, #0] + 80167c0: 685a ldr r2, [r3, #4] + 80167c2: 687b ldr r3, [r7, #4] + 80167c4: 1ad3 subs r3, r2, r3 + 80167c6: 603b str r3, [r7, #0] + LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT); + 80167c8: 683b ldr r3, [r7, #0] + 80167ca: 2b00 cmp r3, #0 + 80167cc: da06 bge.n 80167dc + 80167ce: 4b07 ldr r3, [pc, #28] ; (80167ec ) + 80167d0: f44f 72dc mov.w r2, #440 ; 0x1b8 + 80167d4: 4906 ldr r1, [pc, #24] ; (80167f0 ) + 80167d6: 4807 ldr r0, [pc, #28] ; (80167f4 ) + 80167d8: f005 fc1c bl 801c014 + return ret; + 80167dc: 683b ldr r3, [r7, #0] + } +} + 80167de: 4618 mov r0, r3 + 80167e0: 3708 adds r7, #8 + 80167e2: 46bd mov sp, r7 + 80167e4: bd80 pop {r7, pc} + 80167e6: bf00 nop + 80167e8: 2000cf80 .word 0x2000cf80 + 80167ec: 08020924 .word 0x08020924 + 80167f0: 080209f8 .word 0x080209f8 + 80167f4: 08020998 .word 0x08020998 + +080167f8 : +/** + * Initialize this module. + */ +void +udp_init(void) +{ + 80167f8: b580 push {r7, lr} + 80167fa: af00 add r7, sp, #0 +#ifdef LWIP_RAND + udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); + 80167fc: f005 fc98 bl 801c130 + 8016800: 4603 mov r3, r0 + 8016802: b29b uxth r3, r3 + 8016804: f3c3 030d ubfx r3, r3, #0, #14 + 8016808: b29b uxth r3, r3 + 801680a: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 + 801680e: b29a uxth r2, r3 + 8016810: 4b01 ldr r3, [pc, #4] ; (8016818 ) + 8016812: 801a strh r2, [r3, #0] +#endif /* LWIP_RAND */ +} + 8016814: bf00 nop + 8016816: bd80 pop {r7, pc} + 8016818: 200000bc .word 0x200000bc + +0801681c : + * + * @return a new (free) local UDP port number + */ +static u16_t +udp_new_port(void) +{ + 801681c: b480 push {r7} + 801681e: b083 sub sp, #12 + 8016820: af00 add r7, sp, #0 + u16_t n = 0; + 8016822: 2300 movs r3, #0 + 8016824: 80fb strh r3, [r7, #6] + struct udp_pcb *pcb; + +again: + if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) { + 8016826: 4b17 ldr r3, [pc, #92] ; (8016884 ) + 8016828: 881b ldrh r3, [r3, #0] + 801682a: 1c5a adds r2, r3, #1 + 801682c: b291 uxth r1, r2 + 801682e: 4a15 ldr r2, [pc, #84] ; (8016884 ) + 8016830: 8011 strh r1, [r2, #0] + 8016832: f64f 72ff movw r2, #65535 ; 0xffff + 8016836: 4293 cmp r3, r2 + 8016838: d103 bne.n 8016842 + udp_port = UDP_LOCAL_PORT_RANGE_START; + 801683a: 4b12 ldr r3, [pc, #72] ; (8016884 ) + 801683c: f44f 4240 mov.w r2, #49152 ; 0xc000 + 8016840: 801a strh r2, [r3, #0] + } + /* Check all PCBs. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 8016842: 4b11 ldr r3, [pc, #68] ; (8016888 ) + 8016844: 681b ldr r3, [r3, #0] + 8016846: 603b str r3, [r7, #0] + 8016848: e011 b.n 801686e + if (pcb->local_port == udp_port) { + 801684a: 683b ldr r3, [r7, #0] + 801684c: 8a5a ldrh r2, [r3, #18] + 801684e: 4b0d ldr r3, [pc, #52] ; (8016884 ) + 8016850: 881b ldrh r3, [r3, #0] + 8016852: 429a cmp r2, r3 + 8016854: d108 bne.n 8016868 + if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) { + 8016856: 88fb ldrh r3, [r7, #6] + 8016858: 3301 adds r3, #1 + 801685a: 80fb strh r3, [r7, #6] + 801685c: 88fb ldrh r3, [r7, #6] + 801685e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8016862: d3e0 bcc.n 8016826 + return 0; + 8016864: 2300 movs r3, #0 + 8016866: e007 b.n 8016878 + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 8016868: 683b ldr r3, [r7, #0] + 801686a: 68db ldr r3, [r3, #12] + 801686c: 603b str r3, [r7, #0] + 801686e: 683b ldr r3, [r7, #0] + 8016870: 2b00 cmp r3, #0 + 8016872: d1ea bne.n 801684a + } + goto again; + } + } + return udp_port; + 8016874: 4b03 ldr r3, [pc, #12] ; (8016884 ) + 8016876: 881b ldrh r3, [r3, #0] +} + 8016878: 4618 mov r0, r3 + 801687a: 370c adds r7, #12 + 801687c: 46bd mov sp, r7 + 801687e: f85d 7b04 ldr.w r7, [sp], #4 + 8016882: 4770 bx lr + 8016884: 200000bc .word 0x200000bc + 8016888: 2000cf8c .word 0x2000cf8c + +0801688c : + * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4) + * @return 1 on match, 0 otherwise + */ +static u8_t +udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast) +{ + 801688c: b580 push {r7, lr} + 801688e: b084 sub sp, #16 + 8016890: af00 add r7, sp, #0 + 8016892: 60f8 str r0, [r7, #12] + 8016894: 60b9 str r1, [r7, #8] + 8016896: 4613 mov r3, r2 + 8016898: 71fb strb r3, [r7, #7] + LWIP_UNUSED_ARG(inp); /* in IPv6 only case */ + LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ + + LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL); + 801689a: 68fb ldr r3, [r7, #12] + 801689c: 2b00 cmp r3, #0 + 801689e: d105 bne.n 80168ac + 80168a0: 4b27 ldr r3, [pc, #156] ; (8016940 ) + 80168a2: 2287 movs r2, #135 ; 0x87 + 80168a4: 4927 ldr r1, [pc, #156] ; (8016944 ) + 80168a6: 4828 ldr r0, [pc, #160] ; (8016948 ) + 80168a8: f005 fbb4 bl 801c014 + LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL); + 80168ac: 68bb ldr r3, [r7, #8] + 80168ae: 2b00 cmp r3, #0 + 80168b0: d105 bne.n 80168be + 80168b2: 4b23 ldr r3, [pc, #140] ; (8016940 ) + 80168b4: 2288 movs r2, #136 ; 0x88 + 80168b6: 4925 ldr r1, [pc, #148] ; (801694c ) + 80168b8: 4823 ldr r0, [pc, #140] ; (8016948 ) + 80168ba: f005 fbab bl 801c014 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 80168be: 68fb ldr r3, [r7, #12] + 80168c0: 7a1b ldrb r3, [r3, #8] + 80168c2: 2b00 cmp r3, #0 + 80168c4: d00b beq.n 80168de + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 80168c6: 68fb ldr r3, [r7, #12] + 80168c8: 7a1a ldrb r2, [r3, #8] + 80168ca: 4b21 ldr r3, [pc, #132] ; (8016950 ) + 80168cc: 685b ldr r3, [r3, #4] + 80168ce: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 80168d2: 3301 adds r3, #1 + 80168d4: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 80168d6: 429a cmp r2, r3 + 80168d8: d001 beq.n 80168de + return 0; + 80168da: 2300 movs r3, #0 + 80168dc: e02b b.n 8016936 + /* Only need to check PCB if incoming IP version matches PCB IP version */ + if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { +#if LWIP_IPV4 + /* Special case: IPv4 broadcast: all or broadcasts in my subnet + * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ + if (broadcast != 0) { + 80168de: 79fb ldrb r3, [r7, #7] + 80168e0: 2b00 cmp r3, #0 + 80168e2: d018 beq.n 8016916 +#if IP_SOF_BROADCAST_RECV + if (ip_get_option(pcb, SOF_BROADCAST)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 80168e4: 68fb ldr r3, [r7, #12] + 80168e6: 2b00 cmp r3, #0 + 80168e8: d013 beq.n 8016912 + 80168ea: 68fb ldr r3, [r7, #12] + 80168ec: 681b ldr r3, [r3, #0] + 80168ee: 2b00 cmp r3, #0 + 80168f0: d00f beq.n 8016912 + ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || + 80168f2: 4b17 ldr r3, [pc, #92] ; (8016950 ) + 80168f4: 695b ldr r3, [r3, #20] + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 80168f6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80168fa: d00a beq.n 8016912 + ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) { + 80168fc: 68fb ldr r3, [r7, #12] + 80168fe: 681a ldr r2, [r3, #0] + 8016900: 4b13 ldr r3, [pc, #76] ; (8016950 ) + 8016902: 695b ldr r3, [r3, #20] + 8016904: 405a eors r2, r3 + 8016906: 68bb ldr r3, [r7, #8] + 8016908: 3308 adds r3, #8 + 801690a: 681b ldr r3, [r3, #0] + 801690c: 4013 ands r3, r2 + ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || + 801690e: 2b00 cmp r3, #0 + 8016910: d110 bne.n 8016934 + return 1; + 8016912: 2301 movs r3, #1 + 8016914: e00f b.n 8016936 + } + } + } else +#endif /* LWIP_IPV4 */ + /* Handle IPv4 and IPv6: all or exact match */ + if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 8016916: 68fb ldr r3, [r7, #12] + 8016918: 2b00 cmp r3, #0 + 801691a: d009 beq.n 8016930 + 801691c: 68fb ldr r3, [r7, #12] + 801691e: 681b ldr r3, [r3, #0] + 8016920: 2b00 cmp r3, #0 + 8016922: d005 beq.n 8016930 + 8016924: 68fb ldr r3, [r7, #12] + 8016926: 681a ldr r2, [r3, #0] + 8016928: 4b09 ldr r3, [pc, #36] ; (8016950 ) + 801692a: 695b ldr r3, [r3, #20] + 801692c: 429a cmp r2, r3 + 801692e: d101 bne.n 8016934 + return 1; + 8016930: 2301 movs r3, #1 + 8016932: e000 b.n 8016936 + } + } + + return 0; + 8016934: 2300 movs r3, #0 +} + 8016936: 4618 mov r0, r3 + 8016938: 3710 adds r7, #16 + 801693a: 46bd mov sp, r7 + 801693c: bd80 pop {r7, pc} + 801693e: bf00 nop + 8016940: 08020a0c .word 0x08020a0c + 8016944: 08020a3c .word 0x08020a3c + 8016948: 08020a60 .word 0x08020a60 + 801694c: 08020a88 .word 0x08020a88 + 8016950: 20009670 .word 0x20009670 + +08016954 : + * @param inp network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + 8016954: b590 push {r4, r7, lr} + 8016956: b08d sub sp, #52 ; 0x34 + 8016958: af02 add r7, sp, #8 + 801695a: 6078 str r0, [r7, #4] + 801695c: 6039 str r1, [r7, #0] + struct udp_hdr *udphdr; + struct udp_pcb *pcb, *prev; + struct udp_pcb *uncon_pcb; + u16_t src, dest; + u8_t broadcast; + u8_t for_us = 0; + 801695e: 2300 movs r3, #0 + 8016960: 76fb strb r3, [r7, #27] + + LWIP_UNUSED_ARG(inp); + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("udp_input: invalid pbuf", p != NULL); + 8016962: 687b ldr r3, [r7, #4] + 8016964: 2b00 cmp r3, #0 + 8016966: d105 bne.n 8016974 + 8016968: 4b7c ldr r3, [pc, #496] ; (8016b5c ) + 801696a: 22cf movs r2, #207 ; 0xcf + 801696c: 497c ldr r1, [pc, #496] ; (8016b60 ) + 801696e: 487d ldr r0, [pc, #500] ; (8016b64 ) + 8016970: f005 fb50 bl 801c014 + LWIP_ASSERT("udp_input: invalid netif", inp != NULL); + 8016974: 683b ldr r3, [r7, #0] + 8016976: 2b00 cmp r3, #0 + 8016978: d105 bne.n 8016986 + 801697a: 4b78 ldr r3, [pc, #480] ; (8016b5c ) + 801697c: 22d0 movs r2, #208 ; 0xd0 + 801697e: 497a ldr r1, [pc, #488] ; (8016b68 ) + 8016980: 4878 ldr r0, [pc, #480] ; (8016b64 ) + 8016982: f005 fb47 bl 801c014 + PERF_START; + + UDP_STATS_INC(udp.recv); + + /* Check minimum length (UDP header) */ + if (p->len < UDP_HLEN) { + 8016986: 687b ldr r3, [r7, #4] + 8016988: 895b ldrh r3, [r3, #10] + 801698a: 2b07 cmp r3, #7 + 801698c: d803 bhi.n 8016996 + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + 801698e: 6878 ldr r0, [r7, #4] + 8016990: f7fa f836 bl 8010a00 + goto end; + 8016994: e0de b.n 8016b54 + } + + udphdr = (struct udp_hdr *)p->payload; + 8016996: 687b ldr r3, [r7, #4] + 8016998: 685b ldr r3, [r3, #4] + 801699a: 617b str r3, [r7, #20] + + /* is broadcast packet ? */ + broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); + 801699c: 4b73 ldr r3, [pc, #460] ; (8016b6c ) + 801699e: 695b ldr r3, [r3, #20] + 80169a0: 4a72 ldr r2, [pc, #456] ; (8016b6c ) + 80169a2: 6812 ldr r2, [r2, #0] + 80169a4: 4611 mov r1, r2 + 80169a6: 4618 mov r0, r3 + 80169a8: f003 ff1c bl 801a7e4 + 80169ac: 4603 mov r3, r0 + 80169ae: 74fb strb r3, [r7, #19] + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + /* convert src and dest ports to host byte order */ + src = lwip_ntohs(udphdr->src); + 80169b0: 697b ldr r3, [r7, #20] + 80169b2: 881b ldrh r3, [r3, #0] + 80169b4: b29b uxth r3, r3 + 80169b6: 4618 mov r0, r3 + 80169b8: f7f7 fc3a bl 800e230 + 80169bc: 4603 mov r3, r0 + 80169be: 823b strh r3, [r7, #16] + dest = lwip_ntohs(udphdr->dest); + 80169c0: 697b ldr r3, [r7, #20] + 80169c2: 885b ldrh r3, [r3, #2] + 80169c4: b29b uxth r3, r3 + 80169c6: 4618 mov r0, r3 + 80169c8: f7f7 fc32 bl 800e230 + 80169cc: 4603 mov r3, r0 + 80169ce: 81fb strh r3, [r7, #14] + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest))); + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src))); + + pcb = NULL; + 80169d0: 2300 movs r3, #0 + 80169d2: 627b str r3, [r7, #36] ; 0x24 + prev = NULL; + 80169d4: 2300 movs r3, #0 + 80169d6: 623b str r3, [r7, #32] + uncon_pcb = NULL; + 80169d8: 2300 movs r3, #0 + 80169da: 61fb str r3, [r7, #28] + /* Iterate through the UDP pcb list for a matching pcb. + * 'Perfect match' pcbs (connected to the remote port & ip address) are + * preferred. If no perfect match is found, the first unconnected pcb that + * matches the local port and ip address gets the datagram. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 80169dc: 4b64 ldr r3, [pc, #400] ; (8016b70 ) + 80169de: 681b ldr r3, [r3, #0] + 80169e0: 627b str r3, [r7, #36] ; 0x24 + 80169e2: e054 b.n 8016a8e + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port)); + ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + 80169e4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80169e6: 8a5b ldrh r3, [r3, #18] + 80169e8: 89fa ldrh r2, [r7, #14] + 80169ea: 429a cmp r2, r3 + 80169ec: d14a bne.n 8016a84 + (udp_input_local_match(pcb, inp, broadcast) != 0)) { + 80169ee: 7cfb ldrb r3, [r7, #19] + 80169f0: 461a mov r2, r3 + 80169f2: 6839 ldr r1, [r7, #0] + 80169f4: 6a78 ldr r0, [r7, #36] ; 0x24 + 80169f6: f7ff ff49 bl 801688c + 80169fa: 4603 mov r3, r0 + if ((pcb->local_port == dest) && + 80169fc: 2b00 cmp r3, #0 + 80169fe: d041 beq.n 8016a84 + if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) { + 8016a00: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a02: 7c1b ldrb r3, [r3, #16] + 8016a04: f003 0304 and.w r3, r3, #4 + 8016a08: 2b00 cmp r3, #0 + 8016a0a: d11d bne.n 8016a48 + if (uncon_pcb == NULL) { + 8016a0c: 69fb ldr r3, [r7, #28] + 8016a0e: 2b00 cmp r3, #0 + 8016a10: d102 bne.n 8016a18 + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + 8016a12: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a14: 61fb str r3, [r7, #28] + 8016a16: e017 b.n 8016a48 +#if LWIP_IPV4 + } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) { + 8016a18: 7cfb ldrb r3, [r7, #19] + 8016a1a: 2b00 cmp r3, #0 + 8016a1c: d014 beq.n 8016a48 + 8016a1e: 4b53 ldr r3, [pc, #332] ; (8016b6c ) + 8016a20: 695b ldr r3, [r3, #20] + 8016a22: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8016a26: d10f bne.n 8016a48 + /* global broadcast address (only valid for IPv4; match was checked before) */ + if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) { + 8016a28: 69fb ldr r3, [r7, #28] + 8016a2a: 681a ldr r2, [r3, #0] + 8016a2c: 683b ldr r3, [r7, #0] + 8016a2e: 3304 adds r3, #4 + 8016a30: 681b ldr r3, [r3, #0] + 8016a32: 429a cmp r2, r3 + 8016a34: d008 beq.n 8016a48 + /* uncon_pcb does not match the input netif, check this pcb */ + if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) { + 8016a36: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a38: 681a ldr r2, [r3, #0] + 8016a3a: 683b ldr r3, [r7, #0] + 8016a3c: 3304 adds r3, #4 + 8016a3e: 681b ldr r3, [r3, #0] + 8016a40: 429a cmp r2, r3 + 8016a42: d101 bne.n 8016a48 + /* better match */ + uncon_pcb = pcb; + 8016a44: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a46: 61fb str r3, [r7, #28] + } +#endif /* SO_REUSE */ + } + + /* compare PCB remote addr+port to UDP source addr+port */ + if ((pcb->remote_port == src) && + 8016a48: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a4a: 8a9b ldrh r3, [r3, #20] + 8016a4c: 8a3a ldrh r2, [r7, #16] + 8016a4e: 429a cmp r2, r3 + 8016a50: d118 bne.n 8016a84 + (ip_addr_isany_val(pcb->remote_ip) || + 8016a52: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a54: 685b ldr r3, [r3, #4] + if ((pcb->remote_port == src) && + 8016a56: 2b00 cmp r3, #0 + 8016a58: d005 beq.n 8016a66 + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { + 8016a5a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a5c: 685a ldr r2, [r3, #4] + 8016a5e: 4b43 ldr r3, [pc, #268] ; (8016b6c ) + 8016a60: 691b ldr r3, [r3, #16] + (ip_addr_isany_val(pcb->remote_ip) || + 8016a62: 429a cmp r2, r3 + 8016a64: d10e bne.n 8016a84 + /* the first fully matching PCB */ + if (prev != NULL) { + 8016a66: 6a3b ldr r3, [r7, #32] + 8016a68: 2b00 cmp r3, #0 + 8016a6a: d014 beq.n 8016a96 + /* move the pcb to the front of udp_pcbs so that is + found faster next time */ + prev->next = pcb->next; + 8016a6c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a6e: 68da ldr r2, [r3, #12] + 8016a70: 6a3b ldr r3, [r7, #32] + 8016a72: 60da str r2, [r3, #12] + pcb->next = udp_pcbs; + 8016a74: 4b3e ldr r3, [pc, #248] ; (8016b70 ) + 8016a76: 681a ldr r2, [r3, #0] + 8016a78: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a7a: 60da str r2, [r3, #12] + udp_pcbs = pcb; + 8016a7c: 4a3c ldr r2, [pc, #240] ; (8016b70 ) + 8016a7e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a80: 6013 str r3, [r2, #0] + } else { + UDP_STATS_INC(udp.cachehit); + } + break; + 8016a82: e008 b.n 8016a96 + } + } + + prev = pcb; + 8016a84: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a86: 623b str r3, [r7, #32] + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 8016a88: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a8a: 68db ldr r3, [r3, #12] + 8016a8c: 627b str r3, [r7, #36] ; 0x24 + 8016a8e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a90: 2b00 cmp r3, #0 + 8016a92: d1a7 bne.n 80169e4 + 8016a94: e000 b.n 8016a98 + break; + 8016a96: bf00 nop + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + 8016a98: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016a9a: 2b00 cmp r3, #0 + 8016a9c: d101 bne.n 8016aa2 + pcb = uncon_pcb; + 8016a9e: 69fb ldr r3, [r7, #28] + 8016aa0: 627b str r3, [r7, #36] ; 0x24 + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL) { + 8016aa2: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016aa4: 2b00 cmp r3, #0 + 8016aa6: d002 beq.n 8016aae + for_us = 1; + 8016aa8: 2301 movs r3, #1 + 8016aaa: 76fb strb r3, [r7, #27] + 8016aac: e00a b.n 8016ac4 + for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0; + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + if (!ip_current_is_v6()) { + for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr()); + 8016aae: 683b ldr r3, [r7, #0] + 8016ab0: 3304 adds r3, #4 + 8016ab2: 681a ldr r2, [r3, #0] + 8016ab4: 4b2d ldr r3, [pc, #180] ; (8016b6c ) + 8016ab6: 695b ldr r3, [r3, #20] + 8016ab8: 429a cmp r2, r3 + 8016aba: bf0c ite eq + 8016abc: 2301 moveq r3, #1 + 8016abe: 2300 movne r3, #0 + 8016ac0: b2db uxtb r3, r3 + 8016ac2: 76fb strb r3, [r7, #27] + } +#endif /* LWIP_IPV4 */ + } + + if (for_us) { + 8016ac4: 7efb ldrb r3, [r7, #27] + 8016ac6: 2b00 cmp r3, #0 + 8016ac8: d041 beq.n 8016b4e + } + } + } + } +#endif /* CHECKSUM_CHECK_UDP */ + if (pbuf_remove_header(p, UDP_HLEN)) { + 8016aca: 2108 movs r1, #8 + 8016acc: 6878 ldr r0, [r7, #4] + 8016ace: f7f9 ff11 bl 80108f4 + 8016ad2: 4603 mov r3, r0 + 8016ad4: 2b00 cmp r3, #0 + 8016ad6: d00a beq.n 8016aee + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + 8016ad8: 4b20 ldr r3, [pc, #128] ; (8016b5c ) + 8016ada: f44f 72b8 mov.w r2, #368 ; 0x170 + 8016ade: 4925 ldr r1, [pc, #148] ; (8016b74 ) + 8016ae0: 4820 ldr r0, [pc, #128] ; (8016b64 ) + 8016ae2: f005 fa97 bl 801c014 + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + 8016ae6: 6878 ldr r0, [r7, #4] + 8016ae8: f7f9 ff8a bl 8010a00 + goto end; + 8016aec: e032 b.n 8016b54 + } + + if (pcb != NULL) { + 8016aee: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016af0: 2b00 cmp r3, #0 + 8016af2: d012 beq.n 8016b1a + } + } + } +#endif /* SO_REUSE && SO_REUSE_RXTOALL */ + /* callback */ + if (pcb->recv != NULL) { + 8016af4: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016af6: 699b ldr r3, [r3, #24] + 8016af8: 2b00 cmp r3, #0 + 8016afa: d00a beq.n 8016b12 + /* now the recv function is responsible for freeing p */ + pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); + 8016afc: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016afe: 699c ldr r4, [r3, #24] + 8016b00: 6a7b ldr r3, [r7, #36] ; 0x24 + 8016b02: 69d8 ldr r0, [r3, #28] + 8016b04: 8a3b ldrh r3, [r7, #16] + 8016b06: 9300 str r3, [sp, #0] + 8016b08: 4b1b ldr r3, [pc, #108] ; (8016b78 ) + 8016b0a: 687a ldr r2, [r7, #4] + 8016b0c: 6a79 ldr r1, [r7, #36] ; 0x24 + 8016b0e: 47a0 blx r4 + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); + return; + 8016b10: e021 b.n 8016b56 + pbuf_free(p); + 8016b12: 6878 ldr r0, [r7, #4] + 8016b14: f7f9 ff74 bl 8010a00 + goto end; + 8016b18: e01c b.n 8016b54 + if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) { + 8016b1a: 7cfb ldrb r3, [r7, #19] + 8016b1c: 2b00 cmp r3, #0 + 8016b1e: d112 bne.n 8016b46 + 8016b20: 4b12 ldr r3, [pc, #72] ; (8016b6c ) + 8016b22: 695b ldr r3, [r3, #20] + 8016b24: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8016b28: 2be0 cmp r3, #224 ; 0xe0 + 8016b2a: d00c beq.n 8016b46 + pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN)); + 8016b2c: 4b0f ldr r3, [pc, #60] ; (8016b6c ) + 8016b2e: 899b ldrh r3, [r3, #12] + 8016b30: 3308 adds r3, #8 + 8016b32: b29b uxth r3, r3 + 8016b34: b21b sxth r3, r3 + 8016b36: 4619 mov r1, r3 + 8016b38: 6878 ldr r0, [r7, #4] + 8016b3a: f7f9 ff4e bl 80109da + icmp_port_unreach(ip_current_is_v6(), p); + 8016b3e: 2103 movs r1, #3 + 8016b40: 6878 ldr r0, [r7, #4] + 8016b42: f003 fb11 bl 801a168 + pbuf_free(p); + 8016b46: 6878 ldr r0, [r7, #4] + 8016b48: f7f9 ff5a bl 8010a00 + return; + 8016b4c: e003 b.n 8016b56 + pbuf_free(p); + 8016b4e: 6878 ldr r0, [r7, #4] + 8016b50: f7f9 ff56 bl 8010a00 + return; + 8016b54: bf00 nop + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + PERF_STOP("udp_input"); +#endif /* CHECKSUM_CHECK_UDP */ +} + 8016b56: 372c adds r7, #44 ; 0x2c + 8016b58: 46bd mov sp, r7 + 8016b5a: bd90 pop {r4, r7, pc} + 8016b5c: 08020a0c .word 0x08020a0c + 8016b60: 08020ab0 .word 0x08020ab0 + 8016b64: 08020a60 .word 0x08020a60 + 8016b68: 08020ac8 .word 0x08020ac8 + 8016b6c: 20009670 .word 0x20009670 + 8016b70: 2000cf8c .word 0x2000cf8c + 8016b74: 08020ae4 .word 0x08020ae4 + 8016b78: 20009680 .word 0x20009680 + +08016b7c : + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + 8016b7c: b580 push {r7, lr} + 8016b7e: b082 sub sp, #8 + 8016b80: af00 add r7, sp, #0 + 8016b82: 6078 str r0, [r7, #4] + 8016b84: 6039 str r1, [r7, #0] + LWIP_ERROR("udp_send: invalid pcb", pcb != NULL, return ERR_ARG); + 8016b86: 687b ldr r3, [r7, #4] + 8016b88: 2b00 cmp r3, #0 + 8016b8a: d109 bne.n 8016ba0 + 8016b8c: 4b11 ldr r3, [pc, #68] ; (8016bd4 ) + 8016b8e: f240 12d5 movw r2, #469 ; 0x1d5 + 8016b92: 4911 ldr r1, [pc, #68] ; (8016bd8 ) + 8016b94: 4811 ldr r0, [pc, #68] ; (8016bdc ) + 8016b96: f005 fa3d bl 801c014 + 8016b9a: f06f 030f mvn.w r3, #15 + 8016b9e: e015 b.n 8016bcc + LWIP_ERROR("udp_send: invalid pbuf", p != NULL, return ERR_ARG); + 8016ba0: 683b ldr r3, [r7, #0] + 8016ba2: 2b00 cmp r3, #0 + 8016ba4: d109 bne.n 8016bba + 8016ba6: 4b0b ldr r3, [pc, #44] ; (8016bd4 ) + 8016ba8: f44f 72eb mov.w r2, #470 ; 0x1d6 + 8016bac: 490c ldr r1, [pc, #48] ; (8016be0 ) + 8016bae: 480b ldr r0, [pc, #44] ; (8016bdc ) + 8016bb0: f005 fa30 bl 801c014 + 8016bb4: f06f 030f mvn.w r3, #15 + 8016bb8: e008 b.n 8016bcc + if (IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) { + return ERR_VAL; + } + + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); + 8016bba: 687b ldr r3, [r7, #4] + 8016bbc: 1d1a adds r2, r3, #4 + 8016bbe: 687b ldr r3, [r7, #4] + 8016bc0: 8a9b ldrh r3, [r3, #20] + 8016bc2: 6839 ldr r1, [r7, #0] + 8016bc4: 6878 ldr r0, [r7, #4] + 8016bc6: f000 f80d bl 8016be4 + 8016bca: 4603 mov r3, r0 +} + 8016bcc: 4618 mov r0, r3 + 8016bce: 3708 adds r7, #8 + 8016bd0: 46bd mov sp, r7 + 8016bd2: bd80 pop {r7, pc} + 8016bd4: 08020a0c .word 0x08020a0c + 8016bd8: 08020b00 .word 0x08020b00 + 8016bdc: 08020a60 .word 0x08020a60 + 8016be0: 08020b18 .word 0x08020b18 + +08016be4 : + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port) +{ + 8016be4: b580 push {r7, lr} + 8016be6: b088 sub sp, #32 + 8016be8: af02 add r7, sp, #8 + 8016bea: 60f8 str r0, [r7, #12] + 8016bec: 60b9 str r1, [r7, #8] + 8016bee: 607a str r2, [r7, #4] + 8016bf0: 807b strh r3, [r7, #2] + u16_t dst_port, u8_t have_chksum, u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + struct netif *netif; + + LWIP_ERROR("udp_sendto: invalid pcb", pcb != NULL, return ERR_ARG); + 8016bf2: 68fb ldr r3, [r7, #12] + 8016bf4: 2b00 cmp r3, #0 + 8016bf6: d109 bne.n 8016c0c + 8016bf8: 4b23 ldr r3, [pc, #140] ; (8016c88 ) + 8016bfa: f44f 7206 mov.w r2, #536 ; 0x218 + 8016bfe: 4923 ldr r1, [pc, #140] ; (8016c8c ) + 8016c00: 4823 ldr r0, [pc, #140] ; (8016c90 ) + 8016c02: f005 fa07 bl 801c014 + 8016c06: f06f 030f mvn.w r3, #15 + 8016c0a: e038 b.n 8016c7e + LWIP_ERROR("udp_sendto: invalid pbuf", p != NULL, return ERR_ARG); + 8016c0c: 68bb ldr r3, [r7, #8] + 8016c0e: 2b00 cmp r3, #0 + 8016c10: d109 bne.n 8016c26 + 8016c12: 4b1d ldr r3, [pc, #116] ; (8016c88 ) + 8016c14: f240 2219 movw r2, #537 ; 0x219 + 8016c18: 491e ldr r1, [pc, #120] ; (8016c94 ) + 8016c1a: 481d ldr r0, [pc, #116] ; (8016c90 ) + 8016c1c: f005 f9fa bl 801c014 + 8016c20: f06f 030f mvn.w r3, #15 + 8016c24: e02b b.n 8016c7e + LWIP_ERROR("udp_sendto: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + 8016c26: 687b ldr r3, [r7, #4] + 8016c28: 2b00 cmp r3, #0 + 8016c2a: d109 bne.n 8016c40 + 8016c2c: 4b16 ldr r3, [pc, #88] ; (8016c88 ) + 8016c2e: f240 221a movw r2, #538 ; 0x21a + 8016c32: 4919 ldr r1, [pc, #100] ; (8016c98 ) + 8016c34: 4816 ldr r0, [pc, #88] ; (8016c90 ) + 8016c36: f005 f9ed bl 801c014 + 8016c3a: f06f 030f mvn.w r3, #15 + 8016c3e: e01e b.n 8016c7e + return ERR_VAL; + } + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); + + if (pcb->netif_idx != NETIF_NO_INDEX) { + 8016c40: 68fb ldr r3, [r7, #12] + 8016c42: 7a1b ldrb r3, [r3, #8] + 8016c44: 2b00 cmp r3, #0 + 8016c46: d006 beq.n 8016c56 + netif = netif_get_by_index(pcb->netif_idx); + 8016c48: 68fb ldr r3, [r7, #12] + 8016c4a: 7a1b ldrb r3, [r3, #8] + 8016c4c: 4618 mov r0, r3 + 8016c4e: f7f9 fb49 bl 80102e4 + 8016c52: 6178 str r0, [r7, #20] + 8016c54: e003 b.n 8016c5e + + if (netif == NULL) +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + { + /* find the outgoing network interface for this packet */ + netif = ip_route(&pcb->local_ip, dst_ip); + 8016c56: 6878 ldr r0, [r7, #4] + 8016c58: f003 fb10 bl 801a27c + 8016c5c: 6178 str r0, [r7, #20] + } + } + + /* no outgoing network interface could be found? */ + if (netif == NULL) { + 8016c5e: 697b ldr r3, [r7, #20] + 8016c60: 2b00 cmp r3, #0 + 8016c62: d102 bne.n 8016c6a + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to ")); + ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, dst_ip); + LWIP_DEBUGF(UDP_DEBUG, ("\n")); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + 8016c64: f06f 0303 mvn.w r3, #3 + 8016c68: e009 b.n 8016c7e + } +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum); +#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); + 8016c6a: 887a ldrh r2, [r7, #2] + 8016c6c: 697b ldr r3, [r7, #20] + 8016c6e: 9300 str r3, [sp, #0] + 8016c70: 4613 mov r3, r2 + 8016c72: 687a ldr r2, [r7, #4] + 8016c74: 68b9 ldr r1, [r7, #8] + 8016c76: 68f8 ldr r0, [r7, #12] + 8016c78: f000 f810 bl 8016c9c + 8016c7c: 4603 mov r3, r0 +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ +} + 8016c7e: 4618 mov r0, r3 + 8016c80: 3718 adds r7, #24 + 8016c82: 46bd mov sp, r7 + 8016c84: bd80 pop {r7, pc} + 8016c86: bf00 nop + 8016c88: 08020a0c .word 0x08020a0c + 8016c8c: 08020b30 .word 0x08020b30 + 8016c90: 08020a60 .word 0x08020a60 + 8016c94: 08020b48 .word 0x08020b48 + 8016c98: 08020b64 .word 0x08020b64 + +08016c9c : + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif) +{ + 8016c9c: b580 push {r7, lr} + 8016c9e: b088 sub sp, #32 + 8016ca0: af02 add r7, sp, #8 + 8016ca2: 60f8 str r0, [r7, #12] + 8016ca4: 60b9 str r1, [r7, #8] + 8016ca6: 607a str r2, [r7, #4] + 8016ca8: 807b strh r3, [r7, #2] + u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + const ip_addr_t *src_ip; + + LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG); + 8016caa: 68fb ldr r3, [r7, #12] + 8016cac: 2b00 cmp r3, #0 + 8016cae: d109 bne.n 8016cc4 + 8016cb0: 4b2e ldr r3, [pc, #184] ; (8016d6c ) + 8016cb2: f44f 7220 mov.w r2, #640 ; 0x280 + 8016cb6: 492e ldr r1, [pc, #184] ; (8016d70 ) + 8016cb8: 482e ldr r0, [pc, #184] ; (8016d74 ) + 8016cba: f005 f9ab bl 801c014 + 8016cbe: f06f 030f mvn.w r3, #15 + 8016cc2: e04f b.n 8016d64 + LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG); + 8016cc4: 68bb ldr r3, [r7, #8] + 8016cc6: 2b00 cmp r3, #0 + 8016cc8: d109 bne.n 8016cde + 8016cca: 4b28 ldr r3, [pc, #160] ; (8016d6c ) + 8016ccc: f240 2281 movw r2, #641 ; 0x281 + 8016cd0: 4929 ldr r1, [pc, #164] ; (8016d78 ) + 8016cd2: 4828 ldr r0, [pc, #160] ; (8016d74 ) + 8016cd4: f005 f99e bl 801c014 + 8016cd8: f06f 030f mvn.w r3, #15 + 8016cdc: e042 b.n 8016d64 + LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + 8016cde: 687b ldr r3, [r7, #4] + 8016ce0: 2b00 cmp r3, #0 + 8016ce2: d109 bne.n 8016cf8 + 8016ce4: 4b21 ldr r3, [pc, #132] ; (8016d6c ) + 8016ce6: f240 2282 movw r2, #642 ; 0x282 + 8016cea: 4924 ldr r1, [pc, #144] ; (8016d7c ) + 8016cec: 4821 ldr r0, [pc, #132] ; (8016d74 ) + 8016cee: f005 f991 bl 801c014 + 8016cf2: f06f 030f mvn.w r3, #15 + 8016cf6: e035 b.n 8016d64 + LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG); + 8016cf8: 6a3b ldr r3, [r7, #32] + 8016cfa: 2b00 cmp r3, #0 + 8016cfc: d109 bne.n 8016d12 + 8016cfe: 4b1b ldr r3, [pc, #108] ; (8016d6c ) + 8016d00: f240 2283 movw r2, #643 ; 0x283 + 8016d04: 491e ldr r1, [pc, #120] ; (8016d80 ) + 8016d06: 481b ldr r0, [pc, #108] ; (8016d74 ) + 8016d08: f005 f984 bl 801c014 + 8016d0c: f06f 030f mvn.w r3, #15 + 8016d10: e028 b.n 8016d64 +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 && LWIP_IPV6 + else +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_IPV4 + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 8016d12: 68fb ldr r3, [r7, #12] + 8016d14: 2b00 cmp r3, #0 + 8016d16: d009 beq.n 8016d2c + 8016d18: 68fb ldr r3, [r7, #12] + 8016d1a: 681b ldr r3, [r3, #0] + 8016d1c: 2b00 cmp r3, #0 + 8016d1e: d005 beq.n 8016d2c + ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) { + 8016d20: 68fb ldr r3, [r7, #12] + 8016d22: 681b ldr r3, [r3, #0] + 8016d24: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 8016d28: 2be0 cmp r3, #224 ; 0xe0 + 8016d2a: d103 bne.n 8016d34 + /* if the local_ip is any or multicast + * use the outgoing network interface IP address as source address */ + src_ip = netif_ip_addr4(netif); + 8016d2c: 6a3b ldr r3, [r7, #32] + 8016d2e: 3304 adds r3, #4 + 8016d30: 617b str r3, [r7, #20] + 8016d32: e00b b.n 8016d4c + } else { + /* check if UDP PCB local IP address is correct + * this could be an old address if netif->ip_addr has changed */ + if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) { + 8016d34: 68fb ldr r3, [r7, #12] + 8016d36: 681a ldr r2, [r3, #0] + 8016d38: 6a3b ldr r3, [r7, #32] + 8016d3a: 3304 adds r3, #4 + 8016d3c: 681b ldr r3, [r3, #0] + 8016d3e: 429a cmp r2, r3 + 8016d40: d002 beq.n 8016d48 + /* local_ip doesn't match, drop the packet */ + return ERR_RTE; + 8016d42: f06f 0303 mvn.w r3, #3 + 8016d46: e00d b.n 8016d64 + } + /* use UDP PCB local IP address as source address */ + src_ip = &pcb->local_ip; + 8016d48: 68fb ldr r3, [r7, #12] + 8016d4a: 617b str r3, [r7, #20] + } +#endif /* LWIP_IPV4 */ +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip); +#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip); + 8016d4c: 887a ldrh r2, [r7, #2] + 8016d4e: 697b ldr r3, [r7, #20] + 8016d50: 9301 str r3, [sp, #4] + 8016d52: 6a3b ldr r3, [r7, #32] + 8016d54: 9300 str r3, [sp, #0] + 8016d56: 4613 mov r3, r2 + 8016d58: 687a ldr r2, [r7, #4] + 8016d5a: 68b9 ldr r1, [r7, #8] + 8016d5c: 68f8 ldr r0, [r7, #12] + 8016d5e: f000 f811 bl 8016d84 + 8016d62: 4603 mov r3, r0 +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ +} + 8016d64: 4618 mov r0, r3 + 8016d66: 3718 adds r7, #24 + 8016d68: 46bd mov sp, r7 + 8016d6a: bd80 pop {r7, pc} + 8016d6c: 08020a0c .word 0x08020a0c + 8016d70: 08020b80 .word 0x08020b80 + 8016d74: 08020a60 .word 0x08020a60 + 8016d78: 08020b9c .word 0x08020b9c + 8016d7c: 08020bb8 .word 0x08020bb8 + 8016d80: 08020bd8 .word 0x08020bd8 + +08016d84 : +/** @ingroup udp_raw + * Same as @ref udp_sendto_if, but with source address */ +err_t +udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip) +{ + 8016d84: b580 push {r7, lr} + 8016d86: b08c sub sp, #48 ; 0x30 + 8016d88: af04 add r7, sp, #16 + 8016d8a: 60f8 str r0, [r7, #12] + 8016d8c: 60b9 str r1, [r7, #8] + 8016d8e: 607a str r2, [r7, #4] + 8016d90: 807b strh r3, [r7, #2] + u8_t ip_proto; + u8_t ttl; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG); + 8016d92: 68fb ldr r3, [r7, #12] + 8016d94: 2b00 cmp r3, #0 + 8016d96: d109 bne.n 8016dac + 8016d98: 4b65 ldr r3, [pc, #404] ; (8016f30 ) + 8016d9a: f240 22d1 movw r2, #721 ; 0x2d1 + 8016d9e: 4965 ldr r1, [pc, #404] ; (8016f34 ) + 8016da0: 4865 ldr r0, [pc, #404] ; (8016f38 ) + 8016da2: f005 f937 bl 801c014 + 8016da6: f06f 030f mvn.w r3, #15 + 8016daa: e0bc b.n 8016f26 + LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG); + 8016dac: 68bb ldr r3, [r7, #8] + 8016dae: 2b00 cmp r3, #0 + 8016db0: d109 bne.n 8016dc6 + 8016db2: 4b5f ldr r3, [pc, #380] ; (8016f30 ) + 8016db4: f240 22d2 movw r2, #722 ; 0x2d2 + 8016db8: 4960 ldr r1, [pc, #384] ; (8016f3c ) + 8016dba: 485f ldr r0, [pc, #380] ; (8016f38 ) + 8016dbc: f005 f92a bl 801c014 + 8016dc0: f06f 030f mvn.w r3, #15 + 8016dc4: e0af b.n 8016f26 + LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + 8016dc6: 687b ldr r3, [r7, #4] + 8016dc8: 2b00 cmp r3, #0 + 8016dca: d109 bne.n 8016de0 + 8016dcc: 4b58 ldr r3, [pc, #352] ; (8016f30 ) + 8016dce: f240 22d3 movw r2, #723 ; 0x2d3 + 8016dd2: 495b ldr r1, [pc, #364] ; (8016f40 ) + 8016dd4: 4858 ldr r0, [pc, #352] ; (8016f38 ) + 8016dd6: f005 f91d bl 801c014 + 8016dda: f06f 030f mvn.w r3, #15 + 8016dde: e0a2 b.n 8016f26 + LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG); + 8016de0: 6afb ldr r3, [r7, #44] ; 0x2c + 8016de2: 2b00 cmp r3, #0 + 8016de4: d109 bne.n 8016dfa + 8016de6: 4b52 ldr r3, [pc, #328] ; (8016f30 ) + 8016de8: f44f 7235 mov.w r2, #724 ; 0x2d4 + 8016dec: 4955 ldr r1, [pc, #340] ; (8016f44 ) + 8016dee: 4852 ldr r0, [pc, #328] ; (8016f38 ) + 8016df0: f005 f910 bl 801c014 + 8016df4: f06f 030f mvn.w r3, #15 + 8016df8: e095 b.n 8016f26 + LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG); + 8016dfa: 6abb ldr r3, [r7, #40] ; 0x28 + 8016dfc: 2b00 cmp r3, #0 + 8016dfe: d109 bne.n 8016e14 + 8016e00: 4b4b ldr r3, [pc, #300] ; (8016f30 ) + 8016e02: f240 22d5 movw r2, #725 ; 0x2d5 + 8016e06: 4950 ldr r1, [pc, #320] ; (8016f48 ) + 8016e08: 484b ldr r0, [pc, #300] ; (8016f38 ) + 8016e0a: f005 f903 bl 801c014 + 8016e0e: f06f 030f mvn.w r3, #15 + 8016e12: e088 b.n 8016f26 + return ERR_VAL; + } +#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */ + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + 8016e14: 68fb ldr r3, [r7, #12] + 8016e16: 8a5b ldrh r3, [r3, #18] + 8016e18: 2b00 cmp r3, #0 + 8016e1a: d10f bne.n 8016e3c + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + 8016e1c: 68f9 ldr r1, [r7, #12] + 8016e1e: 68fb ldr r3, [r7, #12] + 8016e20: 8a5b ldrh r3, [r3, #18] + 8016e22: 461a mov r2, r3 + 8016e24: 68f8 ldr r0, [r7, #12] + 8016e26: f000 f893 bl 8016f50 + 8016e2a: 4603 mov r3, r0 + 8016e2c: 76fb strb r3, [r7, #27] + if (err != ERR_OK) { + 8016e2e: f997 301b ldrsb.w r3, [r7, #27] + 8016e32: 2b00 cmp r3, #0 + 8016e34: d002 beq.n 8016e3c + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); + return err; + 8016e36: f997 301b ldrsb.w r3, [r7, #27] + 8016e3a: e074 b.n 8016f26 + } + } + + /* packet too large to add a UDP header without causing an overflow? */ + if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) { + 8016e3c: 68bb ldr r3, [r7, #8] + 8016e3e: 891b ldrh r3, [r3, #8] + 8016e40: f64f 72f7 movw r2, #65527 ; 0xfff7 + 8016e44: 4293 cmp r3, r2 + 8016e46: d902 bls.n 8016e4e + return ERR_MEM; + 8016e48: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8016e4c: e06b b.n 8016f26 + } + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_add_header(p, UDP_HLEN)) { + 8016e4e: 2108 movs r1, #8 + 8016e50: 68b8 ldr r0, [r7, #8] + 8016e52: f7f9 fd3f bl 80108d4 + 8016e56: 4603 mov r3, r0 + 8016e58: 2b00 cmp r3, #0 + 8016e5a: d015 beq.n 8016e88 + /* allocate header in a separate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + 8016e5c: f44f 7220 mov.w r2, #640 ; 0x280 + 8016e60: 2108 movs r1, #8 + 8016e62: 2022 movs r0, #34 ; 0x22 + 8016e64: f7f9 fae8 bl 8010438 + 8016e68: 61f8 str r0, [r7, #28] + /* new header pbuf could not be allocated? */ + if (q == NULL) { + 8016e6a: 69fb ldr r3, [r7, #28] + 8016e6c: 2b00 cmp r3, #0 + 8016e6e: d102 bne.n 8016e76 + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); + return ERR_MEM; + 8016e70: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8016e74: e057 b.n 8016f26 + } + if (p->tot_len != 0) { + 8016e76: 68bb ldr r3, [r7, #8] + 8016e78: 891b ldrh r3, [r3, #8] + 8016e7a: 2b00 cmp r3, #0 + 8016e7c: d006 beq.n 8016e8c + /* chain header q in front of given pbuf p (only if p contains data) */ + pbuf_chain(q, p); + 8016e7e: 68b9 ldr r1, [r7, #8] + 8016e80: 69f8 ldr r0, [r7, #28] + 8016e82: f7f9 fee1 bl 8010c48 + 8016e86: e001 b.n 8016e8c + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* adding space for header within p succeeded */ + /* first pbuf q equals given pbuf */ + q = p; + 8016e88: 68bb ldr r3, [r7, #8] + 8016e8a: 61fb str r3, [r7, #28] + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", + 8016e8c: 69fb ldr r3, [r7, #28] + 8016e8e: 895b ldrh r3, [r3, #10] + 8016e90: 2b07 cmp r3, #7 + 8016e92: d806 bhi.n 8016ea2 + 8016e94: 4b26 ldr r3, [pc, #152] ; (8016f30 ) + 8016e96: f240 320d movw r2, #781 ; 0x30d + 8016e9a: 492c ldr r1, [pc, #176] ; (8016f4c ) + 8016e9c: 4826 ldr r0, [pc, #152] ; (8016f38 ) + 8016e9e: f005 f8b9 bl 801c014 + (q->len >= sizeof(struct udp_hdr))); + /* q now represents the packet to be sent */ + udphdr = (struct udp_hdr *)q->payload; + 8016ea2: 69fb ldr r3, [r7, #28] + 8016ea4: 685b ldr r3, [r3, #4] + 8016ea6: 617b str r3, [r7, #20] + udphdr->src = lwip_htons(pcb->local_port); + 8016ea8: 68fb ldr r3, [r7, #12] + 8016eaa: 8a5b ldrh r3, [r3, #18] + 8016eac: 4618 mov r0, r3 + 8016eae: f7f7 f9bf bl 800e230 + 8016eb2: 4603 mov r3, r0 + 8016eb4: 461a mov r2, r3 + 8016eb6: 697b ldr r3, [r7, #20] + 8016eb8: 801a strh r2, [r3, #0] + udphdr->dest = lwip_htons(dst_port); + 8016eba: 887b ldrh r3, [r7, #2] + 8016ebc: 4618 mov r0, r3 + 8016ebe: f7f7 f9b7 bl 800e230 + 8016ec2: 4603 mov r3, r0 + 8016ec4: 461a mov r2, r3 + 8016ec6: 697b ldr r3, [r7, #20] + 8016ec8: 805a strh r2, [r3, #2] + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + 8016eca: 697b ldr r3, [r7, #20] + 8016ecc: 2200 movs r2, #0 + 8016ece: 719a strb r2, [r3, #6] + 8016ed0: 2200 movs r2, #0 + 8016ed2: 71da strb r2, [r3, #7] + ip_proto = IP_PROTO_UDPLITE; + } else +#endif /* LWIP_UDPLITE */ + { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = lwip_htons(q->tot_len); + 8016ed4: 69fb ldr r3, [r7, #28] + 8016ed6: 891b ldrh r3, [r3, #8] + 8016ed8: 4618 mov r0, r3 + 8016eda: f7f7 f9a9 bl 800e230 + 8016ede: 4603 mov r3, r0 + 8016ee0: 461a mov r2, r3 + 8016ee2: 697b ldr r3, [r7, #20] + 8016ee4: 809a strh r2, [r3, #4] + } + udphdr->chksum = udpchksum; + } + } +#endif /* CHECKSUM_GEN_UDP */ + ip_proto = IP_PROTO_UDP; + 8016ee6: 2311 movs r3, #17 + 8016ee8: 74fb strb r3, [r7, #19] + + /* Determine TTL to use */ +#if LWIP_MULTICAST_TX_OPTIONS + ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl); +#else /* LWIP_MULTICAST_TX_OPTIONS */ + ttl = pcb->ttl; + 8016eea: 68fb ldr r3, [r7, #12] + 8016eec: 7adb ldrb r3, [r3, #11] + 8016eee: 74bb strb r3, [r7, #18] + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto)); + /* output to IP */ + NETIF_SET_HINTS(netif, &(pcb->netif_hints)); + err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif); + 8016ef0: 68fb ldr r3, [r7, #12] + 8016ef2: 7a9b ldrb r3, [r3, #10] + 8016ef4: 7cb9 ldrb r1, [r7, #18] + 8016ef6: 6aba ldr r2, [r7, #40] ; 0x28 + 8016ef8: 9202 str r2, [sp, #8] + 8016efa: 7cfa ldrb r2, [r7, #19] + 8016efc: 9201 str r2, [sp, #4] + 8016efe: 9300 str r3, [sp, #0] + 8016f00: 460b mov r3, r1 + 8016f02: 687a ldr r2, [r7, #4] + 8016f04: 6af9 ldr r1, [r7, #44] ; 0x2c + 8016f06: 69f8 ldr r0, [r7, #28] + 8016f08: f003 fbbe bl 801a688 + 8016f0c: 4603 mov r3, r0 + 8016f0e: 76fb strb r3, [r7, #27] + + /* @todo: must this be increased even if error occurred? */ + MIB2_STATS_INC(mib2.udpoutdatagrams); + + /* did we chain a separate header pbuf earlier? */ + if (q != p) { + 8016f10: 69fa ldr r2, [r7, #28] + 8016f12: 68bb ldr r3, [r7, #8] + 8016f14: 429a cmp r2, r3 + 8016f16: d004 beq.n 8016f22 + /* free the header pbuf */ + pbuf_free(q); + 8016f18: 69f8 ldr r0, [r7, #28] + 8016f1a: f7f9 fd71 bl 8010a00 + q = NULL; + 8016f1e: 2300 movs r3, #0 + 8016f20: 61fb str r3, [r7, #28] + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; + 8016f22: f997 301b ldrsb.w r3, [r7, #27] +} + 8016f26: 4618 mov r0, r3 + 8016f28: 3720 adds r7, #32 + 8016f2a: 46bd mov sp, r7 + 8016f2c: bd80 pop {r7, pc} + 8016f2e: bf00 nop + 8016f30: 08020a0c .word 0x08020a0c + 8016f34: 08020bf8 .word 0x08020bf8 + 8016f38: 08020a60 .word 0x08020a60 + 8016f3c: 08020c18 .word 0x08020c18 + 8016f40: 08020c38 .word 0x08020c38 + 8016f44: 08020c5c .word 0x08020c5c + 8016f48: 08020c80 .word 0x08020c80 + 8016f4c: 08020ca4 .word 0x08020ca4 + +08016f50 : + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) +{ + 8016f50: b580 push {r7, lr} + 8016f52: b086 sub sp, #24 + 8016f54: af00 add r7, sp, #0 + 8016f56: 60f8 str r0, [r7, #12] + 8016f58: 60b9 str r1, [r7, #8] + 8016f5a: 4613 mov r3, r2 + 8016f5c: 80fb strh r3, [r7, #6] + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + 8016f5e: 68bb ldr r3, [r7, #8] + 8016f60: 2b00 cmp r3, #0 + 8016f62: d101 bne.n 8016f68 + ipaddr = IP4_ADDR_ANY; + 8016f64: 4b39 ldr r3, [pc, #228] ; (801704c ) + 8016f66: 60bb str r3, [r7, #8] + } +#else /* LWIP_IPV4 */ + LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG); +#endif /* LWIP_IPV4 */ + + LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG); + 8016f68: 68fb ldr r3, [r7, #12] + 8016f6a: 2b00 cmp r3, #0 + 8016f6c: d109 bne.n 8016f82 + 8016f6e: 4b38 ldr r3, [pc, #224] ; (8017050 ) + 8016f70: f240 32b7 movw r2, #951 ; 0x3b7 + 8016f74: 4937 ldr r1, [pc, #220] ; (8017054 ) + 8016f76: 4838 ldr r0, [pc, #224] ; (8017058 ) + 8016f78: f005 f84c bl 801c014 + 8016f7c: f06f 030f mvn.w r3, #15 + 8016f80: e060 b.n 8017044 + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); + + rebind = 0; + 8016f82: 2300 movs r3, #0 + 8016f84: 74fb strb r3, [r7, #19] + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 8016f86: 4b35 ldr r3, [pc, #212] ; (801705c ) + 8016f88: 681b ldr r3, [r3, #0] + 8016f8a: 617b str r3, [r7, #20] + 8016f8c: e009 b.n 8016fa2 + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + 8016f8e: 68fa ldr r2, [r7, #12] + 8016f90: 697b ldr r3, [r7, #20] + 8016f92: 429a cmp r2, r3 + 8016f94: d102 bne.n 8016f9c + rebind = 1; + 8016f96: 2301 movs r3, #1 + 8016f98: 74fb strb r3, [r7, #19] + break; + 8016f9a: e005 b.n 8016fa8 + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 8016f9c: 697b ldr r3, [r7, #20] + 8016f9e: 68db ldr r3, [r3, #12] + 8016fa0: 617b str r3, [r7, #20] + 8016fa2: 697b ldr r3, [r7, #20] + 8016fa4: 2b00 cmp r3, #0 + 8016fa6: d1f2 bne.n 8016f8e + ipaddr = &zoned_ipaddr; + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + /* no port specified? */ + if (port == 0) { + 8016fa8: 88fb ldrh r3, [r7, #6] + 8016faa: 2b00 cmp r3, #0 + 8016fac: d109 bne.n 8016fc2 + port = udp_new_port(); + 8016fae: f7ff fc35 bl 801681c + 8016fb2: 4603 mov r3, r0 + 8016fb4: 80fb strh r3, [r7, #6] + if (port == 0) { + 8016fb6: 88fb ldrh r3, [r7, #6] + 8016fb8: 2b00 cmp r3, #0 + 8016fba: d12c bne.n 8017016 + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + 8016fbc: f06f 0307 mvn.w r3, #7 + 8016fc0: e040 b.n 8017044 + } + } else { + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 8016fc2: 4b26 ldr r3, [pc, #152] ; (801705c ) + 8016fc4: 681b ldr r3, [r3, #0] + 8016fc6: 617b str r3, [r7, #20] + 8016fc8: e022 b.n 8017010 + if (pcb != ipcb) { + 8016fca: 68fa ldr r2, [r7, #12] + 8016fcc: 697b ldr r3, [r7, #20] + 8016fce: 429a cmp r2, r3 + 8016fd0: d01b beq.n 801700a + if (!ip_get_option(pcb, SOF_REUSEADDR) || + !ip_get_option(ipcb, SOF_REUSEADDR)) +#endif /* SO_REUSE */ + { + /* port matches that of PCB in list and REUSEADDR not set -> reject */ + if ((ipcb->local_port == port) && + 8016fd2: 697b ldr r3, [r7, #20] + 8016fd4: 8a5b ldrh r3, [r3, #18] + 8016fd6: 88fa ldrh r2, [r7, #6] + 8016fd8: 429a cmp r2, r3 + 8016fda: d116 bne.n 801700a + /* IP address matches or any IP used? */ + (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || + 8016fdc: 697b ldr r3, [r7, #20] + 8016fde: 681a ldr r2, [r3, #0] + 8016fe0: 68bb ldr r3, [r7, #8] + 8016fe2: 681b ldr r3, [r3, #0] + if ((ipcb->local_port == port) && + 8016fe4: 429a cmp r2, r3 + 8016fe6: d00d beq.n 8017004 + (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || + 8016fe8: 68bb ldr r3, [r7, #8] + 8016fea: 2b00 cmp r3, #0 + 8016fec: d00a beq.n 8017004 + 8016fee: 68bb ldr r3, [r7, #8] + 8016ff0: 681b ldr r3, [r3, #0] + 8016ff2: 2b00 cmp r3, #0 + 8016ff4: d006 beq.n 8017004 + ip_addr_isany(&ipcb->local_ip))) { + 8016ff6: 697b ldr r3, [r7, #20] + (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || + 8016ff8: 2b00 cmp r3, #0 + 8016ffa: d003 beq.n 8017004 + ip_addr_isany(&ipcb->local_ip))) { + 8016ffc: 697b ldr r3, [r7, #20] + 8016ffe: 681b ldr r3, [r3, #0] + 8017000: 2b00 cmp r3, #0 + 8017002: d102 bne.n 801700a + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + 8017004: f06f 0307 mvn.w r3, #7 + 8017008: e01c b.n 8017044 + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 801700a: 697b ldr r3, [r7, #20] + 801700c: 68db ldr r3, [r3, #12] + 801700e: 617b str r3, [r7, #20] + 8017010: 697b ldr r3, [r7, #20] + 8017012: 2b00 cmp r3, #0 + 8017014: d1d9 bne.n 8016fca + } + } + } + } + + ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); + 8017016: 68bb ldr r3, [r7, #8] + 8017018: 2b00 cmp r3, #0 + 801701a: d002 beq.n 8017022 + 801701c: 68bb ldr r3, [r7, #8] + 801701e: 681b ldr r3, [r3, #0] + 8017020: e000 b.n 8017024 + 8017022: 2300 movs r3, #0 + 8017024: 68fa ldr r2, [r7, #12] + 8017026: 6013 str r3, [r2, #0] + + pcb->local_port = port; + 8017028: 68fb ldr r3, [r7, #12] + 801702a: 88fa ldrh r2, [r7, #6] + 801702c: 825a strh r2, [r3, #18] + mib2_udp_bind(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + 801702e: 7cfb ldrb r3, [r7, #19] + 8017030: 2b00 cmp r3, #0 + 8017032: d106 bne.n 8017042 + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + 8017034: 4b09 ldr r3, [pc, #36] ; (801705c ) + 8017036: 681a ldr r2, [r3, #0] + 8017038: 68fb ldr r3, [r7, #12] + 801703a: 60da str r2, [r3, #12] + udp_pcbs = pcb; + 801703c: 4a07 ldr r2, [pc, #28] ; (801705c ) + 801703e: 68fb ldr r3, [r7, #12] + 8017040: 6013 str r3, [r2, #0] + } + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to ")); + ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port)); + return ERR_OK; + 8017042: 2300 movs r3, #0 +} + 8017044: 4618 mov r0, r3 + 8017046: 3718 adds r7, #24 + 8017048: 46bd mov sp, r7 + 801704a: bd80 pop {r7, pc} + 801704c: 08023914 .word 0x08023914 + 8017050: 08020a0c .word 0x08020a0c + 8017054: 08020cd4 .word 0x08020cd4 + 8017058: 08020a60 .word 0x08020a60 + 801705c: 2000cf8c .word 0x2000cf8c + +08017060 : + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) +{ + 8017060: b580 push {r7, lr} + 8017062: b086 sub sp, #24 + 8017064: af00 add r7, sp, #0 + 8017066: 60f8 str r0, [r7, #12] + 8017068: 60b9 str r1, [r7, #8] + 801706a: 4613 mov r3, r2 + 801706c: 80fb strh r3, [r7, #6] + struct udp_pcb *ipcb; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG); + 801706e: 68fb ldr r3, [r7, #12] + 8017070: 2b00 cmp r3, #0 + 8017072: d109 bne.n 8017088 + 8017074: 4b2c ldr r3, [pc, #176] ; (8017128 ) + 8017076: f240 4235 movw r2, #1077 ; 0x435 + 801707a: 492c ldr r1, [pc, #176] ; (801712c ) + 801707c: 482c ldr r0, [pc, #176] ; (8017130 ) + 801707e: f004 ffc9 bl 801c014 + 8017082: f06f 030f mvn.w r3, #15 + 8017086: e04b b.n 8017120 + LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); + 8017088: 68bb ldr r3, [r7, #8] + 801708a: 2b00 cmp r3, #0 + 801708c: d109 bne.n 80170a2 + 801708e: 4b26 ldr r3, [pc, #152] ; (8017128 ) + 8017090: f240 4236 movw r2, #1078 ; 0x436 + 8017094: 4927 ldr r1, [pc, #156] ; (8017134 ) + 8017096: 4826 ldr r0, [pc, #152] ; (8017130 ) + 8017098: f004 ffbc bl 801c014 + 801709c: f06f 030f mvn.w r3, #15 + 80170a0: e03e b.n 8017120 + + if (pcb->local_port == 0) { + 80170a2: 68fb ldr r3, [r7, #12] + 80170a4: 8a5b ldrh r3, [r3, #18] + 80170a6: 2b00 cmp r3, #0 + 80170a8: d10f bne.n 80170ca + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + 80170aa: 68f9 ldr r1, [r7, #12] + 80170ac: 68fb ldr r3, [r7, #12] + 80170ae: 8a5b ldrh r3, [r3, #18] + 80170b0: 461a mov r2, r3 + 80170b2: 68f8 ldr r0, [r7, #12] + 80170b4: f7ff ff4c bl 8016f50 + 80170b8: 4603 mov r3, r0 + 80170ba: 74fb strb r3, [r7, #19] + if (err != ERR_OK) { + 80170bc: f997 3013 ldrsb.w r3, [r7, #19] + 80170c0: 2b00 cmp r3, #0 + 80170c2: d002 beq.n 80170ca + return err; + 80170c4: f997 3013 ldrsb.w r3, [r7, #19] + 80170c8: e02a b.n 8017120 + } + } + + ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); + 80170ca: 68bb ldr r3, [r7, #8] + 80170cc: 2b00 cmp r3, #0 + 80170ce: d002 beq.n 80170d6 + 80170d0: 68bb ldr r3, [r7, #8] + 80170d2: 681b ldr r3, [r3, #0] + 80170d4: e000 b.n 80170d8 + 80170d6: 2300 movs r3, #0 + 80170d8: 68fa ldr r2, [r7, #12] + 80170da: 6053 str r3, [r2, #4] + ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) { + ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip)); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + pcb->remote_port = port; + 80170dc: 68fb ldr r3, [r7, #12] + 80170de: 88fa ldrh r2, [r7, #6] + 80170e0: 829a strh r2, [r3, #20] + pcb->flags |= UDP_FLAGS_CONNECTED; + 80170e2: 68fb ldr r3, [r7, #12] + 80170e4: 7c1b ldrb r3, [r3, #16] + 80170e6: f043 0304 orr.w r3, r3, #4 + 80170ea: b2da uxtb r2, r3 + 80170ec: 68fb ldr r3, [r7, #12] + 80170ee: 741a strb r2, [r3, #16] + ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + pcb->remote_ip); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 80170f0: 4b11 ldr r3, [pc, #68] ; (8017138 ) + 80170f2: 681b ldr r3, [r3, #0] + 80170f4: 617b str r3, [r7, #20] + 80170f6: e008 b.n 801710a + if (pcb == ipcb) { + 80170f8: 68fa ldr r2, [r7, #12] + 80170fa: 697b ldr r3, [r7, #20] + 80170fc: 429a cmp r2, r3 + 80170fe: d101 bne.n 8017104 + /* already on the list, just return */ + return ERR_OK; + 8017100: 2300 movs r3, #0 + 8017102: e00d b.n 8017120 + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + 8017104: 697b ldr r3, [r7, #20] + 8017106: 68db ldr r3, [r3, #12] + 8017108: 617b str r3, [r7, #20] + 801710a: 697b ldr r3, [r7, #20] + 801710c: 2b00 cmp r3, #0 + 801710e: d1f3 bne.n 80170f8 + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + 8017110: 4b09 ldr r3, [pc, #36] ; (8017138 ) + 8017112: 681a ldr r2, [r3, #0] + 8017114: 68fb ldr r3, [r7, #12] + 8017116: 60da str r2, [r3, #12] + udp_pcbs = pcb; + 8017118: 4a07 ldr r2, [pc, #28] ; (8017138 ) + 801711a: 68fb ldr r3, [r7, #12] + 801711c: 6013 str r3, [r2, #0] + return ERR_OK; + 801711e: 2300 movs r3, #0 +} + 8017120: 4618 mov r0, r3 + 8017122: 3718 adds r7, #24 + 8017124: 46bd mov sp, r7 + 8017126: bd80 pop {r7, pc} + 8017128: 08020a0c .word 0x08020a0c + 801712c: 08020cec .word 0x08020cec + 8017130: 08020a60 .word 0x08020a60 + 8017134: 08020d08 .word 0x08020d08 + 8017138: 2000cf8c .word 0x2000cf8c + +0801713c : + * + * @param pcb the udp pcb to disconnect. + */ +void +udp_disconnect(struct udp_pcb *pcb) +{ + 801713c: b580 push {r7, lr} + 801713e: b082 sub sp, #8 + 8017140: af00 add r7, sp, #0 + 8017142: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_disconnect: invalid pcb", pcb != NULL, return); + 8017144: 687b ldr r3, [r7, #4] + 8017146: 2b00 cmp r3, #0 + 8017148: d107 bne.n 801715a + 801714a: 4b0d ldr r3, [pc, #52] ; (8017180 ) + 801714c: f240 426a movw r2, #1130 ; 0x46a + 8017150: 490c ldr r1, [pc, #48] ; (8017184 ) + 8017152: 480d ldr r0, [pc, #52] ; (8017188 ) + 8017154: f004 ff5e bl 801c014 + 8017158: e00f b.n 801717a +#if LWIP_IPV4 && LWIP_IPV6 + if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { + ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE); + } else { +#endif + ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip); + 801715a: 687b ldr r3, [r7, #4] + 801715c: 2200 movs r2, #0 + 801715e: 605a str r2, [r3, #4] +#if LWIP_IPV4 && LWIP_IPV6 + } +#endif + pcb->remote_port = 0; + 8017160: 687b ldr r3, [r7, #4] + 8017162: 2200 movs r2, #0 + 8017164: 829a strh r2, [r3, #20] + pcb->netif_idx = NETIF_NO_INDEX; + 8017166: 687b ldr r3, [r7, #4] + 8017168: 2200 movs r2, #0 + 801716a: 721a strb r2, [r3, #8] + /* mark PCB as unconnected */ + udp_clear_flags(pcb, UDP_FLAGS_CONNECTED); + 801716c: 687b ldr r3, [r7, #4] + 801716e: 7c1b ldrb r3, [r3, #16] + 8017170: f023 0304 bic.w r3, r3, #4 + 8017174: b2da uxtb r2, r3 + 8017176: 687b ldr r3, [r7, #4] + 8017178: 741a strb r2, [r3, #16] +} + 801717a: 3708 adds r7, #8 + 801717c: 46bd mov sp, r7 + 801717e: bd80 pop {r7, pc} + 8017180: 08020a0c .word 0x08020a0c + 8017184: 08020d24 .word 0x08020d24 + 8017188: 08020a60 .word 0x08020a60 + +0801718c : + * @param recv function pointer of the callback function + * @param recv_arg additional argument to pass to the callback function + */ +void +udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg) +{ + 801718c: b580 push {r7, lr} + 801718e: b084 sub sp, #16 + 8017190: af00 add r7, sp, #0 + 8017192: 60f8 str r0, [r7, #12] + 8017194: 60b9 str r1, [r7, #8] + 8017196: 607a str r2, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return); + 8017198: 68fb ldr r3, [r7, #12] + 801719a: 2b00 cmp r3, #0 + 801719c: d107 bne.n 80171ae + 801719e: 4b08 ldr r3, [pc, #32] ; (80171c0 ) + 80171a0: f240 428a movw r2, #1162 ; 0x48a + 80171a4: 4907 ldr r1, [pc, #28] ; (80171c4 ) + 80171a6: 4808 ldr r0, [pc, #32] ; (80171c8 ) + 80171a8: f004 ff34 bl 801c014 + 80171ac: e005 b.n 80171ba + + /* remember recv() callback and user data */ + pcb->recv = recv; + 80171ae: 68fb ldr r3, [r7, #12] + 80171b0: 68ba ldr r2, [r7, #8] + 80171b2: 619a str r2, [r3, #24] + pcb->recv_arg = recv_arg; + 80171b4: 68fb ldr r3, [r7, #12] + 80171b6: 687a ldr r2, [r7, #4] + 80171b8: 61da str r2, [r3, #28] +} + 80171ba: 3710 adds r7, #16 + 80171bc: 46bd mov sp, r7 + 80171be: bd80 pop {r7, pc} + 80171c0: 08020a0c .word 0x08020a0c + 80171c4: 08020d40 .word 0x08020d40 + 80171c8: 08020a60 .word 0x08020a60 + +080171cc : + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + 80171cc: b580 push {r7, lr} + 80171ce: b084 sub sp, #16 + 80171d0: af00 add r7, sp, #0 + 80171d2: 6078 str r0, [r7, #4] + struct udp_pcb *pcb2; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return); + 80171d4: 687b ldr r3, [r7, #4] + 80171d6: 2b00 cmp r3, #0 + 80171d8: d107 bne.n 80171ea + 80171da: 4b19 ldr r3, [pc, #100] ; (8017240 ) + 80171dc: f240 42a1 movw r2, #1185 ; 0x4a1 + 80171e0: 4918 ldr r1, [pc, #96] ; (8017244 ) + 80171e2: 4819 ldr r0, [pc, #100] ; (8017248 ) + 80171e4: f004 ff16 bl 801c014 + 80171e8: e026 b.n 8017238 + + mib2_udp_unbind(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + 80171ea: 4b18 ldr r3, [pc, #96] ; (801724c ) + 80171ec: 681b ldr r3, [r3, #0] + 80171ee: 687a ldr r2, [r7, #4] + 80171f0: 429a cmp r2, r3 + 80171f2: d105 bne.n 8017200 + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + 80171f4: 4b15 ldr r3, [pc, #84] ; (801724c ) + 80171f6: 681b ldr r3, [r3, #0] + 80171f8: 68db ldr r3, [r3, #12] + 80171fa: 4a14 ldr r2, [pc, #80] ; (801724c ) + 80171fc: 6013 str r3, [r2, #0] + 80171fe: e017 b.n 8017230 + /* pcb not 1st in list */ + } else { + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + 8017200: 4b12 ldr r3, [pc, #72] ; (801724c ) + 8017202: 681b ldr r3, [r3, #0] + 8017204: 60fb str r3, [r7, #12] + 8017206: e010 b.n 801722a + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + 8017208: 68fb ldr r3, [r7, #12] + 801720a: 68db ldr r3, [r3, #12] + 801720c: 2b00 cmp r3, #0 + 801720e: d009 beq.n 8017224 + 8017210: 68fb ldr r3, [r7, #12] + 8017212: 68db ldr r3, [r3, #12] + 8017214: 687a ldr r2, [r7, #4] + 8017216: 429a cmp r2, r3 + 8017218: d104 bne.n 8017224 + /* remove pcb from list */ + pcb2->next = pcb->next; + 801721a: 687b ldr r3, [r7, #4] + 801721c: 68da ldr r2, [r3, #12] + 801721e: 68fb ldr r3, [r7, #12] + 8017220: 60da str r2, [r3, #12] + break; + 8017222: e005 b.n 8017230 + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + 8017224: 68fb ldr r3, [r7, #12] + 8017226: 68db ldr r3, [r3, #12] + 8017228: 60fb str r3, [r7, #12] + 801722a: 68fb ldr r3, [r7, #12] + 801722c: 2b00 cmp r3, #0 + 801722e: d1eb bne.n 8017208 + } + } + } + memp_free(MEMP_UDP_PCB, pcb); + 8017230: 6879 ldr r1, [r7, #4] + 8017232: 2000 movs r0, #0 + 8017234: f7f8 fd34 bl 800fca0 +} + 8017238: 3710 adds r7, #16 + 801723a: 46bd mov sp, r7 + 801723c: bd80 pop {r7, pc} + 801723e: bf00 nop + 8017240: 08020a0c .word 0x08020a0c + 8017244: 08020d58 .word 0x08020d58 + 8017248: 08020a60 .word 0x08020a60 + 801724c: 2000cf8c .word 0x2000cf8c + +08017250 : + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + 8017250: b580 push {r7, lr} + 8017252: b082 sub sp, #8 + 8017254: af00 add r7, sp, #0 + struct udp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB); + 8017256: 2000 movs r0, #0 + 8017258: f7f8 fcac bl 800fbb4 + 801725c: 6078 str r0, [r7, #4] + /* could allocate UDP PCB? */ + if (pcb != NULL) { + 801725e: 687b ldr r3, [r7, #4] + 8017260: 2b00 cmp r3, #0 + 8017262: d007 beq.n 8017274 + /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 + * which means checksum is generated over the whole datagram per default + * (recommended as default by RFC 3828). */ + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + 8017264: 2220 movs r2, #32 + 8017266: 2100 movs r1, #0 + 8017268: 6878 ldr r0, [r7, #4] + 801726a: f004 fe36 bl 801beda + pcb->ttl = UDP_TTL; + 801726e: 687b ldr r3, [r7, #4] + 8017270: 22ff movs r2, #255 ; 0xff + 8017272: 72da strb r2, [r3, #11] +#if LWIP_MULTICAST_TX_OPTIONS + udp_set_multicast_ttl(pcb, UDP_TTL); +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + } + return pcb; + 8017274: 687b ldr r3, [r7, #4] +} + 8017276: 4618 mov r0, r3 + 8017278: 3708 adds r7, #8 + 801727a: 46bd mov sp, r7 + 801727c: bd80 pop {r7, pc} + +0801727e : + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new_ip_type(u8_t type) +{ + 801727e: b580 push {r7, lr} + 8017280: b084 sub sp, #16 + 8017282: af00 add r7, sp, #0 + 8017284: 4603 mov r3, r0 + 8017286: 71fb strb r3, [r7, #7] + struct udp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = udp_new(); + 8017288: f7ff ffe2 bl 8017250 + 801728c: 60f8 str r0, [r7, #12] + IP_SET_TYPE_VAL(pcb->remote_ip, type); + } +#else + LWIP_UNUSED_ARG(type); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + return pcb; + 801728e: 68fb ldr r3, [r7, #12] +} + 8017290: 4618 mov r0, r3 + 8017292: 3710 adds r7, #16 + 8017294: 46bd mov sp, r7 + 8017296: bd80 pop {r7, pc} + +08017298 : + * + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change + */ +void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 8017298: b480 push {r7} + 801729a: b085 sub sp, #20 + 801729c: af00 add r7, sp, #0 + 801729e: 6078 str r0, [r7, #4] + 80172a0: 6039 str r1, [r7, #0] + struct udp_pcb *upcb; + + if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { + 80172a2: 687b ldr r3, [r7, #4] + 80172a4: 2b00 cmp r3, #0 + 80172a6: d01e beq.n 80172e6 + 80172a8: 687b ldr r3, [r7, #4] + 80172aa: 681b ldr r3, [r3, #0] + 80172ac: 2b00 cmp r3, #0 + 80172ae: d01a beq.n 80172e6 + 80172b0: 683b ldr r3, [r7, #0] + 80172b2: 2b00 cmp r3, #0 + 80172b4: d017 beq.n 80172e6 + 80172b6: 683b ldr r3, [r7, #0] + 80172b8: 681b ldr r3, [r3, #0] + 80172ba: 2b00 cmp r3, #0 + 80172bc: d013 beq.n 80172e6 + for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { + 80172be: 4b0d ldr r3, [pc, #52] ; (80172f4 ) + 80172c0: 681b ldr r3, [r3, #0] + 80172c2: 60fb str r3, [r7, #12] + 80172c4: e00c b.n 80172e0 + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&upcb->local_ip, old_addr)) { + 80172c6: 68fb ldr r3, [r7, #12] + 80172c8: 681a ldr r2, [r3, #0] + 80172ca: 687b ldr r3, [r7, #4] + 80172cc: 681b ldr r3, [r3, #0] + 80172ce: 429a cmp r2, r3 + 80172d0: d103 bne.n 80172da + /* The PCB is bound to the old ipaddr and + * is set to bound to the new one instead */ + ip_addr_copy(upcb->local_ip, *new_addr); + 80172d2: 683b ldr r3, [r7, #0] + 80172d4: 681a ldr r2, [r3, #0] + 80172d6: 68fb ldr r3, [r7, #12] + 80172d8: 601a str r2, [r3, #0] + for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { + 80172da: 68fb ldr r3, [r7, #12] + 80172dc: 68db ldr r3, [r3, #12] + 80172de: 60fb str r3, [r7, #12] + 80172e0: 68fb ldr r3, [r7, #12] + 80172e2: 2b00 cmp r3, #0 + 80172e4: d1ef bne.n 80172c6 + } + } + } +} + 80172e6: bf00 nop + 80172e8: 3714 adds r7, #20 + 80172ea: 46bd mov sp, r7 + 80172ec: f85d 7b04 ldr.w r7, [sp], #4 + 80172f0: 4770 bx lr + 80172f2: bf00 nop + 80172f4: 2000cf8c .word 0x2000cf8c + +080172f8 : +static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out); + +/** Ensure DHCP PCB is allocated and bound */ +static err_t +dhcp_inc_pcb_refcount(void) +{ + 80172f8: b580 push {r7, lr} + 80172fa: af00 add r7, sp, #0 + if (dhcp_pcb_refcount == 0) { + 80172fc: 4b20 ldr r3, [pc, #128] ; (8017380 ) + 80172fe: 781b ldrb r3, [r3, #0] + 8017300: 2b00 cmp r3, #0 + 8017302: d133 bne.n 801736c + LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL); + 8017304: 4b1f ldr r3, [pc, #124] ; (8017384 ) + 8017306: 681b ldr r3, [r3, #0] + 8017308: 2b00 cmp r3, #0 + 801730a: d005 beq.n 8017318 + 801730c: 4b1e ldr r3, [pc, #120] ; (8017388 ) + 801730e: 22e5 movs r2, #229 ; 0xe5 + 8017310: 491e ldr r1, [pc, #120] ; (801738c ) + 8017312: 481f ldr r0, [pc, #124] ; (8017390 ) + 8017314: f004 fe7e bl 801c014 + + /* allocate UDP PCB */ + dhcp_pcb = udp_new(); + 8017318: f7ff ff9a bl 8017250 + 801731c: 4603 mov r3, r0 + 801731e: 4a19 ldr r2, [pc, #100] ; (8017384 ) + 8017320: 6013 str r3, [r2, #0] + + if (dhcp_pcb == NULL) { + 8017322: 4b18 ldr r3, [pc, #96] ; (8017384 ) + 8017324: 681b ldr r3, [r3, #0] + 8017326: 2b00 cmp r3, #0 + 8017328: d102 bne.n 8017330 + return ERR_MEM; + 801732a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801732e: e024 b.n 801737a + } + + ip_set_option(dhcp_pcb, SOF_BROADCAST); + 8017330: 4b14 ldr r3, [pc, #80] ; (8017384 ) + 8017332: 681b ldr r3, [r3, #0] + 8017334: 7a5a ldrb r2, [r3, #9] + 8017336: 4b13 ldr r3, [pc, #76] ; (8017384 ) + 8017338: 681b ldr r3, [r3, #0] + 801733a: f042 0220 orr.w r2, r2, #32 + 801733e: b2d2 uxtb r2, r2 + 8017340: 725a strb r2, [r3, #9] + + /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */ + udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT); + 8017342: 4b10 ldr r3, [pc, #64] ; (8017384 ) + 8017344: 681b ldr r3, [r3, #0] + 8017346: 2244 movs r2, #68 ; 0x44 + 8017348: 4912 ldr r1, [pc, #72] ; (8017394 ) + 801734a: 4618 mov r0, r3 + 801734c: f7ff fe00 bl 8016f50 + udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER); + 8017350: 4b0c ldr r3, [pc, #48] ; (8017384 ) + 8017352: 681b ldr r3, [r3, #0] + 8017354: 2243 movs r2, #67 ; 0x43 + 8017356: 490f ldr r1, [pc, #60] ; (8017394 ) + 8017358: 4618 mov r0, r3 + 801735a: f7ff fe81 bl 8017060 + udp_recv(dhcp_pcb, dhcp_recv, NULL); + 801735e: 4b09 ldr r3, [pc, #36] ; (8017384 ) + 8017360: 681b ldr r3, [r3, #0] + 8017362: 2200 movs r2, #0 + 8017364: 490c ldr r1, [pc, #48] ; (8017398 ) + 8017366: 4618 mov r0, r3 + 8017368: f7ff ff10 bl 801718c + } + + dhcp_pcb_refcount++; + 801736c: 4b04 ldr r3, [pc, #16] ; (8017380 ) + 801736e: 781b ldrb r3, [r3, #0] + 8017370: 3301 adds r3, #1 + 8017372: b2da uxtb r2, r3 + 8017374: 4b02 ldr r3, [pc, #8] ; (8017380 ) + 8017376: 701a strb r2, [r3, #0] + + return ERR_OK; + 8017378: 2300 movs r3, #0 +} + 801737a: 4618 mov r0, r3 + 801737c: bd80 pop {r7, pc} + 801737e: bf00 nop + 8017380: 2000cfc8 .word 0x2000cfc8 + 8017384: 2000cfc4 .word 0x2000cfc4 + 8017388: 08020d70 .word 0x08020d70 + 801738c: 08020da8 .word 0x08020da8 + 8017390: 08020dd0 .word 0x08020dd0 + 8017394: 08023914 .word 0x08023914 + 8017398: 08018cd1 .word 0x08018cd1 + +0801739c : + +/** Free DHCP PCB if the last netif stops using it */ +static void +dhcp_dec_pcb_refcount(void) +{ + 801739c: b580 push {r7, lr} + 801739e: af00 add r7, sp, #0 + LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0)); + 80173a0: 4b0e ldr r3, [pc, #56] ; (80173dc ) + 80173a2: 781b ldrb r3, [r3, #0] + 80173a4: 2b00 cmp r3, #0 + 80173a6: d105 bne.n 80173b4 + 80173a8: 4b0d ldr r3, [pc, #52] ; (80173e0 ) + 80173aa: 22ff movs r2, #255 ; 0xff + 80173ac: 490d ldr r1, [pc, #52] ; (80173e4 ) + 80173ae: 480e ldr r0, [pc, #56] ; (80173e8 ) + 80173b0: f004 fe30 bl 801c014 + dhcp_pcb_refcount--; + 80173b4: 4b09 ldr r3, [pc, #36] ; (80173dc ) + 80173b6: 781b ldrb r3, [r3, #0] + 80173b8: 3b01 subs r3, #1 + 80173ba: b2da uxtb r2, r3 + 80173bc: 4b07 ldr r3, [pc, #28] ; (80173dc ) + 80173be: 701a strb r2, [r3, #0] + + if (dhcp_pcb_refcount == 0) { + 80173c0: 4b06 ldr r3, [pc, #24] ; (80173dc ) + 80173c2: 781b ldrb r3, [r3, #0] + 80173c4: 2b00 cmp r3, #0 + 80173c6: d107 bne.n 80173d8 + udp_remove(dhcp_pcb); + 80173c8: 4b08 ldr r3, [pc, #32] ; (80173ec ) + 80173ca: 681b ldr r3, [r3, #0] + 80173cc: 4618 mov r0, r3 + 80173ce: f7ff fefd bl 80171cc + dhcp_pcb = NULL; + 80173d2: 4b06 ldr r3, [pc, #24] ; (80173ec ) + 80173d4: 2200 movs r2, #0 + 80173d6: 601a str r2, [r3, #0] + } +} + 80173d8: bf00 nop + 80173da: bd80 pop {r7, pc} + 80173dc: 2000cfc8 .word 0x2000cfc8 + 80173e0: 08020d70 .word 0x08020d70 + 80173e4: 08020df8 .word 0x08020df8 + 80173e8: 08020dd0 .word 0x08020dd0 + 80173ec: 2000cfc4 .word 0x2000cfc4 + +080173f0 : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_nak(struct netif *netif) +{ + 80173f0: b580 push {r7, lr} + 80173f2: b084 sub sp, #16 + 80173f4: af00 add r7, sp, #0 + 80173f6: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 80173f8: 687b ldr r3, [r7, #4] + 80173fa: 6a5b ldr r3, [r3, #36] ; 0x24 + 80173fc: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", + (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* Change to a defined state - set this before assigning the address + to ensure the callback can use dhcp_supplied_address() */ + dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); + 80173fe: 210c movs r1, #12 + 8017400: 68f8 ldr r0, [r7, #12] + 8017402: f001 f877 bl 80184f4 + /* remove IP address from interface (must no longer be used, as per RFC2131) */ + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + 8017406: 4b06 ldr r3, [pc, #24] ; (8017420 ) + 8017408: 4a05 ldr r2, [pc, #20] ; (8017420 ) + 801740a: 4905 ldr r1, [pc, #20] ; (8017420 ) + 801740c: 6878 ldr r0, [r7, #4] + 801740e: f7f8 fde9 bl 800ffe4 + /* We can immediately restart discovery */ + dhcp_discover(netif); + 8017412: 6878 ldr r0, [r7, #4] + 8017414: f000 fc6a bl 8017cec +} + 8017418: bf00 nop + 801741a: 3710 adds r7, #16 + 801741c: 46bd mov sp, r7 + 801741e: bd80 pop {r7, pc} + 8017420: 08023914 .word 0x08023914 + +08017424 : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_check(struct netif *netif) +{ + 8017424: b580 push {r7, lr} + 8017426: b084 sub sp, #16 + 8017428: af00 add r7, sp, #0 + 801742a: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 801742c: 687b ldr r3, [r7, #4] + 801742e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017430: 60fb str r3, [r7, #12] + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], + (s16_t)netif->name[1])); + dhcp_set_state(dhcp, DHCP_STATE_CHECKING); + 8017432: 2108 movs r1, #8 + 8017434: 68f8 ldr r0, [r7, #12] + 8017436: f001 f85d bl 80184f4 + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); + 801743a: 68fb ldr r3, [r7, #12] + 801743c: 331c adds r3, #28 + 801743e: 2200 movs r2, #0 + 8017440: 4619 mov r1, r3 + 8017442: 6878 ldr r0, [r7, #4] + 8017444: f002 fb8e bl 8019b64 + 8017448: 4603 mov r3, r0 + 801744a: 72fb strb r3, [r7, #11] + if (result != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n")); + } + if (dhcp->tries < 255) { + 801744c: 68fb ldr r3, [r7, #12] + 801744e: 799b ldrb r3, [r3, #6] + 8017450: 2bff cmp r3, #255 ; 0xff + 8017452: d005 beq.n 8017460 + dhcp->tries++; + 8017454: 68fb ldr r3, [r7, #12] + 8017456: 799b ldrb r3, [r3, #6] + 8017458: 3301 adds r3, #1 + 801745a: b2da uxtb r2, r3 + 801745c: 68fb ldr r3, [r7, #12] + 801745e: 719a strb r2, [r3, #6] + } + msecs = 500; + 8017460: f44f 73fa mov.w r3, #500 ; 0x1f4 + 8017464: 813b strh r3, [r7, #8] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 8017466: 893b ldrh r3, [r7, #8] + 8017468: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 801746c: 4a06 ldr r2, [pc, #24] ; (8017488 ) + 801746e: fb82 1203 smull r1, r2, r2, r3 + 8017472: 1152 asrs r2, r2, #5 + 8017474: 17db asrs r3, r3, #31 + 8017476: 1ad3 subs r3, r2, r3 + 8017478: b29a uxth r2, r3 + 801747a: 68fb ldr r3, [r7, #12] + 801747c: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); +} + 801747e: bf00 nop + 8017480: 3710 adds r7, #16 + 8017482: 46bd mov sp, r7 + 8017484: bd80 pop {r7, pc} + 8017486: bf00 nop + 8017488: 10624dd3 .word 0x10624dd3 + +0801748c : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in) +{ + 801748c: b580 push {r7, lr} + 801748e: b084 sub sp, #16 + 8017490: af00 add r7, sp, #0 + 8017492: 6078 str r0, [r7, #4] + 8017494: 6039 str r1, [r7, #0] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017496: 687b ldr r3, [r7, #4] + 8017498: 6a5b ldr r3, [r3, #36] ; 0x24 + 801749a: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", + (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* obtain the server address */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) { + 801749c: 4b0c ldr r3, [pc, #48] ; (80174d0 ) + 801749e: 789b ldrb r3, [r3, #2] + 80174a0: 2b00 cmp r3, #0 + 80174a2: d011 beq.n 80174c8 + dhcp->request_timeout = 0; /* stop timer */ + 80174a4: 68fb ldr r3, [r7, #12] + 80174a6: 2200 movs r2, #0 + 80174a8: 811a strh r2, [r3, #8] + + ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID))); + 80174aa: 4b0a ldr r3, [pc, #40] ; (80174d4 ) + 80174ac: 689b ldr r3, [r3, #8] + 80174ae: 4618 mov r0, r3 + 80174b0: f7f6 fed3 bl 800e25a + 80174b4: 4602 mov r2, r0 + 80174b6: 68fb ldr r3, [r7, #12] + 80174b8: 619a str r2, [r3, #24] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", + ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); + /* remember offered address */ + ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr); + 80174ba: 683b ldr r3, [r7, #0] + 80174bc: 691a ldr r2, [r3, #16] + 80174be: 68fb ldr r3, [r7, #12] + 80174c0: 61da str r2, [r3, #28] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_select(netif); + 80174c2: 6878 ldr r0, [r7, #4] + 80174c4: f000 f808 bl 80174d8 + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif)); + } +} + 80174c8: bf00 nop + 80174ca: 3710 adds r7, #16 + 80174cc: 46bd mov sp, r7 + 80174ce: bd80 pop {r7, pc} + 80174d0: 2000cfb8 .word 0x2000cfb8 + 80174d4: 2000cf90 .word 0x2000cf90 + +080174d8 : + * @param netif the netif under DHCP control + * @return lwIP specific error (see error.h) + */ +static err_t +dhcp_select(struct netif *netif) +{ + 80174d8: b5b0 push {r4, r5, r7, lr} + 80174da: b08a sub sp, #40 ; 0x28 + 80174dc: af02 add r7, sp, #8 + 80174de: 6078 str r0, [r7, #4] + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;); + 80174e0: 687b ldr r3, [r7, #4] + 80174e2: 2b00 cmp r3, #0 + 80174e4: d109 bne.n 80174fa + 80174e6: 4b71 ldr r3, [pc, #452] ; (80176ac ) + 80174e8: f240 1277 movw r2, #375 ; 0x177 + 80174ec: 4970 ldr r1, [pc, #448] ; (80176b0 ) + 80174ee: 4871 ldr r0, [pc, #452] ; (80176b4 ) + 80174f0: f004 fd90 bl 801c014 + 80174f4: f06f 030f mvn.w r3, #15 + 80174f8: e0d3 b.n 80176a2 + dhcp = netif_dhcp_data(netif); + 80174fa: 687b ldr r3, [r7, #4] + 80174fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80174fe: 61bb str r3, [r7, #24] + LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;); + 8017500: 69bb ldr r3, [r7, #24] + 8017502: 2b00 cmp r3, #0 + 8017504: d109 bne.n 801751a + 8017506: 4b69 ldr r3, [pc, #420] ; (80176ac ) + 8017508: f240 1279 movw r2, #377 ; 0x179 + 801750c: 496a ldr r1, [pc, #424] ; (80176b8 ) + 801750e: 4869 ldr r0, [pc, #420] ; (80176b4 ) + 8017510: f004 fd80 bl 801c014 + 8017514: f06f 0305 mvn.w r3, #5 + 8017518: e0c3 b.n 80176a2 + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + dhcp_set_state(dhcp, DHCP_STATE_REQUESTING); + 801751a: 2101 movs r1, #1 + 801751c: 69b8 ldr r0, [r7, #24] + 801751e: f000 ffe9 bl 80184f4 + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + 8017522: f107 030c add.w r3, r7, #12 + 8017526: 2203 movs r2, #3 + 8017528: 69b9 ldr r1, [r7, #24] + 801752a: 6878 ldr r0, [r7, #4] + 801752c: f001 fc9e bl 8018e6c + 8017530: 6178 str r0, [r7, #20] + if (p_out != NULL) { + 8017532: 697b ldr r3, [r7, #20] + 8017534: 2b00 cmp r3, #0 + 8017536: f000 8085 beq.w 8017644 + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 801753a: 697b ldr r3, [r7, #20] + 801753c: 685b ldr r3, [r3, #4] + 801753e: 613b str r3, [r7, #16] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + 8017540: 89b8 ldrh r0, [r7, #12] + 8017542: 693b ldr r3, [r7, #16] + 8017544: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017548: 2302 movs r3, #2 + 801754a: 2239 movs r2, #57 ; 0x39 + 801754c: f000 ffec bl 8018528 + 8017550: 4603 mov r3, r0 + 8017552: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + 8017554: 89b8 ldrh r0, [r7, #12] + 8017556: 693b ldr r3, [r7, #16] + 8017558: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 801755c: 687b ldr r3, [r7, #4] + 801755e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8017560: 461a mov r2, r3 + 8017562: f001 f83b bl 80185dc + 8017566: 4603 mov r3, r0 + 8017568: 81bb strh r3, [r7, #12] + + /* MUST request the offered IP address */ + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + 801756a: 89b8 ldrh r0, [r7, #12] + 801756c: 693b ldr r3, [r7, #16] + 801756e: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017572: 2304 movs r3, #4 + 8017574: 2232 movs r2, #50 ; 0x32 + 8017576: f000 ffd7 bl 8018528 + 801757a: 4603 mov r3, r0 + 801757c: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + 801757e: 89bc ldrh r4, [r7, #12] + 8017580: 693b ldr r3, [r7, #16] + 8017582: f103 05f0 add.w r5, r3, #240 ; 0xf0 + 8017586: 69bb ldr r3, [r7, #24] + 8017588: 69db ldr r3, [r3, #28] + 801758a: 4618 mov r0, r3 + 801758c: f7f6 fe65 bl 800e25a + 8017590: 4603 mov r3, r0 + 8017592: 461a mov r2, r3 + 8017594: 4629 mov r1, r5 + 8017596: 4620 mov r0, r4 + 8017598: f001 f852 bl 8018640 + 801759c: 4603 mov r3, r0 + 801759e: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4); + 80175a0: 89b8 ldrh r0, [r7, #12] + 80175a2: 693b ldr r3, [r7, #16] + 80175a4: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 80175a8: 2304 movs r3, #4 + 80175aa: 2236 movs r2, #54 ; 0x36 + 80175ac: f000 ffbc bl 8018528 + 80175b0: 4603 mov r3, r0 + 80175b2: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); + 80175b4: 89bc ldrh r4, [r7, #12] + 80175b6: 693b ldr r3, [r7, #16] + 80175b8: f103 05f0 add.w r5, r3, #240 ; 0xf0 + 80175bc: 69bb ldr r3, [r7, #24] + 80175be: 699b ldr r3, [r3, #24] + 80175c0: 4618 mov r0, r3 + 80175c2: f7f6 fe4a bl 800e25a + 80175c6: 4603 mov r3, r0 + 80175c8: 461a mov r2, r3 + 80175ca: 4629 mov r1, r5 + 80175cc: 4620 mov r0, r4 + 80175ce: f001 f837 bl 8018640 + 80175d2: 4603 mov r3, r0 + 80175d4: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + 80175d6: 89b8 ldrh r0, [r7, #12] + 80175d8: 693b ldr r3, [r7, #16] + 80175da: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 80175de: 2304 movs r3, #4 + 80175e0: 2237 movs r2, #55 ; 0x37 + 80175e2: f000 ffa1 bl 8018528 + 80175e6: 4603 mov r3, r0 + 80175e8: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 80175ea: 2300 movs r3, #0 + 80175ec: 77bb strb r3, [r7, #30] + 80175ee: e00e b.n 801760e + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + 80175f0: 89b8 ldrh r0, [r7, #12] + 80175f2: 693b ldr r3, [r7, #16] + 80175f4: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 80175f8: 7fbb ldrb r3, [r7, #30] + 80175fa: 4a30 ldr r2, [pc, #192] ; (80176bc ) + 80175fc: 5cd3 ldrb r3, [r2, r3] + 80175fe: 461a mov r2, r3 + 8017600: f000 ffc6 bl 8018590 + 8017604: 4603 mov r3, r0 + 8017606: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8017608: 7fbb ldrb r3, [r7, #30] + 801760a: 3301 adds r3, #1 + 801760c: 77bb strb r3, [r7, #30] + 801760e: 7fbb ldrb r3, [r7, #30] + 8017610: 2b03 cmp r3, #3 + 8017612: d9ed bls.n 80175f0 +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 8017614: 89b8 ldrh r0, [r7, #12] + 8017616: 693b ldr r3, [r7, #16] + 8017618: 33f0 adds r3, #240 ; 0xf0 + 801761a: 697a ldr r2, [r7, #20] + 801761c: 4619 mov r1, r3 + 801761e: f001 fcfb bl 8019018 + + /* send broadcast to any DHCP server */ + result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + 8017622: 4b27 ldr r3, [pc, #156] ; (80176c0 ) + 8017624: 6818 ldr r0, [r3, #0] + 8017626: 4b27 ldr r3, [pc, #156] ; (80176c4 ) + 8017628: 9301 str r3, [sp, #4] + 801762a: 687b ldr r3, [r7, #4] + 801762c: 9300 str r3, [sp, #0] + 801762e: 2343 movs r3, #67 ; 0x43 + 8017630: 4a25 ldr r2, [pc, #148] ; (80176c8 ) + 8017632: 6979 ldr r1, [r7, #20] + 8017634: f7ff fba6 bl 8016d84 + 8017638: 4603 mov r3, r0 + 801763a: 77fb strb r3, [r7, #31] + pbuf_free(p_out); + 801763c: 6978 ldr r0, [r7, #20] + 801763e: f7f9 f9df bl 8010a00 + 8017642: e001 b.n 8017648 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n")); + result = ERR_MEM; + 8017644: 23ff movs r3, #255 ; 0xff + 8017646: 77fb strb r3, [r7, #31] + } + if (dhcp->tries < 255) { + 8017648: 69bb ldr r3, [r7, #24] + 801764a: 799b ldrb r3, [r3, #6] + 801764c: 2bff cmp r3, #255 ; 0xff + 801764e: d005 beq.n 801765c + dhcp->tries++; + 8017650: 69bb ldr r3, [r7, #24] + 8017652: 799b ldrb r3, [r3, #6] + 8017654: 3301 adds r3, #1 + 8017656: b2da uxtb r2, r3 + 8017658: 69bb ldr r3, [r7, #24] + 801765a: 719a strb r2, [r3, #6] + } + msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000); + 801765c: 69bb ldr r3, [r7, #24] + 801765e: 799b ldrb r3, [r3, #6] + 8017660: 2b05 cmp r3, #5 + 8017662: d80d bhi.n 8017680 + 8017664: 69bb ldr r3, [r7, #24] + 8017666: 799b ldrb r3, [r3, #6] + 8017668: 461a mov r2, r3 + 801766a: 2301 movs r3, #1 + 801766c: 4093 lsls r3, r2 + 801766e: b29b uxth r3, r3 + 8017670: 461a mov r2, r3 + 8017672: 0152 lsls r2, r2, #5 + 8017674: 1ad2 subs r2, r2, r3 + 8017676: 0092 lsls r2, r2, #2 + 8017678: 4413 add r3, r2 + 801767a: 00db lsls r3, r3, #3 + 801767c: b29b uxth r3, r3 + 801767e: e001 b.n 8017684 + 8017680: f64e 2360 movw r3, #60000 ; 0xea60 + 8017684: 81fb strh r3, [r7, #14] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 8017686: 89fb ldrh r3, [r7, #14] + 8017688: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 801768c: 4a0f ldr r2, [pc, #60] ; (80176cc ) + 801768e: fb82 1203 smull r1, r2, r2, r3 + 8017692: 1152 asrs r2, r2, #5 + 8017694: 17db asrs r3, r3, #31 + 8017696: 1ad3 subs r3, r2, r3 + 8017698: b29a uxth r2, r3 + 801769a: 69bb ldr r3, [r7, #24] + 801769c: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 801769e: f997 301f ldrsb.w r3, [r7, #31] +} + 80176a2: 4618 mov r0, r3 + 80176a4: 3720 adds r7, #32 + 80176a6: 46bd mov sp, r7 + 80176a8: bdb0 pop {r4, r5, r7, pc} + 80176aa: bf00 nop + 80176ac: 08020d70 .word 0x08020d70 + 80176b0: 08020e1c .word 0x08020e1c + 80176b4: 08020dd0 .word 0x08020dd0 + 80176b8: 08020e38 .word 0x08020e38 + 80176bc: 200000c0 .word 0x200000c0 + 80176c0: 2000cfc4 .word 0x2000cfc4 + 80176c4: 08023914 .word 0x08023914 + 80176c8: 08023918 .word 0x08023918 + 80176cc: 10624dd3 .word 0x10624dd3 + +080176d0 : + * The DHCP timer that checks for lease renewal/rebind timeouts. + * Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS). + */ +void +dhcp_coarse_tmr(void) +{ + 80176d0: b580 push {r7, lr} + 80176d2: b082 sub sp, #8 + 80176d4: af00 add r7, sp, #0 + struct netif *netif; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n")); + /* iterate through all network interfaces */ + NETIF_FOREACH(netif) { + 80176d6: 4b27 ldr r3, [pc, #156] ; (8017774 ) + 80176d8: 681b ldr r3, [r3, #0] + 80176da: 607b str r3, [r7, #4] + 80176dc: e042 b.n 8017764 + /* only act on DHCP configured interfaces */ + struct dhcp *dhcp = netif_dhcp_data(netif); + 80176de: 687b ldr r3, [r7, #4] + 80176e0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80176e2: 603b str r3, [r7, #0] + if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) { + 80176e4: 683b ldr r3, [r7, #0] + 80176e6: 2b00 cmp r3, #0 + 80176e8: d039 beq.n 801775e + 80176ea: 683b ldr r3, [r7, #0] + 80176ec: 795b ldrb r3, [r3, #5] + 80176ee: 2b00 cmp r3, #0 + 80176f0: d035 beq.n 801775e + /* compare lease time to expire timeout */ + if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) { + 80176f2: 683b ldr r3, [r7, #0] + 80176f4: 8a9b ldrh r3, [r3, #20] + 80176f6: 2b00 cmp r3, #0 + 80176f8: d012 beq.n 8017720 + 80176fa: 683b ldr r3, [r7, #0] + 80176fc: 8a5b ldrh r3, [r3, #18] + 80176fe: 3301 adds r3, #1 + 8017700: b29a uxth r2, r3 + 8017702: 683b ldr r3, [r7, #0] + 8017704: 825a strh r2, [r3, #18] + 8017706: 683b ldr r3, [r7, #0] + 8017708: 8a5a ldrh r2, [r3, #18] + 801770a: 683b ldr r3, [r7, #0] + 801770c: 8a9b ldrh r3, [r3, #20] + 801770e: 429a cmp r2, r3 + 8017710: d106 bne.n 8017720 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n")); + /* this clients' lease time has expired */ + dhcp_release_and_stop(netif); + 8017712: 6878 ldr r0, [r7, #4] + 8017714: f000 fe54 bl 80183c0 + dhcp_start(netif); + 8017718: 6878 ldr r0, [r7, #4] + 801771a: f000 f98b bl 8017a34 + 801771e: e01e b.n 801775e + /* timer is active (non zero), and triggers (zeroes) now? */ + } else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) { + 8017720: 683b ldr r3, [r7, #0] + 8017722: 8a1b ldrh r3, [r3, #16] + 8017724: 2b00 cmp r3, #0 + 8017726: d00b beq.n 8017740 + 8017728: 683b ldr r3, [r7, #0] + 801772a: 8a1b ldrh r3, [r3, #16] + 801772c: 1e5a subs r2, r3, #1 + 801772e: b291 uxth r1, r2 + 8017730: 683a ldr r2, [r7, #0] + 8017732: 8211 strh r1, [r2, #16] + 8017734: 2b01 cmp r3, #1 + 8017736: d103 bne.n 8017740 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(netif); + 8017738: 6878 ldr r0, [r7, #4] + 801773a: f000 f8c7 bl 80178cc + 801773e: e00e b.n 801775e + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) { + 8017740: 683b ldr r3, [r7, #0] + 8017742: 89db ldrh r3, [r3, #14] + 8017744: 2b00 cmp r3, #0 + 8017746: d00a beq.n 801775e + 8017748: 683b ldr r3, [r7, #0] + 801774a: 89db ldrh r3, [r3, #14] + 801774c: 1e5a subs r2, r3, #1 + 801774e: b291 uxth r1, r2 + 8017750: 683a ldr r2, [r7, #0] + 8017752: 81d1 strh r1, [r2, #14] + 8017754: 2b01 cmp r3, #1 + 8017756: d102 bne.n 801775e + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(netif); + 8017758: 6878 ldr r0, [r7, #4] + 801775a: f000 f888 bl 801786e + NETIF_FOREACH(netif) { + 801775e: 687b ldr r3, [r7, #4] + 8017760: 681b ldr r3, [r3, #0] + 8017762: 607b str r3, [r7, #4] + 8017764: 687b ldr r3, [r7, #4] + 8017766: 2b00 cmp r3, #0 + 8017768: d1b9 bne.n 80176de + } + } + } +} + 801776a: bf00 nop + 801776c: bf00 nop + 801776e: 3708 adds r7, #8 + 8017770: 46bd mov sp, r7 + 8017772: bd80 pop {r7, pc} + 8017774: 2000cf24 .word 0x2000cf24 + +08017778 : + * A DHCP server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCP request is timed out. + */ +void +dhcp_fine_tmr(void) +{ + 8017778: b580 push {r7, lr} + 801777a: b082 sub sp, #8 + 801777c: af00 add r7, sp, #0 + struct netif *netif; + /* loop through netif's */ + NETIF_FOREACH(netif) { + 801777e: 4b16 ldr r3, [pc, #88] ; (80177d8 ) + 8017780: 681b ldr r3, [r3, #0] + 8017782: 607b str r3, [r7, #4] + 8017784: e020 b.n 80177c8 + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017786: 687b ldr r3, [r7, #4] + 8017788: 6a5b ldr r3, [r3, #36] ; 0x24 + 801778a: 603b str r3, [r7, #0] + /* only act on DHCP configured interfaces */ + if (dhcp != NULL) { + 801778c: 683b ldr r3, [r7, #0] + 801778e: 2b00 cmp r3, #0 + 8017790: d017 beq.n 80177c2 + /* timer is active (non zero), and is about to trigger now */ + if (dhcp->request_timeout > 1) { + 8017792: 683b ldr r3, [r7, #0] + 8017794: 891b ldrh r3, [r3, #8] + 8017796: 2b01 cmp r3, #1 + 8017798: d906 bls.n 80177a8 + dhcp->request_timeout--; + 801779a: 683b ldr r3, [r7, #0] + 801779c: 891b ldrh r3, [r3, #8] + 801779e: 3b01 subs r3, #1 + 80177a0: b29a uxth r2, r3 + 80177a2: 683b ldr r3, [r7, #0] + 80177a4: 811a strh r2, [r3, #8] + 80177a6: e00c b.n 80177c2 + } else if (dhcp->request_timeout == 1) { + 80177a8: 683b ldr r3, [r7, #0] + 80177aa: 891b ldrh r3, [r3, #8] + 80177ac: 2b01 cmp r3, #1 + 80177ae: d108 bne.n 80177c2 + dhcp->request_timeout--; + 80177b0: 683b ldr r3, [r7, #0] + 80177b2: 891b ldrh r3, [r3, #8] + 80177b4: 3b01 subs r3, #1 + 80177b6: b29a uxth r2, r3 + 80177b8: 683b ldr r3, [r7, #0] + 80177ba: 811a strh r2, [r3, #8] + /* { dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this client's request timeout triggered */ + dhcp_timeout(netif); + 80177bc: 6878 ldr r0, [r7, #4] + 80177be: f000 f80d bl 80177dc + NETIF_FOREACH(netif) { + 80177c2: 687b ldr r3, [r7, #4] + 80177c4: 681b ldr r3, [r3, #0] + 80177c6: 607b str r3, [r7, #4] + 80177c8: 687b ldr r3, [r7, #4] + 80177ca: 2b00 cmp r3, #0 + 80177cc: d1db bne.n 8017786 + } + } + } +} + 80177ce: bf00 nop + 80177d0: bf00 nop + 80177d2: 3708 adds r7, #8 + 80177d4: 46bd mov sp, r7 + 80177d6: bd80 pop {r7, pc} + 80177d8: 2000cf24 .word 0x2000cf24 + +080177dc : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_timeout(struct netif *netif) +{ + 80177dc: b580 push {r7, lr} + 80177de: b084 sub sp, #16 + 80177e0: af00 add r7, sp, #0 + 80177e2: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 80177e4: 687b ldr r3, [r7, #4] + 80177e6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80177e8: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n")); + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) { + 80177ea: 68fb ldr r3, [r7, #12] + 80177ec: 795b ldrb r3, [r3, #5] + 80177ee: 2b0c cmp r3, #12 + 80177f0: d003 beq.n 80177fa + 80177f2: 68fb ldr r3, [r7, #12] + 80177f4: 795b ldrb r3, [r3, #5] + 80177f6: 2b06 cmp r3, #6 + 80177f8: d103 bne.n 8017802 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); + dhcp_discover(netif); + 80177fa: 6878 ldr r0, [r7, #4] + 80177fc: f000 fa76 bl 8017cec + dhcp_reboot(netif); + } else { + dhcp_discover(netif); + } + } +} + 8017800: e031 b.n 8017866 + } else if (dhcp->state == DHCP_STATE_REQUESTING) { + 8017802: 68fb ldr r3, [r7, #12] + 8017804: 795b ldrb r3, [r3, #5] + 8017806: 2b01 cmp r3, #1 + 8017808: d10e bne.n 8017828 + if (dhcp->tries <= 5) { + 801780a: 68fb ldr r3, [r7, #12] + 801780c: 799b ldrb r3, [r3, #6] + 801780e: 2b05 cmp r3, #5 + 8017810: d803 bhi.n 801781a + dhcp_select(netif); + 8017812: 6878 ldr r0, [r7, #4] + 8017814: f7ff fe60 bl 80174d8 +} + 8017818: e025 b.n 8017866 + dhcp_release_and_stop(netif); + 801781a: 6878 ldr r0, [r7, #4] + 801781c: f000 fdd0 bl 80183c0 + dhcp_start(netif); + 8017820: 6878 ldr r0, [r7, #4] + 8017822: f000 f907 bl 8017a34 +} + 8017826: e01e b.n 8017866 + } else if (dhcp->state == DHCP_STATE_CHECKING) { + 8017828: 68fb ldr r3, [r7, #12] + 801782a: 795b ldrb r3, [r3, #5] + 801782c: 2b08 cmp r3, #8 + 801782e: d10b bne.n 8017848 + if (dhcp->tries <= 1) { + 8017830: 68fb ldr r3, [r7, #12] + 8017832: 799b ldrb r3, [r3, #6] + 8017834: 2b01 cmp r3, #1 + 8017836: d803 bhi.n 8017840 + dhcp_check(netif); + 8017838: 6878 ldr r0, [r7, #4] + 801783a: f7ff fdf3 bl 8017424 +} + 801783e: e012 b.n 8017866 + dhcp_bind(netif); + 8017840: 6878 ldr r0, [r7, #4] + 8017842: f000 faf5 bl 8017e30 +} + 8017846: e00e b.n 8017866 + } else if (dhcp->state == DHCP_STATE_REBOOTING) { + 8017848: 68fb ldr r3, [r7, #12] + 801784a: 795b ldrb r3, [r3, #5] + 801784c: 2b03 cmp r3, #3 + 801784e: d10a bne.n 8017866 + if (dhcp->tries < REBOOT_TRIES) { + 8017850: 68fb ldr r3, [r7, #12] + 8017852: 799b ldrb r3, [r3, #6] + 8017854: 2b01 cmp r3, #1 + 8017856: d803 bhi.n 8017860 + dhcp_reboot(netif); + 8017858: 6878 ldr r0, [r7, #4] + 801785a: f000 fcfb bl 8018254 +} + 801785e: e002 b.n 8017866 + dhcp_discover(netif); + 8017860: 6878 ldr r0, [r7, #4] + 8017862: f000 fa43 bl 8017cec +} + 8017866: bf00 nop + 8017868: 3710 adds r7, #16 + 801786a: 46bd mov sp, r7 + 801786c: bd80 pop {r7, pc} + +0801786e : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t1_timeout(struct netif *netif) +{ + 801786e: b580 push {r7, lr} + 8017870: b084 sub sp, #16 + 8017872: af00 add r7, sp, #0 + 8017874: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017876: 687b ldr r3, [r7, #4] + 8017878: 6a5b ldr r3, [r3, #36] ; 0x24 + 801787a: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + 801787c: 68fb ldr r3, [r7, #12] + 801787e: 795b ldrb r3, [r3, #5] + 8017880: 2b01 cmp r3, #1 + 8017882: d007 beq.n 8017894 + 8017884: 68fb ldr r3, [r7, #12] + 8017886: 795b ldrb r3, [r3, #5] + 8017888: 2b0a cmp r3, #10 + 801788a: d003 beq.n 8017894 + (dhcp->state == DHCP_STATE_RENEWING)) { + 801788c: 68fb ldr r3, [r7, #12] + 801788e: 795b ldrb r3, [r3, #5] + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + 8017890: 2b05 cmp r3, #5 + 8017892: d117 bne.n 80178c4 + * eventually time-out if renew tries fail. */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t1_timeout(): must renew\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */ + dhcp_renew(netif); + 8017894: 6878 ldr r0, [r7, #4] + 8017896: f000 fba5 bl 8017fe4 + /* Calculate next timeout */ + if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) { + 801789a: 68fb ldr r3, [r7, #12] + 801789c: 899b ldrh r3, [r3, #12] + 801789e: 461a mov r2, r3 + 80178a0: 68fb ldr r3, [r7, #12] + 80178a2: 8a5b ldrh r3, [r3, #18] + 80178a4: 1ad3 subs r3, r2, r3 + 80178a6: 2b01 cmp r3, #1 + 80178a8: dd0c ble.n 80178c4 + dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2); + 80178aa: 68fb ldr r3, [r7, #12] + 80178ac: 899b ldrh r3, [r3, #12] + 80178ae: 461a mov r2, r3 + 80178b0: 68fb ldr r3, [r7, #12] + 80178b2: 8a5b ldrh r3, [r3, #18] + 80178b4: 1ad3 subs r3, r2, r3 + 80178b6: 2b00 cmp r3, #0 + 80178b8: da00 bge.n 80178bc + 80178ba: 3301 adds r3, #1 + 80178bc: 105b asrs r3, r3, #1 + 80178be: b29a uxth r2, r3 + 80178c0: 68fb ldr r3, [r7, #12] + 80178c2: 81da strh r2, [r3, #14] + } + } +} + 80178c4: bf00 nop + 80178c6: 3710 adds r7, #16 + 80178c8: 46bd mov sp, r7 + 80178ca: bd80 pop {r7, pc} + +080178cc : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t2_timeout(struct netif *netif) +{ + 80178cc: b580 push {r7, lr} + 80178ce: b084 sub sp, #16 + 80178d0: af00 add r7, sp, #0 + 80178d2: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 80178d4: 687b ldr r3, [r7, #4] + 80178d6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80178d8: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n")); + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + 80178da: 68fb ldr r3, [r7, #12] + 80178dc: 795b ldrb r3, [r3, #5] + 80178de: 2b01 cmp r3, #1 + 80178e0: d00b beq.n 80178fa + 80178e2: 68fb ldr r3, [r7, #12] + 80178e4: 795b ldrb r3, [r3, #5] + 80178e6: 2b0a cmp r3, #10 + 80178e8: d007 beq.n 80178fa + (dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) { + 80178ea: 68fb ldr r3, [r7, #12] + 80178ec: 795b ldrb r3, [r3, #5] + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + 80178ee: 2b05 cmp r3, #5 + 80178f0: d003 beq.n 80178fa + (dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) { + 80178f2: 68fb ldr r3, [r7, #12] + 80178f4: 795b ldrb r3, [r3, #5] + 80178f6: 2b04 cmp r3, #4 + 80178f8: d117 bne.n 801792a + /* just retry to rebind */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t2_timeout(): must rebind\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */ + dhcp_rebind(netif); + 80178fa: 6878 ldr r0, [r7, #4] + 80178fc: f000 fc0e bl 801811c + /* Calculate next timeout */ + if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) { + 8017900: 68fb ldr r3, [r7, #12] + 8017902: 8a9b ldrh r3, [r3, #20] + 8017904: 461a mov r2, r3 + 8017906: 68fb ldr r3, [r7, #12] + 8017908: 8a5b ldrh r3, [r3, #18] + 801790a: 1ad3 subs r3, r2, r3 + 801790c: 2b01 cmp r3, #1 + 801790e: dd0c ble.n 801792a + dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2); + 8017910: 68fb ldr r3, [r7, #12] + 8017912: 8a9b ldrh r3, [r3, #20] + 8017914: 461a mov r2, r3 + 8017916: 68fb ldr r3, [r7, #12] + 8017918: 8a5b ldrh r3, [r3, #18] + 801791a: 1ad3 subs r3, r2, r3 + 801791c: 2b00 cmp r3, #0 + 801791e: da00 bge.n 8017922 + 8017920: 3301 adds r3, #1 + 8017922: 105b asrs r3, r3, #1 + 8017924: b29a uxth r2, r3 + 8017926: 68fb ldr r3, [r7, #12] + 8017928: 821a strh r2, [r3, #16] + } + } +} + 801792a: bf00 nop + 801792c: 3710 adds r7, #16 + 801792e: 46bd mov sp, r7 + 8017930: bd80 pop {r7, pc} + ... + +08017934 : + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in) +{ + 8017934: b580 push {r7, lr} + 8017936: b086 sub sp, #24 + 8017938: af00 add r7, sp, #0 + 801793a: 6078 str r0, [r7, #4] + 801793c: 6039 str r1, [r7, #0] + struct dhcp *dhcp = netif_dhcp_data(netif); + 801793e: 687b ldr r3, [r7, #4] + 8017940: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017942: 613b str r3, [r7, #16] +#if LWIP_DHCP_GET_NTP_SRV + ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS]; +#endif + + /* clear options we might not get from the ACK */ + ip4_addr_set_zero(&dhcp->offered_sn_mask); + 8017944: 693b ldr r3, [r7, #16] + 8017946: 2200 movs r2, #0 + 8017948: 621a str r2, [r3, #32] + ip4_addr_set_zero(&dhcp->offered_gw_addr); + 801794a: 693b ldr r3, [r7, #16] + 801794c: 2200 movs r2, #0 + 801794e: 625a str r2, [r3, #36] ; 0x24 +#if LWIP_DHCP_BOOTP_FILE + ip4_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* lease time given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) { + 8017950: 4b36 ldr r3, [pc, #216] ; (8017a2c ) + 8017952: 78db ldrb r3, [r3, #3] + 8017954: 2b00 cmp r3, #0 + 8017956: d003 beq.n 8017960 + /* remember offered lease time */ + dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME); + 8017958: 4b35 ldr r3, [pc, #212] ; (8017a30 ) + 801795a: 68da ldr r2, [r3, #12] + 801795c: 693b ldr r3, [r7, #16] + 801795e: 629a str r2, [r3, #40] ; 0x28 + } + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) { + 8017960: 4b32 ldr r3, [pc, #200] ; (8017a2c ) + 8017962: 791b ldrb r3, [r3, #4] + 8017964: 2b00 cmp r3, #0 + 8017966: d004 beq.n 8017972 + /* remember given renewal period */ + dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1); + 8017968: 4b31 ldr r3, [pc, #196] ; (8017a30 ) + 801796a: 691a ldr r2, [r3, #16] + 801796c: 693b ldr r3, [r7, #16] + 801796e: 62da str r2, [r3, #44] ; 0x2c + 8017970: e004 b.n 801797c + } else { + /* calculate safe periods for renewal */ + dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; + 8017972: 693b ldr r3, [r7, #16] + 8017974: 6a9b ldr r3, [r3, #40] ; 0x28 + 8017976: 085a lsrs r2, r3, #1 + 8017978: 693b ldr r3, [r7, #16] + 801797a: 62da str r2, [r3, #44] ; 0x2c + } + + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) { + 801797c: 4b2b ldr r3, [pc, #172] ; (8017a2c ) + 801797e: 795b ldrb r3, [r3, #5] + 8017980: 2b00 cmp r3, #0 + 8017982: d004 beq.n 801798e + /* remember given rebind period */ + dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2); + 8017984: 4b2a ldr r3, [pc, #168] ; (8017a30 ) + 8017986: 695a ldr r2, [r3, #20] + 8017988: 693b ldr r3, [r7, #16] + 801798a: 631a str r2, [r3, #48] ; 0x30 + 801798c: e007 b.n 801799e + } else { + /* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/ + dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U; + 801798e: 693b ldr r3, [r7, #16] + 8017990: 6a9a ldr r2, [r3, #40] ; 0x28 + 8017992: 4613 mov r3, r2 + 8017994: 00db lsls r3, r3, #3 + 8017996: 1a9b subs r3, r3, r2 + 8017998: 08da lsrs r2, r3, #3 + 801799a: 693b ldr r3, [r7, #16] + 801799c: 631a str r2, [r3, #48] ; 0x30 + } + + /* (y)our internet address */ + ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr); + 801799e: 683b ldr r3, [r7, #0] + 80179a0: 691a ldr r2, [r3, #16] + 80179a2: 693b ldr r3, [r7, #16] + 80179a4: 61da str r2, [r3, #28] + boot file name copied in dhcp_parse_reply if not overloaded */ + ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* subnet mask given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) { + 80179a6: 4b21 ldr r3, [pc, #132] ; (8017a2c ) + 80179a8: 799b ldrb r3, [r3, #6] + 80179aa: 2b00 cmp r3, #0 + 80179ac: d00b beq.n 80179c6 + /* remember given subnet mask */ + ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK))); + 80179ae: 4b20 ldr r3, [pc, #128] ; (8017a30 ) + 80179b0: 699b ldr r3, [r3, #24] + 80179b2: 4618 mov r0, r3 + 80179b4: f7f6 fc51 bl 800e25a + 80179b8: 4602 mov r2, r0 + 80179ba: 693b ldr r3, [r7, #16] + 80179bc: 621a str r2, [r3, #32] + dhcp->subnet_mask_given = 1; + 80179be: 693b ldr r3, [r7, #16] + 80179c0: 2201 movs r2, #1 + 80179c2: 71da strb r2, [r3, #7] + 80179c4: e002 b.n 80179cc + } else { + dhcp->subnet_mask_given = 0; + 80179c6: 693b ldr r3, [r7, #16] + 80179c8: 2200 movs r2, #0 + 80179ca: 71da strb r2, [r3, #7] + } + + /* gateway router */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) { + 80179cc: 4b17 ldr r3, [pc, #92] ; (8017a2c ) + 80179ce: 79db ldrb r3, [r3, #7] + 80179d0: 2b00 cmp r3, #0 + 80179d2: d007 beq.n 80179e4 + ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER))); + 80179d4: 4b16 ldr r3, [pc, #88] ; (8017a30 ) + 80179d6: 69db ldr r3, [r3, #28] + 80179d8: 4618 mov r0, r3 + 80179da: f7f6 fc3e bl 800e25a + 80179de: 4602 mov r2, r0 + 80179e0: 693b ldr r3, [r7, #16] + 80179e2: 625a str r2, [r3, #36] ; 0x24 + dhcp_set_ntp_servers(n, ntp_server_addrs); +#endif /* LWIP_DHCP_GET_NTP_SRV */ + +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + /* DNS servers */ + for (n = 0; (n < LWIP_DHCP_PROVIDE_DNS_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) { + 80179e4: 2300 movs r3, #0 + 80179e6: 75fb strb r3, [r7, #23] + 80179e8: e013 b.n 8017a12 + ip_addr_t dns_addr; + ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n))); + 80179ea: 7dfb ldrb r3, [r7, #23] + 80179ec: 3308 adds r3, #8 + 80179ee: 4a10 ldr r2, [pc, #64] ; (8017a30 ) + 80179f0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80179f4: 4618 mov r0, r3 + 80179f6: f7f6 fc30 bl 800e25a + 80179fa: 4603 mov r3, r0 + 80179fc: 60fb str r3, [r7, #12] + dns_setserver(n, &dns_addr); + 80179fe: f107 020c add.w r2, r7, #12 + 8017a02: 7dfb ldrb r3, [r7, #23] + 8017a04: 4611 mov r1, r2 + 8017a06: 4618 mov r0, r3 + 8017a08: f7f6 fc82 bl 800e310 + for (n = 0; (n < LWIP_DHCP_PROVIDE_DNS_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) { + 8017a0c: 7dfb ldrb r3, [r7, #23] + 8017a0e: 3301 adds r3, #1 + 8017a10: 75fb strb r3, [r7, #23] + 8017a12: 7dfb ldrb r3, [r7, #23] + 8017a14: 2b01 cmp r3, #1 + 8017a16: d805 bhi.n 8017a24 + 8017a18: 7dfb ldrb r3, [r7, #23] + 8017a1a: 3308 adds r3, #8 + 8017a1c: 4a03 ldr r2, [pc, #12] ; (8017a2c ) + 8017a1e: 5cd3 ldrb r3, [r2, r3] + 8017a20: 2b00 cmp r3, #0 + 8017a22: d1e2 bne.n 80179ea + } +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ +} + 8017a24: bf00 nop + 8017a26: 3718 adds r7, #24 + 8017a28: 46bd mov sp, r7 + 8017a2a: bd80 pop {r7, pc} + 8017a2c: 2000cfb8 .word 0x2000cfb8 + 8017a30: 2000cf90 .word 0x2000cf90 + +08017a34 : + * - ERR_OK - No error + * - ERR_MEM - Out of memory + */ +err_t +dhcp_start(struct netif *netif) +{ + 8017a34: b580 push {r7, lr} + 8017a36: b084 sub sp, #16 + 8017a38: af00 add r7, sp, #0 + 8017a3a: 6078 str r0, [r7, #4] + struct dhcp *dhcp; + err_t result; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;); + 8017a3c: 687b ldr r3, [r7, #4] + 8017a3e: 2b00 cmp r3, #0 + 8017a40: d109 bne.n 8017a56 + 8017a42: 4b37 ldr r3, [pc, #220] ; (8017b20 ) + 8017a44: f240 22e7 movw r2, #743 ; 0x2e7 + 8017a48: 4936 ldr r1, [pc, #216] ; (8017b24 ) + 8017a4a: 4837 ldr r0, [pc, #220] ; (8017b28 ) + 8017a4c: f004 fae2 bl 801c014 + 8017a50: f06f 030f mvn.w r3, #15 + 8017a54: e060 b.n 8017b18 + LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;); + 8017a56: 687b ldr r3, [r7, #4] + 8017a58: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8017a5c: f003 0301 and.w r3, r3, #1 + 8017a60: 2b00 cmp r3, #0 + 8017a62: d109 bne.n 8017a78 + 8017a64: 4b2e ldr r3, [pc, #184] ; (8017b20 ) + 8017a66: f44f 723a mov.w r2, #744 ; 0x2e8 + 8017a6a: 4930 ldr r1, [pc, #192] ; (8017b2c ) + 8017a6c: 482e ldr r0, [pc, #184] ; (8017b28 ) + 8017a6e: f004 fad1 bl 801c014 + 8017a72: f06f 030f mvn.w r3, #15 + 8017a76: e04f b.n 8017b18 + dhcp = netif_dhcp_data(netif); + 8017a78: 687b ldr r3, [r7, #4] + 8017a7a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017a7c: 60fb str r3, [r7, #12] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* check MTU of the netif */ + if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) { + 8017a7e: 687b ldr r3, [r7, #4] + 8017a80: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8017a82: f5b3 7f10 cmp.w r3, #576 ; 0x240 + 8017a86: d202 bcs.n 8017a8e + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n")); + return ERR_MEM; + 8017a88: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8017a8c: e044 b.n 8017b18 + } + + /* no DHCP client attached yet? */ + if (dhcp == NULL) { + 8017a8e: 68fb ldr r3, [r7, #12] + 8017a90: 2b00 cmp r3, #0 + 8017a92: d10d bne.n 8017ab0 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n")); + dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp)); + 8017a94: 2034 movs r0, #52 ; 0x34 + 8017a96: f7f7 fee9 bl 800f86c + 8017a9a: 60f8 str r0, [r7, #12] + if (dhcp == NULL) { + 8017a9c: 68fb ldr r3, [r7, #12] + 8017a9e: 2b00 cmp r3, #0 + 8017aa0: d102 bne.n 8017aa8 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); + return ERR_MEM; + 8017aa2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8017aa6: e037 b.n 8017b18 + } + + /* store this dhcp client in the netif */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp); + 8017aa8: 687b ldr r3, [r7, #4] + 8017aaa: 68fa ldr r2, [r7, #12] + 8017aac: 625a str r2, [r3, #36] ; 0x24 + 8017aae: e005 b.n 8017abc + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp")); + /* already has DHCP client attached */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n")); + + if (dhcp->pcb_allocated != 0) { + 8017ab0: 68fb ldr r3, [r7, #12] + 8017ab2: 791b ldrb r3, [r3, #4] + 8017ab4: 2b00 cmp r3, #0 + 8017ab6: d001 beq.n 8017abc + dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ + 8017ab8: f7ff fc70 bl 801739c + } + /* dhcp is cleared below, no need to reset flag*/ + } + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + 8017abc: 2234 movs r2, #52 ; 0x34 + 8017abe: 2100 movs r1, #0 + 8017ac0: 68f8 ldr r0, [r7, #12] + 8017ac2: f004 fa0a bl 801beda + /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */ + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + + if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */ + 8017ac6: f7ff fc17 bl 80172f8 + 8017aca: 4603 mov r3, r0 + 8017acc: 2b00 cmp r3, #0 + 8017ace: d002 beq.n 8017ad6 + return ERR_MEM; + 8017ad0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8017ad4: e020 b.n 8017b18 + } + dhcp->pcb_allocated = 1; + 8017ad6: 68fb ldr r3, [r7, #12] + 8017ad8: 2201 movs r2, #1 + 8017ada: 711a strb r2, [r3, #4] + + if (!netif_is_link_up(netif)) { + 8017adc: 687b ldr r3, [r7, #4] + 8017ade: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8017ae2: f003 0304 and.w r3, r3, #4 + 8017ae6: 2b00 cmp r3, #0 + 8017ae8: d105 bne.n 8017af6 + /* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */ + dhcp_set_state(dhcp, DHCP_STATE_INIT); + 8017aea: 2102 movs r1, #2 + 8017aec: 68f8 ldr r0, [r7, #12] + 8017aee: f000 fd01 bl 80184f4 + return ERR_OK; + 8017af2: 2300 movs r3, #0 + 8017af4: e010 b.n 8017b18 + } + + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + 8017af6: 6878 ldr r0, [r7, #4] + 8017af8: f000 f8f8 bl 8017cec + 8017afc: 4603 mov r3, r0 + 8017afe: 72fb strb r3, [r7, #11] + if (result != ERR_OK) { + 8017b00: f997 300b ldrsb.w r3, [r7, #11] + 8017b04: 2b00 cmp r3, #0 + 8017b06: d005 beq.n 8017b14 + /* free resources allocated above */ + dhcp_release_and_stop(netif); + 8017b08: 6878 ldr r0, [r7, #4] + 8017b0a: f000 fc59 bl 80183c0 + return ERR_MEM; + 8017b0e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8017b12: e001 b.n 8017b18 + } + return result; + 8017b14: f997 300b ldrsb.w r3, [r7, #11] +} + 8017b18: 4618 mov r0, r3 + 8017b1a: 3710 adds r7, #16 + 8017b1c: 46bd mov sp, r7 + 8017b1e: bd80 pop {r7, pc} + 8017b20: 08020d70 .word 0x08020d70 + 8017b24: 08020e54 .word 0x08020e54 + 8017b28: 08020dd0 .word 0x08020dd0 + 8017b2c: 08020e98 .word 0x08020e98 + +08017b30 : + * This enters the REBOOTING state to verify that the currently bound + * address is still valid. + */ +void +dhcp_network_changed(struct netif *netif) +{ + 8017b30: b580 push {r7, lr} + 8017b32: b084 sub sp, #16 + 8017b34: af00 add r7, sp, #0 + 8017b36: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017b38: 687b ldr r3, [r7, #4] + 8017b3a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017b3c: 60fb str r3, [r7, #12] + + if (!dhcp) { + 8017b3e: 68fb ldr r3, [r7, #12] + 8017b40: 2b00 cmp r3, #0 + 8017b42: d025 beq.n 8017b90 + return; + } + switch (dhcp->state) { + 8017b44: 68fb ldr r3, [r7, #12] + 8017b46: 795b ldrb r3, [r3, #5] + 8017b48: 2b0a cmp r3, #10 + 8017b4a: d008 beq.n 8017b5e + 8017b4c: 2b0a cmp r3, #10 + 8017b4e: dc0d bgt.n 8017b6c + 8017b50: 2b00 cmp r3, #0 + 8017b52: d01f beq.n 8017b94 + 8017b54: 2b00 cmp r3, #0 + 8017b56: db09 blt.n 8017b6c + 8017b58: 3b03 subs r3, #3 + 8017b5a: 2b02 cmp r3, #2 + 8017b5c: d806 bhi.n 8017b6c + case DHCP_STATE_REBINDING: + case DHCP_STATE_RENEWING: + case DHCP_STATE_BOUND: + case DHCP_STATE_REBOOTING: + dhcp->tries = 0; + 8017b5e: 68fb ldr r3, [r7, #12] + 8017b60: 2200 movs r2, #0 + 8017b62: 719a strb r2, [r3, #6] + dhcp_reboot(netif); + 8017b64: 6878 ldr r0, [r7, #4] + 8017b66: f000 fb75 bl 8018254 + break; + 8017b6a: e014 b.n 8017b96 + case DHCP_STATE_OFF: + /* stay off */ + break; + default: + LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF); + 8017b6c: 68fb ldr r3, [r7, #12] + 8017b6e: 795b ldrb r3, [r3, #5] + 8017b70: 2b0c cmp r3, #12 + 8017b72: d906 bls.n 8017b82 + 8017b74: 4b09 ldr r3, [pc, #36] ; (8017b9c ) + 8017b76: f240 326d movw r2, #877 ; 0x36d + 8017b7a: 4909 ldr r1, [pc, #36] ; (8017ba0 ) + 8017b7c: 4809 ldr r0, [pc, #36] ; (8017ba4 ) + 8017b7e: f004 fa49 bl 801c014 + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + /* ensure we start with short timeouts, even if already discovering */ + dhcp->tries = 0; + 8017b82: 68fb ldr r3, [r7, #12] + 8017b84: 2200 movs r2, #0 + 8017b86: 719a strb r2, [r3, #6] + dhcp_discover(netif); + 8017b88: 6878 ldr r0, [r7, #4] + 8017b8a: f000 f8af bl 8017cec + break; + 8017b8e: e002 b.n 8017b96 + return; + 8017b90: bf00 nop + 8017b92: e000 b.n 8017b96 + break; + 8017b94: bf00 nop + } +} + 8017b96: 3710 adds r7, #16 + 8017b98: 46bd mov sp, r7 + 8017b9a: bd80 pop {r7, pc} + 8017b9c: 08020d70 .word 0x08020d70 + 8017ba0: 08020ebc .word 0x08020ebc + 8017ba4: 08020dd0 .word 0x08020dd0 + +08017ba8 : + * @param netif the network interface on which the reply was received + * @param addr The IP address we received a reply from + */ +void +dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr) +{ + 8017ba8: b580 push {r7, lr} + 8017baa: b084 sub sp, #16 + 8017bac: af00 add r7, sp, #0 + 8017bae: 6078 str r0, [r7, #4] + 8017bb0: 6039 str r1, [r7, #0] + struct dhcp *dhcp; + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + 8017bb2: 687b ldr r3, [r7, #4] + 8017bb4: 2b00 cmp r3, #0 + 8017bb6: d107 bne.n 8017bc8 + 8017bb8: 4b0e ldr r3, [pc, #56] ; (8017bf4 ) + 8017bba: f240 328b movw r2, #907 ; 0x38b + 8017bbe: 490e ldr r1, [pc, #56] ; (8017bf8 ) + 8017bc0: 480e ldr r0, [pc, #56] ; (8017bfc ) + 8017bc2: f004 fa27 bl 801c014 + 8017bc6: e012 b.n 8017bee + dhcp = netif_dhcp_data(netif); + 8017bc8: 687b ldr r3, [r7, #4] + 8017bca: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017bcc: 60fb str r3, [r7, #12] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n")); + /* is a DHCP client doing an ARP check? */ + if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) { + 8017bce: 68fb ldr r3, [r7, #12] + 8017bd0: 2b00 cmp r3, #0 + 8017bd2: d00c beq.n 8017bee + 8017bd4: 68fb ldr r3, [r7, #12] + 8017bd6: 795b ldrb r3, [r3, #5] + 8017bd8: 2b08 cmp r3, #8 + 8017bda: d108 bne.n 8017bee + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", + ip4_addr_get_u32(addr))); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) { + 8017bdc: 683b ldr r3, [r7, #0] + 8017bde: 681a ldr r2, [r3, #0] + 8017be0: 68fb ldr r3, [r7, #12] + 8017be2: 69db ldr r3, [r3, #28] + 8017be4: 429a cmp r2, r3 + 8017be6: d102 bne.n 8017bee + /* we will not accept the offered address */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); + dhcp_decline(netif); + 8017be8: 6878 ldr r0, [r7, #4] + 8017bea: f000 f809 bl 8017c00 + } + } +} + 8017bee: 3710 adds r7, #16 + 8017bf0: 46bd mov sp, r7 + 8017bf2: bd80 pop {r7, pc} + 8017bf4: 08020d70 .word 0x08020d70 + 8017bf8: 08020e54 .word 0x08020e54 + 8017bfc: 08020dd0 .word 0x08020dd0 + +08017c00 : + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_decline(struct netif *netif) +{ + 8017c00: b5b0 push {r4, r5, r7, lr} + 8017c02: b08a sub sp, #40 ; 0x28 + 8017c04: af02 add r7, sp, #8 + 8017c06: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017c08: 687b ldr r3, [r7, #4] + 8017c0a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017c0c: 61bb str r3, [r7, #24] + u16_t msecs; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n")); + dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); + 8017c0e: 210c movs r1, #12 + 8017c10: 69b8 ldr r0, [r7, #24] + 8017c12: f000 fc6f bl 80184f4 + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len); + 8017c16: f107 030c add.w r3, r7, #12 + 8017c1a: 2204 movs r2, #4 + 8017c1c: 69b9 ldr r1, [r7, #24] + 8017c1e: 6878 ldr r0, [r7, #4] + 8017c20: f001 f924 bl 8018e6c + 8017c24: 6178 str r0, [r7, #20] + if (p_out != NULL) { + 8017c26: 697b ldr r3, [r7, #20] + 8017c28: 2b00 cmp r3, #0 + 8017c2a: d035 beq.n 8017c98 + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8017c2c: 697b ldr r3, [r7, #20] + 8017c2e: 685b ldr r3, [r3, #4] + 8017c30: 613b str r3, [r7, #16] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + 8017c32: 89b8 ldrh r0, [r7, #12] + 8017c34: 693b ldr r3, [r7, #16] + 8017c36: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017c3a: 2304 movs r3, #4 + 8017c3c: 2232 movs r2, #50 ; 0x32 + 8017c3e: f000 fc73 bl 8018528 + 8017c42: 4603 mov r3, r0 + 8017c44: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + 8017c46: 89bc ldrh r4, [r7, #12] + 8017c48: 693b ldr r3, [r7, #16] + 8017c4a: f103 05f0 add.w r5, r3, #240 ; 0xf0 + 8017c4e: 69bb ldr r3, [r7, #24] + 8017c50: 69db ldr r3, [r3, #28] + 8017c52: 4618 mov r0, r3 + 8017c54: f7f6 fb01 bl 800e25a + 8017c58: 4603 mov r3, r0 + 8017c5a: 461a mov r2, r3 + 8017c5c: 4629 mov r1, r5 + 8017c5e: 4620 mov r0, r4 + 8017c60: f000 fcee bl 8018640 + 8017c64: 4603 mov r3, r0 + 8017c66: 81bb strh r3, [r7, #12] + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 8017c68: 89b8 ldrh r0, [r7, #12] + 8017c6a: 693b ldr r3, [r7, #16] + 8017c6c: 33f0 adds r3, #240 ; 0xf0 + 8017c6e: 697a ldr r2, [r7, #20] + 8017c70: 4619 mov r1, r3 + 8017c72: f001 f9d1 bl 8019018 + + /* per section 4.4.4, broadcast DECLINE messages */ + result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + 8017c76: 4b19 ldr r3, [pc, #100] ; (8017cdc ) + 8017c78: 6818 ldr r0, [r3, #0] + 8017c7a: 4b19 ldr r3, [pc, #100] ; (8017ce0 ) + 8017c7c: 9301 str r3, [sp, #4] + 8017c7e: 687b ldr r3, [r7, #4] + 8017c80: 9300 str r3, [sp, #0] + 8017c82: 2343 movs r3, #67 ; 0x43 + 8017c84: 4a17 ldr r2, [pc, #92] ; (8017ce4 ) + 8017c86: 6979 ldr r1, [r7, #20] + 8017c88: f7ff f87c bl 8016d84 + 8017c8c: 4603 mov r3, r0 + 8017c8e: 77fb strb r3, [r7, #31] + pbuf_free(p_out); + 8017c90: 6978 ldr r0, [r7, #20] + 8017c92: f7f8 feb5 bl 8010a00 + 8017c96: e001 b.n 8017c9c + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_decline: could not allocate DHCP request\n")); + result = ERR_MEM; + 8017c98: 23ff movs r3, #255 ; 0xff + 8017c9a: 77fb strb r3, [r7, #31] + } + if (dhcp->tries < 255) { + 8017c9c: 69bb ldr r3, [r7, #24] + 8017c9e: 799b ldrb r3, [r3, #6] + 8017ca0: 2bff cmp r3, #255 ; 0xff + 8017ca2: d005 beq.n 8017cb0 + dhcp->tries++; + 8017ca4: 69bb ldr r3, [r7, #24] + 8017ca6: 799b ldrb r3, [r3, #6] + 8017ca8: 3301 adds r3, #1 + 8017caa: b2da uxtb r2, r3 + 8017cac: 69bb ldr r3, [r7, #24] + 8017cae: 719a strb r2, [r3, #6] + } + msecs = 10 * 1000; + 8017cb0: f242 7310 movw r3, #10000 ; 0x2710 + 8017cb4: 81fb strh r3, [r7, #14] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 8017cb6: 89fb ldrh r3, [r7, #14] + 8017cb8: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 8017cbc: 4a0a ldr r2, [pc, #40] ; (8017ce8 ) + 8017cbe: fb82 1203 smull r1, r2, r2, r3 + 8017cc2: 1152 asrs r2, r2, #5 + 8017cc4: 17db asrs r3, r3, #31 + 8017cc6: 1ad3 subs r3, r2, r3 + 8017cc8: b29a uxth r2, r3 + 8017cca: 69bb ldr r3, [r7, #24] + 8017ccc: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 8017cce: f997 301f ldrsb.w r3, [r7, #31] +} + 8017cd2: 4618 mov r0, r3 + 8017cd4: 3720 adds r7, #32 + 8017cd6: 46bd mov sp, r7 + 8017cd8: bdb0 pop {r4, r5, r7, pc} + 8017cda: bf00 nop + 8017cdc: 2000cfc4 .word 0x2000cfc4 + 8017ce0: 08023914 .word 0x08023914 + 8017ce4: 08023918 .word 0x08023918 + 8017ce8: 10624dd3 .word 0x10624dd3 + +08017cec : + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_discover(struct netif *netif) +{ + 8017cec: b580 push {r7, lr} + 8017cee: b08a sub sp, #40 ; 0x28 + 8017cf0: af02 add r7, sp, #8 + 8017cf2: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017cf4: 687b ldr r3, [r7, #4] + 8017cf6: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017cf8: 61bb str r3, [r7, #24] + err_t result = ERR_OK; + 8017cfa: 2300 movs r3, #0 + 8017cfc: 75fb strb r3, [r7, #23] + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n")); + + ip4_addr_set_any(&dhcp->offered_ip_addr); + 8017cfe: 69bb ldr r3, [r7, #24] + 8017d00: 2200 movs r2, #0 + 8017d02: 61da str r2, [r3, #28] + dhcp_set_state(dhcp, DHCP_STATE_SELECTING); + 8017d04: 2106 movs r1, #6 + 8017d06: 69b8 ldr r0, [r7, #24] + 8017d08: f000 fbf4 bl 80184f4 + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len); + 8017d0c: f107 0308 add.w r3, r7, #8 + 8017d10: 2201 movs r2, #1 + 8017d12: 69b9 ldr r1, [r7, #24] + 8017d14: 6878 ldr r0, [r7, #4] + 8017d16: f001 f8a9 bl 8018e6c + 8017d1a: 6138 str r0, [r7, #16] + if (p_out != NULL) { + 8017d1c: 693b ldr r3, [r7, #16] + 8017d1e: 2b00 cmp r3, #0 + 8017d20: d04b beq.n 8017dba + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8017d22: 693b ldr r3, [r7, #16] + 8017d24: 685b ldr r3, [r3, #4] + 8017d26: 60fb str r3, [r7, #12] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n")); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + 8017d28: 8938 ldrh r0, [r7, #8] + 8017d2a: 68fb ldr r3, [r7, #12] + 8017d2c: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017d30: 2302 movs r3, #2 + 8017d32: 2239 movs r2, #57 ; 0x39 + 8017d34: f000 fbf8 bl 8018528 + 8017d38: 4603 mov r3, r0 + 8017d3a: 813b strh r3, [r7, #8] + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + 8017d3c: 8938 ldrh r0, [r7, #8] + 8017d3e: 68fb ldr r3, [r7, #12] + 8017d40: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017d44: 687b ldr r3, [r7, #4] + 8017d46: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8017d48: 461a mov r2, r3 + 8017d4a: f000 fc47 bl 80185dc + 8017d4e: 4603 mov r3, r0 + 8017d50: 813b strh r3, [r7, #8] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + 8017d52: 8938 ldrh r0, [r7, #8] + 8017d54: 68fb ldr r3, [r7, #12] + 8017d56: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017d5a: 2304 movs r3, #4 + 8017d5c: 2237 movs r2, #55 ; 0x37 + 8017d5e: f000 fbe3 bl 8018528 + 8017d62: 4603 mov r3, r0 + 8017d64: 813b strh r3, [r7, #8] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8017d66: 2300 movs r3, #0 + 8017d68: 77fb strb r3, [r7, #31] + 8017d6a: e00e b.n 8017d8a + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + 8017d6c: 8938 ldrh r0, [r7, #8] + 8017d6e: 68fb ldr r3, [r7, #12] + 8017d70: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8017d74: 7ffb ldrb r3, [r7, #31] + 8017d76: 4a29 ldr r2, [pc, #164] ; (8017e1c ) + 8017d78: 5cd3 ldrb r3, [r2, r3] + 8017d7a: 461a mov r2, r3 + 8017d7c: f000 fc08 bl 8018590 + 8017d80: 4603 mov r3, r0 + 8017d82: 813b strh r3, [r7, #8] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8017d84: 7ffb ldrb r3, [r7, #31] + 8017d86: 3301 adds r3, #1 + 8017d88: 77fb strb r3, [r7, #31] + 8017d8a: 7ffb ldrb r3, [r7, #31] + 8017d8c: 2b03 cmp r3, #3 + 8017d8e: d9ed bls.n 8017d6c + } + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 8017d90: 8938 ldrh r0, [r7, #8] + 8017d92: 68fb ldr r3, [r7, #12] + 8017d94: 33f0 adds r3, #240 ; 0xf0 + 8017d96: 693a ldr r2, [r7, #16] + 8017d98: 4619 mov r1, r3 + 8017d9a: f001 f93d bl 8019018 + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n")); + udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + 8017d9e: 4b20 ldr r3, [pc, #128] ; (8017e20 ) + 8017da0: 6818 ldr r0, [r3, #0] + 8017da2: 4b20 ldr r3, [pc, #128] ; (8017e24 ) + 8017da4: 9301 str r3, [sp, #4] + 8017da6: 687b ldr r3, [r7, #4] + 8017da8: 9300 str r3, [sp, #0] + 8017daa: 2343 movs r3, #67 ; 0x43 + 8017dac: 4a1e ldr r2, [pc, #120] ; (8017e28 ) + 8017dae: 6939 ldr r1, [r7, #16] + 8017db0: f7fe ffe8 bl 8016d84 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n")); + pbuf_free(p_out); + 8017db4: 6938 ldr r0, [r7, #16] + 8017db6: f7f8 fe23 bl 8010a00 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n")); + } + if (dhcp->tries < 255) { + 8017dba: 69bb ldr r3, [r7, #24] + 8017dbc: 799b ldrb r3, [r3, #6] + 8017dbe: 2bff cmp r3, #255 ; 0xff + 8017dc0: d005 beq.n 8017dce + dhcp->tries++; + 8017dc2: 69bb ldr r3, [r7, #24] + 8017dc4: 799b ldrb r3, [r3, #6] + 8017dc6: 3301 adds r3, #1 + 8017dc8: b2da uxtb r2, r3 + 8017dca: 69bb ldr r3, [r7, #24] + 8017dcc: 719a strb r2, [r3, #6] + if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) { + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON; + autoip_start(netif); + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000); + 8017dce: 69bb ldr r3, [r7, #24] + 8017dd0: 799b ldrb r3, [r3, #6] + 8017dd2: 2b05 cmp r3, #5 + 8017dd4: d80d bhi.n 8017df2 + 8017dd6: 69bb ldr r3, [r7, #24] + 8017dd8: 799b ldrb r3, [r3, #6] + 8017dda: 461a mov r2, r3 + 8017ddc: 2301 movs r3, #1 + 8017dde: 4093 lsls r3, r2 + 8017de0: b29b uxth r3, r3 + 8017de2: 461a mov r2, r3 + 8017de4: 0152 lsls r2, r2, #5 + 8017de6: 1ad2 subs r2, r2, r3 + 8017de8: 0092 lsls r2, r2, #2 + 8017dea: 4413 add r3, r2 + 8017dec: 00db lsls r3, r3, #3 + 8017dee: b29b uxth r3, r3 + 8017df0: e001 b.n 8017df6 + 8017df2: f64e 2360 movw r3, #60000 ; 0xea60 + 8017df6: 817b strh r3, [r7, #10] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 8017df8: 897b ldrh r3, [r7, #10] + 8017dfa: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 8017dfe: 4a0b ldr r2, [pc, #44] ; (8017e2c ) + 8017e00: fb82 1203 smull r1, r2, r2, r3 + 8017e04: 1152 asrs r2, r2, #5 + 8017e06: 17db asrs r3, r3, #31 + 8017e08: 1ad3 subs r3, r2, r3 + 8017e0a: b29a uxth r2, r3 + 8017e0c: 69bb ldr r3, [r7, #24] + 8017e0e: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 8017e10: f997 3017 ldrsb.w r3, [r7, #23] +} + 8017e14: 4618 mov r0, r3 + 8017e16: 3720 adds r7, #32 + 8017e18: 46bd mov sp, r7 + 8017e1a: bd80 pop {r7, pc} + 8017e1c: 200000c0 .word 0x200000c0 + 8017e20: 2000cfc4 .word 0x2000cfc4 + 8017e24: 08023914 .word 0x08023914 + 8017e28: 08023918 .word 0x08023918 + 8017e2c: 10624dd3 .word 0x10624dd3 + +08017e30 : + * + * @param netif network interface to bind to the offered address + */ +static void +dhcp_bind(struct netif *netif) +{ + 8017e30: b580 push {r7, lr} + 8017e32: b088 sub sp, #32 + 8017e34: af00 add r7, sp, #0 + 8017e36: 6078 str r0, [r7, #4] + u32_t timeout; + struct dhcp *dhcp; + ip4_addr_t sn_mask, gw_addr; + LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;); + 8017e38: 687b ldr r3, [r7, #4] + 8017e3a: 2b00 cmp r3, #0 + 8017e3c: d107 bne.n 8017e4e + 8017e3e: 4b64 ldr r3, [pc, #400] ; (8017fd0 ) + 8017e40: f240 4215 movw r2, #1045 ; 0x415 + 8017e44: 4963 ldr r1, [pc, #396] ; (8017fd4 ) + 8017e46: 4864 ldr r0, [pc, #400] ; (8017fd8 ) + 8017e48: f004 f8e4 bl 801c014 + 8017e4c: e0bc b.n 8017fc8 + dhcp = netif_dhcp_data(netif); + 8017e4e: 687b ldr r3, [r7, #4] + 8017e50: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017e52: 61bb str r3, [r7, #24] + LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;); + 8017e54: 69bb ldr r3, [r7, #24] + 8017e56: 2b00 cmp r3, #0 + 8017e58: d107 bne.n 8017e6a + 8017e5a: 4b5d ldr r3, [pc, #372] ; (8017fd0 ) + 8017e5c: f240 4217 movw r2, #1047 ; 0x417 + 8017e60: 495e ldr r1, [pc, #376] ; (8017fdc ) + 8017e62: 485d ldr r0, [pc, #372] ; (8017fd8 ) + 8017e64: f004 f8d6 bl 801c014 + 8017e68: e0ae b.n 8017fc8 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* reset time used of lease */ + dhcp->lease_used = 0; + 8017e6a: 69bb ldr r3, [r7, #24] + 8017e6c: 2200 movs r2, #0 + 8017e6e: 825a strh r2, [r3, #18] + + if (dhcp->offered_t0_lease != 0xffffffffUL) { + 8017e70: 69bb ldr r3, [r7, #24] + 8017e72: 6a9b ldr r3, [r3, #40] ; 0x28 + 8017e74: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8017e78: d019 beq.n 8017eae + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease)); + timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + 8017e7a: 69bb ldr r3, [r7, #24] + 8017e7c: 6a9b ldr r3, [r3, #40] ; 0x28 + 8017e7e: 331e adds r3, #30 + 8017e80: 4a57 ldr r2, [pc, #348] ; (8017fe0 ) + 8017e82: fba2 2303 umull r2, r3, r2, r3 + 8017e86: 095b lsrs r3, r3, #5 + 8017e88: 61fb str r3, [r7, #28] + if (timeout > 0xffff) { + 8017e8a: 69fb ldr r3, [r7, #28] + 8017e8c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8017e90: d302 bcc.n 8017e98 + timeout = 0xffff; + 8017e92: f64f 73ff movw r3, #65535 ; 0xffff + 8017e96: 61fb str r3, [r7, #28] + } + dhcp->t0_timeout = (u16_t)timeout; + 8017e98: 69fb ldr r3, [r7, #28] + 8017e9a: b29a uxth r2, r3 + 8017e9c: 69bb ldr r3, [r7, #24] + 8017e9e: 829a strh r2, [r3, #20] + if (dhcp->t0_timeout == 0) { + 8017ea0: 69bb ldr r3, [r7, #24] + 8017ea2: 8a9b ldrh r3, [r3, #20] + 8017ea4: 2b00 cmp r3, #0 + 8017ea6: d102 bne.n 8017eae + dhcp->t0_timeout = 1; + 8017ea8: 69bb ldr r3, [r7, #24] + 8017eaa: 2201 movs r2, #1 + 8017eac: 829a strh r2, [r3, #20] + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000)); + } + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + 8017eae: 69bb ldr r3, [r7, #24] + 8017eb0: 6adb ldr r3, [r3, #44] ; 0x2c + 8017eb2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8017eb6: d01d beq.n 8017ef4 + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); + timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + 8017eb8: 69bb ldr r3, [r7, #24] + 8017eba: 6adb ldr r3, [r3, #44] ; 0x2c + 8017ebc: 331e adds r3, #30 + 8017ebe: 4a48 ldr r2, [pc, #288] ; (8017fe0 ) + 8017ec0: fba2 2303 umull r2, r3, r2, r3 + 8017ec4: 095b lsrs r3, r3, #5 + 8017ec6: 61fb str r3, [r7, #28] + if (timeout > 0xffff) { + 8017ec8: 69fb ldr r3, [r7, #28] + 8017eca: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8017ece: d302 bcc.n 8017ed6 + timeout = 0xffff; + 8017ed0: f64f 73ff movw r3, #65535 ; 0xffff + 8017ed4: 61fb str r3, [r7, #28] + } + dhcp->t1_timeout = (u16_t)timeout; + 8017ed6: 69fb ldr r3, [r7, #28] + 8017ed8: b29a uxth r2, r3 + 8017eda: 69bb ldr r3, [r7, #24] + 8017edc: 815a strh r2, [r3, #10] + if (dhcp->t1_timeout == 0) { + 8017ede: 69bb ldr r3, [r7, #24] + 8017ee0: 895b ldrh r3, [r3, #10] + 8017ee2: 2b00 cmp r3, #0 + 8017ee4: d102 bne.n 8017eec + dhcp->t1_timeout = 1; + 8017ee6: 69bb ldr r3, [r7, #24] + 8017ee8: 2201 movs r2, #1 + 8017eea: 815a strh r2, [r3, #10] + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000)); + dhcp->t1_renew_time = dhcp->t1_timeout; + 8017eec: 69bb ldr r3, [r7, #24] + 8017eee: 895a ldrh r2, [r3, #10] + 8017ef0: 69bb ldr r3, [r7, #24] + 8017ef2: 81da strh r2, [r3, #14] + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { + 8017ef4: 69bb ldr r3, [r7, #24] + 8017ef6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8017ef8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8017efc: d01d beq.n 8017f3a + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); + timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + 8017efe: 69bb ldr r3, [r7, #24] + 8017f00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8017f02: 331e adds r3, #30 + 8017f04: 4a36 ldr r2, [pc, #216] ; (8017fe0 ) + 8017f06: fba2 2303 umull r2, r3, r2, r3 + 8017f0a: 095b lsrs r3, r3, #5 + 8017f0c: 61fb str r3, [r7, #28] + if (timeout > 0xffff) { + 8017f0e: 69fb ldr r3, [r7, #28] + 8017f10: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8017f14: d302 bcc.n 8017f1c + timeout = 0xffff; + 8017f16: f64f 73ff movw r3, #65535 ; 0xffff + 8017f1a: 61fb str r3, [r7, #28] + } + dhcp->t2_timeout = (u16_t)timeout; + 8017f1c: 69fb ldr r3, [r7, #28] + 8017f1e: b29a uxth r2, r3 + 8017f20: 69bb ldr r3, [r7, #24] + 8017f22: 819a strh r2, [r3, #12] + if (dhcp->t2_timeout == 0) { + 8017f24: 69bb ldr r3, [r7, #24] + 8017f26: 899b ldrh r3, [r3, #12] + 8017f28: 2b00 cmp r3, #0 + 8017f2a: d102 bne.n 8017f32 + dhcp->t2_timeout = 1; + 8017f2c: 69bb ldr r3, [r7, #24] + 8017f2e: 2201 movs r2, #1 + 8017f30: 819a strh r2, [r3, #12] + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000)); + dhcp->t2_rebind_time = dhcp->t2_timeout; + 8017f32: 69bb ldr r3, [r7, #24] + 8017f34: 899a ldrh r2, [r3, #12] + 8017f36: 69bb ldr r3, [r7, #24] + 8017f38: 821a strh r2, [r3, #16] + } + + /* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */ + if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) { + 8017f3a: 69bb ldr r3, [r7, #24] + 8017f3c: 895a ldrh r2, [r3, #10] + 8017f3e: 69bb ldr r3, [r7, #24] + 8017f40: 899b ldrh r3, [r3, #12] + 8017f42: 429a cmp r2, r3 + 8017f44: d306 bcc.n 8017f54 + 8017f46: 69bb ldr r3, [r7, #24] + 8017f48: 899b ldrh r3, [r3, #12] + 8017f4a: 2b00 cmp r3, #0 + 8017f4c: d002 beq.n 8017f54 + dhcp->t1_timeout = 0; + 8017f4e: 69bb ldr r3, [r7, #24] + 8017f50: 2200 movs r2, #0 + 8017f52: 815a strh r2, [r3, #10] + } + + if (dhcp->subnet_mask_given) { + 8017f54: 69bb ldr r3, [r7, #24] + 8017f56: 79db ldrb r3, [r3, #7] + 8017f58: 2b00 cmp r3, #0 + 8017f5a: d003 beq.n 8017f64 + /* copy offered network mask */ + ip4_addr_copy(sn_mask, dhcp->offered_sn_mask); + 8017f5c: 69bb ldr r3, [r7, #24] + 8017f5e: 6a1b ldr r3, [r3, #32] + 8017f60: 613b str r3, [r7, #16] + 8017f62: e014 b.n 8017f8e + } else { + /* subnet mask not given, choose a safe subnet mask given the network class */ + u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr); + 8017f64: 69bb ldr r3, [r7, #24] + 8017f66: 331c adds r3, #28 + 8017f68: 781b ldrb r3, [r3, #0] + 8017f6a: 75fb strb r3, [r7, #23] + if (first_octet <= 127) { + 8017f6c: f997 3017 ldrsb.w r3, [r7, #23] + 8017f70: 2b00 cmp r3, #0 + 8017f72: db02 blt.n 8017f7a + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL)); + 8017f74: 23ff movs r3, #255 ; 0xff + 8017f76: 613b str r3, [r7, #16] + 8017f78: e009 b.n 8017f8e + } else if (first_octet >= 192) { + 8017f7a: 7dfb ldrb r3, [r7, #23] + 8017f7c: 2bbf cmp r3, #191 ; 0xbf + 8017f7e: d903 bls.n 8017f88 + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL)); + 8017f80: f06f 437f mvn.w r3, #4278190080 ; 0xff000000 + 8017f84: 613b str r3, [r7, #16] + 8017f86: e002 b.n 8017f8e + } else { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL)); + 8017f88: f64f 73ff movw r3, #65535 ; 0xffff + 8017f8c: 613b str r3, [r7, #16] + } + } + + ip4_addr_copy(gw_addr, dhcp->offered_gw_addr); + 8017f8e: 69bb ldr r3, [r7, #24] + 8017f90: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017f92: 60fb str r3, [r7, #12] + /* gateway address not given? */ + if (ip4_addr_isany_val(gw_addr)) { + 8017f94: 68fb ldr r3, [r7, #12] + 8017f96: 2b00 cmp r3, #0 + 8017f98: d108 bne.n 8017fac + /* copy network address */ + ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask); + 8017f9a: 69bb ldr r3, [r7, #24] + 8017f9c: 69da ldr r2, [r3, #28] + 8017f9e: 693b ldr r3, [r7, #16] + 8017fa0: 4013 ands r3, r2 + 8017fa2: 60fb str r3, [r7, #12] + /* use first host address on network as gateway */ + ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL)); + 8017fa4: 68fb ldr r3, [r7, #12] + 8017fa6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8017faa: 60fb str r3, [r7, #12] + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr))); + /* netif is now bound to DHCP leased address - set this before assigning the address + to ensure the callback can use dhcp_supplied_address() */ + dhcp_set_state(dhcp, DHCP_STATE_BOUND); + 8017fac: 210a movs r1, #10 + 8017fae: 69b8 ldr r0, [r7, #24] + 8017fb0: f000 faa0 bl 80184f4 + + netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr); + 8017fb4: 69bb ldr r3, [r7, #24] + 8017fb6: f103 011c add.w r1, r3, #28 + 8017fba: f107 030c add.w r3, r7, #12 + 8017fbe: f107 0210 add.w r2, r7, #16 + 8017fc2: 6878 ldr r0, [r7, #4] + 8017fc4: f7f8 f80e bl 800ffe4 + /* interface is used by routing now that an address is set */ +} + 8017fc8: 3720 adds r7, #32 + 8017fca: 46bd mov sp, r7 + 8017fcc: bd80 pop {r7, pc} + 8017fce: bf00 nop + 8017fd0: 08020d70 .word 0x08020d70 + 8017fd4: 08020ed0 .word 0x08020ed0 + 8017fd8: 08020dd0 .word 0x08020dd0 + 8017fdc: 08020eec .word 0x08020eec + 8017fe0: 88888889 .word 0x88888889 + +08017fe4 : + * + * @param netif network interface which must renew its lease + */ +err_t +dhcp_renew(struct netif *netif) +{ + 8017fe4: b580 push {r7, lr} + 8017fe6: b08a sub sp, #40 ; 0x28 + 8017fe8: af02 add r7, sp, #8 + 8017fea: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8017fec: 687b ldr r3, [r7, #4] + 8017fee: 6a5b ldr r3, [r3, #36] ; 0x24 + 8017ff0: 61bb str r3, [r7, #24] + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n")); + dhcp_set_state(dhcp, DHCP_STATE_RENEWING); + 8017ff2: 2105 movs r1, #5 + 8017ff4: 69b8 ldr r0, [r7, #24] + 8017ff6: f000 fa7d bl 80184f4 + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + 8017ffa: f107 030c add.w r3, r7, #12 + 8017ffe: 2203 movs r2, #3 + 8018000: 69b9 ldr r1, [r7, #24] + 8018002: 6878 ldr r0, [r7, #4] + 8018004: f000 ff32 bl 8018e6c + 8018008: 6178 str r0, [r7, #20] + if (p_out != NULL) { + 801800a: 697b ldr r3, [r7, #20] + 801800c: 2b00 cmp r3, #0 + 801800e: d04e beq.n 80180ae + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8018010: 697b ldr r3, [r7, #20] + 8018012: 685b ldr r3, [r3, #4] + 8018014: 613b str r3, [r7, #16] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + 8018016: 89b8 ldrh r0, [r7, #12] + 8018018: 693b ldr r3, [r7, #16] + 801801a: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 801801e: 2302 movs r3, #2 + 8018020: 2239 movs r2, #57 ; 0x39 + 8018022: f000 fa81 bl 8018528 + 8018026: 4603 mov r3, r0 + 8018028: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + 801802a: 89b8 ldrh r0, [r7, #12] + 801802c: 693b ldr r3, [r7, #16] + 801802e: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018032: 687b ldr r3, [r7, #4] + 8018034: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8018036: 461a mov r2, r3 + 8018038: f000 fad0 bl 80185dc + 801803c: 4603 mov r3, r0 + 801803e: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + 8018040: 89b8 ldrh r0, [r7, #12] + 8018042: 693b ldr r3, [r7, #16] + 8018044: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018048: 2304 movs r3, #4 + 801804a: 2237 movs r2, #55 ; 0x37 + 801804c: f000 fa6c bl 8018528 + 8018050: 4603 mov r3, r0 + 8018052: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8018054: 2300 movs r3, #0 + 8018056: 77bb strb r3, [r7, #30] + 8018058: e00e b.n 8018078 + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + 801805a: 89b8 ldrh r0, [r7, #12] + 801805c: 693b ldr r3, [r7, #16] + 801805e: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018062: 7fbb ldrb r3, [r7, #30] + 8018064: 4a2a ldr r2, [pc, #168] ; (8018110 ) + 8018066: 5cd3 ldrb r3, [r2, r3] + 8018068: 461a mov r2, r3 + 801806a: f000 fa91 bl 8018590 + 801806e: 4603 mov r3, r0 + 8018070: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8018072: 7fbb ldrb r3, [r7, #30] + 8018074: 3301 adds r3, #1 + 8018076: 77bb strb r3, [r7, #30] + 8018078: 7fbb ldrb r3, [r7, #30] + 801807a: 2b03 cmp r3, #3 + 801807c: d9ed bls.n 801805a +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 801807e: 89b8 ldrh r0, [r7, #12] + 8018080: 693b ldr r3, [r7, #16] + 8018082: 33f0 adds r3, #240 ; 0xf0 + 8018084: 697a ldr r2, [r7, #20] + 8018086: 4619 mov r1, r3 + 8018088: f000 ffc6 bl 8019018 + + result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif); + 801808c: 4b21 ldr r3, [pc, #132] ; (8018114 ) + 801808e: 6818 ldr r0, [r3, #0] + 8018090: 69bb ldr r3, [r7, #24] + 8018092: f103 0218 add.w r2, r3, #24 + 8018096: 687b ldr r3, [r7, #4] + 8018098: 9300 str r3, [sp, #0] + 801809a: 2343 movs r3, #67 ; 0x43 + 801809c: 6979 ldr r1, [r7, #20] + 801809e: f7fe fdfd bl 8016c9c + 80180a2: 4603 mov r3, r0 + 80180a4: 77fb strb r3, [r7, #31] + pbuf_free(p_out); + 80180a6: 6978 ldr r0, [r7, #20] + 80180a8: f7f8 fcaa bl 8010a00 + 80180ac: e001 b.n 80180b2 + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n")); + result = ERR_MEM; + 80180ae: 23ff movs r3, #255 ; 0xff + 80180b0: 77fb strb r3, [r7, #31] + } + if (dhcp->tries < 255) { + 80180b2: 69bb ldr r3, [r7, #24] + 80180b4: 799b ldrb r3, [r3, #6] + 80180b6: 2bff cmp r3, #255 ; 0xff + 80180b8: d005 beq.n 80180c6 + dhcp->tries++; + 80180ba: 69bb ldr r3, [r7, #24] + 80180bc: 799b ldrb r3, [r3, #6] + 80180be: 3301 adds r3, #1 + 80180c0: b2da uxtb r2, r3 + 80180c2: 69bb ldr r3, [r7, #24] + 80180c4: 719a strb r2, [r3, #6] + } + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000); + 80180c6: 69bb ldr r3, [r7, #24] + 80180c8: 799b ldrb r3, [r3, #6] + 80180ca: 2b09 cmp r3, #9 + 80180cc: d80a bhi.n 80180e4 + 80180ce: 69bb ldr r3, [r7, #24] + 80180d0: 799b ldrb r3, [r3, #6] + 80180d2: b29b uxth r3, r3 + 80180d4: 461a mov r2, r3 + 80180d6: 0152 lsls r2, r2, #5 + 80180d8: 1ad2 subs r2, r2, r3 + 80180da: 0092 lsls r2, r2, #2 + 80180dc: 4413 add r3, r2 + 80180de: 011b lsls r3, r3, #4 + 80180e0: b29b uxth r3, r3 + 80180e2: e001 b.n 80180e8 + 80180e4: f644 6320 movw r3, #20000 ; 0x4e20 + 80180e8: 81fb strh r3, [r7, #14] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 80180ea: 89fb ldrh r3, [r7, #14] + 80180ec: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 80180f0: 4a09 ldr r2, [pc, #36] ; (8018118 ) + 80180f2: fb82 1203 smull r1, r2, r2, r3 + 80180f6: 1152 asrs r2, r2, #5 + 80180f8: 17db asrs r3, r3, #31 + 80180fa: 1ad3 subs r3, r2, r3 + 80180fc: b29a uxth r2, r3 + 80180fe: 69bb ldr r3, [r7, #24] + 8018100: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 8018102: f997 301f ldrsb.w r3, [r7, #31] +} + 8018106: 4618 mov r0, r3 + 8018108: 3720 adds r7, #32 + 801810a: 46bd mov sp, r7 + 801810c: bd80 pop {r7, pc} + 801810e: bf00 nop + 8018110: 200000c0 .word 0x200000c0 + 8018114: 2000cfc4 .word 0x2000cfc4 + 8018118: 10624dd3 .word 0x10624dd3 + +0801811c : + * + * @param netif network interface which must rebind with a DHCP server + */ +static err_t +dhcp_rebind(struct netif *netif) +{ + 801811c: b580 push {r7, lr} + 801811e: b08a sub sp, #40 ; 0x28 + 8018120: af02 add r7, sp, #8 + 8018122: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8018124: 687b ldr r3, [r7, #4] + 8018126: 6a5b ldr r3, [r3, #36] ; 0x24 + 8018128: 61bb str r3, [r7, #24] + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n")); + dhcp_set_state(dhcp, DHCP_STATE_REBINDING); + 801812a: 2104 movs r1, #4 + 801812c: 69b8 ldr r0, [r7, #24] + 801812e: f000 f9e1 bl 80184f4 + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + 8018132: f107 030c add.w r3, r7, #12 + 8018136: 2203 movs r2, #3 + 8018138: 69b9 ldr r1, [r7, #24] + 801813a: 6878 ldr r0, [r7, #4] + 801813c: f000 fe96 bl 8018e6c + 8018140: 6178 str r0, [r7, #20] + if (p_out != NULL) { + 8018142: 697b ldr r3, [r7, #20] + 8018144: 2b00 cmp r3, #0 + 8018146: d04c beq.n 80181e2 + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8018148: 697b ldr r3, [r7, #20] + 801814a: 685b ldr r3, [r3, #4] + 801814c: 613b str r3, [r7, #16] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + 801814e: 89b8 ldrh r0, [r7, #12] + 8018150: 693b ldr r3, [r7, #16] + 8018152: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018156: 2302 movs r3, #2 + 8018158: 2239 movs r2, #57 ; 0x39 + 801815a: f000 f9e5 bl 8018528 + 801815e: 4603 mov r3, r0 + 8018160: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + 8018162: 89b8 ldrh r0, [r7, #12] + 8018164: 693b ldr r3, [r7, #16] + 8018166: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 801816a: 687b ldr r3, [r7, #4] + 801816c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801816e: 461a mov r2, r3 + 8018170: f000 fa34 bl 80185dc + 8018174: 4603 mov r3, r0 + 8018176: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + 8018178: 89b8 ldrh r0, [r7, #12] + 801817a: 693b ldr r3, [r7, #16] + 801817c: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018180: 2304 movs r3, #4 + 8018182: 2237 movs r2, #55 ; 0x37 + 8018184: f000 f9d0 bl 8018528 + 8018188: 4603 mov r3, r0 + 801818a: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 801818c: 2300 movs r3, #0 + 801818e: 77bb strb r3, [r7, #30] + 8018190: e00e b.n 80181b0 + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + 8018192: 89b8 ldrh r0, [r7, #12] + 8018194: 693b ldr r3, [r7, #16] + 8018196: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 801819a: 7fbb ldrb r3, [r7, #30] + 801819c: 4a29 ldr r2, [pc, #164] ; (8018244 ) + 801819e: 5cd3 ldrb r3, [r2, r3] + 80181a0: 461a mov r2, r3 + 80181a2: f000 f9f5 bl 8018590 + 80181a6: 4603 mov r3, r0 + 80181a8: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 80181aa: 7fbb ldrb r3, [r7, #30] + 80181ac: 3301 adds r3, #1 + 80181ae: 77bb strb r3, [r7, #30] + 80181b0: 7fbb ldrb r3, [r7, #30] + 80181b2: 2b03 cmp r3, #3 + 80181b4: d9ed bls.n 8018192 +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 80181b6: 89b8 ldrh r0, [r7, #12] + 80181b8: 693b ldr r3, [r7, #16] + 80181ba: 33f0 adds r3, #240 ; 0xf0 + 80181bc: 697a ldr r2, [r7, #20] + 80181be: 4619 mov r1, r3 + 80181c0: f000 ff2a bl 8019018 + + /* broadcast to server */ + result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif); + 80181c4: 4b20 ldr r3, [pc, #128] ; (8018248 ) + 80181c6: 6818 ldr r0, [r3, #0] + 80181c8: 687b ldr r3, [r7, #4] + 80181ca: 9300 str r3, [sp, #0] + 80181cc: 2343 movs r3, #67 ; 0x43 + 80181ce: 4a1f ldr r2, [pc, #124] ; (801824c ) + 80181d0: 6979 ldr r1, [r7, #20] + 80181d2: f7fe fd63 bl 8016c9c + 80181d6: 4603 mov r3, r0 + 80181d8: 77fb strb r3, [r7, #31] + pbuf_free(p_out); + 80181da: 6978 ldr r0, [r7, #20] + 80181dc: f7f8 fc10 bl 8010a00 + 80181e0: e001 b.n 80181e6 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n")); + result = ERR_MEM; + 80181e2: 23ff movs r3, #255 ; 0xff + 80181e4: 77fb strb r3, [r7, #31] + } + if (dhcp->tries < 255) { + 80181e6: 69bb ldr r3, [r7, #24] + 80181e8: 799b ldrb r3, [r3, #6] + 80181ea: 2bff cmp r3, #255 ; 0xff + 80181ec: d005 beq.n 80181fa + dhcp->tries++; + 80181ee: 69bb ldr r3, [r7, #24] + 80181f0: 799b ldrb r3, [r3, #6] + 80181f2: 3301 adds r3, #1 + 80181f4: b2da uxtb r2, r3 + 80181f6: 69bb ldr r3, [r7, #24] + 80181f8: 719a strb r2, [r3, #6] + } + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000); + 80181fa: 69bb ldr r3, [r7, #24] + 80181fc: 799b ldrb r3, [r3, #6] + 80181fe: 2b09 cmp r3, #9 + 8018200: d80a bhi.n 8018218 + 8018202: 69bb ldr r3, [r7, #24] + 8018204: 799b ldrb r3, [r3, #6] + 8018206: b29b uxth r3, r3 + 8018208: 461a mov r2, r3 + 801820a: 0152 lsls r2, r2, #5 + 801820c: 1ad2 subs r2, r2, r3 + 801820e: 0092 lsls r2, r2, #2 + 8018210: 4413 add r3, r2 + 8018212: 00db lsls r3, r3, #3 + 8018214: b29b uxth r3, r3 + 8018216: e001 b.n 801821c + 8018218: f242 7310 movw r3, #10000 ; 0x2710 + 801821c: 81fb strh r3, [r7, #14] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 801821e: 89fb ldrh r3, [r7, #14] + 8018220: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 8018224: 4a0a ldr r2, [pc, #40] ; (8018250 ) + 8018226: fb82 1203 smull r1, r2, r2, r3 + 801822a: 1152 asrs r2, r2, #5 + 801822c: 17db asrs r3, r3, #31 + 801822e: 1ad3 subs r3, r2, r3 + 8018230: b29a uxth r2, r3 + 8018232: 69bb ldr r3, [r7, #24] + 8018234: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 8018236: f997 301f ldrsb.w r3, [r7, #31] +} + 801823a: 4618 mov r0, r3 + 801823c: 3720 adds r7, #32 + 801823e: 46bd mov sp, r7 + 8018240: bd80 pop {r7, pc} + 8018242: bf00 nop + 8018244: 200000c0 .word 0x200000c0 + 8018248: 2000cfc4 .word 0x2000cfc4 + 801824c: 08023918 .word 0x08023918 + 8018250: 10624dd3 .word 0x10624dd3 + +08018254 : + * + * @param netif network interface which must reboot + */ +static err_t +dhcp_reboot(struct netif *netif) +{ + 8018254: b5b0 push {r4, r5, r7, lr} + 8018256: b08a sub sp, #40 ; 0x28 + 8018258: af02 add r7, sp, #8 + 801825a: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 801825c: 687b ldr r3, [r7, #4] + 801825e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8018260: 61bb str r3, [r7, #24] + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n")); + dhcp_set_state(dhcp, DHCP_STATE_REBOOTING); + 8018262: 2103 movs r1, #3 + 8018264: 69b8 ldr r0, [r7, #24] + 8018266: f000 f945 bl 80184f4 + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + 801826a: f107 030c add.w r3, r7, #12 + 801826e: 2203 movs r2, #3 + 8018270: 69b9 ldr r1, [r7, #24] + 8018272: 6878 ldr r0, [r7, #4] + 8018274: f000 fdfa bl 8018e6c + 8018278: 6178 str r0, [r7, #20] + if (p_out != NULL) { + 801827a: 697b ldr r3, [r7, #20] + 801827c: 2b00 cmp r3, #0 + 801827e: d066 beq.n 801834e + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8018280: 697b ldr r3, [r7, #20] + 8018282: 685b ldr r3, [r3, #4] + 8018284: 613b str r3, [r7, #16] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + 8018286: 89b8 ldrh r0, [r7, #12] + 8018288: 693b ldr r3, [r7, #16] + 801828a: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 801828e: 2302 movs r3, #2 + 8018290: 2239 movs r2, #57 ; 0x39 + 8018292: f000 f949 bl 8018528 + 8018296: 4603 mov r3, r0 + 8018298: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED); + 801829a: 89b8 ldrh r0, [r7, #12] + 801829c: 693b ldr r3, [r7, #16] + 801829e: 33f0 adds r3, #240 ; 0xf0 + 80182a0: f44f 7210 mov.w r2, #576 ; 0x240 + 80182a4: 4619 mov r1, r3 + 80182a6: f000 f999 bl 80185dc + 80182aa: 4603 mov r3, r0 + 80182ac: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + 80182ae: 89b8 ldrh r0, [r7, #12] + 80182b0: 693b ldr r3, [r7, #16] + 80182b2: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 80182b6: 2304 movs r3, #4 + 80182b8: 2232 movs r2, #50 ; 0x32 + 80182ba: f000 f935 bl 8018528 + 80182be: 4603 mov r3, r0 + 80182c0: 81bb strh r3, [r7, #12] + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + 80182c2: 89bc ldrh r4, [r7, #12] + 80182c4: 693b ldr r3, [r7, #16] + 80182c6: f103 05f0 add.w r5, r3, #240 ; 0xf0 + 80182ca: 69bb ldr r3, [r7, #24] + 80182cc: 69db ldr r3, [r3, #28] + 80182ce: 4618 mov r0, r3 + 80182d0: f7f5 ffc3 bl 800e25a + 80182d4: 4603 mov r3, r0 + 80182d6: 461a mov r2, r3 + 80182d8: 4629 mov r1, r5 + 80182da: 4620 mov r0, r4 + 80182dc: f000 f9b0 bl 8018640 + 80182e0: 4603 mov r3, r0 + 80182e2: 81bb strh r3, [r7, #12] + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + 80182e4: 89b8 ldrh r0, [r7, #12] + 80182e6: 693b ldr r3, [r7, #16] + 80182e8: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 80182ec: 2304 movs r3, #4 + 80182ee: 2237 movs r2, #55 ; 0x37 + 80182f0: f000 f91a bl 8018528 + 80182f4: 4603 mov r3, r0 + 80182f6: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 80182f8: 2300 movs r3, #0 + 80182fa: 77bb strb r3, [r7, #30] + 80182fc: e00e b.n 801831c + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + 80182fe: 89b8 ldrh r0, [r7, #12] + 8018300: 693b ldr r3, [r7, #16] + 8018302: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018306: 7fbb ldrb r3, [r7, #30] + 8018308: 4a29 ldr r2, [pc, #164] ; (80183b0 ) + 801830a: 5cd3 ldrb r3, [r2, r3] + 801830c: 461a mov r2, r3 + 801830e: f000 f93f bl 8018590 + 8018312: 4603 mov r3, r0 + 8018314: 81bb strh r3, [r7, #12] + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + 8018316: 7fbb ldrb r3, [r7, #30] + 8018318: 3301 adds r3, #1 + 801831a: 77bb strb r3, [r7, #30] + 801831c: 7fbb ldrb r3, [r7, #30] + 801831e: 2b03 cmp r3, #3 + 8018320: d9ed bls.n 80182fe +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 8018322: 89b8 ldrh r0, [r7, #12] + 8018324: 693b ldr r3, [r7, #16] + 8018326: 33f0 adds r3, #240 ; 0xf0 + 8018328: 697a ldr r2, [r7, #20] + 801832a: 4619 mov r1, r3 + 801832c: f000 fe74 bl 8019018 + + /* broadcast to server */ + result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif); + 8018330: 4b20 ldr r3, [pc, #128] ; (80183b4 ) + 8018332: 6818 ldr r0, [r3, #0] + 8018334: 687b ldr r3, [r7, #4] + 8018336: 9300 str r3, [sp, #0] + 8018338: 2343 movs r3, #67 ; 0x43 + 801833a: 4a1f ldr r2, [pc, #124] ; (80183b8 ) + 801833c: 6979 ldr r1, [r7, #20] + 801833e: f7fe fcad bl 8016c9c + 8018342: 4603 mov r3, r0 + 8018344: 77fb strb r3, [r7, #31] + pbuf_free(p_out); + 8018346: 6978 ldr r0, [r7, #20] + 8018348: f7f8 fb5a bl 8010a00 + 801834c: e001 b.n 8018352 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n")); + result = ERR_MEM; + 801834e: 23ff movs r3, #255 ; 0xff + 8018350: 77fb strb r3, [r7, #31] + } + if (dhcp->tries < 255) { + 8018352: 69bb ldr r3, [r7, #24] + 8018354: 799b ldrb r3, [r3, #6] + 8018356: 2bff cmp r3, #255 ; 0xff + 8018358: d005 beq.n 8018366 + dhcp->tries++; + 801835a: 69bb ldr r3, [r7, #24] + 801835c: 799b ldrb r3, [r3, #6] + 801835e: 3301 adds r3, #1 + 8018360: b2da uxtb r2, r3 + 8018362: 69bb ldr r3, [r7, #24] + 8018364: 719a strb r2, [r3, #6] + } + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000); + 8018366: 69bb ldr r3, [r7, #24] + 8018368: 799b ldrb r3, [r3, #6] + 801836a: 2b09 cmp r3, #9 + 801836c: d80a bhi.n 8018384 + 801836e: 69bb ldr r3, [r7, #24] + 8018370: 799b ldrb r3, [r3, #6] + 8018372: b29b uxth r3, r3 + 8018374: 461a mov r2, r3 + 8018376: 0152 lsls r2, r2, #5 + 8018378: 1ad2 subs r2, r2, r3 + 801837a: 0092 lsls r2, r2, #2 + 801837c: 4413 add r3, r2 + 801837e: 00db lsls r3, r3, #3 + 8018380: b29b uxth r3, r3 + 8018382: e001 b.n 8018388 + 8018384: f242 7310 movw r3, #10000 ; 0x2710 + 8018388: 81fb strh r3, [r7, #14] + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + 801838a: 89fb ldrh r3, [r7, #14] + 801838c: f203 13f3 addw r3, r3, #499 ; 0x1f3 + 8018390: 4a0a ldr r2, [pc, #40] ; (80183bc ) + 8018392: fb82 1203 smull r1, r2, r2, r3 + 8018396: 1152 asrs r2, r2, #5 + 8018398: 17db asrs r3, r3, #31 + 801839a: 1ad3 subs r3, r2, r3 + 801839c: b29a uxth r2, r3 + 801839e: 69bb ldr r3, [r7, #24] + 80183a0: 811a strh r2, [r3, #8] + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs)); + return result; + 80183a2: f997 301f ldrsb.w r3, [r7, #31] +} + 80183a6: 4618 mov r0, r3 + 80183a8: 3720 adds r7, #32 + 80183aa: 46bd mov sp, r7 + 80183ac: bdb0 pop {r4, r5, r7, pc} + 80183ae: bf00 nop + 80183b0: 200000c0 .word 0x200000c0 + 80183b4: 2000cfc4 .word 0x2000cfc4 + 80183b8: 08023918 .word 0x08023918 + 80183bc: 10624dd3 .word 0x10624dd3 + +080183c0 : + * + * @param netif network interface + */ +void +dhcp_release_and_stop(struct netif *netif) +{ + 80183c0: b5b0 push {r4, r5, r7, lr} + 80183c2: b08a sub sp, #40 ; 0x28 + 80183c4: af02 add r7, sp, #8 + 80183c6: 6078 str r0, [r7, #4] + struct dhcp *dhcp = netif_dhcp_data(netif); + 80183c8: 687b ldr r3, [r7, #4] + 80183ca: 6a5b ldr r3, [r3, #36] ; 0x24 + 80183cc: 61fb str r3, [r7, #28] + ip_addr_t server_ip_addr; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n")); + if (dhcp == NULL) { + 80183ce: 69fb ldr r3, [r7, #28] + 80183d0: 2b00 cmp r3, #0 + 80183d2: f000 8084 beq.w 80184de + return; + } + + /* already off? -> nothing to do */ + if (dhcp->state == DHCP_STATE_OFF) { + 80183d6: 69fb ldr r3, [r7, #28] + 80183d8: 795b ldrb r3, [r3, #5] + 80183da: 2b00 cmp r3, #0 + 80183dc: f000 8081 beq.w 80184e2 + return; + } + + ip_addr_copy(server_ip_addr, dhcp->server_ip_addr); + 80183e0: 69fb ldr r3, [r7, #28] + 80183e2: 699b ldr r3, [r3, #24] + 80183e4: 613b str r3, [r7, #16] + + /* clean old DHCP offer */ + ip_addr_set_zero_ip4(&dhcp->server_ip_addr); + 80183e6: 69fb ldr r3, [r7, #28] + 80183e8: 2200 movs r2, #0 + 80183ea: 619a str r2, [r3, #24] + ip4_addr_set_zero(&dhcp->offered_ip_addr); + 80183ec: 69fb ldr r3, [r7, #28] + 80183ee: 2200 movs r2, #0 + 80183f0: 61da str r2, [r3, #28] + ip4_addr_set_zero(&dhcp->offered_sn_mask); + 80183f2: 69fb ldr r3, [r7, #28] + 80183f4: 2200 movs r2, #0 + 80183f6: 621a str r2, [r3, #32] + ip4_addr_set_zero(&dhcp->offered_gw_addr); + 80183f8: 69fb ldr r3, [r7, #28] + 80183fa: 2200 movs r2, #0 + 80183fc: 625a str r2, [r3, #36] ; 0x24 +#if LWIP_DHCP_BOOTP_FILE + ip4_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; + 80183fe: 69fb ldr r3, [r7, #28] + 8018400: 2200 movs r2, #0 + 8018402: 631a str r2, [r3, #48] ; 0x30 + 8018404: 69fb ldr r3, [r7, #28] + 8018406: 6b1a ldr r2, [r3, #48] ; 0x30 + 8018408: 69fb ldr r3, [r7, #28] + 801840a: 62da str r2, [r3, #44] ; 0x2c + 801840c: 69fb ldr r3, [r7, #28] + 801840e: 6ada ldr r2, [r3, #44] ; 0x2c + 8018410: 69fb ldr r3, [r7, #28] + 8018412: 629a str r2, [r3, #40] ; 0x28 + dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0; + 8018414: 69fb ldr r3, [r7, #28] + 8018416: 2200 movs r2, #0 + 8018418: 829a strh r2, [r3, #20] + 801841a: 69fb ldr r3, [r7, #28] + 801841c: 8a9a ldrh r2, [r3, #20] + 801841e: 69fb ldr r3, [r7, #28] + 8018420: 825a strh r2, [r3, #18] + 8018422: 69fb ldr r3, [r7, #28] + 8018424: 8a5a ldrh r2, [r3, #18] + 8018426: 69fb ldr r3, [r7, #28] + 8018428: 821a strh r2, [r3, #16] + 801842a: 69fb ldr r3, [r7, #28] + 801842c: 8a1a ldrh r2, [r3, #16] + 801842e: 69fb ldr r3, [r7, #28] + 8018430: 81da strh r2, [r3, #14] + + /* send release message when current IP was assigned via DHCP */ + if (dhcp_supplied_address(netif)) { + 8018432: 6878 ldr r0, [r7, #4] + 8018434: f000 fe1e bl 8019074 + 8018438: 4603 mov r3, r0 + 801843a: 2b00 cmp r3, #0 + 801843c: d03b beq.n 80184b6 + /* create and initialize the DHCP message header */ + struct pbuf *p_out; + u16_t options_out_len; + p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len); + 801843e: f107 030e add.w r3, r7, #14 + 8018442: 2207 movs r2, #7 + 8018444: 69f9 ldr r1, [r7, #28] + 8018446: 6878 ldr r0, [r7, #4] + 8018448: f000 fd10 bl 8018e6c + 801844c: 61b8 str r0, [r7, #24] + if (p_out != NULL) { + 801844e: 69bb ldr r3, [r7, #24] + 8018450: 2b00 cmp r3, #0 + 8018452: d030 beq.n 80184b6 + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + 8018454: 69bb ldr r3, [r7, #24] + 8018456: 685b ldr r3, [r3, #4] + 8018458: 617b str r3, [r7, #20] + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4); + 801845a: 89f8 ldrh r0, [r7, #14] + 801845c: 697b ldr r3, [r7, #20] + 801845e: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018462: 2304 movs r3, #4 + 8018464: 2236 movs r2, #54 ; 0x36 + 8018466: f000 f85f bl 8018528 + 801846a: 4603 mov r3, r0 + 801846c: 81fb strh r3, [r7, #14] + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr)))); + 801846e: 89fc ldrh r4, [r7, #14] + 8018470: 697b ldr r3, [r7, #20] + 8018472: f103 05f0 add.w r5, r3, #240 ; 0xf0 + 8018476: 693b ldr r3, [r7, #16] + 8018478: 4618 mov r0, r3 + 801847a: f7f5 feee bl 800e25a + 801847e: 4603 mov r3, r0 + 8018480: 461a mov r2, r3 + 8018482: 4629 mov r1, r5 + 8018484: 4620 mov r0, r4 + 8018486: f000 f8db bl 8018640 + 801848a: 4603 mov r3, r0 + 801848c: 81fb strh r3, [r7, #14] + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + 801848e: 89f8 ldrh r0, [r7, #14] + 8018490: 697b ldr r3, [r7, #20] + 8018492: 33f0 adds r3, #240 ; 0xf0 + 8018494: 69ba ldr r2, [r7, #24] + 8018496: 4619 mov r1, r3 + 8018498: f000 fdbe bl 8019018 + + udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif); + 801849c: 4b13 ldr r3, [pc, #76] ; (80184ec ) + 801849e: 6818 ldr r0, [r3, #0] + 80184a0: f107 0210 add.w r2, r7, #16 + 80184a4: 687b ldr r3, [r7, #4] + 80184a6: 9300 str r3, [sp, #0] + 80184a8: 2343 movs r3, #67 ; 0x43 + 80184aa: 69b9 ldr r1, [r7, #24] + 80184ac: f7fe fbf6 bl 8016c9c + pbuf_free(p_out); + 80184b0: 69b8 ldr r0, [r7, #24] + 80184b2: f7f8 faa5 bl 8010a00 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n")); + } + } + + /* remove IP address from interface (prevents routing from selecting this interface) */ + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + 80184b6: 4b0e ldr r3, [pc, #56] ; (80184f0 ) + 80184b8: 4a0d ldr r2, [pc, #52] ; (80184f0 ) + 80184ba: 490d ldr r1, [pc, #52] ; (80184f0 ) + 80184bc: 6878 ldr r0, [r7, #4] + 80184be: f7f7 fd91 bl 800ffe4 + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + + dhcp_set_state(dhcp, DHCP_STATE_OFF); + 80184c2: 2100 movs r1, #0 + 80184c4: 69f8 ldr r0, [r7, #28] + 80184c6: f000 f815 bl 80184f4 + + if (dhcp->pcb_allocated != 0) { + 80184ca: 69fb ldr r3, [r7, #28] + 80184cc: 791b ldrb r3, [r3, #4] + 80184ce: 2b00 cmp r3, #0 + 80184d0: d008 beq.n 80184e4 + dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ + 80184d2: f7fe ff63 bl 801739c + dhcp->pcb_allocated = 0; + 80184d6: 69fb ldr r3, [r7, #28] + 80184d8: 2200 movs r2, #0 + 80184da: 711a strb r2, [r3, #4] + 80184dc: e002 b.n 80184e4 + return; + 80184de: bf00 nop + 80184e0: e000 b.n 80184e4 + return; + 80184e2: bf00 nop + } +} + 80184e4: 3720 adds r7, #32 + 80184e6: 46bd mov sp, r7 + 80184e8: bdb0 pop {r4, r5, r7, pc} + 80184ea: bf00 nop + 80184ec: 2000cfc4 .word 0x2000cfc4 + 80184f0: 08023914 .word 0x08023914 + +080184f4 : + * + * If the state changed, reset the number of tries. + */ +static void +dhcp_set_state(struct dhcp *dhcp, u8_t new_state) +{ + 80184f4: b480 push {r7} + 80184f6: b083 sub sp, #12 + 80184f8: af00 add r7, sp, #0 + 80184fa: 6078 str r0, [r7, #4] + 80184fc: 460b mov r3, r1 + 80184fe: 70fb strb r3, [r7, #3] + if (new_state != dhcp->state) { + 8018500: 687b ldr r3, [r7, #4] + 8018502: 795b ldrb r3, [r3, #5] + 8018504: 78fa ldrb r2, [r7, #3] + 8018506: 429a cmp r2, r3 + 8018508: d008 beq.n 801851c + dhcp->state = new_state; + 801850a: 687b ldr r3, [r7, #4] + 801850c: 78fa ldrb r2, [r7, #3] + 801850e: 715a strb r2, [r3, #5] + dhcp->tries = 0; + 8018510: 687b ldr r3, [r7, #4] + 8018512: 2200 movs r2, #0 + 8018514: 719a strb r2, [r3, #6] + dhcp->request_timeout = 0; + 8018516: 687b ldr r3, [r7, #4] + 8018518: 2200 movs r2, #0 + 801851a: 811a strh r2, [r3, #8] + } +} + 801851c: bf00 nop + 801851e: 370c adds r7, #12 + 8018520: 46bd mov sp, r7 + 8018522: f85d 7b04 ldr.w r7, [sp], #4 + 8018526: 4770 bx lr + +08018528 : + * DHCP message. + * + */ +static u16_t +dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len) +{ + 8018528: b580 push {r7, lr} + 801852a: b082 sub sp, #8 + 801852c: af00 add r7, sp, #0 + 801852e: 6039 str r1, [r7, #0] + 8018530: 4611 mov r1, r2 + 8018532: 461a mov r2, r3 + 8018534: 4603 mov r3, r0 + 8018536: 80fb strh r3, [r7, #6] + 8018538: 460b mov r3, r1 + 801853a: 717b strb r3, [r7, #5] + 801853c: 4613 mov r3, r2 + 801853e: 713b strb r3, [r7, #4] + LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN); + 8018540: 88fa ldrh r2, [r7, #6] + 8018542: 793b ldrb r3, [r7, #4] + 8018544: 4413 add r3, r2 + 8018546: 3302 adds r3, #2 + 8018548: 2b44 cmp r3, #68 ; 0x44 + 801854a: d906 bls.n 801855a + 801854c: 4b0d ldr r3, [pc, #52] ; (8018584 ) + 801854e: f240 529a movw r2, #1434 ; 0x59a + 8018552: 490d ldr r1, [pc, #52] ; (8018588 ) + 8018554: 480d ldr r0, [pc, #52] ; (801858c ) + 8018556: f003 fd5d bl 801c014 + options[options_out_len++] = option_type; + 801855a: 88fb ldrh r3, [r7, #6] + 801855c: 1c5a adds r2, r3, #1 + 801855e: 80fa strh r2, [r7, #6] + 8018560: 461a mov r2, r3 + 8018562: 683b ldr r3, [r7, #0] + 8018564: 4413 add r3, r2 + 8018566: 797a ldrb r2, [r7, #5] + 8018568: 701a strb r2, [r3, #0] + options[options_out_len++] = option_len; + 801856a: 88fb ldrh r3, [r7, #6] + 801856c: 1c5a adds r2, r3, #1 + 801856e: 80fa strh r2, [r7, #6] + 8018570: 461a mov r2, r3 + 8018572: 683b ldr r3, [r7, #0] + 8018574: 4413 add r3, r2 + 8018576: 793a ldrb r2, [r7, #4] + 8018578: 701a strb r2, [r3, #0] + return options_out_len; + 801857a: 88fb ldrh r3, [r7, #6] +} + 801857c: 4618 mov r0, r3 + 801857e: 3708 adds r7, #8 + 8018580: 46bd mov sp, r7 + 8018582: bd80 pop {r7, pc} + 8018584: 08020d70 .word 0x08020d70 + 8018588: 08020f04 .word 0x08020f04 + 801858c: 08020dd0 .word 0x08020dd0 + +08018590 : + * Concatenate a single byte to the outgoing DHCP message. + * + */ +static u16_t +dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value) +{ + 8018590: b580 push {r7, lr} + 8018592: b082 sub sp, #8 + 8018594: af00 add r7, sp, #0 + 8018596: 4603 mov r3, r0 + 8018598: 6039 str r1, [r7, #0] + 801859a: 80fb strh r3, [r7, #6] + 801859c: 4613 mov r3, r2 + 801859e: 717b strb r3, [r7, #5] + LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN); + 80185a0: 88fb ldrh r3, [r7, #6] + 80185a2: 2b43 cmp r3, #67 ; 0x43 + 80185a4: d906 bls.n 80185b4 + 80185a6: 4b0a ldr r3, [pc, #40] ; (80185d0 ) + 80185a8: f240 52a6 movw r2, #1446 ; 0x5a6 + 80185ac: 4909 ldr r1, [pc, #36] ; (80185d4 ) + 80185ae: 480a ldr r0, [pc, #40] ; (80185d8 ) + 80185b0: f003 fd30 bl 801c014 + options[options_out_len++] = value; + 80185b4: 88fb ldrh r3, [r7, #6] + 80185b6: 1c5a adds r2, r3, #1 + 80185b8: 80fa strh r2, [r7, #6] + 80185ba: 461a mov r2, r3 + 80185bc: 683b ldr r3, [r7, #0] + 80185be: 4413 add r3, r2 + 80185c0: 797a ldrb r2, [r7, #5] + 80185c2: 701a strb r2, [r3, #0] + return options_out_len; + 80185c4: 88fb ldrh r3, [r7, #6] +} + 80185c6: 4618 mov r0, r3 + 80185c8: 3708 adds r7, #8 + 80185ca: 46bd mov sp, r7 + 80185cc: bd80 pop {r7, pc} + 80185ce: bf00 nop + 80185d0: 08020d70 .word 0x08020d70 + 80185d4: 08020f48 .word 0x08020f48 + 80185d8: 08020dd0 .word 0x08020dd0 + +080185dc : + +static u16_t +dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value) +{ + 80185dc: b580 push {r7, lr} + 80185de: b082 sub sp, #8 + 80185e0: af00 add r7, sp, #0 + 80185e2: 4603 mov r3, r0 + 80185e4: 6039 str r1, [r7, #0] + 80185e6: 80fb strh r3, [r7, #6] + 80185e8: 4613 mov r3, r2 + 80185ea: 80bb strh r3, [r7, #4] + LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN); + 80185ec: 88fb ldrh r3, [r7, #6] + 80185ee: 3302 adds r3, #2 + 80185f0: 2b44 cmp r3, #68 ; 0x44 + 80185f2: d906 bls.n 8018602 + 80185f4: 4b0f ldr r3, [pc, #60] ; (8018634 ) + 80185f6: f240 52ae movw r2, #1454 ; 0x5ae + 80185fa: 490f ldr r1, [pc, #60] ; (8018638 ) + 80185fc: 480f ldr r0, [pc, #60] ; (801863c ) + 80185fe: f003 fd09 bl 801c014 + options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8); + 8018602: 88bb ldrh r3, [r7, #4] + 8018604: 0a1b lsrs r3, r3, #8 + 8018606: b29a uxth r2, r3 + 8018608: 88fb ldrh r3, [r7, #6] + 801860a: 1c59 adds r1, r3, #1 + 801860c: 80f9 strh r1, [r7, #6] + 801860e: 4619 mov r1, r3 + 8018610: 683b ldr r3, [r7, #0] + 8018612: 440b add r3, r1 + 8018614: b2d2 uxtb r2, r2 + 8018616: 701a strb r2, [r3, #0] + options[options_out_len++] = (u8_t) (value & 0x00ffU); + 8018618: 88fb ldrh r3, [r7, #6] + 801861a: 1c5a adds r2, r3, #1 + 801861c: 80fa strh r2, [r7, #6] + 801861e: 461a mov r2, r3 + 8018620: 683b ldr r3, [r7, #0] + 8018622: 4413 add r3, r2 + 8018624: 88ba ldrh r2, [r7, #4] + 8018626: b2d2 uxtb r2, r2 + 8018628: 701a strb r2, [r3, #0] + return options_out_len; + 801862a: 88fb ldrh r3, [r7, #6] +} + 801862c: 4618 mov r0, r3 + 801862e: 3708 adds r7, #8 + 8018630: 46bd mov sp, r7 + 8018632: bd80 pop {r7, pc} + 8018634: 08020d70 .word 0x08020d70 + 8018638: 08020f80 .word 0x08020f80 + 801863c: 08020dd0 .word 0x08020dd0 + +08018640 : + +static u16_t +dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value) +{ + 8018640: b580 push {r7, lr} + 8018642: b084 sub sp, #16 + 8018644: af00 add r7, sp, #0 + 8018646: 4603 mov r3, r0 + 8018648: 60b9 str r1, [r7, #8] + 801864a: 607a str r2, [r7, #4] + 801864c: 81fb strh r3, [r7, #14] + LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN); + 801864e: 89fb ldrh r3, [r7, #14] + 8018650: 3304 adds r3, #4 + 8018652: 2b44 cmp r3, #68 ; 0x44 + 8018654: d906 bls.n 8018664 + 8018656: 4b19 ldr r3, [pc, #100] ; (80186bc ) + 8018658: f240 52b7 movw r2, #1463 ; 0x5b7 + 801865c: 4918 ldr r1, [pc, #96] ; (80186c0 ) + 801865e: 4819 ldr r0, [pc, #100] ; (80186c4 ) + 8018660: f003 fcd8 bl 801c014 + options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24); + 8018664: 687b ldr r3, [r7, #4] + 8018666: 0e1a lsrs r2, r3, #24 + 8018668: 89fb ldrh r3, [r7, #14] + 801866a: 1c59 adds r1, r3, #1 + 801866c: 81f9 strh r1, [r7, #14] + 801866e: 4619 mov r1, r3 + 8018670: 68bb ldr r3, [r7, #8] + 8018672: 440b add r3, r1 + 8018674: b2d2 uxtb r2, r2 + 8018676: 701a strb r2, [r3, #0] + options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16); + 8018678: 687b ldr r3, [r7, #4] + 801867a: 0c1a lsrs r2, r3, #16 + 801867c: 89fb ldrh r3, [r7, #14] + 801867e: 1c59 adds r1, r3, #1 + 8018680: 81f9 strh r1, [r7, #14] + 8018682: 4619 mov r1, r3 + 8018684: 68bb ldr r3, [r7, #8] + 8018686: 440b add r3, r1 + 8018688: b2d2 uxtb r2, r2 + 801868a: 701a strb r2, [r3, #0] + options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8); + 801868c: 687b ldr r3, [r7, #4] + 801868e: 0a1a lsrs r2, r3, #8 + 8018690: 89fb ldrh r3, [r7, #14] + 8018692: 1c59 adds r1, r3, #1 + 8018694: 81f9 strh r1, [r7, #14] + 8018696: 4619 mov r1, r3 + 8018698: 68bb ldr r3, [r7, #8] + 801869a: 440b add r3, r1 + 801869c: b2d2 uxtb r2, r2 + 801869e: 701a strb r2, [r3, #0] + options[options_out_len++] = (u8_t)((value & 0x000000ffUL)); + 80186a0: 89fb ldrh r3, [r7, #14] + 80186a2: 1c5a adds r2, r3, #1 + 80186a4: 81fa strh r2, [r7, #14] + 80186a6: 461a mov r2, r3 + 80186a8: 68bb ldr r3, [r7, #8] + 80186aa: 4413 add r3, r2 + 80186ac: 687a ldr r2, [r7, #4] + 80186ae: b2d2 uxtb r2, r2 + 80186b0: 701a strb r2, [r3, #0] + return options_out_len; + 80186b2: 89fb ldrh r3, [r7, #14] +} + 80186b4: 4618 mov r0, r3 + 80186b6: 3710 adds r7, #16 + 80186b8: 46bd mov sp, r7 + 80186ba: bd80 pop {r7, pc} + 80186bc: 08020d70 .word 0x08020d70 + 80186c0: 08020fbc .word 0x08020fbc + 80186c4: 08020dd0 .word 0x08020dd0 + +080186c8 : + * use that further on. + * + */ +static err_t +dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp) +{ + 80186c8: b580 push {r7, lr} + 80186ca: b090 sub sp, #64 ; 0x40 + 80186cc: af00 add r7, sp, #0 + 80186ce: 6078 str r0, [r7, #4] + 80186d0: 6039 str r1, [r7, #0] + u16_t offset; + u16_t offset_max; + u16_t options_idx; + u16_t options_idx_max; + struct pbuf *q; + int parse_file_as_options = 0; + 80186d2: 2300 movs r3, #0 + 80186d4: 62fb str r3, [r7, #44] ; 0x2c + int parse_sname_as_options = 0; + 80186d6: 2300 movs r3, #0 + 80186d8: 62bb str r3, [r7, #40] ; 0x28 +#endif + + LWIP_UNUSED_ARG(dhcp); + + /* clear received options */ + dhcp_clear_all_options(dhcp); + 80186da: 220a movs r2, #10 + 80186dc: 2100 movs r1, #0 + 80186de: 48ba ldr r0, [pc, #744] ; (80189c8 ) + 80186e0: f003 fbfb bl 801beda + /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */ + if (p->len < DHCP_SNAME_OFS) { + 80186e4: 687b ldr r3, [r7, #4] + 80186e6: 895b ldrh r3, [r3, #10] + 80186e8: 2b2b cmp r3, #43 ; 0x2b + 80186ea: d802 bhi.n 80186f2 + return ERR_BUF; + 80186ec: f06f 0301 mvn.w r3, #1 + 80186f0: e2ea b.n 8018cc8 + } + msg_in = (struct dhcp_msg *)p->payload; + 80186f2: 687b ldr r3, [r7, #4] + 80186f4: 685b ldr r3, [r3, #4] + 80186f6: 61bb str r3, [r7, #24] +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* parse options */ + + /* start with options field */ + options_idx = DHCP_OPTIONS_OFS; + 80186f8: 23f0 movs r3, #240 ; 0xf0 + 80186fa: 86fb strh r3, [r7, #54] ; 0x36 + /* parse options to the end of the received packet */ + options_idx_max = p->tot_len; + 80186fc: 687b ldr r3, [r7, #4] + 80186fe: 891b ldrh r3, [r3, #8] + 8018700: 86bb strh r3, [r7, #52] ; 0x34 +again: + q = p; + 8018702: 687b ldr r3, [r7, #4] + 8018704: 633b str r3, [r7, #48] ; 0x30 + while ((q != NULL) && (options_idx >= q->len)) { + 8018706: e00c b.n 8018722 + options_idx = (u16_t)(options_idx - q->len); + 8018708: 6b3b ldr r3, [r7, #48] ; 0x30 + 801870a: 895b ldrh r3, [r3, #10] + 801870c: 8efa ldrh r2, [r7, #54] ; 0x36 + 801870e: 1ad3 subs r3, r2, r3 + 8018710: 86fb strh r3, [r7, #54] ; 0x36 + options_idx_max = (u16_t)(options_idx_max - q->len); + 8018712: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018714: 895b ldrh r3, [r3, #10] + 8018716: 8eba ldrh r2, [r7, #52] ; 0x34 + 8018718: 1ad3 subs r3, r2, r3 + 801871a: 86bb strh r3, [r7, #52] ; 0x34 + q = q->next; + 801871c: 6b3b ldr r3, [r7, #48] ; 0x30 + 801871e: 681b ldr r3, [r3, #0] + 8018720: 633b str r3, [r7, #48] ; 0x30 + while ((q != NULL) && (options_idx >= q->len)) { + 8018722: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018724: 2b00 cmp r3, #0 + 8018726: d004 beq.n 8018732 + 8018728: 6b3b ldr r3, [r7, #48] ; 0x30 + 801872a: 895b ldrh r3, [r3, #10] + 801872c: 8efa ldrh r2, [r7, #54] ; 0x36 + 801872e: 429a cmp r2, r3 + 8018730: d2ea bcs.n 8018708 + } + if (q == NULL) { + 8018732: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018734: 2b00 cmp r3, #0 + 8018736: d102 bne.n 801873e + return ERR_BUF; + 8018738: f06f 0301 mvn.w r3, #1 + 801873c: e2c4 b.n 8018cc8 + } + offset = options_idx; + 801873e: 8efb ldrh r3, [r7, #54] ; 0x36 + 8018740: 877b strh r3, [r7, #58] ; 0x3a + offset_max = options_idx_max; + 8018742: 8ebb ldrh r3, [r7, #52] ; 0x34 + 8018744: 873b strh r3, [r7, #56] ; 0x38 + options = (u8_t *)q->payload; + 8018746: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018748: 685b ldr r3, [r3, #4] + 801874a: 63fb str r3, [r7, #60] ; 0x3c + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) { + 801874c: e267 b.n 8018c1e + u8_t op = options[offset]; + 801874e: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018750: 6bfa ldr r2, [r7, #60] ; 0x3c + 8018752: 4413 add r3, r2 + 8018754: 781b ldrb r3, [r3, #0] + 8018756: 75fb strb r3, [r7, #23] + u8_t len; + u8_t decode_len = 0; + 8018758: 2300 movs r3, #0 + 801875a: f887 3026 strb.w r3, [r7, #38] ; 0x26 + int decode_idx = -1; + 801875e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8018762: 623b str r3, [r7, #32] + u16_t val_offset = (u16_t)(offset + 2); + 8018764: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018766: 3302 adds r3, #2 + 8018768: 83fb strh r3, [r7, #30] + if (val_offset < offset) { + 801876a: 8bfa ldrh r2, [r7, #30] + 801876c: 8f7b ldrh r3, [r7, #58] ; 0x3a + 801876e: 429a cmp r2, r3 + 8018770: d202 bcs.n 8018778 + /* overflow */ + return ERR_BUF; + 8018772: f06f 0301 mvn.w r3, #1 + 8018776: e2a7 b.n 8018cc8 + } + /* len byte might be in the next pbuf */ + if ((offset + 1) < q->len) { + 8018778: 8f7b ldrh r3, [r7, #58] ; 0x3a + 801877a: 3301 adds r3, #1 + 801877c: 6b3a ldr r2, [r7, #48] ; 0x30 + 801877e: 8952 ldrh r2, [r2, #10] + 8018780: 4293 cmp r3, r2 + 8018782: da07 bge.n 8018794 + len = options[offset + 1]; + 8018784: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018786: 3301 adds r3, #1 + 8018788: 6bfa ldr r2, [r7, #60] ; 0x3c + 801878a: 4413 add r3, r2 + 801878c: 781b ldrb r3, [r3, #0] + 801878e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8018792: e00b b.n 80187ac + } else { + len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0); + 8018794: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018796: 681b ldr r3, [r3, #0] + 8018798: 2b00 cmp r3, #0 + 801879a: d004 beq.n 80187a6 + 801879c: 6b3b ldr r3, [r7, #48] ; 0x30 + 801879e: 681b ldr r3, [r3, #0] + 80187a0: 685b ldr r3, [r3, #4] + 80187a2: 781b ldrb r3, [r3, #0] + 80187a4: e000 b.n 80187a8 + 80187a6: 2300 movs r3, #0 + 80187a8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ + decode_len = len; + 80187ac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80187b0: f887 3026 strb.w r3, [r7, #38] ; 0x26 + switch (op) { + 80187b4: 7dfb ldrb r3, [r7, #23] + 80187b6: 2b3b cmp r3, #59 ; 0x3b + 80187b8: f200 815a bhi.w 8018a70 + 80187bc: a201 add r2, pc, #4 ; (adr r2, 80187c4 ) + 80187be: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80187c2: bf00 nop + 80187c4: 080188b5 .word 0x080188b5 + 80187c8: 080188c5 .word 0x080188c5 + 80187cc: 08018a71 .word 0x08018a71 + 80187d0: 080188e7 .word 0x080188e7 + 80187d4: 08018a71 .word 0x08018a71 + 80187d8: 08018a71 .word 0x08018a71 + 80187dc: 08018913 .word 0x08018913 + 80187e0: 08018a71 .word 0x08018a71 + 80187e4: 08018a71 .word 0x08018a71 + 80187e8: 08018a71 .word 0x08018a71 + 80187ec: 08018a71 .word 0x08018a71 + 80187f0: 08018a71 .word 0x08018a71 + 80187f4: 08018a71 .word 0x08018a71 + 80187f8: 08018a71 .word 0x08018a71 + 80187fc: 08018a71 .word 0x08018a71 + 8018800: 08018a71 .word 0x08018a71 + 8018804: 08018a71 .word 0x08018a71 + 8018808: 08018a71 .word 0x08018a71 + 801880c: 08018a71 .word 0x08018a71 + 8018810: 08018a71 .word 0x08018a71 + 8018814: 08018a71 .word 0x08018a71 + 8018818: 08018a71 .word 0x08018a71 + 801881c: 08018a71 .word 0x08018a71 + 8018820: 08018a71 .word 0x08018a71 + 8018824: 08018a71 .word 0x08018a71 + 8018828: 08018a71 .word 0x08018a71 + 801882c: 08018a71 .word 0x08018a71 + 8018830: 08018a71 .word 0x08018a71 + 8018834: 08018a71 .word 0x08018a71 + 8018838: 08018a71 .word 0x08018a71 + 801883c: 08018a71 .word 0x08018a71 + 8018840: 08018a71 .word 0x08018a71 + 8018844: 08018a71 .word 0x08018a71 + 8018848: 08018a71 .word 0x08018a71 + 801884c: 08018a71 .word 0x08018a71 + 8018850: 08018a71 .word 0x08018a71 + 8018854: 08018a71 .word 0x08018a71 + 8018858: 08018a71 .word 0x08018a71 + 801885c: 08018a71 .word 0x08018a71 + 8018860: 08018a71 .word 0x08018a71 + 8018864: 08018a71 .word 0x08018a71 + 8018868: 08018a71 .word 0x08018a71 + 801886c: 08018a71 .word 0x08018a71 + 8018870: 08018a71 .word 0x08018a71 + 8018874: 08018a71 .word 0x08018a71 + 8018878: 08018a71 .word 0x08018a71 + 801887c: 08018a71 .word 0x08018a71 + 8018880: 08018a71 .word 0x08018a71 + 8018884: 08018a71 .word 0x08018a71 + 8018888: 08018a71 .word 0x08018a71 + 801888c: 08018a71 .word 0x08018a71 + 8018890: 08018969 .word 0x08018969 + 8018894: 0801898b .word 0x0801898b + 8018898: 080189e9 .word 0x080189e9 + 801889c: 08018a0b .word 0x08018a0b + 80188a0: 08018a71 .word 0x08018a71 + 80188a4: 08018a71 .word 0x08018a71 + 80188a8: 08018a71 .word 0x08018a71 + 80188ac: 08018a2d .word 0x08018a2d + 80188b0: 08018a4f .word 0x08018a4f + /* case(DHCP_OPTION_END): handled above */ + case (DHCP_OPTION_PAD): + /* special option: no len encoded */ + decode_len = len = 0; + 80188b4: 2300 movs r3, #0 + 80188b6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 80188ba: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80188be: f887 3026 strb.w r3, [r7, #38] ; 0x26 + /* will be increased below */ + break; + 80188c2: e0d9 b.n 8018a78 + case (DHCP_OPTION_SUBNET_MASK): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + 80188c4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80188c8: 2b04 cmp r3, #4 + 80188ca: d009 beq.n 80188e0 + 80188cc: 4b3f ldr r3, [pc, #252] ; (80189cc ) + 80188ce: f240 622e movw r2, #1582 ; 0x62e + 80188d2: 493f ldr r1, [pc, #252] ; (80189d0 ) + 80188d4: 483f ldr r0, [pc, #252] ; (80189d4 ) + 80188d6: f003 fb9d bl 801c014 + 80188da: f06f 0305 mvn.w r3, #5 + 80188de: e1f3 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_SUBNET_MASK; + 80188e0: 2306 movs r3, #6 + 80188e2: 623b str r3, [r7, #32] + break; + 80188e4: e0c8 b.n 8018a78 + case (DHCP_OPTION_ROUTER): + decode_len = 4; /* only copy the first given router */ + 80188e6: 2304 movs r3, #4 + 80188e8: f887 3026 strb.w r3, [r7, #38] ; 0x26 + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + 80188ec: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 80188f0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80188f4: 429a cmp r2, r3 + 80188f6: d209 bcs.n 801890c + 80188f8: 4b34 ldr r3, [pc, #208] ; (80189cc ) + 80188fa: f240 6233 movw r2, #1587 ; 0x633 + 80188fe: 4936 ldr r1, [pc, #216] ; (80189d8 ) + 8018900: 4834 ldr r0, [pc, #208] ; (80189d4 ) + 8018902: f003 fb87 bl 801c014 + 8018906: f06f 0305 mvn.w r3, #5 + 801890a: e1dd b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_ROUTER; + 801890c: 2307 movs r3, #7 + 801890e: 623b str r3, [r7, #32] + break; + 8018910: e0b2 b.n 8018a78 +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + case (DHCP_OPTION_DNS_SERVER): + /* special case: there might be more than one server */ + LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;); + 8018912: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018916: f003 0303 and.w r3, r3, #3 + 801891a: b2db uxtb r3, r3 + 801891c: 2b00 cmp r3, #0 + 801891e: d009 beq.n 8018934 + 8018920: 4b2a ldr r3, [pc, #168] ; (80189cc ) + 8018922: f240 6239 movw r2, #1593 ; 0x639 + 8018926: 492d ldr r1, [pc, #180] ; (80189dc ) + 8018928: 482a ldr r0, [pc, #168] ; (80189d4 ) + 801892a: f003 fb73 bl 801c014 + 801892e: f06f 0305 mvn.w r3, #5 + 8018932: e1c9 b.n 8018cc8 + /* limit number of DNS servers */ + decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS); + 8018934: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018938: 2b08 cmp r3, #8 + 801893a: bf28 it cs + 801893c: 2308 movcs r3, #8 + 801893e: f887 3026 strb.w r3, [r7, #38] ; 0x26 + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + 8018942: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 8018946: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 801894a: 429a cmp r2, r3 + 801894c: d209 bcs.n 8018962 + 801894e: 4b1f ldr r3, [pc, #124] ; (80189cc ) + 8018950: f240 623c movw r2, #1596 ; 0x63c + 8018954: 4920 ldr r1, [pc, #128] ; (80189d8 ) + 8018956: 481f ldr r0, [pc, #124] ; (80189d4 ) + 8018958: f003 fb5c bl 801c014 + 801895c: f06f 0305 mvn.w r3, #5 + 8018960: e1b2 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_DNS_SERVER; + 8018962: 2308 movs r3, #8 + 8018964: 623b str r3, [r7, #32] + break; + 8018966: e087 b.n 8018a78 +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ + case (DHCP_OPTION_LEASE_TIME): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + 8018968: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 801896c: 2b04 cmp r3, #4 + 801896e: d009 beq.n 8018984 + 8018970: 4b16 ldr r3, [pc, #88] ; (80189cc ) + 8018972: f240 6241 movw r2, #1601 ; 0x641 + 8018976: 4916 ldr r1, [pc, #88] ; (80189d0 ) + 8018978: 4816 ldr r0, [pc, #88] ; (80189d4 ) + 801897a: f003 fb4b bl 801c014 + 801897e: f06f 0305 mvn.w r3, #5 + 8018982: e1a1 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_LEASE_TIME; + 8018984: 2303 movs r3, #3 + 8018986: 623b str r3, [r7, #32] + break; + 8018988: e076 b.n 8018a78 + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_NTP_SERVER; + break; +#endif /* LWIP_DHCP_GET_NTP_SRV*/ + case (DHCP_OPTION_OVERLOAD): + LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); + 801898a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 801898e: 2b01 cmp r3, #1 + 8018990: d009 beq.n 80189a6 + 8018992: 4b0e ldr r3, [pc, #56] ; (80189cc ) + 8018994: f240 624f movw r2, #1615 ; 0x64f + 8018998: 4911 ldr r1, [pc, #68] ; (80189e0 ) + 801899a: 480e ldr r0, [pc, #56] ; (80189d4 ) + 801899c: f003 fb3a bl 801c014 + 80189a0: f06f 0305 mvn.w r3, #5 + 80189a4: e190 b.n 8018cc8 + /* decode overload only in options, not in file/sname: invalid packet */ + LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;); + 80189a6: 8efb ldrh r3, [r7, #54] ; 0x36 + 80189a8: 2bf0 cmp r3, #240 ; 0xf0 + 80189aa: d009 beq.n 80189c0 + 80189ac: 4b07 ldr r3, [pc, #28] ; (80189cc ) + 80189ae: f240 6251 movw r2, #1617 ; 0x651 + 80189b2: 490c ldr r1, [pc, #48] ; (80189e4 ) + 80189b4: 4807 ldr r0, [pc, #28] ; (80189d4 ) + 80189b6: f003 fb2d bl 801c014 + 80189ba: f06f 0305 mvn.w r3, #5 + 80189be: e183 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_OVERLOAD; + 80189c0: 2300 movs r3, #0 + 80189c2: 623b str r3, [r7, #32] + break; + 80189c4: e058 b.n 8018a78 + 80189c6: bf00 nop + 80189c8: 2000cfb8 .word 0x2000cfb8 + 80189cc: 08020d70 .word 0x08020d70 + 80189d0: 08020ff8 .word 0x08020ff8 + 80189d4: 08020dd0 .word 0x08020dd0 + 80189d8: 08021004 .word 0x08021004 + 80189dc: 08021018 .word 0x08021018 + 80189e0: 08021028 .word 0x08021028 + 80189e4: 08021034 .word 0x08021034 + case (DHCP_OPTION_MESSAGE_TYPE): + LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); + 80189e8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80189ec: 2b01 cmp r3, #1 + 80189ee: d009 beq.n 8018a04 + 80189f0: 4b9d ldr r3, [pc, #628] ; (8018c68 ) + 80189f2: f240 6255 movw r2, #1621 ; 0x655 + 80189f6: 499d ldr r1, [pc, #628] ; (8018c6c ) + 80189f8: 489d ldr r0, [pc, #628] ; (8018c70 ) + 80189fa: f003 fb0b bl 801c014 + 80189fe: f06f 0305 mvn.w r3, #5 + 8018a02: e161 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_MSG_TYPE; + 8018a04: 2301 movs r3, #1 + 8018a06: 623b str r3, [r7, #32] + break; + 8018a08: e036 b.n 8018a78 + case (DHCP_OPTION_SERVER_ID): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + 8018a0a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018a0e: 2b04 cmp r3, #4 + 8018a10: d009 beq.n 8018a26 + 8018a12: 4b95 ldr r3, [pc, #596] ; (8018c68 ) + 8018a14: f240 6259 movw r2, #1625 ; 0x659 + 8018a18: 4996 ldr r1, [pc, #600] ; (8018c74 ) + 8018a1a: 4895 ldr r0, [pc, #596] ; (8018c70 ) + 8018a1c: f003 fafa bl 801c014 + 8018a20: f06f 0305 mvn.w r3, #5 + 8018a24: e150 b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_SERVER_ID; + 8018a26: 2302 movs r3, #2 + 8018a28: 623b str r3, [r7, #32] + break; + 8018a2a: e025 b.n 8018a78 + case (DHCP_OPTION_T1): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + 8018a2c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018a30: 2b04 cmp r3, #4 + 8018a32: d009 beq.n 8018a48 + 8018a34: 4b8c ldr r3, [pc, #560] ; (8018c68 ) + 8018a36: f240 625d movw r2, #1629 ; 0x65d + 8018a3a: 498e ldr r1, [pc, #568] ; (8018c74 ) + 8018a3c: 488c ldr r0, [pc, #560] ; (8018c70 ) + 8018a3e: f003 fae9 bl 801c014 + 8018a42: f06f 0305 mvn.w r3, #5 + 8018a46: e13f b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_T1; + 8018a48: 2304 movs r3, #4 + 8018a4a: 623b str r3, [r7, #32] + break; + 8018a4c: e014 b.n 8018a78 + case (DHCP_OPTION_T2): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + 8018a4e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018a52: 2b04 cmp r3, #4 + 8018a54: d009 beq.n 8018a6a + 8018a56: 4b84 ldr r3, [pc, #528] ; (8018c68 ) + 8018a58: f240 6261 movw r2, #1633 ; 0x661 + 8018a5c: 4985 ldr r1, [pc, #532] ; (8018c74 ) + 8018a5e: 4884 ldr r0, [pc, #528] ; (8018c70 ) + 8018a60: f003 fad8 bl 801c014 + 8018a64: f06f 0305 mvn.w r3, #5 + 8018a68: e12e b.n 8018cc8 + decode_idx = DHCP_OPTION_IDX_T2; + 8018a6a: 2305 movs r3, #5 + 8018a6c: 623b str r3, [r7, #32] + break; + 8018a6e: e003 b.n 8018a78 + default: + decode_len = 0; + 8018a70: 2300 movs r3, #0 + 8018a72: f887 3026 strb.w r3, [r7, #38] ; 0x26 + LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op)); + LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in, + dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0, + op, len, q, val_offset); + break; + 8018a76: bf00 nop + } + if (op == DHCP_OPTION_PAD) { + 8018a78: 7dfb ldrb r3, [r7, #23] + 8018a7a: 2b00 cmp r3, #0 + 8018a7c: d103 bne.n 8018a86 + offset++; + 8018a7e: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018a80: 3301 adds r3, #1 + 8018a82: 877b strh r3, [r7, #58] ; 0x3a + 8018a84: e0a1 b.n 8018bca + } else { + if (offset + len + 2 > 0xFFFF) { + 8018a86: 8f7a ldrh r2, [r7, #58] ; 0x3a + 8018a88: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018a8c: 4413 add r3, r2 + 8018a8e: f64f 72fd movw r2, #65533 ; 0xfffd + 8018a92: 4293 cmp r3, r2 + 8018a94: dd02 ble.n 8018a9c + /* overflow */ + return ERR_BUF; + 8018a96: f06f 0301 mvn.w r3, #1 + 8018a9a: e115 b.n 8018cc8 + } + offset = (u16_t)(offset + len + 2); + 8018a9c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018aa0: b29a uxth r2, r3 + 8018aa2: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018aa4: 4413 add r3, r2 + 8018aa6: b29b uxth r3, r3 + 8018aa8: 3302 adds r3, #2 + 8018aaa: 877b strh r3, [r7, #58] ; 0x3a + if (decode_len > 0) { + 8018aac: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018ab0: 2b00 cmp r3, #0 + 8018ab2: f000 808a beq.w 8018bca + u32_t value = 0; + 8018ab6: 2300 movs r3, #0 + 8018ab8: 60bb str r3, [r7, #8] + u16_t copy_len; +decode_next: + LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX); + 8018aba: 6a3b ldr r3, [r7, #32] + 8018abc: 2b00 cmp r3, #0 + 8018abe: db02 blt.n 8018ac6 + 8018ac0: 6a3b ldr r3, [r7, #32] + 8018ac2: 2b09 cmp r3, #9 + 8018ac4: dd06 ble.n 8018ad4 + 8018ac6: 4b68 ldr r3, [pc, #416] ; (8018c68 ) + 8018ac8: f44f 62cf mov.w r2, #1656 ; 0x678 + 8018acc: 496a ldr r1, [pc, #424] ; (8018c78 ) + 8018ace: 4868 ldr r0, [pc, #416] ; (8018c70 ) + 8018ad0: f003 faa0 bl 801c014 + if (!dhcp_option_given(dhcp, decode_idx)) { + 8018ad4: 4a69 ldr r2, [pc, #420] ; (8018c7c ) + 8018ad6: 6a3b ldr r3, [r7, #32] + 8018ad8: 4413 add r3, r2 + 8018ada: 781b ldrb r3, [r3, #0] + 8018adc: 2b00 cmp r3, #0 + 8018ade: d174 bne.n 8018bca + copy_len = LWIP_MIN(decode_len, 4); + 8018ae0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018ae4: 2b04 cmp r3, #4 + 8018ae6: bf28 it cs + 8018ae8: 2304 movcs r3, #4 + 8018aea: b2db uxtb r3, r3 + 8018aec: 82bb strh r3, [r7, #20] + if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) { + 8018aee: 8bfb ldrh r3, [r7, #30] + 8018af0: 8aba ldrh r2, [r7, #20] + 8018af2: f107 0108 add.w r1, r7, #8 + 8018af6: 6b38 ldr r0, [r7, #48] ; 0x30 + 8018af8: f7f8 f988 bl 8010e0c + 8018afc: 4603 mov r3, r0 + 8018afe: 461a mov r2, r3 + 8018b00: 8abb ldrh r3, [r7, #20] + 8018b02: 4293 cmp r3, r2 + 8018b04: d002 beq.n 8018b0c + return ERR_BUF; + 8018b06: f06f 0301 mvn.w r3, #1 + 8018b0a: e0dd b.n 8018cc8 + } + if (decode_len > 4) { + 8018b0c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018b10: 2b04 cmp r3, #4 + 8018b12: d933 bls.n 8018b7c + /* decode more than one u32_t */ + u16_t next_val_offset; + LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;); + 8018b14: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018b18: f003 0303 and.w r3, r3, #3 + 8018b1c: b2db uxtb r3, r3 + 8018b1e: 2b00 cmp r3, #0 + 8018b20: d009 beq.n 8018b36 + 8018b22: 4b51 ldr r3, [pc, #324] ; (8018c68 ) + 8018b24: f240 6281 movw r2, #1665 ; 0x681 + 8018b28: 4955 ldr r1, [pc, #340] ; (8018c80 ) + 8018b2a: 4851 ldr r0, [pc, #324] ; (8018c70 ) + 8018b2c: f003 fa72 bl 801c014 + 8018b30: f06f 0305 mvn.w r3, #5 + 8018b34: e0c8 b.n 8018cc8 + dhcp_got_option(dhcp, decode_idx); + 8018b36: 4a51 ldr r2, [pc, #324] ; (8018c7c ) + 8018b38: 6a3b ldr r3, [r7, #32] + 8018b3a: 4413 add r3, r2 + 8018b3c: 2201 movs r2, #1 + 8018b3e: 701a strb r2, [r3, #0] + dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value)); + 8018b40: 68bb ldr r3, [r7, #8] + 8018b42: 4618 mov r0, r3 + 8018b44: f7f5 fb89 bl 800e25a + 8018b48: 4602 mov r2, r0 + 8018b4a: 494e ldr r1, [pc, #312] ; (8018c84 ) + 8018b4c: 6a3b ldr r3, [r7, #32] + 8018b4e: f841 2023 str.w r2, [r1, r3, lsl #2] + decode_len = (u8_t)(decode_len - 4); + 8018b52: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018b56: 3b04 subs r3, #4 + 8018b58: f887 3026 strb.w r3, [r7, #38] ; 0x26 + next_val_offset = (u16_t)(val_offset + 4); + 8018b5c: 8bfb ldrh r3, [r7, #30] + 8018b5e: 3304 adds r3, #4 + 8018b60: 827b strh r3, [r7, #18] + if (next_val_offset < val_offset) { + 8018b62: 8a7a ldrh r2, [r7, #18] + 8018b64: 8bfb ldrh r3, [r7, #30] + 8018b66: 429a cmp r2, r3 + 8018b68: d202 bcs.n 8018b70 + /* overflow */ + return ERR_BUF; + 8018b6a: f06f 0301 mvn.w r3, #1 + 8018b6e: e0ab b.n 8018cc8 + } + val_offset = next_val_offset; + 8018b70: 8a7b ldrh r3, [r7, #18] + 8018b72: 83fb strh r3, [r7, #30] + decode_idx++; + 8018b74: 6a3b ldr r3, [r7, #32] + 8018b76: 3301 adds r3, #1 + 8018b78: 623b str r3, [r7, #32] + goto decode_next; + 8018b7a: e79e b.n 8018aba + } else if (decode_len == 4) { + 8018b7c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018b80: 2b04 cmp r3, #4 + 8018b82: d106 bne.n 8018b92 + value = lwip_ntohl(value); + 8018b84: 68bb ldr r3, [r7, #8] + 8018b86: 4618 mov r0, r3 + 8018b88: f7f5 fb67 bl 800e25a + 8018b8c: 4603 mov r3, r0 + 8018b8e: 60bb str r3, [r7, #8] + 8018b90: e011 b.n 8018bb6 + } else { + LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;); + 8018b92: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8018b96: 2b01 cmp r3, #1 + 8018b98: d009 beq.n 8018bae + 8018b9a: 4b33 ldr r3, [pc, #204] ; (8018c68 ) + 8018b9c: f44f 62d2 mov.w r2, #1680 ; 0x690 + 8018ba0: 4939 ldr r1, [pc, #228] ; (8018c88 ) + 8018ba2: 4833 ldr r0, [pc, #204] ; (8018c70 ) + 8018ba4: f003 fa36 bl 801c014 + 8018ba8: f06f 0305 mvn.w r3, #5 + 8018bac: e08c b.n 8018cc8 + value = ((u8_t *)&value)[0]; + 8018bae: f107 0308 add.w r3, r7, #8 + 8018bb2: 781b ldrb r3, [r3, #0] + 8018bb4: 60bb str r3, [r7, #8] + } + dhcp_got_option(dhcp, decode_idx); + 8018bb6: 4a31 ldr r2, [pc, #196] ; (8018c7c ) + 8018bb8: 6a3b ldr r3, [r7, #32] + 8018bba: 4413 add r3, r2 + 8018bbc: 2201 movs r2, #1 + 8018bbe: 701a strb r2, [r3, #0] + dhcp_set_option_value(dhcp, decode_idx, value); + 8018bc0: 68ba ldr r2, [r7, #8] + 8018bc2: 4930 ldr r1, [pc, #192] ; (8018c84 ) + 8018bc4: 6a3b ldr r3, [r7, #32] + 8018bc6: f841 2023 str.w r2, [r1, r3, lsl #2] + } + } + } + if (offset >= q->len) { + 8018bca: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018bcc: 895b ldrh r3, [r3, #10] + 8018bce: 8f7a ldrh r2, [r7, #58] ; 0x3a + 8018bd0: 429a cmp r2, r3 + 8018bd2: d324 bcc.n 8018c1e + offset = (u16_t)(offset - q->len); + 8018bd4: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018bd6: 895b ldrh r3, [r3, #10] + 8018bd8: 8f7a ldrh r2, [r7, #58] ; 0x3a + 8018bda: 1ad3 subs r3, r2, r3 + 8018bdc: 877b strh r3, [r7, #58] ; 0x3a + offset_max = (u16_t)(offset_max - q->len); + 8018bde: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018be0: 895b ldrh r3, [r3, #10] + 8018be2: 8f3a ldrh r2, [r7, #56] ; 0x38 + 8018be4: 1ad3 subs r3, r2, r3 + 8018be6: 873b strh r3, [r7, #56] ; 0x38 + if (offset < offset_max) { + 8018be8: 8f7a ldrh r2, [r7, #58] ; 0x3a + 8018bea: 8f3b ldrh r3, [r7, #56] ; 0x38 + 8018bec: 429a cmp r2, r3 + 8018bee: d213 bcs.n 8018c18 + q = q->next; + 8018bf0: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018bf2: 681b ldr r3, [r3, #0] + 8018bf4: 633b str r3, [r7, #48] ; 0x30 + LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;); + 8018bf6: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018bf8: 2b00 cmp r3, #0 + 8018bfa: d109 bne.n 8018c10 + 8018bfc: 4b1a ldr r3, [pc, #104] ; (8018c68 ) + 8018bfe: f240 629d movw r2, #1693 ; 0x69d + 8018c02: 4922 ldr r1, [pc, #136] ; (8018c8c ) + 8018c04: 481a ldr r0, [pc, #104] ; (8018c70 ) + 8018c06: f003 fa05 bl 801c014 + 8018c0a: f06f 0305 mvn.w r3, #5 + 8018c0e: e05b b.n 8018cc8 + options = (u8_t *)q->payload; + 8018c10: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018c12: 685b ldr r3, [r3, #4] + 8018c14: 63fb str r3, [r7, #60] ; 0x3c + 8018c16: e002 b.n 8018c1e + } else { + /* We've run out of bytes, probably no end marker. Don't proceed. */ + return ERR_BUF; + 8018c18: f06f 0301 mvn.w r3, #1 + 8018c1c: e054 b.n 8018cc8 + while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) { + 8018c1e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8018c20: 2b00 cmp r3, #0 + 8018c22: d00a beq.n 8018c3a + 8018c24: 8f7a ldrh r2, [r7, #58] ; 0x3a + 8018c26: 8f3b ldrh r3, [r7, #56] ; 0x38 + 8018c28: 429a cmp r2, r3 + 8018c2a: d206 bcs.n 8018c3a + 8018c2c: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8018c2e: 6bfa ldr r2, [r7, #60] ; 0x3c + 8018c30: 4413 add r3, r2 + 8018c32: 781b ldrb r3, [r3, #0] + 8018c34: 2bff cmp r3, #255 ; 0xff + 8018c36: f47f ad8a bne.w 801874e + } + } + } + /* is this an overloaded message? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) { + 8018c3a: 4b10 ldr r3, [pc, #64] ; (8018c7c ) + 8018c3c: 781b ldrb r3, [r3, #0] + 8018c3e: 2b00 cmp r3, #0 + 8018c40: d02d beq.n 8018c9e + u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD); + 8018c42: 4b10 ldr r3, [pc, #64] ; (8018c84 ) + 8018c44: 681b ldr r3, [r3, #0] + 8018c46: 60fb str r3, [r7, #12] + dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD); + 8018c48: 4b0c ldr r3, [pc, #48] ; (8018c7c ) + 8018c4a: 2200 movs r2, #0 + 8018c4c: 701a strb r2, [r3, #0] + if (overload == DHCP_OVERLOAD_FILE) { + 8018c4e: 68fb ldr r3, [r7, #12] + 8018c50: 2b01 cmp r3, #1 + 8018c52: d102 bne.n 8018c5a + parse_file_as_options = 1; + 8018c54: 2301 movs r3, #1 + 8018c56: 62fb str r3, [r7, #44] ; 0x2c + 8018c58: e021 b.n 8018c9e + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME) { + 8018c5a: 68fb ldr r3, [r7, #12] + 8018c5c: 2b02 cmp r3, #2 + 8018c5e: d117 bne.n 8018c90 + parse_sname_as_options = 1; + 8018c60: 2301 movs r3, #1 + 8018c62: 62bb str r3, [r7, #40] ; 0x28 + 8018c64: e01b b.n 8018c9e + 8018c66: bf00 nop + 8018c68: 08020d70 .word 0x08020d70 + 8018c6c: 08021028 .word 0x08021028 + 8018c70: 08020dd0 .word 0x08020dd0 + 8018c74: 08020ff8 .word 0x08020ff8 + 8018c78: 0802104c .word 0x0802104c + 8018c7c: 2000cfb8 .word 0x2000cfb8 + 8018c80: 08021060 .word 0x08021060 + 8018c84: 2000cf90 .word 0x2000cf90 + 8018c88: 08021078 .word 0x08021078 + 8018c8c: 0802108c .word 0x0802108c + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME_FILE) { + 8018c90: 68fb ldr r3, [r7, #12] + 8018c92: 2b03 cmp r3, #3 + 8018c94: d103 bne.n 8018c9e + parse_sname_as_options = 1; + 8018c96: 2301 movs r3, #1 + 8018c98: 62bb str r3, [r7, #40] ; 0x28 + parse_file_as_options = 1; + 8018c9a: 2301 movs r3, #1 + 8018c9c: 62fb str r3, [r7, #44] ; 0x2c + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload)); + } + } + if (parse_file_as_options) { + 8018c9e: 6afb ldr r3, [r7, #44] ; 0x2c + 8018ca0: 2b00 cmp r3, #0 + 8018ca2: d006 beq.n 8018cb2 + /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */ + parse_file_as_options = 0; + 8018ca4: 2300 movs r3, #0 + 8018ca6: 62fb str r3, [r7, #44] ; 0x2c + options_idx = DHCP_FILE_OFS; + 8018ca8: 236c movs r3, #108 ; 0x6c + 8018caa: 86fb strh r3, [r7, #54] ; 0x36 + options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN; + 8018cac: 23ec movs r3, #236 ; 0xec + 8018cae: 86bb strh r3, [r7, #52] ; 0x34 +#if LWIP_DHCP_BOOTP_FILE + file_overloaded = 1; +#endif + goto again; + 8018cb0: e527 b.n 8018702 + } else if (parse_sname_as_options) { + 8018cb2: 6abb ldr r3, [r7, #40] ; 0x28 + 8018cb4: 2b00 cmp r3, #0 + 8018cb6: d006 beq.n 8018cc6 + parse_sname_as_options = 0; + 8018cb8: 2300 movs r3, #0 + 8018cba: 62bb str r3, [r7, #40] ; 0x28 + options_idx = DHCP_SNAME_OFS; + 8018cbc: 232c movs r3, #44 ; 0x2c + 8018cbe: 86fb strh r3, [r7, #54] ; 0x36 + options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN; + 8018cc0: 236c movs r3, #108 ; 0x6c + 8018cc2: 86bb strh r3, [r7, #52] ; 0x34 + goto again; + 8018cc4: e51d b.n 8018702 + } + /* make sure the string is really NULL-terminated */ + dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0; + } +#endif /* LWIP_DHCP_BOOTP_FILE */ + return ERR_OK; + 8018cc6: 2300 movs r3, #0 +} + 8018cc8: 4618 mov r0, r3 + 8018cca: 3740 adds r7, #64 ; 0x40 + 8018ccc: 46bd mov sp, r7 + 8018cce: bd80 pop {r7, pc} + +08018cd0 : +/** + * If an incoming DHCP message is in response to us, then trigger the state machine + */ +static void +dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + 8018cd0: b580 push {r7, lr} + 8018cd2: b08a sub sp, #40 ; 0x28 + 8018cd4: af00 add r7, sp, #0 + 8018cd6: 60f8 str r0, [r7, #12] + 8018cd8: 60b9 str r1, [r7, #8] + 8018cda: 607a str r2, [r7, #4] + 8018cdc: 603b str r3, [r7, #0] + struct netif *netif = ip_current_input_netif(); + 8018cde: 4b60 ldr r3, [pc, #384] ; (8018e60 ) + 8018ce0: 685b ldr r3, [r3, #4] + 8018ce2: 623b str r3, [r7, #32] + struct dhcp *dhcp = netif_dhcp_data(netif); + 8018ce4: 6a3b ldr r3, [r7, #32] + 8018ce6: 6a5b ldr r3, [r3, #36] ; 0x24 + 8018ce8: 61fb str r3, [r7, #28] + struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; + 8018cea: 687b ldr r3, [r7, #4] + 8018cec: 685b ldr r3, [r3, #4] + 8018cee: 61bb str r3, [r7, #24] + struct dhcp_msg *msg_in; + + LWIP_UNUSED_ARG(arg); + + /* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */ + if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) { + 8018cf0: 69fb ldr r3, [r7, #28] + 8018cf2: 2b00 cmp r3, #0 + 8018cf4: f000 809d beq.w 8018e32 + 8018cf8: 69fb ldr r3, [r7, #28] + 8018cfa: 791b ldrb r3, [r3, #4] + 8018cfc: 2b00 cmp r3, #0 + 8018cfe: f000 8098 beq.w 8018e32 + /* prevent warnings about unused arguments */ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + + if (p->len < DHCP_MIN_REPLY_LEN) { + 8018d02: 687b ldr r3, [r7, #4] + 8018d04: 895b ldrh r3, [r3, #10] + 8018d06: 2b2b cmp r3, #43 ; 0x2b + 8018d08: f240 8095 bls.w 8018e36 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n")); + goto free_pbuf_and_return; + } + + if (reply_msg->op != DHCP_BOOTREPLY) { + 8018d0c: 69bb ldr r3, [r7, #24] + 8018d0e: 781b ldrb r3, [r3, #0] + 8018d10: 2b02 cmp r3, #2 + 8018d12: f040 8092 bne.w 8018e3a + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); + goto free_pbuf_and_return; + } + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + 8018d16: 2300 movs r3, #0 + 8018d18: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8018d1c: e012 b.n 8018d44 + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { + 8018d1e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018d22: 6a3a ldr r2, [r7, #32] + 8018d24: 4413 add r3, r2 + 8018d26: f893 202a ldrb.w r2, [r3, #42] ; 0x2a + 8018d2a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018d2e: 69b9 ldr r1, [r7, #24] + 8018d30: 440b add r3, r1 + 8018d32: 7f1b ldrb r3, [r3, #28] + 8018d34: 429a cmp r2, r3 + 8018d36: f040 8082 bne.w 8018e3e + for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + 8018d3a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018d3e: 3301 adds r3, #1 + 8018d40: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8018d44: 6a3b ldr r3, [r7, #32] + 8018d46: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8018d4a: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 8018d4e: 429a cmp r2, r3 + 8018d50: d203 bcs.n 8018d5a + 8018d52: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8018d56: 2b05 cmp r3, #5 + 8018d58: d9e1 bls.n 8018d1e + (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); + goto free_pbuf_and_return; + } + } + /* match transaction ID against what we expected */ + if (lwip_ntohl(reply_msg->xid) != dhcp->xid) { + 8018d5a: 69bb ldr r3, [r7, #24] + 8018d5c: 685b ldr r3, [r3, #4] + 8018d5e: 4618 mov r0, r3 + 8018d60: f7f5 fa7b bl 800e25a + 8018d64: 4602 mov r2, r0 + 8018d66: 69fb ldr r3, [r7, #28] + 8018d68: 681b ldr r3, [r3, #0] + 8018d6a: 429a cmp r2, r3 + 8018d6c: d169 bne.n 8018e42 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid)); + goto free_pbuf_and_return; + } + /* option fields could be unfold? */ + if (dhcp_parse_reply(p, dhcp) != ERR_OK) { + 8018d6e: 69f9 ldr r1, [r7, #28] + 8018d70: 6878 ldr r0, [r7, #4] + 8018d72: f7ff fca9 bl 80186c8 + 8018d76: 4603 mov r3, r0 + 8018d78: 2b00 cmp r3, #0 + 8018d7a: d164 bne.n 8018e46 + goto free_pbuf_and_return; + } + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); + /* obtain pointer to DHCP message type */ + if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) { + 8018d7c: 4b39 ldr r3, [pc, #228] ; (8018e64 ) + 8018d7e: 785b ldrb r3, [r3, #1] + 8018d80: 2b00 cmp r3, #0 + 8018d82: d062 beq.n 8018e4a + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); + goto free_pbuf_and_return; + } + + msg_in = (struct dhcp_msg *)p->payload; + 8018d84: 687b ldr r3, [r7, #4] + 8018d86: 685b ldr r3, [r3, #4] + 8018d88: 617b str r3, [r7, #20] + /* read DHCP message type */ + msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE); + 8018d8a: 4b37 ldr r3, [pc, #220] ; (8018e68 ) + 8018d8c: 685b ldr r3, [r3, #4] + 8018d8e: 74fb strb r3, [r7, #19] + /* message type is DHCP ACK? */ + if (msg_type == DHCP_ACK) { + 8018d90: 7cfb ldrb r3, [r7, #19] + 8018d92: 2b05 cmp r3, #5 + 8018d94: d12a bne.n 8018dec + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n")); + /* in requesting state? */ + if (dhcp->state == DHCP_STATE_REQUESTING) { + 8018d96: 69fb ldr r3, [r7, #28] + 8018d98: 795b ldrb r3, [r3, #5] + 8018d9a: 2b01 cmp r3, #1 + 8018d9c: d112 bne.n 8018dc4 + dhcp_handle_ack(netif, msg_in); + 8018d9e: 6979 ldr r1, [r7, #20] + 8018da0: 6a38 ldr r0, [r7, #32] + 8018da2: f7fe fdc7 bl 8017934 +#if DHCP_DOES_ARP_CHECK + if ((netif->flags & NETIF_FLAG_ETHARP) != 0) { + 8018da6: 6a3b ldr r3, [r7, #32] + 8018da8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8018dac: f003 0308 and.w r3, r3, #8 + 8018db0: 2b00 cmp r3, #0 + 8018db2: d003 beq.n 8018dbc + /* check if the acknowledged lease address is already in use */ + dhcp_check(netif); + 8018db4: 6a38 ldr r0, [r7, #32] + 8018db6: f7fe fb35 bl 8017424 + 8018dba: e049 b.n 8018e50 + } else { + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); + 8018dbc: 6a38 ldr r0, [r7, #32] + 8018dbe: f7ff f837 bl 8017e30 + 8018dc2: e045 b.n 8018e50 + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); +#endif + } + /* already bound to the given lease address? */ + else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) || + 8018dc4: 69fb ldr r3, [r7, #28] + 8018dc6: 795b ldrb r3, [r3, #5] + 8018dc8: 2b03 cmp r3, #3 + 8018dca: d007 beq.n 8018ddc + 8018dcc: 69fb ldr r3, [r7, #28] + 8018dce: 795b ldrb r3, [r3, #5] + 8018dd0: 2b04 cmp r3, #4 + 8018dd2: d003 beq.n 8018ddc + (dhcp->state == DHCP_STATE_RENEWING)) { + 8018dd4: 69fb ldr r3, [r7, #28] + 8018dd6: 795b ldrb r3, [r3, #5] + else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) || + 8018dd8: 2b05 cmp r3, #5 + 8018dda: d139 bne.n 8018e50 + dhcp_handle_ack(netif, msg_in); + 8018ddc: 6979 ldr r1, [r7, #20] + 8018dde: 6a38 ldr r0, [r7, #32] + 8018de0: f7fe fda8 bl 8017934 + dhcp_bind(netif); + 8018de4: 6a38 ldr r0, [r7, #32] + 8018de6: f7ff f823 bl 8017e30 + 8018dea: e031 b.n 8018e50 + } + } + /* received a DHCP_NAK in appropriate state? */ + else if ((msg_type == DHCP_NAK) && + 8018dec: 7cfb ldrb r3, [r7, #19] + 8018dee: 2b06 cmp r3, #6 + 8018df0: d113 bne.n 8018e1a + ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) || + 8018df2: 69fb ldr r3, [r7, #28] + 8018df4: 795b ldrb r3, [r3, #5] + else if ((msg_type == DHCP_NAK) && + 8018df6: 2b03 cmp r3, #3 + 8018df8: d00b beq.n 8018e12 + ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) || + 8018dfa: 69fb ldr r3, [r7, #28] + 8018dfc: 795b ldrb r3, [r3, #5] + 8018dfe: 2b01 cmp r3, #1 + 8018e00: d007 beq.n 8018e12 + (dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) { + 8018e02: 69fb ldr r3, [r7, #28] + 8018e04: 795b ldrb r3, [r3, #5] + ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) || + 8018e06: 2b04 cmp r3, #4 + 8018e08: d003 beq.n 8018e12 + (dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) { + 8018e0a: 69fb ldr r3, [r7, #28] + 8018e0c: 795b ldrb r3, [r3, #5] + 8018e0e: 2b05 cmp r3, #5 + 8018e10: d103 bne.n 8018e1a + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n")); + dhcp_handle_nak(netif); + 8018e12: 6a38 ldr r0, [r7, #32] + 8018e14: f7fe faec bl 80173f0 + 8018e18: e01a b.n 8018e50 + } + /* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */ + else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) { + 8018e1a: 7cfb ldrb r3, [r7, #19] + 8018e1c: 2b02 cmp r3, #2 + 8018e1e: d116 bne.n 8018e4e + 8018e20: 69fb ldr r3, [r7, #28] + 8018e22: 795b ldrb r3, [r3, #5] + 8018e24: 2b06 cmp r3, #6 + 8018e26: d112 bne.n 8018e4e + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n")); + /* remember offered lease */ + dhcp_handle_offer(netif, msg_in); + 8018e28: 6979 ldr r1, [r7, #20] + 8018e2a: 6a38 ldr r0, [r7, #32] + 8018e2c: f7fe fb2e bl 801748c + 8018e30: e00e b.n 8018e50 + goto free_pbuf_and_return; + 8018e32: bf00 nop + 8018e34: e00c b.n 8018e50 + goto free_pbuf_and_return; + 8018e36: bf00 nop + 8018e38: e00a b.n 8018e50 + goto free_pbuf_and_return; + 8018e3a: bf00 nop + 8018e3c: e008 b.n 8018e50 + goto free_pbuf_and_return; + 8018e3e: bf00 nop + 8018e40: e006 b.n 8018e50 + goto free_pbuf_and_return; + 8018e42: bf00 nop + 8018e44: e004 b.n 8018e50 + goto free_pbuf_and_return; + 8018e46: bf00 nop + 8018e48: e002 b.n 8018e50 + goto free_pbuf_and_return; + 8018e4a: bf00 nop + 8018e4c: e000 b.n 8018e50 + } + +free_pbuf_and_return: + 8018e4e: bf00 nop + pbuf_free(p); + 8018e50: 6878 ldr r0, [r7, #4] + 8018e52: f7f7 fdd5 bl 8010a00 +} + 8018e56: bf00 nop + 8018e58: 3728 adds r7, #40 ; 0x28 + 8018e5a: 46bd mov sp, r7 + 8018e5c: bd80 pop {r7, pc} + 8018e5e: bf00 nop + 8018e60: 20009670 .word 0x20009670 + 8018e64: 2000cfb8 .word 0x2000cfb8 + 8018e68: 2000cf90 .word 0x2000cf90 + +08018e6c : + * @param dhcp dhcp control struct + * @param message_type message type of the request + */ +static struct pbuf * +dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len) +{ + 8018e6c: b580 push {r7, lr} + 8018e6e: b088 sub sp, #32 + 8018e70: af00 add r7, sp, #0 + 8018e72: 60f8 str r0, [r7, #12] + 8018e74: 60b9 str r1, [r7, #8] + 8018e76: 603b str r3, [r7, #0] + 8018e78: 4613 mov r3, r2 + 8018e7a: 71fb strb r3, [r7, #7] + if (!xid_initialised) { + xid = DHCP_GLOBAL_XID; + xid_initialised = !xid_initialised; + } +#endif + LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;); + 8018e7c: 68fb ldr r3, [r7, #12] + 8018e7e: 2b00 cmp r3, #0 + 8018e80: d108 bne.n 8018e94 + 8018e82: 4b5f ldr r3, [pc, #380] ; (8019000 ) + 8018e84: f240 7269 movw r2, #1897 ; 0x769 + 8018e88: 495e ldr r1, [pc, #376] ; (8019004 ) + 8018e8a: 485f ldr r0, [pc, #380] ; (8019008 ) + 8018e8c: f003 f8c2 bl 801c014 + 8018e90: 2300 movs r3, #0 + 8018e92: e0b1 b.n 8018ff8 + LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;); + 8018e94: 68bb ldr r3, [r7, #8] + 8018e96: 2b00 cmp r3, #0 + 8018e98: d108 bne.n 8018eac + 8018e9a: 4b59 ldr r3, [pc, #356] ; (8019000 ) + 8018e9c: f240 726a movw r2, #1898 ; 0x76a + 8018ea0: 495a ldr r1, [pc, #360] ; (801900c ) + 8018ea2: 4859 ldr r0, [pc, #356] ; (8019008 ) + 8018ea4: f003 f8b6 bl 801c014 + 8018ea8: 2300 movs r3, #0 + 8018eaa: e0a5 b.n 8018ff8 + p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); + 8018eac: f44f 7220 mov.w r2, #640 ; 0x280 + 8018eb0: f44f 719a mov.w r1, #308 ; 0x134 + 8018eb4: 2036 movs r0, #54 ; 0x36 + 8018eb6: f7f7 fabf bl 8010438 + 8018eba: 61b8 str r0, [r7, #24] + if (p_out == NULL) { + 8018ebc: 69bb ldr r3, [r7, #24] + 8018ebe: 2b00 cmp r3, #0 + 8018ec0: d101 bne.n 8018ec6 + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_create_msg(): could not allocate pbuf\n")); + return NULL; + 8018ec2: 2300 movs r3, #0 + 8018ec4: e098 b.n 8018ff8 + } + LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg", + 8018ec6: 69bb ldr r3, [r7, #24] + 8018ec8: 895b ldrh r3, [r3, #10] + 8018eca: f5b3 7f9a cmp.w r3, #308 ; 0x134 + 8018ece: d206 bcs.n 8018ede + 8018ed0: 4b4b ldr r3, [pc, #300] ; (8019000 ) + 8018ed2: f240 7271 movw r2, #1905 ; 0x771 + 8018ed6: 494e ldr r1, [pc, #312] ; (8019010 ) + 8018ed8: 484b ldr r0, [pc, #300] ; (8019008 ) + 8018eda: f003 f89b bl 801c014 + (p_out->len >= sizeof(struct dhcp_msg))); + + /* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */ + if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) { + 8018ede: 79fb ldrb r3, [r7, #7] + 8018ee0: 2b03 cmp r3, #3 + 8018ee2: d103 bne.n 8018eec + 8018ee4: 68bb ldr r3, [r7, #8] + 8018ee6: 795b ldrb r3, [r3, #5] + 8018ee8: 2b03 cmp r3, #3 + 8018eea: d10d bne.n 8018f08 + /* reuse transaction identifier in retransmissions */ + if (dhcp->tries == 0) { + 8018eec: 68bb ldr r3, [r7, #8] + 8018eee: 799b ldrb r3, [r3, #6] + 8018ef0: 2b00 cmp r3, #0 + 8018ef2: d105 bne.n 8018f00 +#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND) + xid = LWIP_RAND(); + 8018ef4: f003 f91c bl 801c130 + 8018ef8: 4603 mov r3, r0 + 8018efa: 461a mov r2, r3 + 8018efc: 4b45 ldr r3, [pc, #276] ; (8019014 ) + 8018efe: 601a str r2, [r3, #0] +#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ + xid++; +#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ + } + dhcp->xid = xid; + 8018f00: 4b44 ldr r3, [pc, #272] ; (8019014 ) + 8018f02: 681a ldr r2, [r3, #0] + 8018f04: 68bb ldr r3, [r7, #8] + 8018f06: 601a str r2, [r3, #0] + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, + ("transaction id xid(%"X32_F")\n", xid)); + + msg_out = (struct dhcp_msg *)p_out->payload; + 8018f08: 69bb ldr r3, [r7, #24] + 8018f0a: 685b ldr r3, [r3, #4] + 8018f0c: 617b str r3, [r7, #20] + memset(msg_out, 0, sizeof(struct dhcp_msg)); + 8018f0e: f44f 729a mov.w r2, #308 ; 0x134 + 8018f12: 2100 movs r1, #0 + 8018f14: 6978 ldr r0, [r7, #20] + 8018f16: f002 ffe0 bl 801beda + + msg_out->op = DHCP_BOOTREQUEST; + 8018f1a: 697b ldr r3, [r7, #20] + 8018f1c: 2201 movs r2, #1 + 8018f1e: 701a strb r2, [r3, #0] + /* @todo: make link layer independent */ + msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET; + 8018f20: 697b ldr r3, [r7, #20] + 8018f22: 2201 movs r2, #1 + 8018f24: 705a strb r2, [r3, #1] + msg_out->hlen = netif->hwaddr_len; + 8018f26: 68fb ldr r3, [r7, #12] + 8018f28: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 + 8018f2c: 697b ldr r3, [r7, #20] + 8018f2e: 709a strb r2, [r3, #2] + msg_out->xid = lwip_htonl(dhcp->xid); + 8018f30: 68bb ldr r3, [r7, #8] + 8018f32: 681b ldr r3, [r3, #0] + 8018f34: 4618 mov r0, r3 + 8018f36: f7f5 f990 bl 800e25a + 8018f3a: 4602 mov r2, r0 + 8018f3c: 697b ldr r3, [r7, #20] + 8018f3e: 605a str r2, [r3, #4] + /* we don't need the broadcast flag since we can receive unicast traffic + before being fully configured! */ + /* set ciaddr to netif->ip_addr based on message_type and state */ + if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) || + 8018f40: 79fb ldrb r3, [r7, #7] + 8018f42: 2b08 cmp r3, #8 + 8018f44: d010 beq.n 8018f68 + 8018f46: 79fb ldrb r3, [r7, #7] + 8018f48: 2b04 cmp r3, #4 + 8018f4a: d00d beq.n 8018f68 + 8018f4c: 79fb ldrb r3, [r7, #7] + 8018f4e: 2b07 cmp r3, #7 + 8018f50: d00a beq.n 8018f68 + 8018f52: 79fb ldrb r3, [r7, #7] + 8018f54: 2b03 cmp r3, #3 + 8018f56: d10c bne.n 8018f72 + ((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */ + ((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) { + 8018f58: 68bb ldr r3, [r7, #8] + 8018f5a: 795b ldrb r3, [r3, #5] + ((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */ + 8018f5c: 2b05 cmp r3, #5 + 8018f5e: d003 beq.n 8018f68 + ((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) { + 8018f60: 68bb ldr r3, [r7, #8] + 8018f62: 795b ldrb r3, [r3, #5] + 8018f64: 2b04 cmp r3, #4 + 8018f66: d104 bne.n 8018f72 + ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif)); + 8018f68: 68fb ldr r3, [r7, #12] + 8018f6a: 3304 adds r3, #4 + 8018f6c: 681a ldr r2, [r3, #0] + 8018f6e: 697b ldr r3, [r7, #20] + 8018f70: 60da str r2, [r3, #12] + } + for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + 8018f72: 2300 movs r3, #0 + 8018f74: 83fb strh r3, [r7, #30] + 8018f76: e00c b.n 8018f92 + /* copy netif hardware address (padded with zeroes through memset already) */ + msg_out->chaddr[i] = netif->hwaddr[i]; + 8018f78: 8bfa ldrh r2, [r7, #30] + 8018f7a: 8bfb ldrh r3, [r7, #30] + 8018f7c: 68f9 ldr r1, [r7, #12] + 8018f7e: 440a add r2, r1 + 8018f80: f892 102a ldrb.w r1, [r2, #42] ; 0x2a + 8018f84: 697a ldr r2, [r7, #20] + 8018f86: 4413 add r3, r2 + 8018f88: 460a mov r2, r1 + 8018f8a: 771a strb r2, [r3, #28] + for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + 8018f8c: 8bfb ldrh r3, [r7, #30] + 8018f8e: 3301 adds r3, #1 + 8018f90: 83fb strh r3, [r7, #30] + 8018f92: 8bfb ldrh r3, [r7, #30] + 8018f94: 2b05 cmp r3, #5 + 8018f96: d9ef bls.n 8018f78 + } + msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE); + 8018f98: 697b ldr r3, [r7, #20] + 8018f9a: 2200 movs r2, #0 + 8018f9c: f042 0263 orr.w r2, r2, #99 ; 0x63 + 8018fa0: f883 20ec strb.w r2, [r3, #236] ; 0xec + 8018fa4: 2200 movs r2, #0 + 8018fa6: f062 027d orn r2, r2, #125 ; 0x7d + 8018faa: f883 20ed strb.w r2, [r3, #237] ; 0xed + 8018fae: 2200 movs r2, #0 + 8018fb0: f042 0253 orr.w r2, r2, #83 ; 0x53 + 8018fb4: f883 20ee strb.w r2, [r3, #238] ; 0xee + 8018fb8: 2200 movs r2, #0 + 8018fba: f042 0263 orr.w r2, r2, #99 ; 0x63 + 8018fbe: f883 20ef strb.w r2, [r3, #239] ; 0xef + /* Add option MESSAGE_TYPE */ + options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + 8018fc2: 697b ldr r3, [r7, #20] + 8018fc4: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018fc8: 2301 movs r3, #1 + 8018fca: 2235 movs r2, #53 ; 0x35 + 8018fcc: 2000 movs r0, #0 + 8018fce: f7ff faab bl 8018528 + 8018fd2: 4603 mov r3, r0 + 8018fd4: 827b strh r3, [r7, #18] + options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type); + 8018fd6: 697b ldr r3, [r7, #20] + 8018fd8: f103 01f0 add.w r1, r3, #240 ; 0xf0 + 8018fdc: 79fa ldrb r2, [r7, #7] + 8018fde: 8a7b ldrh r3, [r7, #18] + 8018fe0: 4618 mov r0, r3 + 8018fe2: f7ff fad5 bl 8018590 + 8018fe6: 4603 mov r3, r0 + 8018fe8: 827b strh r3, [r7, #18] + if (options_out_len) { + 8018fea: 683b ldr r3, [r7, #0] + 8018fec: 2b00 cmp r3, #0 + 8018fee: d002 beq.n 8018ff6 + *options_out_len = options_out_len_loc; + 8018ff0: 683b ldr r3, [r7, #0] + 8018ff2: 8a7a ldrh r2, [r7, #18] + 8018ff4: 801a strh r2, [r3, #0] + } + return p_out; + 8018ff6: 69bb ldr r3, [r7, #24] +} + 8018ff8: 4618 mov r0, r3 + 8018ffa: 3720 adds r7, #32 + 8018ffc: 46bd mov sp, r7 + 8018ffe: bd80 pop {r7, pc} + 8019000: 08020d70 .word 0x08020d70 + 8019004: 080210a0 .word 0x080210a0 + 8019008: 08020dd0 .word 0x08020dd0 + 801900c: 080210c0 .word 0x080210c0 + 8019010: 080210e0 .word 0x080210e0 + 8019014: 2000cfcc .word 0x2000cfcc + +08019018 : + * Adds the END option to the DHCP message, and if + * necessary, up to three padding bytes. + */ +static void +dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out) +{ + 8019018: b580 push {r7, lr} + 801901a: b084 sub sp, #16 + 801901c: af00 add r7, sp, #0 + 801901e: 4603 mov r3, r0 + 8019020: 60b9 str r1, [r7, #8] + 8019022: 607a str r2, [r7, #4] + 8019024: 81fb strh r3, [r7, #14] + options[options_out_len++] = DHCP_OPTION_END; + 8019026: 89fb ldrh r3, [r7, #14] + 8019028: 1c5a adds r2, r3, #1 + 801902a: 81fa strh r2, [r7, #14] + 801902c: 461a mov r2, r3 + 801902e: 68bb ldr r3, [r7, #8] + 8019030: 4413 add r3, r2 + 8019032: 22ff movs r2, #255 ; 0xff + 8019034: 701a strb r2, [r3, #0] + /* packet is too small, or not 4 byte aligned? */ + while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) && + 8019036: e007 b.n 8019048 + (options_out_len < DHCP_OPTIONS_LEN)) { + /* add a fill/padding byte */ + options[options_out_len++] = 0; + 8019038: 89fb ldrh r3, [r7, #14] + 801903a: 1c5a adds r2, r3, #1 + 801903c: 81fa strh r2, [r7, #14] + 801903e: 461a mov r2, r3 + 8019040: 68bb ldr r3, [r7, #8] + 8019042: 4413 add r3, r2 + 8019044: 2200 movs r2, #0 + 8019046: 701a strb r2, [r3, #0] + while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) && + 8019048: 89fb ldrh r3, [r7, #14] + 801904a: 2b43 cmp r3, #67 ; 0x43 + 801904c: d904 bls.n 8019058 + 801904e: 89fb ldrh r3, [r7, #14] + 8019050: f003 0303 and.w r3, r3, #3 + 8019054: 2b00 cmp r3, #0 + 8019056: d002 beq.n 801905e + 8019058: 89fb ldrh r3, [r7, #14] + 801905a: 2b43 cmp r3, #67 ; 0x43 + 801905c: d9ec bls.n 8019038 + } + /* shrink the pbuf to the actual content length */ + pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len)); + 801905e: 89fb ldrh r3, [r7, #14] + 8019060: 33f0 adds r3, #240 ; 0xf0 + 8019062: b29b uxth r3, r3 + 8019064: 4619 mov r1, r3 + 8019066: 6878 ldr r0, [r7, #4] + 8019068: f7f7 fb44 bl 80106f4 +} + 801906c: bf00 nop + 801906e: 3710 adds r7, #16 + 8019070: 46bd mov sp, r7 + 8019072: bd80 pop {r7, pc} + +08019074 : + * @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING), + * 0 otherwise + */ +u8_t +dhcp_supplied_address(const struct netif *netif) +{ + 8019074: b480 push {r7} + 8019076: b085 sub sp, #20 + 8019078: af00 add r7, sp, #0 + 801907a: 6078 str r0, [r7, #4] + if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) { + 801907c: 687b ldr r3, [r7, #4] + 801907e: 2b00 cmp r3, #0 + 8019080: d017 beq.n 80190b2 + 8019082: 687b ldr r3, [r7, #4] + 8019084: 6a5b ldr r3, [r3, #36] ; 0x24 + 8019086: 2b00 cmp r3, #0 + 8019088: d013 beq.n 80190b2 + struct dhcp *dhcp = netif_dhcp_data(netif); + 801908a: 687b ldr r3, [r7, #4] + 801908c: 6a5b ldr r3, [r3, #36] ; 0x24 + 801908e: 60fb str r3, [r7, #12] + return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) || + 8019090: 68fb ldr r3, [r7, #12] + 8019092: 795b ldrb r3, [r3, #5] + 8019094: 2b0a cmp r3, #10 + 8019096: d007 beq.n 80190a8 + 8019098: 68fb ldr r3, [r7, #12] + 801909a: 795b ldrb r3, [r3, #5] + 801909c: 2b05 cmp r3, #5 + 801909e: d003 beq.n 80190a8 + (dhcp->state == DHCP_STATE_REBINDING); + 80190a0: 68fb ldr r3, [r7, #12] + 80190a2: 795b ldrb r3, [r3, #5] + return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) || + 80190a4: 2b04 cmp r3, #4 + 80190a6: d101 bne.n 80190ac + 80190a8: 2301 movs r3, #1 + 80190aa: e000 b.n 80190ae + 80190ac: 2300 movs r3, #0 + 80190ae: b2db uxtb r3, r3 + 80190b0: e000 b.n 80190b4 + } + return 0; + 80190b2: 2300 movs r3, #0 +} + 80190b4: 4618 mov r0, r3 + 80190b6: 3714 adds r7, #20 + 80190b8: 46bd mov sp, r7 + 80190ba: f85d 7b04 ldr.w r7, [sp], #4 + 80190be: 4770 bx lr + +080190c0 : +#endif /* ARP_QUEUEING */ + +/** Clean up ARP table entries */ +static void +etharp_free_entry(int i) +{ + 80190c0: b580 push {r7, lr} + 80190c2: b082 sub sp, #8 + 80190c4: af00 add r7, sp, #0 + 80190c6: 6078 str r0, [r7, #4] + /* remove from SNMP ARP index tree */ + mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr); + /* and empty packet queue */ + if (arp_table[i].q != NULL) { + 80190c8: 4915 ldr r1, [pc, #84] ; (8019120 ) + 80190ca: 687a ldr r2, [r7, #4] + 80190cc: 4613 mov r3, r2 + 80190ce: 005b lsls r3, r3, #1 + 80190d0: 4413 add r3, r2 + 80190d2: 00db lsls r3, r3, #3 + 80190d4: 440b add r3, r1 + 80190d6: 681b ldr r3, [r3, #0] + 80190d8: 2b00 cmp r3, #0 + 80190da: d013 beq.n 8019104 + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + 80190dc: 4910 ldr r1, [pc, #64] ; (8019120 ) + 80190de: 687a ldr r2, [r7, #4] + 80190e0: 4613 mov r3, r2 + 80190e2: 005b lsls r3, r3, #1 + 80190e4: 4413 add r3, r2 + 80190e6: 00db lsls r3, r3, #3 + 80190e8: 440b add r3, r1 + 80190ea: 681b ldr r3, [r3, #0] + 80190ec: 4618 mov r0, r3 + 80190ee: f7f7 fc87 bl 8010a00 + arp_table[i].q = NULL; + 80190f2: 490b ldr r1, [pc, #44] ; (8019120 ) + 80190f4: 687a ldr r2, [r7, #4] + 80190f6: 4613 mov r3, r2 + 80190f8: 005b lsls r3, r3, #1 + 80190fa: 4413 add r3, r2 + 80190fc: 00db lsls r3, r3, #3 + 80190fe: 440b add r3, r1 + 8019100: 2200 movs r2, #0 + 8019102: 601a str r2, [r3, #0] + } + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; + 8019104: 4906 ldr r1, [pc, #24] ; (8019120 ) + 8019106: 687a ldr r2, [r7, #4] + 8019108: 4613 mov r3, r2 + 801910a: 005b lsls r3, r3, #1 + 801910c: 4413 add r3, r2 + 801910e: 00db lsls r3, r3, #3 + 8019110: 440b add r3, r1 + 8019112: 3314 adds r3, #20 + 8019114: 2200 movs r2, #0 + 8019116: 701a strb r2, [r3, #0] + arp_table[i].ctime = 0; + arp_table[i].netif = NULL; + ip4_addr_set_zero(&arp_table[i].ipaddr); + arp_table[i].ethaddr = ethzero; +#endif /* LWIP_DEBUG */ +} + 8019118: bf00 nop + 801911a: 3708 adds r7, #8 + 801911c: 46bd mov sp, r7 + 801911e: bd80 pop {r7, pc} + 8019120: 2000cfd0 .word 0x2000cfd0 + +08019124 : + * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + 8019124: b580 push {r7, lr} + 8019126: b082 sub sp, #8 + 8019128: af00 add r7, sp, #0 + int i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 801912a: 2300 movs r3, #0 + 801912c: 607b str r3, [r7, #4] + 801912e: e096 b.n 801925e + u8_t state = arp_table[i].state; + 8019130: 494f ldr r1, [pc, #316] ; (8019270 ) + 8019132: 687a ldr r2, [r7, #4] + 8019134: 4613 mov r3, r2 + 8019136: 005b lsls r3, r3, #1 + 8019138: 4413 add r3, r2 + 801913a: 00db lsls r3, r3, #3 + 801913c: 440b add r3, r1 + 801913e: 3314 adds r3, #20 + 8019140: 781b ldrb r3, [r3, #0] + 8019142: 70fb strb r3, [r7, #3] + if (state != ETHARP_STATE_EMPTY + 8019144: 78fb ldrb r3, [r7, #3] + 8019146: 2b00 cmp r3, #0 + 8019148: f000 8086 beq.w 8019258 +#if ETHARP_SUPPORT_STATIC_ENTRIES + && (state != ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + ) { + arp_table[i].ctime++; + 801914c: 4948 ldr r1, [pc, #288] ; (8019270 ) + 801914e: 687a ldr r2, [r7, #4] + 8019150: 4613 mov r3, r2 + 8019152: 005b lsls r3, r3, #1 + 8019154: 4413 add r3, r2 + 8019156: 00db lsls r3, r3, #3 + 8019158: 440b add r3, r1 + 801915a: 3312 adds r3, #18 + 801915c: 881b ldrh r3, [r3, #0] + 801915e: 3301 adds r3, #1 + 8019160: b298 uxth r0, r3 + 8019162: 4943 ldr r1, [pc, #268] ; (8019270 ) + 8019164: 687a ldr r2, [r7, #4] + 8019166: 4613 mov r3, r2 + 8019168: 005b lsls r3, r3, #1 + 801916a: 4413 add r3, r2 + 801916c: 00db lsls r3, r3, #3 + 801916e: 440b add r3, r1 + 8019170: 3312 adds r3, #18 + 8019172: 4602 mov r2, r0 + 8019174: 801a strh r2, [r3, #0] + if ((arp_table[i].ctime >= ARP_MAXAGE) || + 8019176: 493e ldr r1, [pc, #248] ; (8019270 ) + 8019178: 687a ldr r2, [r7, #4] + 801917a: 4613 mov r3, r2 + 801917c: 005b lsls r3, r3, #1 + 801917e: 4413 add r3, r2 + 8019180: 00db lsls r3, r3, #3 + 8019182: 440b add r3, r1 + 8019184: 3312 adds r3, #18 + 8019186: 881b ldrh r3, [r3, #0] + 8019188: f5b3 7f96 cmp.w r3, #300 ; 0x12c + 801918c: d215 bcs.n 80191ba + ((arp_table[i].state == ETHARP_STATE_PENDING) && + 801918e: 4938 ldr r1, [pc, #224] ; (8019270 ) + 8019190: 687a ldr r2, [r7, #4] + 8019192: 4613 mov r3, r2 + 8019194: 005b lsls r3, r3, #1 + 8019196: 4413 add r3, r2 + 8019198: 00db lsls r3, r3, #3 + 801919a: 440b add r3, r1 + 801919c: 3314 adds r3, #20 + 801919e: 781b ldrb r3, [r3, #0] + if ((arp_table[i].ctime >= ARP_MAXAGE) || + 80191a0: 2b01 cmp r3, #1 + 80191a2: d10e bne.n 80191c2 + (arp_table[i].ctime >= ARP_MAXPENDING))) { + 80191a4: 4932 ldr r1, [pc, #200] ; (8019270 ) + 80191a6: 687a ldr r2, [r7, #4] + 80191a8: 4613 mov r3, r2 + 80191aa: 005b lsls r3, r3, #1 + 80191ac: 4413 add r3, r2 + 80191ae: 00db lsls r3, r3, #3 + 80191b0: 440b add r3, r1 + 80191b2: 3312 adds r3, #18 + 80191b4: 881b ldrh r3, [r3, #0] + ((arp_table[i].state == ETHARP_STATE_PENDING) && + 80191b6: 2b04 cmp r3, #4 + 80191b8: d903 bls.n 80191c2 + /* pending or stable entry has become old! */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n", + arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i)); + /* clean up entries that have just been expired */ + etharp_free_entry(i); + 80191ba: 6878 ldr r0, [r7, #4] + 80191bc: f7ff ff80 bl 80190c0 + 80191c0: e04a b.n 8019258 + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) { + 80191c2: 492b ldr r1, [pc, #172] ; (8019270 ) + 80191c4: 687a ldr r2, [r7, #4] + 80191c6: 4613 mov r3, r2 + 80191c8: 005b lsls r3, r3, #1 + 80191ca: 4413 add r3, r2 + 80191cc: 00db lsls r3, r3, #3 + 80191ce: 440b add r3, r1 + 80191d0: 3314 adds r3, #20 + 80191d2: 781b ldrb r3, [r3, #0] + 80191d4: 2b03 cmp r3, #3 + 80191d6: d10a bne.n 80191ee + /* Don't send more than one request every 2 seconds. */ + arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2; + 80191d8: 4925 ldr r1, [pc, #148] ; (8019270 ) + 80191da: 687a ldr r2, [r7, #4] + 80191dc: 4613 mov r3, r2 + 80191de: 005b lsls r3, r3, #1 + 80191e0: 4413 add r3, r2 + 80191e2: 00db lsls r3, r3, #3 + 80191e4: 440b add r3, r1 + 80191e6: 3314 adds r3, #20 + 80191e8: 2204 movs r2, #4 + 80191ea: 701a strb r2, [r3, #0] + 80191ec: e034 b.n 8019258 + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) { + 80191ee: 4920 ldr r1, [pc, #128] ; (8019270 ) + 80191f0: 687a ldr r2, [r7, #4] + 80191f2: 4613 mov r3, r2 + 80191f4: 005b lsls r3, r3, #1 + 80191f6: 4413 add r3, r2 + 80191f8: 00db lsls r3, r3, #3 + 80191fa: 440b add r3, r1 + 80191fc: 3314 adds r3, #20 + 80191fe: 781b ldrb r3, [r3, #0] + 8019200: 2b04 cmp r3, #4 + 8019202: d10a bne.n 801921a + /* Reset state to stable, so that the next transmitted packet will + re-send an ARP request. */ + arp_table[i].state = ETHARP_STATE_STABLE; + 8019204: 491a ldr r1, [pc, #104] ; (8019270 ) + 8019206: 687a ldr r2, [r7, #4] + 8019208: 4613 mov r3, r2 + 801920a: 005b lsls r3, r3, #1 + 801920c: 4413 add r3, r2 + 801920e: 00db lsls r3, r3, #3 + 8019210: 440b add r3, r1 + 8019212: 3314 adds r3, #20 + 8019214: 2202 movs r2, #2 + 8019216: 701a strb r2, [r3, #0] + 8019218: e01e b.n 8019258 + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + 801921a: 4915 ldr r1, [pc, #84] ; (8019270 ) + 801921c: 687a ldr r2, [r7, #4] + 801921e: 4613 mov r3, r2 + 8019220: 005b lsls r3, r3, #1 + 8019222: 4413 add r3, r2 + 8019224: 00db lsls r3, r3, #3 + 8019226: 440b add r3, r1 + 8019228: 3314 adds r3, #20 + 801922a: 781b ldrb r3, [r3, #0] + 801922c: 2b01 cmp r3, #1 + 801922e: d113 bne.n 8019258 + /* still pending, resend an ARP query */ + etharp_request(arp_table[i].netif, &arp_table[i].ipaddr); + 8019230: 490f ldr r1, [pc, #60] ; (8019270 ) + 8019232: 687a ldr r2, [r7, #4] + 8019234: 4613 mov r3, r2 + 8019236: 005b lsls r3, r3, #1 + 8019238: 4413 add r3, r2 + 801923a: 00db lsls r3, r3, #3 + 801923c: 440b add r3, r1 + 801923e: 3308 adds r3, #8 + 8019240: 6818 ldr r0, [r3, #0] + 8019242: 687a ldr r2, [r7, #4] + 8019244: 4613 mov r3, r2 + 8019246: 005b lsls r3, r3, #1 + 8019248: 4413 add r3, r2 + 801924a: 00db lsls r3, r3, #3 + 801924c: 4a08 ldr r2, [pc, #32] ; (8019270 ) + 801924e: 4413 add r3, r2 + 8019250: 3304 adds r3, #4 + 8019252: 4619 mov r1, r3 + 8019254: f000 fe72 bl 8019f3c + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 8019258: 687b ldr r3, [r7, #4] + 801925a: 3301 adds r3, #1 + 801925c: 607b str r3, [r7, #4] + 801925e: 687b ldr r3, [r7, #4] + 8019260: 2b09 cmp r3, #9 + 8019262: f77f af65 ble.w 8019130 + } + } + } +} + 8019266: bf00 nop + 8019268: bf00 nop + 801926a: 3708 adds r7, #8 + 801926c: 46bd mov sp, r7 + 801926e: bd80 pop {r7, pc} + 8019270: 2000cfd0 .word 0x2000cfd0 + +08019274 : + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s16_t +etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif) +{ + 8019274: b580 push {r7, lr} + 8019276: b08a sub sp, #40 ; 0x28 + 8019278: af00 add r7, sp, #0 + 801927a: 60f8 str r0, [r7, #12] + 801927c: 460b mov r3, r1 + 801927e: 607a str r2, [r7, #4] + 8019280: 72fb strb r3, [r7, #11] + s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + 8019282: 230a movs r3, #10 + 8019284: 84fb strh r3, [r7, #38] ; 0x26 + 8019286: 230a movs r3, #10 + 8019288: 84bb strh r3, [r7, #36] ; 0x24 + s16_t empty = ARP_TABLE_SIZE; + 801928a: 230a movs r3, #10 + 801928c: 847b strh r3, [r7, #34] ; 0x22 + s16_t i = 0; + 801928e: 2300 movs r3, #0 + 8019290: 843b strh r3, [r7, #32] + /* oldest entry with packets on queue */ + s16_t old_queue = ARP_TABLE_SIZE; + 8019292: 230a movs r3, #10 + 8019294: 83fb strh r3, [r7, #30] + /* its age */ + u16_t age_queue = 0, age_pending = 0, age_stable = 0; + 8019296: 2300 movs r3, #0 + 8019298: 83bb strh r3, [r7, #28] + 801929a: 2300 movs r3, #0 + 801929c: 837b strh r3, [r7, #26] + 801929e: 2300 movs r3, #0 + 80192a0: 833b strh r3, [r7, #24] + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 80192a2: 2300 movs r3, #0 + 80192a4: 843b strh r3, [r7, #32] + 80192a6: e0ae b.n 8019406 + u8_t state = arp_table[i].state; + 80192a8: f9b7 2020 ldrsh.w r2, [r7, #32] + 80192ac: 49a6 ldr r1, [pc, #664] ; (8019548 ) + 80192ae: 4613 mov r3, r2 + 80192b0: 005b lsls r3, r3, #1 + 80192b2: 4413 add r3, r2 + 80192b4: 00db lsls r3, r3, #3 + 80192b6: 440b add r3, r1 + 80192b8: 3314 adds r3, #20 + 80192ba: 781b ldrb r3, [r3, #0] + 80192bc: 75fb strb r3, [r7, #23] + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { + 80192be: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22 + 80192c2: 2b0a cmp r3, #10 + 80192c4: d105 bne.n 80192d2 + 80192c6: 7dfb ldrb r3, [r7, #23] + 80192c8: 2b00 cmp r3, #0 + 80192ca: d102 bne.n 80192d2 + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i)); + /* remember first empty entry */ + empty = i; + 80192cc: 8c3b ldrh r3, [r7, #32] + 80192ce: 847b strh r3, [r7, #34] ; 0x22 + 80192d0: e095 b.n 80193fe + } else if (state != ETHARP_STATE_EMPTY) { + 80192d2: 7dfb ldrb r3, [r7, #23] + 80192d4: 2b00 cmp r3, #0 + 80192d6: f000 8092 beq.w 80193fe + LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE", + 80192da: 7dfb ldrb r3, [r7, #23] + 80192dc: 2b01 cmp r3, #1 + 80192de: d009 beq.n 80192f4 + 80192e0: 7dfb ldrb r3, [r7, #23] + 80192e2: 2b01 cmp r3, #1 + 80192e4: d806 bhi.n 80192f4 + 80192e6: 4b99 ldr r3, [pc, #612] ; (801954c ) + 80192e8: f240 1223 movw r2, #291 ; 0x123 + 80192ec: 4998 ldr r1, [pc, #608] ; (8019550 ) + 80192ee: 4899 ldr r0, [pc, #612] ; (8019554 ) + 80192f0: f002 fe90 bl 801c014 + state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE); + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr) + 80192f4: 68fb ldr r3, [r7, #12] + 80192f6: 2b00 cmp r3, #0 + 80192f8: d020 beq.n 801933c + 80192fa: 68fb ldr r3, [r7, #12] + 80192fc: 6819 ldr r1, [r3, #0] + 80192fe: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019302: 4891 ldr r0, [pc, #580] ; (8019548 ) + 8019304: 4613 mov r3, r2 + 8019306: 005b lsls r3, r3, #1 + 8019308: 4413 add r3, r2 + 801930a: 00db lsls r3, r3, #3 + 801930c: 4403 add r3, r0 + 801930e: 3304 adds r3, #4 + 8019310: 681b ldr r3, [r3, #0] + 8019312: 4299 cmp r1, r3 + 8019314: d112 bne.n 801933c +#if ETHARP_TABLE_MATCH_NETIF + && ((netif == NULL) || (netif == arp_table[i].netif)) + 8019316: 687b ldr r3, [r7, #4] + 8019318: 2b00 cmp r3, #0 + 801931a: d00c beq.n 8019336 + 801931c: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019320: 4989 ldr r1, [pc, #548] ; (8019548 ) + 8019322: 4613 mov r3, r2 + 8019324: 005b lsls r3, r3, #1 + 8019326: 4413 add r3, r2 + 8019328: 00db lsls r3, r3, #3 + 801932a: 440b add r3, r1 + 801932c: 3308 adds r3, #8 + 801932e: 681b ldr r3, [r3, #0] + 8019330: 687a ldr r2, [r7, #4] + 8019332: 429a cmp r2, r3 + 8019334: d102 bne.n 801933c +#endif /* ETHARP_TABLE_MATCH_NETIF */ + ) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i)); + /* found exact IP address match, simply bail out */ + return i; + 8019336: f9b7 3020 ldrsh.w r3, [r7, #32] + 801933a: e100 b.n 801953e + } + /* pending entry? */ + if (state == ETHARP_STATE_PENDING) { + 801933c: 7dfb ldrb r3, [r7, #23] + 801933e: 2b01 cmp r3, #1 + 8019340: d140 bne.n 80193c4 + /* pending with queued packets? */ + if (arp_table[i].q != NULL) { + 8019342: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019346: 4980 ldr r1, [pc, #512] ; (8019548 ) + 8019348: 4613 mov r3, r2 + 801934a: 005b lsls r3, r3, #1 + 801934c: 4413 add r3, r2 + 801934e: 00db lsls r3, r3, #3 + 8019350: 440b add r3, r1 + 8019352: 681b ldr r3, [r3, #0] + 8019354: 2b00 cmp r3, #0 + 8019356: d01a beq.n 801938e + if (arp_table[i].ctime >= age_queue) { + 8019358: f9b7 2020 ldrsh.w r2, [r7, #32] + 801935c: 497a ldr r1, [pc, #488] ; (8019548 ) + 801935e: 4613 mov r3, r2 + 8019360: 005b lsls r3, r3, #1 + 8019362: 4413 add r3, r2 + 8019364: 00db lsls r3, r3, #3 + 8019366: 440b add r3, r1 + 8019368: 3312 adds r3, #18 + 801936a: 881b ldrh r3, [r3, #0] + 801936c: 8bba ldrh r2, [r7, #28] + 801936e: 429a cmp r2, r3 + 8019370: d845 bhi.n 80193fe + old_queue = i; + 8019372: 8c3b ldrh r3, [r7, #32] + 8019374: 83fb strh r3, [r7, #30] + age_queue = arp_table[i].ctime; + 8019376: f9b7 2020 ldrsh.w r2, [r7, #32] + 801937a: 4973 ldr r1, [pc, #460] ; (8019548 ) + 801937c: 4613 mov r3, r2 + 801937e: 005b lsls r3, r3, #1 + 8019380: 4413 add r3, r2 + 8019382: 00db lsls r3, r3, #3 + 8019384: 440b add r3, r1 + 8019386: 3312 adds r3, #18 + 8019388: 881b ldrh r3, [r3, #0] + 801938a: 83bb strh r3, [r7, #28] + 801938c: e037 b.n 80193fe + } + } else + /* pending without queued packets? */ + { + if (arp_table[i].ctime >= age_pending) { + 801938e: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019392: 496d ldr r1, [pc, #436] ; (8019548 ) + 8019394: 4613 mov r3, r2 + 8019396: 005b lsls r3, r3, #1 + 8019398: 4413 add r3, r2 + 801939a: 00db lsls r3, r3, #3 + 801939c: 440b add r3, r1 + 801939e: 3312 adds r3, #18 + 80193a0: 881b ldrh r3, [r3, #0] + 80193a2: 8b7a ldrh r2, [r7, #26] + 80193a4: 429a cmp r2, r3 + 80193a6: d82a bhi.n 80193fe + old_pending = i; + 80193a8: 8c3b ldrh r3, [r7, #32] + 80193aa: 84fb strh r3, [r7, #38] ; 0x26 + age_pending = arp_table[i].ctime; + 80193ac: f9b7 2020 ldrsh.w r2, [r7, #32] + 80193b0: 4965 ldr r1, [pc, #404] ; (8019548 ) + 80193b2: 4613 mov r3, r2 + 80193b4: 005b lsls r3, r3, #1 + 80193b6: 4413 add r3, r2 + 80193b8: 00db lsls r3, r3, #3 + 80193ba: 440b add r3, r1 + 80193bc: 3312 adds r3, #18 + 80193be: 881b ldrh r3, [r3, #0] + 80193c0: 837b strh r3, [r7, #26] + 80193c2: e01c b.n 80193fe + } + } + /* stable entry? */ + } else if (state >= ETHARP_STATE_STABLE) { + 80193c4: 7dfb ldrb r3, [r7, #23] + 80193c6: 2b01 cmp r3, #1 + 80193c8: d919 bls.n 80193fe + /* don't record old_stable for static entries since they never expire */ + if (state < ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + if (arp_table[i].ctime >= age_stable) { + 80193ca: f9b7 2020 ldrsh.w r2, [r7, #32] + 80193ce: 495e ldr r1, [pc, #376] ; (8019548 ) + 80193d0: 4613 mov r3, r2 + 80193d2: 005b lsls r3, r3, #1 + 80193d4: 4413 add r3, r2 + 80193d6: 00db lsls r3, r3, #3 + 80193d8: 440b add r3, r1 + 80193da: 3312 adds r3, #18 + 80193dc: 881b ldrh r3, [r3, #0] + 80193de: 8b3a ldrh r2, [r7, #24] + 80193e0: 429a cmp r2, r3 + 80193e2: d80c bhi.n 80193fe + old_stable = i; + 80193e4: 8c3b ldrh r3, [r7, #32] + 80193e6: 84bb strh r3, [r7, #36] ; 0x24 + age_stable = arp_table[i].ctime; + 80193e8: f9b7 2020 ldrsh.w r2, [r7, #32] + 80193ec: 4956 ldr r1, [pc, #344] ; (8019548 ) + 80193ee: 4613 mov r3, r2 + 80193f0: 005b lsls r3, r3, #1 + 80193f2: 4413 add r3, r2 + 80193f4: 00db lsls r3, r3, #3 + 80193f6: 440b add r3, r1 + 80193f8: 3312 adds r3, #18 + 80193fa: 881b ldrh r3, [r3, #0] + 80193fc: 833b strh r3, [r7, #24] + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 80193fe: 8c3b ldrh r3, [r7, #32] + 8019400: 3301 adds r3, #1 + 8019402: b29b uxth r3, r3 + 8019404: 843b strh r3, [r7, #32] + 8019406: f9b7 3020 ldrsh.w r3, [r7, #32] + 801940a: 2b09 cmp r3, #9 + 801940c: f77f af4c ble.w 80192a8 + } + } + /* { we have no match } => try to create a new entry */ + + /* don't create new entry, only search? */ + if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || + 8019410: 7afb ldrb r3, [r7, #11] + 8019412: f003 0302 and.w r3, r3, #2 + 8019416: 2b00 cmp r3, #0 + 8019418: d108 bne.n 801942c + 801941a: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22 + 801941e: 2b0a cmp r3, #10 + 8019420: d107 bne.n 8019432 + /* or no empty entry found and not allowed to recycle? */ + ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { + 8019422: 7afb ldrb r3, [r7, #11] + 8019424: f003 0301 and.w r3, r3, #1 + 8019428: 2b00 cmp r3, #0 + 801942a: d102 bne.n 8019432 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n")); + return (s16_t)ERR_MEM; + 801942c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8019430: e085 b.n 801953e + * + * { ETHARP_FLAG_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + 8019432: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22 + 8019436: 2b09 cmp r3, #9 + 8019438: dc02 bgt.n 8019440 + i = empty; + 801943a: 8c7b ldrh r3, [r7, #34] ; 0x22 + 801943c: 843b strh r3, [r7, #32] + 801943e: e039 b.n 80194b4 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i)); + } else { + /* 2) found recyclable stable entry? */ + if (old_stable < ARP_TABLE_SIZE) { + 8019440: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 + 8019444: 2b09 cmp r3, #9 + 8019446: dc14 bgt.n 8019472 + /* recycle oldest stable*/ + i = old_stable; + 8019448: 8cbb ldrh r3, [r7, #36] ; 0x24 + 801944a: 843b strh r3, [r7, #32] + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i)); + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); + 801944c: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019450: 493d ldr r1, [pc, #244] ; (8019548 ) + 8019452: 4613 mov r3, r2 + 8019454: 005b lsls r3, r3, #1 + 8019456: 4413 add r3, r2 + 8019458: 00db lsls r3, r3, #3 + 801945a: 440b add r3, r1 + 801945c: 681b ldr r3, [r3, #0] + 801945e: 2b00 cmp r3, #0 + 8019460: d018 beq.n 8019494 + 8019462: 4b3a ldr r3, [pc, #232] ; (801954c ) + 8019464: f240 126d movw r2, #365 ; 0x16d + 8019468: 493b ldr r1, [pc, #236] ; (8019558 ) + 801946a: 483a ldr r0, [pc, #232] ; (8019554 ) + 801946c: f002 fdd2 bl 801c014 + 8019470: e010 b.n 8019494 + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + 8019472: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 8019476: 2b09 cmp r3, #9 + 8019478: dc02 bgt.n 8019480 + /* recycle oldest pending */ + i = old_pending; + 801947a: 8cfb ldrh r3, [r7, #38] ; 0x26 + 801947c: 843b strh r3, [r7, #32] + 801947e: e009 b.n 8019494 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i)); + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + 8019480: f9b7 301e ldrsh.w r3, [r7, #30] + 8019484: 2b09 cmp r3, #9 + 8019486: dc02 bgt.n 801948e + /* recycle oldest pending (queued packets are free in etharp_free_entry) */ + i = old_queue; + 8019488: 8bfb ldrh r3, [r7, #30] + 801948a: 843b strh r3, [r7, #32] + 801948c: e002 b.n 8019494 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q))); + /* no empty or recyclable entries found */ + } else { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n")); + return (s16_t)ERR_MEM; + 801948e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8019492: e054 b.n 801953e + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + 8019494: f9b7 3020 ldrsh.w r3, [r7, #32] + 8019498: 2b09 cmp r3, #9 + 801949a: dd06 ble.n 80194aa + 801949c: 4b2b ldr r3, [pc, #172] ; (801954c ) + 801949e: f240 127f movw r2, #383 ; 0x17f + 80194a2: 492e ldr r1, [pc, #184] ; (801955c ) + 80194a4: 482b ldr r0, [pc, #172] ; (8019554 ) + 80194a6: f002 fdb5 bl 801c014 + etharp_free_entry(i); + 80194aa: f9b7 3020 ldrsh.w r3, [r7, #32] + 80194ae: 4618 mov r0, r3 + 80194b0: f7ff fe06 bl 80190c0 + } + + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + 80194b4: f9b7 3020 ldrsh.w r3, [r7, #32] + 80194b8: 2b09 cmp r3, #9 + 80194ba: dd06 ble.n 80194ca + 80194bc: 4b23 ldr r3, [pc, #140] ; (801954c ) + 80194be: f240 1283 movw r2, #387 ; 0x183 + 80194c2: 4926 ldr r1, [pc, #152] ; (801955c ) + 80194c4: 4823 ldr r0, [pc, #140] ; (8019554 ) + 80194c6: f002 fda5 bl 801c014 + LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", + 80194ca: f9b7 2020 ldrsh.w r2, [r7, #32] + 80194ce: 491e ldr r1, [pc, #120] ; (8019548 ) + 80194d0: 4613 mov r3, r2 + 80194d2: 005b lsls r3, r3, #1 + 80194d4: 4413 add r3, r2 + 80194d6: 00db lsls r3, r3, #3 + 80194d8: 440b add r3, r1 + 80194da: 3314 adds r3, #20 + 80194dc: 781b ldrb r3, [r3, #0] + 80194de: 2b00 cmp r3, #0 + 80194e0: d006 beq.n 80194f0 + 80194e2: 4b1a ldr r3, [pc, #104] ; (801954c ) + 80194e4: f44f 72c2 mov.w r2, #388 ; 0x184 + 80194e8: 491d ldr r1, [pc, #116] ; (8019560 ) + 80194ea: 481a ldr r0, [pc, #104] ; (8019554 ) + 80194ec: f002 fd92 bl 801c014 + arp_table[i].state == ETHARP_STATE_EMPTY); + + /* IP address given? */ + if (ipaddr != NULL) { + 80194f0: 68fb ldr r3, [r7, #12] + 80194f2: 2b00 cmp r3, #0 + 80194f4: d00b beq.n 801950e + /* set IP address */ + ip4_addr_copy(arp_table[i].ipaddr, *ipaddr); + 80194f6: f9b7 2020 ldrsh.w r2, [r7, #32] + 80194fa: 68fb ldr r3, [r7, #12] + 80194fc: 6819 ldr r1, [r3, #0] + 80194fe: 4812 ldr r0, [pc, #72] ; (8019548 ) + 8019500: 4613 mov r3, r2 + 8019502: 005b lsls r3, r3, #1 + 8019504: 4413 add r3, r2 + 8019506: 00db lsls r3, r3, #3 + 8019508: 4403 add r3, r0 + 801950a: 3304 adds r3, #4 + 801950c: 6019 str r1, [r3, #0] + } + arp_table[i].ctime = 0; + 801950e: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019512: 490d ldr r1, [pc, #52] ; (8019548 ) + 8019514: 4613 mov r3, r2 + 8019516: 005b lsls r3, r3, #1 + 8019518: 4413 add r3, r2 + 801951a: 00db lsls r3, r3, #3 + 801951c: 440b add r3, r1 + 801951e: 3312 adds r3, #18 + 8019520: 2200 movs r2, #0 + 8019522: 801a strh r2, [r3, #0] +#if ETHARP_TABLE_MATCH_NETIF + arp_table[i].netif = netif; + 8019524: f9b7 2020 ldrsh.w r2, [r7, #32] + 8019528: 4907 ldr r1, [pc, #28] ; (8019548 ) + 801952a: 4613 mov r3, r2 + 801952c: 005b lsls r3, r3, #1 + 801952e: 4413 add r3, r2 + 8019530: 00db lsls r3, r3, #3 + 8019532: 440b add r3, r1 + 8019534: 3308 adds r3, #8 + 8019536: 687a ldr r2, [r7, #4] + 8019538: 601a str r2, [r3, #0] +#endif /* ETHARP_TABLE_MATCH_NETIF */ + return (s16_t)i; + 801953a: f9b7 3020 ldrsh.w r3, [r7, #32] +} + 801953e: 4618 mov r0, r3 + 8019540: 3728 adds r7, #40 ; 0x28 + 8019542: 46bd mov sp, r7 + 8019544: bd80 pop {r7, pc} + 8019546: bf00 nop + 8019548: 2000cfd0 .word 0x2000cfd0 + 801954c: 08021120 .word 0x08021120 + 8019550: 08021158 .word 0x08021158 + 8019554: 08021198 .word 0x08021198 + 8019558: 080211c0 .word 0x080211c0 + 801955c: 080211d8 .word 0x080211d8 + 8019560: 080211ec .word 0x080211ec + +08019564 : + * + * @see pbuf_free() + */ +static err_t +etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + 8019564: b580 push {r7, lr} + 8019566: b088 sub sp, #32 + 8019568: af02 add r7, sp, #8 + 801956a: 60f8 str r0, [r7, #12] + 801956c: 60b9 str r1, [r7, #8] + 801956e: 607a str r2, [r7, #4] + 8019570: 70fb strb r3, [r7, #3] + s16_t i; + LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN); + 8019572: 68fb ldr r3, [r7, #12] + 8019574: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8019578: 2b06 cmp r3, #6 + 801957a: d006 beq.n 801958a + 801957c: 4b48 ldr r3, [pc, #288] ; (80196a0 ) + 801957e: f240 12a9 movw r2, #425 ; 0x1a9 + 8019582: 4948 ldr r1, [pc, #288] ; (80196a4 ) + 8019584: 4848 ldr r0, [pc, #288] ; (80196a8 ) + 8019586: f002 fd45 bl 801c014 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], + (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); + /* non-unicast address? */ + if (ip4_addr_isany(ipaddr) || + 801958a: 68bb ldr r3, [r7, #8] + 801958c: 2b00 cmp r3, #0 + 801958e: d012 beq.n 80195b6 + 8019590: 68bb ldr r3, [r7, #8] + 8019592: 681b ldr r3, [r3, #0] + 8019594: 2b00 cmp r3, #0 + 8019596: d00e beq.n 80195b6 + ip4_addr_isbroadcast(ipaddr, netif) || + 8019598: 68bb ldr r3, [r7, #8] + 801959a: 681b ldr r3, [r3, #0] + 801959c: 68f9 ldr r1, [r7, #12] + 801959e: 4618 mov r0, r3 + 80195a0: f001 f920 bl 801a7e4 + 80195a4: 4603 mov r3, r0 + if (ip4_addr_isany(ipaddr) || + 80195a6: 2b00 cmp r3, #0 + 80195a8: d105 bne.n 80195b6 + ip4_addr_ismulticast(ipaddr)) { + 80195aa: 68bb ldr r3, [r7, #8] + 80195ac: 681b ldr r3, [r3, #0] + 80195ae: f003 03f0 and.w r3, r3, #240 ; 0xf0 + ip4_addr_isbroadcast(ipaddr, netif) || + 80195b2: 2be0 cmp r3, #224 ; 0xe0 + 80195b4: d102 bne.n 80195bc + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + 80195b6: f06f 030f mvn.w r3, #15 + 80195ba: e06c b.n 8019696 + } + /* find or create ARP entry */ + i = etharp_find_entry(ipaddr, flags, netif); + 80195bc: 78fb ldrb r3, [r7, #3] + 80195be: 68fa ldr r2, [r7, #12] + 80195c0: 4619 mov r1, r3 + 80195c2: 68b8 ldr r0, [r7, #8] + 80195c4: f7ff fe56 bl 8019274 + 80195c8: 4603 mov r3, r0 + 80195ca: 82fb strh r3, [r7, #22] + /* bail out if no entry could be found */ + if (i < 0) { + 80195cc: f9b7 3016 ldrsh.w r3, [r7, #22] + 80195d0: 2b00 cmp r3, #0 + 80195d2: da02 bge.n 80195da + return (err_t)i; + 80195d4: 8afb ldrh r3, [r7, #22] + 80195d6: b25b sxtb r3, r3 + 80195d8: e05d b.n 8019696 + return ERR_VAL; + } else +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + 80195da: f9b7 2016 ldrsh.w r2, [r7, #22] + 80195de: 4933 ldr r1, [pc, #204] ; (80196ac ) + 80195e0: 4613 mov r3, r2 + 80195e2: 005b lsls r3, r3, #1 + 80195e4: 4413 add r3, r2 + 80195e6: 00db lsls r3, r3, #3 + 80195e8: 440b add r3, r1 + 80195ea: 3314 adds r3, #20 + 80195ec: 2202 movs r2, #2 + 80195ee: 701a strb r2, [r3, #0] + } + + /* record network interface */ + arp_table[i].netif = netif; + 80195f0: f9b7 2016 ldrsh.w r2, [r7, #22] + 80195f4: 492d ldr r1, [pc, #180] ; (80196ac ) + 80195f6: 4613 mov r3, r2 + 80195f8: 005b lsls r3, r3, #1 + 80195fa: 4413 add r3, r2 + 80195fc: 00db lsls r3, r3, #3 + 80195fe: 440b add r3, r1 + 8019600: 3308 adds r3, #8 + 8019602: 68fa ldr r2, [r7, #12] + 8019604: 601a str r2, [r3, #0] + /* insert in SNMP ARP index tree */ + mib2_add_arp_entry(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i)); + /* update address */ + SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN); + 8019606: f9b7 2016 ldrsh.w r2, [r7, #22] + 801960a: 4613 mov r3, r2 + 801960c: 005b lsls r3, r3, #1 + 801960e: 4413 add r3, r2 + 8019610: 00db lsls r3, r3, #3 + 8019612: 3308 adds r3, #8 + 8019614: 4a25 ldr r2, [pc, #148] ; (80196ac ) + 8019616: 4413 add r3, r2 + 8019618: 3304 adds r3, #4 + 801961a: 2206 movs r2, #6 + 801961c: 6879 ldr r1, [r7, #4] + 801961e: 4618 mov r0, r3 + 8019620: f002 fc33 bl 801be8a + /* reset time stamp */ + arp_table[i].ctime = 0; + 8019624: f9b7 2016 ldrsh.w r2, [r7, #22] + 8019628: 4920 ldr r1, [pc, #128] ; (80196ac ) + 801962a: 4613 mov r3, r2 + 801962c: 005b lsls r3, r3, #1 + 801962e: 4413 add r3, r2 + 8019630: 00db lsls r3, r3, #3 + 8019632: 440b add r3, r1 + 8019634: 3312 adds r3, #18 + 8019636: 2200 movs r2, #0 + 8019638: 801a strh r2, [r3, #0] + /* get the packet pointer */ + p = q->p; + /* now queue entry can be freed */ + memp_free(MEMP_ARP_QUEUE, q); +#else /* ARP_QUEUEING */ + if (arp_table[i].q != NULL) { + 801963a: f9b7 2016 ldrsh.w r2, [r7, #22] + 801963e: 491b ldr r1, [pc, #108] ; (80196ac ) + 8019640: 4613 mov r3, r2 + 8019642: 005b lsls r3, r3, #1 + 8019644: 4413 add r3, r2 + 8019646: 00db lsls r3, r3, #3 + 8019648: 440b add r3, r1 + 801964a: 681b ldr r3, [r3, #0] + 801964c: 2b00 cmp r3, #0 + 801964e: d021 beq.n 8019694 + struct pbuf *p = arp_table[i].q; + 8019650: f9b7 2016 ldrsh.w r2, [r7, #22] + 8019654: 4915 ldr r1, [pc, #84] ; (80196ac ) + 8019656: 4613 mov r3, r2 + 8019658: 005b lsls r3, r3, #1 + 801965a: 4413 add r3, r2 + 801965c: 00db lsls r3, r3, #3 + 801965e: 440b add r3, r1 + 8019660: 681b ldr r3, [r3, #0] + 8019662: 613b str r3, [r7, #16] + arp_table[i].q = NULL; + 8019664: f9b7 2016 ldrsh.w r2, [r7, #22] + 8019668: 4910 ldr r1, [pc, #64] ; (80196ac ) + 801966a: 4613 mov r3, r2 + 801966c: 005b lsls r3, r3, #1 + 801966e: 4413 add r3, r2 + 8019670: 00db lsls r3, r3, #3 + 8019672: 440b add r3, r1 + 8019674: 2200 movs r2, #0 + 8019676: 601a str r2, [r3, #0] +#endif /* ARP_QUEUEING */ + /* send the queued IP packet */ + ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP); + 8019678: 68fb ldr r3, [r7, #12] + 801967a: f103 022a add.w r2, r3, #42 ; 0x2a + 801967e: f44f 6300 mov.w r3, #2048 ; 0x800 + 8019682: 9300 str r3, [sp, #0] + 8019684: 687b ldr r3, [r7, #4] + 8019686: 6939 ldr r1, [r7, #16] + 8019688: 68f8 ldr r0, [r7, #12] + 801968a: f002 f973 bl 801b974 + /* free the queued IP packet */ + pbuf_free(p); + 801968e: 6938 ldr r0, [r7, #16] + 8019690: f7f7 f9b6 bl 8010a00 + } + return ERR_OK; + 8019694: 2300 movs r3, #0 +} + 8019696: 4618 mov r0, r3 + 8019698: 3718 adds r7, #24 + 801969a: 46bd mov sp, r7 + 801969c: bd80 pop {r7, pc} + 801969e: bf00 nop + 80196a0: 08021120 .word 0x08021120 + 80196a4: 08021218 .word 0x08021218 + 80196a8: 08021198 .word 0x08021198 + 80196ac: 2000cfd0 .word 0x2000cfd0 + +080196b0 : + * + * @param netif points to a network interface + */ +void +etharp_cleanup_netif(struct netif *netif) +{ + 80196b0: b580 push {r7, lr} + 80196b2: b084 sub sp, #16 + 80196b4: af00 add r7, sp, #0 + 80196b6: 6078 str r0, [r7, #4] + int i; + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 80196b8: 2300 movs r3, #0 + 80196ba: 60fb str r3, [r7, #12] + 80196bc: e01e b.n 80196fc + u8_t state = arp_table[i].state; + 80196be: 4913 ldr r1, [pc, #76] ; (801970c ) + 80196c0: 68fa ldr r2, [r7, #12] + 80196c2: 4613 mov r3, r2 + 80196c4: 005b lsls r3, r3, #1 + 80196c6: 4413 add r3, r2 + 80196c8: 00db lsls r3, r3, #3 + 80196ca: 440b add r3, r1 + 80196cc: 3314 adds r3, #20 + 80196ce: 781b ldrb r3, [r3, #0] + 80196d0: 72fb strb r3, [r7, #11] + if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) { + 80196d2: 7afb ldrb r3, [r7, #11] + 80196d4: 2b00 cmp r3, #0 + 80196d6: d00e beq.n 80196f6 + 80196d8: 490c ldr r1, [pc, #48] ; (801970c ) + 80196da: 68fa ldr r2, [r7, #12] + 80196dc: 4613 mov r3, r2 + 80196de: 005b lsls r3, r3, #1 + 80196e0: 4413 add r3, r2 + 80196e2: 00db lsls r3, r3, #3 + 80196e4: 440b add r3, r1 + 80196e6: 3308 adds r3, #8 + 80196e8: 681b ldr r3, [r3, #0] + 80196ea: 687a ldr r2, [r7, #4] + 80196ec: 429a cmp r2, r3 + 80196ee: d102 bne.n 80196f6 + etharp_free_entry(i); + 80196f0: 68f8 ldr r0, [r7, #12] + 80196f2: f7ff fce5 bl 80190c0 + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 80196f6: 68fb ldr r3, [r7, #12] + 80196f8: 3301 adds r3, #1 + 80196fa: 60fb str r3, [r7, #12] + 80196fc: 68fb ldr r3, [r7, #12] + 80196fe: 2b09 cmp r3, #9 + 8019700: dddd ble.n 80196be + } + } +} + 8019702: bf00 nop + 8019704: bf00 nop + 8019706: 3710 adds r7, #16 + 8019708: 46bd mov sp, r7 + 801970a: bd80 pop {r7, pc} + 801970c: 2000cfd0 .word 0x2000cfd0 + +08019710 : + * + * @see pbuf_free() + */ +void +etharp_input(struct pbuf *p, struct netif *netif) +{ + 8019710: b5b0 push {r4, r5, r7, lr} + 8019712: b08a sub sp, #40 ; 0x28 + 8019714: af04 add r7, sp, #16 + 8019716: 6078 str r0, [r7, #4] + 8019718: 6039 str r1, [r7, #0] + ip4_addr_t sipaddr, dipaddr; + u8_t for_us; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + 801971a: 683b ldr r3, [r7, #0] + 801971c: 2b00 cmp r3, #0 + 801971e: d107 bne.n 8019730 + 8019720: 4b3f ldr r3, [pc, #252] ; (8019820 ) + 8019722: f240 228a movw r2, #650 ; 0x28a + 8019726: 493f ldr r1, [pc, #252] ; (8019824 ) + 8019728: 483f ldr r0, [pc, #252] ; (8019828 ) + 801972a: f002 fc73 bl 801c014 + 801972e: e074 b.n 801981a + + hdr = (struct etharp_hdr *)p->payload; + 8019730: 687b ldr r3, [r7, #4] + 8019732: 685b ldr r3, [r3, #4] + 8019734: 613b str r3, [r7, #16] + + /* RFC 826 "Packet Reception": */ + if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || + 8019736: 693b ldr r3, [r7, #16] + 8019738: 881b ldrh r3, [r3, #0] + 801973a: b29b uxth r3, r3 + 801973c: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8019740: d10c bne.n 801975c + (hdr->hwlen != ETH_HWADDR_LEN) || + 8019742: 693b ldr r3, [r7, #16] + 8019744: 791b ldrb r3, [r3, #4] + if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || + 8019746: 2b06 cmp r3, #6 + 8019748: d108 bne.n 801975c + (hdr->protolen != sizeof(ip4_addr_t)) || + 801974a: 693b ldr r3, [r7, #16] + 801974c: 795b ldrb r3, [r3, #5] + (hdr->hwlen != ETH_HWADDR_LEN) || + 801974e: 2b04 cmp r3, #4 + 8019750: d104 bne.n 801975c + (hdr->proto != PP_HTONS(ETHTYPE_IP))) { + 8019752: 693b ldr r3, [r7, #16] + 8019754: 885b ldrh r3, [r3, #2] + 8019756: b29b uxth r3, r3 + (hdr->protolen != sizeof(ip4_addr_t)) || + 8019758: 2b08 cmp r3, #8 + 801975a: d003 beq.n 8019764 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", + hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen)); + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + 801975c: 6878 ldr r0, [r7, #4] + 801975e: f7f7 f94f bl 8010a00 + return; + 8019762: e05a b.n 801981a + autoip_arp_reply(netif, hdr); +#endif /* LWIP_AUTOIP */ + + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr); + 8019764: 693b ldr r3, [r7, #16] + 8019766: 330e adds r3, #14 + 8019768: 681b ldr r3, [r3, #0] + 801976a: 60fb str r3, [r7, #12] + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr); + 801976c: 693b ldr r3, [r7, #16] + 801976e: 3318 adds r3, #24 + 8019770: 681b ldr r3, [r3, #0] + 8019772: 60bb str r3, [r7, #8] + + /* this interface is not configured? */ + if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 8019774: 683b ldr r3, [r7, #0] + 8019776: 3304 adds r3, #4 + 8019778: 681b ldr r3, [r3, #0] + 801977a: 2b00 cmp r3, #0 + 801977c: d102 bne.n 8019784 + for_us = 0; + 801977e: 2300 movs r3, #0 + 8019780: 75fb strb r3, [r7, #23] + 8019782: e009 b.n 8019798 + } else { + /* ARP packet directed to us? */ + for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif)); + 8019784: 68ba ldr r2, [r7, #8] + 8019786: 683b ldr r3, [r7, #0] + 8019788: 3304 adds r3, #4 + 801978a: 681b ldr r3, [r3, #0] + 801978c: 429a cmp r2, r3 + 801978e: bf0c ite eq + 8019790: 2301 moveq r3, #1 + 8019792: 2300 movne r3, #0 + 8019794: b2db uxtb r3, r3 + 8019796: 75fb strb r3, [r7, #23] + /* ARP message directed to us? + -> add IP address in ARP cache; assume requester wants to talk to us, + can result in directly sending the queued packets for this host. + ARP message not directed to us? + -> update the source IP address in the cache, if present */ + etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), + 8019798: 693b ldr r3, [r7, #16] + 801979a: f103 0208 add.w r2, r3, #8 + 801979e: 7dfb ldrb r3, [r7, #23] + 80197a0: 2b00 cmp r3, #0 + 80197a2: d001 beq.n 80197a8 + 80197a4: 2301 movs r3, #1 + 80197a6: e000 b.n 80197aa + 80197a8: 2302 movs r3, #2 + 80197aa: f107 010c add.w r1, r7, #12 + 80197ae: 6838 ldr r0, [r7, #0] + 80197b0: f7ff fed8 bl 8019564 + for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); + + /* now act on the message itself */ + switch (hdr->opcode) { + 80197b4: 693b ldr r3, [r7, #16] + 80197b6: 88db ldrh r3, [r3, #6] + 80197b8: b29b uxth r3, r3 + 80197ba: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80197be: d003 beq.n 80197c8 + 80197c0: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80197c4: d01e beq.n 8019804 +#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode))); + ETHARP_STATS_INC(etharp.err); + break; + 80197c6: e025 b.n 8019814 + if (for_us) { + 80197c8: 7dfb ldrb r3, [r7, #23] + 80197ca: 2b00 cmp r3, #0 + 80197cc: d021 beq.n 8019812 + (struct eth_addr *)netif->hwaddr, &hdr->shwaddr, + 80197ce: 683b ldr r3, [r7, #0] + 80197d0: f103 002a add.w r0, r3, #42 ; 0x2a + 80197d4: 693b ldr r3, [r7, #16] + 80197d6: f103 0408 add.w r4, r3, #8 + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), + 80197da: 683b ldr r3, [r7, #0] + 80197dc: f103 052a add.w r5, r3, #42 ; 0x2a + 80197e0: 683b ldr r3, [r7, #0] + 80197e2: 3304 adds r3, #4 + &hdr->shwaddr, &sipaddr, + 80197e4: 693a ldr r2, [r7, #16] + 80197e6: 3208 adds r2, #8 + etharp_raw(netif, + 80197e8: 2102 movs r1, #2 + 80197ea: 9103 str r1, [sp, #12] + 80197ec: f107 010c add.w r1, r7, #12 + 80197f0: 9102 str r1, [sp, #8] + 80197f2: 9201 str r2, [sp, #4] + 80197f4: 9300 str r3, [sp, #0] + 80197f6: 462b mov r3, r5 + 80197f8: 4622 mov r2, r4 + 80197fa: 4601 mov r1, r0 + 80197fc: 6838 ldr r0, [r7, #0] + 80197fe: f000 faef bl 8019de0 + break; + 8019802: e006 b.n 8019812 + dhcp_arp_reply(netif, &sipaddr); + 8019804: f107 030c add.w r3, r7, #12 + 8019808: 4619 mov r1, r3 + 801980a: 6838 ldr r0, [r7, #0] + 801980c: f7fe f9cc bl 8017ba8 + break; + 8019810: e000 b.n 8019814 + break; + 8019812: bf00 nop + } + /* free ARP packet */ + pbuf_free(p); + 8019814: 6878 ldr r0, [r7, #4] + 8019816: f7f7 f8f3 bl 8010a00 +} + 801981a: 3718 adds r7, #24 + 801981c: 46bd mov sp, r7 + 801981e: bdb0 pop {r4, r5, r7, pc} + 8019820: 08021120 .word 0x08021120 + 8019824: 08021270 .word 0x08021270 + 8019828: 08021198 .word 0x08021198 + +0801982c : +/** Just a small helper function that sends a pbuf to an ethernet address + * in the arp_table specified by the index 'arp_idx'. + */ +static err_t +etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx) +{ + 801982c: b580 push {r7, lr} + 801982e: b086 sub sp, #24 + 8019830: af02 add r7, sp, #8 + 8019832: 60f8 str r0, [r7, #12] + 8019834: 60b9 str r1, [r7, #8] + 8019836: 4613 mov r3, r2 + 8019838: 71fb strb r3, [r7, #7] + LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE", + 801983a: 79fa ldrb r2, [r7, #7] + 801983c: 4944 ldr r1, [pc, #272] ; (8019950 ) + 801983e: 4613 mov r3, r2 + 8019840: 005b lsls r3, r3, #1 + 8019842: 4413 add r3, r2 + 8019844: 00db lsls r3, r3, #3 + 8019846: 440b add r3, r1 + 8019848: 3314 adds r3, #20 + 801984a: 781b ldrb r3, [r3, #0] + 801984c: 2b01 cmp r3, #1 + 801984e: d806 bhi.n 801985e + 8019850: 4b40 ldr r3, [pc, #256] ; (8019954 ) + 8019852: f240 22ee movw r2, #750 ; 0x2ee + 8019856: 4940 ldr r1, [pc, #256] ; (8019958 ) + 8019858: 4840 ldr r0, [pc, #256] ; (801995c ) + 801985a: f002 fbdb bl 801c014 + arp_table[arp_idx].state >= ETHARP_STATE_STABLE); + /* if arp table entry is about to expire: re-request it, + but only if its state is ETHARP_STATE_STABLE to prevent flooding the + network with ARP requests if this address is used frequently. */ + if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) { + 801985e: 79fa ldrb r2, [r7, #7] + 8019860: 493b ldr r1, [pc, #236] ; (8019950 ) + 8019862: 4613 mov r3, r2 + 8019864: 005b lsls r3, r3, #1 + 8019866: 4413 add r3, r2 + 8019868: 00db lsls r3, r3, #3 + 801986a: 440b add r3, r1 + 801986c: 3314 adds r3, #20 + 801986e: 781b ldrb r3, [r3, #0] + 8019870: 2b02 cmp r3, #2 + 8019872: d153 bne.n 801991c + if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) { + 8019874: 79fa ldrb r2, [r7, #7] + 8019876: 4936 ldr r1, [pc, #216] ; (8019950 ) + 8019878: 4613 mov r3, r2 + 801987a: 005b lsls r3, r3, #1 + 801987c: 4413 add r3, r2 + 801987e: 00db lsls r3, r3, #3 + 8019880: 440b add r3, r1 + 8019882: 3312 adds r3, #18 + 8019884: 881b ldrh r3, [r3, #0] + 8019886: f5b3 7f8e cmp.w r3, #284 ; 0x11c + 801988a: d919 bls.n 80198c0 + /* issue a standard request using broadcast */ + if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) { + 801988c: 79fa ldrb r2, [r7, #7] + 801988e: 4613 mov r3, r2 + 8019890: 005b lsls r3, r3, #1 + 8019892: 4413 add r3, r2 + 8019894: 00db lsls r3, r3, #3 + 8019896: 4a2e ldr r2, [pc, #184] ; (8019950 ) + 8019898: 4413 add r3, r2 + 801989a: 3304 adds r3, #4 + 801989c: 4619 mov r1, r3 + 801989e: 68f8 ldr r0, [r7, #12] + 80198a0: f000 fb4c bl 8019f3c + 80198a4: 4603 mov r3, r0 + 80198a6: 2b00 cmp r3, #0 + 80198a8: d138 bne.n 801991c + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + 80198aa: 79fa ldrb r2, [r7, #7] + 80198ac: 4928 ldr r1, [pc, #160] ; (8019950 ) + 80198ae: 4613 mov r3, r2 + 80198b0: 005b lsls r3, r3, #1 + 80198b2: 4413 add r3, r2 + 80198b4: 00db lsls r3, r3, #3 + 80198b6: 440b add r3, r1 + 80198b8: 3314 adds r3, #20 + 80198ba: 2203 movs r2, #3 + 80198bc: 701a strb r2, [r3, #0] + 80198be: e02d b.n 801991c + } + } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) { + 80198c0: 79fa ldrb r2, [r7, #7] + 80198c2: 4923 ldr r1, [pc, #140] ; (8019950 ) + 80198c4: 4613 mov r3, r2 + 80198c6: 005b lsls r3, r3, #1 + 80198c8: 4413 add r3, r2 + 80198ca: 00db lsls r3, r3, #3 + 80198cc: 440b add r3, r1 + 80198ce: 3312 adds r3, #18 + 80198d0: 881b ldrh r3, [r3, #0] + 80198d2: f5b3 7f87 cmp.w r3, #270 ; 0x10e + 80198d6: d321 bcc.n 801991c + /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */ + if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) { + 80198d8: 79fa ldrb r2, [r7, #7] + 80198da: 4613 mov r3, r2 + 80198dc: 005b lsls r3, r3, #1 + 80198de: 4413 add r3, r2 + 80198e0: 00db lsls r3, r3, #3 + 80198e2: 4a1b ldr r2, [pc, #108] ; (8019950 ) + 80198e4: 4413 add r3, r2 + 80198e6: 1d19 adds r1, r3, #4 + 80198e8: 79fa ldrb r2, [r7, #7] + 80198ea: 4613 mov r3, r2 + 80198ec: 005b lsls r3, r3, #1 + 80198ee: 4413 add r3, r2 + 80198f0: 00db lsls r3, r3, #3 + 80198f2: 3308 adds r3, #8 + 80198f4: 4a16 ldr r2, [pc, #88] ; (8019950 ) + 80198f6: 4413 add r3, r2 + 80198f8: 3304 adds r3, #4 + 80198fa: 461a mov r2, r3 + 80198fc: 68f8 ldr r0, [r7, #12] + 80198fe: f000 fafb bl 8019ef8 + 8019902: 4603 mov r3, r0 + 8019904: 2b00 cmp r3, #0 + 8019906: d109 bne.n 801991c + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + 8019908: 79fa ldrb r2, [r7, #7] + 801990a: 4911 ldr r1, [pc, #68] ; (8019950 ) + 801990c: 4613 mov r3, r2 + 801990e: 005b lsls r3, r3, #1 + 8019910: 4413 add r3, r2 + 8019912: 00db lsls r3, r3, #3 + 8019914: 440b add r3, r1 + 8019916: 3314 adds r3, #20 + 8019918: 2203 movs r2, #3 + 801991a: 701a strb r2, [r3, #0] + } + } + } + + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP); + 801991c: 68fb ldr r3, [r7, #12] + 801991e: f103 012a add.w r1, r3, #42 ; 0x2a + 8019922: 79fa ldrb r2, [r7, #7] + 8019924: 4613 mov r3, r2 + 8019926: 005b lsls r3, r3, #1 + 8019928: 4413 add r3, r2 + 801992a: 00db lsls r3, r3, #3 + 801992c: 3308 adds r3, #8 + 801992e: 4a08 ldr r2, [pc, #32] ; (8019950 ) + 8019930: 4413 add r3, r2 + 8019932: 3304 adds r3, #4 + 8019934: f44f 6200 mov.w r2, #2048 ; 0x800 + 8019938: 9200 str r2, [sp, #0] + 801993a: 460a mov r2, r1 + 801993c: 68b9 ldr r1, [r7, #8] + 801993e: 68f8 ldr r0, [r7, #12] + 8019940: f002 f818 bl 801b974 + 8019944: 4603 mov r3, r0 +} + 8019946: 4618 mov r0, r3 + 8019948: 3710 adds r7, #16 + 801994a: 46bd mov sp, r7 + 801994c: bd80 pop {r7, pc} + 801994e: bf00 nop + 8019950: 2000cfd0 .word 0x2000cfd0 + 8019954: 08021120 .word 0x08021120 + 8019958: 08021290 .word 0x08021290 + 801995c: 08021198 .word 0x08021198 + +08019960 : + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or ethernet_output(). + */ +err_t +etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) +{ + 8019960: b580 push {r7, lr} + 8019962: b08a sub sp, #40 ; 0x28 + 8019964: af02 add r7, sp, #8 + 8019966: 60f8 str r0, [r7, #12] + 8019968: 60b9 str r1, [r7, #8] + 801996a: 607a str r2, [r7, #4] + const struct eth_addr *dest; + struct eth_addr mcastaddr; + const ip4_addr_t *dst_addr = ipaddr; + 801996c: 687b ldr r3, [r7, #4] + 801996e: 61bb str r3, [r7, #24] + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + 8019970: 68fb ldr r3, [r7, #12] + 8019972: 2b00 cmp r3, #0 + 8019974: d106 bne.n 8019984 + 8019976: 4b73 ldr r3, [pc, #460] ; (8019b44 ) + 8019978: f240 321e movw r2, #798 ; 0x31e + 801997c: 4972 ldr r1, [pc, #456] ; (8019b48 ) + 801997e: 4873 ldr r0, [pc, #460] ; (8019b4c ) + 8019980: f002 fb48 bl 801c014 + LWIP_ASSERT("q != NULL", q != NULL); + 8019984: 68bb ldr r3, [r7, #8] + 8019986: 2b00 cmp r3, #0 + 8019988: d106 bne.n 8019998 + 801998a: 4b6e ldr r3, [pc, #440] ; (8019b44 ) + 801998c: f240 321f movw r2, #799 ; 0x31f + 8019990: 496f ldr r1, [pc, #444] ; (8019b50 ) + 8019992: 486e ldr r0, [pc, #440] ; (8019b4c ) + 8019994: f002 fb3e bl 801c014 + LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); + 8019998: 687b ldr r3, [r7, #4] + 801999a: 2b00 cmp r3, #0 + 801999c: d106 bne.n 80199ac + 801999e: 4b69 ldr r3, [pc, #420] ; (8019b44 ) + 80199a0: f44f 7248 mov.w r2, #800 ; 0x320 + 80199a4: 496b ldr r1, [pc, #428] ; (8019b54 ) + 80199a6: 4869 ldr r0, [pc, #420] ; (8019b4c ) + 80199a8: f002 fb34 bl 801c014 + + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip4_addr_isbroadcast(ipaddr, netif)) { + 80199ac: 687b ldr r3, [r7, #4] + 80199ae: 681b ldr r3, [r3, #0] + 80199b0: 68f9 ldr r1, [r7, #12] + 80199b2: 4618 mov r0, r3 + 80199b4: f000 ff16 bl 801a7e4 + 80199b8: 4603 mov r3, r0 + 80199ba: 2b00 cmp r3, #0 + 80199bc: d002 beq.n 80199c4 + /* broadcast on Ethernet also */ + dest = (const struct eth_addr *)ðbroadcast; + 80199be: 4b66 ldr r3, [pc, #408] ; (8019b58 ) + 80199c0: 61fb str r3, [r7, #28] + 80199c2: e0af b.n 8019b24 + /* multicast destination IP address? */ + } else if (ip4_addr_ismulticast(ipaddr)) { + 80199c4: 687b ldr r3, [r7, #4] + 80199c6: 681b ldr r3, [r3, #0] + 80199c8: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80199cc: 2be0 cmp r3, #224 ; 0xe0 + 80199ce: d118 bne.n 8019a02 + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0; + 80199d0: 2301 movs r3, #1 + 80199d2: 743b strb r3, [r7, #16] + mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1; + 80199d4: 2300 movs r3, #0 + 80199d6: 747b strb r3, [r7, #17] + mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2; + 80199d8: 235e movs r3, #94 ; 0x5e + 80199da: 74bb strb r3, [r7, #18] + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + 80199dc: 687b ldr r3, [r7, #4] + 80199de: 3301 adds r3, #1 + 80199e0: 781b ldrb r3, [r3, #0] + 80199e2: f003 037f and.w r3, r3, #127 ; 0x7f + 80199e6: b2db uxtb r3, r3 + 80199e8: 74fb strb r3, [r7, #19] + mcastaddr.addr[4] = ip4_addr3(ipaddr); + 80199ea: 687b ldr r3, [r7, #4] + 80199ec: 3302 adds r3, #2 + 80199ee: 781b ldrb r3, [r3, #0] + 80199f0: 753b strb r3, [r7, #20] + mcastaddr.addr[5] = ip4_addr4(ipaddr); + 80199f2: 687b ldr r3, [r7, #4] + 80199f4: 3303 adds r3, #3 + 80199f6: 781b ldrb r3, [r3, #0] + 80199f8: 757b strb r3, [r7, #21] + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + 80199fa: f107 0310 add.w r3, r7, #16 + 80199fe: 61fb str r3, [r7, #28] + 8019a00: e090 b.n 8019b24 + /* unicast destination IP address? */ + } else { + netif_addr_idx_t i; + /* outside local network? if so, this can neither be a global broadcast nor + a subnet broadcast. */ + if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && + 8019a02: 687b ldr r3, [r7, #4] + 8019a04: 681a ldr r2, [r3, #0] + 8019a06: 68fb ldr r3, [r7, #12] + 8019a08: 3304 adds r3, #4 + 8019a0a: 681b ldr r3, [r3, #0] + 8019a0c: 405a eors r2, r3 + 8019a0e: 68fb ldr r3, [r7, #12] + 8019a10: 3308 adds r3, #8 + 8019a12: 681b ldr r3, [r3, #0] + 8019a14: 4013 ands r3, r2 + 8019a16: 2b00 cmp r3, #0 + 8019a18: d012 beq.n 8019a40 + !ip4_addr_islinklocal(ipaddr)) { + 8019a1a: 687b ldr r3, [r7, #4] + 8019a1c: 681b ldr r3, [r3, #0] + 8019a1e: b29b uxth r3, r3 + if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && + 8019a20: f64f 62a9 movw r2, #65193 ; 0xfea9 + 8019a24: 4293 cmp r3, r2 + 8019a26: d00b beq.n 8019a40 + dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr); + if (dst_addr == NULL) +#endif /* LWIP_HOOK_ETHARP_GET_GW */ + { + /* interface has default gateway? */ + if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) { + 8019a28: 68fb ldr r3, [r7, #12] + 8019a2a: 330c adds r3, #12 + 8019a2c: 681b ldr r3, [r3, #0] + 8019a2e: 2b00 cmp r3, #0 + 8019a30: d003 beq.n 8019a3a + /* send to hardware address of default gateway IP address */ + dst_addr = netif_ip4_gw(netif); + 8019a32: 68fb ldr r3, [r7, #12] + 8019a34: 330c adds r3, #12 + 8019a36: 61bb str r3, [r7, #24] + 8019a38: e002 b.n 8019a40 + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + 8019a3a: f06f 0303 mvn.w r3, #3 + 8019a3e: e07d b.n 8019b3c + if (netif->hints != NULL) { + /* per-pcb cached entry was given */ + netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint; + if (etharp_cached_entry < ARP_TABLE_SIZE) { +#endif /* LWIP_NETIF_HWADDRHINT */ + if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && + 8019a40: 4b46 ldr r3, [pc, #280] ; (8019b5c ) + 8019a42: 781b ldrb r3, [r3, #0] + 8019a44: 4619 mov r1, r3 + 8019a46: 4a46 ldr r2, [pc, #280] ; (8019b60 ) + 8019a48: 460b mov r3, r1 + 8019a4a: 005b lsls r3, r3, #1 + 8019a4c: 440b add r3, r1 + 8019a4e: 00db lsls r3, r3, #3 + 8019a50: 4413 add r3, r2 + 8019a52: 3314 adds r3, #20 + 8019a54: 781b ldrb r3, [r3, #0] + 8019a56: 2b01 cmp r3, #1 + 8019a58: d925 bls.n 8019aa6 +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[etharp_cached_entry].netif == netif) && + 8019a5a: 4b40 ldr r3, [pc, #256] ; (8019b5c ) + 8019a5c: 781b ldrb r3, [r3, #0] + 8019a5e: 4619 mov r1, r3 + 8019a60: 4a3f ldr r2, [pc, #252] ; (8019b60 ) + 8019a62: 460b mov r3, r1 + 8019a64: 005b lsls r3, r3, #1 + 8019a66: 440b add r3, r1 + 8019a68: 00db lsls r3, r3, #3 + 8019a6a: 4413 add r3, r2 + 8019a6c: 3308 adds r3, #8 + 8019a6e: 681b ldr r3, [r3, #0] + if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && + 8019a70: 68fa ldr r2, [r7, #12] + 8019a72: 429a cmp r2, r3 + 8019a74: d117 bne.n 8019aa6 +#endif + (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) { + 8019a76: 69bb ldr r3, [r7, #24] + 8019a78: 681a ldr r2, [r3, #0] + 8019a7a: 4b38 ldr r3, [pc, #224] ; (8019b5c ) + 8019a7c: 781b ldrb r3, [r3, #0] + 8019a7e: 4618 mov r0, r3 + 8019a80: 4937 ldr r1, [pc, #220] ; (8019b60 ) + 8019a82: 4603 mov r3, r0 + 8019a84: 005b lsls r3, r3, #1 + 8019a86: 4403 add r3, r0 + 8019a88: 00db lsls r3, r3, #3 + 8019a8a: 440b add r3, r1 + 8019a8c: 3304 adds r3, #4 + 8019a8e: 681b ldr r3, [r3, #0] + (arp_table[etharp_cached_entry].netif == netif) && + 8019a90: 429a cmp r2, r3 + 8019a92: d108 bne.n 8019aa6 + /* the per-pcb-cached entry is stable and the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return etharp_output_to_arp_index(netif, q, etharp_cached_entry); + 8019a94: 4b31 ldr r3, [pc, #196] ; (8019b5c ) + 8019a96: 781b ldrb r3, [r3, #0] + 8019a98: 461a mov r2, r3 + 8019a9a: 68b9 ldr r1, [r7, #8] + 8019a9c: 68f8 ldr r0, [r7, #12] + 8019a9e: f7ff fec5 bl 801982c + 8019aa2: 4603 mov r3, r0 + 8019aa4: e04a b.n 8019b3c + } +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* find stable entry: do this here since this is a critical path for + throughput and etharp_find_entry() is kind of slow */ + for (i = 0; i < ARP_TABLE_SIZE; i++) { + 8019aa6: 2300 movs r3, #0 + 8019aa8: 75fb strb r3, [r7, #23] + 8019aaa: e031 b.n 8019b10 + if ((arp_table[i].state >= ETHARP_STATE_STABLE) && + 8019aac: 7dfa ldrb r2, [r7, #23] + 8019aae: 492c ldr r1, [pc, #176] ; (8019b60 ) + 8019ab0: 4613 mov r3, r2 + 8019ab2: 005b lsls r3, r3, #1 + 8019ab4: 4413 add r3, r2 + 8019ab6: 00db lsls r3, r3, #3 + 8019ab8: 440b add r3, r1 + 8019aba: 3314 adds r3, #20 + 8019abc: 781b ldrb r3, [r3, #0] + 8019abe: 2b01 cmp r3, #1 + 8019ac0: d923 bls.n 8019b0a +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[i].netif == netif) && + 8019ac2: 7dfa ldrb r2, [r7, #23] + 8019ac4: 4926 ldr r1, [pc, #152] ; (8019b60 ) + 8019ac6: 4613 mov r3, r2 + 8019ac8: 005b lsls r3, r3, #1 + 8019aca: 4413 add r3, r2 + 8019acc: 00db lsls r3, r3, #3 + 8019ace: 440b add r3, r1 + 8019ad0: 3308 adds r3, #8 + 8019ad2: 681b ldr r3, [r3, #0] + if ((arp_table[i].state >= ETHARP_STATE_STABLE) && + 8019ad4: 68fa ldr r2, [r7, #12] + 8019ad6: 429a cmp r2, r3 + 8019ad8: d117 bne.n 8019b0a +#endif + (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) { + 8019ada: 69bb ldr r3, [r7, #24] + 8019adc: 6819 ldr r1, [r3, #0] + 8019ade: 7dfa ldrb r2, [r7, #23] + 8019ae0: 481f ldr r0, [pc, #124] ; (8019b60 ) + 8019ae2: 4613 mov r3, r2 + 8019ae4: 005b lsls r3, r3, #1 + 8019ae6: 4413 add r3, r2 + 8019ae8: 00db lsls r3, r3, #3 + 8019aea: 4403 add r3, r0 + 8019aec: 3304 adds r3, #4 + 8019aee: 681b ldr r3, [r3, #0] + (arp_table[i].netif == netif) && + 8019af0: 4299 cmp r1, r3 + 8019af2: d10a bne.n 8019b0a + /* found an existing, stable entry */ + ETHARP_SET_ADDRHINT(netif, i); + 8019af4: 4a19 ldr r2, [pc, #100] ; (8019b5c ) + 8019af6: 7dfb ldrb r3, [r7, #23] + 8019af8: 7013 strb r3, [r2, #0] + return etharp_output_to_arp_index(netif, q, i); + 8019afa: 7dfb ldrb r3, [r7, #23] + 8019afc: 461a mov r2, r3 + 8019afe: 68b9 ldr r1, [r7, #8] + 8019b00: 68f8 ldr r0, [r7, #12] + 8019b02: f7ff fe93 bl 801982c + 8019b06: 4603 mov r3, r0 + 8019b08: e018 b.n 8019b3c + for (i = 0; i < ARP_TABLE_SIZE; i++) { + 8019b0a: 7dfb ldrb r3, [r7, #23] + 8019b0c: 3301 adds r3, #1 + 8019b0e: 75fb strb r3, [r7, #23] + 8019b10: 7dfb ldrb r3, [r7, #23] + 8019b12: 2b09 cmp r3, #9 + 8019b14: d9ca bls.n 8019aac + } + } + /* no stable entry found, use the (slower) query function: + queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, dst_addr, q); + 8019b16: 68ba ldr r2, [r7, #8] + 8019b18: 69b9 ldr r1, [r7, #24] + 8019b1a: 68f8 ldr r0, [r7, #12] + 8019b1c: f000 f822 bl 8019b64 + 8019b20: 4603 mov r3, r0 + 8019b22: e00b b.n 8019b3c + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + /* send packet directly on the link */ + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP); + 8019b24: 68fb ldr r3, [r7, #12] + 8019b26: f103 022a add.w r2, r3, #42 ; 0x2a + 8019b2a: f44f 6300 mov.w r3, #2048 ; 0x800 + 8019b2e: 9300 str r3, [sp, #0] + 8019b30: 69fb ldr r3, [r7, #28] + 8019b32: 68b9 ldr r1, [r7, #8] + 8019b34: 68f8 ldr r0, [r7, #12] + 8019b36: f001 ff1d bl 801b974 + 8019b3a: 4603 mov r3, r0 +} + 8019b3c: 4618 mov r0, r3 + 8019b3e: 3720 adds r7, #32 + 8019b40: 46bd mov sp, r7 + 8019b42: bd80 pop {r7, pc} + 8019b44: 08021120 .word 0x08021120 + 8019b48: 08021270 .word 0x08021270 + 8019b4c: 08021198 .word 0x08021198 + 8019b50: 080212c0 .word 0x080212c0 + 8019b54: 08021260 .word 0x08021260 + 8019b58: 0802391c .word 0x0802391c + 8019b5c: 2000d0c0 .word 0x2000d0c0 + 8019b60: 2000cfd0 .word 0x2000cfd0 + +08019b64 : + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t +etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q) +{ + 8019b64: b580 push {r7, lr} + 8019b66: b08c sub sp, #48 ; 0x30 + 8019b68: af02 add r7, sp, #8 + 8019b6a: 60f8 str r0, [r7, #12] + 8019b6c: 60b9 str r1, [r7, #8] + 8019b6e: 607a str r2, [r7, #4] + struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr; + 8019b70: 68fb ldr r3, [r7, #12] + 8019b72: 332a adds r3, #42 ; 0x2a + 8019b74: 617b str r3, [r7, #20] + err_t result = ERR_MEM; + 8019b76: 23ff movs r3, #255 ; 0xff + 8019b78: f887 3027 strb.w r3, [r7, #39] ; 0x27 + int is_new_entry = 0; + 8019b7c: 2300 movs r3, #0 + 8019b7e: 623b str r3, [r7, #32] + s16_t i_err; + netif_addr_idx_t i; + + /* non-unicast address? */ + if (ip4_addr_isbroadcast(ipaddr, netif) || + 8019b80: 68bb ldr r3, [r7, #8] + 8019b82: 681b ldr r3, [r3, #0] + 8019b84: 68f9 ldr r1, [r7, #12] + 8019b86: 4618 mov r0, r3 + 8019b88: f000 fe2c bl 801a7e4 + 8019b8c: 4603 mov r3, r0 + 8019b8e: 2b00 cmp r3, #0 + 8019b90: d10c bne.n 8019bac + ip4_addr_ismulticast(ipaddr) || + 8019b92: 68bb ldr r3, [r7, #8] + 8019b94: 681b ldr r3, [r3, #0] + 8019b96: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (ip4_addr_isbroadcast(ipaddr, netif) || + 8019b9a: 2be0 cmp r3, #224 ; 0xe0 + 8019b9c: d006 beq.n 8019bac + ip4_addr_ismulticast(ipaddr) || + 8019b9e: 68bb ldr r3, [r7, #8] + 8019ba0: 2b00 cmp r3, #0 + 8019ba2: d003 beq.n 8019bac + ip4_addr_isany(ipaddr)) { + 8019ba4: 68bb ldr r3, [r7, #8] + 8019ba6: 681b ldr r3, [r3, #0] + 8019ba8: 2b00 cmp r3, #0 + 8019baa: d102 bne.n 8019bb2 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + 8019bac: f06f 030f mvn.w r3, #15 + 8019bb0: e101 b.n 8019db6 + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif); + 8019bb2: 68fa ldr r2, [r7, #12] + 8019bb4: 2101 movs r1, #1 + 8019bb6: 68b8 ldr r0, [r7, #8] + 8019bb8: f7ff fb5c bl 8019274 + 8019bbc: 4603 mov r3, r0 + 8019bbe: 827b strh r3, [r7, #18] + + /* could not find or create entry? */ + if (i_err < 0) { + 8019bc0: f9b7 3012 ldrsh.w r3, [r7, #18] + 8019bc4: 2b00 cmp r3, #0 + 8019bc6: da02 bge.n 8019bce + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); + ETHARP_STATS_INC(etharp.memerr); + } + return (err_t)i_err; + 8019bc8: 8a7b ldrh r3, [r7, #18] + 8019bca: b25b sxtb r3, r3 + 8019bcc: e0f3 b.n 8019db6 + } + LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX); + 8019bce: 8a7b ldrh r3, [r7, #18] + 8019bd0: 2b7e cmp r3, #126 ; 0x7e + 8019bd2: d906 bls.n 8019be2 + 8019bd4: 4b7a ldr r3, [pc, #488] ; (8019dc0 ) + 8019bd6: f240 32c1 movw r2, #961 ; 0x3c1 + 8019bda: 497a ldr r1, [pc, #488] ; (8019dc4 ) + 8019bdc: 487a ldr r0, [pc, #488] ; (8019dc8 ) + 8019bde: f002 fa19 bl 801c014 + i = (netif_addr_idx_t)i_err; + 8019be2: 8a7b ldrh r3, [r7, #18] + 8019be4: 747b strb r3, [r7, #17] + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + 8019be6: 7c7a ldrb r2, [r7, #17] + 8019be8: 4978 ldr r1, [pc, #480] ; (8019dcc ) + 8019bea: 4613 mov r3, r2 + 8019bec: 005b lsls r3, r3, #1 + 8019bee: 4413 add r3, r2 + 8019bf0: 00db lsls r3, r3, #3 + 8019bf2: 440b add r3, r1 + 8019bf4: 3314 adds r3, #20 + 8019bf6: 781b ldrb r3, [r3, #0] + 8019bf8: 2b00 cmp r3, #0 + 8019bfa: d115 bne.n 8019c28 + is_new_entry = 1; + 8019bfc: 2301 movs r3, #1 + 8019bfe: 623b str r3, [r7, #32] + arp_table[i].state = ETHARP_STATE_PENDING; + 8019c00: 7c7a ldrb r2, [r7, #17] + 8019c02: 4972 ldr r1, [pc, #456] ; (8019dcc ) + 8019c04: 4613 mov r3, r2 + 8019c06: 005b lsls r3, r3, #1 + 8019c08: 4413 add r3, r2 + 8019c0a: 00db lsls r3, r3, #3 + 8019c0c: 440b add r3, r1 + 8019c0e: 3314 adds r3, #20 + 8019c10: 2201 movs r2, #1 + 8019c12: 701a strb r2, [r3, #0] + /* record network interface for re-sending arp request in etharp_tmr */ + arp_table[i].netif = netif; + 8019c14: 7c7a ldrb r2, [r7, #17] + 8019c16: 496d ldr r1, [pc, #436] ; (8019dcc ) + 8019c18: 4613 mov r3, r2 + 8019c1a: 005b lsls r3, r3, #1 + 8019c1c: 4413 add r3, r2 + 8019c1e: 00db lsls r3, r3, #3 + 8019c20: 440b add r3, r1 + 8019c22: 3308 adds r3, #8 + 8019c24: 68fa ldr r2, [r7, #12] + 8019c26: 601a str r2, [r3, #0] + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + 8019c28: 7c7a ldrb r2, [r7, #17] + 8019c2a: 4968 ldr r1, [pc, #416] ; (8019dcc ) + 8019c2c: 4613 mov r3, r2 + 8019c2e: 005b lsls r3, r3, #1 + 8019c30: 4413 add r3, r2 + 8019c32: 00db lsls r3, r3, #3 + 8019c34: 440b add r3, r1 + 8019c36: 3314 adds r3, #20 + 8019c38: 781b ldrb r3, [r3, #0] + 8019c3a: 2b01 cmp r3, #1 + 8019c3c: d011 beq.n 8019c62 + 8019c3e: 7c7a ldrb r2, [r7, #17] + 8019c40: 4962 ldr r1, [pc, #392] ; (8019dcc ) + 8019c42: 4613 mov r3, r2 + 8019c44: 005b lsls r3, r3, #1 + 8019c46: 4413 add r3, r2 + 8019c48: 00db lsls r3, r3, #3 + 8019c4a: 440b add r3, r1 + 8019c4c: 3314 adds r3, #20 + 8019c4e: 781b ldrb r3, [r3, #0] + 8019c50: 2b01 cmp r3, #1 + 8019c52: d806 bhi.n 8019c62 + 8019c54: 4b5a ldr r3, [pc, #360] ; (8019dc0 ) + 8019c56: f240 32cd movw r2, #973 ; 0x3cd + 8019c5a: 495d ldr r1, [pc, #372] ; (8019dd0 ) + 8019c5c: 485a ldr r0, [pc, #360] ; (8019dc8 ) + 8019c5e: f002 f9d9 bl 801c014 + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state >= ETHARP_STATE_STABLE))); + + /* do we have a new entry? or an implicit query request? */ + if (is_new_entry || (q == NULL)) { + 8019c62: 6a3b ldr r3, [r7, #32] + 8019c64: 2b00 cmp r3, #0 + 8019c66: d102 bne.n 8019c6e + 8019c68: 687b ldr r3, [r7, #4] + 8019c6a: 2b00 cmp r3, #0 + 8019c6c: d10c bne.n 8019c88 + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + 8019c6e: 68b9 ldr r1, [r7, #8] + 8019c70: 68f8 ldr r0, [r7, #12] + 8019c72: f000 f963 bl 8019f3c + 8019c76: 4603 mov r3, r0 + 8019c78: f887 3027 strb.w r3, [r7, #39] ; 0x27 + /* ARP request couldn't be sent */ + /* We don't re-send arp request in etharp_tmr, but we still queue packets, + since this failure could be temporary, and the next packet calling + etharp_query again could lead to sending the queued packets. */ + } + if (q == NULL) { + 8019c7c: 687b ldr r3, [r7, #4] + 8019c7e: 2b00 cmp r3, #0 + 8019c80: d102 bne.n 8019c88 + return result; + 8019c82: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 8019c86: e096 b.n 8019db6 + } + } + + /* packet given? */ + LWIP_ASSERT("q != NULL", q != NULL); + 8019c88: 687b ldr r3, [r7, #4] + 8019c8a: 2b00 cmp r3, #0 + 8019c8c: d106 bne.n 8019c9c + 8019c8e: 4b4c ldr r3, [pc, #304] ; (8019dc0 ) + 8019c90: f240 32e1 movw r2, #993 ; 0x3e1 + 8019c94: 494f ldr r1, [pc, #316] ; (8019dd4 ) + 8019c96: 484c ldr r0, [pc, #304] ; (8019dc8 ) + 8019c98: f002 f9bc bl 801c014 + /* stable entry? */ + if (arp_table[i].state >= ETHARP_STATE_STABLE) { + 8019c9c: 7c7a ldrb r2, [r7, #17] + 8019c9e: 494b ldr r1, [pc, #300] ; (8019dcc ) + 8019ca0: 4613 mov r3, r2 + 8019ca2: 005b lsls r3, r3, #1 + 8019ca4: 4413 add r3, r2 + 8019ca6: 00db lsls r3, r3, #3 + 8019ca8: 440b add r3, r1 + 8019caa: 3314 adds r3, #20 + 8019cac: 781b ldrb r3, [r3, #0] + 8019cae: 2b01 cmp r3, #1 + 8019cb0: d917 bls.n 8019ce2 + /* we have a valid IP->Ethernet address mapping */ + ETHARP_SET_ADDRHINT(netif, i); + 8019cb2: 4a49 ldr r2, [pc, #292] ; (8019dd8 ) + 8019cb4: 7c7b ldrb r3, [r7, #17] + 8019cb6: 7013 strb r3, [r2, #0] + /* send the packet */ + result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP); + 8019cb8: 7c7a ldrb r2, [r7, #17] + 8019cba: 4613 mov r3, r2 + 8019cbc: 005b lsls r3, r3, #1 + 8019cbe: 4413 add r3, r2 + 8019cc0: 00db lsls r3, r3, #3 + 8019cc2: 3308 adds r3, #8 + 8019cc4: 4a41 ldr r2, [pc, #260] ; (8019dcc ) + 8019cc6: 4413 add r3, r2 + 8019cc8: 3304 adds r3, #4 + 8019cca: f44f 6200 mov.w r2, #2048 ; 0x800 + 8019cce: 9200 str r2, [sp, #0] + 8019cd0: 697a ldr r2, [r7, #20] + 8019cd2: 6879 ldr r1, [r7, #4] + 8019cd4: 68f8 ldr r0, [r7, #12] + 8019cd6: f001 fe4d bl 801b974 + 8019cda: 4603 mov r3, r0 + 8019cdc: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8019ce0: e067 b.n 8019db2 + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + 8019ce2: 7c7a ldrb r2, [r7, #17] + 8019ce4: 4939 ldr r1, [pc, #228] ; (8019dcc ) + 8019ce6: 4613 mov r3, r2 + 8019ce8: 005b lsls r3, r3, #1 + 8019cea: 4413 add r3, r2 + 8019cec: 00db lsls r3, r3, #3 + 8019cee: 440b add r3, r1 + 8019cf0: 3314 adds r3, #20 + 8019cf2: 781b ldrb r3, [r3, #0] + 8019cf4: 2b01 cmp r3, #1 + 8019cf6: d15c bne.n 8019db2 + /* entry is still pending, queue the given packet 'q' */ + struct pbuf *p; + int copy_needed = 0; + 8019cf8: 2300 movs r3, #0 + 8019cfa: 61bb str r3, [r7, #24] + /* IF q includes a pbuf that must be copied, copy the whole chain into a + * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */ + p = q; + 8019cfc: 687b ldr r3, [r7, #4] + 8019cfe: 61fb str r3, [r7, #28] + while (p) { + 8019d00: e01c b.n 8019d3c + LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); + 8019d02: 69fb ldr r3, [r7, #28] + 8019d04: 895a ldrh r2, [r3, #10] + 8019d06: 69fb ldr r3, [r7, #28] + 8019d08: 891b ldrh r3, [r3, #8] + 8019d0a: 429a cmp r2, r3 + 8019d0c: d10a bne.n 8019d24 + 8019d0e: 69fb ldr r3, [r7, #28] + 8019d10: 681b ldr r3, [r3, #0] + 8019d12: 2b00 cmp r3, #0 + 8019d14: d006 beq.n 8019d24 + 8019d16: 4b2a ldr r3, [pc, #168] ; (8019dc0 ) + 8019d18: f240 32f1 movw r2, #1009 ; 0x3f1 + 8019d1c: 492f ldr r1, [pc, #188] ; (8019ddc ) + 8019d1e: 482a ldr r0, [pc, #168] ; (8019dc8 ) + 8019d20: f002 f978 bl 801c014 + if (PBUF_NEEDS_COPY(p)) { + 8019d24: 69fb ldr r3, [r7, #28] + 8019d26: 7b1b ldrb r3, [r3, #12] + 8019d28: f003 0340 and.w r3, r3, #64 ; 0x40 + 8019d2c: 2b00 cmp r3, #0 + 8019d2e: d002 beq.n 8019d36 + copy_needed = 1; + 8019d30: 2301 movs r3, #1 + 8019d32: 61bb str r3, [r7, #24] + break; + 8019d34: e005 b.n 8019d42 + } + p = p->next; + 8019d36: 69fb ldr r3, [r7, #28] + 8019d38: 681b ldr r3, [r3, #0] + 8019d3a: 61fb str r3, [r7, #28] + while (p) { + 8019d3c: 69fb ldr r3, [r7, #28] + 8019d3e: 2b00 cmp r3, #0 + 8019d40: d1df bne.n 8019d02 + } + if (copy_needed) { + 8019d42: 69bb ldr r3, [r7, #24] + 8019d44: 2b00 cmp r3, #0 + 8019d46: d007 beq.n 8019d58 + /* copy the whole packet into new pbufs */ + p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); + 8019d48: 687a ldr r2, [r7, #4] + 8019d4a: f44f 7120 mov.w r1, #640 ; 0x280 + 8019d4e: 200e movs r0, #14 + 8019d50: f7f7 fa06 bl 8011160 + 8019d54: 61f8 str r0, [r7, #28] + 8019d56: e004 b.n 8019d62 + } else { + /* referencing the old pbuf is enough */ + p = q; + 8019d58: 687b ldr r3, [r7, #4] + 8019d5a: 61fb str r3, [r7, #28] + pbuf_ref(p); + 8019d5c: 69f8 ldr r0, [r7, #28] + 8019d5e: f7f6 fef5 bl 8010b4c + } + /* packet could be taken over? */ + if (p != NULL) { + 8019d62: 69fb ldr r3, [r7, #28] + 8019d64: 2b00 cmp r3, #0 + 8019d66: d021 beq.n 8019dac + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } +#else /* ARP_QUEUEING */ + /* always queue one packet per ARP request only, freeing a previously queued packet */ + if (arp_table[i].q != NULL) { + 8019d68: 7c7a ldrb r2, [r7, #17] + 8019d6a: 4918 ldr r1, [pc, #96] ; (8019dcc ) + 8019d6c: 4613 mov r3, r2 + 8019d6e: 005b lsls r3, r3, #1 + 8019d70: 4413 add r3, r2 + 8019d72: 00db lsls r3, r3, #3 + 8019d74: 440b add r3, r1 + 8019d76: 681b ldr r3, [r3, #0] + 8019d78: 2b00 cmp r3, #0 + 8019d7a: d00a beq.n 8019d92 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); + pbuf_free(arp_table[i].q); + 8019d7c: 7c7a ldrb r2, [r7, #17] + 8019d7e: 4913 ldr r1, [pc, #76] ; (8019dcc ) + 8019d80: 4613 mov r3, r2 + 8019d82: 005b lsls r3, r3, #1 + 8019d84: 4413 add r3, r2 + 8019d86: 00db lsls r3, r3, #3 + 8019d88: 440b add r3, r1 + 8019d8a: 681b ldr r3, [r3, #0] + 8019d8c: 4618 mov r0, r3 + 8019d8e: f7f6 fe37 bl 8010a00 + } + arp_table[i].q = p; + 8019d92: 7c7a ldrb r2, [r7, #17] + 8019d94: 490d ldr r1, [pc, #52] ; (8019dcc ) + 8019d96: 4613 mov r3, r2 + 8019d98: 005b lsls r3, r3, #1 + 8019d9a: 4413 add r3, r2 + 8019d9c: 00db lsls r3, r3, #3 + 8019d9e: 440b add r3, r1 + 8019da0: 69fa ldr r2, [r7, #28] + 8019da2: 601a str r2, [r3, #0] + result = ERR_OK; + 8019da4: 2300 movs r3, #0 + 8019da6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8019daa: e002 b.n 8019db2 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); +#endif /* ARP_QUEUEING */ + } else { + ETHARP_STATS_INC(etharp.memerr); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + 8019dac: 23ff movs r3, #255 ; 0xff + 8019dae: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + } + return result; + 8019db2: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 +} + 8019db6: 4618 mov r0, r3 + 8019db8: 3728 adds r7, #40 ; 0x28 + 8019dba: 46bd mov sp, r7 + 8019dbc: bd80 pop {r7, pc} + 8019dbe: bf00 nop + 8019dc0: 08021120 .word 0x08021120 + 8019dc4: 080212cc .word 0x080212cc + 8019dc8: 08021198 .word 0x08021198 + 8019dcc: 2000cfd0 .word 0x2000cfd0 + 8019dd0: 080212dc .word 0x080212dc + 8019dd4: 080212c0 .word 0x080212c0 + 8019dd8: 2000d0c0 .word 0x2000d0c0 + 8019ddc: 08021304 .word 0x08021304 + +08019de0 : +etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, + const u16_t opcode) +{ + 8019de0: b580 push {r7, lr} + 8019de2: b08a sub sp, #40 ; 0x28 + 8019de4: af02 add r7, sp, #8 + 8019de6: 60f8 str r0, [r7, #12] + 8019de8: 60b9 str r1, [r7, #8] + 8019dea: 607a str r2, [r7, #4] + 8019dec: 603b str r3, [r7, #0] + struct pbuf *p; + err_t result = ERR_OK; + 8019dee: 2300 movs r3, #0 + 8019df0: 77fb strb r3, [r7, #31] + struct etharp_hdr *hdr; + + LWIP_ASSERT("netif != NULL", netif != NULL); + 8019df2: 68fb ldr r3, [r7, #12] + 8019df4: 2b00 cmp r3, #0 + 8019df6: d106 bne.n 8019e06 + 8019df8: 4b3a ldr r3, [pc, #232] ; (8019ee4 ) + 8019dfa: f240 4257 movw r2, #1111 ; 0x457 + 8019dfe: 493a ldr r1, [pc, #232] ; (8019ee8 ) + 8019e00: 483a ldr r0, [pc, #232] ; (8019eec ) + 8019e02: f002 f907 bl 801c014 + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM); + 8019e06: f44f 7220 mov.w r2, #640 ; 0x280 + 8019e0a: 211c movs r1, #28 + 8019e0c: 200e movs r0, #14 + 8019e0e: f7f6 fb13 bl 8010438 + 8019e12: 61b8 str r0, [r7, #24] + /* could allocate a pbuf for an ARP request? */ + if (p == NULL) { + 8019e14: 69bb ldr r3, [r7, #24] + 8019e16: 2b00 cmp r3, #0 + 8019e18: d102 bne.n 8019e20 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_raw: could not allocate pbuf for ARP request.\n")); + ETHARP_STATS_INC(etharp.memerr); + return ERR_MEM; + 8019e1a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8019e1e: e05d b.n 8019edc + } + LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", + 8019e20: 69bb ldr r3, [r7, #24] + 8019e22: 895b ldrh r3, [r3, #10] + 8019e24: 2b1b cmp r3, #27 + 8019e26: d806 bhi.n 8019e36 + 8019e28: 4b2e ldr r3, [pc, #184] ; (8019ee4 ) + 8019e2a: f240 4262 movw r2, #1122 ; 0x462 + 8019e2e: 4930 ldr r1, [pc, #192] ; (8019ef0 ) + 8019e30: 482e ldr r0, [pc, #184] ; (8019eec ) + 8019e32: f002 f8ef bl 801c014 + (p->len >= SIZEOF_ETHARP_HDR)); + + hdr = (struct etharp_hdr *)p->payload; + 8019e36: 69bb ldr r3, [r7, #24] + 8019e38: 685b ldr r3, [r3, #4] + 8019e3a: 617b str r3, [r7, #20] + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); + hdr->opcode = lwip_htons(opcode); + 8019e3c: 8ebb ldrh r3, [r7, #52] ; 0x34 + 8019e3e: 4618 mov r0, r3 + 8019e40: f7f4 f9f6 bl 800e230 + 8019e44: 4603 mov r3, r0 + 8019e46: 461a mov r2, r3 + 8019e48: 697b ldr r3, [r7, #20] + 8019e4a: 80da strh r2, [r3, #6] + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!", + 8019e4c: 68fb ldr r3, [r7, #12] + 8019e4e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8019e52: 2b06 cmp r3, #6 + 8019e54: d006 beq.n 8019e64 + 8019e56: 4b23 ldr r3, [pc, #140] ; (8019ee4 ) + 8019e58: f240 4269 movw r2, #1129 ; 0x469 + 8019e5c: 4925 ldr r1, [pc, #148] ; (8019ef4 ) + 8019e5e: 4823 ldr r0, [pc, #140] ; (8019eec ) + 8019e60: f002 f8d8 bl 801c014 + (netif->hwaddr_len == ETH_HWADDR_LEN)); + + /* Write the ARP MAC-Addresses */ + SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN); + 8019e64: 697b ldr r3, [r7, #20] + 8019e66: 3308 adds r3, #8 + 8019e68: 2206 movs r2, #6 + 8019e6a: 6839 ldr r1, [r7, #0] + 8019e6c: 4618 mov r0, r3 + 8019e6e: f002 f80c bl 801be8a + SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN); + 8019e72: 697b ldr r3, [r7, #20] + 8019e74: 3312 adds r3, #18 + 8019e76: 2206 movs r2, #6 + 8019e78: 6af9 ldr r1, [r7, #44] ; 0x2c + 8019e7a: 4618 mov r0, r3 + 8019e7c: f002 f805 bl 801be8a + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing. */ + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr); + 8019e80: 697b ldr r3, [r7, #20] + 8019e82: 330e adds r3, #14 + 8019e84: 6aba ldr r2, [r7, #40] ; 0x28 + 8019e86: 6812 ldr r2, [r2, #0] + 8019e88: 601a str r2, [r3, #0] + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr); + 8019e8a: 697b ldr r3, [r7, #20] + 8019e8c: 3318 adds r3, #24 + 8019e8e: 6b3a ldr r2, [r7, #48] ; 0x30 + 8019e90: 6812 ldr r2, [r2, #0] + 8019e92: 601a str r2, [r3, #0] + + hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET); + 8019e94: 697b ldr r3, [r7, #20] + 8019e96: 2200 movs r2, #0 + 8019e98: 701a strb r2, [r3, #0] + 8019e9a: 2200 movs r2, #0 + 8019e9c: f042 0201 orr.w r2, r2, #1 + 8019ea0: 705a strb r2, [r3, #1] + hdr->proto = PP_HTONS(ETHTYPE_IP); + 8019ea2: 697b ldr r3, [r7, #20] + 8019ea4: 2200 movs r2, #0 + 8019ea6: f042 0208 orr.w r2, r2, #8 + 8019eaa: 709a strb r2, [r3, #2] + 8019eac: 2200 movs r2, #0 + 8019eae: 70da strb r2, [r3, #3] + /* set hwlen and protolen */ + hdr->hwlen = ETH_HWADDR_LEN; + 8019eb0: 697b ldr r3, [r7, #20] + 8019eb2: 2206 movs r2, #6 + 8019eb4: 711a strb r2, [r3, #4] + hdr->protolen = sizeof(ip4_addr_t); + 8019eb6: 697b ldr r3, [r7, #20] + 8019eb8: 2204 movs r2, #4 + 8019eba: 715a strb r2, [r3, #5] + if (ip4_addr_islinklocal(ipsrc_addr)) { + ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP); + } else +#endif /* LWIP_AUTOIP */ + { + ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP); + 8019ebc: f640 0306 movw r3, #2054 ; 0x806 + 8019ec0: 9300 str r3, [sp, #0] + 8019ec2: 687b ldr r3, [r7, #4] + 8019ec4: 68ba ldr r2, [r7, #8] + 8019ec6: 69b9 ldr r1, [r7, #24] + 8019ec8: 68f8 ldr r0, [r7, #12] + 8019eca: f001 fd53 bl 801b974 + } + + ETHARP_STATS_INC(etharp.xmit); + /* free ARP query packet */ + pbuf_free(p); + 8019ece: 69b8 ldr r0, [r7, #24] + 8019ed0: f7f6 fd96 bl 8010a00 + p = NULL; + 8019ed4: 2300 movs r3, #0 + 8019ed6: 61bb str r3, [r7, #24] + /* could not allocate pbuf for ARP request */ + + return result; + 8019ed8: f997 301f ldrsb.w r3, [r7, #31] +} + 8019edc: 4618 mov r0, r3 + 8019ede: 3720 adds r7, #32 + 8019ee0: 46bd mov sp, r7 + 8019ee2: bd80 pop {r7, pc} + 8019ee4: 08021120 .word 0x08021120 + 8019ee8: 08021270 .word 0x08021270 + 8019eec: 08021198 .word 0x08021198 + 8019ef0: 08021320 .word 0x08021320 + 8019ef4: 08021354 .word 0x08021354 + +08019ef8 : + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +static err_t +etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr) +{ + 8019ef8: b580 push {r7, lr} + 8019efa: b088 sub sp, #32 + 8019efc: af04 add r7, sp, #16 + 8019efe: 60f8 str r0, [r7, #12] + 8019f00: 60b9 str r1, [r7, #8] + 8019f02: 607a str r2, [r7, #4] + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, + 8019f04: 68fb ldr r3, [r7, #12] + 8019f06: f103 012a add.w r1, r3, #42 ; 0x2a + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero, + 8019f0a: 68fb ldr r3, [r7, #12] + 8019f0c: f103 002a add.w r0, r3, #42 ; 0x2a + 8019f10: 68fb ldr r3, [r7, #12] + 8019f12: 3304 adds r3, #4 + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, + 8019f14: 2201 movs r2, #1 + 8019f16: 9203 str r2, [sp, #12] + 8019f18: 68ba ldr r2, [r7, #8] + 8019f1a: 9202 str r2, [sp, #8] + 8019f1c: 4a06 ldr r2, [pc, #24] ; (8019f38 ) + 8019f1e: 9201 str r2, [sp, #4] + 8019f20: 9300 str r3, [sp, #0] + 8019f22: 4603 mov r3, r0 + 8019f24: 687a ldr r2, [r7, #4] + 8019f26: 68f8 ldr r0, [r7, #12] + 8019f28: f7ff ff5a bl 8019de0 + 8019f2c: 4603 mov r3, r0 + ipaddr, ARP_REQUEST); +} + 8019f2e: 4618 mov r0, r3 + 8019f30: 3710 adds r7, #16 + 8019f32: 46bd mov sp, r7 + 8019f34: bd80 pop {r7, pc} + 8019f36: bf00 nop + 8019f38: 08023924 .word 0x08023924 + +08019f3c : + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +err_t +etharp_request(struct netif *netif, const ip4_addr_t *ipaddr) +{ + 8019f3c: b580 push {r7, lr} + 8019f3e: b082 sub sp, #8 + 8019f40: af00 add r7, sp, #0 + 8019f42: 6078 str r0, [r7, #4] + 8019f44: 6039 str r1, [r7, #0] + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); + return etharp_request_dst(netif, ipaddr, ðbroadcast); + 8019f46: 4a05 ldr r2, [pc, #20] ; (8019f5c ) + 8019f48: 6839 ldr r1, [r7, #0] + 8019f4a: 6878 ldr r0, [r7, #4] + 8019f4c: f7ff ffd4 bl 8019ef8 + 8019f50: 4603 mov r3, r0 +} + 8019f52: 4618 mov r0, r3 + 8019f54: 3708 adds r7, #8 + 8019f56: 46bd mov sp, r7 + 8019f58: bd80 pop {r7, pc} + 8019f5a: bf00 nop + 8019f5c: 0802391c .word 0x0802391c + +08019f60 : + * @param p the icmp echo request packet, p->payload pointing to the icmp header + * @param inp the netif on which this packet was received + */ +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + 8019f60: b580 push {r7, lr} + 8019f62: b08e sub sp, #56 ; 0x38 + 8019f64: af04 add r7, sp, #16 + 8019f66: 6078 str r0, [r7, #4] + 8019f68: 6039 str r1, [r7, #0] + const ip4_addr_t *src; + + ICMP_STATS_INC(icmp.recv); + MIB2_STATS_INC(mib2.icmpinmsgs); + + iphdr_in = ip4_current_header(); + 8019f6a: 4b79 ldr r3, [pc, #484] ; (801a150 ) + 8019f6c: 689b ldr r3, [r3, #8] + 8019f6e: 627b str r3, [r7, #36] ; 0x24 + hlen = IPH_HL_BYTES(iphdr_in); + 8019f70: 6a7b ldr r3, [r7, #36] ; 0x24 + 8019f72: 781b ldrb r3, [r3, #0] + 8019f74: f003 030f and.w r3, r3, #15 + 8019f78: b2db uxtb r3, r3 + 8019f7a: 009b lsls r3, r3, #2 + 8019f7c: b2db uxtb r3, r3 + 8019f7e: 847b strh r3, [r7, #34] ; 0x22 + if (hlen < IP_HLEN) { + 8019f80: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8019f82: 2b13 cmp r3, #19 + 8019f84: f240 80cd bls.w 801a122 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen)); + goto lenerr; + } + if (p->len < sizeof(u16_t) * 2) { + 8019f88: 687b ldr r3, [r7, #4] + 8019f8a: 895b ldrh r3, [r3, #10] + 8019f8c: 2b03 cmp r3, #3 + 8019f8e: f240 80ca bls.w 801a126 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + goto lenerr; + } + + type = *((u8_t *)p->payload); + 8019f92: 687b ldr r3, [r7, #4] + 8019f94: 685b ldr r3, [r3, #4] + 8019f96: 781b ldrb r3, [r3, #0] + 8019f98: f887 3021 strb.w r3, [r7, #33] ; 0x21 +#ifdef LWIP_DEBUG + code = *(((u8_t *)p->payload) + 1); + /* if debug is enabled but debug statement below is somehow disabled: */ + LWIP_UNUSED_ARG(code); +#endif /* LWIP_DEBUG */ + switch (type) { + 8019f9c: f897 3021 ldrb.w r3, [r7, #33] ; 0x21 + 8019fa0: 2b00 cmp r3, #0 + 8019fa2: f000 80b7 beq.w 801a114 + 8019fa6: 2b08 cmp r3, #8 + 8019fa8: f040 80b7 bne.w 801a11a + (as obviously, an echo request has been sent, too). */ + MIB2_STATS_INC(mib2.icmpinechoreps); + break; + case ICMP_ECHO: + MIB2_STATS_INC(mib2.icmpinechos); + src = ip4_current_dest_addr(); + 8019fac: 4b69 ldr r3, [pc, #420] ; (801a154 ) + 8019fae: 61fb str r3, [r7, #28] + /* multicast destination address? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { + 8019fb0: 4b67 ldr r3, [pc, #412] ; (801a150 ) + 8019fb2: 695b ldr r3, [r3, #20] + 8019fb4: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8019fb8: 2be0 cmp r3, #224 ; 0xe0 + 8019fba: f000 80bb beq.w 801a134 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n")); + goto icmperr; +#endif /* LWIP_MULTICAST_PING */ + } + /* broadcast destination address? */ + if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) { + 8019fbe: 4b64 ldr r3, [pc, #400] ; (801a150 ) + 8019fc0: 695b ldr r3, [r3, #20] + 8019fc2: 4a63 ldr r2, [pc, #396] ; (801a150 ) + 8019fc4: 6812 ldr r2, [r2, #0] + 8019fc6: 4611 mov r1, r2 + 8019fc8: 4618 mov r0, r3 + 8019fca: f000 fc0b bl 801a7e4 + 8019fce: 4603 mov r3, r0 + 8019fd0: 2b00 cmp r3, #0 + 8019fd2: f040 80b1 bne.w 801a138 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n")); + goto icmperr; +#endif /* LWIP_BROADCAST_PING */ + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + 8019fd6: 687b ldr r3, [r7, #4] + 8019fd8: 891b ldrh r3, [r3, #8] + 8019fda: 2b07 cmp r3, #7 + 8019fdc: f240 80a5 bls.w 801a12a + return; + } + } +#endif +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + 8019fe0: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8019fe2: 330e adds r3, #14 + 8019fe4: 4619 mov r1, r3 + 8019fe6: 6878 ldr r0, [r7, #4] + 8019fe8: f7f6 fc74 bl 80108d4 + 8019fec: 4603 mov r3, r0 + 8019fee: 2b00 cmp r3, #0 + 8019ff0: d04b beq.n 801a08a + /* p is not big enough to contain link headers + * allocate a new one and copy p into it + */ + struct pbuf *r; + u16_t alloc_len = (u16_t)(p->tot_len + hlen); + 8019ff2: 687b ldr r3, [r7, #4] + 8019ff4: 891a ldrh r2, [r3, #8] + 8019ff6: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8019ff8: 4413 add r3, r2 + 8019ffa: 837b strh r3, [r7, #26] + if (alloc_len < p->tot_len) { + 8019ffc: 687b ldr r3, [r7, #4] + 8019ffe: 891b ldrh r3, [r3, #8] + 801a000: 8b7a ldrh r2, [r7, #26] + 801a002: 429a cmp r2, r3 + 801a004: f0c0 809a bcc.w 801a13c + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n")); + goto icmperr; + } + /* allocate new packet buffer with space for link headers */ + r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM); + 801a008: 8b7b ldrh r3, [r7, #26] + 801a00a: f44f 7220 mov.w r2, #640 ; 0x280 + 801a00e: 4619 mov r1, r3 + 801a010: 200e movs r0, #14 + 801a012: f7f6 fa11 bl 8010438 + 801a016: 6178 str r0, [r7, #20] + if (r == NULL) { + 801a018: 697b ldr r3, [r7, #20] + 801a01a: 2b00 cmp r3, #0 + 801a01c: f000 8090 beq.w 801a140 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); + goto icmperr; + } + if (r->len < hlen + sizeof(struct icmp_echo_hdr)) { + 801a020: 697b ldr r3, [r7, #20] + 801a022: 895b ldrh r3, [r3, #10] + 801a024: 461a mov r2, r3 + 801a026: 8c7b ldrh r3, [r7, #34] ; 0x22 + 801a028: 3308 adds r3, #8 + 801a02a: 429a cmp r2, r3 + 801a02c: d203 bcs.n 801a036 + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header")); + pbuf_free(r); + 801a02e: 6978 ldr r0, [r7, #20] + 801a030: f7f6 fce6 bl 8010a00 + goto icmperr; + 801a034: e085 b.n 801a142 + } + /* copy the ip header */ + MEMCPY(r->payload, iphdr_in, hlen); + 801a036: 697b ldr r3, [r7, #20] + 801a038: 685b ldr r3, [r3, #4] + 801a03a: 8c7a ldrh r2, [r7, #34] ; 0x22 + 801a03c: 6a79 ldr r1, [r7, #36] ; 0x24 + 801a03e: 4618 mov r0, r3 + 801a040: f001 ff23 bl 801be8a + /* switch r->payload back to icmp header (cannot fail) */ + if (pbuf_remove_header(r, hlen)) { + 801a044: 8c7b ldrh r3, [r7, #34] ; 0x22 + 801a046: 4619 mov r1, r3 + 801a048: 6978 ldr r0, [r7, #20] + 801a04a: f7f6 fc53 bl 80108f4 + 801a04e: 4603 mov r3, r0 + 801a050: 2b00 cmp r3, #0 + 801a052: d009 beq.n 801a068 + LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0); + 801a054: 4b40 ldr r3, [pc, #256] ; (801a158 ) + 801a056: 22b6 movs r2, #182 ; 0xb6 + 801a058: 4940 ldr r1, [pc, #256] ; (801a15c ) + 801a05a: 4841 ldr r0, [pc, #260] ; (801a160 ) + 801a05c: f001 ffda bl 801c014 + pbuf_free(r); + 801a060: 6978 ldr r0, [r7, #20] + 801a062: f7f6 fccd bl 8010a00 + goto icmperr; + 801a066: e06c b.n 801a142 + } + /* copy the rest of the packet without ip header */ + if (pbuf_copy(r, p) != ERR_OK) { + 801a068: 6879 ldr r1, [r7, #4] + 801a06a: 6978 ldr r0, [r7, #20] + 801a06c: f7f6 fdfc bl 8010c68 + 801a070: 4603 mov r3, r0 + 801a072: 2b00 cmp r3, #0 + 801a074: d003 beq.n 801a07e + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed")); + pbuf_free(r); + 801a076: 6978 ldr r0, [r7, #20] + 801a078: f7f6 fcc2 bl 8010a00 + goto icmperr; + 801a07c: e061 b.n 801a142 + } + /* free the original p */ + pbuf_free(p); + 801a07e: 6878 ldr r0, [r7, #4] + 801a080: f7f6 fcbe bl 8010a00 + /* we now have an identical copy of p that has room for link headers */ + p = r; + 801a084: 697b ldr r3, [r7, #20] + 801a086: 607b str r3, [r7, #4] + 801a088: e00f b.n 801a0aa + } else { + /* restore p->payload to point to icmp header (cannot fail) */ + if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + 801a08a: 8c7b ldrh r3, [r7, #34] ; 0x22 + 801a08c: 330e adds r3, #14 + 801a08e: 4619 mov r1, r3 + 801a090: 6878 ldr r0, [r7, #4] + 801a092: f7f6 fc2f bl 80108f4 + 801a096: 4603 mov r3, r0 + 801a098: 2b00 cmp r3, #0 + 801a09a: d006 beq.n 801a0aa + LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); + 801a09c: 4b2e ldr r3, [pc, #184] ; (801a158 ) + 801a09e: 22c7 movs r2, #199 ; 0xc7 + 801a0a0: 4930 ldr r1, [pc, #192] ; (801a164 ) + 801a0a2: 482f ldr r0, [pc, #188] ; (801a160 ) + 801a0a4: f001 ffb6 bl 801c014 + goto icmperr; + 801a0a8: e04b b.n 801a142 + } +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + /* At this point, all checks are OK. */ + /* We generate an answer by switching the dest and src ip addresses, + * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ + iecho = (struct icmp_echo_hdr *)p->payload; + 801a0aa: 687b ldr r3, [r7, #4] + 801a0ac: 685b ldr r3, [r3, #4] + 801a0ae: 613b str r3, [r7, #16] + if (pbuf_add_header(p, hlen)) { + 801a0b0: 8c7b ldrh r3, [r7, #34] ; 0x22 + 801a0b2: 4619 mov r1, r3 + 801a0b4: 6878 ldr r0, [r7, #4] + 801a0b6: f7f6 fc0d bl 80108d4 + 801a0ba: 4603 mov r3, r0 + 801a0bc: 2b00 cmp r3, #0 + 801a0be: d12b bne.n 801a118 + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet")); + } else { + err_t ret; + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + 801a0c0: 687b ldr r3, [r7, #4] + 801a0c2: 685b ldr r3, [r3, #4] + 801a0c4: 60fb str r3, [r7, #12] + ip4_addr_copy(iphdr->src, *src); + 801a0c6: 69fb ldr r3, [r7, #28] + 801a0c8: 681a ldr r2, [r3, #0] + 801a0ca: 68fb ldr r3, [r7, #12] + 801a0cc: 60da str r2, [r3, #12] + ip4_addr_copy(iphdr->dest, *ip4_current_src_addr()); + 801a0ce: 4b20 ldr r3, [pc, #128] ; (801a150 ) + 801a0d0: 691a ldr r2, [r3, #16] + 801a0d2: 68fb ldr r3, [r7, #12] + 801a0d4: 611a str r2, [r3, #16] + ICMPH_TYPE_SET(iecho, ICMP_ER); + 801a0d6: 693b ldr r3, [r7, #16] + 801a0d8: 2200 movs r2, #0 + 801a0da: 701a strb r2, [r3, #0] + else { + iecho->chksum = 0; + } +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ +#else /* CHECKSUM_GEN_ICMP */ + iecho->chksum = 0; + 801a0dc: 693b ldr r3, [r7, #16] + 801a0de: 2200 movs r2, #0 + 801a0e0: 709a strb r2, [r3, #2] + 801a0e2: 2200 movs r2, #0 + 801a0e4: 70da strb r2, [r3, #3] +#endif /* CHECKSUM_GEN_ICMP */ + + /* Set the correct TTL and recalculate the header checksum. */ + IPH_TTL_SET(iphdr, ICMP_TTL); + 801a0e6: 68fb ldr r3, [r7, #12] + 801a0e8: 22ff movs r2, #255 ; 0xff + 801a0ea: 721a strb r2, [r3, #8] + IPH_CHKSUM_SET(iphdr, 0); + 801a0ec: 68fb ldr r3, [r7, #12] + 801a0ee: 2200 movs r2, #0 + 801a0f0: 729a strb r2, [r3, #10] + 801a0f2: 2200 movs r2, #0 + 801a0f4: 72da strb r2, [r3, #11] + MIB2_STATS_INC(mib2.icmpoutmsgs); + /* increase number of echo replies attempted to send */ + MIB2_STATS_INC(mib2.icmpoutechoreps); + + /* send an ICMP packet */ + ret = ip4_output_if(p, src, LWIP_IP_HDRINCL, + 801a0f6: 683b ldr r3, [r7, #0] + 801a0f8: 9302 str r3, [sp, #8] + 801a0fa: 2301 movs r3, #1 + 801a0fc: 9301 str r3, [sp, #4] + 801a0fe: 2300 movs r3, #0 + 801a100: 9300 str r3, [sp, #0] + 801a102: 23ff movs r3, #255 ; 0xff + 801a104: 2200 movs r2, #0 + 801a106: 69f9 ldr r1, [r7, #28] + 801a108: 6878 ldr r0, [r7, #4] + 801a10a: f000 fa93 bl 801a634 + 801a10e: 4603 mov r3, r0 + 801a110: 72fb strb r3, [r7, #11] + ICMP_TTL, 0, IP_PROTO_ICMP, inp); + if (ret != ERR_OK) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); + } + } + break; + 801a112: e001 b.n 801a118 + break; + 801a114: bf00 nop + 801a116: e000 b.n 801a11a + break; + 801a118: bf00 nop + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", + (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); + 801a11a: 6878 ldr r0, [r7, #4] + 801a11c: f7f6 fc70 bl 8010a00 + return; + 801a120: e013 b.n 801a14a + goto lenerr; + 801a122: bf00 nop + 801a124: e002 b.n 801a12c + goto lenerr; + 801a126: bf00 nop + 801a128: e000 b.n 801a12c + goto lenerr; + 801a12a: bf00 nop +lenerr: + pbuf_free(p); + 801a12c: 6878 ldr r0, [r7, #4] + 801a12e: f7f6 fc67 bl 8010a00 + ICMP_STATS_INC(icmp.lenerr); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + 801a132: e00a b.n 801a14a + goto icmperr; + 801a134: bf00 nop + 801a136: e004 b.n 801a142 + goto icmperr; + 801a138: bf00 nop + 801a13a: e002 b.n 801a142 + goto icmperr; + 801a13c: bf00 nop + 801a13e: e000 b.n 801a142 + goto icmperr; + 801a140: bf00 nop +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING +icmperr: + pbuf_free(p); + 801a142: 6878 ldr r0, [r7, #4] + 801a144: f7f6 fc5c bl 8010a00 + ICMP_STATS_INC(icmp.err); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + 801a148: bf00 nop +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ +} + 801a14a: 3728 adds r7, #40 ; 0x28 + 801a14c: 46bd mov sp, r7 + 801a14e: bd80 pop {r7, pc} + 801a150: 20009670 .word 0x20009670 + 801a154: 20009684 .word 0x20009684 + 801a158: 08021398 .word 0x08021398 + 801a15c: 080213d0 .word 0x080213d0 + 801a160: 08021408 .word 0x08021408 + 801a164: 08021430 .word 0x08021430 + +0801a168 : + * p->payload pointing to the IP header + * @param t type of the 'unreachable' packet + */ +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + 801a168: b580 push {r7, lr} + 801a16a: b082 sub sp, #8 + 801a16c: af00 add r7, sp, #0 + 801a16e: 6078 str r0, [r7, #4] + 801a170: 460b mov r3, r1 + 801a172: 70fb strb r3, [r7, #3] + MIB2_STATS_INC(mib2.icmpoutdestunreachs); + icmp_send_response(p, ICMP_DUR, t); + 801a174: 78fb ldrb r3, [r7, #3] + 801a176: 461a mov r2, r3 + 801a178: 2103 movs r1, #3 + 801a17a: 6878 ldr r0, [r7, #4] + 801a17c: f000 f814 bl 801a1a8 +} + 801a180: bf00 nop + 801a182: 3708 adds r7, #8 + 801a184: 46bd mov sp, r7 + 801a186: bd80 pop {r7, pc} + +0801a188 : + * p->payload pointing to the IP header + * @param t type of the 'time exceeded' packet + */ +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + 801a188: b580 push {r7, lr} + 801a18a: b082 sub sp, #8 + 801a18c: af00 add r7, sp, #0 + 801a18e: 6078 str r0, [r7, #4] + 801a190: 460b mov r3, r1 + 801a192: 70fb strb r3, [r7, #3] + MIB2_STATS_INC(mib2.icmpouttimeexcds); + icmp_send_response(p, ICMP_TE, t); + 801a194: 78fb ldrb r3, [r7, #3] + 801a196: 461a mov r2, r3 + 801a198: 210b movs r1, #11 + 801a19a: 6878 ldr r0, [r7, #4] + 801a19c: f000 f804 bl 801a1a8 +} + 801a1a0: bf00 nop + 801a1a2: 3708 adds r7, #8 + 801a1a4: 46bd mov sp, r7 + 801a1a6: bd80 pop {r7, pc} + +0801a1a8 : + * @param type Type of the ICMP header + * @param code Code of the ICMP header + */ +static void +icmp_send_response(struct pbuf *p, u8_t type, u8_t code) +{ + 801a1a8: b580 push {r7, lr} + 801a1aa: b08c sub sp, #48 ; 0x30 + 801a1ac: af04 add r7, sp, #16 + 801a1ae: 6078 str r0, [r7, #4] + 801a1b0: 460b mov r3, r1 + 801a1b2: 70fb strb r3, [r7, #3] + 801a1b4: 4613 mov r3, r2 + 801a1b6: 70bb strb r3, [r7, #2] + + /* increase number of messages attempted to send */ + MIB2_STATS_INC(mib2.icmpoutmsgs); + + /* ICMP header + IP header + 8 bytes of data */ + q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, + 801a1b8: f44f 7220 mov.w r2, #640 ; 0x280 + 801a1bc: 2124 movs r1, #36 ; 0x24 + 801a1be: 2022 movs r0, #34 ; 0x22 + 801a1c0: f7f6 f93a bl 8010438 + 801a1c4: 61f8 str r0, [r7, #28] + PBUF_RAM); + if (q == NULL) { + 801a1c6: 69fb ldr r3, [r7, #28] + 801a1c8: 2b00 cmp r3, #0 + 801a1ca: d04c beq.n 801a266 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); + MIB2_STATS_INC(mib2.icmpouterrors); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + 801a1cc: 69fb ldr r3, [r7, #28] + 801a1ce: 895b ldrh r3, [r3, #10] + 801a1d0: 2b23 cmp r3, #35 ; 0x23 + 801a1d2: d806 bhi.n 801a1e2 + 801a1d4: 4b26 ldr r3, [pc, #152] ; (801a270 ) + 801a1d6: f44f 72b4 mov.w r2, #360 ; 0x168 + 801a1da: 4926 ldr r1, [pc, #152] ; (801a274 ) + 801a1dc: 4826 ldr r0, [pc, #152] ; (801a278 ) + 801a1de: f001 ff19 bl 801c014 + (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); + + iphdr = (struct ip_hdr *)p->payload; + 801a1e2: 687b ldr r3, [r7, #4] + 801a1e4: 685b ldr r3, [r3, #4] + 801a1e6: 61bb str r3, [r7, #24] + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src); + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest); + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + + icmphdr = (struct icmp_echo_hdr *)q->payload; + 801a1e8: 69fb ldr r3, [r7, #28] + 801a1ea: 685b ldr r3, [r3, #4] + 801a1ec: 617b str r3, [r7, #20] + icmphdr->type = type; + 801a1ee: 697b ldr r3, [r7, #20] + 801a1f0: 78fa ldrb r2, [r7, #3] + 801a1f2: 701a strb r2, [r3, #0] + icmphdr->code = code; + 801a1f4: 697b ldr r3, [r7, #20] + 801a1f6: 78ba ldrb r2, [r7, #2] + 801a1f8: 705a strb r2, [r3, #1] + icmphdr->id = 0; + 801a1fa: 697b ldr r3, [r7, #20] + 801a1fc: 2200 movs r2, #0 + 801a1fe: 711a strb r2, [r3, #4] + 801a200: 2200 movs r2, #0 + 801a202: 715a strb r2, [r3, #5] + icmphdr->seqno = 0; + 801a204: 697b ldr r3, [r7, #20] + 801a206: 2200 movs r2, #0 + 801a208: 719a strb r2, [r3, #6] + 801a20a: 2200 movs r2, #0 + 801a20c: 71da strb r2, [r3, #7] + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, + 801a20e: 69fb ldr r3, [r7, #28] + 801a210: 685b ldr r3, [r3, #4] + 801a212: f103 0008 add.w r0, r3, #8 + 801a216: 687b ldr r3, [r7, #4] + 801a218: 685b ldr r3, [r3, #4] + 801a21a: 221c movs r2, #28 + 801a21c: 4619 mov r1, r3 + 801a21e: f001 fe34 bl 801be8a + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); + + ip4_addr_copy(iphdr_src, iphdr->src); + 801a222: 69bb ldr r3, [r7, #24] + 801a224: 68db ldr r3, [r3, #12] + 801a226: 60fb str r3, [r7, #12] + ip4_addr_t iphdr_dst; + ip4_addr_copy(iphdr_dst, iphdr->dest); + netif = ip4_route_src(&iphdr_dst, &iphdr_src); + } +#else + netif = ip4_route(&iphdr_src); + 801a228: f107 030c add.w r3, r7, #12 + 801a22c: 4618 mov r0, r3 + 801a22e: f000 f825 bl 801a27c + 801a232: 6138 str r0, [r7, #16] +#endif + if (netif != NULL) { + 801a234: 693b ldr r3, [r7, #16] + 801a236: 2b00 cmp r3, #0 + 801a238: d011 beq.n 801a25e + /* calculate checksum */ + icmphdr->chksum = 0; + 801a23a: 697b ldr r3, [r7, #20] + 801a23c: 2200 movs r2, #0 + 801a23e: 709a strb r2, [r3, #2] + 801a240: 2200 movs r2, #0 + 801a242: 70da strb r2, [r3, #3] + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) { + icmphdr->chksum = inet_chksum(icmphdr, q->len); + } +#endif + ICMP_STATS_INC(icmp.xmit); + ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif); + 801a244: f107 020c add.w r2, r7, #12 + 801a248: 693b ldr r3, [r7, #16] + 801a24a: 9302 str r3, [sp, #8] + 801a24c: 2301 movs r3, #1 + 801a24e: 9301 str r3, [sp, #4] + 801a250: 2300 movs r3, #0 + 801a252: 9300 str r3, [sp, #0] + 801a254: 23ff movs r3, #255 ; 0xff + 801a256: 2100 movs r1, #0 + 801a258: 69f8 ldr r0, [r7, #28] + 801a25a: f000 f9eb bl 801a634 + } + pbuf_free(q); + 801a25e: 69f8 ldr r0, [r7, #28] + 801a260: f7f6 fbce bl 8010a00 + 801a264: e000 b.n 801a268 + return; + 801a266: bf00 nop +} + 801a268: 3720 adds r7, #32 + 801a26a: 46bd mov sp, r7 + 801a26c: bd80 pop {r7, pc} + 801a26e: bf00 nop + 801a270: 08021398 .word 0x08021398 + 801a274: 08021464 .word 0x08021464 + 801a278: 08021408 .word 0x08021408 + +0801a27c : + * @param dest the destination IP address for which to find the route + * @return the netif on which to send to reach dest + */ +struct netif * +ip4_route(const ip4_addr_t *dest) +{ + 801a27c: b480 push {r7} + 801a27e: b085 sub sp, #20 + 801a280: af00 add r7, sp, #0 + 801a282: 6078 str r0, [r7, #4] + + /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */ + LWIP_UNUSED_ARG(dest); + + /* iterate through netifs */ + NETIF_FOREACH(netif) { + 801a284: 4b33 ldr r3, [pc, #204] ; (801a354 ) + 801a286: 681b ldr r3, [r3, #0] + 801a288: 60fb str r3, [r7, #12] + 801a28a: e036 b.n 801a2fa + /* is the netif up, does it have a link and a valid address? */ + if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 801a28c: 68fb ldr r3, [r7, #12] + 801a28e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a292: f003 0301 and.w r3, r3, #1 + 801a296: b2db uxtb r3, r3 + 801a298: 2b00 cmp r3, #0 + 801a29a: d02b beq.n 801a2f4 + 801a29c: 68fb ldr r3, [r7, #12] + 801a29e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a2a2: 089b lsrs r3, r3, #2 + 801a2a4: f003 0301 and.w r3, r3, #1 + 801a2a8: b2db uxtb r3, r3 + 801a2aa: 2b00 cmp r3, #0 + 801a2ac: d022 beq.n 801a2f4 + 801a2ae: 68fb ldr r3, [r7, #12] + 801a2b0: 3304 adds r3, #4 + 801a2b2: 681b ldr r3, [r3, #0] + 801a2b4: 2b00 cmp r3, #0 + 801a2b6: d01d beq.n 801a2f4 + /* network mask matches? */ + if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) { + 801a2b8: 687b ldr r3, [r7, #4] + 801a2ba: 681a ldr r2, [r3, #0] + 801a2bc: 68fb ldr r3, [r7, #12] + 801a2be: 3304 adds r3, #4 + 801a2c0: 681b ldr r3, [r3, #0] + 801a2c2: 405a eors r2, r3 + 801a2c4: 68fb ldr r3, [r7, #12] + 801a2c6: 3308 adds r3, #8 + 801a2c8: 681b ldr r3, [r3, #0] + 801a2ca: 4013 ands r3, r2 + 801a2cc: 2b00 cmp r3, #0 + 801a2ce: d101 bne.n 801a2d4 + /* return netif on which to forward IP packet */ + return netif; + 801a2d0: 68fb ldr r3, [r7, #12] + 801a2d2: e038 b.n 801a346 + } + /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */ + if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) { + 801a2d4: 68fb ldr r3, [r7, #12] + 801a2d6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a2da: f003 0302 and.w r3, r3, #2 + 801a2de: 2b00 cmp r3, #0 + 801a2e0: d108 bne.n 801a2f4 + 801a2e2: 687b ldr r3, [r7, #4] + 801a2e4: 681a ldr r2, [r3, #0] + 801a2e6: 68fb ldr r3, [r7, #12] + 801a2e8: 330c adds r3, #12 + 801a2ea: 681b ldr r3, [r3, #0] + 801a2ec: 429a cmp r2, r3 + 801a2ee: d101 bne.n 801a2f4 + /* return netif on which to forward IP packet */ + return netif; + 801a2f0: 68fb ldr r3, [r7, #12] + 801a2f2: e028 b.n 801a346 + NETIF_FOREACH(netif) { + 801a2f4: 68fb ldr r3, [r7, #12] + 801a2f6: 681b ldr r3, [r3, #0] + 801a2f8: 60fb str r3, [r7, #12] + 801a2fa: 68fb ldr r3, [r7, #12] + 801a2fc: 2b00 cmp r3, #0 + 801a2fe: d1c5 bne.n 801a28c + return netif; + } +#endif +#endif /* !LWIP_SINGLE_NETIF */ + + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || + 801a300: 4b15 ldr r3, [pc, #84] ; (801a358 ) + 801a302: 681b ldr r3, [r3, #0] + 801a304: 2b00 cmp r3, #0 + 801a306: d01a beq.n 801a33e + 801a308: 4b13 ldr r3, [pc, #76] ; (801a358 ) + 801a30a: 681b ldr r3, [r3, #0] + 801a30c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a310: f003 0301 and.w r3, r3, #1 + 801a314: 2b00 cmp r3, #0 + 801a316: d012 beq.n 801a33e + 801a318: 4b0f ldr r3, [pc, #60] ; (801a358 ) + 801a31a: 681b ldr r3, [r3, #0] + 801a31c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a320: f003 0304 and.w r3, r3, #4 + 801a324: 2b00 cmp r3, #0 + 801a326: d00a beq.n 801a33e + ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { + 801a328: 4b0b ldr r3, [pc, #44] ; (801a358 ) + 801a32a: 681b ldr r3, [r3, #0] + 801a32c: 3304 adds r3, #4 + 801a32e: 681b ldr r3, [r3, #0] + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || + 801a330: 2b00 cmp r3, #0 + 801a332: d004 beq.n 801a33e + ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { + 801a334: 687b ldr r3, [r7, #4] + 801a336: 681b ldr r3, [r3, #0] + 801a338: b2db uxtb r3, r3 + 801a33a: 2b7f cmp r3, #127 ; 0x7f + 801a33c: d101 bne.n 801a342 + If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + MIB2_STATS_INC(mib2.ipoutnoroutes); + return NULL; + 801a33e: 2300 movs r3, #0 + 801a340: e001 b.n 801a346 + } + + return netif_default; + 801a342: 4b05 ldr r3, [pc, #20] ; (801a358 ) + 801a344: 681b ldr r3, [r3, #0] +} + 801a346: 4618 mov r0, r3 + 801a348: 3714 adds r7, #20 + 801a34a: 46bd mov sp, r7 + 801a34c: f85d 7b04 ldr.w r7, [sp], #4 + 801a350: 4770 bx lr + 801a352: bf00 nop + 801a354: 2000cf24 .word 0x2000cf24 + 801a358: 2000cf28 .word 0x2000cf28 + +0801a35c : +#endif /* IP_FORWARD */ + +/** Return true if the current input packet should be accepted on this netif */ +static int +ip4_input_accept(struct netif *netif) +{ + 801a35c: b580 push {r7, lr} + 801a35e: b082 sub sp, #8 + 801a360: af00 add r7, sp, #0 + 801a362: 6078 str r0, [r7, #4] + ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif)))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) { + 801a364: 687b ldr r3, [r7, #4] + 801a366: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a36a: f003 0301 and.w r3, r3, #1 + 801a36e: b2db uxtb r3, r3 + 801a370: 2b00 cmp r3, #0 + 801a372: d016 beq.n 801a3a2 + 801a374: 687b ldr r3, [r7, #4] + 801a376: 3304 adds r3, #4 + 801a378: 681b ldr r3, [r3, #0] + 801a37a: 2b00 cmp r3, #0 + 801a37c: d011 beq.n 801a3a2 + /* unicast to this interface address? */ + if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || + 801a37e: 4b0b ldr r3, [pc, #44] ; (801a3ac ) + 801a380: 695a ldr r2, [r3, #20] + 801a382: 687b ldr r3, [r7, #4] + 801a384: 3304 adds r3, #4 + 801a386: 681b ldr r3, [r3, #0] + 801a388: 429a cmp r2, r3 + 801a38a: d008 beq.n 801a39e + /* or broadcast on this interface network address? */ + ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) + 801a38c: 4b07 ldr r3, [pc, #28] ; (801a3ac ) + 801a38e: 695b ldr r3, [r3, #20] + 801a390: 6879 ldr r1, [r7, #4] + 801a392: 4618 mov r0, r3 + 801a394: f000 fa26 bl 801a7e4 + 801a398: 4603 mov r3, r0 + if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || + 801a39a: 2b00 cmp r3, #0 + 801a39c: d001 beq.n 801a3a2 +#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ + ) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* accept on this netif */ + return 1; + 801a39e: 2301 movs r3, #1 + 801a3a0: e000 b.n 801a3a4 + /* accept on this netif */ + return 1; + } +#endif /* LWIP_AUTOIP */ + } + return 0; + 801a3a2: 2300 movs r3, #0 +} + 801a3a4: 4618 mov r0, r3 + 801a3a6: 3708 adds r7, #8 + 801a3a8: 46bd mov sp, r7 + 801a3aa: bd80 pop {r7, pc} + 801a3ac: 20009670 .word 0x20009670 + +0801a3b0 : + * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't + * processed, but currently always returns ERR_OK) + */ +err_t +ip4_input(struct pbuf *p, struct netif *inp) +{ + 801a3b0: b580 push {r7, lr} + 801a3b2: b088 sub sp, #32 + 801a3b4: af00 add r7, sp, #0 + 801a3b6: 6078 str r0, [r7, #4] + 801a3b8: 6039 str r1, [r7, #0] + const struct ip_hdr *iphdr; + struct netif *netif; + u16_t iphdr_hlen; + u16_t iphdr_len; +#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP + int check_ip_src = 1; + 801a3ba: 2301 movs r3, #1 + 801a3bc: 617b str r3, [r7, #20] + + IP_STATS_INC(ip.recv); + MIB2_STATS_INC(mib2.ipinreceives); + + /* identify the IP header */ + iphdr = (struct ip_hdr *)p->payload; + 801a3be: 687b ldr r3, [r7, #4] + 801a3c0: 685b ldr r3, [r3, #4] + 801a3c2: 61fb str r3, [r7, #28] + if (IPH_V(iphdr) != 4) { + 801a3c4: 69fb ldr r3, [r7, #28] + 801a3c6: 781b ldrb r3, [r3, #0] + 801a3c8: 091b lsrs r3, r3, #4 + 801a3ca: b2db uxtb r3, r3 + 801a3cc: 2b04 cmp r3, #4 + 801a3ce: d004 beq.n 801a3da + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr))); + ip4_debug_print(p); + pbuf_free(p); + 801a3d0: 6878 ldr r0, [r7, #4] + 801a3d2: f7f6 fb15 bl 8010a00 + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinhdrerrors); + return ERR_OK; + 801a3d6: 2300 movs r3, #0 + 801a3d8: e123 b.n 801a622 + return ERR_OK; + } +#endif + + /* obtain IP header length in bytes */ + iphdr_hlen = IPH_HL_BYTES(iphdr); + 801a3da: 69fb ldr r3, [r7, #28] + 801a3dc: 781b ldrb r3, [r3, #0] + 801a3de: f003 030f and.w r3, r3, #15 + 801a3e2: b2db uxtb r3, r3 + 801a3e4: 009b lsls r3, r3, #2 + 801a3e6: b2db uxtb r3, r3 + 801a3e8: 827b strh r3, [r7, #18] + /* obtain ip length in bytes */ + iphdr_len = lwip_ntohs(IPH_LEN(iphdr)); + 801a3ea: 69fb ldr r3, [r7, #28] + 801a3ec: 885b ldrh r3, [r3, #2] + 801a3ee: b29b uxth r3, r3 + 801a3f0: 4618 mov r0, r3 + 801a3f2: f7f3 ff1d bl 800e230 + 801a3f6: 4603 mov r3, r0 + 801a3f8: 823b strh r3, [r7, #16] + + /* Trim pbuf. This is especially required for packets < 60 bytes. */ + if (iphdr_len < p->tot_len) { + 801a3fa: 687b ldr r3, [r7, #4] + 801a3fc: 891b ldrh r3, [r3, #8] + 801a3fe: 8a3a ldrh r2, [r7, #16] + 801a400: 429a cmp r2, r3 + 801a402: d204 bcs.n 801a40e + pbuf_realloc(p, iphdr_len); + 801a404: 8a3b ldrh r3, [r7, #16] + 801a406: 4619 mov r1, r3 + 801a408: 6878 ldr r0, [r7, #4] + 801a40a: f7f6 f973 bl 80106f4 + } + + /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ + if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) { + 801a40e: 687b ldr r3, [r7, #4] + 801a410: 895b ldrh r3, [r3, #10] + 801a412: 8a7a ldrh r2, [r7, #18] + 801a414: 429a cmp r2, r3 + 801a416: d807 bhi.n 801a428 + 801a418: 687b ldr r3, [r7, #4] + 801a41a: 891b ldrh r3, [r3, #8] + 801a41c: 8a3a ldrh r2, [r7, #16] + 801a41e: 429a cmp r2, r3 + 801a420: d802 bhi.n 801a428 + 801a422: 8a7b ldrh r3, [r7, #18] + 801a424: 2b13 cmp r3, #19 + 801a426: d804 bhi.n 801a432 + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_len, p->tot_len)); + } + /* free (drop) packet pbufs */ + pbuf_free(p); + 801a428: 6878 ldr r0, [r7, #4] + 801a42a: f7f6 fae9 bl 8010a00 + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + 801a42e: 2300 movs r3, #0 + 801a430: e0f7 b.n 801a622 + } + } +#endif + + /* copy IP addresses to aligned ip_addr_t */ + ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest); + 801a432: 69fb ldr r3, [r7, #28] + 801a434: 691b ldr r3, [r3, #16] + 801a436: 4a7d ldr r2, [pc, #500] ; (801a62c ) + 801a438: 6153 str r3, [r2, #20] + ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src); + 801a43a: 69fb ldr r3, [r7, #28] + 801a43c: 68db ldr r3, [r3, #12] + 801a43e: 4a7b ldr r2, [pc, #492] ; (801a62c ) + 801a440: 6113 str r3, [r2, #16] + + /* match packet against an interface, i.e. is this packet for us? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { + 801a442: 4b7a ldr r3, [pc, #488] ; (801a62c ) + 801a444: 695b ldr r3, [r3, #20] + 801a446: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 801a44a: 2be0 cmp r3, #224 ; 0xe0 + 801a44c: d112 bne.n 801a474 + netif = inp; + } else { + netif = NULL; + } +#else /* LWIP_IGMP */ + if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) { + 801a44e: 683b ldr r3, [r7, #0] + 801a450: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a454: f003 0301 and.w r3, r3, #1 + 801a458: b2db uxtb r3, r3 + 801a45a: 2b00 cmp r3, #0 + 801a45c: d007 beq.n 801a46e + 801a45e: 683b ldr r3, [r7, #0] + 801a460: 3304 adds r3, #4 + 801a462: 681b ldr r3, [r3, #0] + 801a464: 2b00 cmp r3, #0 + 801a466: d002 beq.n 801a46e + netif = inp; + 801a468: 683b ldr r3, [r7, #0] + 801a46a: 61bb str r3, [r7, #24] + 801a46c: e02a b.n 801a4c4 + } else { + netif = NULL; + 801a46e: 2300 movs r3, #0 + 801a470: 61bb str r3, [r7, #24] + 801a472: e027 b.n 801a4c4 + } +#endif /* LWIP_IGMP */ + } else { + /* start trying with inp. if that's not acceptable, start walking the + list of configured netifs. */ + if (ip4_input_accept(inp)) { + 801a474: 6838 ldr r0, [r7, #0] + 801a476: f7ff ff71 bl 801a35c + 801a47a: 4603 mov r3, r0 + 801a47c: 2b00 cmp r3, #0 + 801a47e: d002 beq.n 801a486 + netif = inp; + 801a480: 683b ldr r3, [r7, #0] + 801a482: 61bb str r3, [r7, #24] + 801a484: e01e b.n 801a4c4 + } else { + netif = NULL; + 801a486: 2300 movs r3, #0 + 801a488: 61bb str r3, [r7, #24] +#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF + /* Packets sent to the loopback address must not be accepted on an + * interface that does not have the loopback address assigned to it, + * unless a non-loopback interface is used for loopback traffic. */ + if (!ip4_addr_isloopback(ip4_current_dest_addr())) + 801a48a: 4b68 ldr r3, [pc, #416] ; (801a62c ) + 801a48c: 695b ldr r3, [r3, #20] + 801a48e: b2db uxtb r3, r3 + 801a490: 2b7f cmp r3, #127 ; 0x7f + 801a492: d017 beq.n 801a4c4 +#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ + { +#if !LWIP_SINGLE_NETIF + NETIF_FOREACH(netif) { + 801a494: 4b66 ldr r3, [pc, #408] ; (801a630 ) + 801a496: 681b ldr r3, [r3, #0] + 801a498: 61bb str r3, [r7, #24] + 801a49a: e00e b.n 801a4ba + if (netif == inp) { + 801a49c: 69ba ldr r2, [r7, #24] + 801a49e: 683b ldr r3, [r7, #0] + 801a4a0: 429a cmp r2, r3 + 801a4a2: d006 beq.n 801a4b2 + /* we checked that before already */ + continue; + } + if (ip4_input_accept(netif)) { + 801a4a4: 69b8 ldr r0, [r7, #24] + 801a4a6: f7ff ff59 bl 801a35c + 801a4aa: 4603 mov r3, r0 + 801a4ac: 2b00 cmp r3, #0 + 801a4ae: d108 bne.n 801a4c2 + 801a4b0: e000 b.n 801a4b4 + continue; + 801a4b2: bf00 nop + NETIF_FOREACH(netif) { + 801a4b4: 69bb ldr r3, [r7, #24] + 801a4b6: 681b ldr r3, [r3, #0] + 801a4b8: 61bb str r3, [r7, #24] + 801a4ba: 69bb ldr r3, [r7, #24] + 801a4bc: 2b00 cmp r3, #0 + 801a4be: d1ed bne.n 801a49c + 801a4c0: e000 b.n 801a4c4 + break; + 801a4c2: bf00 nop + * If you want to accept private broadcast communication while a netif is down, + * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.: + * + * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345)) + */ + if (netif == NULL) { + 801a4c4: 69bb ldr r3, [r7, #24] + 801a4c6: 2b00 cmp r3, #0 + 801a4c8: d111 bne.n 801a4ee + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { + 801a4ca: 69fb ldr r3, [r7, #28] + 801a4cc: 7a5b ldrb r3, [r3, #9] + 801a4ce: 2b11 cmp r3, #17 + 801a4d0: d10d bne.n 801a4ee + const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen); + 801a4d2: 8a7b ldrh r3, [r7, #18] + 801a4d4: 69fa ldr r2, [r7, #28] + 801a4d6: 4413 add r3, r2 + 801a4d8: 60fb str r3, [r7, #12] + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n", + lwip_ntohs(udphdr->dest))); + if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) { + 801a4da: 68fb ldr r3, [r7, #12] + 801a4dc: 885b ldrh r3, [r3, #2] + 801a4de: b29b uxth r3, r3 + 801a4e0: f5b3 4f88 cmp.w r3, #17408 ; 0x4400 + 801a4e4: d103 bne.n 801a4ee + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n")); + netif = inp; + 801a4e6: 683b ldr r3, [r7, #0] + 801a4e8: 61bb str r3, [r7, #24] + check_ip_src = 0; + 801a4ea: 2300 movs r3, #0 + 801a4ec: 617b str r3, [r7, #20] + } +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + + /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ +#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING + if (check_ip_src + 801a4ee: 697b ldr r3, [r7, #20] + 801a4f0: 2b00 cmp r3, #0 + 801a4f2: d017 beq.n 801a524 +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ + && !ip4_addr_isany_val(*ip4_current_src_addr()) + 801a4f4: 4b4d ldr r3, [pc, #308] ; (801a62c ) + 801a4f6: 691b ldr r3, [r3, #16] + 801a4f8: 2b00 cmp r3, #0 + 801a4fa: d013 beq.n 801a524 +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + ) +#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */ + { + if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || + 801a4fc: 4b4b ldr r3, [pc, #300] ; (801a62c ) + 801a4fe: 691b ldr r3, [r3, #16] + 801a500: 6839 ldr r1, [r7, #0] + 801a502: 4618 mov r0, r3 + 801a504: f000 f96e bl 801a7e4 + 801a508: 4603 mov r3, r0 + 801a50a: 2b00 cmp r3, #0 + 801a50c: d105 bne.n 801a51a + (ip4_addr_ismulticast(ip4_current_src_addr()))) { + 801a50e: 4b47 ldr r3, [pc, #284] ; (801a62c ) + 801a510: 691b ldr r3, [r3, #16] + 801a512: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || + 801a516: 2be0 cmp r3, #224 ; 0xe0 + 801a518: d104 bne.n 801a524 + /* packet source is not valid */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n")); + /* free (drop) packet pbufs */ + pbuf_free(p); + 801a51a: 6878 ldr r0, [r7, #4] + 801a51c: f7f6 fa70 bl 8010a00 + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + 801a520: 2300 movs r3, #0 + 801a522: e07e b.n 801a622 + } + } + + /* packet not for us? */ + if (netif == NULL) { + 801a524: 69bb ldr r3, [r7, #24] + 801a526: 2b00 cmp r3, #0 + 801a528: d104 bne.n 801a534 + { + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + } + pbuf_free(p); + 801a52a: 6878 ldr r0, [r7, #4] + 801a52c: f7f6 fa68 bl 8010a00 + return ERR_OK; + 801a530: 2300 movs r3, #0 + 801a532: e076 b.n 801a622 + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { + 801a534: 69fb ldr r3, [r7, #28] + 801a536: 88db ldrh r3, [r3, #6] + 801a538: b29b uxth r3, r3 + 801a53a: 461a mov r2, r3 + 801a53c: f64f 733f movw r3, #65343 ; 0xff3f + 801a540: 4013 ands r3, r2 + 801a542: 2b00 cmp r3, #0 + 801a544: d00b beq.n 801a55e +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n", + lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8))); + /* reassemble the packet*/ + p = ip4_reass(p); + 801a546: 6878 ldr r0, [r7, #4] + 801a548: f000 fe4c bl 801b1e4 + 801a54c: 6078 str r0, [r7, #4] + /* packet not fully reassembled yet? */ + if (p == NULL) { + 801a54e: 687b ldr r3, [r7, #4] + 801a550: 2b00 cmp r3, #0 + 801a552: d101 bne.n 801a558 + return ERR_OK; + 801a554: 2300 movs r3, #0 + 801a556: e064 b.n 801a622 + } + iphdr = (const struct ip_hdr *)p->payload; + 801a558: 687b ldr r3, [r7, #4] + 801a55a: 685b ldr r3, [r3, #4] + 801a55c: 61fb str r3, [r7, #28] + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n")); + ip4_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + + ip_data.current_netif = netif; + 801a55e: 4a33 ldr r2, [pc, #204] ; (801a62c ) + 801a560: 69bb ldr r3, [r7, #24] + 801a562: 6013 str r3, [r2, #0] + ip_data.current_input_netif = inp; + 801a564: 4a31 ldr r2, [pc, #196] ; (801a62c ) + 801a566: 683b ldr r3, [r7, #0] + 801a568: 6053 str r3, [r2, #4] + ip_data.current_ip4_header = iphdr; + 801a56a: 4a30 ldr r2, [pc, #192] ; (801a62c ) + 801a56c: 69fb ldr r3, [r7, #28] + 801a56e: 6093 str r3, [r2, #8] + ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr); + 801a570: 69fb ldr r3, [r7, #28] + 801a572: 781b ldrb r3, [r3, #0] + 801a574: f003 030f and.w r3, r3, #15 + 801a578: b2db uxtb r3, r3 + 801a57a: 009b lsls r3, r3, #2 + 801a57c: b2db uxtb r3, r3 + 801a57e: b29a uxth r2, r3 + 801a580: 4b2a ldr r3, [pc, #168] ; (801a62c ) + 801a582: 819a strh r2, [r3, #12] + /* raw input did not eat the packet? */ + raw_status = raw_input(p, inp); + if (raw_status != RAW_INPUT_EATEN) +#endif /* LWIP_RAW */ + { + pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */ + 801a584: 8a7b ldrh r3, [r7, #18] + 801a586: 4619 mov r1, r3 + 801a588: 6878 ldr r0, [r7, #4] + 801a58a: f7f6 f9b3 bl 80108f4 + + switch (IPH_PROTO(iphdr)) { + 801a58e: 69fb ldr r3, [r7, #28] + 801a590: 7a5b ldrb r3, [r3, #9] + 801a592: 2b11 cmp r3, #17 + 801a594: d006 beq.n 801a5a4 + 801a596: 2b11 cmp r3, #17 + 801a598: dc13 bgt.n 801a5c2 + 801a59a: 2b01 cmp r3, #1 + 801a59c: d00c beq.n 801a5b8 + 801a59e: 2b06 cmp r3, #6 + 801a5a0: d005 beq.n 801a5ae + 801a5a2: e00e b.n 801a5c2 + case IP_PROTO_UDP: +#if LWIP_UDPLITE + case IP_PROTO_UDPLITE: +#endif /* LWIP_UDPLITE */ + MIB2_STATS_INC(mib2.ipindelivers); + udp_input(p, inp); + 801a5a4: 6839 ldr r1, [r7, #0] + 801a5a6: 6878 ldr r0, [r7, #4] + 801a5a8: f7fc f9d4 bl 8016954 + break; + 801a5ac: e026 b.n 801a5fc +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + MIB2_STATS_INC(mib2.ipindelivers); + tcp_input(p, inp); + 801a5ae: 6839 ldr r1, [r7, #0] + 801a5b0: 6878 ldr r0, [r7, #4] + 801a5b2: f7f8 f9e5 bl 8012980 + break; + 801a5b6: e021 b.n 801a5fc +#endif /* LWIP_TCP */ +#if LWIP_ICMP + case IP_PROTO_ICMP: + MIB2_STATS_INC(mib2.ipindelivers); + icmp_input(p, inp); + 801a5b8: 6839 ldr r1, [r7, #0] + 801a5ba: 6878 ldr r0, [r7, #4] + 801a5bc: f7ff fcd0 bl 8019f60 + break; + 801a5c0: e01c b.n 801a5fc + } else +#endif /* LWIP_RAW */ + { +#if LWIP_ICMP + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && + 801a5c2: 4b1a ldr r3, [pc, #104] ; (801a62c ) + 801a5c4: 695b ldr r3, [r3, #20] + 801a5c6: 69b9 ldr r1, [r7, #24] + 801a5c8: 4618 mov r0, r3 + 801a5ca: f000 f90b bl 801a7e4 + 801a5ce: 4603 mov r3, r0 + 801a5d0: 2b00 cmp r3, #0 + 801a5d2: d10f bne.n 801a5f4 + !ip4_addr_ismulticast(ip4_current_dest_addr())) { + 801a5d4: 4b15 ldr r3, [pc, #84] ; (801a62c ) + 801a5d6: 695b ldr r3, [r3, #20] + 801a5d8: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && + 801a5dc: 2be0 cmp r3, #224 ; 0xe0 + 801a5de: d009 beq.n 801a5f4 + pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */ + 801a5e0: f9b7 3012 ldrsh.w r3, [r7, #18] + 801a5e4: 4619 mov r1, r3 + 801a5e6: 6878 ldr r0, [r7, #4] + 801a5e8: f7f6 f9f7 bl 80109da + icmp_dest_unreach(p, ICMP_DUR_PROTO); + 801a5ec: 2102 movs r1, #2 + 801a5ee: 6878 ldr r0, [r7, #4] + 801a5f0: f7ff fdba bl 801a168 + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinunknownprotos); + } + pbuf_free(p); + 801a5f4: 6878 ldr r0, [r7, #4] + 801a5f6: f7f6 fa03 bl 8010a00 + break; + 801a5fa: bf00 nop + } + } + + /* @todo: this is not really necessary... */ + ip_data.current_netif = NULL; + 801a5fc: 4b0b ldr r3, [pc, #44] ; (801a62c ) + 801a5fe: 2200 movs r2, #0 + 801a600: 601a str r2, [r3, #0] + ip_data.current_input_netif = NULL; + 801a602: 4b0a ldr r3, [pc, #40] ; (801a62c ) + 801a604: 2200 movs r2, #0 + 801a606: 605a str r2, [r3, #4] + ip_data.current_ip4_header = NULL; + 801a608: 4b08 ldr r3, [pc, #32] ; (801a62c ) + 801a60a: 2200 movs r2, #0 + 801a60c: 609a str r2, [r3, #8] + ip_data.current_ip_header_tot_len = 0; + 801a60e: 4b07 ldr r3, [pc, #28] ; (801a62c ) + 801a610: 2200 movs r2, #0 + 801a612: 819a strh r2, [r3, #12] + ip4_addr_set_any(ip4_current_src_addr()); + 801a614: 4b05 ldr r3, [pc, #20] ; (801a62c ) + 801a616: 2200 movs r2, #0 + 801a618: 611a str r2, [r3, #16] + ip4_addr_set_any(ip4_current_dest_addr()); + 801a61a: 4b04 ldr r3, [pc, #16] ; (801a62c ) + 801a61c: 2200 movs r2, #0 + 801a61e: 615a str r2, [r3, #20] + + return ERR_OK; + 801a620: 2300 movs r3, #0 +} + 801a622: 4618 mov r0, r3 + 801a624: 3720 adds r7, #32 + 801a626: 46bd mov sp, r7 + 801a628: bd80 pop {r7, pc} + 801a62a: bf00 nop + 801a62c: 20009670 .word 0x20009670 + 801a630: 2000cf24 .word 0x2000cf24 + +0801a634 : + */ +err_t +ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + 801a634: b580 push {r7, lr} + 801a636: b08a sub sp, #40 ; 0x28 + 801a638: af04 add r7, sp, #16 + 801a63a: 60f8 str r0, [r7, #12] + 801a63c: 60b9 str r1, [r7, #8] + 801a63e: 607a str r2, [r7, #4] + 801a640: 70fb strb r3, [r7, #3] +ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen) +{ +#endif /* IP_OPTIONS_SEND */ + const ip4_addr_t *src_used = src; + 801a642: 68bb ldr r3, [r7, #8] + 801a644: 617b str r3, [r7, #20] + if (dest != LWIP_IP_HDRINCL) { + 801a646: 687b ldr r3, [r7, #4] + 801a648: 2b00 cmp r3, #0 + 801a64a: d009 beq.n 801a660 + if (ip4_addr_isany(src)) { + 801a64c: 68bb ldr r3, [r7, #8] + 801a64e: 2b00 cmp r3, #0 + 801a650: d003 beq.n 801a65a + 801a652: 68bb ldr r3, [r7, #8] + 801a654: 681b ldr r3, [r3, #0] + 801a656: 2b00 cmp r3, #0 + 801a658: d102 bne.n 801a660 + src_used = netif_ip4_addr(netif); + 801a65a: 6abb ldr r3, [r7, #40] ; 0x28 + 801a65c: 3304 adds r3, #4 + 801a65e: 617b str r3, [r7, #20] + +#if IP_OPTIONS_SEND + return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif, + ip_options, optlen); +#else /* IP_OPTIONS_SEND */ + return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif); + 801a660: 78fa ldrb r2, [r7, #3] + 801a662: 6abb ldr r3, [r7, #40] ; 0x28 + 801a664: 9302 str r3, [sp, #8] + 801a666: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 801a66a: 9301 str r3, [sp, #4] + 801a66c: f897 3020 ldrb.w r3, [r7, #32] + 801a670: 9300 str r3, [sp, #0] + 801a672: 4613 mov r3, r2 + 801a674: 687a ldr r2, [r7, #4] + 801a676: 6979 ldr r1, [r7, #20] + 801a678: 68f8 ldr r0, [r7, #12] + 801a67a: f000 f805 bl 801a688 + 801a67e: 4603 mov r3, r0 +#endif /* IP_OPTIONS_SEND */ +} + 801a680: 4618 mov r0, r3 + 801a682: 3718 adds r7, #24 + 801a684: 46bd mov sp, r7 + 801a686: bd80 pop {r7, pc} + +0801a688 : + */ +err_t +ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + 801a688: b580 push {r7, lr} + 801a68a: b088 sub sp, #32 + 801a68c: af00 add r7, sp, #0 + 801a68e: 60f8 str r0, [r7, #12] + 801a690: 60b9 str r1, [r7, #8] + 801a692: 607a str r2, [r7, #4] + 801a694: 70fb strb r3, [r7, #3] +#if CHECKSUM_GEN_IP_INLINE + u32_t chk_sum = 0; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + 801a696: 68fb ldr r3, [r7, #12] + 801a698: 7b9b ldrb r3, [r3, #14] + 801a69a: 2b01 cmp r3, #1 + 801a69c: d006 beq.n 801a6ac + 801a69e: 4b4b ldr r3, [pc, #300] ; (801a7cc ) + 801a6a0: f44f 7255 mov.w r2, #852 ; 0x354 + 801a6a4: 494a ldr r1, [pc, #296] ; (801a7d0 ) + 801a6a6: 484b ldr r0, [pc, #300] ; (801a7d4 ) + 801a6a8: f001 fcb4 bl 801c014 + + MIB2_STATS_INC(mib2.ipoutrequests); + + /* Should the IP header be generated or is it already included in p? */ + if (dest != LWIP_IP_HDRINCL) { + 801a6ac: 687b ldr r3, [r7, #4] + 801a6ae: 2b00 cmp r3, #0 + 801a6b0: d060 beq.n 801a774 + u16_t ip_hlen = IP_HLEN; + 801a6b2: 2314 movs r3, #20 + 801a6b4: 837b strh r3, [r7, #26] + } +#endif /* CHECKSUM_GEN_IP_INLINE */ + } +#endif /* IP_OPTIONS_SEND */ + /* generate IP header */ + if (pbuf_add_header(p, IP_HLEN)) { + 801a6b6: 2114 movs r1, #20 + 801a6b8: 68f8 ldr r0, [r7, #12] + 801a6ba: f7f6 f90b bl 80108d4 + 801a6be: 4603 mov r3, r0 + 801a6c0: 2b00 cmp r3, #0 + 801a6c2: d002 beq.n 801a6ca + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + 801a6c4: f06f 0301 mvn.w r3, #1 + 801a6c8: e07c b.n 801a7c4 + } + + iphdr = (struct ip_hdr *)p->payload; + 801a6ca: 68fb ldr r3, [r7, #12] + 801a6cc: 685b ldr r3, [r3, #4] + 801a6ce: 61fb str r3, [r7, #28] + LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", + 801a6d0: 68fb ldr r3, [r7, #12] + 801a6d2: 895b ldrh r3, [r3, #10] + 801a6d4: 2b13 cmp r3, #19 + 801a6d6: d806 bhi.n 801a6e6 + 801a6d8: 4b3c ldr r3, [pc, #240] ; (801a7cc ) + 801a6da: f44f 7262 mov.w r2, #904 ; 0x388 + 801a6de: 493e ldr r1, [pc, #248] ; (801a7d8 ) + 801a6e0: 483c ldr r0, [pc, #240] ; (801a7d4 ) + 801a6e2: f001 fc97 bl 801c014 + (p->len >= sizeof(struct ip_hdr))); + + IPH_TTL_SET(iphdr, ttl); + 801a6e6: 69fb ldr r3, [r7, #28] + 801a6e8: 78fa ldrb r2, [r7, #3] + 801a6ea: 721a strb r2, [r3, #8] + IPH_PROTO_SET(iphdr, proto); + 801a6ec: 69fb ldr r3, [r7, #28] + 801a6ee: f897 202c ldrb.w r2, [r7, #44] ; 0x2c + 801a6f2: 725a strb r2, [r3, #9] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(proto | (ttl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + + /* dest cannot be NULL here */ + ip4_addr_copy(iphdr->dest, *dest); + 801a6f4: 687b ldr r3, [r7, #4] + 801a6f6: 681a ldr r2, [r3, #0] + 801a6f8: 69fb ldr r3, [r7, #28] + 801a6fa: 611a str r2, [r3, #16] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + IPH_VHL_SET(iphdr, 4, ip_hlen / 4); + 801a6fc: 8b7b ldrh r3, [r7, #26] + 801a6fe: 089b lsrs r3, r3, #2 + 801a700: b29b uxth r3, r3 + 801a702: b2db uxtb r3, r3 + 801a704: f043 0340 orr.w r3, r3, #64 ; 0x40 + 801a708: b2da uxtb r2, r3 + 801a70a: 69fb ldr r3, [r7, #28] + 801a70c: 701a strb r2, [r3, #0] + IPH_TOS_SET(iphdr, tos); + 801a70e: 69fb ldr r3, [r7, #28] + 801a710: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 + 801a714: 705a strb r2, [r3, #1] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_LEN_SET(iphdr, lwip_htons(p->tot_len)); + 801a716: 68fb ldr r3, [r7, #12] + 801a718: 891b ldrh r3, [r3, #8] + 801a71a: 4618 mov r0, r3 + 801a71c: f7f3 fd88 bl 800e230 + 801a720: 4603 mov r3, r0 + 801a722: 461a mov r2, r3 + 801a724: 69fb ldr r3, [r7, #28] + 801a726: 805a strh r2, [r3, #2] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_len; +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_OFFSET_SET(iphdr, 0); + 801a728: 69fb ldr r3, [r7, #28] + 801a72a: 2200 movs r2, #0 + 801a72c: 719a strb r2, [r3, #6] + 801a72e: 2200 movs r2, #0 + 801a730: 71da strb r2, [r3, #7] + IPH_ID_SET(iphdr, lwip_htons(ip_id)); + 801a732: 4b2a ldr r3, [pc, #168] ; (801a7dc ) + 801a734: 881b ldrh r3, [r3, #0] + 801a736: 4618 mov r0, r3 + 801a738: f7f3 fd7a bl 800e230 + 801a73c: 4603 mov r3, r0 + 801a73e: 461a mov r2, r3 + 801a740: 69fb ldr r3, [r7, #28] + 801a742: 809a strh r2, [r3, #4] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_id; +#endif /* CHECKSUM_GEN_IP_INLINE */ + ++ip_id; + 801a744: 4b25 ldr r3, [pc, #148] ; (801a7dc ) + 801a746: 881b ldrh r3, [r3, #0] + 801a748: 3301 adds r3, #1 + 801a74a: b29a uxth r2, r3 + 801a74c: 4b23 ldr r3, [pc, #140] ; (801a7dc ) + 801a74e: 801a strh r2, [r3, #0] + + if (src == NULL) { + 801a750: 68bb ldr r3, [r7, #8] + 801a752: 2b00 cmp r3, #0 + 801a754: d104 bne.n 801a760 + ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4); + 801a756: 4b22 ldr r3, [pc, #136] ; (801a7e0 ) + 801a758: 681a ldr r2, [r3, #0] + 801a75a: 69fb ldr r3, [r7, #28] + 801a75c: 60da str r2, [r3, #12] + 801a75e: e003 b.n 801a768 + } else { + /* src cannot be NULL here */ + ip4_addr_copy(iphdr->src, *src); + 801a760: 68bb ldr r3, [r7, #8] + 801a762: 681a ldr r2, [r3, #0] + 801a764: 69fb ldr r3, [r7, #28] + 801a766: 60da str r2, [r3, #12] + else { + IPH_CHKSUM_SET(iphdr, 0); + } +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ +#else /* CHECKSUM_GEN_IP_INLINE */ + IPH_CHKSUM_SET(iphdr, 0); + 801a768: 69fb ldr r3, [r7, #28] + 801a76a: 2200 movs r2, #0 + 801a76c: 729a strb r2, [r3, #10] + 801a76e: 2200 movs r2, #0 + 801a770: 72da strb r2, [r3, #11] + 801a772: e00f b.n 801a794 + } +#endif /* CHECKSUM_GEN_IP */ +#endif /* CHECKSUM_GEN_IP_INLINE */ + } else { + /* IP header already included in p */ + if (p->len < IP_HLEN) { + 801a774: 68fb ldr r3, [r7, #12] + 801a776: 895b ldrh r3, [r3, #10] + 801a778: 2b13 cmp r3, #19 + 801a77a: d802 bhi.n 801a782 + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n")); + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + 801a77c: f06f 0301 mvn.w r3, #1 + 801a780: e020 b.n 801a7c4 + } + iphdr = (struct ip_hdr *)p->payload; + 801a782: 68fb ldr r3, [r7, #12] + 801a784: 685b ldr r3, [r3, #4] + 801a786: 61fb str r3, [r7, #28] + ip4_addr_copy(dest_addr, iphdr->dest); + 801a788: 69fb ldr r3, [r7, #28] + 801a78a: 691b ldr r3, [r3, #16] + 801a78c: 617b str r3, [r7, #20] + dest = &dest_addr; + 801a78e: f107 0314 add.w r3, r7, #20 + 801a792: 607b str r3, [r7, #4] + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#endif /* ENABLE_LOOPBACK */ +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) { + 801a794: 6b3b ldr r3, [r7, #48] ; 0x30 + 801a796: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801a798: 2b00 cmp r3, #0 + 801a79a: d00c beq.n 801a7b6 + 801a79c: 68fb ldr r3, [r7, #12] + 801a79e: 891a ldrh r2, [r3, #8] + 801a7a0: 6b3b ldr r3, [r7, #48] ; 0x30 + 801a7a2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801a7a4: 429a cmp r2, r3 + 801a7a6: d906 bls.n 801a7b6 + return ip4_frag(p, netif, dest); + 801a7a8: 687a ldr r2, [r7, #4] + 801a7aa: 6b39 ldr r1, [r7, #48] ; 0x30 + 801a7ac: 68f8 ldr r0, [r7, #12] + 801a7ae: f000 ff0d bl 801b5cc + 801a7b2: 4603 mov r3, r0 + 801a7b4: e006 b.n 801a7c4 + } +#endif /* IP_FRAG */ + + LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n")); + return netif->output(netif, p, dest); + 801a7b6: 6b3b ldr r3, [r7, #48] ; 0x30 + 801a7b8: 695b ldr r3, [r3, #20] + 801a7ba: 687a ldr r2, [r7, #4] + 801a7bc: 68f9 ldr r1, [r7, #12] + 801a7be: 6b38 ldr r0, [r7, #48] ; 0x30 + 801a7c0: 4798 blx r3 + 801a7c2: 4603 mov r3, r0 +} + 801a7c4: 4618 mov r0, r3 + 801a7c6: 3720 adds r7, #32 + 801a7c8: 46bd mov sp, r7 + 801a7ca: bd80 pop {r7, pc} + 801a7cc: 08021490 .word 0x08021490 + 801a7d0: 080214c4 .word 0x080214c4 + 801a7d4: 080214d0 .word 0x080214d0 + 801a7d8: 080214f8 .word 0x080214f8 + 801a7dc: 2000d0c2 .word 0x2000d0c2 + 801a7e0: 08023914 .word 0x08023914 + +0801a7e4 : + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + */ +u8_t +ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif) +{ + 801a7e4: b480 push {r7} + 801a7e6: b085 sub sp, #20 + 801a7e8: af00 add r7, sp, #0 + 801a7ea: 6078 str r0, [r7, #4] + 801a7ec: 6039 str r1, [r7, #0] + ip4_addr_t ipaddr; + ip4_addr_set_u32(&ipaddr, addr); + 801a7ee: 687b ldr r3, [r7, #4] + 801a7f0: 60fb str r3, [r7, #12] + + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr == IPADDR_ANY) || + 801a7f2: 687b ldr r3, [r7, #4] + 801a7f4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 801a7f8: d002 beq.n 801a800 + 801a7fa: 687b ldr r3, [r7, #4] + 801a7fc: 2b00 cmp r3, #0 + 801a7fe: d101 bne.n 801a804 + (addr == IPADDR_ANY)) { + return 1; + 801a800: 2301 movs r3, #1 + 801a802: e02a b.n 801a85a + /* no broadcast support on this network interface? */ + } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { + 801a804: 683b ldr r3, [r7, #0] + 801a806: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801a80a: f003 0302 and.w r3, r3, #2 + 801a80e: 2b00 cmp r3, #0 + 801a810: d101 bne.n 801a816 + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + 801a812: 2300 movs r3, #0 + 801a814: e021 b.n 801a85a + /* address matches network interface address exactly? => no broadcast */ + } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) { + 801a816: 683b ldr r3, [r7, #0] + 801a818: 3304 adds r3, #4 + 801a81a: 681b ldr r3, [r3, #0] + 801a81c: 687a ldr r2, [r7, #4] + 801a81e: 429a cmp r2, r3 + 801a820: d101 bne.n 801a826 + return 0; + 801a822: 2300 movs r3, #0 + 801a824: e019 b.n 801a85a + /* on the same (sub) network... */ + } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) + 801a826: 68fa ldr r2, [r7, #12] + 801a828: 683b ldr r3, [r7, #0] + 801a82a: 3304 adds r3, #4 + 801a82c: 681b ldr r3, [r3, #0] + 801a82e: 405a eors r2, r3 + 801a830: 683b ldr r3, [r7, #0] + 801a832: 3308 adds r3, #8 + 801a834: 681b ldr r3, [r3, #0] + 801a836: 4013 ands r3, r2 + 801a838: 2b00 cmp r3, #0 + 801a83a: d10d bne.n 801a858 + /* ...and host identifier bits are all ones? =>... */ + && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == + 801a83c: 683b ldr r3, [r7, #0] + 801a83e: 3308 adds r3, #8 + 801a840: 681b ldr r3, [r3, #0] + 801a842: 43da mvns r2, r3 + 801a844: 687b ldr r3, [r7, #4] + 801a846: 401a ands r2, r3 + (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) { + 801a848: 683b ldr r3, [r7, #0] + 801a84a: 3308 adds r3, #8 + 801a84c: 681b ldr r3, [r3, #0] + 801a84e: 43db mvns r3, r3 + && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == + 801a850: 429a cmp r2, r3 + 801a852: d101 bne.n 801a858 + /* => network broadcast address */ + return 1; + 801a854: 2301 movs r3, #1 + 801a856: e000 b.n 801a85a + } else { + return 0; + 801a858: 2300 movs r3, #0 + } +} + 801a85a: 4618 mov r0, r3 + 801a85c: 3714 adds r7, #20 + 801a85e: 46bd mov sp, r7 + 801a860: f85d 7b04 ldr.w r7, [sp], #4 + 801a864: 4770 bx lr + ... + +0801a868 : + * @param addr pointer to which to save the ip address in network order + * @return 1 if cp could be converted to addr, 0 on failure + */ +int +ip4addr_aton(const char *cp, ip4_addr_t *addr) +{ + 801a868: b580 push {r7, lr} + 801a86a: b08a sub sp, #40 ; 0x28 + 801a86c: af00 add r7, sp, #0 + 801a86e: 6078 str r0, [r7, #4] + 801a870: 6039 str r1, [r7, #0] + u32_t val; + u8_t base; + char c; + u32_t parts[4]; + u32_t *pp = parts; + 801a872: f107 030c add.w r3, r7, #12 + 801a876: 61fb str r3, [r7, #28] + + c = *cp; + 801a878: 687b ldr r3, [r7, #4] + 801a87a: 781b ldrb r3, [r3, #0] + 801a87c: f887 3022 strb.w r3, [r7, #34] ; 0x22 + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (!lwip_isdigit(c)) { + 801a880: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a884: 3301 adds r3, #1 + 801a886: 4a89 ldr r2, [pc, #548] ; (801aaac ) + 801a888: 4413 add r3, r2 + 801a88a: 781b ldrb r3, [r3, #0] + 801a88c: f003 0304 and.w r3, r3, #4 + 801a890: 2b00 cmp r3, #0 + 801a892: d101 bne.n 801a898 + return 0; + 801a894: 2300 movs r3, #0 + 801a896: e105 b.n 801aaa4 + } + val = 0; + 801a898: 2300 movs r3, #0 + 801a89a: 627b str r3, [r7, #36] ; 0x24 + base = 10; + 801a89c: 230a movs r3, #10 + 801a89e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + if (c == '0') { + 801a8a2: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a8a6: 2b30 cmp r3, #48 ; 0x30 + 801a8a8: d11c bne.n 801a8e4 + c = *++cp; + 801a8aa: 687b ldr r3, [r7, #4] + 801a8ac: 3301 adds r3, #1 + 801a8ae: 607b str r3, [r7, #4] + 801a8b0: 687b ldr r3, [r7, #4] + 801a8b2: 781b ldrb r3, [r3, #0] + 801a8b4: f887 3022 strb.w r3, [r7, #34] ; 0x22 + if (c == 'x' || c == 'X') { + 801a8b8: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a8bc: 2b78 cmp r3, #120 ; 0x78 + 801a8be: d003 beq.n 801a8c8 + 801a8c0: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a8c4: 2b58 cmp r3, #88 ; 0x58 + 801a8c6: d10a bne.n 801a8de + base = 16; + 801a8c8: 2310 movs r3, #16 + 801a8ca: f887 3023 strb.w r3, [r7, #35] ; 0x23 + c = *++cp; + 801a8ce: 687b ldr r3, [r7, #4] + 801a8d0: 3301 adds r3, #1 + 801a8d2: 607b str r3, [r7, #4] + 801a8d4: 687b ldr r3, [r7, #4] + 801a8d6: 781b ldrb r3, [r3, #0] + 801a8d8: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 801a8dc: e002 b.n 801a8e4 + } else { + base = 8; + 801a8de: 2308 movs r3, #8 + 801a8e0: f887 3023 strb.w r3, [r7, #35] ; 0x23 + } + } + for (;;) { + if (lwip_isdigit(c)) { + 801a8e4: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a8e8: 3301 adds r3, #1 + 801a8ea: 4a70 ldr r2, [pc, #448] ; (801aaac ) + 801a8ec: 4413 add r3, r2 + 801a8ee: 781b ldrb r3, [r3, #0] + 801a8f0: f003 0304 and.w r3, r3, #4 + 801a8f4: 2b00 cmp r3, #0 + 801a8f6: d011 beq.n 801a91c + val = (val * base) + (u32_t)(c - '0'); + 801a8f8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 801a8fc: 6a7a ldr r2, [r7, #36] ; 0x24 + 801a8fe: fb03 f202 mul.w r2, r3, r2 + 801a902: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a906: 4413 add r3, r2 + 801a908: 3b30 subs r3, #48 ; 0x30 + 801a90a: 627b str r3, [r7, #36] ; 0x24 + c = *++cp; + 801a90c: 687b ldr r3, [r7, #4] + 801a90e: 3301 adds r3, #1 + 801a910: 607b str r3, [r7, #4] + 801a912: 687b ldr r3, [r7, #4] + 801a914: 781b ldrb r3, [r3, #0] + 801a916: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 801a91a: e7e3 b.n 801a8e4 + } else if (base == 16 && lwip_isxdigit(c)) { + 801a91c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 801a920: 2b10 cmp r3, #16 + 801a922: d127 bne.n 801a974 + 801a924: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a928: 3301 adds r3, #1 + 801a92a: 4a60 ldr r2, [pc, #384] ; (801aaac ) + 801a92c: 4413 add r3, r2 + 801a92e: 781b ldrb r3, [r3, #0] + 801a930: f003 0344 and.w r3, r3, #68 ; 0x44 + 801a934: 2b00 cmp r3, #0 + 801a936: d01d beq.n 801a974 + val = (val << 4) | (u32_t)(c + 10 - (lwip_islower(c) ? 'a' : 'A')); + 801a938: 6a7b ldr r3, [r7, #36] ; 0x24 + 801a93a: 011b lsls r3, r3, #4 + 801a93c: f897 2022 ldrb.w r2, [r7, #34] ; 0x22 + 801a940: f102 010a add.w r1, r2, #10 + 801a944: f897 2022 ldrb.w r2, [r7, #34] ; 0x22 + 801a948: 3201 adds r2, #1 + 801a94a: 4858 ldr r0, [pc, #352] ; (801aaac ) + 801a94c: 4402 add r2, r0 + 801a94e: 7812 ldrb r2, [r2, #0] + 801a950: f002 0203 and.w r2, r2, #3 + 801a954: 2a02 cmp r2, #2 + 801a956: d101 bne.n 801a95c + 801a958: 2261 movs r2, #97 ; 0x61 + 801a95a: e000 b.n 801a95e + 801a95c: 2241 movs r2, #65 ; 0x41 + 801a95e: 1a8a subs r2, r1, r2 + 801a960: 4313 orrs r3, r2 + 801a962: 627b str r3, [r7, #36] ; 0x24 + c = *++cp; + 801a964: 687b ldr r3, [r7, #4] + 801a966: 3301 adds r3, #1 + 801a968: 607b str r3, [r7, #4] + 801a96a: 687b ldr r3, [r7, #4] + 801a96c: 781b ldrb r3, [r3, #0] + 801a96e: f887 3022 strb.w r3, [r7, #34] ; 0x22 + if (lwip_isdigit(c)) { + 801a972: e7b7 b.n 801a8e4 + } else { + break; + } + } + if (c == '.') { + 801a974: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a978: 2b2e cmp r3, #46 ; 0x2e + 801a97a: d114 bne.n 801a9a6 + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= parts + 3) { + 801a97c: f107 030c add.w r3, r7, #12 + 801a980: 330c adds r3, #12 + 801a982: 69fa ldr r2, [r7, #28] + 801a984: 429a cmp r2, r3 + 801a986: d301 bcc.n 801a98c + return 0; + 801a988: 2300 movs r3, #0 + 801a98a: e08b b.n 801aaa4 + } + *pp++ = val; + 801a98c: 69fb ldr r3, [r7, #28] + 801a98e: 1d1a adds r2, r3, #4 + 801a990: 61fa str r2, [r7, #28] + 801a992: 6a7a ldr r2, [r7, #36] ; 0x24 + 801a994: 601a str r2, [r3, #0] + c = *++cp; + 801a996: 687b ldr r3, [r7, #4] + 801a998: 3301 adds r3, #1 + 801a99a: 607b str r3, [r7, #4] + 801a99c: 687b ldr r3, [r7, #4] + 801a99e: 781b ldrb r3, [r3, #0] + 801a9a0: f887 3022 strb.w r3, [r7, #34] ; 0x22 + if (!lwip_isdigit(c)) { + 801a9a4: e76c b.n 801a880 + } else { + break; + 801a9a6: bf00 nop + } + } + /* + * Check for trailing characters. + */ + if (c != '\0' && !lwip_isspace(c)) { + 801a9a8: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a9ac: 2b00 cmp r3, #0 + 801a9ae: d00b beq.n 801a9c8 + 801a9b0: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 801a9b4: 3301 adds r3, #1 + 801a9b6: 4a3d ldr r2, [pc, #244] ; (801aaac ) + 801a9b8: 4413 add r3, r2 + 801a9ba: 781b ldrb r3, [r3, #0] + 801a9bc: f003 0308 and.w r3, r3, #8 + 801a9c0: 2b00 cmp r3, #0 + 801a9c2: d101 bne.n 801a9c8 + return 0; + 801a9c4: 2300 movs r3, #0 + 801a9c6: e06d b.n 801aaa4 + } + /* + * Concoct the address according to + * the number of parts specified. + */ + switch (pp - parts + 1) { + 801a9c8: f107 030c add.w r3, r7, #12 + 801a9cc: 69fa ldr r2, [r7, #28] + 801a9ce: 1ad3 subs r3, r2, r3 + 801a9d0: 109b asrs r3, r3, #2 + 801a9d2: 3301 adds r3, #1 + 801a9d4: 2b04 cmp r3, #4 + 801a9d6: d853 bhi.n 801aa80 + 801a9d8: a201 add r2, pc, #4 ; (adr r2, 801a9e0 ) + 801a9da: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 801a9de: bf00 nop + 801a9e0: 0801a9f5 .word 0x0801a9f5 + 801a9e4: 0801aa8f .word 0x0801aa8f + 801a9e8: 0801a9f9 .word 0x0801a9f9 + 801a9ec: 0801aa1b .word 0x0801aa1b + 801a9f0: 0801aa49 .word 0x0801aa49 + + case 0: + return 0; /* initial nondigit */ + 801a9f4: 2300 movs r3, #0 + 801a9f6: e055 b.n 801aaa4 + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffffUL) { + 801a9f8: 6a7b ldr r3, [r7, #36] ; 0x24 + 801a9fa: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 801a9fe: d301 bcc.n 801aa04 + return 0; + 801aa00: 2300 movs r3, #0 + 801aa02: e04f b.n 801aaa4 + } + if (parts[0] > 0xff) { + 801aa04: 68fb ldr r3, [r7, #12] + 801aa06: 2bff cmp r3, #255 ; 0xff + 801aa08: d901 bls.n 801aa0e + return 0; + 801aa0a: 2300 movs r3, #0 + 801aa0c: e04a b.n 801aaa4 + } + val |= parts[0] << 24; + 801aa0e: 68fb ldr r3, [r7, #12] + 801aa10: 061b lsls r3, r3, #24 + 801aa12: 6a7a ldr r2, [r7, #36] ; 0x24 + 801aa14: 4313 orrs r3, r2 + 801aa16: 627b str r3, [r7, #36] ; 0x24 + break; + 801aa18: e03a b.n 801aa90 + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffff) { + 801aa1a: 6a7b ldr r3, [r7, #36] ; 0x24 + 801aa1c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 801aa20: d301 bcc.n 801aa26 + return 0; + 801aa22: 2300 movs r3, #0 + 801aa24: e03e b.n 801aaa4 + } + if ((parts[0] > 0xff) || (parts[1] > 0xff)) { + 801aa26: 68fb ldr r3, [r7, #12] + 801aa28: 2bff cmp r3, #255 ; 0xff + 801aa2a: d802 bhi.n 801aa32 + 801aa2c: 693b ldr r3, [r7, #16] + 801aa2e: 2bff cmp r3, #255 ; 0xff + 801aa30: d901 bls.n 801aa36 + return 0; + 801aa32: 2300 movs r3, #0 + 801aa34: e036 b.n 801aaa4 + } + val |= (parts[0] << 24) | (parts[1] << 16); + 801aa36: 68fb ldr r3, [r7, #12] + 801aa38: 061a lsls r2, r3, #24 + 801aa3a: 693b ldr r3, [r7, #16] + 801aa3c: 041b lsls r3, r3, #16 + 801aa3e: 4313 orrs r3, r2 + 801aa40: 6a7a ldr r2, [r7, #36] ; 0x24 + 801aa42: 4313 orrs r3, r2 + 801aa44: 627b str r3, [r7, #36] ; 0x24 + break; + 801aa46: e023 b.n 801aa90 + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xff) { + 801aa48: 6a7b ldr r3, [r7, #36] ; 0x24 + 801aa4a: 2bff cmp r3, #255 ; 0xff + 801aa4c: d901 bls.n 801aa52 + return 0; + 801aa4e: 2300 movs r3, #0 + 801aa50: e028 b.n 801aaa4 + } + if ((parts[0] > 0xff) || (parts[1] > 0xff) || (parts[2] > 0xff)) { + 801aa52: 68fb ldr r3, [r7, #12] + 801aa54: 2bff cmp r3, #255 ; 0xff + 801aa56: d805 bhi.n 801aa64 + 801aa58: 693b ldr r3, [r7, #16] + 801aa5a: 2bff cmp r3, #255 ; 0xff + 801aa5c: d802 bhi.n 801aa64 + 801aa5e: 697b ldr r3, [r7, #20] + 801aa60: 2bff cmp r3, #255 ; 0xff + 801aa62: d901 bls.n 801aa68 + return 0; + 801aa64: 2300 movs r3, #0 + 801aa66: e01d b.n 801aaa4 + } + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + 801aa68: 68fb ldr r3, [r7, #12] + 801aa6a: 061a lsls r2, r3, #24 + 801aa6c: 693b ldr r3, [r7, #16] + 801aa6e: 041b lsls r3, r3, #16 + 801aa70: 431a orrs r2, r3 + 801aa72: 697b ldr r3, [r7, #20] + 801aa74: 021b lsls r3, r3, #8 + 801aa76: 4313 orrs r3, r2 + 801aa78: 6a7a ldr r2, [r7, #36] ; 0x24 + 801aa7a: 4313 orrs r3, r2 + 801aa7c: 627b str r3, [r7, #36] ; 0x24 + break; + 801aa7e: e007 b.n 801aa90 + default: + LWIP_ASSERT("unhandled", 0); + 801aa80: 4b0b ldr r3, [pc, #44] ; (801aab0 ) + 801aa82: 22f9 movs r2, #249 ; 0xf9 + 801aa84: 490b ldr r1, [pc, #44] ; (801aab4 ) + 801aa86: 480c ldr r0, [pc, #48] ; (801aab8 ) + 801aa88: f001 fac4 bl 801c014 + break; + 801aa8c: e000 b.n 801aa90 + break; + 801aa8e: bf00 nop + } + if (addr) { + 801aa90: 683b ldr r3, [r7, #0] + 801aa92: 2b00 cmp r3, #0 + 801aa94: d005 beq.n 801aaa2 + ip4_addr_set_u32(addr, lwip_htonl(val)); + 801aa96: 6a78 ldr r0, [r7, #36] ; 0x24 + 801aa98: f7f3 fbdf bl 800e25a + 801aa9c: 4602 mov r2, r0 + 801aa9e: 683b ldr r3, [r7, #0] + 801aaa0: 601a str r2, [r3, #0] + } + return 1; + 801aaa2: 2301 movs r3, #1 +} + 801aaa4: 4618 mov r0, r3 + 801aaa6: 3728 adds r7, #40 ; 0x28 + 801aaa8: 46bd mov sp, r7 + 801aaaa: bd80 pop {r7, pc} + 801aaac: 08023934 .word 0x08023934 + 801aab0: 08021528 .word 0x08021528 + 801aab4: 08021564 .word 0x08021564 + 801aab8: 08021570 .word 0x08021570 + +0801aabc : + * @return pointer to a global static (!) buffer that holds the ASCII + * representation of addr + */ +char * +ip4addr_ntoa(const ip4_addr_t *addr) +{ + 801aabc: b580 push {r7, lr} + 801aabe: b082 sub sp, #8 + 801aac0: af00 add r7, sp, #0 + 801aac2: 6078 str r0, [r7, #4] + static char str[IP4ADDR_STRLEN_MAX]; + return ip4addr_ntoa_r(addr, str, IP4ADDR_STRLEN_MAX); + 801aac4: 2210 movs r2, #16 + 801aac6: 4904 ldr r1, [pc, #16] ; (801aad8 ) + 801aac8: 6878 ldr r0, [r7, #4] + 801aaca: f000 f807 bl 801aadc + 801aace: 4603 mov r3, r0 +} + 801aad0: 4618 mov r0, r3 + 801aad2: 3708 adds r7, #8 + 801aad4: 46bd mov sp, r7 + 801aad6: bd80 pop {r7, pc} + 801aad8: 2000d0c4 .word 0x2000d0c4 + +0801aadc : + * @return either pointer to buf which now holds the ASCII + * representation of addr or NULL if buf was too small + */ +char * +ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen) +{ + 801aadc: b480 push {r7} + 801aade: b08d sub sp, #52 ; 0x34 + 801aae0: af00 add r7, sp, #0 + 801aae2: 60f8 str r0, [r7, #12] + 801aae4: 60b9 str r1, [r7, #8] + 801aae6: 607a str r2, [r7, #4] + char *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + int len = 0; + 801aae8: 2300 movs r3, #0 + 801aaea: 623b str r3, [r7, #32] + + s_addr = ip4_addr_get_u32(addr); + 801aaec: 68fb ldr r3, [r7, #12] + 801aaee: 681b ldr r3, [r3, #0] + 801aaf0: 61bb str r3, [r7, #24] + + rp = buf; + 801aaf2: 68bb ldr r3, [r7, #8] + 801aaf4: 62fb str r3, [r7, #44] ; 0x2c + ap = (u8_t *)&s_addr; + 801aaf6: f107 0318 add.w r3, r7, #24 + 801aafa: 62bb str r3, [r7, #40] ; 0x28 + for (n = 0; n < 4; n++) { + 801aafc: 2300 movs r3, #0 + 801aafe: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 801ab02: e058 b.n 801abb6 + i = 0; + 801ab04: 2300 movs r3, #0 + 801ab06: f887 3026 strb.w r3, [r7, #38] ; 0x26 + do { + rem = *ap % (u8_t)10; + 801ab0a: 6abb ldr r3, [r7, #40] ; 0x28 + 801ab0c: 781a ldrb r2, [r3, #0] + 801ab0e: 4b32 ldr r3, [pc, #200] ; (801abd8 ) + 801ab10: fba3 1302 umull r1, r3, r3, r2 + 801ab14: 08d9 lsrs r1, r3, #3 + 801ab16: 460b mov r3, r1 + 801ab18: 009b lsls r3, r3, #2 + 801ab1a: 440b add r3, r1 + 801ab1c: 005b lsls r3, r3, #1 + 801ab1e: 1ad3 subs r3, r2, r3 + 801ab20: 77fb strb r3, [r7, #31] + *ap /= (u8_t)10; + 801ab22: 6abb ldr r3, [r7, #40] ; 0x28 + 801ab24: 781b ldrb r3, [r3, #0] + 801ab26: 4a2c ldr r2, [pc, #176] ; (801abd8 ) + 801ab28: fba2 2303 umull r2, r3, r2, r3 + 801ab2c: 08db lsrs r3, r3, #3 + 801ab2e: b2da uxtb r2, r3 + 801ab30: 6abb ldr r3, [r7, #40] ; 0x28 + 801ab32: 701a strb r2, [r3, #0] + inv[i++] = (char)('0' + rem); + 801ab34: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 801ab38: 1c5a adds r2, r3, #1 + 801ab3a: f887 2026 strb.w r2, [r7, #38] ; 0x26 + 801ab3e: 4619 mov r1, r3 + 801ab40: 7ffb ldrb r3, [r7, #31] + 801ab42: 3330 adds r3, #48 ; 0x30 + 801ab44: b2da uxtb r2, r3 + 801ab46: f101 0330 add.w r3, r1, #48 ; 0x30 + 801ab4a: 443b add r3, r7 + 801ab4c: f803 2c1c strb.w r2, [r3, #-28] + } while (*ap); + 801ab50: 6abb ldr r3, [r7, #40] ; 0x28 + 801ab52: 781b ldrb r3, [r3, #0] + 801ab54: 2b00 cmp r3, #0 + 801ab56: d1d8 bne.n 801ab0a + while (i--) { + 801ab58: e011 b.n 801ab7e + if (len++ >= buflen) { + 801ab5a: 6a3b ldr r3, [r7, #32] + 801ab5c: 1c5a adds r2, r3, #1 + 801ab5e: 623a str r2, [r7, #32] + 801ab60: 687a ldr r2, [r7, #4] + 801ab62: 429a cmp r2, r3 + 801ab64: dc01 bgt.n 801ab6a + return NULL; + 801ab66: 2300 movs r3, #0 + 801ab68: e030 b.n 801abcc + } + *rp++ = inv[i]; + 801ab6a: f897 2026 ldrb.w r2, [r7, #38] ; 0x26 + 801ab6e: 6afb ldr r3, [r7, #44] ; 0x2c + 801ab70: 1c59 adds r1, r3, #1 + 801ab72: 62f9 str r1, [r7, #44] ; 0x2c + 801ab74: 3230 adds r2, #48 ; 0x30 + 801ab76: 443a add r2, r7 + 801ab78: f812 2c1c ldrb.w r2, [r2, #-28] + 801ab7c: 701a strb r2, [r3, #0] + while (i--) { + 801ab7e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 801ab82: 1e5a subs r2, r3, #1 + 801ab84: f887 2026 strb.w r2, [r7, #38] ; 0x26 + 801ab88: 2b00 cmp r3, #0 + 801ab8a: d1e6 bne.n 801ab5a + } + if (len++ >= buflen) { + 801ab8c: 6a3b ldr r3, [r7, #32] + 801ab8e: 1c5a adds r2, r3, #1 + 801ab90: 623a str r2, [r7, #32] + 801ab92: 687a ldr r2, [r7, #4] + 801ab94: 429a cmp r2, r3 + 801ab96: dc01 bgt.n 801ab9c + return NULL; + 801ab98: 2300 movs r3, #0 + 801ab9a: e017 b.n 801abcc + } + *rp++ = '.'; + 801ab9c: 6afb ldr r3, [r7, #44] ; 0x2c + 801ab9e: 1c5a adds r2, r3, #1 + 801aba0: 62fa str r2, [r7, #44] ; 0x2c + 801aba2: 222e movs r2, #46 ; 0x2e + 801aba4: 701a strb r2, [r3, #0] + ap++; + 801aba6: 6abb ldr r3, [r7, #40] ; 0x28 + 801aba8: 3301 adds r3, #1 + 801abaa: 62bb str r3, [r7, #40] ; 0x28 + for (n = 0; n < 4; n++) { + 801abac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 801abb0: 3301 adds r3, #1 + 801abb2: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 801abb6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 801abba: 2b03 cmp r3, #3 + 801abbc: d9a2 bls.n 801ab04 + } + *--rp = 0; + 801abbe: 6afb ldr r3, [r7, #44] ; 0x2c + 801abc0: 3b01 subs r3, #1 + 801abc2: 62fb str r3, [r7, #44] ; 0x2c + 801abc4: 6afb ldr r3, [r7, #44] ; 0x2c + 801abc6: 2200 movs r2, #0 + 801abc8: 701a strb r2, [r3, #0] + return buf; + 801abca: 68bb ldr r3, [r7, #8] +} + 801abcc: 4618 mov r0, r3 + 801abce: 3734 adds r7, #52 ; 0x34 + 801abd0: 46bd mov sp, r7 + 801abd2: f85d 7b04 ldr.w r7, [sp], #4 + 801abd6: 4770 bx lr + 801abd8: cccccccd .word 0xcccccccd + +0801abdc : + * + * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). + */ +void +ip_reass_tmr(void) +{ + 801abdc: b580 push {r7, lr} + 801abde: b084 sub sp, #16 + 801abe0: af00 add r7, sp, #0 + struct ip_reassdata *r, *prev = NULL; + 801abe2: 2300 movs r3, #0 + 801abe4: 60bb str r3, [r7, #8] + + r = reassdatagrams; + 801abe6: 4b12 ldr r3, [pc, #72] ; (801ac30 ) + 801abe8: 681b ldr r3, [r3, #0] + 801abea: 60fb str r3, [r7, #12] + while (r != NULL) { + 801abec: e018 b.n 801ac20 + /* Decrement the timer. Once it reaches 0, + * clean up the incomplete fragment assembly */ + if (r->timer > 0) { + 801abee: 68fb ldr r3, [r7, #12] + 801abf0: 7fdb ldrb r3, [r3, #31] + 801abf2: 2b00 cmp r3, #0 + 801abf4: d00b beq.n 801ac0e + r->timer--; + 801abf6: 68fb ldr r3, [r7, #12] + 801abf8: 7fdb ldrb r3, [r3, #31] + 801abfa: 3b01 subs r3, #1 + 801abfc: b2da uxtb r2, r3 + 801abfe: 68fb ldr r3, [r7, #12] + 801ac00: 77da strb r2, [r3, #31] + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer)); + prev = r; + 801ac02: 68fb ldr r3, [r7, #12] + 801ac04: 60bb str r3, [r7, #8] + r = r->next; + 801ac06: 68fb ldr r3, [r7, #12] + 801ac08: 681b ldr r3, [r3, #0] + 801ac0a: 60fb str r3, [r7, #12] + 801ac0c: e008 b.n 801ac20 + } else { + /* reassembly timed out */ + struct ip_reassdata *tmp; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); + tmp = r; + 801ac0e: 68fb ldr r3, [r7, #12] + 801ac10: 607b str r3, [r7, #4] + /* get the next pointer before freeing */ + r = r->next; + 801ac12: 68fb ldr r3, [r7, #12] + 801ac14: 681b ldr r3, [r3, #0] + 801ac16: 60fb str r3, [r7, #12] + /* free the helper struct and all enqueued pbufs */ + ip_reass_free_complete_datagram(tmp, prev); + 801ac18: 68b9 ldr r1, [r7, #8] + 801ac1a: 6878 ldr r0, [r7, #4] + 801ac1c: f000 f80a bl 801ac34 + while (r != NULL) { + 801ac20: 68fb ldr r3, [r7, #12] + 801ac22: 2b00 cmp r3, #0 + 801ac24: d1e3 bne.n 801abee + } + } +} + 801ac26: bf00 nop + 801ac28: bf00 nop + 801ac2a: 3710 adds r7, #16 + 801ac2c: 46bd mov sp, r7 + 801ac2e: bd80 pop {r7, pc} + 801ac30: 2000d0d4 .word 0x2000d0d4 + +0801ac34 : + * @param prev the previous datagram in the linked list + * @return the number of pbufs freed + */ +static int +ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + 801ac34: b580 push {r7, lr} + 801ac36: b088 sub sp, #32 + 801ac38: af00 add r7, sp, #0 + 801ac3a: 6078 str r0, [r7, #4] + 801ac3c: 6039 str r1, [r7, #0] + u16_t pbufs_freed = 0; + 801ac3e: 2300 movs r3, #0 + 801ac40: 83fb strh r3, [r7, #30] + u16_t clen; + struct pbuf *p; + struct ip_reass_helper *iprh; + + LWIP_ASSERT("prev != ipr", prev != ipr); + 801ac42: 683a ldr r2, [r7, #0] + 801ac44: 687b ldr r3, [r7, #4] + 801ac46: 429a cmp r2, r3 + 801ac48: d105 bne.n 801ac56 + 801ac4a: 4b45 ldr r3, [pc, #276] ; (801ad60 ) + 801ac4c: 22ab movs r2, #171 ; 0xab + 801ac4e: 4945 ldr r1, [pc, #276] ; (801ad64 ) + 801ac50: 4845 ldr r0, [pc, #276] ; (801ad68 ) + 801ac52: f001 f9df bl 801c014 + if (prev != NULL) { + 801ac56: 683b ldr r3, [r7, #0] + 801ac58: 2b00 cmp r3, #0 + 801ac5a: d00a beq.n 801ac72 + LWIP_ASSERT("prev->next == ipr", prev->next == ipr); + 801ac5c: 683b ldr r3, [r7, #0] + 801ac5e: 681b ldr r3, [r3, #0] + 801ac60: 687a ldr r2, [r7, #4] + 801ac62: 429a cmp r2, r3 + 801ac64: d005 beq.n 801ac72 + 801ac66: 4b3e ldr r3, [pc, #248] ; (801ad60 ) + 801ac68: 22ad movs r2, #173 ; 0xad + 801ac6a: 4940 ldr r1, [pc, #256] ; (801ad6c ) + 801ac6c: 483e ldr r0, [pc, #248] ; (801ad68 ) + 801ac6e: f001 f9d1 bl 801c014 + } + + MIB2_STATS_INC(mib2.ipreasmfails); +#if LWIP_ICMP + iprh = (struct ip_reass_helper *)ipr->p->payload; + 801ac72: 687b ldr r3, [r7, #4] + 801ac74: 685b ldr r3, [r3, #4] + 801ac76: 685b ldr r3, [r3, #4] + 801ac78: 617b str r3, [r7, #20] + if (iprh->start == 0) { + 801ac7a: 697b ldr r3, [r7, #20] + 801ac7c: 889b ldrh r3, [r3, #4] + 801ac7e: b29b uxth r3, r3 + 801ac80: 2b00 cmp r3, #0 + 801ac82: d12a bne.n 801acda + /* The first fragment was received, send ICMP time exceeded. */ + /* First, de-queue the first pbuf from r->p. */ + p = ipr->p; + 801ac84: 687b ldr r3, [r7, #4] + 801ac86: 685b ldr r3, [r3, #4] + 801ac88: 61bb str r3, [r7, #24] + ipr->p = iprh->next_pbuf; + 801ac8a: 697b ldr r3, [r7, #20] + 801ac8c: 681a ldr r2, [r3, #0] + 801ac8e: 687b ldr r3, [r7, #4] + 801ac90: 605a str r2, [r3, #4] + /* Then, copy the original header into it. */ + SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); + 801ac92: 69bb ldr r3, [r7, #24] + 801ac94: 6858 ldr r0, [r3, #4] + 801ac96: 687b ldr r3, [r7, #4] + 801ac98: 3308 adds r3, #8 + 801ac9a: 2214 movs r2, #20 + 801ac9c: 4619 mov r1, r3 + 801ac9e: f001 f8f4 bl 801be8a + icmp_time_exceeded(p, ICMP_TE_FRAG); + 801aca2: 2101 movs r1, #1 + 801aca4: 69b8 ldr r0, [r7, #24] + 801aca6: f7ff fa6f bl 801a188 + clen = pbuf_clen(p); + 801acaa: 69b8 ldr r0, [r7, #24] + 801acac: f7f5 ff36 bl 8010b1c + 801acb0: 4603 mov r3, r0 + 801acb2: 827b strh r3, [r7, #18] + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + 801acb4: 8bfa ldrh r2, [r7, #30] + 801acb6: 8a7b ldrh r3, [r7, #18] + 801acb8: 4413 add r3, r2 + 801acba: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 801acbe: db05 blt.n 801accc + 801acc0: 4b27 ldr r3, [pc, #156] ; (801ad60 ) + 801acc2: 22bc movs r2, #188 ; 0xbc + 801acc4: 492a ldr r1, [pc, #168] ; (801ad70 ) + 801acc6: 4828 ldr r0, [pc, #160] ; (801ad68 ) + 801acc8: f001 f9a4 bl 801c014 + pbufs_freed = (u16_t)(pbufs_freed + clen); + 801accc: 8bfa ldrh r2, [r7, #30] + 801acce: 8a7b ldrh r3, [r7, #18] + 801acd0: 4413 add r3, r2 + 801acd2: 83fb strh r3, [r7, #30] + pbuf_free(p); + 801acd4: 69b8 ldr r0, [r7, #24] + 801acd6: f7f5 fe93 bl 8010a00 + } +#endif /* LWIP_ICMP */ + + /* First, free all received pbufs. The individual pbufs need to be released + separately as they have not yet been chained */ + p = ipr->p; + 801acda: 687b ldr r3, [r7, #4] + 801acdc: 685b ldr r3, [r3, #4] + 801acde: 61bb str r3, [r7, #24] + while (p != NULL) { + 801ace0: e01f b.n 801ad22 + struct pbuf *pcur; + iprh = (struct ip_reass_helper *)p->payload; + 801ace2: 69bb ldr r3, [r7, #24] + 801ace4: 685b ldr r3, [r3, #4] + 801ace6: 617b str r3, [r7, #20] + pcur = p; + 801ace8: 69bb ldr r3, [r7, #24] + 801acea: 60fb str r3, [r7, #12] + /* get the next pointer before freeing */ + p = iprh->next_pbuf; + 801acec: 697b ldr r3, [r7, #20] + 801acee: 681b ldr r3, [r3, #0] + 801acf0: 61bb str r3, [r7, #24] + clen = pbuf_clen(pcur); + 801acf2: 68f8 ldr r0, [r7, #12] + 801acf4: f7f5 ff12 bl 8010b1c + 801acf8: 4603 mov r3, r0 + 801acfa: 827b strh r3, [r7, #18] + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + 801acfc: 8bfa ldrh r2, [r7, #30] + 801acfe: 8a7b ldrh r3, [r7, #18] + 801ad00: 4413 add r3, r2 + 801ad02: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 801ad06: db05 blt.n 801ad14 + 801ad08: 4b15 ldr r3, [pc, #84] ; (801ad60 ) + 801ad0a: 22cc movs r2, #204 ; 0xcc + 801ad0c: 4918 ldr r1, [pc, #96] ; (801ad70 ) + 801ad0e: 4816 ldr r0, [pc, #88] ; (801ad68 ) + 801ad10: f001 f980 bl 801c014 + pbufs_freed = (u16_t)(pbufs_freed + clen); + 801ad14: 8bfa ldrh r2, [r7, #30] + 801ad16: 8a7b ldrh r3, [r7, #18] + 801ad18: 4413 add r3, r2 + 801ad1a: 83fb strh r3, [r7, #30] + pbuf_free(pcur); + 801ad1c: 68f8 ldr r0, [r7, #12] + 801ad1e: f7f5 fe6f bl 8010a00 + while (p != NULL) { + 801ad22: 69bb ldr r3, [r7, #24] + 801ad24: 2b00 cmp r3, #0 + 801ad26: d1dc bne.n 801ace2 + } + /* Then, unchain the struct ip_reassdata from the list and free it. */ + ip_reass_dequeue_datagram(ipr, prev); + 801ad28: 6839 ldr r1, [r7, #0] + 801ad2a: 6878 ldr r0, [r7, #4] + 801ad2c: f000 f8c2 bl 801aeb4 + LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed); + 801ad30: 4b10 ldr r3, [pc, #64] ; (801ad74 ) + 801ad32: 881b ldrh r3, [r3, #0] + 801ad34: 8bfa ldrh r2, [r7, #30] + 801ad36: 429a cmp r2, r3 + 801ad38: d905 bls.n 801ad46 + 801ad3a: 4b09 ldr r3, [pc, #36] ; (801ad60 ) + 801ad3c: 22d2 movs r2, #210 ; 0xd2 + 801ad3e: 490e ldr r1, [pc, #56] ; (801ad78 ) + 801ad40: 4809 ldr r0, [pc, #36] ; (801ad68 ) + 801ad42: f001 f967 bl 801c014 + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed); + 801ad46: 4b0b ldr r3, [pc, #44] ; (801ad74 ) + 801ad48: 881a ldrh r2, [r3, #0] + 801ad4a: 8bfb ldrh r3, [r7, #30] + 801ad4c: 1ad3 subs r3, r2, r3 + 801ad4e: b29a uxth r2, r3 + 801ad50: 4b08 ldr r3, [pc, #32] ; (801ad74 ) + 801ad52: 801a strh r2, [r3, #0] + + return pbufs_freed; + 801ad54: 8bfb ldrh r3, [r7, #30] +} + 801ad56: 4618 mov r0, r3 + 801ad58: 3720 adds r7, #32 + 801ad5a: 46bd mov sp, r7 + 801ad5c: bd80 pop {r7, pc} + 801ad5e: bf00 nop + 801ad60: 08021598 .word 0x08021598 + 801ad64: 080215d4 .word 0x080215d4 + 801ad68: 080215e0 .word 0x080215e0 + 801ad6c: 08021608 .word 0x08021608 + 801ad70: 0802161c .word 0x0802161c + 801ad74: 2000d0d8 .word 0x2000d0d8 + 801ad78: 0802163c .word 0x0802163c + +0801ad7c : + * (used for freeing other datagrams if not enough space) + * @return the number of pbufs freed + */ +static int +ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) +{ + 801ad7c: b580 push {r7, lr} + 801ad7e: b08a sub sp, #40 ; 0x28 + 801ad80: af00 add r7, sp, #0 + 801ad82: 6078 str r0, [r7, #4] + 801ad84: 6039 str r1, [r7, #0] + /* @todo Can't we simply remove the last datagram in the + * linked list behind reassdatagrams? + */ + struct ip_reassdata *r, *oldest, *prev, *oldest_prev; + int pbufs_freed = 0, pbufs_freed_current; + 801ad86: 2300 movs r3, #0 + 801ad88: 617b str r3, [r7, #20] + int other_datagrams; + + /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, + * but don't free the datagram that 'fraghdr' belongs to! */ + do { + oldest = NULL; + 801ad8a: 2300 movs r3, #0 + 801ad8c: 623b str r3, [r7, #32] + prev = NULL; + 801ad8e: 2300 movs r3, #0 + 801ad90: 61fb str r3, [r7, #28] + oldest_prev = NULL; + 801ad92: 2300 movs r3, #0 + 801ad94: 61bb str r3, [r7, #24] + other_datagrams = 0; + 801ad96: 2300 movs r3, #0 + 801ad98: 613b str r3, [r7, #16] + r = reassdatagrams; + 801ad9a: 4b28 ldr r3, [pc, #160] ; (801ae3c ) + 801ad9c: 681b ldr r3, [r3, #0] + 801ad9e: 627b str r3, [r7, #36] ; 0x24 + while (r != NULL) { + 801ada0: e030 b.n 801ae04 + if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { + 801ada2: 6a7b ldr r3, [r7, #36] ; 0x24 + 801ada4: 695a ldr r2, [r3, #20] + 801ada6: 687b ldr r3, [r7, #4] + 801ada8: 68db ldr r3, [r3, #12] + 801adaa: 429a cmp r2, r3 + 801adac: d10c bne.n 801adc8 + 801adae: 6a7b ldr r3, [r7, #36] ; 0x24 + 801adb0: 699a ldr r2, [r3, #24] + 801adb2: 687b ldr r3, [r7, #4] + 801adb4: 691b ldr r3, [r3, #16] + 801adb6: 429a cmp r2, r3 + 801adb8: d106 bne.n 801adc8 + 801adba: 6a7b ldr r3, [r7, #36] ; 0x24 + 801adbc: 899a ldrh r2, [r3, #12] + 801adbe: 687b ldr r3, [r7, #4] + 801adc0: 889b ldrh r3, [r3, #4] + 801adc2: b29b uxth r3, r3 + 801adc4: 429a cmp r2, r3 + 801adc6: d014 beq.n 801adf2 + /* Not the same datagram as fraghdr */ + other_datagrams++; + 801adc8: 693b ldr r3, [r7, #16] + 801adca: 3301 adds r3, #1 + 801adcc: 613b str r3, [r7, #16] + if (oldest == NULL) { + 801adce: 6a3b ldr r3, [r7, #32] + 801add0: 2b00 cmp r3, #0 + 801add2: d104 bne.n 801adde + oldest = r; + 801add4: 6a7b ldr r3, [r7, #36] ; 0x24 + 801add6: 623b str r3, [r7, #32] + oldest_prev = prev; + 801add8: 69fb ldr r3, [r7, #28] + 801adda: 61bb str r3, [r7, #24] + 801addc: e009 b.n 801adf2 + } else if (r->timer <= oldest->timer) { + 801adde: 6a7b ldr r3, [r7, #36] ; 0x24 + 801ade0: 7fda ldrb r2, [r3, #31] + 801ade2: 6a3b ldr r3, [r7, #32] + 801ade4: 7fdb ldrb r3, [r3, #31] + 801ade6: 429a cmp r2, r3 + 801ade8: d803 bhi.n 801adf2 + /* older than the previous oldest */ + oldest = r; + 801adea: 6a7b ldr r3, [r7, #36] ; 0x24 + 801adec: 623b str r3, [r7, #32] + oldest_prev = prev; + 801adee: 69fb ldr r3, [r7, #28] + 801adf0: 61bb str r3, [r7, #24] + } + } + if (r->next != NULL) { + 801adf2: 6a7b ldr r3, [r7, #36] ; 0x24 + 801adf4: 681b ldr r3, [r3, #0] + 801adf6: 2b00 cmp r3, #0 + 801adf8: d001 beq.n 801adfe + prev = r; + 801adfa: 6a7b ldr r3, [r7, #36] ; 0x24 + 801adfc: 61fb str r3, [r7, #28] + } + r = r->next; + 801adfe: 6a7b ldr r3, [r7, #36] ; 0x24 + 801ae00: 681b ldr r3, [r3, #0] + 801ae02: 627b str r3, [r7, #36] ; 0x24 + while (r != NULL) { + 801ae04: 6a7b ldr r3, [r7, #36] ; 0x24 + 801ae06: 2b00 cmp r3, #0 + 801ae08: d1cb bne.n 801ada2 + } + if (oldest != NULL) { + 801ae0a: 6a3b ldr r3, [r7, #32] + 801ae0c: 2b00 cmp r3, #0 + 801ae0e: d008 beq.n 801ae22 + pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev); + 801ae10: 69b9 ldr r1, [r7, #24] + 801ae12: 6a38 ldr r0, [r7, #32] + 801ae14: f7ff ff0e bl 801ac34 + 801ae18: 60f8 str r0, [r7, #12] + pbufs_freed += pbufs_freed_current; + 801ae1a: 697a ldr r2, [r7, #20] + 801ae1c: 68fb ldr r3, [r7, #12] + 801ae1e: 4413 add r3, r2 + 801ae20: 617b str r3, [r7, #20] + } + } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); + 801ae22: 697a ldr r2, [r7, #20] + 801ae24: 683b ldr r3, [r7, #0] + 801ae26: 429a cmp r2, r3 + 801ae28: da02 bge.n 801ae30 + 801ae2a: 693b ldr r3, [r7, #16] + 801ae2c: 2b01 cmp r3, #1 + 801ae2e: dcac bgt.n 801ad8a + return pbufs_freed; + 801ae30: 697b ldr r3, [r7, #20] +} + 801ae32: 4618 mov r0, r3 + 801ae34: 3728 adds r7, #40 ; 0x28 + 801ae36: 46bd mov sp, r7 + 801ae38: bd80 pop {r7, pc} + 801ae3a: bf00 nop + 801ae3c: 2000d0d4 .word 0x2000d0d4 + +0801ae40 : + * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) + * @return A pointer to the queue location into which the fragment was enqueued + */ +static struct ip_reassdata * +ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) +{ + 801ae40: b580 push {r7, lr} + 801ae42: b084 sub sp, #16 + 801ae44: af00 add r7, sp, #0 + 801ae46: 6078 str r0, [r7, #4] + 801ae48: 6039 str r1, [r7, #0] +#if ! IP_REASS_FREE_OLDEST + LWIP_UNUSED_ARG(clen); +#endif + + /* No matching previous fragment found, allocate a new reassdata struct */ + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + 801ae4a: 2004 movs r0, #4 + 801ae4c: f7f4 feb2 bl 800fbb4 + 801ae50: 60f8 str r0, [r7, #12] + if (ipr == NULL) { + 801ae52: 68fb ldr r3, [r7, #12] + 801ae54: 2b00 cmp r3, #0 + 801ae56: d110 bne.n 801ae7a +#if IP_REASS_FREE_OLDEST + if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { + 801ae58: 6839 ldr r1, [r7, #0] + 801ae5a: 6878 ldr r0, [r7, #4] + 801ae5c: f7ff ff8e bl 801ad7c + 801ae60: 4602 mov r2, r0 + 801ae62: 683b ldr r3, [r7, #0] + 801ae64: 4293 cmp r3, r2 + 801ae66: dc03 bgt.n 801ae70 + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + 801ae68: 2004 movs r0, #4 + 801ae6a: f7f4 fea3 bl 800fbb4 + 801ae6e: 60f8 str r0, [r7, #12] + } + if (ipr == NULL) + 801ae70: 68fb ldr r3, [r7, #12] + 801ae72: 2b00 cmp r3, #0 + 801ae74: d101 bne.n 801ae7a +#endif /* IP_REASS_FREE_OLDEST */ + { + IPFRAG_STATS_INC(ip_frag.memerr); + LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n")); + return NULL; + 801ae76: 2300 movs r3, #0 + 801ae78: e016 b.n 801aea8 + } + } + memset(ipr, 0, sizeof(struct ip_reassdata)); + 801ae7a: 2220 movs r2, #32 + 801ae7c: 2100 movs r1, #0 + 801ae7e: 68f8 ldr r0, [r7, #12] + 801ae80: f001 f82b bl 801beda + ipr->timer = IP_REASS_MAXAGE; + 801ae84: 68fb ldr r3, [r7, #12] + 801ae86: 220f movs r2, #15 + 801ae88: 77da strb r2, [r3, #31] + + /* enqueue the new structure to the front of the list */ + ipr->next = reassdatagrams; + 801ae8a: 4b09 ldr r3, [pc, #36] ; (801aeb0 ) + 801ae8c: 681a ldr r2, [r3, #0] + 801ae8e: 68fb ldr r3, [r7, #12] + 801ae90: 601a str r2, [r3, #0] + reassdatagrams = ipr; + 801ae92: 4a07 ldr r2, [pc, #28] ; (801aeb0 ) + 801ae94: 68fb ldr r3, [r7, #12] + 801ae96: 6013 str r3, [r2, #0] + /* copy the ip header for later tests and input */ + /* @todo: no ip options supported? */ + SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); + 801ae98: 68fb ldr r3, [r7, #12] + 801ae9a: 3308 adds r3, #8 + 801ae9c: 2214 movs r2, #20 + 801ae9e: 6879 ldr r1, [r7, #4] + 801aea0: 4618 mov r0, r3 + 801aea2: f000 fff2 bl 801be8a + return ipr; + 801aea6: 68fb ldr r3, [r7, #12] +} + 801aea8: 4618 mov r0, r3 + 801aeaa: 3710 adds r7, #16 + 801aeac: 46bd mov sp, r7 + 801aeae: bd80 pop {r7, pc} + 801aeb0: 2000d0d4 .word 0x2000d0d4 + +0801aeb4 : + * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. + * @param ipr points to the queue entry to dequeue + */ +static void +ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + 801aeb4: b580 push {r7, lr} + 801aeb6: b082 sub sp, #8 + 801aeb8: af00 add r7, sp, #0 + 801aeba: 6078 str r0, [r7, #4] + 801aebc: 6039 str r1, [r7, #0] + /* dequeue the reass struct */ + if (reassdatagrams == ipr) { + 801aebe: 4b10 ldr r3, [pc, #64] ; (801af00 ) + 801aec0: 681b ldr r3, [r3, #0] + 801aec2: 687a ldr r2, [r7, #4] + 801aec4: 429a cmp r2, r3 + 801aec6: d104 bne.n 801aed2 + /* it was the first in the list */ + reassdatagrams = ipr->next; + 801aec8: 687b ldr r3, [r7, #4] + 801aeca: 681b ldr r3, [r3, #0] + 801aecc: 4a0c ldr r2, [pc, #48] ; (801af00 ) + 801aece: 6013 str r3, [r2, #0] + 801aed0: e00d b.n 801aeee + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", prev != NULL); + 801aed2: 683b ldr r3, [r7, #0] + 801aed4: 2b00 cmp r3, #0 + 801aed6: d106 bne.n 801aee6 + 801aed8: 4b0a ldr r3, [pc, #40] ; (801af04 ) + 801aeda: f240 1245 movw r2, #325 ; 0x145 + 801aede: 490a ldr r1, [pc, #40] ; (801af08 ) + 801aee0: 480a ldr r0, [pc, #40] ; (801af0c ) + 801aee2: f001 f897 bl 801c014 + prev->next = ipr->next; + 801aee6: 687b ldr r3, [r7, #4] + 801aee8: 681a ldr r2, [r3, #0] + 801aeea: 683b ldr r3, [r7, #0] + 801aeec: 601a str r2, [r3, #0] + } + + /* now we can free the ip_reassdata struct */ + memp_free(MEMP_REASSDATA, ipr); + 801aeee: 6879 ldr r1, [r7, #4] + 801aef0: 2004 movs r0, #4 + 801aef2: f7f4 fed5 bl 800fca0 +} + 801aef6: bf00 nop + 801aef8: 3708 adds r7, #8 + 801aefa: 46bd mov sp, r7 + 801aefc: bd80 pop {r7, pc} + 801aefe: bf00 nop + 801af00: 2000d0d4 .word 0x2000d0d4 + 801af04: 08021598 .word 0x08021598 + 801af08: 08021660 .word 0x08021660 + 801af0c: 080215e0 .word 0x080215e0 + +0801af10 : + * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet) + * @return see IP_REASS_VALIDATE_* defines + */ +static int +ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last) +{ + 801af10: b580 push {r7, lr} + 801af12: b08c sub sp, #48 ; 0x30 + 801af14: af00 add r7, sp, #0 + 801af16: 60f8 str r0, [r7, #12] + 801af18: 60b9 str r1, [r7, #8] + 801af1a: 607a str r2, [r7, #4] + struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL; + 801af1c: 2300 movs r3, #0 + 801af1e: 62bb str r3, [r7, #40] ; 0x28 + struct pbuf *q; + u16_t offset, len; + u8_t hlen; + struct ip_hdr *fraghdr; + int valid = 1; + 801af20: 2301 movs r3, #1 + 801af22: 623b str r3, [r7, #32] + + /* Extract length and fragment offset from current fragment */ + fraghdr = (struct ip_hdr *)new_p->payload; + 801af24: 68bb ldr r3, [r7, #8] + 801af26: 685b ldr r3, [r3, #4] + 801af28: 61fb str r3, [r7, #28] + len = lwip_ntohs(IPH_LEN(fraghdr)); + 801af2a: 69fb ldr r3, [r7, #28] + 801af2c: 885b ldrh r3, [r3, #2] + 801af2e: b29b uxth r3, r3 + 801af30: 4618 mov r0, r3 + 801af32: f7f3 f97d bl 800e230 + 801af36: 4603 mov r3, r0 + 801af38: 837b strh r3, [r7, #26] + hlen = IPH_HL_BYTES(fraghdr); + 801af3a: 69fb ldr r3, [r7, #28] + 801af3c: 781b ldrb r3, [r3, #0] + 801af3e: f003 030f and.w r3, r3, #15 + 801af42: b2db uxtb r3, r3 + 801af44: 009b lsls r3, r3, #2 + 801af46: 767b strb r3, [r7, #25] + if (hlen > len) { + 801af48: 7e7b ldrb r3, [r7, #25] + 801af4a: b29b uxth r3, r3 + 801af4c: 8b7a ldrh r2, [r7, #26] + 801af4e: 429a cmp r2, r3 + 801af50: d202 bcs.n 801af58 + /* invalid datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801af52: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801af56: e135 b.n 801b1c4 + } + len = (u16_t)(len - hlen); + 801af58: 7e7b ldrb r3, [r7, #25] + 801af5a: b29b uxth r3, r3 + 801af5c: 8b7a ldrh r2, [r7, #26] + 801af5e: 1ad3 subs r3, r2, r3 + 801af60: 837b strh r3, [r7, #26] + offset = IPH_OFFSET_BYTES(fraghdr); + 801af62: 69fb ldr r3, [r7, #28] + 801af64: 88db ldrh r3, [r3, #6] + 801af66: b29b uxth r3, r3 + 801af68: 4618 mov r0, r3 + 801af6a: f7f3 f961 bl 800e230 + 801af6e: 4603 mov r3, r0 + 801af70: f3c3 030c ubfx r3, r3, #0, #13 + 801af74: b29b uxth r3, r3 + 801af76: 00db lsls r3, r3, #3 + 801af78: 82fb strh r3, [r7, #22] + /* overwrite the fragment's ip header from the pbuf with our helper struct, + * and setup the embedded helper structure. */ + /* make sure the struct ip_reass_helper fits into the IP header */ + LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", + sizeof(struct ip_reass_helper) <= IP_HLEN); + iprh = (struct ip_reass_helper *)new_p->payload; + 801af7a: 68bb ldr r3, [r7, #8] + 801af7c: 685b ldr r3, [r3, #4] + 801af7e: 62fb str r3, [r7, #44] ; 0x2c + iprh->next_pbuf = NULL; + 801af80: 6afb ldr r3, [r7, #44] ; 0x2c + 801af82: 2200 movs r2, #0 + 801af84: 701a strb r2, [r3, #0] + 801af86: 2200 movs r2, #0 + 801af88: 705a strb r2, [r3, #1] + 801af8a: 2200 movs r2, #0 + 801af8c: 709a strb r2, [r3, #2] + 801af8e: 2200 movs r2, #0 + 801af90: 70da strb r2, [r3, #3] + iprh->start = offset; + 801af92: 6afb ldr r3, [r7, #44] ; 0x2c + 801af94: 8afa ldrh r2, [r7, #22] + 801af96: 809a strh r2, [r3, #4] + iprh->end = (u16_t)(offset + len); + 801af98: 8afa ldrh r2, [r7, #22] + 801af9a: 8b7b ldrh r3, [r7, #26] + 801af9c: 4413 add r3, r2 + 801af9e: b29a uxth r2, r3 + 801afa0: 6afb ldr r3, [r7, #44] ; 0x2c + 801afa2: 80da strh r2, [r3, #6] + if (iprh->end < offset) { + 801afa4: 6afb ldr r3, [r7, #44] ; 0x2c + 801afa6: 88db ldrh r3, [r3, #6] + 801afa8: b29b uxth r3, r3 + 801afaa: 8afa ldrh r2, [r7, #22] + 801afac: 429a cmp r2, r3 + 801afae: d902 bls.n 801afb6 + /* u16_t overflow, cannot handle this */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801afb0: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801afb4: e106 b.n 801b1c4 + } + + /* Iterate through until we either get to the end of the list (append), + * or we find one with a larger offset (insert). */ + for (q = ipr->p; q != NULL;) { + 801afb6: 68fb ldr r3, [r7, #12] + 801afb8: 685b ldr r3, [r3, #4] + 801afba: 627b str r3, [r7, #36] ; 0x24 + 801afbc: e068 b.n 801b090 + iprh_tmp = (struct ip_reass_helper *)q->payload; + 801afbe: 6a7b ldr r3, [r7, #36] ; 0x24 + 801afc0: 685b ldr r3, [r3, #4] + 801afc2: 613b str r3, [r7, #16] + if (iprh->start < iprh_tmp->start) { + 801afc4: 6afb ldr r3, [r7, #44] ; 0x2c + 801afc6: 889b ldrh r3, [r3, #4] + 801afc8: b29a uxth r2, r3 + 801afca: 693b ldr r3, [r7, #16] + 801afcc: 889b ldrh r3, [r3, #4] + 801afce: b29b uxth r3, r3 + 801afd0: 429a cmp r2, r3 + 801afd2: d235 bcs.n 801b040 + /* the new pbuf should be inserted before this */ + iprh->next_pbuf = q; + 801afd4: 6afb ldr r3, [r7, #44] ; 0x2c + 801afd6: 6a7a ldr r2, [r7, #36] ; 0x24 + 801afd8: 601a str r2, [r3, #0] + if (iprh_prev != NULL) { + 801afda: 6abb ldr r3, [r7, #40] ; 0x28 + 801afdc: 2b00 cmp r3, #0 + 801afde: d020 beq.n 801b022 + /* not the fragment with the lowest offset */ +#if IP_REASS_CHECK_OVERLAP + if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { + 801afe0: 6afb ldr r3, [r7, #44] ; 0x2c + 801afe2: 889b ldrh r3, [r3, #4] + 801afe4: b29a uxth r2, r3 + 801afe6: 6abb ldr r3, [r7, #40] ; 0x28 + 801afe8: 88db ldrh r3, [r3, #6] + 801afea: b29b uxth r3, r3 + 801afec: 429a cmp r2, r3 + 801afee: d307 bcc.n 801b000 + 801aff0: 6afb ldr r3, [r7, #44] ; 0x2c + 801aff2: 88db ldrh r3, [r3, #6] + 801aff4: b29a uxth r2, r3 + 801aff6: 693b ldr r3, [r7, #16] + 801aff8: 889b ldrh r3, [r3, #4] + 801affa: b29b uxth r3, r3 + 801affc: 429a cmp r2, r3 + 801affe: d902 bls.n 801b006 + /* fragment overlaps with previous or following, throw away */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801b000: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801b004: e0de b.n 801b1c4 + } +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + 801b006: 6abb ldr r3, [r7, #40] ; 0x28 + 801b008: 68ba ldr r2, [r7, #8] + 801b00a: 601a str r2, [r3, #0] + if (iprh_prev->end != iprh->start) { + 801b00c: 6abb ldr r3, [r7, #40] ; 0x28 + 801b00e: 88db ldrh r3, [r3, #6] + 801b010: b29a uxth r2, r3 + 801b012: 6afb ldr r3, [r7, #44] ; 0x2c + 801b014: 889b ldrh r3, [r3, #4] + 801b016: b29b uxth r3, r3 + 801b018: 429a cmp r2, r3 + 801b01a: d03d beq.n 801b098 + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + 801b01c: 2300 movs r3, #0 + 801b01e: 623b str r3, [r7, #32] + } +#endif /* IP_REASS_CHECK_OVERLAP */ + /* fragment with the lowest offset */ + ipr->p = new_p; + } + break; + 801b020: e03a b.n 801b098 + if (iprh->end > iprh_tmp->start) { + 801b022: 6afb ldr r3, [r7, #44] ; 0x2c + 801b024: 88db ldrh r3, [r3, #6] + 801b026: b29a uxth r2, r3 + 801b028: 693b ldr r3, [r7, #16] + 801b02a: 889b ldrh r3, [r3, #4] + 801b02c: b29b uxth r3, r3 + 801b02e: 429a cmp r2, r3 + 801b030: d902 bls.n 801b038 + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801b032: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801b036: e0c5 b.n 801b1c4 + ipr->p = new_p; + 801b038: 68fb ldr r3, [r7, #12] + 801b03a: 68ba ldr r2, [r7, #8] + 801b03c: 605a str r2, [r3, #4] + break; + 801b03e: e02b b.n 801b098 + } else if (iprh->start == iprh_tmp->start) { + 801b040: 6afb ldr r3, [r7, #44] ; 0x2c + 801b042: 889b ldrh r3, [r3, #4] + 801b044: b29a uxth r2, r3 + 801b046: 693b ldr r3, [r7, #16] + 801b048: 889b ldrh r3, [r3, #4] + 801b04a: b29b uxth r3, r3 + 801b04c: 429a cmp r2, r3 + 801b04e: d102 bne.n 801b056 + /* received the same datagram twice: no need to keep the datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801b050: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801b054: e0b6 b.n 801b1c4 +#if IP_REASS_CHECK_OVERLAP + } else if (iprh->start < iprh_tmp->end) { + 801b056: 6afb ldr r3, [r7, #44] ; 0x2c + 801b058: 889b ldrh r3, [r3, #4] + 801b05a: b29a uxth r2, r3 + 801b05c: 693b ldr r3, [r7, #16] + 801b05e: 88db ldrh r3, [r3, #6] + 801b060: b29b uxth r3, r3 + 801b062: 429a cmp r2, r3 + 801b064: d202 bcs.n 801b06c + /* overlap: no need to keep the new datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 801b066: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801b06a: e0ab b.n 801b1c4 +#endif /* IP_REASS_CHECK_OVERLAP */ + } else { + /* Check if the fragments received so far have no holes. */ + if (iprh_prev != NULL) { + 801b06c: 6abb ldr r3, [r7, #40] ; 0x28 + 801b06e: 2b00 cmp r3, #0 + 801b070: d009 beq.n 801b086 + if (iprh_prev->end != iprh_tmp->start) { + 801b072: 6abb ldr r3, [r7, #40] ; 0x28 + 801b074: 88db ldrh r3, [r3, #6] + 801b076: b29a uxth r2, r3 + 801b078: 693b ldr r3, [r7, #16] + 801b07a: 889b ldrh r3, [r3, #4] + 801b07c: b29b uxth r3, r3 + 801b07e: 429a cmp r2, r3 + 801b080: d001 beq.n 801b086 + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + 801b082: 2300 movs r3, #0 + 801b084: 623b str r3, [r7, #32] + } + } + } + q = iprh_tmp->next_pbuf; + 801b086: 693b ldr r3, [r7, #16] + 801b088: 681b ldr r3, [r3, #0] + 801b08a: 627b str r3, [r7, #36] ; 0x24 + iprh_prev = iprh_tmp; + 801b08c: 693b ldr r3, [r7, #16] + 801b08e: 62bb str r3, [r7, #40] ; 0x28 + for (q = ipr->p; q != NULL;) { + 801b090: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b092: 2b00 cmp r3, #0 + 801b094: d193 bne.n 801afbe + 801b096: e000 b.n 801b09a + break; + 801b098: bf00 nop + } + + /* If q is NULL, then we made it to the end of the list. Determine what to do now */ + if (q == NULL) { + 801b09a: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b09c: 2b00 cmp r3, #0 + 801b09e: d12d bne.n 801b0fc + if (iprh_prev != NULL) { + 801b0a0: 6abb ldr r3, [r7, #40] ; 0x28 + 801b0a2: 2b00 cmp r3, #0 + 801b0a4: d01c beq.n 801b0e0 + /* this is (for now), the fragment with the highest offset: + * chain it to the last fragment */ +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); + 801b0a6: 6abb ldr r3, [r7, #40] ; 0x28 + 801b0a8: 88db ldrh r3, [r3, #6] + 801b0aa: b29a uxth r2, r3 + 801b0ac: 6afb ldr r3, [r7, #44] ; 0x2c + 801b0ae: 889b ldrh r3, [r3, #4] + 801b0b0: b29b uxth r3, r3 + 801b0b2: 429a cmp r2, r3 + 801b0b4: d906 bls.n 801b0c4 + 801b0b6: 4b45 ldr r3, [pc, #276] ; (801b1cc ) + 801b0b8: f44f 72db mov.w r2, #438 ; 0x1b6 + 801b0bc: 4944 ldr r1, [pc, #272] ; (801b1d0 ) + 801b0be: 4845 ldr r0, [pc, #276] ; (801b1d4 ) + 801b0c0: f000 ffa8 bl 801c014 +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + 801b0c4: 6abb ldr r3, [r7, #40] ; 0x28 + 801b0c6: 68ba ldr r2, [r7, #8] + 801b0c8: 601a str r2, [r3, #0] + if (iprh_prev->end != iprh->start) { + 801b0ca: 6abb ldr r3, [r7, #40] ; 0x28 + 801b0cc: 88db ldrh r3, [r3, #6] + 801b0ce: b29a uxth r2, r3 + 801b0d0: 6afb ldr r3, [r7, #44] ; 0x2c + 801b0d2: 889b ldrh r3, [r3, #4] + 801b0d4: b29b uxth r3, r3 + 801b0d6: 429a cmp r2, r3 + 801b0d8: d010 beq.n 801b0fc + valid = 0; + 801b0da: 2300 movs r3, #0 + 801b0dc: 623b str r3, [r7, #32] + 801b0de: e00d b.n 801b0fc + } + } else { +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("no previous fragment, this must be the first fragment!", + 801b0e0: 68fb ldr r3, [r7, #12] + 801b0e2: 685b ldr r3, [r3, #4] + 801b0e4: 2b00 cmp r3, #0 + 801b0e6: d006 beq.n 801b0f6 + 801b0e8: 4b38 ldr r3, [pc, #224] ; (801b1cc ) + 801b0ea: f44f 72df mov.w r2, #446 ; 0x1be + 801b0ee: 493a ldr r1, [pc, #232] ; (801b1d8 ) + 801b0f0: 4838 ldr r0, [pc, #224] ; (801b1d4 ) + 801b0f2: f000 ff8f bl 801c014 + ipr->p == NULL); +#endif /* IP_REASS_CHECK_OVERLAP */ + /* this is the first fragment we ever received for this ip datagram */ + ipr->p = new_p; + 801b0f6: 68fb ldr r3, [r7, #12] + 801b0f8: 68ba ldr r2, [r7, #8] + 801b0fa: 605a str r2, [r3, #4] + } + } + + /* At this point, the validation part begins: */ + /* If we already received the last fragment */ + if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) { + 801b0fc: 687b ldr r3, [r7, #4] + 801b0fe: 2b00 cmp r3, #0 + 801b100: d105 bne.n 801b10e + 801b102: 68fb ldr r3, [r7, #12] + 801b104: 7f9b ldrb r3, [r3, #30] + 801b106: f003 0301 and.w r3, r3, #1 + 801b10a: 2b00 cmp r3, #0 + 801b10c: d059 beq.n 801b1c2 + /* and had no holes so far */ + if (valid) { + 801b10e: 6a3b ldr r3, [r7, #32] + 801b110: 2b00 cmp r3, #0 + 801b112: d04f beq.n 801b1b4 + /* then check if the rest of the fragments is here */ + /* Check if the queue starts with the first datagram */ + if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) { + 801b114: 68fb ldr r3, [r7, #12] + 801b116: 685b ldr r3, [r3, #4] + 801b118: 2b00 cmp r3, #0 + 801b11a: d006 beq.n 801b12a + 801b11c: 68fb ldr r3, [r7, #12] + 801b11e: 685b ldr r3, [r3, #4] + 801b120: 685b ldr r3, [r3, #4] + 801b122: 889b ldrh r3, [r3, #4] + 801b124: b29b uxth r3, r3 + 801b126: 2b00 cmp r3, #0 + 801b128: d002 beq.n 801b130 + valid = 0; + 801b12a: 2300 movs r3, #0 + 801b12c: 623b str r3, [r7, #32] + 801b12e: e041 b.n 801b1b4 + } else { + /* and check that there are no holes after this datagram */ + iprh_prev = iprh; + 801b130: 6afb ldr r3, [r7, #44] ; 0x2c + 801b132: 62bb str r3, [r7, #40] ; 0x28 + q = iprh->next_pbuf; + 801b134: 6afb ldr r3, [r7, #44] ; 0x2c + 801b136: 681b ldr r3, [r3, #0] + 801b138: 627b str r3, [r7, #36] ; 0x24 + while (q != NULL) { + 801b13a: e012 b.n 801b162 + iprh = (struct ip_reass_helper *)q->payload; + 801b13c: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b13e: 685b ldr r3, [r3, #4] + 801b140: 62fb str r3, [r7, #44] ; 0x2c + if (iprh_prev->end != iprh->start) { + 801b142: 6abb ldr r3, [r7, #40] ; 0x28 + 801b144: 88db ldrh r3, [r3, #6] + 801b146: b29a uxth r2, r3 + 801b148: 6afb ldr r3, [r7, #44] ; 0x2c + 801b14a: 889b ldrh r3, [r3, #4] + 801b14c: b29b uxth r3, r3 + 801b14e: 429a cmp r2, r3 + 801b150: d002 beq.n 801b158 + valid = 0; + 801b152: 2300 movs r3, #0 + 801b154: 623b str r3, [r7, #32] + break; + 801b156: e007 b.n 801b168 + } + iprh_prev = iprh; + 801b158: 6afb ldr r3, [r7, #44] ; 0x2c + 801b15a: 62bb str r3, [r7, #40] ; 0x28 + q = iprh->next_pbuf; + 801b15c: 6afb ldr r3, [r7, #44] ; 0x2c + 801b15e: 681b ldr r3, [r3, #0] + 801b160: 627b str r3, [r7, #36] ; 0x24 + while (q != NULL) { + 801b162: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b164: 2b00 cmp r3, #0 + 801b166: d1e9 bne.n 801b13c + } + /* if still valid, all fragments are received + * (because to the MF==0 already arrived */ + if (valid) { + 801b168: 6a3b ldr r3, [r7, #32] + 801b16a: 2b00 cmp r3, #0 + 801b16c: d022 beq.n 801b1b4 + LWIP_ASSERT("sanity check", ipr->p != NULL); + 801b16e: 68fb ldr r3, [r7, #12] + 801b170: 685b ldr r3, [r3, #4] + 801b172: 2b00 cmp r3, #0 + 801b174: d106 bne.n 801b184 + 801b176: 4b15 ldr r3, [pc, #84] ; (801b1cc ) + 801b178: f240 12df movw r2, #479 ; 0x1df + 801b17c: 4917 ldr r1, [pc, #92] ; (801b1dc ) + 801b17e: 4815 ldr r0, [pc, #84] ; (801b1d4 ) + 801b180: f000 ff48 bl 801c014 + LWIP_ASSERT("sanity check", + 801b184: 68fb ldr r3, [r7, #12] + 801b186: 685b ldr r3, [r3, #4] + 801b188: 685b ldr r3, [r3, #4] + 801b18a: 6afa ldr r2, [r7, #44] ; 0x2c + 801b18c: 429a cmp r2, r3 + 801b18e: d106 bne.n 801b19e + 801b190: 4b0e ldr r3, [pc, #56] ; (801b1cc ) + 801b192: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 801b196: 4911 ldr r1, [pc, #68] ; (801b1dc ) + 801b198: 480e ldr r0, [pc, #56] ; (801b1d4 ) + 801b19a: f000 ff3b bl 801c014 + ((struct ip_reass_helper *)ipr->p->payload) != iprh); + LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", + 801b19e: 6afb ldr r3, [r7, #44] ; 0x2c + 801b1a0: 681b ldr r3, [r3, #0] + 801b1a2: 2b00 cmp r3, #0 + 801b1a4: d006 beq.n 801b1b4 + 801b1a6: 4b09 ldr r3, [pc, #36] ; (801b1cc ) + 801b1a8: f44f 72f1 mov.w r2, #482 ; 0x1e2 + 801b1ac: 490c ldr r1, [pc, #48] ; (801b1e0 ) + 801b1ae: 4809 ldr r0, [pc, #36] ; (801b1d4 ) + 801b1b0: f000 ff30 bl 801c014 + } + } + /* If valid is 0 here, there are some fragments missing in the middle + * (since MF == 0 has already arrived). Such datagrams simply time out if + * no more fragments are received... */ + return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED; + 801b1b4: 6a3b ldr r3, [r7, #32] + 801b1b6: 2b00 cmp r3, #0 + 801b1b8: bf14 ite ne + 801b1ba: 2301 movne r3, #1 + 801b1bc: 2300 moveq r3, #0 + 801b1be: b2db uxtb r3, r3 + 801b1c0: e000 b.n 801b1c4 + } + /* If we come here, not all fragments were received, yet! */ + return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */ + 801b1c2: 2300 movs r3, #0 +} + 801b1c4: 4618 mov r0, r3 + 801b1c6: 3730 adds r7, #48 ; 0x30 + 801b1c8: 46bd mov sp, r7 + 801b1ca: bd80 pop {r7, pc} + 801b1cc: 08021598 .word 0x08021598 + 801b1d0: 0802167c .word 0x0802167c + 801b1d4: 080215e0 .word 0x080215e0 + 801b1d8: 0802169c .word 0x0802169c + 801b1dc: 080216d4 .word 0x080216d4 + 801b1e0: 080216e4 .word 0x080216e4 + +0801b1e4 : + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip4_reass(struct pbuf *p) +{ + 801b1e4: b580 push {r7, lr} + 801b1e6: b08e sub sp, #56 ; 0x38 + 801b1e8: af00 add r7, sp, #0 + 801b1ea: 6078 str r0, [r7, #4] + int is_last; + + IPFRAG_STATS_INC(ip_frag.recv); + MIB2_STATS_INC(mib2.ipreasmreqds); + + fraghdr = (struct ip_hdr *)p->payload; + 801b1ec: 687b ldr r3, [r7, #4] + 801b1ee: 685b ldr r3, [r3, #4] + 801b1f0: 62bb str r3, [r7, #40] ; 0x28 + + if (IPH_HL_BYTES(fraghdr) != IP_HLEN) { + 801b1f2: 6abb ldr r3, [r7, #40] ; 0x28 + 801b1f4: 781b ldrb r3, [r3, #0] + 801b1f6: f003 030f and.w r3, r3, #15 + 801b1fa: b2db uxtb r3, r3 + 801b1fc: 009b lsls r3, r3, #2 + 801b1fe: b2db uxtb r3, r3 + 801b200: 2b14 cmp r3, #20 + 801b202: f040 8171 bne.w 801b4e8 + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n")); + IPFRAG_STATS_INC(ip_frag.err); + goto nullreturn; + } + + offset = IPH_OFFSET_BYTES(fraghdr); + 801b206: 6abb ldr r3, [r7, #40] ; 0x28 + 801b208: 88db ldrh r3, [r3, #6] + 801b20a: b29b uxth r3, r3 + 801b20c: 4618 mov r0, r3 + 801b20e: f7f3 f80f bl 800e230 + 801b212: 4603 mov r3, r0 + 801b214: f3c3 030c ubfx r3, r3, #0, #13 + 801b218: b29b uxth r3, r3 + 801b21a: 00db lsls r3, r3, #3 + 801b21c: 84fb strh r3, [r7, #38] ; 0x26 + len = lwip_ntohs(IPH_LEN(fraghdr)); + 801b21e: 6abb ldr r3, [r7, #40] ; 0x28 + 801b220: 885b ldrh r3, [r3, #2] + 801b222: b29b uxth r3, r3 + 801b224: 4618 mov r0, r3 + 801b226: f7f3 f803 bl 800e230 + 801b22a: 4603 mov r3, r0 + 801b22c: 84bb strh r3, [r7, #36] ; 0x24 + hlen = IPH_HL_BYTES(fraghdr); + 801b22e: 6abb ldr r3, [r7, #40] ; 0x28 + 801b230: 781b ldrb r3, [r3, #0] + 801b232: f003 030f and.w r3, r3, #15 + 801b236: b2db uxtb r3, r3 + 801b238: 009b lsls r3, r3, #2 + 801b23a: f887 3023 strb.w r3, [r7, #35] ; 0x23 + if (hlen > len) { + 801b23e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 801b242: b29b uxth r3, r3 + 801b244: 8cba ldrh r2, [r7, #36] ; 0x24 + 801b246: 429a cmp r2, r3 + 801b248: f0c0 8150 bcc.w 801b4ec + /* invalid datagram */ + goto nullreturn; + } + len = (u16_t)(len - hlen); + 801b24c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 801b250: b29b uxth r3, r3 + 801b252: 8cba ldrh r2, [r7, #36] ; 0x24 + 801b254: 1ad3 subs r3, r2, r3 + 801b256: 84bb strh r3, [r7, #36] ; 0x24 + + /* Check if we are allowed to enqueue more datagrams. */ + clen = pbuf_clen(p); + 801b258: 6878 ldr r0, [r7, #4] + 801b25a: f7f5 fc5f bl 8010b1c + 801b25e: 4603 mov r3, r0 + 801b260: 843b strh r3, [r7, #32] + if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { + 801b262: 4b8c ldr r3, [pc, #560] ; (801b494 ) + 801b264: 881b ldrh r3, [r3, #0] + 801b266: 461a mov r2, r3 + 801b268: 8c3b ldrh r3, [r7, #32] + 801b26a: 4413 add r3, r2 + 801b26c: 2b0a cmp r3, #10 + 801b26e: dd10 ble.n 801b292 +#if IP_REASS_FREE_OLDEST + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + 801b270: 8c3b ldrh r3, [r7, #32] + 801b272: 4619 mov r1, r3 + 801b274: 6ab8 ldr r0, [r7, #40] ; 0x28 + 801b276: f7ff fd81 bl 801ad7c + 801b27a: 4603 mov r3, r0 + 801b27c: 2b00 cmp r3, #0 + 801b27e: f000 8137 beq.w 801b4f0 + ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) + 801b282: 4b84 ldr r3, [pc, #528] ; (801b494 ) + 801b284: 881b ldrh r3, [r3, #0] + 801b286: 461a mov r2, r3 + 801b288: 8c3b ldrh r3, [r7, #32] + 801b28a: 4413 add r3, r2 + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + 801b28c: 2b0a cmp r3, #10 + 801b28e: f300 812f bgt.w 801b4f0 + } + } + + /* Look for the datagram the fragment belongs to in the current datagram queue, + * remembering the previous in the queue for later dequeueing. */ + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + 801b292: 4b81 ldr r3, [pc, #516] ; (801b498 ) + 801b294: 681b ldr r3, [r3, #0] + 801b296: 633b str r3, [r7, #48] ; 0x30 + 801b298: e015 b.n 801b2c6 + /* Check if the incoming fragment matches the one currently present + in the reassembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { + 801b29a: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b29c: 695a ldr r2, [r3, #20] + 801b29e: 6abb ldr r3, [r7, #40] ; 0x28 + 801b2a0: 68db ldr r3, [r3, #12] + 801b2a2: 429a cmp r2, r3 + 801b2a4: d10c bne.n 801b2c0 + 801b2a6: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2a8: 699a ldr r2, [r3, #24] + 801b2aa: 6abb ldr r3, [r7, #40] ; 0x28 + 801b2ac: 691b ldr r3, [r3, #16] + 801b2ae: 429a cmp r2, r3 + 801b2b0: d106 bne.n 801b2c0 + 801b2b2: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2b4: 899a ldrh r2, [r3, #12] + 801b2b6: 6abb ldr r3, [r7, #40] ; 0x28 + 801b2b8: 889b ldrh r3, [r3, #4] + 801b2ba: b29b uxth r3, r3 + 801b2bc: 429a cmp r2, r3 + 801b2be: d006 beq.n 801b2ce + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + 801b2c0: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2c2: 681b ldr r3, [r3, #0] + 801b2c4: 633b str r3, [r7, #48] ; 0x30 + 801b2c6: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2c8: 2b00 cmp r3, #0 + 801b2ca: d1e6 bne.n 801b29a + 801b2cc: e000 b.n 801b2d0 + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n", + lwip_ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + break; + 801b2ce: bf00 nop + } + } + + if (ipr == NULL) { + 801b2d0: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2d2: 2b00 cmp r3, #0 + 801b2d4: d109 bne.n 801b2ea + /* Enqueue a new datagram into the datagram queue */ + ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); + 801b2d6: 8c3b ldrh r3, [r7, #32] + 801b2d8: 4619 mov r1, r3 + 801b2da: 6ab8 ldr r0, [r7, #40] ; 0x28 + 801b2dc: f7ff fdb0 bl 801ae40 + 801b2e0: 6338 str r0, [r7, #48] ; 0x30 + /* Bail if unable to enqueue */ + if (ipr == NULL) { + 801b2e2: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b2e4: 2b00 cmp r3, #0 + 801b2e6: d11c bne.n 801b322 + goto nullreturn; + 801b2e8: e105 b.n 801b4f6 + } + } else { + if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + 801b2ea: 6abb ldr r3, [r7, #40] ; 0x28 + 801b2ec: 88db ldrh r3, [r3, #6] + 801b2ee: b29b uxth r3, r3 + 801b2f0: 4618 mov r0, r3 + 801b2f2: f7f2 ff9d bl 800e230 + 801b2f6: 4603 mov r3, r0 + 801b2f8: f3c3 030c ubfx r3, r3, #0, #13 + 801b2fc: 2b00 cmp r3, #0 + 801b2fe: d110 bne.n 801b322 + ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { + 801b300: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b302: 89db ldrh r3, [r3, #14] + 801b304: 4618 mov r0, r3 + 801b306: f7f2 ff93 bl 800e230 + 801b30a: 4603 mov r3, r0 + 801b30c: f3c3 030c ubfx r3, r3, #0, #13 + if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + 801b310: 2b00 cmp r3, #0 + 801b312: d006 beq.n 801b322 + /* ipr->iphdr is not the header from the first fragment, but fraghdr is + * -> copy fraghdr into ipr->iphdr since we want to have the header + * of the first fragment (for ICMP time exceeded and later, for copying + * all options, if supported)*/ + SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); + 801b314: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b316: 3308 adds r3, #8 + 801b318: 2214 movs r2, #20 + 801b31a: 6ab9 ldr r1, [r7, #40] ; 0x28 + 801b31c: 4618 mov r0, r3 + 801b31e: f000 fdb4 bl 801be8a + + /* At this point, we have either created a new entry or pointing + * to an existing one */ + + /* check for 'no more fragments', and update queue entry*/ + is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0; + 801b322: 6abb ldr r3, [r7, #40] ; 0x28 + 801b324: 88db ldrh r3, [r3, #6] + 801b326: b29b uxth r3, r3 + 801b328: f003 0320 and.w r3, r3, #32 + 801b32c: 2b00 cmp r3, #0 + 801b32e: bf0c ite eq + 801b330: 2301 moveq r3, #1 + 801b332: 2300 movne r3, #0 + 801b334: b2db uxtb r3, r3 + 801b336: 61fb str r3, [r7, #28] + if (is_last) { + 801b338: 69fb ldr r3, [r7, #28] + 801b33a: 2b00 cmp r3, #0 + 801b33c: d00e beq.n 801b35c + u16_t datagram_len = (u16_t)(offset + len); + 801b33e: 8cfa ldrh r2, [r7, #38] ; 0x26 + 801b340: 8cbb ldrh r3, [r7, #36] ; 0x24 + 801b342: 4413 add r3, r2 + 801b344: 837b strh r3, [r7, #26] + if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) { + 801b346: 8b7a ldrh r2, [r7, #26] + 801b348: 8cfb ldrh r3, [r7, #38] ; 0x26 + 801b34a: 429a cmp r2, r3 + 801b34c: f0c0 80a0 bcc.w 801b490 + 801b350: 8b7b ldrh r3, [r7, #26] + 801b352: f64f 72eb movw r2, #65515 ; 0xffeb + 801b356: 4293 cmp r3, r2 + 801b358: f200 809a bhi.w 801b490 + goto nullreturn_ipr; + } + } + /* find the right place to insert this pbuf */ + /* @todo: trim pbufs if fragments are overlapping */ + valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last); + 801b35c: 69fa ldr r2, [r7, #28] + 801b35e: 6879 ldr r1, [r7, #4] + 801b360: 6b38 ldr r0, [r7, #48] ; 0x30 + 801b362: f7ff fdd5 bl 801af10 + 801b366: 6178 str r0, [r7, #20] + if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) { + 801b368: 697b ldr r3, [r7, #20] + 801b36a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 801b36e: f000 809b beq.w 801b4a8 + /* if we come here, the pbuf has been enqueued */ + + /* Track the current number of pbufs current 'in-flight', in order to limit + the number of fragments that may be enqueued at any one time + (overflow checked by testing against IP_REASS_MAX_PBUFS) */ + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen); + 801b372: 4b48 ldr r3, [pc, #288] ; (801b494 ) + 801b374: 881a ldrh r2, [r3, #0] + 801b376: 8c3b ldrh r3, [r7, #32] + 801b378: 4413 add r3, r2 + 801b37a: b29a uxth r2, r3 + 801b37c: 4b45 ldr r3, [pc, #276] ; (801b494 ) + 801b37e: 801a strh r2, [r3, #0] + if (is_last) { + 801b380: 69fb ldr r3, [r7, #28] + 801b382: 2b00 cmp r3, #0 + 801b384: d00d beq.n 801b3a2 + u16_t datagram_len = (u16_t)(offset + len); + 801b386: 8cfa ldrh r2, [r7, #38] ; 0x26 + 801b388: 8cbb ldrh r3, [r7, #36] ; 0x24 + 801b38a: 4413 add r3, r2 + 801b38c: 827b strh r3, [r7, #18] + ipr->datagram_len = datagram_len; + 801b38e: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b390: 8a7a ldrh r2, [r7, #18] + 801b392: 839a strh r2, [r3, #28] + ipr->flags |= IP_REASS_FLAG_LASTFRAG; + 801b394: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b396: 7f9b ldrb r3, [r3, #30] + 801b398: f043 0301 orr.w r3, r3, #1 + 801b39c: b2da uxtb r2, r3 + 801b39e: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3a0: 779a strb r2, [r3, #30] + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip4_reass: last fragment seen, total len %"S16_F"\n", + ipr->datagram_len)); + } + + if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) { + 801b3a2: 697b ldr r3, [r7, #20] + 801b3a4: 2b01 cmp r3, #1 + 801b3a6: d171 bne.n 801b48c + struct ip_reassdata *ipr_prev; + /* the totally last fragment (flag more fragments = 0) was received at least + * once AND all fragments are received */ + u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN); + 801b3a8: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3aa: 8b9b ldrh r3, [r3, #28] + 801b3ac: 3314 adds r3, #20 + 801b3ae: 823b strh r3, [r7, #16] + + /* save the second pbuf before copying the header over the pointer */ + r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf; + 801b3b0: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3b2: 685b ldr r3, [r3, #4] + 801b3b4: 685b ldr r3, [r3, #4] + 801b3b6: 681b ldr r3, [r3, #0] + 801b3b8: 637b str r3, [r7, #52] ; 0x34 + + /* copy the original ip header back to the first pbuf */ + fraghdr = (struct ip_hdr *)(ipr->p->payload); + 801b3ba: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3bc: 685b ldr r3, [r3, #4] + 801b3be: 685b ldr r3, [r3, #4] + 801b3c0: 62bb str r3, [r7, #40] ; 0x28 + SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); + 801b3c2: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3c4: 3308 adds r3, #8 + 801b3c6: 2214 movs r2, #20 + 801b3c8: 4619 mov r1, r3 + 801b3ca: 6ab8 ldr r0, [r7, #40] ; 0x28 + 801b3cc: f000 fd5d bl 801be8a + IPH_LEN_SET(fraghdr, lwip_htons(datagram_len)); + 801b3d0: 8a3b ldrh r3, [r7, #16] + 801b3d2: 4618 mov r0, r3 + 801b3d4: f7f2 ff2c bl 800e230 + 801b3d8: 4603 mov r3, r0 + 801b3da: 461a mov r2, r3 + 801b3dc: 6abb ldr r3, [r7, #40] ; 0x28 + 801b3de: 805a strh r2, [r3, #2] + IPH_OFFSET_SET(fraghdr, 0); + 801b3e0: 6abb ldr r3, [r7, #40] ; 0x28 + 801b3e2: 2200 movs r2, #0 + 801b3e4: 719a strb r2, [r3, #6] + 801b3e6: 2200 movs r2, #0 + 801b3e8: 71da strb r2, [r3, #7] + IPH_CHKSUM_SET(fraghdr, 0); + 801b3ea: 6abb ldr r3, [r7, #40] ; 0x28 + 801b3ec: 2200 movs r2, #0 + 801b3ee: 729a strb r2, [r3, #10] + 801b3f0: 2200 movs r2, #0 + 801b3f2: 72da strb r2, [r3, #11] + IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); + } +#endif /* CHECKSUM_GEN_IP */ + + p = ipr->p; + 801b3f4: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b3f6: 685b ldr r3, [r3, #4] + 801b3f8: 607b str r3, [r7, #4] + + /* chain together the pbufs contained within the reass_data list. */ + while (r != NULL) { + 801b3fa: e00d b.n 801b418 + iprh = (struct ip_reass_helper *)r->payload; + 801b3fc: 6b7b ldr r3, [r7, #52] ; 0x34 + 801b3fe: 685b ldr r3, [r3, #4] + 801b400: 60fb str r3, [r7, #12] + + /* hide the ip header for every succeeding fragment */ + pbuf_remove_header(r, IP_HLEN); + 801b402: 2114 movs r1, #20 + 801b404: 6b78 ldr r0, [r7, #52] ; 0x34 + 801b406: f7f5 fa75 bl 80108f4 + pbuf_cat(p, r); + 801b40a: 6b79 ldr r1, [r7, #52] ; 0x34 + 801b40c: 6878 ldr r0, [r7, #4] + 801b40e: f7f5 fbc5 bl 8010b9c + r = iprh->next_pbuf; + 801b412: 68fb ldr r3, [r7, #12] + 801b414: 681b ldr r3, [r3, #0] + 801b416: 637b str r3, [r7, #52] ; 0x34 + while (r != NULL) { + 801b418: 6b7b ldr r3, [r7, #52] ; 0x34 + 801b41a: 2b00 cmp r3, #0 + 801b41c: d1ee bne.n 801b3fc + } + + /* find the previous entry in the linked list */ + if (ipr == reassdatagrams) { + 801b41e: 4b1e ldr r3, [pc, #120] ; (801b498 ) + 801b420: 681b ldr r3, [r3, #0] + 801b422: 6b3a ldr r2, [r7, #48] ; 0x30 + 801b424: 429a cmp r2, r3 + 801b426: d102 bne.n 801b42e + ipr_prev = NULL; + 801b428: 2300 movs r3, #0 + 801b42a: 62fb str r3, [r7, #44] ; 0x2c + 801b42c: e010 b.n 801b450 + } else { + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + 801b42e: 4b1a ldr r3, [pc, #104] ; (801b498 ) + 801b430: 681b ldr r3, [r3, #0] + 801b432: 62fb str r3, [r7, #44] ; 0x2c + 801b434: e007 b.n 801b446 + if (ipr_prev->next == ipr) { + 801b436: 6afb ldr r3, [r7, #44] ; 0x2c + 801b438: 681b ldr r3, [r3, #0] + 801b43a: 6b3a ldr r2, [r7, #48] ; 0x30 + 801b43c: 429a cmp r2, r3 + 801b43e: d006 beq.n 801b44e + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + 801b440: 6afb ldr r3, [r7, #44] ; 0x2c + 801b442: 681b ldr r3, [r3, #0] + 801b444: 62fb str r3, [r7, #44] ; 0x2c + 801b446: 6afb ldr r3, [r7, #44] ; 0x2c + 801b448: 2b00 cmp r3, #0 + 801b44a: d1f4 bne.n 801b436 + 801b44c: e000 b.n 801b450 + break; + 801b44e: bf00 nop + } + } + } + + /* release the sources allocate for the fragment queue entry */ + ip_reass_dequeue_datagram(ipr, ipr_prev); + 801b450: 6af9 ldr r1, [r7, #44] ; 0x2c + 801b452: 6b38 ldr r0, [r7, #48] ; 0x30 + 801b454: f7ff fd2e bl 801aeb4 + + /* and adjust the number of pbufs currently queued for reassembly. */ + clen = pbuf_clen(p); + 801b458: 6878 ldr r0, [r7, #4] + 801b45a: f7f5 fb5f bl 8010b1c + 801b45e: 4603 mov r3, r0 + 801b460: 843b strh r3, [r7, #32] + LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen); + 801b462: 4b0c ldr r3, [pc, #48] ; (801b494 ) + 801b464: 881b ldrh r3, [r3, #0] + 801b466: 8c3a ldrh r2, [r7, #32] + 801b468: 429a cmp r2, r3 + 801b46a: d906 bls.n 801b47a + 801b46c: 4b0b ldr r3, [pc, #44] ; (801b49c ) + 801b46e: f240 229b movw r2, #667 ; 0x29b + 801b472: 490b ldr r1, [pc, #44] ; (801b4a0 ) + 801b474: 480b ldr r0, [pc, #44] ; (801b4a4 ) + 801b476: f000 fdcd bl 801c014 + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen); + 801b47a: 4b06 ldr r3, [pc, #24] ; (801b494 ) + 801b47c: 881a ldrh r2, [r3, #0] + 801b47e: 8c3b ldrh r3, [r7, #32] + 801b480: 1ad3 subs r3, r2, r3 + 801b482: b29a uxth r2, r3 + 801b484: 4b03 ldr r3, [pc, #12] ; (801b494 ) + 801b486: 801a strh r2, [r3, #0] + + MIB2_STATS_INC(mib2.ipreasmoks); + + /* Return the pbuf chain */ + return p; + 801b488: 687b ldr r3, [r7, #4] + 801b48a: e038 b.n 801b4fe + } + /* the datagram is not (yet?) reassembled completely */ + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); + return NULL; + 801b48c: 2300 movs r3, #0 + 801b48e: e036 b.n 801b4fe + goto nullreturn_ipr; + 801b490: bf00 nop + 801b492: e00a b.n 801b4aa + 801b494: 2000d0d8 .word 0x2000d0d8 + 801b498: 2000d0d4 .word 0x2000d0d4 + 801b49c: 08021598 .word 0x08021598 + 801b4a0: 08021708 .word 0x08021708 + 801b4a4: 080215e0 .word 0x080215e0 + goto nullreturn_ipr; + 801b4a8: bf00 nop + +nullreturn_ipr: + LWIP_ASSERT("ipr != NULL", ipr != NULL); + 801b4aa: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b4ac: 2b00 cmp r3, #0 + 801b4ae: d106 bne.n 801b4be + 801b4b0: 4b15 ldr r3, [pc, #84] ; (801b508 ) + 801b4b2: f44f 722a mov.w r2, #680 ; 0x2a8 + 801b4b6: 4915 ldr r1, [pc, #84] ; (801b50c ) + 801b4b8: 4815 ldr r0, [pc, #84] ; (801b510 ) + 801b4ba: f000 fdab bl 801c014 + if (ipr->p == NULL) { + 801b4be: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b4c0: 685b ldr r3, [r3, #4] + 801b4c2: 2b00 cmp r3, #0 + 801b4c4: d116 bne.n 801b4f4 + /* dropped pbuf after creating a new datagram entry: remove the entry, too */ + LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams); + 801b4c6: 4b13 ldr r3, [pc, #76] ; (801b514 ) + 801b4c8: 681b ldr r3, [r3, #0] + 801b4ca: 6b3a ldr r2, [r7, #48] ; 0x30 + 801b4cc: 429a cmp r2, r3 + 801b4ce: d006 beq.n 801b4de + 801b4d0: 4b0d ldr r3, [pc, #52] ; (801b508 ) + 801b4d2: f240 22ab movw r2, #683 ; 0x2ab + 801b4d6: 4910 ldr r1, [pc, #64] ; (801b518 ) + 801b4d8: 480d ldr r0, [pc, #52] ; (801b510 ) + 801b4da: f000 fd9b bl 801c014 + ip_reass_dequeue_datagram(ipr, NULL); + 801b4de: 2100 movs r1, #0 + 801b4e0: 6b38 ldr r0, [r7, #48] ; 0x30 + 801b4e2: f7ff fce7 bl 801aeb4 + 801b4e6: e006 b.n 801b4f6 + goto nullreturn; + 801b4e8: bf00 nop + 801b4ea: e004 b.n 801b4f6 + goto nullreturn; + 801b4ec: bf00 nop + 801b4ee: e002 b.n 801b4f6 + goto nullreturn; + 801b4f0: bf00 nop + 801b4f2: e000 b.n 801b4f6 + } + +nullreturn: + 801b4f4: bf00 nop + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n")); + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + 801b4f6: 6878 ldr r0, [r7, #4] + 801b4f8: f7f5 fa82 bl 8010a00 + return NULL; + 801b4fc: 2300 movs r3, #0 +} + 801b4fe: 4618 mov r0, r3 + 801b500: 3738 adds r7, #56 ; 0x38 + 801b502: 46bd mov sp, r7 + 801b504: bd80 pop {r7, pc} + 801b506: bf00 nop + 801b508: 08021598 .word 0x08021598 + 801b50c: 08021724 .word 0x08021724 + 801b510: 080215e0 .word 0x080215e0 + 801b514: 2000d0d4 .word 0x2000d0d4 + 801b518: 08021730 .word 0x08021730 + +0801b51c : +#if IP_FRAG +#if !LWIP_NETIF_TX_SINGLE_PBUF +/** Allocate a new struct pbuf_custom_ref */ +static struct pbuf_custom_ref * +ip_frag_alloc_pbuf_custom_ref(void) +{ + 801b51c: b580 push {r7, lr} + 801b51e: af00 add r7, sp, #0 + return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF); + 801b520: 2005 movs r0, #5 + 801b522: f7f4 fb47 bl 800fbb4 + 801b526: 4603 mov r3, r0 +} + 801b528: 4618 mov r0, r3 + 801b52a: bd80 pop {r7, pc} + +0801b52c : + +/** Free a struct pbuf_custom_ref */ +static void +ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p) +{ + 801b52c: b580 push {r7, lr} + 801b52e: b082 sub sp, #8 + 801b530: af00 add r7, sp, #0 + 801b532: 6078 str r0, [r7, #4] + LWIP_ASSERT("p != NULL", p != NULL); + 801b534: 687b ldr r3, [r7, #4] + 801b536: 2b00 cmp r3, #0 + 801b538: d106 bne.n 801b548 + 801b53a: 4b07 ldr r3, [pc, #28] ; (801b558 ) + 801b53c: f44f 7231 mov.w r2, #708 ; 0x2c4 + 801b540: 4906 ldr r1, [pc, #24] ; (801b55c ) + 801b542: 4807 ldr r0, [pc, #28] ; (801b560 ) + 801b544: f000 fd66 bl 801c014 + memp_free(MEMP_FRAG_PBUF, p); + 801b548: 6879 ldr r1, [r7, #4] + 801b54a: 2005 movs r0, #5 + 801b54c: f7f4 fba8 bl 800fca0 +} + 801b550: bf00 nop + 801b552: 3708 adds r7, #8 + 801b554: 46bd mov sp, r7 + 801b556: bd80 pop {r7, pc} + 801b558: 08021598 .word 0x08021598 + 801b55c: 08021750 .word 0x08021750 + 801b560: 080215e0 .word 0x080215e0 + +0801b564 : + +/** Free-callback function to free a 'struct pbuf_custom_ref', called by + * pbuf_free. */ +static void +ipfrag_free_pbuf_custom(struct pbuf *p) +{ + 801b564: b580 push {r7, lr} + 801b566: b084 sub sp, #16 + 801b568: af00 add r7, sp, #0 + 801b56a: 6078 str r0, [r7, #4] + struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p; + 801b56c: 687b ldr r3, [r7, #4] + 801b56e: 60fb str r3, [r7, #12] + LWIP_ASSERT("pcr != NULL", pcr != NULL); + 801b570: 68fb ldr r3, [r7, #12] + 801b572: 2b00 cmp r3, #0 + 801b574: d106 bne.n 801b584 + 801b576: 4b11 ldr r3, [pc, #68] ; (801b5bc ) + 801b578: f240 22ce movw r2, #718 ; 0x2ce + 801b57c: 4910 ldr r1, [pc, #64] ; (801b5c0 ) + 801b57e: 4811 ldr r0, [pc, #68] ; (801b5c4 ) + 801b580: f000 fd48 bl 801c014 + LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p); + 801b584: 68fa ldr r2, [r7, #12] + 801b586: 687b ldr r3, [r7, #4] + 801b588: 429a cmp r2, r3 + 801b58a: d006 beq.n 801b59a + 801b58c: 4b0b ldr r3, [pc, #44] ; (801b5bc ) + 801b58e: f240 22cf movw r2, #719 ; 0x2cf + 801b592: 490d ldr r1, [pc, #52] ; (801b5c8 ) + 801b594: 480b ldr r0, [pc, #44] ; (801b5c4 ) + 801b596: f000 fd3d bl 801c014 + if (pcr->original != NULL) { + 801b59a: 68fb ldr r3, [r7, #12] + 801b59c: 695b ldr r3, [r3, #20] + 801b59e: 2b00 cmp r3, #0 + 801b5a0: d004 beq.n 801b5ac + pbuf_free(pcr->original); + 801b5a2: 68fb ldr r3, [r7, #12] + 801b5a4: 695b ldr r3, [r3, #20] + 801b5a6: 4618 mov r0, r3 + 801b5a8: f7f5 fa2a bl 8010a00 + } + ip_frag_free_pbuf_custom_ref(pcr); + 801b5ac: 68f8 ldr r0, [r7, #12] + 801b5ae: f7ff ffbd bl 801b52c +} + 801b5b2: bf00 nop + 801b5b4: 3710 adds r7, #16 + 801b5b6: 46bd mov sp, r7 + 801b5b8: bd80 pop {r7, pc} + 801b5ba: bf00 nop + 801b5bc: 08021598 .word 0x08021598 + 801b5c0: 0802175c .word 0x0802175c + 801b5c4: 080215e0 .word 0x080215e0 + 801b5c8: 08021768 .word 0x08021768 + +0801b5cc : + * + * @return ERR_OK if sent successfully, err_t otherwise + */ +err_t +ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest) +{ + 801b5cc: b580 push {r7, lr} + 801b5ce: b094 sub sp, #80 ; 0x50 + 801b5d0: af02 add r7, sp, #8 + 801b5d2: 60f8 str r0, [r7, #12] + 801b5d4: 60b9 str r1, [r7, #8] + 801b5d6: 607a str r2, [r7, #4] + struct pbuf *rambuf; +#if !LWIP_NETIF_TX_SINGLE_PBUF + struct pbuf *newpbuf; + u16_t newpbuflen = 0; + 801b5d8: 2300 movs r3, #0 + 801b5da: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + u16_t left_to_copy; +#endif + struct ip_hdr *original_iphdr; + struct ip_hdr *iphdr; + const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8); + 801b5de: 68bb ldr r3, [r7, #8] + 801b5e0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801b5e2: 3b14 subs r3, #20 + 801b5e4: 2b00 cmp r3, #0 + 801b5e6: da00 bge.n 801b5ea + 801b5e8: 3307 adds r3, #7 + 801b5ea: 10db asrs r3, r3, #3 + 801b5ec: 877b strh r3, [r7, #58] ; 0x3a + u16_t left, fragsize; + u16_t ofo; + int last; + u16_t poff = IP_HLEN; + 801b5ee: 2314 movs r3, #20 + 801b5f0: 87fb strh r3, [r7, #62] ; 0x3e + u16_t tmp; + int mf_set; + + original_iphdr = (struct ip_hdr *)p->payload; + 801b5f2: 68fb ldr r3, [r7, #12] + 801b5f4: 685b ldr r3, [r3, #4] + 801b5f6: 637b str r3, [r7, #52] ; 0x34 + iphdr = original_iphdr; + 801b5f8: 6b7b ldr r3, [r7, #52] ; 0x34 + 801b5fa: 633b str r3, [r7, #48] ; 0x30 + if (IPH_HL_BYTES(iphdr) != IP_HLEN) { + 801b5fc: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b5fe: 781b ldrb r3, [r3, #0] + 801b600: f003 030f and.w r3, r3, #15 + 801b604: b2db uxtb r3, r3 + 801b606: 009b lsls r3, r3, #2 + 801b608: b2db uxtb r3, r3 + 801b60a: 2b14 cmp r3, #20 + 801b60c: d002 beq.n 801b614 + /* ip4_frag() does not support IP options */ + return ERR_VAL; + 801b60e: f06f 0305 mvn.w r3, #5 + 801b612: e110 b.n 801b836 + } + LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL); + 801b614: 68fb ldr r3, [r7, #12] + 801b616: 895b ldrh r3, [r3, #10] + 801b618: 2b13 cmp r3, #19 + 801b61a: d809 bhi.n 801b630 + 801b61c: 4b88 ldr r3, [pc, #544] ; (801b840 ) + 801b61e: f44f 723f mov.w r2, #764 ; 0x2fc + 801b622: 4988 ldr r1, [pc, #544] ; (801b844 ) + 801b624: 4888 ldr r0, [pc, #544] ; (801b848 ) + 801b626: f000 fcf5 bl 801c014 + 801b62a: f06f 0305 mvn.w r3, #5 + 801b62e: e102 b.n 801b836 + + /* Save original offset */ + tmp = lwip_ntohs(IPH_OFFSET(iphdr)); + 801b630: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b632: 88db ldrh r3, [r3, #6] + 801b634: b29b uxth r3, r3 + 801b636: 4618 mov r0, r3 + 801b638: f7f2 fdfa bl 800e230 + 801b63c: 4603 mov r3, r0 + 801b63e: 87bb strh r3, [r7, #60] ; 0x3c + ofo = tmp & IP_OFFMASK; + 801b640: 8fbb ldrh r3, [r7, #60] ; 0x3c + 801b642: f3c3 030c ubfx r3, r3, #0, #13 + 801b646: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + /* already fragmented? if so, the last fragment we create must have MF, too */ + mf_set = tmp & IP_MF; + 801b64a: 8fbb ldrh r3, [r7, #60] ; 0x3c + 801b64c: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 801b650: 62fb str r3, [r7, #44] ; 0x2c + + left = (u16_t)(p->tot_len - IP_HLEN); + 801b652: 68fb ldr r3, [r7, #12] + 801b654: 891b ldrh r3, [r3, #8] + 801b656: 3b14 subs r3, #20 + 801b658: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + + while (left) { + 801b65c: e0e1 b.n 801b822 + /* Fill this fragment */ + fragsize = LWIP_MIN(left, (u16_t)(nfb * 8)); + 801b65e: 8f7b ldrh r3, [r7, #58] ; 0x3a + 801b660: 00db lsls r3, r3, #3 + 801b662: b29b uxth r3, r3 + 801b664: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 801b668: 4293 cmp r3, r2 + 801b66a: bf28 it cs + 801b66c: 4613 movcs r3, r2 + 801b66e: 857b strh r3, [r7, #42] ; 0x2a + /* When not using a static buffer, create a chain of pbufs. + * The first will be a PBUF_RAM holding the link and IP header. + * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, + * but limited to the size of an mtu. + */ + rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); + 801b670: f44f 7220 mov.w r2, #640 ; 0x280 + 801b674: 2114 movs r1, #20 + 801b676: 200e movs r0, #14 + 801b678: f7f4 fede bl 8010438 + 801b67c: 6278 str r0, [r7, #36] ; 0x24 + if (rambuf == NULL) { + 801b67e: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b680: 2b00 cmp r3, #0 + 801b682: f000 80d5 beq.w 801b830 + goto memerr; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + 801b686: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b688: 895b ldrh r3, [r3, #10] + 801b68a: 2b13 cmp r3, #19 + 801b68c: d806 bhi.n 801b69c + 801b68e: 4b6c ldr r3, [pc, #432] ; (801b840 ) + 801b690: f44f 7249 mov.w r2, #804 ; 0x324 + 801b694: 496d ldr r1, [pc, #436] ; (801b84c ) + 801b696: 486c ldr r0, [pc, #432] ; (801b848 ) + 801b698: f000 fcbc bl 801c014 + (rambuf->len >= (IP_HLEN))); + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + 801b69c: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b69e: 685b ldr r3, [r3, #4] + 801b6a0: 2214 movs r2, #20 + 801b6a2: 6b79 ldr r1, [r7, #52] ; 0x34 + 801b6a4: 4618 mov r0, r3 + 801b6a6: f000 fbf0 bl 801be8a + iphdr = (struct ip_hdr *)rambuf->payload; + 801b6aa: 6a7b ldr r3, [r7, #36] ; 0x24 + 801b6ac: 685b ldr r3, [r3, #4] + 801b6ae: 633b str r3, [r7, #48] ; 0x30 + + left_to_copy = fragsize; + 801b6b0: 8d7b ldrh r3, [r7, #42] ; 0x2a + 801b6b2: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + while (left_to_copy) { + 801b6b6: e064 b.n 801b782 + struct pbuf_custom_ref *pcr; + u16_t plen = (u16_t)(p->len - poff); + 801b6b8: 68fb ldr r3, [r7, #12] + 801b6ba: 895a ldrh r2, [r3, #10] + 801b6bc: 8ffb ldrh r3, [r7, #62] ; 0x3e + 801b6be: 1ad3 subs r3, r2, r3 + 801b6c0: 83fb strh r3, [r7, #30] + LWIP_ASSERT("p->len >= poff", p->len >= poff); + 801b6c2: 68fb ldr r3, [r7, #12] + 801b6c4: 895b ldrh r3, [r3, #10] + 801b6c6: 8ffa ldrh r2, [r7, #62] ; 0x3e + 801b6c8: 429a cmp r2, r3 + 801b6ca: d906 bls.n 801b6da + 801b6cc: 4b5c ldr r3, [pc, #368] ; (801b840 ) + 801b6ce: f240 322d movw r2, #813 ; 0x32d + 801b6d2: 495f ldr r1, [pc, #380] ; (801b850 ) + 801b6d4: 485c ldr r0, [pc, #368] ; (801b848 ) + 801b6d6: f000 fc9d bl 801c014 + newpbuflen = LWIP_MIN(left_to_copy, plen); + 801b6da: 8bfa ldrh r2, [r7, #30] + 801b6dc: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 801b6e0: 4293 cmp r3, r2 + 801b6e2: bf28 it cs + 801b6e4: 4613 movcs r3, r2 + 801b6e6: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + /* Is this pbuf already empty? */ + if (!newpbuflen) { + 801b6ea: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 801b6ee: 2b00 cmp r3, #0 + 801b6f0: d105 bne.n 801b6fe + poff = 0; + 801b6f2: 2300 movs r3, #0 + 801b6f4: 87fb strh r3, [r7, #62] ; 0x3e + p = p->next; + 801b6f6: 68fb ldr r3, [r7, #12] + 801b6f8: 681b ldr r3, [r3, #0] + 801b6fa: 60fb str r3, [r7, #12] + continue; + 801b6fc: e041 b.n 801b782 + } + pcr = ip_frag_alloc_pbuf_custom_ref(); + 801b6fe: f7ff ff0d bl 801b51c + 801b702: 61b8 str r0, [r7, #24] + if (pcr == NULL) { + 801b704: 69bb ldr r3, [r7, #24] + 801b706: 2b00 cmp r3, #0 + 801b708: d103 bne.n 801b712 + pbuf_free(rambuf); + 801b70a: 6a78 ldr r0, [r7, #36] ; 0x24 + 801b70c: f7f5 f978 bl 8010a00 + goto memerr; + 801b710: e08f b.n 801b832 + } + /* Mirror this pbuf, although we might not need all of it. */ + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, + 801b712: 69b8 ldr r0, [r7, #24] + (u8_t *)p->payload + poff, newpbuflen); + 801b714: 68fb ldr r3, [r7, #12] + 801b716: 685a ldr r2, [r3, #4] + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, + 801b718: 8ffb ldrh r3, [r7, #62] ; 0x3e + 801b71a: 4413 add r3, r2 + 801b71c: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46 + 801b720: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 + 801b724: 9201 str r2, [sp, #4] + 801b726: 9300 str r3, [sp, #0] + 801b728: 4603 mov r3, r0 + 801b72a: 2241 movs r2, #65 ; 0x41 + 801b72c: 2000 movs r0, #0 + 801b72e: f7f4 ffad bl 801068c + 801b732: 6178 str r0, [r7, #20] + if (newpbuf == NULL) { + 801b734: 697b ldr r3, [r7, #20] + 801b736: 2b00 cmp r3, #0 + 801b738: d106 bne.n 801b748 + ip_frag_free_pbuf_custom_ref(pcr); + 801b73a: 69b8 ldr r0, [r7, #24] + 801b73c: f7ff fef6 bl 801b52c + pbuf_free(rambuf); + 801b740: 6a78 ldr r0, [r7, #36] ; 0x24 + 801b742: f7f5 f95d bl 8010a00 + goto memerr; + 801b746: e074 b.n 801b832 + } + pbuf_ref(p); + 801b748: 68f8 ldr r0, [r7, #12] + 801b74a: f7f5 f9ff bl 8010b4c + pcr->original = p; + 801b74e: 69bb ldr r3, [r7, #24] + 801b750: 68fa ldr r2, [r7, #12] + 801b752: 615a str r2, [r3, #20] + pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; + 801b754: 69bb ldr r3, [r7, #24] + 801b756: 4a3f ldr r2, [pc, #252] ; (801b854 ) + 801b758: 611a str r2, [r3, #16] + + /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain + * so that it is removed when pbuf_dechain is later called on rambuf. + */ + pbuf_cat(rambuf, newpbuf); + 801b75a: 6979 ldr r1, [r7, #20] + 801b75c: 6a78 ldr r0, [r7, #36] ; 0x24 + 801b75e: f7f5 fa1d bl 8010b9c + left_to_copy = (u16_t)(left_to_copy - newpbuflen); + 801b762: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44 + 801b766: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 801b76a: 1ad3 subs r3, r2, r3 + 801b76c: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + if (left_to_copy) { + 801b770: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 801b774: 2b00 cmp r3, #0 + 801b776: d004 beq.n 801b782 + poff = 0; + 801b778: 2300 movs r3, #0 + 801b77a: 87fb strh r3, [r7, #62] ; 0x3e + p = p->next; + 801b77c: 68fb ldr r3, [r7, #12] + 801b77e: 681b ldr r3, [r3, #0] + 801b780: 60fb str r3, [r7, #12] + while (left_to_copy) { + 801b782: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 801b786: 2b00 cmp r3, #0 + 801b788: d196 bne.n 801b6b8 + } + } + poff = (u16_t)(poff + newpbuflen); + 801b78a: 8ffa ldrh r2, [r7, #62] ; 0x3e + 801b78c: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 801b790: 4413 add r3, r2 + 801b792: 87fb strh r3, [r7, #62] ; 0x3e +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + /* Correct header */ + last = (left <= netif->mtu - IP_HLEN); + 801b794: 68bb ldr r3, [r7, #8] + 801b796: 8d1b ldrh r3, [r3, #40] ; 0x28 + 801b798: f1a3 0213 sub.w r2, r3, #19 + 801b79c: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 801b7a0: 429a cmp r2, r3 + 801b7a2: bfcc ite gt + 801b7a4: 2301 movgt r3, #1 + 801b7a6: 2300 movle r3, #0 + 801b7a8: b2db uxtb r3, r3 + 801b7aa: 623b str r3, [r7, #32] + + /* Set new offset and MF flag */ + tmp = (IP_OFFMASK & (ofo)); + 801b7ac: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 801b7b0: f3c3 030c ubfx r3, r3, #0, #13 + 801b7b4: 87bb strh r3, [r7, #60] ; 0x3c + if (!last || mf_set) { + 801b7b6: 6a3b ldr r3, [r7, #32] + 801b7b8: 2b00 cmp r3, #0 + 801b7ba: d002 beq.n 801b7c2 + 801b7bc: 6afb ldr r3, [r7, #44] ; 0x2c + 801b7be: 2b00 cmp r3, #0 + 801b7c0: d003 beq.n 801b7ca + /* the last fragment has MF set if the input frame had it */ + tmp = tmp | IP_MF; + 801b7c2: 8fbb ldrh r3, [r7, #60] ; 0x3c + 801b7c4: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 801b7c8: 87bb strh r3, [r7, #60] ; 0x3c + } + IPH_OFFSET_SET(iphdr, lwip_htons(tmp)); + 801b7ca: 8fbb ldrh r3, [r7, #60] ; 0x3c + 801b7cc: 4618 mov r0, r3 + 801b7ce: f7f2 fd2f bl 800e230 + 801b7d2: 4603 mov r3, r0 + 801b7d4: 461a mov r2, r3 + 801b7d6: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b7d8: 80da strh r2, [r3, #6] + IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN))); + 801b7da: 8d7b ldrh r3, [r7, #42] ; 0x2a + 801b7dc: 3314 adds r3, #20 + 801b7de: b29b uxth r3, r3 + 801b7e0: 4618 mov r0, r3 + 801b7e2: f7f2 fd25 bl 800e230 + 801b7e6: 4603 mov r3, r0 + 801b7e8: 461a mov r2, r3 + 801b7ea: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b7ec: 805a strh r2, [r3, #2] + IPH_CHKSUM_SET(iphdr, 0); + 801b7ee: 6b3b ldr r3, [r7, #48] ; 0x30 + 801b7f0: 2200 movs r2, #0 + 801b7f2: 729a strb r2, [r3, #10] + 801b7f4: 2200 movs r2, #0 + 801b7f6: 72da strb r2, [r3, #11] +#endif /* CHECKSUM_GEN_IP */ + + /* No need for separate header pbuf - we allowed room for it in rambuf + * when allocated. + */ + netif->output(netif, rambuf, dest); + 801b7f8: 68bb ldr r3, [r7, #8] + 801b7fa: 695b ldr r3, [r3, #20] + 801b7fc: 687a ldr r2, [r7, #4] + 801b7fe: 6a79 ldr r1, [r7, #36] ; 0x24 + 801b800: 68b8 ldr r0, [r7, #8] + 801b802: 4798 blx r3 + * recreate it next time round the loop. If we're lucky the hardware + * will have already sent the packet, the free will really free, and + * there will be zero memory penalty. + */ + + pbuf_free(rambuf); + 801b804: 6a78 ldr r0, [r7, #36] ; 0x24 + 801b806: f7f5 f8fb bl 8010a00 + left = (u16_t)(left - fragsize); + 801b80a: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 801b80e: 8d7b ldrh r3, [r7, #42] ; 0x2a + 801b810: 1ad3 subs r3, r2, r3 + 801b812: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + ofo = (u16_t)(ofo + nfb); + 801b816: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40 + 801b81a: 8f7b ldrh r3, [r7, #58] ; 0x3a + 801b81c: 4413 add r3, r2 + 801b81e: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + while (left) { + 801b822: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 801b826: 2b00 cmp r3, #0 + 801b828: f47f af19 bne.w 801b65e + } + MIB2_STATS_INC(mib2.ipfragoks); + return ERR_OK; + 801b82c: 2300 movs r3, #0 + 801b82e: e002 b.n 801b836 + goto memerr; + 801b830: bf00 nop +memerr: + MIB2_STATS_INC(mib2.ipfragfails); + return ERR_MEM; + 801b832: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 801b836: 4618 mov r0, r3 + 801b838: 3748 adds r7, #72 ; 0x48 + 801b83a: 46bd mov sp, r7 + 801b83c: bd80 pop {r7, pc} + 801b83e: bf00 nop + 801b840: 08021598 .word 0x08021598 + 801b844: 08021774 .word 0x08021774 + 801b848: 080215e0 .word 0x080215e0 + 801b84c: 08021790 .word 0x08021790 + 801b850: 080217b0 .word 0x080217b0 + 801b854: 0801b565 .word 0x0801b565 + +0801b858 : + * @see ETHARP_SUPPORT_VLAN + * @see LWIP_HOOK_VLAN_CHECK + */ +err_t +ethernet_input(struct pbuf *p, struct netif *netif) +{ + 801b858: b580 push {r7, lr} + 801b85a: b086 sub sp, #24 + 801b85c: af00 add r7, sp, #0 + 801b85e: 6078 str r0, [r7, #4] + 801b860: 6039 str r1, [r7, #0] + struct eth_hdr *ethhdr; + u16_t type; +#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6 + u16_t next_hdr_offset = SIZEOF_ETH_HDR; + 801b862: 230e movs r3, #14 + 801b864: 82fb strh r3, [r7, #22] +#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */ + + LWIP_ASSERT_CORE_LOCKED(); + + if (p->len <= SIZEOF_ETH_HDR) { + 801b866: 687b ldr r3, [r7, #4] + 801b868: 895b ldrh r3, [r3, #10] + 801b86a: 2b0e cmp r3, #14 + 801b86c: d96e bls.n 801b94c + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinerrors); + goto free_and_return; + } + + if (p->if_idx == NETIF_NO_INDEX) { + 801b86e: 687b ldr r3, [r7, #4] + 801b870: 7bdb ldrb r3, [r3, #15] + 801b872: 2b00 cmp r3, #0 + 801b874: d106 bne.n 801b884 + p->if_idx = netif_get_index(netif); + 801b876: 683b ldr r3, [r7, #0] + 801b878: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 801b87c: 3301 adds r3, #1 + 801b87e: b2da uxtb r2, r3 + 801b880: 687b ldr r3, [r7, #4] + 801b882: 73da strb r2, [r3, #15] + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = (struct eth_hdr *)p->payload; + 801b884: 687b ldr r3, [r7, #4] + 801b886: 685b ldr r3, [r3, #4] + 801b888: 613b str r3, [r7, #16] + (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5], + (unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2], + (unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5], + lwip_htons(ethhdr->type))); + + type = ethhdr->type; + 801b88a: 693b ldr r3, [r7, #16] + 801b88c: 7b1a ldrb r2, [r3, #12] + 801b88e: 7b5b ldrb r3, [r3, #13] + 801b890: 021b lsls r3, r3, #8 + 801b892: 4313 orrs r3, r2 + 801b894: 81fb strh r3, [r7, #14] + +#if LWIP_ARP_FILTER_NETIF + netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type)); +#endif /* LWIP_ARP_FILTER_NETIF*/ + + if (ethhdr->dest.addr[0] & 1) { + 801b896: 693b ldr r3, [r7, #16] + 801b898: 781b ldrb r3, [r3, #0] + 801b89a: f003 0301 and.w r3, r3, #1 + 801b89e: 2b00 cmp r3, #0 + 801b8a0: d023 beq.n 801b8ea + /* this might be a multicast or broadcast packet */ + if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) { + 801b8a2: 693b ldr r3, [r7, #16] + 801b8a4: 781b ldrb r3, [r3, #0] + 801b8a6: 2b01 cmp r3, #1 + 801b8a8: d10f bne.n 801b8ca +#if LWIP_IPV4 + if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && + 801b8aa: 693b ldr r3, [r7, #16] + 801b8ac: 785b ldrb r3, [r3, #1] + 801b8ae: 2b00 cmp r3, #0 + 801b8b0: d11b bne.n 801b8ea + (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) { + 801b8b2: 693b ldr r3, [r7, #16] + 801b8b4: 789b ldrb r3, [r3, #2] + if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && + 801b8b6: 2b5e cmp r3, #94 ; 0x5e + 801b8b8: d117 bne.n 801b8ea + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + 801b8ba: 687b ldr r3, [r7, #4] + 801b8bc: 7b5b ldrb r3, [r3, #13] + 801b8be: f043 0310 orr.w r3, r3, #16 + 801b8c2: b2da uxtb r2, r3 + 801b8c4: 687b ldr r3, [r7, #4] + 801b8c6: 735a strb r2, [r3, #13] + 801b8c8: e00f b.n 801b8ea + (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) { + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + } +#endif /* LWIP_IPV6 */ + else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) { + 801b8ca: 693b ldr r3, [r7, #16] + 801b8cc: 2206 movs r2, #6 + 801b8ce: 4928 ldr r1, [pc, #160] ; (801b970 ) + 801b8d0: 4618 mov r0, r3 + 801b8d2: f000 faca bl 801be6a + 801b8d6: 4603 mov r3, r0 + 801b8d8: 2b00 cmp r3, #0 + 801b8da: d106 bne.n 801b8ea + /* mark the pbuf as link-layer broadcast */ + p->flags |= PBUF_FLAG_LLBCAST; + 801b8dc: 687b ldr r3, [r7, #4] + 801b8de: 7b5b ldrb r3, [r3, #13] + 801b8e0: f043 0308 orr.w r3, r3, #8 + 801b8e4: b2da uxtb r2, r3 + 801b8e6: 687b ldr r3, [r7, #4] + 801b8e8: 735a strb r2, [r3, #13] + } + } + + switch (type) { + 801b8ea: 89fb ldrh r3, [r7, #14] + 801b8ec: 2b08 cmp r3, #8 + 801b8ee: d003 beq.n 801b8f8 + 801b8f0: f5b3 6fc1 cmp.w r3, #1544 ; 0x608 + 801b8f4: d014 beq.n 801b920 + } +#endif + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinunknownprotos); + goto free_and_return; + 801b8f6: e032 b.n 801b95e + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + 801b8f8: 683b ldr r3, [r7, #0] + 801b8fa: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801b8fe: f003 0308 and.w r3, r3, #8 + 801b902: 2b00 cmp r3, #0 + 801b904: d024 beq.n 801b950 + if (pbuf_remove_header(p, next_hdr_offset)) { + 801b906: 8afb ldrh r3, [r7, #22] + 801b908: 4619 mov r1, r3 + 801b90a: 6878 ldr r0, [r7, #4] + 801b90c: f7f4 fff2 bl 80108f4 + 801b910: 4603 mov r3, r0 + 801b912: 2b00 cmp r3, #0 + 801b914: d11e bne.n 801b954 + ip4_input(p, netif); + 801b916: 6839 ldr r1, [r7, #0] + 801b918: 6878 ldr r0, [r7, #4] + 801b91a: f7fe fd49 bl 801a3b0 + break; + 801b91e: e013 b.n 801b948 + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + 801b920: 683b ldr r3, [r7, #0] + 801b922: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 801b926: f003 0308 and.w r3, r3, #8 + 801b92a: 2b00 cmp r3, #0 + 801b92c: d014 beq.n 801b958 + if (pbuf_remove_header(p, next_hdr_offset)) { + 801b92e: 8afb ldrh r3, [r7, #22] + 801b930: 4619 mov r1, r3 + 801b932: 6878 ldr r0, [r7, #4] + 801b934: f7f4 ffde bl 80108f4 + 801b938: 4603 mov r3, r0 + 801b93a: 2b00 cmp r3, #0 + 801b93c: d10e bne.n 801b95c + etharp_input(p, netif); + 801b93e: 6839 ldr r1, [r7, #0] + 801b940: 6878 ldr r0, [r7, #4] + 801b942: f7fd fee5 bl 8019710 + break; + 801b946: bf00 nop + } + + /* This means the pbuf is freed or consumed, + so the caller doesn't have to free it again */ + return ERR_OK; + 801b948: 2300 movs r3, #0 + 801b94a: e00c b.n 801b966 + goto free_and_return; + 801b94c: bf00 nop + 801b94e: e006 b.n 801b95e + goto free_and_return; + 801b950: bf00 nop + 801b952: e004 b.n 801b95e + goto free_and_return; + 801b954: bf00 nop + 801b956: e002 b.n 801b95e + goto free_and_return; + 801b958: bf00 nop + 801b95a: e000 b.n 801b95e + goto free_and_return; + 801b95c: bf00 nop + +free_and_return: + pbuf_free(p); + 801b95e: 6878 ldr r0, [r7, #4] + 801b960: f7f5 f84e bl 8010a00 + return ERR_OK; + 801b964: 2300 movs r3, #0 +} + 801b966: 4618 mov r0, r3 + 801b968: 3718 adds r7, #24 + 801b96a: 46bd mov sp, r7 + 801b96c: bd80 pop {r7, pc} + 801b96e: bf00 nop + 801b970: 0802391c .word 0x0802391c + +0801b974 : + * @return ERR_OK if the packet was sent, any other err_t on failure + */ +err_t +ethernet_output(struct netif * netif, struct pbuf * p, + const struct eth_addr * src, const struct eth_addr * dst, + u16_t eth_type) { + 801b974: b580 push {r7, lr} + 801b976: b086 sub sp, #24 + 801b978: af00 add r7, sp, #0 + 801b97a: 60f8 str r0, [r7, #12] + 801b97c: 60b9 str r1, [r7, #8] + 801b97e: 607a str r2, [r7, #4] + 801b980: 603b str r3, [r7, #0] + struct eth_hdr *ethhdr; + u16_t eth_type_be = lwip_htons(eth_type); + 801b982: 8c3b ldrh r3, [r7, #32] + 801b984: 4618 mov r0, r3 + 801b986: f7f2 fc53 bl 800e230 + 801b98a: 4603 mov r3, r0 + 801b98c: 82fb strh r3, [r7, #22] + + eth_type_be = PP_HTONS(ETHTYPE_VLAN); + } else +#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */ + { + if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) { + 801b98e: 210e movs r1, #14 + 801b990: 68b8 ldr r0, [r7, #8] + 801b992: f7f4 ff9f bl 80108d4 + 801b996: 4603 mov r3, r0 + 801b998: 2b00 cmp r3, #0 + 801b99a: d125 bne.n 801b9e8 + } + } + + LWIP_ASSERT_CORE_LOCKED(); + + ethhdr = (struct eth_hdr *)p->payload; + 801b99c: 68bb ldr r3, [r7, #8] + 801b99e: 685b ldr r3, [r3, #4] + 801b9a0: 613b str r3, [r7, #16] + ethhdr->type = eth_type_be; + 801b9a2: 693b ldr r3, [r7, #16] + 801b9a4: 8afa ldrh r2, [r7, #22] + 801b9a6: 819a strh r2, [r3, #12] + SMEMCPY(ðhdr->dest, dst, ETH_HWADDR_LEN); + 801b9a8: 693b ldr r3, [r7, #16] + 801b9aa: 2206 movs r2, #6 + 801b9ac: 6839 ldr r1, [r7, #0] + 801b9ae: 4618 mov r0, r3 + 801b9b0: f000 fa6b bl 801be8a + SMEMCPY(ðhdr->src, src, ETH_HWADDR_LEN); + 801b9b4: 693b ldr r3, [r7, #16] + 801b9b6: 3306 adds r3, #6 + 801b9b8: 2206 movs r2, #6 + 801b9ba: 6879 ldr r1, [r7, #4] + 801b9bc: 4618 mov r0, r3 + 801b9be: f000 fa64 bl 801be8a + + LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!", + 801b9c2: 68fb ldr r3, [r7, #12] + 801b9c4: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 801b9c8: 2b06 cmp r3, #6 + 801b9ca: d006 beq.n 801b9da + 801b9cc: 4b0a ldr r3, [pc, #40] ; (801b9f8 ) + 801b9ce: f44f 7299 mov.w r2, #306 ; 0x132 + 801b9d2: 490a ldr r1, [pc, #40] ; (801b9fc ) + 801b9d4: 480a ldr r0, [pc, #40] ; (801ba00 ) + 801b9d6: f000 fb1d bl 801c014 + (netif->hwaddr_len == ETH_HWADDR_LEN)); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_output: sending packet %p\n", (void *)p)); + + /* send the packet */ + return netif->linkoutput(netif, p); + 801b9da: 68fb ldr r3, [r7, #12] + 801b9dc: 699b ldr r3, [r3, #24] + 801b9de: 68b9 ldr r1, [r7, #8] + 801b9e0: 68f8 ldr r0, [r7, #12] + 801b9e2: 4798 blx r3 + 801b9e4: 4603 mov r3, r0 + 801b9e6: e002 b.n 801b9ee + goto pbuf_header_failed; + 801b9e8: bf00 nop + +pbuf_header_failed: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("ethernet_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + 801b9ea: f06f 0301 mvn.w r3, #1 +} + 801b9ee: 4618 mov r0, r3 + 801b9f0: 3718 adds r7, #24 + 801b9f2: 46bd mov sp, r7 + 801b9f4: bd80 pop {r7, pc} + 801b9f6: bf00 nop + 801b9f8: 080217c0 .word 0x080217c0 + 801b9fc: 080217f8 .word 0x080217f8 + 801ba00: 0802182c .word 0x0802182c + +0801ba04 : +#endif + +/*-----------------------------------------------------------------------------------*/ +// Creates an empty mailbox. +err_t sys_mbox_new(sys_mbox_t *mbox, int size) +{ + 801ba04: b580 push {r7, lr} + 801ba06: b086 sub sp, #24 + 801ba08: af00 add r7, sp, #0 + 801ba0a: 6078 str r0, [r7, #4] + 801ba0c: 6039 str r1, [r7, #0] +#if (osCMSIS < 0x20000U) + osMessageQDef(QUEUE, size, void *); + 801ba0e: 683b ldr r3, [r7, #0] + 801ba10: 60bb str r3, [r7, #8] + 801ba12: 2304 movs r3, #4 + 801ba14: 60fb str r3, [r7, #12] + 801ba16: 2300 movs r3, #0 + 801ba18: 613b str r3, [r7, #16] + 801ba1a: 2300 movs r3, #0 + 801ba1c: 617b str r3, [r7, #20] + *mbox = osMessageCreate(osMessageQ(QUEUE), NULL); + 801ba1e: f107 0308 add.w r3, r7, #8 + 801ba22: 2100 movs r1, #0 + 801ba24: 4618 mov r0, r3 + 801ba26: f7ef fcc9 bl 800b3bc + 801ba2a: 4602 mov r2, r0 + 801ba2c: 687b ldr r3, [r7, #4] + 801ba2e: 601a str r2, [r3, #0] + if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) + { + lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; + } +#endif /* SYS_STATS */ + if(*mbox == NULL) + 801ba30: 687b ldr r3, [r7, #4] + 801ba32: 681b ldr r3, [r3, #0] + 801ba34: 2b00 cmp r3, #0 + 801ba36: d102 bne.n 801ba3e + return ERR_MEM; + 801ba38: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801ba3c: e000 b.n 801ba40 + + return ERR_OK; + 801ba3e: 2300 movs r3, #0 +} + 801ba40: 4618 mov r0, r3 + 801ba42: 3718 adds r7, #24 + 801ba44: 46bd mov sp, r7 + 801ba46: bd80 pop {r7, pc} + +0801ba48 : + + +/*-----------------------------------------------------------------------------------*/ +// Try to post the "msg" to the mailbox. +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) +{ + 801ba48: b580 push {r7, lr} + 801ba4a: b084 sub sp, #16 + 801ba4c: af00 add r7, sp, #0 + 801ba4e: 6078 str r0, [r7, #4] + 801ba50: 6039 str r1, [r7, #0] + err_t result; +#if (osCMSIS < 0x20000U) + if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK) + 801ba52: 687b ldr r3, [r7, #4] + 801ba54: 681b ldr r3, [r3, #0] + 801ba56: 6839 ldr r1, [r7, #0] + 801ba58: 2200 movs r2, #0 + 801ba5a: 4618 mov r0, r3 + 801ba5c: f7ef fcd6 bl 800b40c + 801ba60: 4603 mov r3, r0 + 801ba62: 2b00 cmp r3, #0 + 801ba64: d102 bne.n 801ba6c +#else + if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK) +#endif + { + result = ERR_OK; + 801ba66: 2300 movs r3, #0 + 801ba68: 73fb strb r3, [r7, #15] + 801ba6a: e001 b.n 801ba70 + } + else + { + // could not post, queue must be full + result = ERR_MEM; + 801ba6c: 23ff movs r3, #255 ; 0xff + 801ba6e: 73fb strb r3, [r7, #15] +#if SYS_STATS + lwip_stats.sys.mbox.err++; +#endif /* SYS_STATS */ + } + + return result; + 801ba70: f997 300f ldrsb.w r3, [r7, #15] +} + 801ba74: 4618 mov r0, r3 + 801ba76: 3710 adds r7, #16 + 801ba78: 46bd mov sp, r7 + 801ba7a: bd80 pop {r7, pc} + +0801ba7c : + + Note that a function with a similar name, sys_mbox_fetch(), is + implemented by lwIP. +*/ +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) +{ + 801ba7c: b580 push {r7, lr} + 801ba7e: b08c sub sp, #48 ; 0x30 + 801ba80: af00 add r7, sp, #0 + 801ba82: 61f8 str r0, [r7, #28] + 801ba84: 61b9 str r1, [r7, #24] + 801ba86: 617a str r2, [r7, #20] +#if (osCMSIS < 0x20000U) + osEvent event; + uint32_t starttime = osKernelSysTick(); + 801ba88: f7ef fb08 bl 800b09c + 801ba8c: 62f8 str r0, [r7, #44] ; 0x2c +#else + osStatus_t status; + uint32_t starttime = osKernelGetTickCount(); +#endif + if(timeout != 0) + 801ba8e: 697b ldr r3, [r7, #20] + 801ba90: 2b00 cmp r3, #0 + 801ba92: d017 beq.n 801bac4 + { +#if (osCMSIS < 0x20000U) + event = osMessageGet (*mbox, timeout); + 801ba94: 69fb ldr r3, [r7, #28] + 801ba96: 6819 ldr r1, [r3, #0] + 801ba98: f107 0320 add.w r3, r7, #32 + 801ba9c: 697a ldr r2, [r7, #20] + 801ba9e: 4618 mov r0, r3 + 801baa0: f7ef fcf4 bl 800b48c + + if(event.status == osEventMessage) + 801baa4: 6a3b ldr r3, [r7, #32] + 801baa6: 2b10 cmp r3, #16 + 801baa8: d109 bne.n 801babe + { + *msg = (void *)event.value.v; + 801baaa: 6a7b ldr r3, [r7, #36] ; 0x24 + 801baac: 461a mov r2, r3 + 801baae: 69bb ldr r3, [r7, #24] + 801bab0: 601a str r2, [r3, #0] + return (osKernelSysTick() - starttime); + 801bab2: f7ef faf3 bl 800b09c + 801bab6: 4602 mov r2, r0 + 801bab8: 6afb ldr r3, [r7, #44] ; 0x2c + 801baba: 1ad3 subs r3, r2, r3 + 801babc: e019 b.n 801baf2 + return (osKernelGetTickCount() - starttime); + } +#endif + else + { + return SYS_ARCH_TIMEOUT; + 801babe: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801bac2: e016 b.n 801baf2 + } + } + else + { +#if (osCMSIS < 0x20000U) + event = osMessageGet (*mbox, osWaitForever); + 801bac4: 69fb ldr r3, [r7, #28] + 801bac6: 6819 ldr r1, [r3, #0] + 801bac8: 463b mov r3, r7 + 801baca: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 801bace: 4618 mov r0, r3 + 801bad0: f7ef fcdc bl 800b48c + 801bad4: f107 0320 add.w r3, r7, #32 + 801bad8: 463a mov r2, r7 + 801bada: ca07 ldmia r2, {r0, r1, r2} + 801badc: e883 0007 stmia.w r3, {r0, r1, r2} + *msg = (void *)event.value.v; + 801bae0: 6a7b ldr r3, [r7, #36] ; 0x24 + 801bae2: 461a mov r2, r3 + 801bae4: 69bb ldr r3, [r7, #24] + 801bae6: 601a str r2, [r3, #0] + return (osKernelSysTick() - starttime); + 801bae8: f7ef fad8 bl 800b09c + 801baec: 4602 mov r2, r0 + 801baee: 6afb ldr r3, [r7, #44] ; 0x2c + 801baf0: 1ad3 subs r3, r2, r3 +#else + osMessageQueueGet(*mbox, msg, 0, osWaitForever ); + return (osKernelGetTickCount() - starttime); +#endif + } +} + 801baf2: 4618 mov r0, r3 + 801baf4: 3730 adds r7, #48 ; 0x30 + 801baf6: 46bd mov sp, r7 + 801baf8: bd80 pop {r7, pc} + +0801bafa : + return SYS_MBOX_EMPTY; + } +} +/*----------------------------------------------------------------------------------*/ +int sys_mbox_valid(sys_mbox_t *mbox) +{ + 801bafa: b480 push {r7} + 801bafc: b083 sub sp, #12 + 801bafe: af00 add r7, sp, #0 + 801bb00: 6078 str r0, [r7, #4] + if (*mbox == SYS_MBOX_NULL) + 801bb02: 687b ldr r3, [r7, #4] + 801bb04: 681b ldr r3, [r3, #0] + 801bb06: 2b00 cmp r3, #0 + 801bb08: d101 bne.n 801bb0e + return 0; + 801bb0a: 2300 movs r3, #0 + 801bb0c: e000 b.n 801bb10 + else + return 1; + 801bb0e: 2301 movs r3, #1 +} + 801bb10: 4618 mov r0, r3 + 801bb12: 370c adds r7, #12 + 801bb14: 46bd mov sp, r7 + 801bb16: f85d 7b04 ldr.w r7, [sp], #4 + 801bb1a: 4770 bx lr + +0801bb1c : +#else +osMutexId_t lwip_sys_mutex; +#endif +// Initialize sys arch +void sys_init(void) +{ + 801bb1c: b580 push {r7, lr} + 801bb1e: af00 add r7, sp, #0 +#if (osCMSIS < 0x20000U) + lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex)); + 801bb20: 4803 ldr r0, [pc, #12] ; (801bb30 ) + 801bb22: f7ef fb2b bl 800b17c + 801bb26: 4603 mov r3, r0 + 801bb28: 4a02 ldr r2, [pc, #8] ; (801bb34 ) + 801bb2a: 6013 str r3, [r2, #0] +#else + lwip_sys_mutex = osMutexNew(NULL); +#endif +} + 801bb2c: bf00 nop + 801bb2e: bd80 pop {r7, pc} + 801bb30: 0802392c .word 0x0802392c + 801bb34: 2000d0dc .word 0x2000d0dc + +0801bb38 : + /* Mutexes*/ +/*-----------------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------------*/ +#if LWIP_COMPAT_MUTEX == 0 +/* Create a new mutex*/ +err_t sys_mutex_new(sys_mutex_t *mutex) { + 801bb38: b580 push {r7, lr} + 801bb3a: b084 sub sp, #16 + 801bb3c: af00 add r7, sp, #0 + 801bb3e: 6078 str r0, [r7, #4] + +#if (osCMSIS < 0x20000U) + osMutexDef(MUTEX); + 801bb40: 2300 movs r3, #0 + 801bb42: 60bb str r3, [r7, #8] + 801bb44: 2300 movs r3, #0 + 801bb46: 60fb str r3, [r7, #12] + *mutex = osMutexCreate(osMutex(MUTEX)); + 801bb48: f107 0308 add.w r3, r7, #8 + 801bb4c: 4618 mov r0, r3 + 801bb4e: f7ef fb15 bl 800b17c + 801bb52: 4602 mov r2, r0 + 801bb54: 687b ldr r3, [r7, #4] + 801bb56: 601a str r2, [r3, #0] +#else + *mutex = osMutexNew(NULL); +#endif + + if(*mutex == NULL) + 801bb58: 687b ldr r3, [r7, #4] + 801bb5a: 681b ldr r3, [r3, #0] + 801bb5c: 2b00 cmp r3, #0 + 801bb5e: d102 bne.n 801bb66 + { +#if SYS_STATS + ++lwip_stats.sys.mutex.err; +#endif /* SYS_STATS */ + return ERR_MEM; + 801bb60: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801bb64: e000 b.n 801bb68 + ++lwip_stats.sys.mutex.used; + if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) { + lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used; + } +#endif /* SYS_STATS */ + return ERR_OK; + 801bb66: 2300 movs r3, #0 +} + 801bb68: 4618 mov r0, r3 + 801bb6a: 3710 adds r7, #16 + 801bb6c: 46bd mov sp, r7 + 801bb6e: bd80 pop {r7, pc} + +0801bb70 : + osMutexDelete(*mutex); +} +/*-----------------------------------------------------------------------------------*/ +/* Lock a mutex*/ +void sys_mutex_lock(sys_mutex_t *mutex) +{ + 801bb70: b580 push {r7, lr} + 801bb72: b082 sub sp, #8 + 801bb74: af00 add r7, sp, #0 + 801bb76: 6078 str r0, [r7, #4] +#if (osCMSIS < 0x20000U) + osMutexWait(*mutex, osWaitForever); + 801bb78: 687b ldr r3, [r7, #4] + 801bb7a: 681b ldr r3, [r3, #0] + 801bb7c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 801bb80: 4618 mov r0, r3 + 801bb82: f7ef fb13 bl 800b1ac +#else + osMutexAcquire(*mutex, osWaitForever); +#endif +} + 801bb86: bf00 nop + 801bb88: 3708 adds r7, #8 + 801bb8a: 46bd mov sp, r7 + 801bb8c: bd80 pop {r7, pc} + +0801bb8e : + +/*-----------------------------------------------------------------------------------*/ +/* Unlock a mutex*/ +void sys_mutex_unlock(sys_mutex_t *mutex) +{ + 801bb8e: b580 push {r7, lr} + 801bb90: b082 sub sp, #8 + 801bb92: af00 add r7, sp, #0 + 801bb94: 6078 str r0, [r7, #4] + osMutexRelease(*mutex); + 801bb96: 687b ldr r3, [r7, #4] + 801bb98: 681b ldr r3, [r3, #0] + 801bb9a: 4618 mov r0, r3 + 801bb9c: f7ef fb54 bl 800b248 +} + 801bba0: bf00 nop + 801bba2: 3708 adds r7, #8 + 801bba4: 46bd mov sp, r7 + 801bba6: bd80 pop {r7, pc} + +0801bba8 : + function "thread()". The "arg" argument will be passed as an argument to the + thread() function. The id of the new thread is returned. Both the id and + the priority are system dependent. +*/ +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio) +{ + 801bba8: b580 push {r7, lr} + 801bbaa: b08c sub sp, #48 ; 0x30 + 801bbac: af00 add r7, sp, #0 + 801bbae: 60f8 str r0, [r7, #12] + 801bbb0: 60b9 str r1, [r7, #8] + 801bbb2: 607a str r2, [r7, #4] + 801bbb4: 603b str r3, [r7, #0] +#if (osCMSIS < 0x20000U) + const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize}; + 801bbb6: f107 0314 add.w r3, r7, #20 + 801bbba: 2200 movs r2, #0 + 801bbbc: 601a str r2, [r3, #0] + 801bbbe: 605a str r2, [r3, #4] + 801bbc0: 609a str r2, [r3, #8] + 801bbc2: 60da str r2, [r3, #12] + 801bbc4: 611a str r2, [r3, #16] + 801bbc6: 615a str r2, [r3, #20] + 801bbc8: 619a str r2, [r3, #24] + 801bbca: 68fb ldr r3, [r7, #12] + 801bbcc: 617b str r3, [r7, #20] + 801bbce: 68bb ldr r3, [r7, #8] + 801bbd0: 61bb str r3, [r7, #24] + 801bbd2: 6bbb ldr r3, [r7, #56] ; 0x38 + 801bbd4: b21b sxth r3, r3 + 801bbd6: 83bb strh r3, [r7, #28] + 801bbd8: 683b ldr r3, [r7, #0] + 801bbda: 627b str r3, [r7, #36] ; 0x24 + return osThreadCreate(&os_thread_def, arg); + 801bbdc: f107 0314 add.w r3, r7, #20 + 801bbe0: 6879 ldr r1, [r7, #4] + 801bbe2: 4618 mov r0, r3 + 801bbe4: f7ef fa6a bl 800b0bc + 801bbe8: 4603 mov r3, r0 + .stack_size = stacksize, + .priority = (osPriority_t)prio, + }; + return osThreadNew(thread, arg, &attributes); +#endif +} + 801bbea: 4618 mov r0, r3 + 801bbec: 3730 adds r7, #48 ; 0x30 + 801bbee: 46bd mov sp, r7 + 801bbf0: bd80 pop {r7, pc} + ... + +0801bbf4 : + + Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS + API is available +*/ +sys_prot_t sys_arch_protect(void) +{ + 801bbf4: b580 push {r7, lr} + 801bbf6: af00 add r7, sp, #0 +#if (osCMSIS < 0x20000U) + osMutexWait(lwip_sys_mutex, osWaitForever); + 801bbf8: 4b04 ldr r3, [pc, #16] ; (801bc0c ) + 801bbfa: 681b ldr r3, [r3, #0] + 801bbfc: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 801bc00: 4618 mov r0, r3 + 801bc02: f7ef fad3 bl 800b1ac +#else + osMutexAcquire(lwip_sys_mutex, osWaitForever); +#endif + return (sys_prot_t)1; + 801bc06: 2301 movs r3, #1 +} + 801bc08: 4618 mov r0, r3 + 801bc0a: bd80 pop {r7, pc} + 801bc0c: 2000d0dc .word 0x2000d0dc + +0801bc10 : + + Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS + API is available +*/ +void sys_arch_unprotect(sys_prot_t pval) +{ + 801bc10: b580 push {r7, lr} + 801bc12: b082 sub sp, #8 + 801bc14: af00 add r7, sp, #0 + 801bc16: 6078 str r0, [r7, #4] + ( void ) pval; + osMutexRelease(lwip_sys_mutex); + 801bc18: 4b04 ldr r3, [pc, #16] ; (801bc2c ) + 801bc1a: 681b ldr r3, [r3, #0] + 801bc1c: 4618 mov r0, r3 + 801bc1e: f7ef fb13 bl 800b248 +} + 801bc22: bf00 nop + 801bc24: 3708 adds r7, #8 + 801bc26: 46bd mov sp, r7 + 801bc28: bd80 pop {r7, pc} + 801bc2a: bf00 nop + 801bc2c: 2000d0dc .word 0x2000d0dc + +0801bc30 : + 801bc30: 2300 movs r3, #0 + 801bc32: b510 push {r4, lr} + 801bc34: 4604 mov r4, r0 + 801bc36: e9c0 3300 strd r3, r3, [r0] + 801bc3a: e9c0 3304 strd r3, r3, [r0, #16] + 801bc3e: 6083 str r3, [r0, #8] + 801bc40: 8181 strh r1, [r0, #12] + 801bc42: 6643 str r3, [r0, #100] ; 0x64 + 801bc44: 81c2 strh r2, [r0, #14] + 801bc46: 6183 str r3, [r0, #24] + 801bc48: 4619 mov r1, r3 + 801bc4a: 2208 movs r2, #8 + 801bc4c: 305c adds r0, #92 ; 0x5c + 801bc4e: f000 f944 bl 801beda + 801bc52: 4b05 ldr r3, [pc, #20] ; (801bc68 ) + 801bc54: 6263 str r3, [r4, #36] ; 0x24 + 801bc56: 4b05 ldr r3, [pc, #20] ; (801bc6c ) + 801bc58: 62a3 str r3, [r4, #40] ; 0x28 + 801bc5a: 4b05 ldr r3, [pc, #20] ; (801bc70 ) + 801bc5c: 62e3 str r3, [r4, #44] ; 0x2c + 801bc5e: 4b05 ldr r3, [pc, #20] ; (801bc74 ) + 801bc60: 6224 str r4, [r4, #32] + 801bc62: 6323 str r3, [r4, #48] ; 0x30 + 801bc64: bd10 pop {r4, pc} + 801bc66: bf00 nop + 801bc68: 0801c2e1 .word 0x0801c2e1 + 801bc6c: 0801c303 .word 0x0801c303 + 801bc70: 0801c33b .word 0x0801c33b + 801bc74: 0801c35f .word 0x0801c35f + +0801bc78 <_cleanup_r>: + 801bc78: 4901 ldr r1, [pc, #4] ; (801bc80 <_cleanup_r+0x8>) + 801bc7a: f000 b8af b.w 801bddc <_fwalk_reent> + 801bc7e: bf00 nop + 801bc80: 0801c69d .word 0x0801c69d + +0801bc84 <__sfmoreglue>: + 801bc84: b570 push {r4, r5, r6, lr} + 801bc86: 2268 movs r2, #104 ; 0x68 + 801bc88: 1e4d subs r5, r1, #1 + 801bc8a: 4355 muls r5, r2 + 801bc8c: 460e mov r6, r1 + 801bc8e: f105 0174 add.w r1, r5, #116 ; 0x74 + 801bc92: f000 f94b bl 801bf2c <_malloc_r> + 801bc96: 4604 mov r4, r0 + 801bc98: b140 cbz r0, 801bcac <__sfmoreglue+0x28> + 801bc9a: 2100 movs r1, #0 + 801bc9c: e9c0 1600 strd r1, r6, [r0] + 801bca0: 300c adds r0, #12 + 801bca2: 60a0 str r0, [r4, #8] + 801bca4: f105 0268 add.w r2, r5, #104 ; 0x68 + 801bca8: f000 f917 bl 801beda + 801bcac: 4620 mov r0, r4 + 801bcae: bd70 pop {r4, r5, r6, pc} + +0801bcb0 <__sfp_lock_acquire>: + 801bcb0: 4801 ldr r0, [pc, #4] ; (801bcb8 <__sfp_lock_acquire+0x8>) + 801bcb2: f000 b8d8 b.w 801be66 <__retarget_lock_acquire_recursive> + 801bcb6: bf00 nop + 801bcb8: 2000d0e1 .word 0x2000d0e1 + +0801bcbc <__sfp_lock_release>: + 801bcbc: 4801 ldr r0, [pc, #4] ; (801bcc4 <__sfp_lock_release+0x8>) + 801bcbe: f000 b8d3 b.w 801be68 <__retarget_lock_release_recursive> + 801bcc2: bf00 nop + 801bcc4: 2000d0e1 .word 0x2000d0e1 + +0801bcc8 <__sinit_lock_acquire>: + 801bcc8: 4801 ldr r0, [pc, #4] ; (801bcd0 <__sinit_lock_acquire+0x8>) + 801bcca: f000 b8cc b.w 801be66 <__retarget_lock_acquire_recursive> + 801bcce: bf00 nop + 801bcd0: 2000d0e2 .word 0x2000d0e2 + +0801bcd4 <__sinit_lock_release>: + 801bcd4: 4801 ldr r0, [pc, #4] ; (801bcdc <__sinit_lock_release+0x8>) + 801bcd6: f000 b8c7 b.w 801be68 <__retarget_lock_release_recursive> + 801bcda: bf00 nop + 801bcdc: 2000d0e2 .word 0x2000d0e2 + +0801bce0 <__sinit>: + 801bce0: b510 push {r4, lr} + 801bce2: 4604 mov r4, r0 + 801bce4: f7ff fff0 bl 801bcc8 <__sinit_lock_acquire> + 801bce8: 69a3 ldr r3, [r4, #24] + 801bcea: b11b cbz r3, 801bcf4 <__sinit+0x14> + 801bcec: e8bd 4010 ldmia.w sp!, {r4, lr} + 801bcf0: f7ff bff0 b.w 801bcd4 <__sinit_lock_release> + 801bcf4: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 + 801bcf8: 6523 str r3, [r4, #80] ; 0x50 + 801bcfa: 4b13 ldr r3, [pc, #76] ; (801bd48 <__sinit+0x68>) + 801bcfc: 4a13 ldr r2, [pc, #76] ; (801bd4c <__sinit+0x6c>) + 801bcfe: 681b ldr r3, [r3, #0] + 801bd00: 62a2 str r2, [r4, #40] ; 0x28 + 801bd02: 42a3 cmp r3, r4 + 801bd04: bf04 itt eq + 801bd06: 2301 moveq r3, #1 + 801bd08: 61a3 streq r3, [r4, #24] + 801bd0a: 4620 mov r0, r4 + 801bd0c: f000 f820 bl 801bd50 <__sfp> + 801bd10: 6060 str r0, [r4, #4] + 801bd12: 4620 mov r0, r4 + 801bd14: f000 f81c bl 801bd50 <__sfp> + 801bd18: 60a0 str r0, [r4, #8] + 801bd1a: 4620 mov r0, r4 + 801bd1c: f000 f818 bl 801bd50 <__sfp> + 801bd20: 2200 movs r2, #0 + 801bd22: 60e0 str r0, [r4, #12] + 801bd24: 2104 movs r1, #4 + 801bd26: 6860 ldr r0, [r4, #4] + 801bd28: f7ff ff82 bl 801bc30 + 801bd2c: 68a0 ldr r0, [r4, #8] + 801bd2e: 2201 movs r2, #1 + 801bd30: 2109 movs r1, #9 + 801bd32: f7ff ff7d bl 801bc30 + 801bd36: 68e0 ldr r0, [r4, #12] + 801bd38: 2202 movs r2, #2 + 801bd3a: 2112 movs r1, #18 + 801bd3c: f7ff ff78 bl 801bc30 + 801bd40: 2301 movs r3, #1 + 801bd42: 61a3 str r3, [r4, #24] + 801bd44: e7d2 b.n 801bcec <__sinit+0xc> + 801bd46: bf00 nop + 801bd48: 08023a98 .word 0x08023a98 + 801bd4c: 0801bc79 .word 0x0801bc79 + +0801bd50 <__sfp>: + 801bd50: b5f8 push {r3, r4, r5, r6, r7, lr} + 801bd52: 4607 mov r7, r0 + 801bd54: f7ff ffac bl 801bcb0 <__sfp_lock_acquire> + 801bd58: 4b1e ldr r3, [pc, #120] ; (801bdd4 <__sfp+0x84>) + 801bd5a: 681e ldr r6, [r3, #0] + 801bd5c: 69b3 ldr r3, [r6, #24] + 801bd5e: b913 cbnz r3, 801bd66 <__sfp+0x16> + 801bd60: 4630 mov r0, r6 + 801bd62: f7ff ffbd bl 801bce0 <__sinit> + 801bd66: 3648 adds r6, #72 ; 0x48 + 801bd68: e9d6 3401 ldrd r3, r4, [r6, #4] + 801bd6c: 3b01 subs r3, #1 + 801bd6e: d503 bpl.n 801bd78 <__sfp+0x28> + 801bd70: 6833 ldr r3, [r6, #0] + 801bd72: b30b cbz r3, 801bdb8 <__sfp+0x68> + 801bd74: 6836 ldr r6, [r6, #0] + 801bd76: e7f7 b.n 801bd68 <__sfp+0x18> + 801bd78: f9b4 500c ldrsh.w r5, [r4, #12] + 801bd7c: b9d5 cbnz r5, 801bdb4 <__sfp+0x64> + 801bd7e: 4b16 ldr r3, [pc, #88] ; (801bdd8 <__sfp+0x88>) + 801bd80: 60e3 str r3, [r4, #12] + 801bd82: f104 0058 add.w r0, r4, #88 ; 0x58 + 801bd86: 6665 str r5, [r4, #100] ; 0x64 + 801bd88: f000 f86c bl 801be64 <__retarget_lock_init_recursive> + 801bd8c: f7ff ff96 bl 801bcbc <__sfp_lock_release> + 801bd90: e9c4 5501 strd r5, r5, [r4, #4] + 801bd94: e9c4 5504 strd r5, r5, [r4, #16] + 801bd98: 6025 str r5, [r4, #0] + 801bd9a: 61a5 str r5, [r4, #24] + 801bd9c: 2208 movs r2, #8 + 801bd9e: 4629 mov r1, r5 + 801bda0: f104 005c add.w r0, r4, #92 ; 0x5c + 801bda4: f000 f899 bl 801beda + 801bda8: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 801bdac: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 801bdb0: 4620 mov r0, r4 + 801bdb2: bdf8 pop {r3, r4, r5, r6, r7, pc} + 801bdb4: 3468 adds r4, #104 ; 0x68 + 801bdb6: e7d9 b.n 801bd6c <__sfp+0x1c> + 801bdb8: 2104 movs r1, #4 + 801bdba: 4638 mov r0, r7 + 801bdbc: f7ff ff62 bl 801bc84 <__sfmoreglue> + 801bdc0: 4604 mov r4, r0 + 801bdc2: 6030 str r0, [r6, #0] + 801bdc4: 2800 cmp r0, #0 + 801bdc6: d1d5 bne.n 801bd74 <__sfp+0x24> + 801bdc8: f7ff ff78 bl 801bcbc <__sfp_lock_release> + 801bdcc: 230c movs r3, #12 + 801bdce: 603b str r3, [r7, #0] + 801bdd0: e7ee b.n 801bdb0 <__sfp+0x60> + 801bdd2: bf00 nop + 801bdd4: 08023a98 .word 0x08023a98 + 801bdd8: ffff0001 .word 0xffff0001 + +0801bddc <_fwalk_reent>: + 801bddc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 801bde0: 4606 mov r6, r0 + 801bde2: 4688 mov r8, r1 + 801bde4: f100 0448 add.w r4, r0, #72 ; 0x48 + 801bde8: 2700 movs r7, #0 + 801bdea: e9d4 9501 ldrd r9, r5, [r4, #4] + 801bdee: f1b9 0901 subs.w r9, r9, #1 + 801bdf2: d505 bpl.n 801be00 <_fwalk_reent+0x24> + 801bdf4: 6824 ldr r4, [r4, #0] + 801bdf6: 2c00 cmp r4, #0 + 801bdf8: d1f7 bne.n 801bdea <_fwalk_reent+0xe> + 801bdfa: 4638 mov r0, r7 + 801bdfc: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 801be00: 89ab ldrh r3, [r5, #12] + 801be02: 2b01 cmp r3, #1 + 801be04: d907 bls.n 801be16 <_fwalk_reent+0x3a> + 801be06: f9b5 300e ldrsh.w r3, [r5, #14] + 801be0a: 3301 adds r3, #1 + 801be0c: d003 beq.n 801be16 <_fwalk_reent+0x3a> + 801be0e: 4629 mov r1, r5 + 801be10: 4630 mov r0, r6 + 801be12: 47c0 blx r8 + 801be14: 4307 orrs r7, r0 + 801be16: 3568 adds r5, #104 ; 0x68 + 801be18: e7e9 b.n 801bdee <_fwalk_reent+0x12> + ... + +0801be1c <__libc_init_array>: + 801be1c: b570 push {r4, r5, r6, lr} + 801be1e: 4d0d ldr r5, [pc, #52] ; (801be54 <__libc_init_array+0x38>) + 801be20: 4c0d ldr r4, [pc, #52] ; (801be58 <__libc_init_array+0x3c>) + 801be22: 1b64 subs r4, r4, r5 + 801be24: 10a4 asrs r4, r4, #2 + 801be26: 2600 movs r6, #0 + 801be28: 42a6 cmp r6, r4 + 801be2a: d109 bne.n 801be40 <__libc_init_array+0x24> + 801be2c: 4d0b ldr r5, [pc, #44] ; (801be5c <__libc_init_array+0x40>) + 801be2e: 4c0c ldr r4, [pc, #48] ; (801be60 <__libc_init_array+0x44>) + 801be30: f002 fafc bl 801e42c <_init> + 801be34: 1b64 subs r4, r4, r5 + 801be36: 10a4 asrs r4, r4, #2 + 801be38: 2600 movs r6, #0 + 801be3a: 42a6 cmp r6, r4 + 801be3c: d105 bne.n 801be4a <__libc_init_array+0x2e> + 801be3e: bd70 pop {r4, r5, r6, pc} + 801be40: f855 3b04 ldr.w r3, [r5], #4 + 801be44: 4798 blx r3 + 801be46: 3601 adds r6, #1 + 801be48: e7ee b.n 801be28 <__libc_init_array+0xc> + 801be4a: f855 3b04 ldr.w r3, [r5], #4 + 801be4e: 4798 blx r3 + 801be50: 3601 adds r6, #1 + 801be52: e7f2 b.n 801be3a <__libc_init_array+0x1e> + 801be54: 08023d60 .word 0x08023d60 + 801be58: 08023d60 .word 0x08023d60 + 801be5c: 08023d60 .word 0x08023d60 + 801be60: 08023d64 .word 0x08023d64 + +0801be64 <__retarget_lock_init_recursive>: + 801be64: 4770 bx lr + +0801be66 <__retarget_lock_acquire_recursive>: + 801be66: 4770 bx lr + +0801be68 <__retarget_lock_release_recursive>: + 801be68: 4770 bx lr + +0801be6a : + 801be6a: b510 push {r4, lr} + 801be6c: 3901 subs r1, #1 + 801be6e: 4402 add r2, r0 + 801be70: 4290 cmp r0, r2 + 801be72: d101 bne.n 801be78 + 801be74: 2000 movs r0, #0 + 801be76: e005 b.n 801be84 + 801be78: 7803 ldrb r3, [r0, #0] + 801be7a: f811 4f01 ldrb.w r4, [r1, #1]! + 801be7e: 42a3 cmp r3, r4 + 801be80: d001 beq.n 801be86 + 801be82: 1b18 subs r0, r3, r4 + 801be84: bd10 pop {r4, pc} + 801be86: 3001 adds r0, #1 + 801be88: e7f2 b.n 801be70 + +0801be8a : + 801be8a: 440a add r2, r1 + 801be8c: 4291 cmp r1, r2 + 801be8e: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 801be92: d100 bne.n 801be96 + 801be94: 4770 bx lr + 801be96: b510 push {r4, lr} + 801be98: f811 4b01 ldrb.w r4, [r1], #1 + 801be9c: f803 4f01 strb.w r4, [r3, #1]! + 801bea0: 4291 cmp r1, r2 + 801bea2: d1f9 bne.n 801be98 + 801bea4: bd10 pop {r4, pc} + +0801bea6 : + 801bea6: 4288 cmp r0, r1 + 801bea8: b510 push {r4, lr} + 801beaa: eb01 0402 add.w r4, r1, r2 + 801beae: d902 bls.n 801beb6 + 801beb0: 4284 cmp r4, r0 + 801beb2: 4623 mov r3, r4 + 801beb4: d807 bhi.n 801bec6 + 801beb6: 1e43 subs r3, r0, #1 + 801beb8: 42a1 cmp r1, r4 + 801beba: d008 beq.n 801bece + 801bebc: f811 2b01 ldrb.w r2, [r1], #1 + 801bec0: f803 2f01 strb.w r2, [r3, #1]! + 801bec4: e7f8 b.n 801beb8 + 801bec6: 4402 add r2, r0 + 801bec8: 4601 mov r1, r0 + 801beca: 428a cmp r2, r1 + 801becc: d100 bne.n 801bed0 + 801bece: bd10 pop {r4, pc} + 801bed0: f813 4d01 ldrb.w r4, [r3, #-1]! + 801bed4: f802 4d01 strb.w r4, [r2, #-1]! + 801bed8: e7f7 b.n 801beca + +0801beda : + 801beda: 4402 add r2, r0 + 801bedc: 4603 mov r3, r0 + 801bede: 4293 cmp r3, r2 + 801bee0: d100 bne.n 801bee4 + 801bee2: 4770 bx lr + 801bee4: f803 1b01 strb.w r1, [r3], #1 + 801bee8: e7f9 b.n 801bede + ... + +0801beec : + 801beec: b570 push {r4, r5, r6, lr} + 801beee: 4e0e ldr r6, [pc, #56] ; (801bf28 ) + 801bef0: 460c mov r4, r1 + 801bef2: 6831 ldr r1, [r6, #0] + 801bef4: 4605 mov r5, r0 + 801bef6: b911 cbnz r1, 801befe + 801bef8: f000 f9c2 bl 801c280 <_sbrk_r> + 801befc: 6030 str r0, [r6, #0] + 801befe: 4621 mov r1, r4 + 801bf00: 4628 mov r0, r5 + 801bf02: f000 f9bd bl 801c280 <_sbrk_r> + 801bf06: 1c43 adds r3, r0, #1 + 801bf08: d00a beq.n 801bf20 + 801bf0a: 1cc4 adds r4, r0, #3 + 801bf0c: f024 0403 bic.w r4, r4, #3 + 801bf10: 42a0 cmp r0, r4 + 801bf12: d007 beq.n 801bf24 + 801bf14: 1a21 subs r1, r4, r0 + 801bf16: 4628 mov r0, r5 + 801bf18: f000 f9b2 bl 801c280 <_sbrk_r> + 801bf1c: 3001 adds r0, #1 + 801bf1e: d101 bne.n 801bf24 + 801bf20: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + 801bf24: 4620 mov r0, r4 + 801bf26: bd70 pop {r4, r5, r6, pc} + 801bf28: 2000d0e8 .word 0x2000d0e8 + +0801bf2c <_malloc_r>: + 801bf2c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801bf30: 1ccd adds r5, r1, #3 + 801bf32: f025 0503 bic.w r5, r5, #3 + 801bf36: 3508 adds r5, #8 + 801bf38: 2d0c cmp r5, #12 + 801bf3a: bf38 it cc + 801bf3c: 250c movcc r5, #12 + 801bf3e: 2d00 cmp r5, #0 + 801bf40: 4607 mov r7, r0 + 801bf42: db01 blt.n 801bf48 <_malloc_r+0x1c> + 801bf44: 42a9 cmp r1, r5 + 801bf46: d905 bls.n 801bf54 <_malloc_r+0x28> + 801bf48: 230c movs r3, #12 + 801bf4a: 603b str r3, [r7, #0] + 801bf4c: 2600 movs r6, #0 + 801bf4e: 4630 mov r0, r6 + 801bf50: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801bf54: 4e2e ldr r6, [pc, #184] ; (801c010 <_malloc_r+0xe4>) + 801bf56: f000 fc6f bl 801c838 <__malloc_lock> + 801bf5a: 6833 ldr r3, [r6, #0] + 801bf5c: 461c mov r4, r3 + 801bf5e: bb34 cbnz r4, 801bfae <_malloc_r+0x82> + 801bf60: 4629 mov r1, r5 + 801bf62: 4638 mov r0, r7 + 801bf64: f7ff ffc2 bl 801beec + 801bf68: 1c43 adds r3, r0, #1 + 801bf6a: 4604 mov r4, r0 + 801bf6c: d14d bne.n 801c00a <_malloc_r+0xde> + 801bf6e: 6834 ldr r4, [r6, #0] + 801bf70: 4626 mov r6, r4 + 801bf72: 2e00 cmp r6, #0 + 801bf74: d140 bne.n 801bff8 <_malloc_r+0xcc> + 801bf76: 6823 ldr r3, [r4, #0] + 801bf78: 4631 mov r1, r6 + 801bf7a: 4638 mov r0, r7 + 801bf7c: eb04 0803 add.w r8, r4, r3 + 801bf80: f000 f97e bl 801c280 <_sbrk_r> + 801bf84: 4580 cmp r8, r0 + 801bf86: d13a bne.n 801bffe <_malloc_r+0xd2> + 801bf88: 6821 ldr r1, [r4, #0] + 801bf8a: 3503 adds r5, #3 + 801bf8c: 1a6d subs r5, r5, r1 + 801bf8e: f025 0503 bic.w r5, r5, #3 + 801bf92: 3508 adds r5, #8 + 801bf94: 2d0c cmp r5, #12 + 801bf96: bf38 it cc + 801bf98: 250c movcc r5, #12 + 801bf9a: 4629 mov r1, r5 + 801bf9c: 4638 mov r0, r7 + 801bf9e: f7ff ffa5 bl 801beec + 801bfa2: 3001 adds r0, #1 + 801bfa4: d02b beq.n 801bffe <_malloc_r+0xd2> + 801bfa6: 6823 ldr r3, [r4, #0] + 801bfa8: 442b add r3, r5 + 801bfaa: 6023 str r3, [r4, #0] + 801bfac: e00e b.n 801bfcc <_malloc_r+0xa0> + 801bfae: 6822 ldr r2, [r4, #0] + 801bfb0: 1b52 subs r2, r2, r5 + 801bfb2: d41e bmi.n 801bff2 <_malloc_r+0xc6> + 801bfb4: 2a0b cmp r2, #11 + 801bfb6: d916 bls.n 801bfe6 <_malloc_r+0xba> + 801bfb8: 1961 adds r1, r4, r5 + 801bfba: 42a3 cmp r3, r4 + 801bfbc: 6025 str r5, [r4, #0] + 801bfbe: bf18 it ne + 801bfc0: 6059 strne r1, [r3, #4] + 801bfc2: 6863 ldr r3, [r4, #4] + 801bfc4: bf08 it eq + 801bfc6: 6031 streq r1, [r6, #0] + 801bfc8: 5162 str r2, [r4, r5] + 801bfca: 604b str r3, [r1, #4] + 801bfcc: 4638 mov r0, r7 + 801bfce: f104 060b add.w r6, r4, #11 + 801bfd2: f000 fc37 bl 801c844 <__malloc_unlock> + 801bfd6: f026 0607 bic.w r6, r6, #7 + 801bfda: 1d23 adds r3, r4, #4 + 801bfdc: 1af2 subs r2, r6, r3 + 801bfde: d0b6 beq.n 801bf4e <_malloc_r+0x22> + 801bfe0: 1b9b subs r3, r3, r6 + 801bfe2: 50a3 str r3, [r4, r2] + 801bfe4: e7b3 b.n 801bf4e <_malloc_r+0x22> + 801bfe6: 6862 ldr r2, [r4, #4] + 801bfe8: 42a3 cmp r3, r4 + 801bfea: bf0c ite eq + 801bfec: 6032 streq r2, [r6, #0] + 801bfee: 605a strne r2, [r3, #4] + 801bff0: e7ec b.n 801bfcc <_malloc_r+0xa0> + 801bff2: 4623 mov r3, r4 + 801bff4: 6864 ldr r4, [r4, #4] + 801bff6: e7b2 b.n 801bf5e <_malloc_r+0x32> + 801bff8: 4634 mov r4, r6 + 801bffa: 6876 ldr r6, [r6, #4] + 801bffc: e7b9 b.n 801bf72 <_malloc_r+0x46> + 801bffe: 230c movs r3, #12 + 801c000: 603b str r3, [r7, #0] + 801c002: 4638 mov r0, r7 + 801c004: f000 fc1e bl 801c844 <__malloc_unlock> + 801c008: e7a1 b.n 801bf4e <_malloc_r+0x22> + 801c00a: 6025 str r5, [r4, #0] + 801c00c: e7de b.n 801bfcc <_malloc_r+0xa0> + 801c00e: bf00 nop + 801c010: 2000d0e4 .word 0x2000d0e4 + +0801c014 : + 801c014: b40f push {r0, r1, r2, r3} + 801c016: 4b0a ldr r3, [pc, #40] ; (801c040 ) + 801c018: b513 push {r0, r1, r4, lr} + 801c01a: 681c ldr r4, [r3, #0] + 801c01c: b124 cbz r4, 801c028 + 801c01e: 69a3 ldr r3, [r4, #24] + 801c020: b913 cbnz r3, 801c028 + 801c022: 4620 mov r0, r4 + 801c024: f7ff fe5c bl 801bce0 <__sinit> + 801c028: ab05 add r3, sp, #20 + 801c02a: 9a04 ldr r2, [sp, #16] + 801c02c: 68a1 ldr r1, [r4, #8] + 801c02e: 9301 str r3, [sp, #4] + 801c030: 4620 mov r0, r4 + 801c032: f000 fddf bl 801cbf4 <_vfiprintf_r> + 801c036: b002 add sp, #8 + 801c038: e8bd 4010 ldmia.w sp!, {r4, lr} + 801c03c: b004 add sp, #16 + 801c03e: 4770 bx lr + 801c040: 200000c4 .word 0x200000c4 + +0801c044 <_puts_r>: + 801c044: b570 push {r4, r5, r6, lr} + 801c046: 460e mov r6, r1 + 801c048: 4605 mov r5, r0 + 801c04a: b118 cbz r0, 801c054 <_puts_r+0x10> + 801c04c: 6983 ldr r3, [r0, #24] + 801c04e: b90b cbnz r3, 801c054 <_puts_r+0x10> + 801c050: f7ff fe46 bl 801bce0 <__sinit> + 801c054: 69ab ldr r3, [r5, #24] + 801c056: 68ac ldr r4, [r5, #8] + 801c058: b913 cbnz r3, 801c060 <_puts_r+0x1c> + 801c05a: 4628 mov r0, r5 + 801c05c: f7ff fe40 bl 801bce0 <__sinit> + 801c060: 4b2c ldr r3, [pc, #176] ; (801c114 <_puts_r+0xd0>) + 801c062: 429c cmp r4, r3 + 801c064: d120 bne.n 801c0a8 <_puts_r+0x64> + 801c066: 686c ldr r4, [r5, #4] + 801c068: 6e63 ldr r3, [r4, #100] ; 0x64 + 801c06a: 07db lsls r3, r3, #31 + 801c06c: d405 bmi.n 801c07a <_puts_r+0x36> + 801c06e: 89a3 ldrh r3, [r4, #12] + 801c070: 0598 lsls r0, r3, #22 + 801c072: d402 bmi.n 801c07a <_puts_r+0x36> + 801c074: 6da0 ldr r0, [r4, #88] ; 0x58 + 801c076: f7ff fef6 bl 801be66 <__retarget_lock_acquire_recursive> + 801c07a: 89a3 ldrh r3, [r4, #12] + 801c07c: 0719 lsls r1, r3, #28 + 801c07e: d51d bpl.n 801c0bc <_puts_r+0x78> + 801c080: 6923 ldr r3, [r4, #16] + 801c082: b1db cbz r3, 801c0bc <_puts_r+0x78> + 801c084: 3e01 subs r6, #1 + 801c086: 68a3 ldr r3, [r4, #8] + 801c088: f816 1f01 ldrb.w r1, [r6, #1]! + 801c08c: 3b01 subs r3, #1 + 801c08e: 60a3 str r3, [r4, #8] + 801c090: bb39 cbnz r1, 801c0e2 <_puts_r+0x9e> + 801c092: 2b00 cmp r3, #0 + 801c094: da38 bge.n 801c108 <_puts_r+0xc4> + 801c096: 4622 mov r2, r4 + 801c098: 210a movs r1, #10 + 801c09a: 4628 mov r0, r5 + 801c09c: f000 f978 bl 801c390 <__swbuf_r> + 801c0a0: 3001 adds r0, #1 + 801c0a2: d011 beq.n 801c0c8 <_puts_r+0x84> + 801c0a4: 250a movs r5, #10 + 801c0a6: e011 b.n 801c0cc <_puts_r+0x88> + 801c0a8: 4b1b ldr r3, [pc, #108] ; (801c118 <_puts_r+0xd4>) + 801c0aa: 429c cmp r4, r3 + 801c0ac: d101 bne.n 801c0b2 <_puts_r+0x6e> + 801c0ae: 68ac ldr r4, [r5, #8] + 801c0b0: e7da b.n 801c068 <_puts_r+0x24> + 801c0b2: 4b1a ldr r3, [pc, #104] ; (801c11c <_puts_r+0xd8>) + 801c0b4: 429c cmp r4, r3 + 801c0b6: bf08 it eq + 801c0b8: 68ec ldreq r4, [r5, #12] + 801c0ba: e7d5 b.n 801c068 <_puts_r+0x24> + 801c0bc: 4621 mov r1, r4 + 801c0be: 4628 mov r0, r5 + 801c0c0: f000 f9ca bl 801c458 <__swsetup_r> + 801c0c4: 2800 cmp r0, #0 + 801c0c6: d0dd beq.n 801c084 <_puts_r+0x40> + 801c0c8: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff + 801c0cc: 6e63 ldr r3, [r4, #100] ; 0x64 + 801c0ce: 07da lsls r2, r3, #31 + 801c0d0: d405 bmi.n 801c0de <_puts_r+0x9a> + 801c0d2: 89a3 ldrh r3, [r4, #12] + 801c0d4: 059b lsls r3, r3, #22 + 801c0d6: d402 bmi.n 801c0de <_puts_r+0x9a> + 801c0d8: 6da0 ldr r0, [r4, #88] ; 0x58 + 801c0da: f7ff fec5 bl 801be68 <__retarget_lock_release_recursive> + 801c0de: 4628 mov r0, r5 + 801c0e0: bd70 pop {r4, r5, r6, pc} + 801c0e2: 2b00 cmp r3, #0 + 801c0e4: da04 bge.n 801c0f0 <_puts_r+0xac> + 801c0e6: 69a2 ldr r2, [r4, #24] + 801c0e8: 429a cmp r2, r3 + 801c0ea: dc06 bgt.n 801c0fa <_puts_r+0xb6> + 801c0ec: 290a cmp r1, #10 + 801c0ee: d004 beq.n 801c0fa <_puts_r+0xb6> + 801c0f0: 6823 ldr r3, [r4, #0] + 801c0f2: 1c5a adds r2, r3, #1 + 801c0f4: 6022 str r2, [r4, #0] + 801c0f6: 7019 strb r1, [r3, #0] + 801c0f8: e7c5 b.n 801c086 <_puts_r+0x42> + 801c0fa: 4622 mov r2, r4 + 801c0fc: 4628 mov r0, r5 + 801c0fe: f000 f947 bl 801c390 <__swbuf_r> + 801c102: 3001 adds r0, #1 + 801c104: d1bf bne.n 801c086 <_puts_r+0x42> + 801c106: e7df b.n 801c0c8 <_puts_r+0x84> + 801c108: 6823 ldr r3, [r4, #0] + 801c10a: 250a movs r5, #10 + 801c10c: 1c5a adds r2, r3, #1 + 801c10e: 6022 str r2, [r4, #0] + 801c110: 701d strb r5, [r3, #0] + 801c112: e7db b.n 801c0cc <_puts_r+0x88> + 801c114: 08023a58 .word 0x08023a58 + 801c118: 08023a78 .word 0x08023a78 + 801c11c: 08023a38 .word 0x08023a38 + +0801c120 : + 801c120: 4b02 ldr r3, [pc, #8] ; (801c12c ) + 801c122: 4601 mov r1, r0 + 801c124: 6818 ldr r0, [r3, #0] + 801c126: f7ff bf8d b.w 801c044 <_puts_r> + 801c12a: bf00 nop + 801c12c: 200000c4 .word 0x200000c4 + +0801c130 : + 801c130: 4b16 ldr r3, [pc, #88] ; (801c18c ) + 801c132: b510 push {r4, lr} + 801c134: 681c ldr r4, [r3, #0] + 801c136: 6ba3 ldr r3, [r4, #56] ; 0x38 + 801c138: b9b3 cbnz r3, 801c168 + 801c13a: 2018 movs r0, #24 + 801c13c: f000 fb74 bl 801c828 + 801c140: 63a0 str r0, [r4, #56] ; 0x38 + 801c142: b928 cbnz r0, 801c150 + 801c144: 4602 mov r2, r0 + 801c146: 4b12 ldr r3, [pc, #72] ; (801c190 ) + 801c148: 4812 ldr r0, [pc, #72] ; (801c194 ) + 801c14a: 214e movs r1, #78 ; 0x4e + 801c14c: f000 f9f2 bl 801c534 <__assert_func> + 801c150: 4a11 ldr r2, [pc, #68] ; (801c198 ) + 801c152: 4b12 ldr r3, [pc, #72] ; (801c19c ) + 801c154: e9c0 2300 strd r2, r3, [r0] + 801c158: 4b11 ldr r3, [pc, #68] ; (801c1a0 ) + 801c15a: 6083 str r3, [r0, #8] + 801c15c: 230b movs r3, #11 + 801c15e: 8183 strh r3, [r0, #12] + 801c160: 2201 movs r2, #1 + 801c162: 2300 movs r3, #0 + 801c164: e9c0 2304 strd r2, r3, [r0, #16] + 801c168: 6ba4 ldr r4, [r4, #56] ; 0x38 + 801c16a: 4a0e ldr r2, [pc, #56] ; (801c1a4 ) + 801c16c: 6920 ldr r0, [r4, #16] + 801c16e: 6963 ldr r3, [r4, #20] + 801c170: 490d ldr r1, [pc, #52] ; (801c1a8 ) + 801c172: 4342 muls r2, r0 + 801c174: fb01 2203 mla r2, r1, r3, r2 + 801c178: fba0 0101 umull r0, r1, r0, r1 + 801c17c: 1c43 adds r3, r0, #1 + 801c17e: eb42 0001 adc.w r0, r2, r1 + 801c182: e9c4 3004 strd r3, r0, [r4, #16] + 801c186: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 + 801c18a: bd10 pop {r4, pc} + 801c18c: 200000c4 .word 0x200000c4 + 801c190: 08023a9c .word 0x08023a9c + 801c194: 08023ab3 .word 0x08023ab3 + 801c198: abcd330e .word 0xabcd330e + 801c19c: e66d1234 .word 0xe66d1234 + 801c1a0: 0005deec .word 0x0005deec + 801c1a4: 5851f42d .word 0x5851f42d + 801c1a8: 4c957f2d .word 0x4c957f2d + +0801c1ac : + 801c1ac: b538 push {r3, r4, r5, lr} + 801c1ae: 460c mov r4, r1 + 801c1b0: 6809 ldr r1, [r1, #0] + 801c1b2: 4605 mov r5, r0 + 801c1b4: b109 cbz r1, 801c1ba + 801c1b6: f7ff fff9 bl 801c1ac + 801c1ba: 4621 mov r1, r4 + 801c1bc: 4628 mov r0, r5 + 801c1be: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 801c1c2: f000 bb45 b.w 801c850 <_free_r> + ... + +0801c1c8 <_reclaim_reent>: + 801c1c8: 4b2c ldr r3, [pc, #176] ; (801c27c <_reclaim_reent+0xb4>) + 801c1ca: 681b ldr r3, [r3, #0] + 801c1cc: 4283 cmp r3, r0 + 801c1ce: b570 push {r4, r5, r6, lr} + 801c1d0: 4604 mov r4, r0 + 801c1d2: d051 beq.n 801c278 <_reclaim_reent+0xb0> + 801c1d4: 6a43 ldr r3, [r0, #36] ; 0x24 + 801c1d6: b143 cbz r3, 801c1ea <_reclaim_reent+0x22> + 801c1d8: 68db ldr r3, [r3, #12] + 801c1da: 2b00 cmp r3, #0 + 801c1dc: d14a bne.n 801c274 <_reclaim_reent+0xac> + 801c1de: 6a63 ldr r3, [r4, #36] ; 0x24 + 801c1e0: 6819 ldr r1, [r3, #0] + 801c1e2: b111 cbz r1, 801c1ea <_reclaim_reent+0x22> + 801c1e4: 4620 mov r0, r4 + 801c1e6: f000 fb33 bl 801c850 <_free_r> + 801c1ea: 6961 ldr r1, [r4, #20] + 801c1ec: b111 cbz r1, 801c1f4 <_reclaim_reent+0x2c> + 801c1ee: 4620 mov r0, r4 + 801c1f0: f000 fb2e bl 801c850 <_free_r> + 801c1f4: 6a61 ldr r1, [r4, #36] ; 0x24 + 801c1f6: b111 cbz r1, 801c1fe <_reclaim_reent+0x36> + 801c1f8: 4620 mov r0, r4 + 801c1fa: f000 fb29 bl 801c850 <_free_r> + 801c1fe: 6ba1 ldr r1, [r4, #56] ; 0x38 + 801c200: b111 cbz r1, 801c208 <_reclaim_reent+0x40> + 801c202: 4620 mov r0, r4 + 801c204: f000 fb24 bl 801c850 <_free_r> + 801c208: 6be1 ldr r1, [r4, #60] ; 0x3c + 801c20a: b111 cbz r1, 801c212 <_reclaim_reent+0x4a> + 801c20c: 4620 mov r0, r4 + 801c20e: f000 fb1f bl 801c850 <_free_r> + 801c212: 6c21 ldr r1, [r4, #64] ; 0x40 + 801c214: b111 cbz r1, 801c21c <_reclaim_reent+0x54> + 801c216: 4620 mov r0, r4 + 801c218: f000 fb1a bl 801c850 <_free_r> + 801c21c: 6de1 ldr r1, [r4, #92] ; 0x5c + 801c21e: b111 cbz r1, 801c226 <_reclaim_reent+0x5e> + 801c220: 4620 mov r0, r4 + 801c222: f000 fb15 bl 801c850 <_free_r> + 801c226: 6da1 ldr r1, [r4, #88] ; 0x58 + 801c228: b111 cbz r1, 801c230 <_reclaim_reent+0x68> + 801c22a: 4620 mov r0, r4 + 801c22c: f000 fb10 bl 801c850 <_free_r> + 801c230: 6b61 ldr r1, [r4, #52] ; 0x34 + 801c232: b111 cbz r1, 801c23a <_reclaim_reent+0x72> + 801c234: 4620 mov r0, r4 + 801c236: f000 fb0b bl 801c850 <_free_r> + 801c23a: 69a3 ldr r3, [r4, #24] + 801c23c: b1e3 cbz r3, 801c278 <_reclaim_reent+0xb0> + 801c23e: 6aa3 ldr r3, [r4, #40] ; 0x28 + 801c240: 4620 mov r0, r4 + 801c242: 4798 blx r3 + 801c244: 6ca1 ldr r1, [r4, #72] ; 0x48 + 801c246: b1b9 cbz r1, 801c278 <_reclaim_reent+0xb0> + 801c248: 4620 mov r0, r4 + 801c24a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 801c24e: f7ff bfad b.w 801c1ac + 801c252: 5949 ldr r1, [r1, r5] + 801c254: b941 cbnz r1, 801c268 <_reclaim_reent+0xa0> + 801c256: 3504 adds r5, #4 + 801c258: 6a63 ldr r3, [r4, #36] ; 0x24 + 801c25a: 2d80 cmp r5, #128 ; 0x80 + 801c25c: 68d9 ldr r1, [r3, #12] + 801c25e: d1f8 bne.n 801c252 <_reclaim_reent+0x8a> + 801c260: 4620 mov r0, r4 + 801c262: f000 faf5 bl 801c850 <_free_r> + 801c266: e7ba b.n 801c1de <_reclaim_reent+0x16> + 801c268: 680e ldr r6, [r1, #0] + 801c26a: 4620 mov r0, r4 + 801c26c: f000 faf0 bl 801c850 <_free_r> + 801c270: 4631 mov r1, r6 + 801c272: e7ef b.n 801c254 <_reclaim_reent+0x8c> + 801c274: 2500 movs r5, #0 + 801c276: e7ef b.n 801c258 <_reclaim_reent+0x90> + 801c278: bd70 pop {r4, r5, r6, pc} + 801c27a: bf00 nop + 801c27c: 200000c4 .word 0x200000c4 + +0801c280 <_sbrk_r>: + 801c280: b538 push {r3, r4, r5, lr} + 801c282: 4d06 ldr r5, [pc, #24] ; (801c29c <_sbrk_r+0x1c>) + 801c284: 2300 movs r3, #0 + 801c286: 4604 mov r4, r0 + 801c288: 4608 mov r0, r1 + 801c28a: 602b str r3, [r5, #0] + 801c28c: f7e7 f884 bl 8003398 <_sbrk> + 801c290: 1c43 adds r3, r0, #1 + 801c292: d102 bne.n 801c29a <_sbrk_r+0x1a> + 801c294: 682b ldr r3, [r5, #0] + 801c296: b103 cbz r3, 801c29a <_sbrk_r+0x1a> + 801c298: 6023 str r3, [r4, #0] + 801c29a: bd38 pop {r3, r4, r5, pc} + 801c29c: 2000d0ec .word 0x2000d0ec + +0801c2a0 : + 801c2a0: b40e push {r1, r2, r3} + 801c2a2: b500 push {lr} + 801c2a4: b09c sub sp, #112 ; 0x70 + 801c2a6: ab1d add r3, sp, #116 ; 0x74 + 801c2a8: 9002 str r0, [sp, #8] + 801c2aa: 9006 str r0, [sp, #24] + 801c2ac: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 801c2b0: 4809 ldr r0, [pc, #36] ; (801c2d8 ) + 801c2b2: 9107 str r1, [sp, #28] + 801c2b4: 9104 str r1, [sp, #16] + 801c2b6: 4909 ldr r1, [pc, #36] ; (801c2dc ) + 801c2b8: f853 2b04 ldr.w r2, [r3], #4 + 801c2bc: 9105 str r1, [sp, #20] + 801c2be: 6800 ldr r0, [r0, #0] + 801c2c0: 9301 str r3, [sp, #4] + 801c2c2: a902 add r1, sp, #8 + 801c2c4: f000 fb6c bl 801c9a0 <_svfiprintf_r> + 801c2c8: 9b02 ldr r3, [sp, #8] + 801c2ca: 2200 movs r2, #0 + 801c2cc: 701a strb r2, [r3, #0] + 801c2ce: b01c add sp, #112 ; 0x70 + 801c2d0: f85d eb04 ldr.w lr, [sp], #4 + 801c2d4: b003 add sp, #12 + 801c2d6: 4770 bx lr + 801c2d8: 200000c4 .word 0x200000c4 + 801c2dc: ffff0208 .word 0xffff0208 + +0801c2e0 <__sread>: + 801c2e0: b510 push {r4, lr} + 801c2e2: 460c mov r4, r1 + 801c2e4: f9b1 100e ldrsh.w r1, [r1, #14] + 801c2e8: f000 ff48 bl 801d17c <_read_r> + 801c2ec: 2800 cmp r0, #0 + 801c2ee: bfab itete ge + 801c2f0: 6d63 ldrge r3, [r4, #84] ; 0x54 + 801c2f2: 89a3 ldrhlt r3, [r4, #12] + 801c2f4: 181b addge r3, r3, r0 + 801c2f6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 801c2fa: bfac ite ge + 801c2fc: 6563 strge r3, [r4, #84] ; 0x54 + 801c2fe: 81a3 strhlt r3, [r4, #12] + 801c300: bd10 pop {r4, pc} + +0801c302 <__swrite>: + 801c302: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801c306: 461f mov r7, r3 + 801c308: 898b ldrh r3, [r1, #12] + 801c30a: 05db lsls r3, r3, #23 + 801c30c: 4605 mov r5, r0 + 801c30e: 460c mov r4, r1 + 801c310: 4616 mov r6, r2 + 801c312: d505 bpl.n 801c320 <__swrite+0x1e> + 801c314: f9b1 100e ldrsh.w r1, [r1, #14] + 801c318: 2302 movs r3, #2 + 801c31a: 2200 movs r2, #0 + 801c31c: f000 fa0c bl 801c738 <_lseek_r> + 801c320: 89a3 ldrh r3, [r4, #12] + 801c322: f9b4 100e ldrsh.w r1, [r4, #14] + 801c326: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 801c32a: 81a3 strh r3, [r4, #12] + 801c32c: 4632 mov r2, r6 + 801c32e: 463b mov r3, r7 + 801c330: 4628 mov r0, r5 + 801c332: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 801c336: f000 b87d b.w 801c434 <_write_r> + +0801c33a <__sseek>: + 801c33a: b510 push {r4, lr} + 801c33c: 460c mov r4, r1 + 801c33e: f9b1 100e ldrsh.w r1, [r1, #14] + 801c342: f000 f9f9 bl 801c738 <_lseek_r> + 801c346: 1c43 adds r3, r0, #1 + 801c348: 89a3 ldrh r3, [r4, #12] + 801c34a: bf15 itete ne + 801c34c: 6560 strne r0, [r4, #84] ; 0x54 + 801c34e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 801c352: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 801c356: 81a3 strheq r3, [r4, #12] + 801c358: bf18 it ne + 801c35a: 81a3 strhne r3, [r4, #12] + 801c35c: bd10 pop {r4, pc} + +0801c35e <__sclose>: + 801c35e: f9b1 100e ldrsh.w r1, [r1, #14] + 801c362: f000 b905 b.w 801c570 <_close_r> + +0801c366 : + 801c366: b510 push {r4, lr} + 801c368: b17a cbz r2, 801c38a + 801c36a: 4603 mov r3, r0 + 801c36c: 3901 subs r1, #1 + 801c36e: 1884 adds r4, r0, r2 + 801c370: f813 0b01 ldrb.w r0, [r3], #1 + 801c374: f811 2f01 ldrb.w r2, [r1, #1]! + 801c378: 4290 cmp r0, r2 + 801c37a: d101 bne.n 801c380 + 801c37c: 42a3 cmp r3, r4 + 801c37e: d101 bne.n 801c384 + 801c380: 1a80 subs r0, r0, r2 + 801c382: bd10 pop {r4, pc} + 801c384: 2800 cmp r0, #0 + 801c386: d1f3 bne.n 801c370 + 801c388: e7fa b.n 801c380 + 801c38a: 4610 mov r0, r2 + 801c38c: e7f9 b.n 801c382 + ... + +0801c390 <__swbuf_r>: + 801c390: b5f8 push {r3, r4, r5, r6, r7, lr} + 801c392: 460e mov r6, r1 + 801c394: 4614 mov r4, r2 + 801c396: 4605 mov r5, r0 + 801c398: b118 cbz r0, 801c3a2 <__swbuf_r+0x12> + 801c39a: 6983 ldr r3, [r0, #24] + 801c39c: b90b cbnz r3, 801c3a2 <__swbuf_r+0x12> + 801c39e: f7ff fc9f bl 801bce0 <__sinit> + 801c3a2: 4b21 ldr r3, [pc, #132] ; (801c428 <__swbuf_r+0x98>) + 801c3a4: 429c cmp r4, r3 + 801c3a6: d12b bne.n 801c400 <__swbuf_r+0x70> + 801c3a8: 686c ldr r4, [r5, #4] + 801c3aa: 69a3 ldr r3, [r4, #24] + 801c3ac: 60a3 str r3, [r4, #8] + 801c3ae: 89a3 ldrh r3, [r4, #12] + 801c3b0: 071a lsls r2, r3, #28 + 801c3b2: d52f bpl.n 801c414 <__swbuf_r+0x84> + 801c3b4: 6923 ldr r3, [r4, #16] + 801c3b6: b36b cbz r3, 801c414 <__swbuf_r+0x84> + 801c3b8: 6923 ldr r3, [r4, #16] + 801c3ba: 6820 ldr r0, [r4, #0] + 801c3bc: 1ac0 subs r0, r0, r3 + 801c3be: 6963 ldr r3, [r4, #20] + 801c3c0: b2f6 uxtb r6, r6 + 801c3c2: 4283 cmp r3, r0 + 801c3c4: 4637 mov r7, r6 + 801c3c6: dc04 bgt.n 801c3d2 <__swbuf_r+0x42> + 801c3c8: 4621 mov r1, r4 + 801c3ca: 4628 mov r0, r5 + 801c3cc: f000 f966 bl 801c69c <_fflush_r> + 801c3d0: bb30 cbnz r0, 801c420 <__swbuf_r+0x90> + 801c3d2: 68a3 ldr r3, [r4, #8] + 801c3d4: 3b01 subs r3, #1 + 801c3d6: 60a3 str r3, [r4, #8] + 801c3d8: 6823 ldr r3, [r4, #0] + 801c3da: 1c5a adds r2, r3, #1 + 801c3dc: 6022 str r2, [r4, #0] + 801c3de: 701e strb r6, [r3, #0] + 801c3e0: 6963 ldr r3, [r4, #20] + 801c3e2: 3001 adds r0, #1 + 801c3e4: 4283 cmp r3, r0 + 801c3e6: d004 beq.n 801c3f2 <__swbuf_r+0x62> + 801c3e8: 89a3 ldrh r3, [r4, #12] + 801c3ea: 07db lsls r3, r3, #31 + 801c3ec: d506 bpl.n 801c3fc <__swbuf_r+0x6c> + 801c3ee: 2e0a cmp r6, #10 + 801c3f0: d104 bne.n 801c3fc <__swbuf_r+0x6c> + 801c3f2: 4621 mov r1, r4 + 801c3f4: 4628 mov r0, r5 + 801c3f6: f000 f951 bl 801c69c <_fflush_r> + 801c3fa: b988 cbnz r0, 801c420 <__swbuf_r+0x90> + 801c3fc: 4638 mov r0, r7 + 801c3fe: bdf8 pop {r3, r4, r5, r6, r7, pc} + 801c400: 4b0a ldr r3, [pc, #40] ; (801c42c <__swbuf_r+0x9c>) + 801c402: 429c cmp r4, r3 + 801c404: d101 bne.n 801c40a <__swbuf_r+0x7a> + 801c406: 68ac ldr r4, [r5, #8] + 801c408: e7cf b.n 801c3aa <__swbuf_r+0x1a> + 801c40a: 4b09 ldr r3, [pc, #36] ; (801c430 <__swbuf_r+0xa0>) + 801c40c: 429c cmp r4, r3 + 801c40e: bf08 it eq + 801c410: 68ec ldreq r4, [r5, #12] + 801c412: e7ca b.n 801c3aa <__swbuf_r+0x1a> + 801c414: 4621 mov r1, r4 + 801c416: 4628 mov r0, r5 + 801c418: f000 f81e bl 801c458 <__swsetup_r> + 801c41c: 2800 cmp r0, #0 + 801c41e: d0cb beq.n 801c3b8 <__swbuf_r+0x28> + 801c420: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff + 801c424: e7ea b.n 801c3fc <__swbuf_r+0x6c> + 801c426: bf00 nop + 801c428: 08023a58 .word 0x08023a58 + 801c42c: 08023a78 .word 0x08023a78 + 801c430: 08023a38 .word 0x08023a38 + +0801c434 <_write_r>: + 801c434: b538 push {r3, r4, r5, lr} + 801c436: 4d07 ldr r5, [pc, #28] ; (801c454 <_write_r+0x20>) + 801c438: 4604 mov r4, r0 + 801c43a: 4608 mov r0, r1 + 801c43c: 4611 mov r1, r2 + 801c43e: 2200 movs r2, #0 + 801c440: 602a str r2, [r5, #0] + 801c442: 461a mov r2, r3 + 801c444: f7e5 ff60 bl 8002308 <_write> + 801c448: 1c43 adds r3, r0, #1 + 801c44a: d102 bne.n 801c452 <_write_r+0x1e> + 801c44c: 682b ldr r3, [r5, #0] + 801c44e: b103 cbz r3, 801c452 <_write_r+0x1e> + 801c450: 6023 str r3, [r4, #0] + 801c452: bd38 pop {r3, r4, r5, pc} + 801c454: 2000d0ec .word 0x2000d0ec + +0801c458 <__swsetup_r>: + 801c458: 4b32 ldr r3, [pc, #200] ; (801c524 <__swsetup_r+0xcc>) + 801c45a: b570 push {r4, r5, r6, lr} + 801c45c: 681d ldr r5, [r3, #0] + 801c45e: 4606 mov r6, r0 + 801c460: 460c mov r4, r1 + 801c462: b125 cbz r5, 801c46e <__swsetup_r+0x16> + 801c464: 69ab ldr r3, [r5, #24] + 801c466: b913 cbnz r3, 801c46e <__swsetup_r+0x16> + 801c468: 4628 mov r0, r5 + 801c46a: f7ff fc39 bl 801bce0 <__sinit> + 801c46e: 4b2e ldr r3, [pc, #184] ; (801c528 <__swsetup_r+0xd0>) + 801c470: 429c cmp r4, r3 + 801c472: d10f bne.n 801c494 <__swsetup_r+0x3c> + 801c474: 686c ldr r4, [r5, #4] + 801c476: 89a3 ldrh r3, [r4, #12] + 801c478: f9b4 200c ldrsh.w r2, [r4, #12] + 801c47c: 0719 lsls r1, r3, #28 + 801c47e: d42c bmi.n 801c4da <__swsetup_r+0x82> + 801c480: 06dd lsls r5, r3, #27 + 801c482: d411 bmi.n 801c4a8 <__swsetup_r+0x50> + 801c484: 2309 movs r3, #9 + 801c486: 6033 str r3, [r6, #0] + 801c488: f042 0340 orr.w r3, r2, #64 ; 0x40 + 801c48c: 81a3 strh r3, [r4, #12] + 801c48e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801c492: e03e b.n 801c512 <__swsetup_r+0xba> + 801c494: 4b25 ldr r3, [pc, #148] ; (801c52c <__swsetup_r+0xd4>) + 801c496: 429c cmp r4, r3 + 801c498: d101 bne.n 801c49e <__swsetup_r+0x46> + 801c49a: 68ac ldr r4, [r5, #8] + 801c49c: e7eb b.n 801c476 <__swsetup_r+0x1e> + 801c49e: 4b24 ldr r3, [pc, #144] ; (801c530 <__swsetup_r+0xd8>) + 801c4a0: 429c cmp r4, r3 + 801c4a2: bf08 it eq + 801c4a4: 68ec ldreq r4, [r5, #12] + 801c4a6: e7e6 b.n 801c476 <__swsetup_r+0x1e> + 801c4a8: 0758 lsls r0, r3, #29 + 801c4aa: d512 bpl.n 801c4d2 <__swsetup_r+0x7a> + 801c4ac: 6b61 ldr r1, [r4, #52] ; 0x34 + 801c4ae: b141 cbz r1, 801c4c2 <__swsetup_r+0x6a> + 801c4b0: f104 0344 add.w r3, r4, #68 ; 0x44 + 801c4b4: 4299 cmp r1, r3 + 801c4b6: d002 beq.n 801c4be <__swsetup_r+0x66> + 801c4b8: 4630 mov r0, r6 + 801c4ba: f000 f9c9 bl 801c850 <_free_r> + 801c4be: 2300 movs r3, #0 + 801c4c0: 6363 str r3, [r4, #52] ; 0x34 + 801c4c2: 89a3 ldrh r3, [r4, #12] + 801c4c4: f023 0324 bic.w r3, r3, #36 ; 0x24 + 801c4c8: 81a3 strh r3, [r4, #12] + 801c4ca: 2300 movs r3, #0 + 801c4cc: 6063 str r3, [r4, #4] + 801c4ce: 6923 ldr r3, [r4, #16] + 801c4d0: 6023 str r3, [r4, #0] + 801c4d2: 89a3 ldrh r3, [r4, #12] + 801c4d4: f043 0308 orr.w r3, r3, #8 + 801c4d8: 81a3 strh r3, [r4, #12] + 801c4da: 6923 ldr r3, [r4, #16] + 801c4dc: b94b cbnz r3, 801c4f2 <__swsetup_r+0x9a> + 801c4de: 89a3 ldrh r3, [r4, #12] + 801c4e0: f403 7320 and.w r3, r3, #640 ; 0x280 + 801c4e4: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 801c4e8: d003 beq.n 801c4f2 <__swsetup_r+0x9a> + 801c4ea: 4621 mov r1, r4 + 801c4ec: 4630 mov r0, r6 + 801c4ee: f000 f95b bl 801c7a8 <__smakebuf_r> + 801c4f2: 89a0 ldrh r0, [r4, #12] + 801c4f4: f9b4 200c ldrsh.w r2, [r4, #12] + 801c4f8: f010 0301 ands.w r3, r0, #1 + 801c4fc: d00a beq.n 801c514 <__swsetup_r+0xbc> + 801c4fe: 2300 movs r3, #0 + 801c500: 60a3 str r3, [r4, #8] + 801c502: 6963 ldr r3, [r4, #20] + 801c504: 425b negs r3, r3 + 801c506: 61a3 str r3, [r4, #24] + 801c508: 6923 ldr r3, [r4, #16] + 801c50a: b943 cbnz r3, 801c51e <__swsetup_r+0xc6> + 801c50c: f010 0080 ands.w r0, r0, #128 ; 0x80 + 801c510: d1ba bne.n 801c488 <__swsetup_r+0x30> + 801c512: bd70 pop {r4, r5, r6, pc} + 801c514: 0781 lsls r1, r0, #30 + 801c516: bf58 it pl + 801c518: 6963 ldrpl r3, [r4, #20] + 801c51a: 60a3 str r3, [r4, #8] + 801c51c: e7f4 b.n 801c508 <__swsetup_r+0xb0> + 801c51e: 2000 movs r0, #0 + 801c520: e7f7 b.n 801c512 <__swsetup_r+0xba> + 801c522: bf00 nop + 801c524: 200000c4 .word 0x200000c4 + 801c528: 08023a58 .word 0x08023a58 + 801c52c: 08023a78 .word 0x08023a78 + 801c530: 08023a38 .word 0x08023a38 + +0801c534 <__assert_func>: + 801c534: b51f push {r0, r1, r2, r3, r4, lr} + 801c536: 4614 mov r4, r2 + 801c538: 461a mov r2, r3 + 801c53a: 4b09 ldr r3, [pc, #36] ; (801c560 <__assert_func+0x2c>) + 801c53c: 681b ldr r3, [r3, #0] + 801c53e: 4605 mov r5, r0 + 801c540: 68d8 ldr r0, [r3, #12] + 801c542: b14c cbz r4, 801c558 <__assert_func+0x24> + 801c544: 4b07 ldr r3, [pc, #28] ; (801c564 <__assert_func+0x30>) + 801c546: 9100 str r1, [sp, #0] + 801c548: e9cd 3401 strd r3, r4, [sp, #4] + 801c54c: 4906 ldr r1, [pc, #24] ; (801c568 <__assert_func+0x34>) + 801c54e: 462b mov r3, r5 + 801c550: f000 f8e0 bl 801c714 + 801c554: f000 fe24 bl 801d1a0 + 801c558: 4b04 ldr r3, [pc, #16] ; (801c56c <__assert_func+0x38>) + 801c55a: 461c mov r4, r3 + 801c55c: e7f3 b.n 801c546 <__assert_func+0x12> + 801c55e: bf00 nop + 801c560: 200000c4 .word 0x200000c4 + 801c564: 08023b0e .word 0x08023b0e + 801c568: 08023b1b .word 0x08023b1b + 801c56c: 08023b49 .word 0x08023b49 + +0801c570 <_close_r>: + 801c570: b538 push {r3, r4, r5, lr} + 801c572: 4d06 ldr r5, [pc, #24] ; (801c58c <_close_r+0x1c>) + 801c574: 2300 movs r3, #0 + 801c576: 4604 mov r4, r0 + 801c578: 4608 mov r0, r1 + 801c57a: 602b str r3, [r5, #0] + 801c57c: f7e6 fed8 bl 8003330 <_close> + 801c580: 1c43 adds r3, r0, #1 + 801c582: d102 bne.n 801c58a <_close_r+0x1a> + 801c584: 682b ldr r3, [r5, #0] + 801c586: b103 cbz r3, 801c58a <_close_r+0x1a> + 801c588: 6023 str r3, [r4, #0] + 801c58a: bd38 pop {r3, r4, r5, pc} + 801c58c: 2000d0ec .word 0x2000d0ec + +0801c590 <__sflush_r>: + 801c590: 898a ldrh r2, [r1, #12] + 801c592: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801c596: 4605 mov r5, r0 + 801c598: 0710 lsls r0, r2, #28 + 801c59a: 460c mov r4, r1 + 801c59c: d458 bmi.n 801c650 <__sflush_r+0xc0> + 801c59e: 684b ldr r3, [r1, #4] + 801c5a0: 2b00 cmp r3, #0 + 801c5a2: dc05 bgt.n 801c5b0 <__sflush_r+0x20> + 801c5a4: 6c0b ldr r3, [r1, #64] ; 0x40 + 801c5a6: 2b00 cmp r3, #0 + 801c5a8: dc02 bgt.n 801c5b0 <__sflush_r+0x20> + 801c5aa: 2000 movs r0, #0 + 801c5ac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801c5b0: 6ae6 ldr r6, [r4, #44] ; 0x2c + 801c5b2: 2e00 cmp r6, #0 + 801c5b4: d0f9 beq.n 801c5aa <__sflush_r+0x1a> + 801c5b6: 2300 movs r3, #0 + 801c5b8: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 801c5bc: 682f ldr r7, [r5, #0] + 801c5be: 602b str r3, [r5, #0] + 801c5c0: d032 beq.n 801c628 <__sflush_r+0x98> + 801c5c2: 6d60 ldr r0, [r4, #84] ; 0x54 + 801c5c4: 89a3 ldrh r3, [r4, #12] + 801c5c6: 075a lsls r2, r3, #29 + 801c5c8: d505 bpl.n 801c5d6 <__sflush_r+0x46> + 801c5ca: 6863 ldr r3, [r4, #4] + 801c5cc: 1ac0 subs r0, r0, r3 + 801c5ce: 6b63 ldr r3, [r4, #52] ; 0x34 + 801c5d0: b10b cbz r3, 801c5d6 <__sflush_r+0x46> + 801c5d2: 6c23 ldr r3, [r4, #64] ; 0x40 + 801c5d4: 1ac0 subs r0, r0, r3 + 801c5d6: 2300 movs r3, #0 + 801c5d8: 4602 mov r2, r0 + 801c5da: 6ae6 ldr r6, [r4, #44] ; 0x2c + 801c5dc: 6a21 ldr r1, [r4, #32] + 801c5de: 4628 mov r0, r5 + 801c5e0: 47b0 blx r6 + 801c5e2: 1c43 adds r3, r0, #1 + 801c5e4: 89a3 ldrh r3, [r4, #12] + 801c5e6: d106 bne.n 801c5f6 <__sflush_r+0x66> + 801c5e8: 6829 ldr r1, [r5, #0] + 801c5ea: 291d cmp r1, #29 + 801c5ec: d82c bhi.n 801c648 <__sflush_r+0xb8> + 801c5ee: 4a2a ldr r2, [pc, #168] ; (801c698 <__sflush_r+0x108>) + 801c5f0: 40ca lsrs r2, r1 + 801c5f2: 07d6 lsls r6, r2, #31 + 801c5f4: d528 bpl.n 801c648 <__sflush_r+0xb8> + 801c5f6: 2200 movs r2, #0 + 801c5f8: 6062 str r2, [r4, #4] + 801c5fa: 04d9 lsls r1, r3, #19 + 801c5fc: 6922 ldr r2, [r4, #16] + 801c5fe: 6022 str r2, [r4, #0] + 801c600: d504 bpl.n 801c60c <__sflush_r+0x7c> + 801c602: 1c42 adds r2, r0, #1 + 801c604: d101 bne.n 801c60a <__sflush_r+0x7a> + 801c606: 682b ldr r3, [r5, #0] + 801c608: b903 cbnz r3, 801c60c <__sflush_r+0x7c> + 801c60a: 6560 str r0, [r4, #84] ; 0x54 + 801c60c: 6b61 ldr r1, [r4, #52] ; 0x34 + 801c60e: 602f str r7, [r5, #0] + 801c610: 2900 cmp r1, #0 + 801c612: d0ca beq.n 801c5aa <__sflush_r+0x1a> + 801c614: f104 0344 add.w r3, r4, #68 ; 0x44 + 801c618: 4299 cmp r1, r3 + 801c61a: d002 beq.n 801c622 <__sflush_r+0x92> + 801c61c: 4628 mov r0, r5 + 801c61e: f000 f917 bl 801c850 <_free_r> + 801c622: 2000 movs r0, #0 + 801c624: 6360 str r0, [r4, #52] ; 0x34 + 801c626: e7c1 b.n 801c5ac <__sflush_r+0x1c> + 801c628: 6a21 ldr r1, [r4, #32] + 801c62a: 2301 movs r3, #1 + 801c62c: 4628 mov r0, r5 + 801c62e: 47b0 blx r6 + 801c630: 1c41 adds r1, r0, #1 + 801c632: d1c7 bne.n 801c5c4 <__sflush_r+0x34> + 801c634: 682b ldr r3, [r5, #0] + 801c636: 2b00 cmp r3, #0 + 801c638: d0c4 beq.n 801c5c4 <__sflush_r+0x34> + 801c63a: 2b1d cmp r3, #29 + 801c63c: d001 beq.n 801c642 <__sflush_r+0xb2> + 801c63e: 2b16 cmp r3, #22 + 801c640: d101 bne.n 801c646 <__sflush_r+0xb6> + 801c642: 602f str r7, [r5, #0] + 801c644: e7b1 b.n 801c5aa <__sflush_r+0x1a> + 801c646: 89a3 ldrh r3, [r4, #12] + 801c648: f043 0340 orr.w r3, r3, #64 ; 0x40 + 801c64c: 81a3 strh r3, [r4, #12] + 801c64e: e7ad b.n 801c5ac <__sflush_r+0x1c> + 801c650: 690f ldr r7, [r1, #16] + 801c652: 2f00 cmp r7, #0 + 801c654: d0a9 beq.n 801c5aa <__sflush_r+0x1a> + 801c656: 0793 lsls r3, r2, #30 + 801c658: 680e ldr r6, [r1, #0] + 801c65a: bf08 it eq + 801c65c: 694b ldreq r3, [r1, #20] + 801c65e: 600f str r7, [r1, #0] + 801c660: bf18 it ne + 801c662: 2300 movne r3, #0 + 801c664: eba6 0807 sub.w r8, r6, r7 + 801c668: 608b str r3, [r1, #8] + 801c66a: f1b8 0f00 cmp.w r8, #0 + 801c66e: dd9c ble.n 801c5aa <__sflush_r+0x1a> + 801c670: 6a21 ldr r1, [r4, #32] + 801c672: 6aa6 ldr r6, [r4, #40] ; 0x28 + 801c674: 4643 mov r3, r8 + 801c676: 463a mov r2, r7 + 801c678: 4628 mov r0, r5 + 801c67a: 47b0 blx r6 + 801c67c: 2800 cmp r0, #0 + 801c67e: dc06 bgt.n 801c68e <__sflush_r+0xfe> + 801c680: 89a3 ldrh r3, [r4, #12] + 801c682: f043 0340 orr.w r3, r3, #64 ; 0x40 + 801c686: 81a3 strh r3, [r4, #12] + 801c688: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801c68c: e78e b.n 801c5ac <__sflush_r+0x1c> + 801c68e: 4407 add r7, r0 + 801c690: eba8 0800 sub.w r8, r8, r0 + 801c694: e7e9 b.n 801c66a <__sflush_r+0xda> + 801c696: bf00 nop + 801c698: 20400001 .word 0x20400001 + +0801c69c <_fflush_r>: + 801c69c: b538 push {r3, r4, r5, lr} + 801c69e: 690b ldr r3, [r1, #16] + 801c6a0: 4605 mov r5, r0 + 801c6a2: 460c mov r4, r1 + 801c6a4: b913 cbnz r3, 801c6ac <_fflush_r+0x10> + 801c6a6: 2500 movs r5, #0 + 801c6a8: 4628 mov r0, r5 + 801c6aa: bd38 pop {r3, r4, r5, pc} + 801c6ac: b118 cbz r0, 801c6b6 <_fflush_r+0x1a> + 801c6ae: 6983 ldr r3, [r0, #24] + 801c6b0: b90b cbnz r3, 801c6b6 <_fflush_r+0x1a> + 801c6b2: f7ff fb15 bl 801bce0 <__sinit> + 801c6b6: 4b14 ldr r3, [pc, #80] ; (801c708 <_fflush_r+0x6c>) + 801c6b8: 429c cmp r4, r3 + 801c6ba: d11b bne.n 801c6f4 <_fflush_r+0x58> + 801c6bc: 686c ldr r4, [r5, #4] + 801c6be: f9b4 300c ldrsh.w r3, [r4, #12] + 801c6c2: 2b00 cmp r3, #0 + 801c6c4: d0ef beq.n 801c6a6 <_fflush_r+0xa> + 801c6c6: 6e62 ldr r2, [r4, #100] ; 0x64 + 801c6c8: 07d0 lsls r0, r2, #31 + 801c6ca: d404 bmi.n 801c6d6 <_fflush_r+0x3a> + 801c6cc: 0599 lsls r1, r3, #22 + 801c6ce: d402 bmi.n 801c6d6 <_fflush_r+0x3a> + 801c6d0: 6da0 ldr r0, [r4, #88] ; 0x58 + 801c6d2: f7ff fbc8 bl 801be66 <__retarget_lock_acquire_recursive> + 801c6d6: 4628 mov r0, r5 + 801c6d8: 4621 mov r1, r4 + 801c6da: f7ff ff59 bl 801c590 <__sflush_r> + 801c6de: 6e63 ldr r3, [r4, #100] ; 0x64 + 801c6e0: 07da lsls r2, r3, #31 + 801c6e2: 4605 mov r5, r0 + 801c6e4: d4e0 bmi.n 801c6a8 <_fflush_r+0xc> + 801c6e6: 89a3 ldrh r3, [r4, #12] + 801c6e8: 059b lsls r3, r3, #22 + 801c6ea: d4dd bmi.n 801c6a8 <_fflush_r+0xc> + 801c6ec: 6da0 ldr r0, [r4, #88] ; 0x58 + 801c6ee: f7ff fbbb bl 801be68 <__retarget_lock_release_recursive> + 801c6f2: e7d9 b.n 801c6a8 <_fflush_r+0xc> + 801c6f4: 4b05 ldr r3, [pc, #20] ; (801c70c <_fflush_r+0x70>) + 801c6f6: 429c cmp r4, r3 + 801c6f8: d101 bne.n 801c6fe <_fflush_r+0x62> + 801c6fa: 68ac ldr r4, [r5, #8] + 801c6fc: e7df b.n 801c6be <_fflush_r+0x22> + 801c6fe: 4b04 ldr r3, [pc, #16] ; (801c710 <_fflush_r+0x74>) + 801c700: 429c cmp r4, r3 + 801c702: bf08 it eq + 801c704: 68ec ldreq r4, [r5, #12] + 801c706: e7da b.n 801c6be <_fflush_r+0x22> + 801c708: 08023a58 .word 0x08023a58 + 801c70c: 08023a78 .word 0x08023a78 + 801c710: 08023a38 .word 0x08023a38 + +0801c714 : + 801c714: b40e push {r1, r2, r3} + 801c716: b503 push {r0, r1, lr} + 801c718: 4601 mov r1, r0 + 801c71a: ab03 add r3, sp, #12 + 801c71c: 4805 ldr r0, [pc, #20] ; (801c734 ) + 801c71e: f853 2b04 ldr.w r2, [r3], #4 + 801c722: 6800 ldr r0, [r0, #0] + 801c724: 9301 str r3, [sp, #4] + 801c726: f000 fa65 bl 801cbf4 <_vfiprintf_r> + 801c72a: b002 add sp, #8 + 801c72c: f85d eb04 ldr.w lr, [sp], #4 + 801c730: b003 add sp, #12 + 801c732: 4770 bx lr + 801c734: 200000c4 .word 0x200000c4 + +0801c738 <_lseek_r>: + 801c738: b538 push {r3, r4, r5, lr} + 801c73a: 4d07 ldr r5, [pc, #28] ; (801c758 <_lseek_r+0x20>) + 801c73c: 4604 mov r4, r0 + 801c73e: 4608 mov r0, r1 + 801c740: 4611 mov r1, r2 + 801c742: 2200 movs r2, #0 + 801c744: 602a str r2, [r5, #0] + 801c746: 461a mov r2, r3 + 801c748: f7e6 fe19 bl 800337e <_lseek> + 801c74c: 1c43 adds r3, r0, #1 + 801c74e: d102 bne.n 801c756 <_lseek_r+0x1e> + 801c750: 682b ldr r3, [r5, #0] + 801c752: b103 cbz r3, 801c756 <_lseek_r+0x1e> + 801c754: 6023 str r3, [r4, #0] + 801c756: bd38 pop {r3, r4, r5, pc} + 801c758: 2000d0ec .word 0x2000d0ec + +0801c75c <__swhatbuf_r>: + 801c75c: b570 push {r4, r5, r6, lr} + 801c75e: 460e mov r6, r1 + 801c760: f9b1 100e ldrsh.w r1, [r1, #14] + 801c764: 2900 cmp r1, #0 + 801c766: b096 sub sp, #88 ; 0x58 + 801c768: 4614 mov r4, r2 + 801c76a: 461d mov r5, r3 + 801c76c: da08 bge.n 801c780 <__swhatbuf_r+0x24> + 801c76e: f9b6 300c ldrsh.w r3, [r6, #12] + 801c772: 2200 movs r2, #0 + 801c774: 602a str r2, [r5, #0] + 801c776: 061a lsls r2, r3, #24 + 801c778: d410 bmi.n 801c79c <__swhatbuf_r+0x40> + 801c77a: f44f 6380 mov.w r3, #1024 ; 0x400 + 801c77e: e00e b.n 801c79e <__swhatbuf_r+0x42> + 801c780: 466a mov r2, sp + 801c782: f000 fd15 bl 801d1b0 <_fstat_r> + 801c786: 2800 cmp r0, #0 + 801c788: dbf1 blt.n 801c76e <__swhatbuf_r+0x12> + 801c78a: 9a01 ldr r2, [sp, #4] + 801c78c: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 801c790: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 801c794: 425a negs r2, r3 + 801c796: 415a adcs r2, r3 + 801c798: 602a str r2, [r5, #0] + 801c79a: e7ee b.n 801c77a <__swhatbuf_r+0x1e> + 801c79c: 2340 movs r3, #64 ; 0x40 + 801c79e: 2000 movs r0, #0 + 801c7a0: 6023 str r3, [r4, #0] + 801c7a2: b016 add sp, #88 ; 0x58 + 801c7a4: bd70 pop {r4, r5, r6, pc} + ... + +0801c7a8 <__smakebuf_r>: + 801c7a8: 898b ldrh r3, [r1, #12] + 801c7aa: b573 push {r0, r1, r4, r5, r6, lr} + 801c7ac: 079d lsls r5, r3, #30 + 801c7ae: 4606 mov r6, r0 + 801c7b0: 460c mov r4, r1 + 801c7b2: d507 bpl.n 801c7c4 <__smakebuf_r+0x1c> + 801c7b4: f104 0347 add.w r3, r4, #71 ; 0x47 + 801c7b8: 6023 str r3, [r4, #0] + 801c7ba: 6123 str r3, [r4, #16] + 801c7bc: 2301 movs r3, #1 + 801c7be: 6163 str r3, [r4, #20] + 801c7c0: b002 add sp, #8 + 801c7c2: bd70 pop {r4, r5, r6, pc} + 801c7c4: ab01 add r3, sp, #4 + 801c7c6: 466a mov r2, sp + 801c7c8: f7ff ffc8 bl 801c75c <__swhatbuf_r> + 801c7cc: 9900 ldr r1, [sp, #0] + 801c7ce: 4605 mov r5, r0 + 801c7d0: 4630 mov r0, r6 + 801c7d2: f7ff fbab bl 801bf2c <_malloc_r> + 801c7d6: b948 cbnz r0, 801c7ec <__smakebuf_r+0x44> + 801c7d8: f9b4 300c ldrsh.w r3, [r4, #12] + 801c7dc: 059a lsls r2, r3, #22 + 801c7de: d4ef bmi.n 801c7c0 <__smakebuf_r+0x18> + 801c7e0: f023 0303 bic.w r3, r3, #3 + 801c7e4: f043 0302 orr.w r3, r3, #2 + 801c7e8: 81a3 strh r3, [r4, #12] + 801c7ea: e7e3 b.n 801c7b4 <__smakebuf_r+0xc> + 801c7ec: 4b0d ldr r3, [pc, #52] ; (801c824 <__smakebuf_r+0x7c>) + 801c7ee: 62b3 str r3, [r6, #40] ; 0x28 + 801c7f0: 89a3 ldrh r3, [r4, #12] + 801c7f2: 6020 str r0, [r4, #0] + 801c7f4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 801c7f8: 81a3 strh r3, [r4, #12] + 801c7fa: 9b00 ldr r3, [sp, #0] + 801c7fc: 6163 str r3, [r4, #20] + 801c7fe: 9b01 ldr r3, [sp, #4] + 801c800: 6120 str r0, [r4, #16] + 801c802: b15b cbz r3, 801c81c <__smakebuf_r+0x74> + 801c804: f9b4 100e ldrsh.w r1, [r4, #14] + 801c808: 4630 mov r0, r6 + 801c80a: f000 fce3 bl 801d1d4 <_isatty_r> + 801c80e: b128 cbz r0, 801c81c <__smakebuf_r+0x74> + 801c810: 89a3 ldrh r3, [r4, #12] + 801c812: f023 0303 bic.w r3, r3, #3 + 801c816: f043 0301 orr.w r3, r3, #1 + 801c81a: 81a3 strh r3, [r4, #12] + 801c81c: 89a0 ldrh r0, [r4, #12] + 801c81e: 4305 orrs r5, r0 + 801c820: 81a5 strh r5, [r4, #12] + 801c822: e7cd b.n 801c7c0 <__smakebuf_r+0x18> + 801c824: 0801bc79 .word 0x0801bc79 + +0801c828 : + 801c828: 4b02 ldr r3, [pc, #8] ; (801c834 ) + 801c82a: 4601 mov r1, r0 + 801c82c: 6818 ldr r0, [r3, #0] + 801c82e: f7ff bb7d b.w 801bf2c <_malloc_r> + 801c832: bf00 nop + 801c834: 200000c4 .word 0x200000c4 + +0801c838 <__malloc_lock>: + 801c838: 4801 ldr r0, [pc, #4] ; (801c840 <__malloc_lock+0x8>) + 801c83a: f7ff bb14 b.w 801be66 <__retarget_lock_acquire_recursive> + 801c83e: bf00 nop + 801c840: 2000d0e0 .word 0x2000d0e0 + +0801c844 <__malloc_unlock>: + 801c844: 4801 ldr r0, [pc, #4] ; (801c84c <__malloc_unlock+0x8>) + 801c846: f7ff bb0f b.w 801be68 <__retarget_lock_release_recursive> + 801c84a: bf00 nop + 801c84c: 2000d0e0 .word 0x2000d0e0 + +0801c850 <_free_r>: + 801c850: b537 push {r0, r1, r2, r4, r5, lr} + 801c852: 2900 cmp r1, #0 + 801c854: d044 beq.n 801c8e0 <_free_r+0x90> + 801c856: f851 3c04 ldr.w r3, [r1, #-4] + 801c85a: 9001 str r0, [sp, #4] + 801c85c: 2b00 cmp r3, #0 + 801c85e: f1a1 0404 sub.w r4, r1, #4 + 801c862: bfb8 it lt + 801c864: 18e4 addlt r4, r4, r3 + 801c866: f7ff ffe7 bl 801c838 <__malloc_lock> + 801c86a: 4a1e ldr r2, [pc, #120] ; (801c8e4 <_free_r+0x94>) + 801c86c: 9801 ldr r0, [sp, #4] + 801c86e: 6813 ldr r3, [r2, #0] + 801c870: b933 cbnz r3, 801c880 <_free_r+0x30> + 801c872: 6063 str r3, [r4, #4] + 801c874: 6014 str r4, [r2, #0] + 801c876: b003 add sp, #12 + 801c878: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 801c87c: f7ff bfe2 b.w 801c844 <__malloc_unlock> + 801c880: 42a3 cmp r3, r4 + 801c882: d908 bls.n 801c896 <_free_r+0x46> + 801c884: 6825 ldr r5, [r4, #0] + 801c886: 1961 adds r1, r4, r5 + 801c888: 428b cmp r3, r1 + 801c88a: bf01 itttt eq + 801c88c: 6819 ldreq r1, [r3, #0] + 801c88e: 685b ldreq r3, [r3, #4] + 801c890: 1949 addeq r1, r1, r5 + 801c892: 6021 streq r1, [r4, #0] + 801c894: e7ed b.n 801c872 <_free_r+0x22> + 801c896: 461a mov r2, r3 + 801c898: 685b ldr r3, [r3, #4] + 801c89a: b10b cbz r3, 801c8a0 <_free_r+0x50> + 801c89c: 42a3 cmp r3, r4 + 801c89e: d9fa bls.n 801c896 <_free_r+0x46> + 801c8a0: 6811 ldr r1, [r2, #0] + 801c8a2: 1855 adds r5, r2, r1 + 801c8a4: 42a5 cmp r5, r4 + 801c8a6: d10b bne.n 801c8c0 <_free_r+0x70> + 801c8a8: 6824 ldr r4, [r4, #0] + 801c8aa: 4421 add r1, r4 + 801c8ac: 1854 adds r4, r2, r1 + 801c8ae: 42a3 cmp r3, r4 + 801c8b0: 6011 str r1, [r2, #0] + 801c8b2: d1e0 bne.n 801c876 <_free_r+0x26> + 801c8b4: 681c ldr r4, [r3, #0] + 801c8b6: 685b ldr r3, [r3, #4] + 801c8b8: 6053 str r3, [r2, #4] + 801c8ba: 4421 add r1, r4 + 801c8bc: 6011 str r1, [r2, #0] + 801c8be: e7da b.n 801c876 <_free_r+0x26> + 801c8c0: d902 bls.n 801c8c8 <_free_r+0x78> + 801c8c2: 230c movs r3, #12 + 801c8c4: 6003 str r3, [r0, #0] + 801c8c6: e7d6 b.n 801c876 <_free_r+0x26> + 801c8c8: 6825 ldr r5, [r4, #0] + 801c8ca: 1961 adds r1, r4, r5 + 801c8cc: 428b cmp r3, r1 + 801c8ce: bf04 itt eq + 801c8d0: 6819 ldreq r1, [r3, #0] + 801c8d2: 685b ldreq r3, [r3, #4] + 801c8d4: 6063 str r3, [r4, #4] + 801c8d6: bf04 itt eq + 801c8d8: 1949 addeq r1, r1, r5 + 801c8da: 6021 streq r1, [r4, #0] + 801c8dc: 6054 str r4, [r2, #4] + 801c8de: e7ca b.n 801c876 <_free_r+0x26> + 801c8e0: b003 add sp, #12 + 801c8e2: bd30 pop {r4, r5, pc} + 801c8e4: 2000d0e4 .word 0x2000d0e4 + +0801c8e8 <__ssputs_r>: + 801c8e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 801c8ec: 688e ldr r6, [r1, #8] + 801c8ee: 429e cmp r6, r3 + 801c8f0: 4682 mov sl, r0 + 801c8f2: 460c mov r4, r1 + 801c8f4: 4690 mov r8, r2 + 801c8f6: 461f mov r7, r3 + 801c8f8: d838 bhi.n 801c96c <__ssputs_r+0x84> + 801c8fa: 898a ldrh r2, [r1, #12] + 801c8fc: f412 6f90 tst.w r2, #1152 ; 0x480 + 801c900: d032 beq.n 801c968 <__ssputs_r+0x80> + 801c902: 6825 ldr r5, [r4, #0] + 801c904: 6909 ldr r1, [r1, #16] + 801c906: eba5 0901 sub.w r9, r5, r1 + 801c90a: 6965 ldr r5, [r4, #20] + 801c90c: eb05 0545 add.w r5, r5, r5, lsl #1 + 801c910: eb05 75d5 add.w r5, r5, r5, lsr #31 + 801c914: 3301 adds r3, #1 + 801c916: 444b add r3, r9 + 801c918: 106d asrs r5, r5, #1 + 801c91a: 429d cmp r5, r3 + 801c91c: bf38 it cc + 801c91e: 461d movcc r5, r3 + 801c920: 0553 lsls r3, r2, #21 + 801c922: d531 bpl.n 801c988 <__ssputs_r+0xa0> + 801c924: 4629 mov r1, r5 + 801c926: f7ff fb01 bl 801bf2c <_malloc_r> + 801c92a: 4606 mov r6, r0 + 801c92c: b950 cbnz r0, 801c944 <__ssputs_r+0x5c> + 801c92e: 230c movs r3, #12 + 801c930: f8ca 3000 str.w r3, [sl] + 801c934: 89a3 ldrh r3, [r4, #12] + 801c936: f043 0340 orr.w r3, r3, #64 ; 0x40 + 801c93a: 81a3 strh r3, [r4, #12] + 801c93c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801c940: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801c944: 6921 ldr r1, [r4, #16] + 801c946: 464a mov r2, r9 + 801c948: f7ff fa9f bl 801be8a + 801c94c: 89a3 ldrh r3, [r4, #12] + 801c94e: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 801c952: f043 0380 orr.w r3, r3, #128 ; 0x80 + 801c956: 81a3 strh r3, [r4, #12] + 801c958: 6126 str r6, [r4, #16] + 801c95a: 6165 str r5, [r4, #20] + 801c95c: 444e add r6, r9 + 801c95e: eba5 0509 sub.w r5, r5, r9 + 801c962: 6026 str r6, [r4, #0] + 801c964: 60a5 str r5, [r4, #8] + 801c966: 463e mov r6, r7 + 801c968: 42be cmp r6, r7 + 801c96a: d900 bls.n 801c96e <__ssputs_r+0x86> + 801c96c: 463e mov r6, r7 + 801c96e: 6820 ldr r0, [r4, #0] + 801c970: 4632 mov r2, r6 + 801c972: 4641 mov r1, r8 + 801c974: f7ff fa97 bl 801bea6 + 801c978: 68a3 ldr r3, [r4, #8] + 801c97a: 1b9b subs r3, r3, r6 + 801c97c: 60a3 str r3, [r4, #8] + 801c97e: 6823 ldr r3, [r4, #0] + 801c980: 4433 add r3, r6 + 801c982: 6023 str r3, [r4, #0] + 801c984: 2000 movs r0, #0 + 801c986: e7db b.n 801c940 <__ssputs_r+0x58> + 801c988: 462a mov r2, r5 + 801c98a: f000 fc33 bl 801d1f4 <_realloc_r> + 801c98e: 4606 mov r6, r0 + 801c990: 2800 cmp r0, #0 + 801c992: d1e1 bne.n 801c958 <__ssputs_r+0x70> + 801c994: 6921 ldr r1, [r4, #16] + 801c996: 4650 mov r0, sl + 801c998: f7ff ff5a bl 801c850 <_free_r> + 801c99c: e7c7 b.n 801c92e <__ssputs_r+0x46> + ... + +0801c9a0 <_svfiprintf_r>: + 801c9a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801c9a4: 4698 mov r8, r3 + 801c9a6: 898b ldrh r3, [r1, #12] + 801c9a8: 061b lsls r3, r3, #24 + 801c9aa: b09d sub sp, #116 ; 0x74 + 801c9ac: 4607 mov r7, r0 + 801c9ae: 460d mov r5, r1 + 801c9b0: 4614 mov r4, r2 + 801c9b2: d50e bpl.n 801c9d2 <_svfiprintf_r+0x32> + 801c9b4: 690b ldr r3, [r1, #16] + 801c9b6: b963 cbnz r3, 801c9d2 <_svfiprintf_r+0x32> + 801c9b8: 2140 movs r1, #64 ; 0x40 + 801c9ba: f7ff fab7 bl 801bf2c <_malloc_r> + 801c9be: 6028 str r0, [r5, #0] + 801c9c0: 6128 str r0, [r5, #16] + 801c9c2: b920 cbnz r0, 801c9ce <_svfiprintf_r+0x2e> + 801c9c4: 230c movs r3, #12 + 801c9c6: 603b str r3, [r7, #0] + 801c9c8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801c9cc: e0d1 b.n 801cb72 <_svfiprintf_r+0x1d2> + 801c9ce: 2340 movs r3, #64 ; 0x40 + 801c9d0: 616b str r3, [r5, #20] + 801c9d2: 2300 movs r3, #0 + 801c9d4: 9309 str r3, [sp, #36] ; 0x24 + 801c9d6: 2320 movs r3, #32 + 801c9d8: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 801c9dc: f8cd 800c str.w r8, [sp, #12] + 801c9e0: 2330 movs r3, #48 ; 0x30 + 801c9e2: f8df 81a8 ldr.w r8, [pc, #424] ; 801cb8c <_svfiprintf_r+0x1ec> + 801c9e6: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 801c9ea: f04f 0901 mov.w r9, #1 + 801c9ee: 4623 mov r3, r4 + 801c9f0: 469a mov sl, r3 + 801c9f2: f813 2b01 ldrb.w r2, [r3], #1 + 801c9f6: b10a cbz r2, 801c9fc <_svfiprintf_r+0x5c> + 801c9f8: 2a25 cmp r2, #37 ; 0x25 + 801c9fa: d1f9 bne.n 801c9f0 <_svfiprintf_r+0x50> + 801c9fc: ebba 0b04 subs.w fp, sl, r4 + 801ca00: d00b beq.n 801ca1a <_svfiprintf_r+0x7a> + 801ca02: 465b mov r3, fp + 801ca04: 4622 mov r2, r4 + 801ca06: 4629 mov r1, r5 + 801ca08: 4638 mov r0, r7 + 801ca0a: f7ff ff6d bl 801c8e8 <__ssputs_r> + 801ca0e: 3001 adds r0, #1 + 801ca10: f000 80aa beq.w 801cb68 <_svfiprintf_r+0x1c8> + 801ca14: 9a09 ldr r2, [sp, #36] ; 0x24 + 801ca16: 445a add r2, fp + 801ca18: 9209 str r2, [sp, #36] ; 0x24 + 801ca1a: f89a 3000 ldrb.w r3, [sl] + 801ca1e: 2b00 cmp r3, #0 + 801ca20: f000 80a2 beq.w 801cb68 <_svfiprintf_r+0x1c8> + 801ca24: 2300 movs r3, #0 + 801ca26: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 801ca2a: e9cd 2305 strd r2, r3, [sp, #20] + 801ca2e: f10a 0a01 add.w sl, sl, #1 + 801ca32: 9304 str r3, [sp, #16] + 801ca34: 9307 str r3, [sp, #28] + 801ca36: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 801ca3a: 931a str r3, [sp, #104] ; 0x68 + 801ca3c: 4654 mov r4, sl + 801ca3e: 2205 movs r2, #5 + 801ca40: f814 1b01 ldrb.w r1, [r4], #1 + 801ca44: 4851 ldr r0, [pc, #324] ; (801cb8c <_svfiprintf_r+0x1ec>) + 801ca46: f7e3 fbeb bl 8000220 + 801ca4a: 9a04 ldr r2, [sp, #16] + 801ca4c: b9d8 cbnz r0, 801ca86 <_svfiprintf_r+0xe6> + 801ca4e: 06d0 lsls r0, r2, #27 + 801ca50: bf44 itt mi + 801ca52: 2320 movmi r3, #32 + 801ca54: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 801ca58: 0711 lsls r1, r2, #28 + 801ca5a: bf44 itt mi + 801ca5c: 232b movmi r3, #43 ; 0x2b + 801ca5e: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 801ca62: f89a 3000 ldrb.w r3, [sl] + 801ca66: 2b2a cmp r3, #42 ; 0x2a + 801ca68: d015 beq.n 801ca96 <_svfiprintf_r+0xf6> + 801ca6a: 9a07 ldr r2, [sp, #28] + 801ca6c: 4654 mov r4, sl + 801ca6e: 2000 movs r0, #0 + 801ca70: f04f 0c0a mov.w ip, #10 + 801ca74: 4621 mov r1, r4 + 801ca76: f811 3b01 ldrb.w r3, [r1], #1 + 801ca7a: 3b30 subs r3, #48 ; 0x30 + 801ca7c: 2b09 cmp r3, #9 + 801ca7e: d94e bls.n 801cb1e <_svfiprintf_r+0x17e> + 801ca80: b1b0 cbz r0, 801cab0 <_svfiprintf_r+0x110> + 801ca82: 9207 str r2, [sp, #28] + 801ca84: e014 b.n 801cab0 <_svfiprintf_r+0x110> + 801ca86: eba0 0308 sub.w r3, r0, r8 + 801ca8a: fa09 f303 lsl.w r3, r9, r3 + 801ca8e: 4313 orrs r3, r2 + 801ca90: 9304 str r3, [sp, #16] + 801ca92: 46a2 mov sl, r4 + 801ca94: e7d2 b.n 801ca3c <_svfiprintf_r+0x9c> + 801ca96: 9b03 ldr r3, [sp, #12] + 801ca98: 1d19 adds r1, r3, #4 + 801ca9a: 681b ldr r3, [r3, #0] + 801ca9c: 9103 str r1, [sp, #12] + 801ca9e: 2b00 cmp r3, #0 + 801caa0: bfbb ittet lt + 801caa2: 425b neglt r3, r3 + 801caa4: f042 0202 orrlt.w r2, r2, #2 + 801caa8: 9307 strge r3, [sp, #28] + 801caaa: 9307 strlt r3, [sp, #28] + 801caac: bfb8 it lt + 801caae: 9204 strlt r2, [sp, #16] + 801cab0: 7823 ldrb r3, [r4, #0] + 801cab2: 2b2e cmp r3, #46 ; 0x2e + 801cab4: d10c bne.n 801cad0 <_svfiprintf_r+0x130> + 801cab6: 7863 ldrb r3, [r4, #1] + 801cab8: 2b2a cmp r3, #42 ; 0x2a + 801caba: d135 bne.n 801cb28 <_svfiprintf_r+0x188> + 801cabc: 9b03 ldr r3, [sp, #12] + 801cabe: 1d1a adds r2, r3, #4 + 801cac0: 681b ldr r3, [r3, #0] + 801cac2: 9203 str r2, [sp, #12] + 801cac4: 2b00 cmp r3, #0 + 801cac6: bfb8 it lt + 801cac8: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff + 801cacc: 3402 adds r4, #2 + 801cace: 9305 str r3, [sp, #20] + 801cad0: f8df a0c8 ldr.w sl, [pc, #200] ; 801cb9c <_svfiprintf_r+0x1fc> + 801cad4: 7821 ldrb r1, [r4, #0] + 801cad6: 2203 movs r2, #3 + 801cad8: 4650 mov r0, sl + 801cada: f7e3 fba1 bl 8000220 + 801cade: b140 cbz r0, 801caf2 <_svfiprintf_r+0x152> + 801cae0: 2340 movs r3, #64 ; 0x40 + 801cae2: eba0 000a sub.w r0, r0, sl + 801cae6: fa03 f000 lsl.w r0, r3, r0 + 801caea: 9b04 ldr r3, [sp, #16] + 801caec: 4303 orrs r3, r0 + 801caee: 3401 adds r4, #1 + 801caf0: 9304 str r3, [sp, #16] + 801caf2: f814 1b01 ldrb.w r1, [r4], #1 + 801caf6: 4826 ldr r0, [pc, #152] ; (801cb90 <_svfiprintf_r+0x1f0>) + 801caf8: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 801cafc: 2206 movs r2, #6 + 801cafe: f7e3 fb8f bl 8000220 + 801cb02: 2800 cmp r0, #0 + 801cb04: d038 beq.n 801cb78 <_svfiprintf_r+0x1d8> + 801cb06: 4b23 ldr r3, [pc, #140] ; (801cb94 <_svfiprintf_r+0x1f4>) + 801cb08: bb1b cbnz r3, 801cb52 <_svfiprintf_r+0x1b2> + 801cb0a: 9b03 ldr r3, [sp, #12] + 801cb0c: 3307 adds r3, #7 + 801cb0e: f023 0307 bic.w r3, r3, #7 + 801cb12: 3308 adds r3, #8 + 801cb14: 9303 str r3, [sp, #12] + 801cb16: 9b09 ldr r3, [sp, #36] ; 0x24 + 801cb18: 4433 add r3, r6 + 801cb1a: 9309 str r3, [sp, #36] ; 0x24 + 801cb1c: e767 b.n 801c9ee <_svfiprintf_r+0x4e> + 801cb1e: fb0c 3202 mla r2, ip, r2, r3 + 801cb22: 460c mov r4, r1 + 801cb24: 2001 movs r0, #1 + 801cb26: e7a5 b.n 801ca74 <_svfiprintf_r+0xd4> + 801cb28: 2300 movs r3, #0 + 801cb2a: 3401 adds r4, #1 + 801cb2c: 9305 str r3, [sp, #20] + 801cb2e: 4619 mov r1, r3 + 801cb30: f04f 0c0a mov.w ip, #10 + 801cb34: 4620 mov r0, r4 + 801cb36: f810 2b01 ldrb.w r2, [r0], #1 + 801cb3a: 3a30 subs r2, #48 ; 0x30 + 801cb3c: 2a09 cmp r2, #9 + 801cb3e: d903 bls.n 801cb48 <_svfiprintf_r+0x1a8> + 801cb40: 2b00 cmp r3, #0 + 801cb42: d0c5 beq.n 801cad0 <_svfiprintf_r+0x130> + 801cb44: 9105 str r1, [sp, #20] + 801cb46: e7c3 b.n 801cad0 <_svfiprintf_r+0x130> + 801cb48: fb0c 2101 mla r1, ip, r1, r2 + 801cb4c: 4604 mov r4, r0 + 801cb4e: 2301 movs r3, #1 + 801cb50: e7f0 b.n 801cb34 <_svfiprintf_r+0x194> + 801cb52: ab03 add r3, sp, #12 + 801cb54: 9300 str r3, [sp, #0] + 801cb56: 462a mov r2, r5 + 801cb58: 4b0f ldr r3, [pc, #60] ; (801cb98 <_svfiprintf_r+0x1f8>) + 801cb5a: a904 add r1, sp, #16 + 801cb5c: 4638 mov r0, r7 + 801cb5e: f3af 8000 nop.w + 801cb62: 1c42 adds r2, r0, #1 + 801cb64: 4606 mov r6, r0 + 801cb66: d1d6 bne.n 801cb16 <_svfiprintf_r+0x176> + 801cb68: 89ab ldrh r3, [r5, #12] + 801cb6a: 065b lsls r3, r3, #25 + 801cb6c: f53f af2c bmi.w 801c9c8 <_svfiprintf_r+0x28> + 801cb70: 9809 ldr r0, [sp, #36] ; 0x24 + 801cb72: b01d add sp, #116 ; 0x74 + 801cb74: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801cb78: ab03 add r3, sp, #12 + 801cb7a: 9300 str r3, [sp, #0] + 801cb7c: 462a mov r2, r5 + 801cb7e: 4b06 ldr r3, [pc, #24] ; (801cb98 <_svfiprintf_r+0x1f8>) + 801cb80: a904 add r1, sp, #16 + 801cb82: 4638 mov r0, r7 + 801cb84: f000 f9d4 bl 801cf30 <_printf_i> + 801cb88: e7eb b.n 801cb62 <_svfiprintf_r+0x1c2> + 801cb8a: bf00 nop + 801cb8c: 08023b4a .word 0x08023b4a + 801cb90: 08023b54 .word 0x08023b54 + 801cb94: 00000000 .word 0x00000000 + 801cb98: 0801c8e9 .word 0x0801c8e9 + 801cb9c: 08023b50 .word 0x08023b50 + +0801cba0 <__sfputc_r>: + 801cba0: 6893 ldr r3, [r2, #8] + 801cba2: 3b01 subs r3, #1 + 801cba4: 2b00 cmp r3, #0 + 801cba6: b410 push {r4} + 801cba8: 6093 str r3, [r2, #8] + 801cbaa: da08 bge.n 801cbbe <__sfputc_r+0x1e> + 801cbac: 6994 ldr r4, [r2, #24] + 801cbae: 42a3 cmp r3, r4 + 801cbb0: db01 blt.n 801cbb6 <__sfputc_r+0x16> + 801cbb2: 290a cmp r1, #10 + 801cbb4: d103 bne.n 801cbbe <__sfputc_r+0x1e> + 801cbb6: f85d 4b04 ldr.w r4, [sp], #4 + 801cbba: f7ff bbe9 b.w 801c390 <__swbuf_r> + 801cbbe: 6813 ldr r3, [r2, #0] + 801cbc0: 1c58 adds r0, r3, #1 + 801cbc2: 6010 str r0, [r2, #0] + 801cbc4: 7019 strb r1, [r3, #0] + 801cbc6: 4608 mov r0, r1 + 801cbc8: f85d 4b04 ldr.w r4, [sp], #4 + 801cbcc: 4770 bx lr + +0801cbce <__sfputs_r>: + 801cbce: b5f8 push {r3, r4, r5, r6, r7, lr} + 801cbd0: 4606 mov r6, r0 + 801cbd2: 460f mov r7, r1 + 801cbd4: 4614 mov r4, r2 + 801cbd6: 18d5 adds r5, r2, r3 + 801cbd8: 42ac cmp r4, r5 + 801cbda: d101 bne.n 801cbe0 <__sfputs_r+0x12> + 801cbdc: 2000 movs r0, #0 + 801cbde: e007 b.n 801cbf0 <__sfputs_r+0x22> + 801cbe0: f814 1b01 ldrb.w r1, [r4], #1 + 801cbe4: 463a mov r2, r7 + 801cbe6: 4630 mov r0, r6 + 801cbe8: f7ff ffda bl 801cba0 <__sfputc_r> + 801cbec: 1c43 adds r3, r0, #1 + 801cbee: d1f3 bne.n 801cbd8 <__sfputs_r+0xa> + 801cbf0: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +0801cbf4 <_vfiprintf_r>: + 801cbf4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801cbf8: 460d mov r5, r1 + 801cbfa: b09d sub sp, #116 ; 0x74 + 801cbfc: 4614 mov r4, r2 + 801cbfe: 4698 mov r8, r3 + 801cc00: 4606 mov r6, r0 + 801cc02: b118 cbz r0, 801cc0c <_vfiprintf_r+0x18> + 801cc04: 6983 ldr r3, [r0, #24] + 801cc06: b90b cbnz r3, 801cc0c <_vfiprintf_r+0x18> + 801cc08: f7ff f86a bl 801bce0 <__sinit> + 801cc0c: 4b89 ldr r3, [pc, #548] ; (801ce34 <_vfiprintf_r+0x240>) + 801cc0e: 429d cmp r5, r3 + 801cc10: d11b bne.n 801cc4a <_vfiprintf_r+0x56> + 801cc12: 6875 ldr r5, [r6, #4] + 801cc14: 6e6b ldr r3, [r5, #100] ; 0x64 + 801cc16: 07d9 lsls r1, r3, #31 + 801cc18: d405 bmi.n 801cc26 <_vfiprintf_r+0x32> + 801cc1a: 89ab ldrh r3, [r5, #12] + 801cc1c: 059a lsls r2, r3, #22 + 801cc1e: d402 bmi.n 801cc26 <_vfiprintf_r+0x32> + 801cc20: 6da8 ldr r0, [r5, #88] ; 0x58 + 801cc22: f7ff f920 bl 801be66 <__retarget_lock_acquire_recursive> + 801cc26: 89ab ldrh r3, [r5, #12] + 801cc28: 071b lsls r3, r3, #28 + 801cc2a: d501 bpl.n 801cc30 <_vfiprintf_r+0x3c> + 801cc2c: 692b ldr r3, [r5, #16] + 801cc2e: b9eb cbnz r3, 801cc6c <_vfiprintf_r+0x78> + 801cc30: 4629 mov r1, r5 + 801cc32: 4630 mov r0, r6 + 801cc34: f7ff fc10 bl 801c458 <__swsetup_r> + 801cc38: b1c0 cbz r0, 801cc6c <_vfiprintf_r+0x78> + 801cc3a: 6e6b ldr r3, [r5, #100] ; 0x64 + 801cc3c: 07dc lsls r4, r3, #31 + 801cc3e: d50e bpl.n 801cc5e <_vfiprintf_r+0x6a> + 801cc40: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801cc44: b01d add sp, #116 ; 0x74 + 801cc46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801cc4a: 4b7b ldr r3, [pc, #492] ; (801ce38 <_vfiprintf_r+0x244>) + 801cc4c: 429d cmp r5, r3 + 801cc4e: d101 bne.n 801cc54 <_vfiprintf_r+0x60> + 801cc50: 68b5 ldr r5, [r6, #8] + 801cc52: e7df b.n 801cc14 <_vfiprintf_r+0x20> + 801cc54: 4b79 ldr r3, [pc, #484] ; (801ce3c <_vfiprintf_r+0x248>) + 801cc56: 429d cmp r5, r3 + 801cc58: bf08 it eq + 801cc5a: 68f5 ldreq r5, [r6, #12] + 801cc5c: e7da b.n 801cc14 <_vfiprintf_r+0x20> + 801cc5e: 89ab ldrh r3, [r5, #12] + 801cc60: 0598 lsls r0, r3, #22 + 801cc62: d4ed bmi.n 801cc40 <_vfiprintf_r+0x4c> + 801cc64: 6da8 ldr r0, [r5, #88] ; 0x58 + 801cc66: f7ff f8ff bl 801be68 <__retarget_lock_release_recursive> + 801cc6a: e7e9 b.n 801cc40 <_vfiprintf_r+0x4c> + 801cc6c: 2300 movs r3, #0 + 801cc6e: 9309 str r3, [sp, #36] ; 0x24 + 801cc70: 2320 movs r3, #32 + 801cc72: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 801cc76: f8cd 800c str.w r8, [sp, #12] + 801cc7a: 2330 movs r3, #48 ; 0x30 + 801cc7c: f8df 81c0 ldr.w r8, [pc, #448] ; 801ce40 <_vfiprintf_r+0x24c> + 801cc80: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 801cc84: f04f 0901 mov.w r9, #1 + 801cc88: 4623 mov r3, r4 + 801cc8a: 469a mov sl, r3 + 801cc8c: f813 2b01 ldrb.w r2, [r3], #1 + 801cc90: b10a cbz r2, 801cc96 <_vfiprintf_r+0xa2> + 801cc92: 2a25 cmp r2, #37 ; 0x25 + 801cc94: d1f9 bne.n 801cc8a <_vfiprintf_r+0x96> + 801cc96: ebba 0b04 subs.w fp, sl, r4 + 801cc9a: d00b beq.n 801ccb4 <_vfiprintf_r+0xc0> + 801cc9c: 465b mov r3, fp + 801cc9e: 4622 mov r2, r4 + 801cca0: 4629 mov r1, r5 + 801cca2: 4630 mov r0, r6 + 801cca4: f7ff ff93 bl 801cbce <__sfputs_r> + 801cca8: 3001 adds r0, #1 + 801ccaa: f000 80aa beq.w 801ce02 <_vfiprintf_r+0x20e> + 801ccae: 9a09 ldr r2, [sp, #36] ; 0x24 + 801ccb0: 445a add r2, fp + 801ccb2: 9209 str r2, [sp, #36] ; 0x24 + 801ccb4: f89a 3000 ldrb.w r3, [sl] + 801ccb8: 2b00 cmp r3, #0 + 801ccba: f000 80a2 beq.w 801ce02 <_vfiprintf_r+0x20e> + 801ccbe: 2300 movs r3, #0 + 801ccc0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 801ccc4: e9cd 2305 strd r2, r3, [sp, #20] + 801ccc8: f10a 0a01 add.w sl, sl, #1 + 801cccc: 9304 str r3, [sp, #16] + 801ccce: 9307 str r3, [sp, #28] + 801ccd0: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 801ccd4: 931a str r3, [sp, #104] ; 0x68 + 801ccd6: 4654 mov r4, sl + 801ccd8: 2205 movs r2, #5 + 801ccda: f814 1b01 ldrb.w r1, [r4], #1 + 801ccde: 4858 ldr r0, [pc, #352] ; (801ce40 <_vfiprintf_r+0x24c>) + 801cce0: f7e3 fa9e bl 8000220 + 801cce4: 9a04 ldr r2, [sp, #16] + 801cce6: b9d8 cbnz r0, 801cd20 <_vfiprintf_r+0x12c> + 801cce8: 06d1 lsls r1, r2, #27 + 801ccea: bf44 itt mi + 801ccec: 2320 movmi r3, #32 + 801ccee: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 801ccf2: 0713 lsls r3, r2, #28 + 801ccf4: bf44 itt mi + 801ccf6: 232b movmi r3, #43 ; 0x2b + 801ccf8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 801ccfc: f89a 3000 ldrb.w r3, [sl] + 801cd00: 2b2a cmp r3, #42 ; 0x2a + 801cd02: d015 beq.n 801cd30 <_vfiprintf_r+0x13c> + 801cd04: 9a07 ldr r2, [sp, #28] + 801cd06: 4654 mov r4, sl + 801cd08: 2000 movs r0, #0 + 801cd0a: f04f 0c0a mov.w ip, #10 + 801cd0e: 4621 mov r1, r4 + 801cd10: f811 3b01 ldrb.w r3, [r1], #1 + 801cd14: 3b30 subs r3, #48 ; 0x30 + 801cd16: 2b09 cmp r3, #9 + 801cd18: d94e bls.n 801cdb8 <_vfiprintf_r+0x1c4> + 801cd1a: b1b0 cbz r0, 801cd4a <_vfiprintf_r+0x156> + 801cd1c: 9207 str r2, [sp, #28] + 801cd1e: e014 b.n 801cd4a <_vfiprintf_r+0x156> + 801cd20: eba0 0308 sub.w r3, r0, r8 + 801cd24: fa09 f303 lsl.w r3, r9, r3 + 801cd28: 4313 orrs r3, r2 + 801cd2a: 9304 str r3, [sp, #16] + 801cd2c: 46a2 mov sl, r4 + 801cd2e: e7d2 b.n 801ccd6 <_vfiprintf_r+0xe2> + 801cd30: 9b03 ldr r3, [sp, #12] + 801cd32: 1d19 adds r1, r3, #4 + 801cd34: 681b ldr r3, [r3, #0] + 801cd36: 9103 str r1, [sp, #12] + 801cd38: 2b00 cmp r3, #0 + 801cd3a: bfbb ittet lt + 801cd3c: 425b neglt r3, r3 + 801cd3e: f042 0202 orrlt.w r2, r2, #2 + 801cd42: 9307 strge r3, [sp, #28] + 801cd44: 9307 strlt r3, [sp, #28] + 801cd46: bfb8 it lt + 801cd48: 9204 strlt r2, [sp, #16] + 801cd4a: 7823 ldrb r3, [r4, #0] + 801cd4c: 2b2e cmp r3, #46 ; 0x2e + 801cd4e: d10c bne.n 801cd6a <_vfiprintf_r+0x176> + 801cd50: 7863 ldrb r3, [r4, #1] + 801cd52: 2b2a cmp r3, #42 ; 0x2a + 801cd54: d135 bne.n 801cdc2 <_vfiprintf_r+0x1ce> + 801cd56: 9b03 ldr r3, [sp, #12] + 801cd58: 1d1a adds r2, r3, #4 + 801cd5a: 681b ldr r3, [r3, #0] + 801cd5c: 9203 str r2, [sp, #12] + 801cd5e: 2b00 cmp r3, #0 + 801cd60: bfb8 it lt + 801cd62: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff + 801cd66: 3402 adds r4, #2 + 801cd68: 9305 str r3, [sp, #20] + 801cd6a: f8df a0e4 ldr.w sl, [pc, #228] ; 801ce50 <_vfiprintf_r+0x25c> + 801cd6e: 7821 ldrb r1, [r4, #0] + 801cd70: 2203 movs r2, #3 + 801cd72: 4650 mov r0, sl + 801cd74: f7e3 fa54 bl 8000220 + 801cd78: b140 cbz r0, 801cd8c <_vfiprintf_r+0x198> + 801cd7a: 2340 movs r3, #64 ; 0x40 + 801cd7c: eba0 000a sub.w r0, r0, sl + 801cd80: fa03 f000 lsl.w r0, r3, r0 + 801cd84: 9b04 ldr r3, [sp, #16] + 801cd86: 4303 orrs r3, r0 + 801cd88: 3401 adds r4, #1 + 801cd8a: 9304 str r3, [sp, #16] + 801cd8c: f814 1b01 ldrb.w r1, [r4], #1 + 801cd90: 482c ldr r0, [pc, #176] ; (801ce44 <_vfiprintf_r+0x250>) + 801cd92: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 801cd96: 2206 movs r2, #6 + 801cd98: f7e3 fa42 bl 8000220 + 801cd9c: 2800 cmp r0, #0 + 801cd9e: d03f beq.n 801ce20 <_vfiprintf_r+0x22c> + 801cda0: 4b29 ldr r3, [pc, #164] ; (801ce48 <_vfiprintf_r+0x254>) + 801cda2: bb1b cbnz r3, 801cdec <_vfiprintf_r+0x1f8> + 801cda4: 9b03 ldr r3, [sp, #12] + 801cda6: 3307 adds r3, #7 + 801cda8: f023 0307 bic.w r3, r3, #7 + 801cdac: 3308 adds r3, #8 + 801cdae: 9303 str r3, [sp, #12] + 801cdb0: 9b09 ldr r3, [sp, #36] ; 0x24 + 801cdb2: 443b add r3, r7 + 801cdb4: 9309 str r3, [sp, #36] ; 0x24 + 801cdb6: e767 b.n 801cc88 <_vfiprintf_r+0x94> + 801cdb8: fb0c 3202 mla r2, ip, r2, r3 + 801cdbc: 460c mov r4, r1 + 801cdbe: 2001 movs r0, #1 + 801cdc0: e7a5 b.n 801cd0e <_vfiprintf_r+0x11a> + 801cdc2: 2300 movs r3, #0 + 801cdc4: 3401 adds r4, #1 + 801cdc6: 9305 str r3, [sp, #20] + 801cdc8: 4619 mov r1, r3 + 801cdca: f04f 0c0a mov.w ip, #10 + 801cdce: 4620 mov r0, r4 + 801cdd0: f810 2b01 ldrb.w r2, [r0], #1 + 801cdd4: 3a30 subs r2, #48 ; 0x30 + 801cdd6: 2a09 cmp r2, #9 + 801cdd8: d903 bls.n 801cde2 <_vfiprintf_r+0x1ee> + 801cdda: 2b00 cmp r3, #0 + 801cddc: d0c5 beq.n 801cd6a <_vfiprintf_r+0x176> + 801cdde: 9105 str r1, [sp, #20] + 801cde0: e7c3 b.n 801cd6a <_vfiprintf_r+0x176> + 801cde2: fb0c 2101 mla r1, ip, r1, r2 + 801cde6: 4604 mov r4, r0 + 801cde8: 2301 movs r3, #1 + 801cdea: e7f0 b.n 801cdce <_vfiprintf_r+0x1da> + 801cdec: ab03 add r3, sp, #12 + 801cdee: 9300 str r3, [sp, #0] + 801cdf0: 462a mov r2, r5 + 801cdf2: 4b16 ldr r3, [pc, #88] ; (801ce4c <_vfiprintf_r+0x258>) + 801cdf4: a904 add r1, sp, #16 + 801cdf6: 4630 mov r0, r6 + 801cdf8: f3af 8000 nop.w + 801cdfc: 4607 mov r7, r0 + 801cdfe: 1c78 adds r0, r7, #1 + 801ce00: d1d6 bne.n 801cdb0 <_vfiprintf_r+0x1bc> + 801ce02: 6e6b ldr r3, [r5, #100] ; 0x64 + 801ce04: 07d9 lsls r1, r3, #31 + 801ce06: d405 bmi.n 801ce14 <_vfiprintf_r+0x220> + 801ce08: 89ab ldrh r3, [r5, #12] + 801ce0a: 059a lsls r2, r3, #22 + 801ce0c: d402 bmi.n 801ce14 <_vfiprintf_r+0x220> + 801ce0e: 6da8 ldr r0, [r5, #88] ; 0x58 + 801ce10: f7ff f82a bl 801be68 <__retarget_lock_release_recursive> + 801ce14: 89ab ldrh r3, [r5, #12] + 801ce16: 065b lsls r3, r3, #25 + 801ce18: f53f af12 bmi.w 801cc40 <_vfiprintf_r+0x4c> + 801ce1c: 9809 ldr r0, [sp, #36] ; 0x24 + 801ce1e: e711 b.n 801cc44 <_vfiprintf_r+0x50> + 801ce20: ab03 add r3, sp, #12 + 801ce22: 9300 str r3, [sp, #0] + 801ce24: 462a mov r2, r5 + 801ce26: 4b09 ldr r3, [pc, #36] ; (801ce4c <_vfiprintf_r+0x258>) + 801ce28: a904 add r1, sp, #16 + 801ce2a: 4630 mov r0, r6 + 801ce2c: f000 f880 bl 801cf30 <_printf_i> + 801ce30: e7e4 b.n 801cdfc <_vfiprintf_r+0x208> + 801ce32: bf00 nop + 801ce34: 08023a58 .word 0x08023a58 + 801ce38: 08023a78 .word 0x08023a78 + 801ce3c: 08023a38 .word 0x08023a38 + 801ce40: 08023b4a .word 0x08023b4a + 801ce44: 08023b54 .word 0x08023b54 + 801ce48: 00000000 .word 0x00000000 + 801ce4c: 0801cbcf .word 0x0801cbcf + 801ce50: 08023b50 .word 0x08023b50 + +0801ce54 <_printf_common>: + 801ce54: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 801ce58: 4616 mov r6, r2 + 801ce5a: 4699 mov r9, r3 + 801ce5c: 688a ldr r2, [r1, #8] + 801ce5e: 690b ldr r3, [r1, #16] + 801ce60: f8dd 8020 ldr.w r8, [sp, #32] + 801ce64: 4293 cmp r3, r2 + 801ce66: bfb8 it lt + 801ce68: 4613 movlt r3, r2 + 801ce6a: 6033 str r3, [r6, #0] + 801ce6c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 801ce70: 4607 mov r7, r0 + 801ce72: 460c mov r4, r1 + 801ce74: b10a cbz r2, 801ce7a <_printf_common+0x26> + 801ce76: 3301 adds r3, #1 + 801ce78: 6033 str r3, [r6, #0] + 801ce7a: 6823 ldr r3, [r4, #0] + 801ce7c: 0699 lsls r1, r3, #26 + 801ce7e: bf42 ittt mi + 801ce80: 6833 ldrmi r3, [r6, #0] + 801ce82: 3302 addmi r3, #2 + 801ce84: 6033 strmi r3, [r6, #0] + 801ce86: 6825 ldr r5, [r4, #0] + 801ce88: f015 0506 ands.w r5, r5, #6 + 801ce8c: d106 bne.n 801ce9c <_printf_common+0x48> + 801ce8e: f104 0a19 add.w sl, r4, #25 + 801ce92: 68e3 ldr r3, [r4, #12] + 801ce94: 6832 ldr r2, [r6, #0] + 801ce96: 1a9b subs r3, r3, r2 + 801ce98: 42ab cmp r3, r5 + 801ce9a: dc26 bgt.n 801ceea <_printf_common+0x96> + 801ce9c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 801cea0: 1e13 subs r3, r2, #0 + 801cea2: 6822 ldr r2, [r4, #0] + 801cea4: bf18 it ne + 801cea6: 2301 movne r3, #1 + 801cea8: 0692 lsls r2, r2, #26 + 801ceaa: d42b bmi.n 801cf04 <_printf_common+0xb0> + 801ceac: f104 0243 add.w r2, r4, #67 ; 0x43 + 801ceb0: 4649 mov r1, r9 + 801ceb2: 4638 mov r0, r7 + 801ceb4: 47c0 blx r8 + 801ceb6: 3001 adds r0, #1 + 801ceb8: d01e beq.n 801cef8 <_printf_common+0xa4> + 801ceba: 6823 ldr r3, [r4, #0] + 801cebc: 68e5 ldr r5, [r4, #12] + 801cebe: 6832 ldr r2, [r6, #0] + 801cec0: f003 0306 and.w r3, r3, #6 + 801cec4: 2b04 cmp r3, #4 + 801cec6: bf08 it eq + 801cec8: 1aad subeq r5, r5, r2 + 801ceca: 68a3 ldr r3, [r4, #8] + 801cecc: 6922 ldr r2, [r4, #16] + 801cece: bf0c ite eq + 801ced0: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 801ced4: 2500 movne r5, #0 + 801ced6: 4293 cmp r3, r2 + 801ced8: bfc4 itt gt + 801ceda: 1a9b subgt r3, r3, r2 + 801cedc: 18ed addgt r5, r5, r3 + 801cede: 2600 movs r6, #0 + 801cee0: 341a adds r4, #26 + 801cee2: 42b5 cmp r5, r6 + 801cee4: d11a bne.n 801cf1c <_printf_common+0xc8> + 801cee6: 2000 movs r0, #0 + 801cee8: e008 b.n 801cefc <_printf_common+0xa8> + 801ceea: 2301 movs r3, #1 + 801ceec: 4652 mov r2, sl + 801ceee: 4649 mov r1, r9 + 801cef0: 4638 mov r0, r7 + 801cef2: 47c0 blx r8 + 801cef4: 3001 adds r0, #1 + 801cef6: d103 bne.n 801cf00 <_printf_common+0xac> + 801cef8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801cefc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801cf00: 3501 adds r5, #1 + 801cf02: e7c6 b.n 801ce92 <_printf_common+0x3e> + 801cf04: 18e1 adds r1, r4, r3 + 801cf06: 1c5a adds r2, r3, #1 + 801cf08: 2030 movs r0, #48 ; 0x30 + 801cf0a: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 801cf0e: 4422 add r2, r4 + 801cf10: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 801cf14: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 801cf18: 3302 adds r3, #2 + 801cf1a: e7c7 b.n 801ceac <_printf_common+0x58> + 801cf1c: 2301 movs r3, #1 + 801cf1e: 4622 mov r2, r4 + 801cf20: 4649 mov r1, r9 + 801cf22: 4638 mov r0, r7 + 801cf24: 47c0 blx r8 + 801cf26: 3001 adds r0, #1 + 801cf28: d0e6 beq.n 801cef8 <_printf_common+0xa4> + 801cf2a: 3601 adds r6, #1 + 801cf2c: e7d9 b.n 801cee2 <_printf_common+0x8e> + ... + +0801cf30 <_printf_i>: + 801cf30: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 801cf34: 7e0f ldrb r7, [r1, #24] + 801cf36: 9d0c ldr r5, [sp, #48] ; 0x30 + 801cf38: 2f78 cmp r7, #120 ; 0x78 + 801cf3a: 4691 mov r9, r2 + 801cf3c: 4680 mov r8, r0 + 801cf3e: 460c mov r4, r1 + 801cf40: 469a mov sl, r3 + 801cf42: f101 0243 add.w r2, r1, #67 ; 0x43 + 801cf46: d807 bhi.n 801cf58 <_printf_i+0x28> + 801cf48: 2f62 cmp r7, #98 ; 0x62 + 801cf4a: d80a bhi.n 801cf62 <_printf_i+0x32> + 801cf4c: 2f00 cmp r7, #0 + 801cf4e: f000 80d8 beq.w 801d102 <_printf_i+0x1d2> + 801cf52: 2f58 cmp r7, #88 ; 0x58 + 801cf54: f000 80a3 beq.w 801d09e <_printf_i+0x16e> + 801cf58: f104 0542 add.w r5, r4, #66 ; 0x42 + 801cf5c: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 801cf60: e03a b.n 801cfd8 <_printf_i+0xa8> + 801cf62: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 801cf66: 2b15 cmp r3, #21 + 801cf68: d8f6 bhi.n 801cf58 <_printf_i+0x28> + 801cf6a: a101 add r1, pc, #4 ; (adr r1, 801cf70 <_printf_i+0x40>) + 801cf6c: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 801cf70: 0801cfc9 .word 0x0801cfc9 + 801cf74: 0801cfdd .word 0x0801cfdd + 801cf78: 0801cf59 .word 0x0801cf59 + 801cf7c: 0801cf59 .word 0x0801cf59 + 801cf80: 0801cf59 .word 0x0801cf59 + 801cf84: 0801cf59 .word 0x0801cf59 + 801cf88: 0801cfdd .word 0x0801cfdd + 801cf8c: 0801cf59 .word 0x0801cf59 + 801cf90: 0801cf59 .word 0x0801cf59 + 801cf94: 0801cf59 .word 0x0801cf59 + 801cf98: 0801cf59 .word 0x0801cf59 + 801cf9c: 0801d0e9 .word 0x0801d0e9 + 801cfa0: 0801d00d .word 0x0801d00d + 801cfa4: 0801d0cb .word 0x0801d0cb + 801cfa8: 0801cf59 .word 0x0801cf59 + 801cfac: 0801cf59 .word 0x0801cf59 + 801cfb0: 0801d10b .word 0x0801d10b + 801cfb4: 0801cf59 .word 0x0801cf59 + 801cfb8: 0801d00d .word 0x0801d00d + 801cfbc: 0801cf59 .word 0x0801cf59 + 801cfc0: 0801cf59 .word 0x0801cf59 + 801cfc4: 0801d0d3 .word 0x0801d0d3 + 801cfc8: 682b ldr r3, [r5, #0] + 801cfca: 1d1a adds r2, r3, #4 + 801cfcc: 681b ldr r3, [r3, #0] + 801cfce: 602a str r2, [r5, #0] + 801cfd0: f104 0542 add.w r5, r4, #66 ; 0x42 + 801cfd4: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 801cfd8: 2301 movs r3, #1 + 801cfda: e0a3 b.n 801d124 <_printf_i+0x1f4> + 801cfdc: 6820 ldr r0, [r4, #0] + 801cfde: 6829 ldr r1, [r5, #0] + 801cfe0: 0606 lsls r6, r0, #24 + 801cfe2: f101 0304 add.w r3, r1, #4 + 801cfe6: d50a bpl.n 801cffe <_printf_i+0xce> + 801cfe8: 680e ldr r6, [r1, #0] + 801cfea: 602b str r3, [r5, #0] + 801cfec: 2e00 cmp r6, #0 + 801cfee: da03 bge.n 801cff8 <_printf_i+0xc8> + 801cff0: 232d movs r3, #45 ; 0x2d + 801cff2: 4276 negs r6, r6 + 801cff4: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 801cff8: 485e ldr r0, [pc, #376] ; (801d174 <_printf_i+0x244>) + 801cffa: 230a movs r3, #10 + 801cffc: e019 b.n 801d032 <_printf_i+0x102> + 801cffe: 680e ldr r6, [r1, #0] + 801d000: 602b str r3, [r5, #0] + 801d002: f010 0f40 tst.w r0, #64 ; 0x40 + 801d006: bf18 it ne + 801d008: b236 sxthne r6, r6 + 801d00a: e7ef b.n 801cfec <_printf_i+0xbc> + 801d00c: 682b ldr r3, [r5, #0] + 801d00e: 6820 ldr r0, [r4, #0] + 801d010: 1d19 adds r1, r3, #4 + 801d012: 6029 str r1, [r5, #0] + 801d014: 0601 lsls r1, r0, #24 + 801d016: d501 bpl.n 801d01c <_printf_i+0xec> + 801d018: 681e ldr r6, [r3, #0] + 801d01a: e002 b.n 801d022 <_printf_i+0xf2> + 801d01c: 0646 lsls r6, r0, #25 + 801d01e: d5fb bpl.n 801d018 <_printf_i+0xe8> + 801d020: 881e ldrh r6, [r3, #0] + 801d022: 4854 ldr r0, [pc, #336] ; (801d174 <_printf_i+0x244>) + 801d024: 2f6f cmp r7, #111 ; 0x6f + 801d026: bf0c ite eq + 801d028: 2308 moveq r3, #8 + 801d02a: 230a movne r3, #10 + 801d02c: 2100 movs r1, #0 + 801d02e: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 801d032: 6865 ldr r5, [r4, #4] + 801d034: 60a5 str r5, [r4, #8] + 801d036: 2d00 cmp r5, #0 + 801d038: bfa2 ittt ge + 801d03a: 6821 ldrge r1, [r4, #0] + 801d03c: f021 0104 bicge.w r1, r1, #4 + 801d040: 6021 strge r1, [r4, #0] + 801d042: b90e cbnz r6, 801d048 <_printf_i+0x118> + 801d044: 2d00 cmp r5, #0 + 801d046: d04d beq.n 801d0e4 <_printf_i+0x1b4> + 801d048: 4615 mov r5, r2 + 801d04a: fbb6 f1f3 udiv r1, r6, r3 + 801d04e: fb03 6711 mls r7, r3, r1, r6 + 801d052: 5dc7 ldrb r7, [r0, r7] + 801d054: f805 7d01 strb.w r7, [r5, #-1]! + 801d058: 4637 mov r7, r6 + 801d05a: 42bb cmp r3, r7 + 801d05c: 460e mov r6, r1 + 801d05e: d9f4 bls.n 801d04a <_printf_i+0x11a> + 801d060: 2b08 cmp r3, #8 + 801d062: d10b bne.n 801d07c <_printf_i+0x14c> + 801d064: 6823 ldr r3, [r4, #0] + 801d066: 07de lsls r6, r3, #31 + 801d068: d508 bpl.n 801d07c <_printf_i+0x14c> + 801d06a: 6923 ldr r3, [r4, #16] + 801d06c: 6861 ldr r1, [r4, #4] + 801d06e: 4299 cmp r1, r3 + 801d070: bfde ittt le + 801d072: 2330 movle r3, #48 ; 0x30 + 801d074: f805 3c01 strble.w r3, [r5, #-1] + 801d078: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff + 801d07c: 1b52 subs r2, r2, r5 + 801d07e: 6122 str r2, [r4, #16] + 801d080: f8cd a000 str.w sl, [sp] + 801d084: 464b mov r3, r9 + 801d086: aa03 add r2, sp, #12 + 801d088: 4621 mov r1, r4 + 801d08a: 4640 mov r0, r8 + 801d08c: f7ff fee2 bl 801ce54 <_printf_common> + 801d090: 3001 adds r0, #1 + 801d092: d14c bne.n 801d12e <_printf_i+0x1fe> + 801d094: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801d098: b004 add sp, #16 + 801d09a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801d09e: 4835 ldr r0, [pc, #212] ; (801d174 <_printf_i+0x244>) + 801d0a0: f881 7045 strb.w r7, [r1, #69] ; 0x45 + 801d0a4: 6829 ldr r1, [r5, #0] + 801d0a6: 6823 ldr r3, [r4, #0] + 801d0a8: f851 6b04 ldr.w r6, [r1], #4 + 801d0ac: 6029 str r1, [r5, #0] + 801d0ae: 061d lsls r5, r3, #24 + 801d0b0: d514 bpl.n 801d0dc <_printf_i+0x1ac> + 801d0b2: 07df lsls r7, r3, #31 + 801d0b4: bf44 itt mi + 801d0b6: f043 0320 orrmi.w r3, r3, #32 + 801d0ba: 6023 strmi r3, [r4, #0] + 801d0bc: b91e cbnz r6, 801d0c6 <_printf_i+0x196> + 801d0be: 6823 ldr r3, [r4, #0] + 801d0c0: f023 0320 bic.w r3, r3, #32 + 801d0c4: 6023 str r3, [r4, #0] + 801d0c6: 2310 movs r3, #16 + 801d0c8: e7b0 b.n 801d02c <_printf_i+0xfc> + 801d0ca: 6823 ldr r3, [r4, #0] + 801d0cc: f043 0320 orr.w r3, r3, #32 + 801d0d0: 6023 str r3, [r4, #0] + 801d0d2: 2378 movs r3, #120 ; 0x78 + 801d0d4: 4828 ldr r0, [pc, #160] ; (801d178 <_printf_i+0x248>) + 801d0d6: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 801d0da: e7e3 b.n 801d0a4 <_printf_i+0x174> + 801d0dc: 0659 lsls r1, r3, #25 + 801d0de: bf48 it mi + 801d0e0: b2b6 uxthmi r6, r6 + 801d0e2: e7e6 b.n 801d0b2 <_printf_i+0x182> + 801d0e4: 4615 mov r5, r2 + 801d0e6: e7bb b.n 801d060 <_printf_i+0x130> + 801d0e8: 682b ldr r3, [r5, #0] + 801d0ea: 6826 ldr r6, [r4, #0] + 801d0ec: 6961 ldr r1, [r4, #20] + 801d0ee: 1d18 adds r0, r3, #4 + 801d0f0: 6028 str r0, [r5, #0] + 801d0f2: 0635 lsls r5, r6, #24 + 801d0f4: 681b ldr r3, [r3, #0] + 801d0f6: d501 bpl.n 801d0fc <_printf_i+0x1cc> + 801d0f8: 6019 str r1, [r3, #0] + 801d0fa: e002 b.n 801d102 <_printf_i+0x1d2> + 801d0fc: 0670 lsls r0, r6, #25 + 801d0fe: d5fb bpl.n 801d0f8 <_printf_i+0x1c8> + 801d100: 8019 strh r1, [r3, #0] + 801d102: 2300 movs r3, #0 + 801d104: 6123 str r3, [r4, #16] + 801d106: 4615 mov r5, r2 + 801d108: e7ba b.n 801d080 <_printf_i+0x150> + 801d10a: 682b ldr r3, [r5, #0] + 801d10c: 1d1a adds r2, r3, #4 + 801d10e: 602a str r2, [r5, #0] + 801d110: 681d ldr r5, [r3, #0] + 801d112: 6862 ldr r2, [r4, #4] + 801d114: 2100 movs r1, #0 + 801d116: 4628 mov r0, r5 + 801d118: f7e3 f882 bl 8000220 + 801d11c: b108 cbz r0, 801d122 <_printf_i+0x1f2> + 801d11e: 1b40 subs r0, r0, r5 + 801d120: 6060 str r0, [r4, #4] + 801d122: 6863 ldr r3, [r4, #4] + 801d124: 6123 str r3, [r4, #16] + 801d126: 2300 movs r3, #0 + 801d128: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 801d12c: e7a8 b.n 801d080 <_printf_i+0x150> + 801d12e: 6923 ldr r3, [r4, #16] + 801d130: 462a mov r2, r5 + 801d132: 4649 mov r1, r9 + 801d134: 4640 mov r0, r8 + 801d136: 47d0 blx sl + 801d138: 3001 adds r0, #1 + 801d13a: d0ab beq.n 801d094 <_printf_i+0x164> + 801d13c: 6823 ldr r3, [r4, #0] + 801d13e: 079b lsls r3, r3, #30 + 801d140: d413 bmi.n 801d16a <_printf_i+0x23a> + 801d142: 68e0 ldr r0, [r4, #12] + 801d144: 9b03 ldr r3, [sp, #12] + 801d146: 4298 cmp r0, r3 + 801d148: bfb8 it lt + 801d14a: 4618 movlt r0, r3 + 801d14c: e7a4 b.n 801d098 <_printf_i+0x168> + 801d14e: 2301 movs r3, #1 + 801d150: 4632 mov r2, r6 + 801d152: 4649 mov r1, r9 + 801d154: 4640 mov r0, r8 + 801d156: 47d0 blx sl + 801d158: 3001 adds r0, #1 + 801d15a: d09b beq.n 801d094 <_printf_i+0x164> + 801d15c: 3501 adds r5, #1 + 801d15e: 68e3 ldr r3, [r4, #12] + 801d160: 9903 ldr r1, [sp, #12] + 801d162: 1a5b subs r3, r3, r1 + 801d164: 42ab cmp r3, r5 + 801d166: dcf2 bgt.n 801d14e <_printf_i+0x21e> + 801d168: e7eb b.n 801d142 <_printf_i+0x212> + 801d16a: 2500 movs r5, #0 + 801d16c: f104 0619 add.w r6, r4, #25 + 801d170: e7f5 b.n 801d15e <_printf_i+0x22e> + 801d172: bf00 nop + 801d174: 08023b5b .word 0x08023b5b + 801d178: 08023b6c .word 0x08023b6c + +0801d17c <_read_r>: + 801d17c: b538 push {r3, r4, r5, lr} + 801d17e: 4d07 ldr r5, [pc, #28] ; (801d19c <_read_r+0x20>) + 801d180: 4604 mov r4, r0 + 801d182: 4608 mov r0, r1 + 801d184: 4611 mov r1, r2 + 801d186: 2200 movs r2, #0 + 801d188: 602a str r2, [r5, #0] + 801d18a: 461a mov r2, r3 + 801d18c: f7e5 f902 bl 8002394 <_read> + 801d190: 1c43 adds r3, r0, #1 + 801d192: d102 bne.n 801d19a <_read_r+0x1e> + 801d194: 682b ldr r3, [r5, #0] + 801d196: b103 cbz r3, 801d19a <_read_r+0x1e> + 801d198: 6023 str r3, [r4, #0] + 801d19a: bd38 pop {r3, r4, r5, pc} + 801d19c: 2000d0ec .word 0x2000d0ec + +0801d1a0 : + 801d1a0: b508 push {r3, lr} + 801d1a2: 2006 movs r0, #6 + 801d1a4: f000 f87e bl 801d2a4 + 801d1a8: 2001 movs r0, #1 + 801d1aa: f7e6 f8b7 bl 800331c <_exit> + ... + +0801d1b0 <_fstat_r>: + 801d1b0: b538 push {r3, r4, r5, lr} + 801d1b2: 4d07 ldr r5, [pc, #28] ; (801d1d0 <_fstat_r+0x20>) + 801d1b4: 2300 movs r3, #0 + 801d1b6: 4604 mov r4, r0 + 801d1b8: 4608 mov r0, r1 + 801d1ba: 4611 mov r1, r2 + 801d1bc: 602b str r3, [r5, #0] + 801d1be: f7e6 f8c3 bl 8003348 <_fstat> + 801d1c2: 1c43 adds r3, r0, #1 + 801d1c4: d102 bne.n 801d1cc <_fstat_r+0x1c> + 801d1c6: 682b ldr r3, [r5, #0] + 801d1c8: b103 cbz r3, 801d1cc <_fstat_r+0x1c> + 801d1ca: 6023 str r3, [r4, #0] + 801d1cc: bd38 pop {r3, r4, r5, pc} + 801d1ce: bf00 nop + 801d1d0: 2000d0ec .word 0x2000d0ec + +0801d1d4 <_isatty_r>: + 801d1d4: b538 push {r3, r4, r5, lr} + 801d1d6: 4d06 ldr r5, [pc, #24] ; (801d1f0 <_isatty_r+0x1c>) + 801d1d8: 2300 movs r3, #0 + 801d1da: 4604 mov r4, r0 + 801d1dc: 4608 mov r0, r1 + 801d1de: 602b str r3, [r5, #0] + 801d1e0: f7e6 f8c2 bl 8003368 <_isatty> + 801d1e4: 1c43 adds r3, r0, #1 + 801d1e6: d102 bne.n 801d1ee <_isatty_r+0x1a> + 801d1e8: 682b ldr r3, [r5, #0] + 801d1ea: b103 cbz r3, 801d1ee <_isatty_r+0x1a> + 801d1ec: 6023 str r3, [r4, #0] + 801d1ee: bd38 pop {r3, r4, r5, pc} + 801d1f0: 2000d0ec .word 0x2000d0ec + +0801d1f4 <_realloc_r>: + 801d1f4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801d1f8: 4680 mov r8, r0 + 801d1fa: 4614 mov r4, r2 + 801d1fc: 460e mov r6, r1 + 801d1fe: b921 cbnz r1, 801d20a <_realloc_r+0x16> + 801d200: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 801d204: 4611 mov r1, r2 + 801d206: f7fe be91 b.w 801bf2c <_malloc_r> + 801d20a: b92a cbnz r2, 801d218 <_realloc_r+0x24> + 801d20c: f7ff fb20 bl 801c850 <_free_r> + 801d210: 4625 mov r5, r4 + 801d212: 4628 mov r0, r5 + 801d214: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801d218: f000 f860 bl 801d2dc <_malloc_usable_size_r> + 801d21c: 4284 cmp r4, r0 + 801d21e: 4607 mov r7, r0 + 801d220: d802 bhi.n 801d228 <_realloc_r+0x34> + 801d222: ebb4 0f50 cmp.w r4, r0, lsr #1 + 801d226: d812 bhi.n 801d24e <_realloc_r+0x5a> + 801d228: 4621 mov r1, r4 + 801d22a: 4640 mov r0, r8 + 801d22c: f7fe fe7e bl 801bf2c <_malloc_r> + 801d230: 4605 mov r5, r0 + 801d232: 2800 cmp r0, #0 + 801d234: d0ed beq.n 801d212 <_realloc_r+0x1e> + 801d236: 42bc cmp r4, r7 + 801d238: 4622 mov r2, r4 + 801d23a: 4631 mov r1, r6 + 801d23c: bf28 it cs + 801d23e: 463a movcs r2, r7 + 801d240: f7fe fe23 bl 801be8a + 801d244: 4631 mov r1, r6 + 801d246: 4640 mov r0, r8 + 801d248: f7ff fb02 bl 801c850 <_free_r> + 801d24c: e7e1 b.n 801d212 <_realloc_r+0x1e> + 801d24e: 4635 mov r5, r6 + 801d250: e7df b.n 801d212 <_realloc_r+0x1e> + +0801d252 <_raise_r>: + 801d252: 291f cmp r1, #31 + 801d254: b538 push {r3, r4, r5, lr} + 801d256: 4604 mov r4, r0 + 801d258: 460d mov r5, r1 + 801d25a: d904 bls.n 801d266 <_raise_r+0x14> + 801d25c: 2316 movs r3, #22 + 801d25e: 6003 str r3, [r0, #0] + 801d260: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 801d264: bd38 pop {r3, r4, r5, pc} + 801d266: 6c42 ldr r2, [r0, #68] ; 0x44 + 801d268: b112 cbz r2, 801d270 <_raise_r+0x1e> + 801d26a: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 801d26e: b94b cbnz r3, 801d284 <_raise_r+0x32> + 801d270: 4620 mov r0, r4 + 801d272: f000 f831 bl 801d2d8 <_getpid_r> + 801d276: 462a mov r2, r5 + 801d278: 4601 mov r1, r0 + 801d27a: 4620 mov r0, r4 + 801d27c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 801d280: f000 b818 b.w 801d2b4 <_kill_r> + 801d284: 2b01 cmp r3, #1 + 801d286: d00a beq.n 801d29e <_raise_r+0x4c> + 801d288: 1c59 adds r1, r3, #1 + 801d28a: d103 bne.n 801d294 <_raise_r+0x42> + 801d28c: 2316 movs r3, #22 + 801d28e: 6003 str r3, [r0, #0] + 801d290: 2001 movs r0, #1 + 801d292: e7e7 b.n 801d264 <_raise_r+0x12> + 801d294: 2400 movs r4, #0 + 801d296: f842 4025 str.w r4, [r2, r5, lsl #2] + 801d29a: 4628 mov r0, r5 + 801d29c: 4798 blx r3 + 801d29e: 2000 movs r0, #0 + 801d2a0: e7e0 b.n 801d264 <_raise_r+0x12> + ... + +0801d2a4 : + 801d2a4: 4b02 ldr r3, [pc, #8] ; (801d2b0 ) + 801d2a6: 4601 mov r1, r0 + 801d2a8: 6818 ldr r0, [r3, #0] + 801d2aa: f7ff bfd2 b.w 801d252 <_raise_r> + 801d2ae: bf00 nop + 801d2b0: 200000c4 .word 0x200000c4 + +0801d2b4 <_kill_r>: + 801d2b4: b538 push {r3, r4, r5, lr} + 801d2b6: 4d07 ldr r5, [pc, #28] ; (801d2d4 <_kill_r+0x20>) + 801d2b8: 2300 movs r3, #0 + 801d2ba: 4604 mov r4, r0 + 801d2bc: 4608 mov r0, r1 + 801d2be: 4611 mov r1, r2 + 801d2c0: 602b str r3, [r5, #0] + 801d2c2: f7e6 f819 bl 80032f8 <_kill> + 801d2c6: 1c43 adds r3, r0, #1 + 801d2c8: d102 bne.n 801d2d0 <_kill_r+0x1c> + 801d2ca: 682b ldr r3, [r5, #0] + 801d2cc: b103 cbz r3, 801d2d0 <_kill_r+0x1c> + 801d2ce: 6023 str r3, [r4, #0] + 801d2d0: bd38 pop {r3, r4, r5, pc} + 801d2d2: bf00 nop + 801d2d4: 2000d0ec .word 0x2000d0ec + +0801d2d8 <_getpid_r>: + 801d2d8: f7e6 b806 b.w 80032e8 <_getpid> + +0801d2dc <_malloc_usable_size_r>: + 801d2dc: f851 3c04 ldr.w r3, [r1, #-4] + 801d2e0: 1f18 subs r0, r3, #4 + 801d2e2: 2b00 cmp r3, #0 + 801d2e4: bfbc itt lt + 801d2e6: 580b ldrlt r3, [r1, r0] + 801d2e8: 18c0 addlt r0, r0, r3 + 801d2ea: 4770 bx lr + 801d2ec: 0000 movs r0, r0 + ... + +0801d2f0 : + 801d2f0: b51f push {r0, r1, r2, r3, r4, lr} + 801d2f2: ec53 2b10 vmov r2, r3, d0 + 801d2f6: 4826 ldr r0, [pc, #152] ; (801d390 ) + 801d2f8: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 + 801d2fc: 4281 cmp r1, r0 + 801d2fe: dc06 bgt.n 801d30e + 801d300: ed9f 1b21 vldr d1, [pc, #132] ; 801d388 + 801d304: b005 add sp, #20 + 801d306: f85d eb04 ldr.w lr, [sp], #4 + 801d30a: f000 baa9 b.w 801d860 <__kernel_cos> + 801d30e: 4821 ldr r0, [pc, #132] ; (801d394 ) + 801d310: 4281 cmp r1, r0 + 801d312: dd09 ble.n 801d328 + 801d314: ee10 0a10 vmov r0, s0 + 801d318: 4619 mov r1, r3 + 801d31a: f7e2 ffd5 bl 80002c8 <__aeabi_dsub> + 801d31e: ec41 0b10 vmov d0, r0, r1 + 801d322: b005 add sp, #20 + 801d324: f85d fb04 ldr.w pc, [sp], #4 + 801d328: 4668 mov r0, sp + 801d32a: f000 f88d bl 801d448 <__ieee754_rem_pio2> + 801d32e: f000 0003 and.w r0, r0, #3 + 801d332: 2801 cmp r0, #1 + 801d334: d00b beq.n 801d34e + 801d336: 2802 cmp r0, #2 + 801d338: d016 beq.n 801d368 + 801d33a: b9e0 cbnz r0, 801d376 + 801d33c: ed9d 1b02 vldr d1, [sp, #8] + 801d340: ed9d 0b00 vldr d0, [sp] + 801d344: f000 fa8c bl 801d860 <__kernel_cos> + 801d348: ec51 0b10 vmov r0, r1, d0 + 801d34c: e7e7 b.n 801d31e + 801d34e: ed9d 1b02 vldr d1, [sp, #8] + 801d352: ed9d 0b00 vldr d0, [sp] + 801d356: f000 fe9b bl 801e090 <__kernel_sin> + 801d35a: ec53 2b10 vmov r2, r3, d0 + 801d35e: ee10 0a10 vmov r0, s0 + 801d362: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 801d366: e7da b.n 801d31e + 801d368: ed9d 1b02 vldr d1, [sp, #8] + 801d36c: ed9d 0b00 vldr d0, [sp] + 801d370: f000 fa76 bl 801d860 <__kernel_cos> + 801d374: e7f1 b.n 801d35a + 801d376: ed9d 1b02 vldr d1, [sp, #8] + 801d37a: ed9d 0b00 vldr d0, [sp] + 801d37e: 2001 movs r0, #1 + 801d380: f000 fe86 bl 801e090 <__kernel_sin> + 801d384: e7e0 b.n 801d348 + 801d386: bf00 nop + ... + 801d390: 3fe921fb .word 0x3fe921fb + 801d394: 7fefffff .word 0x7fefffff + +0801d398 : + 801d398: b51f push {r0, r1, r2, r3, r4, lr} + 801d39a: ec53 2b10 vmov r2, r3, d0 + 801d39e: 4828 ldr r0, [pc, #160] ; (801d440 ) + 801d3a0: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 + 801d3a4: 4281 cmp r1, r0 + 801d3a6: dc07 bgt.n 801d3b8 + 801d3a8: ed9f 1b23 vldr d1, [pc, #140] ; 801d438 + 801d3ac: 2000 movs r0, #0 + 801d3ae: b005 add sp, #20 + 801d3b0: f85d eb04 ldr.w lr, [sp], #4 + 801d3b4: f000 be6c b.w 801e090 <__kernel_sin> + 801d3b8: 4822 ldr r0, [pc, #136] ; (801d444 ) + 801d3ba: 4281 cmp r1, r0 + 801d3bc: dd09 ble.n 801d3d2 + 801d3be: ee10 0a10 vmov r0, s0 + 801d3c2: 4619 mov r1, r3 + 801d3c4: f7e2 ff80 bl 80002c8 <__aeabi_dsub> + 801d3c8: ec41 0b10 vmov d0, r0, r1 + 801d3cc: b005 add sp, #20 + 801d3ce: f85d fb04 ldr.w pc, [sp], #4 + 801d3d2: 4668 mov r0, sp + 801d3d4: f000 f838 bl 801d448 <__ieee754_rem_pio2> + 801d3d8: f000 0003 and.w r0, r0, #3 + 801d3dc: 2801 cmp r0, #1 + 801d3de: d00c beq.n 801d3fa + 801d3e0: 2802 cmp r0, #2 + 801d3e2: d011 beq.n 801d408 + 801d3e4: b9f0 cbnz r0, 801d424 + 801d3e6: ed9d 1b02 vldr d1, [sp, #8] + 801d3ea: ed9d 0b00 vldr d0, [sp] + 801d3ee: 2001 movs r0, #1 + 801d3f0: f000 fe4e bl 801e090 <__kernel_sin> + 801d3f4: ec51 0b10 vmov r0, r1, d0 + 801d3f8: e7e6 b.n 801d3c8 + 801d3fa: ed9d 1b02 vldr d1, [sp, #8] + 801d3fe: ed9d 0b00 vldr d0, [sp] + 801d402: f000 fa2d bl 801d860 <__kernel_cos> + 801d406: e7f5 b.n 801d3f4 + 801d408: ed9d 1b02 vldr d1, [sp, #8] + 801d40c: ed9d 0b00 vldr d0, [sp] + 801d410: 2001 movs r0, #1 + 801d412: f000 fe3d bl 801e090 <__kernel_sin> + 801d416: ec53 2b10 vmov r2, r3, d0 + 801d41a: ee10 0a10 vmov r0, s0 + 801d41e: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 801d422: e7d1 b.n 801d3c8 + 801d424: ed9d 1b02 vldr d1, [sp, #8] + 801d428: ed9d 0b00 vldr d0, [sp] + 801d42c: f000 fa18 bl 801d860 <__kernel_cos> + 801d430: e7f1 b.n 801d416 + 801d432: bf00 nop + 801d434: f3af 8000 nop.w + ... + 801d440: 3fe921fb .word 0x3fe921fb + 801d444: 7fefffff .word 0x7fefffff + +0801d448 <__ieee754_rem_pio2>: + 801d448: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801d44c: ed2d 8b02 vpush {d8} + 801d450: ec55 4b10 vmov r4, r5, d0 + 801d454: 4bca ldr r3, [pc, #808] ; (801d780 <__ieee754_rem_pio2+0x338>) + 801d456: b08b sub sp, #44 ; 0x2c + 801d458: f025 4800 bic.w r8, r5, #2147483648 ; 0x80000000 + 801d45c: 4598 cmp r8, r3 + 801d45e: 4682 mov sl, r0 + 801d460: 9502 str r5, [sp, #8] + 801d462: dc08 bgt.n 801d476 <__ieee754_rem_pio2+0x2e> + 801d464: 2200 movs r2, #0 + 801d466: 2300 movs r3, #0 + 801d468: ed80 0b00 vstr d0, [r0] + 801d46c: e9c0 2302 strd r2, r3, [r0, #8] + 801d470: f04f 0b00 mov.w fp, #0 + 801d474: e028 b.n 801d4c8 <__ieee754_rem_pio2+0x80> + 801d476: 4bc3 ldr r3, [pc, #780] ; (801d784 <__ieee754_rem_pio2+0x33c>) + 801d478: 4598 cmp r8, r3 + 801d47a: dc78 bgt.n 801d56e <__ieee754_rem_pio2+0x126> + 801d47c: 9b02 ldr r3, [sp, #8] + 801d47e: 4ec2 ldr r6, [pc, #776] ; (801d788 <__ieee754_rem_pio2+0x340>) + 801d480: 2b00 cmp r3, #0 + 801d482: ee10 0a10 vmov r0, s0 + 801d486: a3b0 add r3, pc, #704 ; (adr r3, 801d748 <__ieee754_rem_pio2+0x300>) + 801d488: e9d3 2300 ldrd r2, r3, [r3] + 801d48c: 4629 mov r1, r5 + 801d48e: dd39 ble.n 801d504 <__ieee754_rem_pio2+0xbc> + 801d490: f7e2 ff1a bl 80002c8 <__aeabi_dsub> + 801d494: 45b0 cmp r8, r6 + 801d496: 4604 mov r4, r0 + 801d498: 460d mov r5, r1 + 801d49a: d01b beq.n 801d4d4 <__ieee754_rem_pio2+0x8c> + 801d49c: a3ac add r3, pc, #688 ; (adr r3, 801d750 <__ieee754_rem_pio2+0x308>) + 801d49e: e9d3 2300 ldrd r2, r3, [r3] + 801d4a2: f7e2 ff11 bl 80002c8 <__aeabi_dsub> + 801d4a6: 4602 mov r2, r0 + 801d4a8: 460b mov r3, r1 + 801d4aa: e9ca 2300 strd r2, r3, [sl] + 801d4ae: 4620 mov r0, r4 + 801d4b0: 4629 mov r1, r5 + 801d4b2: f7e2 ff09 bl 80002c8 <__aeabi_dsub> + 801d4b6: a3a6 add r3, pc, #664 ; (adr r3, 801d750 <__ieee754_rem_pio2+0x308>) + 801d4b8: e9d3 2300 ldrd r2, r3, [r3] + 801d4bc: f7e2 ff04 bl 80002c8 <__aeabi_dsub> + 801d4c0: e9ca 0102 strd r0, r1, [sl, #8] + 801d4c4: f04f 0b01 mov.w fp, #1 + 801d4c8: 4658 mov r0, fp + 801d4ca: b00b add sp, #44 ; 0x2c + 801d4cc: ecbd 8b02 vpop {d8} + 801d4d0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801d4d4: a3a0 add r3, pc, #640 ; (adr r3, 801d758 <__ieee754_rem_pio2+0x310>) + 801d4d6: e9d3 2300 ldrd r2, r3, [r3] + 801d4da: f7e2 fef5 bl 80002c8 <__aeabi_dsub> + 801d4de: a3a0 add r3, pc, #640 ; (adr r3, 801d760 <__ieee754_rem_pio2+0x318>) + 801d4e0: e9d3 2300 ldrd r2, r3, [r3] + 801d4e4: 4604 mov r4, r0 + 801d4e6: 460d mov r5, r1 + 801d4e8: f7e2 feee bl 80002c8 <__aeabi_dsub> + 801d4ec: 4602 mov r2, r0 + 801d4ee: 460b mov r3, r1 + 801d4f0: e9ca 2300 strd r2, r3, [sl] + 801d4f4: 4620 mov r0, r4 + 801d4f6: 4629 mov r1, r5 + 801d4f8: f7e2 fee6 bl 80002c8 <__aeabi_dsub> + 801d4fc: a398 add r3, pc, #608 ; (adr r3, 801d760 <__ieee754_rem_pio2+0x318>) + 801d4fe: e9d3 2300 ldrd r2, r3, [r3] + 801d502: e7db b.n 801d4bc <__ieee754_rem_pio2+0x74> + 801d504: f7e2 fee2 bl 80002cc <__adddf3> + 801d508: 45b0 cmp r8, r6 + 801d50a: 4604 mov r4, r0 + 801d50c: 460d mov r5, r1 + 801d50e: d016 beq.n 801d53e <__ieee754_rem_pio2+0xf6> + 801d510: a38f add r3, pc, #572 ; (adr r3, 801d750 <__ieee754_rem_pio2+0x308>) + 801d512: e9d3 2300 ldrd r2, r3, [r3] + 801d516: f7e2 fed9 bl 80002cc <__adddf3> + 801d51a: 4602 mov r2, r0 + 801d51c: 460b mov r3, r1 + 801d51e: e9ca 2300 strd r2, r3, [sl] + 801d522: 4620 mov r0, r4 + 801d524: 4629 mov r1, r5 + 801d526: f7e2 fecf bl 80002c8 <__aeabi_dsub> + 801d52a: a389 add r3, pc, #548 ; (adr r3, 801d750 <__ieee754_rem_pio2+0x308>) + 801d52c: e9d3 2300 ldrd r2, r3, [r3] + 801d530: f7e2 fecc bl 80002cc <__adddf3> + 801d534: f04f 3bff mov.w fp, #4294967295 ; 0xffffffff + 801d538: e9ca 0102 strd r0, r1, [sl, #8] + 801d53c: e7c4 b.n 801d4c8 <__ieee754_rem_pio2+0x80> + 801d53e: a386 add r3, pc, #536 ; (adr r3, 801d758 <__ieee754_rem_pio2+0x310>) + 801d540: e9d3 2300 ldrd r2, r3, [r3] + 801d544: f7e2 fec2 bl 80002cc <__adddf3> + 801d548: a385 add r3, pc, #532 ; (adr r3, 801d760 <__ieee754_rem_pio2+0x318>) + 801d54a: e9d3 2300 ldrd r2, r3, [r3] + 801d54e: 4604 mov r4, r0 + 801d550: 460d mov r5, r1 + 801d552: f7e2 febb bl 80002cc <__adddf3> + 801d556: 4602 mov r2, r0 + 801d558: 460b mov r3, r1 + 801d55a: e9ca 2300 strd r2, r3, [sl] + 801d55e: 4620 mov r0, r4 + 801d560: 4629 mov r1, r5 + 801d562: f7e2 feb1 bl 80002c8 <__aeabi_dsub> + 801d566: a37e add r3, pc, #504 ; (adr r3, 801d760 <__ieee754_rem_pio2+0x318>) + 801d568: e9d3 2300 ldrd r2, r3, [r3] + 801d56c: e7e0 b.n 801d530 <__ieee754_rem_pio2+0xe8> + 801d56e: 4b87 ldr r3, [pc, #540] ; (801d78c <__ieee754_rem_pio2+0x344>) + 801d570: 4598 cmp r8, r3 + 801d572: f300 80d9 bgt.w 801d728 <__ieee754_rem_pio2+0x2e0> + 801d576: f000 fe49 bl 801e20c + 801d57a: ec55 4b10 vmov r4, r5, d0 + 801d57e: ee10 0a10 vmov r0, s0 + 801d582: a379 add r3, pc, #484 ; (adr r3, 801d768 <__ieee754_rem_pio2+0x320>) + 801d584: e9d3 2300 ldrd r2, r3, [r3] + 801d588: 4629 mov r1, r5 + 801d58a: f7e3 f855 bl 8000638 <__aeabi_dmul> + 801d58e: 4b80 ldr r3, [pc, #512] ; (801d790 <__ieee754_rem_pio2+0x348>) + 801d590: 2200 movs r2, #0 + 801d592: f7e2 fe9b bl 80002cc <__adddf3> + 801d596: f7e3 fae9 bl 8000b6c <__aeabi_d2iz> + 801d59a: 4683 mov fp, r0 + 801d59c: f7e2 ffe2 bl 8000564 <__aeabi_i2d> + 801d5a0: 4602 mov r2, r0 + 801d5a2: 460b mov r3, r1 + 801d5a4: ec43 2b18 vmov d8, r2, r3 + 801d5a8: a367 add r3, pc, #412 ; (adr r3, 801d748 <__ieee754_rem_pio2+0x300>) + 801d5aa: e9d3 2300 ldrd r2, r3, [r3] + 801d5ae: f7e3 f843 bl 8000638 <__aeabi_dmul> + 801d5b2: 4602 mov r2, r0 + 801d5b4: 460b mov r3, r1 + 801d5b6: 4620 mov r0, r4 + 801d5b8: 4629 mov r1, r5 + 801d5ba: f7e2 fe85 bl 80002c8 <__aeabi_dsub> + 801d5be: a364 add r3, pc, #400 ; (adr r3, 801d750 <__ieee754_rem_pio2+0x308>) + 801d5c0: e9d3 2300 ldrd r2, r3, [r3] + 801d5c4: 4606 mov r6, r0 + 801d5c6: 460f mov r7, r1 + 801d5c8: ec51 0b18 vmov r0, r1, d8 + 801d5cc: f7e3 f834 bl 8000638 <__aeabi_dmul> + 801d5d0: f1bb 0f1f cmp.w fp, #31 + 801d5d4: 4604 mov r4, r0 + 801d5d6: 460d mov r5, r1 + 801d5d8: dc0d bgt.n 801d5f6 <__ieee754_rem_pio2+0x1ae> + 801d5da: 4b6e ldr r3, [pc, #440] ; (801d794 <__ieee754_rem_pio2+0x34c>) + 801d5dc: f10b 32ff add.w r2, fp, #4294967295 ; 0xffffffff + 801d5e0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801d5e4: 4543 cmp r3, r8 + 801d5e6: d006 beq.n 801d5f6 <__ieee754_rem_pio2+0x1ae> + 801d5e8: 4622 mov r2, r4 + 801d5ea: 462b mov r3, r5 + 801d5ec: 4630 mov r0, r6 + 801d5ee: 4639 mov r1, r7 + 801d5f0: f7e2 fe6a bl 80002c8 <__aeabi_dsub> + 801d5f4: e00f b.n 801d616 <__ieee754_rem_pio2+0x1ce> + 801d5f6: 462b mov r3, r5 + 801d5f8: 4622 mov r2, r4 + 801d5fa: 4630 mov r0, r6 + 801d5fc: 4639 mov r1, r7 + 801d5fe: f7e2 fe63 bl 80002c8 <__aeabi_dsub> + 801d602: ea4f 5328 mov.w r3, r8, asr #20 + 801d606: 9303 str r3, [sp, #12] + 801d608: f3c1 530a ubfx r3, r1, #20, #11 + 801d60c: ebc3 5818 rsb r8, r3, r8, lsr #20 + 801d610: f1b8 0f10 cmp.w r8, #16 + 801d614: dc02 bgt.n 801d61c <__ieee754_rem_pio2+0x1d4> + 801d616: e9ca 0100 strd r0, r1, [sl] + 801d61a: e039 b.n 801d690 <__ieee754_rem_pio2+0x248> + 801d61c: a34e add r3, pc, #312 ; (adr r3, 801d758 <__ieee754_rem_pio2+0x310>) + 801d61e: e9d3 2300 ldrd r2, r3, [r3] + 801d622: ec51 0b18 vmov r0, r1, d8 + 801d626: f7e3 f807 bl 8000638 <__aeabi_dmul> + 801d62a: 4604 mov r4, r0 + 801d62c: 460d mov r5, r1 + 801d62e: 4602 mov r2, r0 + 801d630: 460b mov r3, r1 + 801d632: 4630 mov r0, r6 + 801d634: 4639 mov r1, r7 + 801d636: f7e2 fe47 bl 80002c8 <__aeabi_dsub> + 801d63a: 4602 mov r2, r0 + 801d63c: 460b mov r3, r1 + 801d63e: 4680 mov r8, r0 + 801d640: 4689 mov r9, r1 + 801d642: 4630 mov r0, r6 + 801d644: 4639 mov r1, r7 + 801d646: f7e2 fe3f bl 80002c8 <__aeabi_dsub> + 801d64a: 4622 mov r2, r4 + 801d64c: 462b mov r3, r5 + 801d64e: f7e2 fe3b bl 80002c8 <__aeabi_dsub> + 801d652: a343 add r3, pc, #268 ; (adr r3, 801d760 <__ieee754_rem_pio2+0x318>) + 801d654: e9d3 2300 ldrd r2, r3, [r3] + 801d658: 4604 mov r4, r0 + 801d65a: 460d mov r5, r1 + 801d65c: ec51 0b18 vmov r0, r1, d8 + 801d660: f7e2 ffea bl 8000638 <__aeabi_dmul> + 801d664: 4622 mov r2, r4 + 801d666: 462b mov r3, r5 + 801d668: f7e2 fe2e bl 80002c8 <__aeabi_dsub> + 801d66c: 4602 mov r2, r0 + 801d66e: 460b mov r3, r1 + 801d670: 4604 mov r4, r0 + 801d672: 460d mov r5, r1 + 801d674: 4640 mov r0, r8 + 801d676: 4649 mov r1, r9 + 801d678: f7e2 fe26 bl 80002c8 <__aeabi_dsub> + 801d67c: 9a03 ldr r2, [sp, #12] + 801d67e: f3c1 530a ubfx r3, r1, #20, #11 + 801d682: 1ad3 subs r3, r2, r3 + 801d684: 2b31 cmp r3, #49 ; 0x31 + 801d686: dc24 bgt.n 801d6d2 <__ieee754_rem_pio2+0x28a> + 801d688: e9ca 0100 strd r0, r1, [sl] + 801d68c: 4646 mov r6, r8 + 801d68e: 464f mov r7, r9 + 801d690: e9da 8900 ldrd r8, r9, [sl] + 801d694: 4630 mov r0, r6 + 801d696: 4642 mov r2, r8 + 801d698: 464b mov r3, r9 + 801d69a: 4639 mov r1, r7 + 801d69c: f7e2 fe14 bl 80002c8 <__aeabi_dsub> + 801d6a0: 462b mov r3, r5 + 801d6a2: 4622 mov r2, r4 + 801d6a4: f7e2 fe10 bl 80002c8 <__aeabi_dsub> + 801d6a8: 9b02 ldr r3, [sp, #8] + 801d6aa: 2b00 cmp r3, #0 + 801d6ac: e9ca 0102 strd r0, r1, [sl, #8] + 801d6b0: f6bf af0a bge.w 801d4c8 <__ieee754_rem_pio2+0x80> + 801d6b4: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 + 801d6b8: f8ca 3004 str.w r3, [sl, #4] + 801d6bc: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801d6c0: f8ca 8000 str.w r8, [sl] + 801d6c4: f8ca 0008 str.w r0, [sl, #8] + 801d6c8: f8ca 300c str.w r3, [sl, #12] + 801d6cc: f1cb 0b00 rsb fp, fp, #0 + 801d6d0: e6fa b.n 801d4c8 <__ieee754_rem_pio2+0x80> + 801d6d2: a327 add r3, pc, #156 ; (adr r3, 801d770 <__ieee754_rem_pio2+0x328>) + 801d6d4: e9d3 2300 ldrd r2, r3, [r3] + 801d6d8: ec51 0b18 vmov r0, r1, d8 + 801d6dc: f7e2 ffac bl 8000638 <__aeabi_dmul> + 801d6e0: 4604 mov r4, r0 + 801d6e2: 460d mov r5, r1 + 801d6e4: 4602 mov r2, r0 + 801d6e6: 460b mov r3, r1 + 801d6e8: 4640 mov r0, r8 + 801d6ea: 4649 mov r1, r9 + 801d6ec: f7e2 fdec bl 80002c8 <__aeabi_dsub> + 801d6f0: 4602 mov r2, r0 + 801d6f2: 460b mov r3, r1 + 801d6f4: 4606 mov r6, r0 + 801d6f6: 460f mov r7, r1 + 801d6f8: 4640 mov r0, r8 + 801d6fa: 4649 mov r1, r9 + 801d6fc: f7e2 fde4 bl 80002c8 <__aeabi_dsub> + 801d700: 4622 mov r2, r4 + 801d702: 462b mov r3, r5 + 801d704: f7e2 fde0 bl 80002c8 <__aeabi_dsub> + 801d708: a31b add r3, pc, #108 ; (adr r3, 801d778 <__ieee754_rem_pio2+0x330>) + 801d70a: e9d3 2300 ldrd r2, r3, [r3] + 801d70e: 4604 mov r4, r0 + 801d710: 460d mov r5, r1 + 801d712: ec51 0b18 vmov r0, r1, d8 + 801d716: f7e2 ff8f bl 8000638 <__aeabi_dmul> + 801d71a: 4622 mov r2, r4 + 801d71c: 462b mov r3, r5 + 801d71e: f7e2 fdd3 bl 80002c8 <__aeabi_dsub> + 801d722: 4604 mov r4, r0 + 801d724: 460d mov r5, r1 + 801d726: e75f b.n 801d5e8 <__ieee754_rem_pio2+0x1a0> + 801d728: 4b1b ldr r3, [pc, #108] ; (801d798 <__ieee754_rem_pio2+0x350>) + 801d72a: 4598 cmp r8, r3 + 801d72c: dd36 ble.n 801d79c <__ieee754_rem_pio2+0x354> + 801d72e: ee10 2a10 vmov r2, s0 + 801d732: 462b mov r3, r5 + 801d734: 4620 mov r0, r4 + 801d736: 4629 mov r1, r5 + 801d738: f7e2 fdc6 bl 80002c8 <__aeabi_dsub> + 801d73c: e9ca 0102 strd r0, r1, [sl, #8] + 801d740: e9ca 0100 strd r0, r1, [sl] + 801d744: e694 b.n 801d470 <__ieee754_rem_pio2+0x28> + 801d746: bf00 nop + 801d748: 54400000 .word 0x54400000 + 801d74c: 3ff921fb .word 0x3ff921fb + 801d750: 1a626331 .word 0x1a626331 + 801d754: 3dd0b461 .word 0x3dd0b461 + 801d758: 1a600000 .word 0x1a600000 + 801d75c: 3dd0b461 .word 0x3dd0b461 + 801d760: 2e037073 .word 0x2e037073 + 801d764: 3ba3198a .word 0x3ba3198a + 801d768: 6dc9c883 .word 0x6dc9c883 + 801d76c: 3fe45f30 .word 0x3fe45f30 + 801d770: 2e000000 .word 0x2e000000 + 801d774: 3ba3198a .word 0x3ba3198a + 801d778: 252049c1 .word 0x252049c1 + 801d77c: 397b839a .word 0x397b839a + 801d780: 3fe921fb .word 0x3fe921fb + 801d784: 4002d97b .word 0x4002d97b + 801d788: 3ff921fb .word 0x3ff921fb + 801d78c: 413921fb .word 0x413921fb + 801d790: 3fe00000 .word 0x3fe00000 + 801d794: 08023b80 .word 0x08023b80 + 801d798: 7fefffff .word 0x7fefffff + 801d79c: ea4f 5428 mov.w r4, r8, asr #20 + 801d7a0: f2a4 4416 subw r4, r4, #1046 ; 0x416 + 801d7a4: ee10 0a10 vmov r0, s0 + 801d7a8: eba8 5104 sub.w r1, r8, r4, lsl #20 + 801d7ac: ee10 6a10 vmov r6, s0 + 801d7b0: 460f mov r7, r1 + 801d7b2: f7e3 f9db bl 8000b6c <__aeabi_d2iz> + 801d7b6: f7e2 fed5 bl 8000564 <__aeabi_i2d> + 801d7ba: 4602 mov r2, r0 + 801d7bc: 460b mov r3, r1 + 801d7be: 4630 mov r0, r6 + 801d7c0: 4639 mov r1, r7 + 801d7c2: e9cd 2304 strd r2, r3, [sp, #16] + 801d7c6: f7e2 fd7f bl 80002c8 <__aeabi_dsub> + 801d7ca: 4b23 ldr r3, [pc, #140] ; (801d858 <__ieee754_rem_pio2+0x410>) + 801d7cc: 2200 movs r2, #0 + 801d7ce: f7e2 ff33 bl 8000638 <__aeabi_dmul> + 801d7d2: 460f mov r7, r1 + 801d7d4: 4606 mov r6, r0 + 801d7d6: f7e3 f9c9 bl 8000b6c <__aeabi_d2iz> + 801d7da: f7e2 fec3 bl 8000564 <__aeabi_i2d> + 801d7de: 4602 mov r2, r0 + 801d7e0: 460b mov r3, r1 + 801d7e2: 4630 mov r0, r6 + 801d7e4: 4639 mov r1, r7 + 801d7e6: e9cd 2306 strd r2, r3, [sp, #24] + 801d7ea: f7e2 fd6d bl 80002c8 <__aeabi_dsub> + 801d7ee: 4b1a ldr r3, [pc, #104] ; (801d858 <__ieee754_rem_pio2+0x410>) + 801d7f0: 2200 movs r2, #0 + 801d7f2: f7e2 ff21 bl 8000638 <__aeabi_dmul> + 801d7f6: e9cd 0108 strd r0, r1, [sp, #32] + 801d7fa: ad04 add r5, sp, #16 + 801d7fc: f04f 0803 mov.w r8, #3 + 801d800: 46a9 mov r9, r5 + 801d802: 2600 movs r6, #0 + 801d804: 2700 movs r7, #0 + 801d806: 4632 mov r2, r6 + 801d808: 463b mov r3, r7 + 801d80a: e9d5 0104 ldrd r0, r1, [r5, #16] + 801d80e: 46c3 mov fp, r8 + 801d810: 3d08 subs r5, #8 + 801d812: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff + 801d816: f7e3 f977 bl 8000b08 <__aeabi_dcmpeq> + 801d81a: 2800 cmp r0, #0 + 801d81c: d1f3 bne.n 801d806 <__ieee754_rem_pio2+0x3be> + 801d81e: 4b0f ldr r3, [pc, #60] ; (801d85c <__ieee754_rem_pio2+0x414>) + 801d820: 9301 str r3, [sp, #4] + 801d822: 2302 movs r3, #2 + 801d824: 9300 str r3, [sp, #0] + 801d826: 4622 mov r2, r4 + 801d828: 465b mov r3, fp + 801d82a: 4651 mov r1, sl + 801d82c: 4648 mov r0, r9 + 801d82e: f000 f8df bl 801d9f0 <__kernel_rem_pio2> + 801d832: 9b02 ldr r3, [sp, #8] + 801d834: 2b00 cmp r3, #0 + 801d836: 4683 mov fp, r0 + 801d838: f6bf ae46 bge.w 801d4c8 <__ieee754_rem_pio2+0x80> + 801d83c: e9da 2100 ldrd r2, r1, [sl] + 801d840: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801d844: e9ca 2300 strd r2, r3, [sl] + 801d848: e9da 2102 ldrd r2, r1, [sl, #8] + 801d84c: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801d850: e9ca 2302 strd r2, r3, [sl, #8] + 801d854: e73a b.n 801d6cc <__ieee754_rem_pio2+0x284> + 801d856: bf00 nop + 801d858: 41700000 .word 0x41700000 + 801d85c: 08023c00 .word 0x08023c00 + +0801d860 <__kernel_cos>: + 801d860: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801d864: ec57 6b10 vmov r6, r7, d0 + 801d868: f027 4800 bic.w r8, r7, #2147483648 ; 0x80000000 + 801d86c: f1b8 5f79 cmp.w r8, #1044381696 ; 0x3e400000 + 801d870: ed8d 1b00 vstr d1, [sp] + 801d874: da07 bge.n 801d886 <__kernel_cos+0x26> + 801d876: ee10 0a10 vmov r0, s0 + 801d87a: 4639 mov r1, r7 + 801d87c: f7e3 f976 bl 8000b6c <__aeabi_d2iz> + 801d880: 2800 cmp r0, #0 + 801d882: f000 8088 beq.w 801d996 <__kernel_cos+0x136> + 801d886: 4632 mov r2, r6 + 801d888: 463b mov r3, r7 + 801d88a: 4630 mov r0, r6 + 801d88c: 4639 mov r1, r7 + 801d88e: f7e2 fed3 bl 8000638 <__aeabi_dmul> + 801d892: 4b51 ldr r3, [pc, #324] ; (801d9d8 <__kernel_cos+0x178>) + 801d894: 2200 movs r2, #0 + 801d896: 4604 mov r4, r0 + 801d898: 460d mov r5, r1 + 801d89a: f7e2 fecd bl 8000638 <__aeabi_dmul> + 801d89e: a340 add r3, pc, #256 ; (adr r3, 801d9a0 <__kernel_cos+0x140>) + 801d8a0: e9d3 2300 ldrd r2, r3, [r3] + 801d8a4: 4682 mov sl, r0 + 801d8a6: 468b mov fp, r1 + 801d8a8: 4620 mov r0, r4 + 801d8aa: 4629 mov r1, r5 + 801d8ac: f7e2 fec4 bl 8000638 <__aeabi_dmul> + 801d8b0: a33d add r3, pc, #244 ; (adr r3, 801d9a8 <__kernel_cos+0x148>) + 801d8b2: e9d3 2300 ldrd r2, r3, [r3] + 801d8b6: f7e2 fd09 bl 80002cc <__adddf3> + 801d8ba: 4622 mov r2, r4 + 801d8bc: 462b mov r3, r5 + 801d8be: f7e2 febb bl 8000638 <__aeabi_dmul> + 801d8c2: a33b add r3, pc, #236 ; (adr r3, 801d9b0 <__kernel_cos+0x150>) + 801d8c4: e9d3 2300 ldrd r2, r3, [r3] + 801d8c8: f7e2 fcfe bl 80002c8 <__aeabi_dsub> + 801d8cc: 4622 mov r2, r4 + 801d8ce: 462b mov r3, r5 + 801d8d0: f7e2 feb2 bl 8000638 <__aeabi_dmul> + 801d8d4: a338 add r3, pc, #224 ; (adr r3, 801d9b8 <__kernel_cos+0x158>) + 801d8d6: e9d3 2300 ldrd r2, r3, [r3] + 801d8da: f7e2 fcf7 bl 80002cc <__adddf3> + 801d8de: 4622 mov r2, r4 + 801d8e0: 462b mov r3, r5 + 801d8e2: f7e2 fea9 bl 8000638 <__aeabi_dmul> + 801d8e6: a336 add r3, pc, #216 ; (adr r3, 801d9c0 <__kernel_cos+0x160>) + 801d8e8: e9d3 2300 ldrd r2, r3, [r3] + 801d8ec: f7e2 fcec bl 80002c8 <__aeabi_dsub> + 801d8f0: 4622 mov r2, r4 + 801d8f2: 462b mov r3, r5 + 801d8f4: f7e2 fea0 bl 8000638 <__aeabi_dmul> + 801d8f8: a333 add r3, pc, #204 ; (adr r3, 801d9c8 <__kernel_cos+0x168>) + 801d8fa: e9d3 2300 ldrd r2, r3, [r3] + 801d8fe: f7e2 fce5 bl 80002cc <__adddf3> + 801d902: 4622 mov r2, r4 + 801d904: 462b mov r3, r5 + 801d906: f7e2 fe97 bl 8000638 <__aeabi_dmul> + 801d90a: 4622 mov r2, r4 + 801d90c: 462b mov r3, r5 + 801d90e: f7e2 fe93 bl 8000638 <__aeabi_dmul> + 801d912: e9dd 2300 ldrd r2, r3, [sp] + 801d916: 4604 mov r4, r0 + 801d918: 460d mov r5, r1 + 801d91a: 4630 mov r0, r6 + 801d91c: 4639 mov r1, r7 + 801d91e: f7e2 fe8b bl 8000638 <__aeabi_dmul> + 801d922: 460b mov r3, r1 + 801d924: 4602 mov r2, r0 + 801d926: 4629 mov r1, r5 + 801d928: 4620 mov r0, r4 + 801d92a: f7e2 fccd bl 80002c8 <__aeabi_dsub> + 801d92e: 4b2b ldr r3, [pc, #172] ; (801d9dc <__kernel_cos+0x17c>) + 801d930: 4598 cmp r8, r3 + 801d932: 4606 mov r6, r0 + 801d934: 460f mov r7, r1 + 801d936: dc10 bgt.n 801d95a <__kernel_cos+0xfa> + 801d938: 4602 mov r2, r0 + 801d93a: 460b mov r3, r1 + 801d93c: 4650 mov r0, sl + 801d93e: 4659 mov r1, fp + 801d940: f7e2 fcc2 bl 80002c8 <__aeabi_dsub> + 801d944: 460b mov r3, r1 + 801d946: 4926 ldr r1, [pc, #152] ; (801d9e0 <__kernel_cos+0x180>) + 801d948: 4602 mov r2, r0 + 801d94a: 2000 movs r0, #0 + 801d94c: f7e2 fcbc bl 80002c8 <__aeabi_dsub> + 801d950: ec41 0b10 vmov d0, r0, r1 + 801d954: b003 add sp, #12 + 801d956: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801d95a: 4b22 ldr r3, [pc, #136] ; (801d9e4 <__kernel_cos+0x184>) + 801d95c: 4920 ldr r1, [pc, #128] ; (801d9e0 <__kernel_cos+0x180>) + 801d95e: 4598 cmp r8, r3 + 801d960: bfcc ite gt + 801d962: 4d21 ldrgt r5, [pc, #132] ; (801d9e8 <__kernel_cos+0x188>) + 801d964: f5a8 1500 suble.w r5, r8, #2097152 ; 0x200000 + 801d968: 2400 movs r4, #0 + 801d96a: 4622 mov r2, r4 + 801d96c: 462b mov r3, r5 + 801d96e: 2000 movs r0, #0 + 801d970: f7e2 fcaa bl 80002c8 <__aeabi_dsub> + 801d974: 4622 mov r2, r4 + 801d976: 4680 mov r8, r0 + 801d978: 4689 mov r9, r1 + 801d97a: 462b mov r3, r5 + 801d97c: 4650 mov r0, sl + 801d97e: 4659 mov r1, fp + 801d980: f7e2 fca2 bl 80002c8 <__aeabi_dsub> + 801d984: 4632 mov r2, r6 + 801d986: 463b mov r3, r7 + 801d988: f7e2 fc9e bl 80002c8 <__aeabi_dsub> + 801d98c: 4602 mov r2, r0 + 801d98e: 460b mov r3, r1 + 801d990: 4640 mov r0, r8 + 801d992: 4649 mov r1, r9 + 801d994: e7da b.n 801d94c <__kernel_cos+0xec> + 801d996: ed9f 0b0e vldr d0, [pc, #56] ; 801d9d0 <__kernel_cos+0x170> + 801d99a: e7db b.n 801d954 <__kernel_cos+0xf4> + 801d99c: f3af 8000 nop.w + 801d9a0: be8838d4 .word 0xbe8838d4 + 801d9a4: bda8fae9 .word 0xbda8fae9 + 801d9a8: bdb4b1c4 .word 0xbdb4b1c4 + 801d9ac: 3e21ee9e .word 0x3e21ee9e + 801d9b0: 809c52ad .word 0x809c52ad + 801d9b4: 3e927e4f .word 0x3e927e4f + 801d9b8: 19cb1590 .word 0x19cb1590 + 801d9bc: 3efa01a0 .word 0x3efa01a0 + 801d9c0: 16c15177 .word 0x16c15177 + 801d9c4: 3f56c16c .word 0x3f56c16c + 801d9c8: 5555554c .word 0x5555554c + 801d9cc: 3fa55555 .word 0x3fa55555 + 801d9d0: 00000000 .word 0x00000000 + 801d9d4: 3ff00000 .word 0x3ff00000 + 801d9d8: 3fe00000 .word 0x3fe00000 + 801d9dc: 3fd33332 .word 0x3fd33332 + 801d9e0: 3ff00000 .word 0x3ff00000 + 801d9e4: 3fe90000 .word 0x3fe90000 + 801d9e8: 3fd20000 .word 0x3fd20000 + 801d9ec: 00000000 .word 0x00000000 + +0801d9f0 <__kernel_rem_pio2>: + 801d9f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801d9f4: ed2d 8b02 vpush {d8} + 801d9f8: f5ad 7d1b sub.w sp, sp, #620 ; 0x26c + 801d9fc: f112 0f14 cmn.w r2, #20 + 801da00: 9308 str r3, [sp, #32] + 801da02: 9101 str r1, [sp, #4] + 801da04: 4bc4 ldr r3, [pc, #784] ; (801dd18 <__kernel_rem_pio2+0x328>) + 801da06: 99a6 ldr r1, [sp, #664] ; 0x298 + 801da08: 900b str r0, [sp, #44] ; 0x2c + 801da0a: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 801da0e: 9302 str r3, [sp, #8] + 801da10: 9b08 ldr r3, [sp, #32] + 801da12: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff + 801da16: bfa8 it ge + 801da18: 1ed4 subge r4, r2, #3 + 801da1a: 9306 str r3, [sp, #24] + 801da1c: bfb2 itee lt + 801da1e: 2400 movlt r4, #0 + 801da20: 2318 movge r3, #24 + 801da22: fb94 f4f3 sdivge r4, r4, r3 + 801da26: f06f 0317 mvn.w r3, #23 + 801da2a: fb04 3303 mla r3, r4, r3, r3 + 801da2e: eb03 0a02 add.w sl, r3, r2 + 801da32: 9b02 ldr r3, [sp, #8] + 801da34: 9a06 ldr r2, [sp, #24] + 801da36: ed9f 8bb4 vldr d8, [pc, #720] ; 801dd08 <__kernel_rem_pio2+0x318> + 801da3a: eb03 0802 add.w r8, r3, r2 + 801da3e: 9ba7 ldr r3, [sp, #668] ; 0x29c + 801da40: 1aa7 subs r7, r4, r2 + 801da42: ae22 add r6, sp, #136 ; 0x88 + 801da44: eb03 0987 add.w r9, r3, r7, lsl #2 + 801da48: 2500 movs r5, #0 + 801da4a: 4545 cmp r5, r8 + 801da4c: dd13 ble.n 801da76 <__kernel_rem_pio2+0x86> + 801da4e: 9b08 ldr r3, [sp, #32] + 801da50: ed9f 8bad vldr d8, [pc, #692] ; 801dd08 <__kernel_rem_pio2+0x318> + 801da54: aa22 add r2, sp, #136 ; 0x88 + 801da56: eb02 05c3 add.w r5, r2, r3, lsl #3 + 801da5a: f50d 7be4 add.w fp, sp, #456 ; 0x1c8 + 801da5e: f04f 0800 mov.w r8, #0 + 801da62: 9b02 ldr r3, [sp, #8] + 801da64: 4598 cmp r8, r3 + 801da66: dc2f bgt.n 801dac8 <__kernel_rem_pio2+0xd8> + 801da68: ed8d 8b04 vstr d8, [sp, #16] + 801da6c: f8dd 902c ldr.w r9, [sp, #44] ; 0x2c + 801da70: 462f mov r7, r5 + 801da72: 2600 movs r6, #0 + 801da74: e01b b.n 801daae <__kernel_rem_pio2+0xbe> + 801da76: 42ef cmn r7, r5 + 801da78: d407 bmi.n 801da8a <__kernel_rem_pio2+0x9a> + 801da7a: f859 0025 ldr.w r0, [r9, r5, lsl #2] + 801da7e: f7e2 fd71 bl 8000564 <__aeabi_i2d> + 801da82: e8e6 0102 strd r0, r1, [r6], #8 + 801da86: 3501 adds r5, #1 + 801da88: e7df b.n 801da4a <__kernel_rem_pio2+0x5a> + 801da8a: ec51 0b18 vmov r0, r1, d8 + 801da8e: e7f8 b.n 801da82 <__kernel_rem_pio2+0x92> + 801da90: e9d7 2300 ldrd r2, r3, [r7] + 801da94: e8f9 0102 ldrd r0, r1, [r9], #8 + 801da98: f7e2 fdce bl 8000638 <__aeabi_dmul> + 801da9c: 4602 mov r2, r0 + 801da9e: 460b mov r3, r1 + 801daa0: e9dd 0104 ldrd r0, r1, [sp, #16] + 801daa4: f7e2 fc12 bl 80002cc <__adddf3> + 801daa8: e9cd 0104 strd r0, r1, [sp, #16] + 801daac: 3601 adds r6, #1 + 801daae: 9b06 ldr r3, [sp, #24] + 801dab0: 429e cmp r6, r3 + 801dab2: f1a7 0708 sub.w r7, r7, #8 + 801dab6: ddeb ble.n 801da90 <__kernel_rem_pio2+0xa0> + 801dab8: ed9d 7b04 vldr d7, [sp, #16] + 801dabc: f108 0801 add.w r8, r8, #1 + 801dac0: ecab 7b02 vstmia fp!, {d7} + 801dac4: 3508 adds r5, #8 + 801dac6: e7cc b.n 801da62 <__kernel_rem_pio2+0x72> + 801dac8: 9b02 ldr r3, [sp, #8] + 801daca: aa0e add r2, sp, #56 ; 0x38 + 801dacc: eb02 0383 add.w r3, r2, r3, lsl #2 + 801dad0: 930d str r3, [sp, #52] ; 0x34 + 801dad2: 9ba7 ldr r3, [sp, #668] ; 0x29c + 801dad4: eb03 0384 add.w r3, r3, r4, lsl #2 + 801dad8: 9c02 ldr r4, [sp, #8] + 801dada: 930c str r3, [sp, #48] ; 0x30 + 801dadc: 00e3 lsls r3, r4, #3 + 801dade: 930a str r3, [sp, #40] ; 0x28 + 801dae0: ab9a add r3, sp, #616 ; 0x268 + 801dae2: eb03 03c4 add.w r3, r3, r4, lsl #3 + 801dae6: e953 6728 ldrd r6, r7, [r3, #-160] ; 0xa0 + 801daea: f10d 0838 add.w r8, sp, #56 ; 0x38 + 801daee: ab72 add r3, sp, #456 ; 0x1c8 + 801daf0: eb03 05c4 add.w r5, r3, r4, lsl #3 + 801daf4: 46c3 mov fp, r8 + 801daf6: 46a1 mov r9, r4 + 801daf8: f1b9 0f00 cmp.w r9, #0 + 801dafc: f1a5 0508 sub.w r5, r5, #8 + 801db00: dc77 bgt.n 801dbf2 <__kernel_rem_pio2+0x202> + 801db02: ec47 6b10 vmov d0, r6, r7 + 801db06: 4650 mov r0, sl + 801db08: f000 fc0a bl 801e320 + 801db0c: ec57 6b10 vmov r6, r7, d0 + 801db10: 2200 movs r2, #0 + 801db12: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 + 801db16: ee10 0a10 vmov r0, s0 + 801db1a: 4639 mov r1, r7 + 801db1c: f7e2 fd8c bl 8000638 <__aeabi_dmul> + 801db20: ec41 0b10 vmov d0, r0, r1 + 801db24: f000 fb7c bl 801e220 + 801db28: 4b7c ldr r3, [pc, #496] ; (801dd1c <__kernel_rem_pio2+0x32c>) + 801db2a: ec51 0b10 vmov r0, r1, d0 + 801db2e: 2200 movs r2, #0 + 801db30: f7e2 fd82 bl 8000638 <__aeabi_dmul> + 801db34: 4602 mov r2, r0 + 801db36: 460b mov r3, r1 + 801db38: 4630 mov r0, r6 + 801db3a: 4639 mov r1, r7 + 801db3c: f7e2 fbc4 bl 80002c8 <__aeabi_dsub> + 801db40: 460f mov r7, r1 + 801db42: 4606 mov r6, r0 + 801db44: f7e3 f812 bl 8000b6c <__aeabi_d2iz> + 801db48: 9004 str r0, [sp, #16] + 801db4a: f7e2 fd0b bl 8000564 <__aeabi_i2d> + 801db4e: 4602 mov r2, r0 + 801db50: 460b mov r3, r1 + 801db52: 4630 mov r0, r6 + 801db54: 4639 mov r1, r7 + 801db56: f7e2 fbb7 bl 80002c8 <__aeabi_dsub> + 801db5a: f1ba 0f00 cmp.w sl, #0 + 801db5e: 4606 mov r6, r0 + 801db60: 460f mov r7, r1 + 801db62: dd6d ble.n 801dc40 <__kernel_rem_pio2+0x250> + 801db64: 1e62 subs r2, r4, #1 + 801db66: ab0e add r3, sp, #56 ; 0x38 + 801db68: 9d04 ldr r5, [sp, #16] + 801db6a: f853 0022 ldr.w r0, [r3, r2, lsl #2] + 801db6e: f1ca 0118 rsb r1, sl, #24 + 801db72: fa40 f301 asr.w r3, r0, r1 + 801db76: 441d add r5, r3 + 801db78: 408b lsls r3, r1 + 801db7a: 1ac0 subs r0, r0, r3 + 801db7c: ab0e add r3, sp, #56 ; 0x38 + 801db7e: 9504 str r5, [sp, #16] + 801db80: f843 0022 str.w r0, [r3, r2, lsl #2] + 801db84: f1ca 0317 rsb r3, sl, #23 + 801db88: fa40 fb03 asr.w fp, r0, r3 + 801db8c: f1bb 0f00 cmp.w fp, #0 + 801db90: dd65 ble.n 801dc5e <__kernel_rem_pio2+0x26e> + 801db92: 9b04 ldr r3, [sp, #16] + 801db94: 2200 movs r2, #0 + 801db96: 3301 adds r3, #1 + 801db98: 9304 str r3, [sp, #16] + 801db9a: 4615 mov r5, r2 + 801db9c: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 + 801dba0: 4294 cmp r4, r2 + 801dba2: f300 809c bgt.w 801dcde <__kernel_rem_pio2+0x2ee> + 801dba6: f1ba 0f00 cmp.w sl, #0 + 801dbaa: dd07 ble.n 801dbbc <__kernel_rem_pio2+0x1cc> + 801dbac: f1ba 0f01 cmp.w sl, #1 + 801dbb0: f000 80c0 beq.w 801dd34 <__kernel_rem_pio2+0x344> + 801dbb4: f1ba 0f02 cmp.w sl, #2 + 801dbb8: f000 80c6 beq.w 801dd48 <__kernel_rem_pio2+0x358> + 801dbbc: f1bb 0f02 cmp.w fp, #2 + 801dbc0: d14d bne.n 801dc5e <__kernel_rem_pio2+0x26e> + 801dbc2: 4632 mov r2, r6 + 801dbc4: 463b mov r3, r7 + 801dbc6: 4956 ldr r1, [pc, #344] ; (801dd20 <__kernel_rem_pio2+0x330>) + 801dbc8: 2000 movs r0, #0 + 801dbca: f7e2 fb7d bl 80002c8 <__aeabi_dsub> + 801dbce: 4606 mov r6, r0 + 801dbd0: 460f mov r7, r1 + 801dbd2: 2d00 cmp r5, #0 + 801dbd4: d043 beq.n 801dc5e <__kernel_rem_pio2+0x26e> + 801dbd6: 4650 mov r0, sl + 801dbd8: ed9f 0b4d vldr d0, [pc, #308] ; 801dd10 <__kernel_rem_pio2+0x320> + 801dbdc: f000 fba0 bl 801e320 + 801dbe0: 4630 mov r0, r6 + 801dbe2: 4639 mov r1, r7 + 801dbe4: ec53 2b10 vmov r2, r3, d0 + 801dbe8: f7e2 fb6e bl 80002c8 <__aeabi_dsub> + 801dbec: 4606 mov r6, r0 + 801dbee: 460f mov r7, r1 + 801dbf0: e035 b.n 801dc5e <__kernel_rem_pio2+0x26e> + 801dbf2: 4b4c ldr r3, [pc, #304] ; (801dd24 <__kernel_rem_pio2+0x334>) + 801dbf4: 2200 movs r2, #0 + 801dbf6: 4630 mov r0, r6 + 801dbf8: 4639 mov r1, r7 + 801dbfa: f7e2 fd1d bl 8000638 <__aeabi_dmul> + 801dbfe: f7e2 ffb5 bl 8000b6c <__aeabi_d2iz> + 801dc02: f7e2 fcaf bl 8000564 <__aeabi_i2d> + 801dc06: 4602 mov r2, r0 + 801dc08: 460b mov r3, r1 + 801dc0a: ec43 2b18 vmov d8, r2, r3 + 801dc0e: 4b46 ldr r3, [pc, #280] ; (801dd28 <__kernel_rem_pio2+0x338>) + 801dc10: 2200 movs r2, #0 + 801dc12: f7e2 fd11 bl 8000638 <__aeabi_dmul> + 801dc16: 4602 mov r2, r0 + 801dc18: 460b mov r3, r1 + 801dc1a: 4630 mov r0, r6 + 801dc1c: 4639 mov r1, r7 + 801dc1e: f7e2 fb53 bl 80002c8 <__aeabi_dsub> + 801dc22: f7e2 ffa3 bl 8000b6c <__aeabi_d2iz> + 801dc26: e9d5 2300 ldrd r2, r3, [r5] + 801dc2a: f84b 0b04 str.w r0, [fp], #4 + 801dc2e: ec51 0b18 vmov r0, r1, d8 + 801dc32: f7e2 fb4b bl 80002cc <__adddf3> + 801dc36: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff + 801dc3a: 4606 mov r6, r0 + 801dc3c: 460f mov r7, r1 + 801dc3e: e75b b.n 801daf8 <__kernel_rem_pio2+0x108> + 801dc40: d106 bne.n 801dc50 <__kernel_rem_pio2+0x260> + 801dc42: 1e63 subs r3, r4, #1 + 801dc44: aa0e add r2, sp, #56 ; 0x38 + 801dc46: f852 0023 ldr.w r0, [r2, r3, lsl #2] + 801dc4a: ea4f 5be0 mov.w fp, r0, asr #23 + 801dc4e: e79d b.n 801db8c <__kernel_rem_pio2+0x19c> + 801dc50: 4b36 ldr r3, [pc, #216] ; (801dd2c <__kernel_rem_pio2+0x33c>) + 801dc52: 2200 movs r2, #0 + 801dc54: f7e2 ff76 bl 8000b44 <__aeabi_dcmpge> + 801dc58: 2800 cmp r0, #0 + 801dc5a: d13d bne.n 801dcd8 <__kernel_rem_pio2+0x2e8> + 801dc5c: 4683 mov fp, r0 + 801dc5e: 2200 movs r2, #0 + 801dc60: 2300 movs r3, #0 + 801dc62: 4630 mov r0, r6 + 801dc64: 4639 mov r1, r7 + 801dc66: f7e2 ff4f bl 8000b08 <__aeabi_dcmpeq> + 801dc6a: 2800 cmp r0, #0 + 801dc6c: f000 80c0 beq.w 801ddf0 <__kernel_rem_pio2+0x400> + 801dc70: 1e65 subs r5, r4, #1 + 801dc72: 462b mov r3, r5 + 801dc74: 2200 movs r2, #0 + 801dc76: 9902 ldr r1, [sp, #8] + 801dc78: 428b cmp r3, r1 + 801dc7a: da6c bge.n 801dd56 <__kernel_rem_pio2+0x366> + 801dc7c: 2a00 cmp r2, #0 + 801dc7e: f000 8089 beq.w 801dd94 <__kernel_rem_pio2+0x3a4> + 801dc82: ab0e add r3, sp, #56 ; 0x38 + 801dc84: f1aa 0a18 sub.w sl, sl, #24 + 801dc88: f853 3025 ldr.w r3, [r3, r5, lsl #2] + 801dc8c: 2b00 cmp r3, #0 + 801dc8e: f000 80ad beq.w 801ddec <__kernel_rem_pio2+0x3fc> + 801dc92: 4650 mov r0, sl + 801dc94: ed9f 0b1e vldr d0, [pc, #120] ; 801dd10 <__kernel_rem_pio2+0x320> + 801dc98: f000 fb42 bl 801e320 + 801dc9c: ab9a add r3, sp, #616 ; 0x268 + 801dc9e: eb03 03c5 add.w r3, r3, r5, lsl #3 + 801dca2: ec57 6b10 vmov r6, r7, d0 + 801dca6: 00ec lsls r4, r5, #3 + 801dca8: f1a3 0898 sub.w r8, r3, #152 ; 0x98 + 801dcac: 46aa mov sl, r5 + 801dcae: f1ba 0f00 cmp.w sl, #0 + 801dcb2: f280 80d6 bge.w 801de62 <__kernel_rem_pio2+0x472> + 801dcb6: ed9f 8b14 vldr d8, [pc, #80] ; 801dd08 <__kernel_rem_pio2+0x318> + 801dcba: 462e mov r6, r5 + 801dcbc: 2e00 cmp r6, #0 + 801dcbe: f2c0 8104 blt.w 801deca <__kernel_rem_pio2+0x4da> + 801dcc2: ab72 add r3, sp, #456 ; 0x1c8 + 801dcc4: ed8d 8b06 vstr d8, [sp, #24] + 801dcc8: f8df a064 ldr.w sl, [pc, #100] ; 801dd30 <__kernel_rem_pio2+0x340> + 801dccc: eb03 09c6 add.w r9, r3, r6, lsl #3 + 801dcd0: f04f 0800 mov.w r8, #0 + 801dcd4: 1baf subs r7, r5, r6 + 801dcd6: e0ea b.n 801deae <__kernel_rem_pio2+0x4be> + 801dcd8: f04f 0b02 mov.w fp, #2 + 801dcdc: e759 b.n 801db92 <__kernel_rem_pio2+0x1a2> + 801dcde: f8d8 3000 ldr.w r3, [r8] + 801dce2: b955 cbnz r5, 801dcfa <__kernel_rem_pio2+0x30a> + 801dce4: b123 cbz r3, 801dcf0 <__kernel_rem_pio2+0x300> + 801dce6: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 + 801dcea: f8c8 3000 str.w r3, [r8] + 801dcee: 2301 movs r3, #1 + 801dcf0: 3201 adds r2, #1 + 801dcf2: f108 0804 add.w r8, r8, #4 + 801dcf6: 461d mov r5, r3 + 801dcf8: e752 b.n 801dba0 <__kernel_rem_pio2+0x1b0> + 801dcfa: 1acb subs r3, r1, r3 + 801dcfc: f8c8 3000 str.w r3, [r8] + 801dd00: 462b mov r3, r5 + 801dd02: e7f5 b.n 801dcf0 <__kernel_rem_pio2+0x300> + 801dd04: f3af 8000 nop.w + ... + 801dd14: 3ff00000 .word 0x3ff00000 + 801dd18: 08023d48 .word 0x08023d48 + 801dd1c: 40200000 .word 0x40200000 + 801dd20: 3ff00000 .word 0x3ff00000 + 801dd24: 3e700000 .word 0x3e700000 + 801dd28: 41700000 .word 0x41700000 + 801dd2c: 3fe00000 .word 0x3fe00000 + 801dd30: 08023d08 .word 0x08023d08 + 801dd34: 1e62 subs r2, r4, #1 + 801dd36: ab0e add r3, sp, #56 ; 0x38 + 801dd38: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801dd3c: f3c3 0316 ubfx r3, r3, #0, #23 + 801dd40: a90e add r1, sp, #56 ; 0x38 + 801dd42: f841 3022 str.w r3, [r1, r2, lsl #2] + 801dd46: e739 b.n 801dbbc <__kernel_rem_pio2+0x1cc> + 801dd48: 1e62 subs r2, r4, #1 + 801dd4a: ab0e add r3, sp, #56 ; 0x38 + 801dd4c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801dd50: f3c3 0315 ubfx r3, r3, #0, #22 + 801dd54: e7f4 b.n 801dd40 <__kernel_rem_pio2+0x350> + 801dd56: a90e add r1, sp, #56 ; 0x38 + 801dd58: f851 1023 ldr.w r1, [r1, r3, lsl #2] + 801dd5c: 3b01 subs r3, #1 + 801dd5e: 430a orrs r2, r1 + 801dd60: e789 b.n 801dc76 <__kernel_rem_pio2+0x286> + 801dd62: 3301 adds r3, #1 + 801dd64: f852 1d04 ldr.w r1, [r2, #-4]! + 801dd68: 2900 cmp r1, #0 + 801dd6a: d0fa beq.n 801dd62 <__kernel_rem_pio2+0x372> + 801dd6c: 9a0a ldr r2, [sp, #40] ; 0x28 + 801dd6e: f502 721a add.w r2, r2, #616 ; 0x268 + 801dd72: 446a add r2, sp + 801dd74: 3a98 subs r2, #152 ; 0x98 + 801dd76: 920a str r2, [sp, #40] ; 0x28 + 801dd78: 9a08 ldr r2, [sp, #32] + 801dd7a: 18e3 adds r3, r4, r3 + 801dd7c: 18a5 adds r5, r4, r2 + 801dd7e: aa22 add r2, sp, #136 ; 0x88 + 801dd80: f104 0801 add.w r8, r4, #1 + 801dd84: eb02 05c5 add.w r5, r2, r5, lsl #3 + 801dd88: 9304 str r3, [sp, #16] + 801dd8a: 9b04 ldr r3, [sp, #16] + 801dd8c: 4543 cmp r3, r8 + 801dd8e: da04 bge.n 801dd9a <__kernel_rem_pio2+0x3aa> + 801dd90: 461c mov r4, r3 + 801dd92: e6a3 b.n 801dadc <__kernel_rem_pio2+0xec> + 801dd94: 9a0d ldr r2, [sp, #52] ; 0x34 + 801dd96: 2301 movs r3, #1 + 801dd98: e7e4 b.n 801dd64 <__kernel_rem_pio2+0x374> + 801dd9a: 9b0c ldr r3, [sp, #48] ; 0x30 + 801dd9c: f853 0028 ldr.w r0, [r3, r8, lsl #2] + 801dda0: f7e2 fbe0 bl 8000564 <__aeabi_i2d> + 801dda4: e8e5 0102 strd r0, r1, [r5], #8 + 801dda8: 9b0b ldr r3, [sp, #44] ; 0x2c + 801ddaa: 46ab mov fp, r5 + 801ddac: 461c mov r4, r3 + 801ddae: f04f 0900 mov.w r9, #0 + 801ddb2: 2600 movs r6, #0 + 801ddb4: 2700 movs r7, #0 + 801ddb6: 9b06 ldr r3, [sp, #24] + 801ddb8: 4599 cmp r9, r3 + 801ddba: dd06 ble.n 801ddca <__kernel_rem_pio2+0x3da> + 801ddbc: 9b0a ldr r3, [sp, #40] ; 0x28 + 801ddbe: e8e3 6702 strd r6, r7, [r3], #8 + 801ddc2: f108 0801 add.w r8, r8, #1 + 801ddc6: 930a str r3, [sp, #40] ; 0x28 + 801ddc8: e7df b.n 801dd8a <__kernel_rem_pio2+0x39a> + 801ddca: e97b 2302 ldrd r2, r3, [fp, #-8]! + 801ddce: e8f4 0102 ldrd r0, r1, [r4], #8 + 801ddd2: f7e2 fc31 bl 8000638 <__aeabi_dmul> + 801ddd6: 4602 mov r2, r0 + 801ddd8: 460b mov r3, r1 + 801ddda: 4630 mov r0, r6 + 801dddc: 4639 mov r1, r7 + 801ddde: f7e2 fa75 bl 80002cc <__adddf3> + 801dde2: f109 0901 add.w r9, r9, #1 + 801dde6: 4606 mov r6, r0 + 801dde8: 460f mov r7, r1 + 801ddea: e7e4 b.n 801ddb6 <__kernel_rem_pio2+0x3c6> + 801ddec: 3d01 subs r5, #1 + 801ddee: e748 b.n 801dc82 <__kernel_rem_pio2+0x292> + 801ddf0: ec47 6b10 vmov d0, r6, r7 + 801ddf4: f1ca 0000 rsb r0, sl, #0 + 801ddf8: f000 fa92 bl 801e320 + 801ddfc: ec57 6b10 vmov r6, r7, d0 + 801de00: 4ba0 ldr r3, [pc, #640] ; (801e084 <__kernel_rem_pio2+0x694>) + 801de02: ee10 0a10 vmov r0, s0 + 801de06: 2200 movs r2, #0 + 801de08: 4639 mov r1, r7 + 801de0a: f7e2 fe9b bl 8000b44 <__aeabi_dcmpge> + 801de0e: b1f8 cbz r0, 801de50 <__kernel_rem_pio2+0x460> + 801de10: 4b9d ldr r3, [pc, #628] ; (801e088 <__kernel_rem_pio2+0x698>) + 801de12: 2200 movs r2, #0 + 801de14: 4630 mov r0, r6 + 801de16: 4639 mov r1, r7 + 801de18: f7e2 fc0e bl 8000638 <__aeabi_dmul> + 801de1c: f7e2 fea6 bl 8000b6c <__aeabi_d2iz> + 801de20: 4680 mov r8, r0 + 801de22: f7e2 fb9f bl 8000564 <__aeabi_i2d> + 801de26: 4b97 ldr r3, [pc, #604] ; (801e084 <__kernel_rem_pio2+0x694>) + 801de28: 2200 movs r2, #0 + 801de2a: f7e2 fc05 bl 8000638 <__aeabi_dmul> + 801de2e: 460b mov r3, r1 + 801de30: 4602 mov r2, r0 + 801de32: 4639 mov r1, r7 + 801de34: 4630 mov r0, r6 + 801de36: f7e2 fa47 bl 80002c8 <__aeabi_dsub> + 801de3a: f7e2 fe97 bl 8000b6c <__aeabi_d2iz> + 801de3e: 1c65 adds r5, r4, #1 + 801de40: ab0e add r3, sp, #56 ; 0x38 + 801de42: f10a 0a18 add.w sl, sl, #24 + 801de46: f843 0024 str.w r0, [r3, r4, lsl #2] + 801de4a: f843 8025 str.w r8, [r3, r5, lsl #2] + 801de4e: e720 b.n 801dc92 <__kernel_rem_pio2+0x2a2> + 801de50: 4630 mov r0, r6 + 801de52: 4639 mov r1, r7 + 801de54: f7e2 fe8a bl 8000b6c <__aeabi_d2iz> + 801de58: ab0e add r3, sp, #56 ; 0x38 + 801de5a: 4625 mov r5, r4 + 801de5c: f843 0024 str.w r0, [r3, r4, lsl #2] + 801de60: e717 b.n 801dc92 <__kernel_rem_pio2+0x2a2> + 801de62: ab0e add r3, sp, #56 ; 0x38 + 801de64: f853 002a ldr.w r0, [r3, sl, lsl #2] + 801de68: f7e2 fb7c bl 8000564 <__aeabi_i2d> + 801de6c: 4632 mov r2, r6 + 801de6e: 463b mov r3, r7 + 801de70: f7e2 fbe2 bl 8000638 <__aeabi_dmul> + 801de74: 4b84 ldr r3, [pc, #528] ; (801e088 <__kernel_rem_pio2+0x698>) + 801de76: e968 0102 strd r0, r1, [r8, #-8]! + 801de7a: 2200 movs r2, #0 + 801de7c: 4630 mov r0, r6 + 801de7e: 4639 mov r1, r7 + 801de80: f7e2 fbda bl 8000638 <__aeabi_dmul> + 801de84: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff + 801de88: 4606 mov r6, r0 + 801de8a: 460f mov r7, r1 + 801de8c: e70f b.n 801dcae <__kernel_rem_pio2+0x2be> + 801de8e: e8f9 2302 ldrd r2, r3, [r9], #8 + 801de92: e8fa 0102 ldrd r0, r1, [sl], #8 + 801de96: f7e2 fbcf bl 8000638 <__aeabi_dmul> + 801de9a: 4602 mov r2, r0 + 801de9c: 460b mov r3, r1 + 801de9e: e9dd 0106 ldrd r0, r1, [sp, #24] + 801dea2: f7e2 fa13 bl 80002cc <__adddf3> + 801dea6: e9cd 0106 strd r0, r1, [sp, #24] + 801deaa: f108 0801 add.w r8, r8, #1 + 801deae: 9b02 ldr r3, [sp, #8] + 801deb0: 4598 cmp r8, r3 + 801deb2: dc01 bgt.n 801deb8 <__kernel_rem_pio2+0x4c8> + 801deb4: 45b8 cmp r8, r7 + 801deb6: ddea ble.n 801de8e <__kernel_rem_pio2+0x49e> + 801deb8: ed9d 7b06 vldr d7, [sp, #24] + 801debc: ab4a add r3, sp, #296 ; 0x128 + 801debe: eb03 07c7 add.w r7, r3, r7, lsl #3 + 801dec2: ed87 7b00 vstr d7, [r7] + 801dec6: 3e01 subs r6, #1 + 801dec8: e6f8 b.n 801dcbc <__kernel_rem_pio2+0x2cc> + 801deca: 9ba6 ldr r3, [sp, #664] ; 0x298 + 801decc: 2b02 cmp r3, #2 + 801dece: dc0b bgt.n 801dee8 <__kernel_rem_pio2+0x4f8> + 801ded0: 2b00 cmp r3, #0 + 801ded2: dc35 bgt.n 801df40 <__kernel_rem_pio2+0x550> + 801ded4: d059 beq.n 801df8a <__kernel_rem_pio2+0x59a> + 801ded6: 9b04 ldr r3, [sp, #16] + 801ded8: f003 0007 and.w r0, r3, #7 + 801dedc: f50d 7d1b add.w sp, sp, #620 ; 0x26c + 801dee0: ecbd 8b02 vpop {d8} + 801dee4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801dee8: 9ba6 ldr r3, [sp, #664] ; 0x298 + 801deea: 2b03 cmp r3, #3 + 801deec: d1f3 bne.n 801ded6 <__kernel_rem_pio2+0x4e6> + 801deee: ab4a add r3, sp, #296 ; 0x128 + 801def0: 4423 add r3, r4 + 801def2: 9306 str r3, [sp, #24] + 801def4: 461c mov r4, r3 + 801def6: 469a mov sl, r3 + 801def8: 9502 str r5, [sp, #8] + 801defa: 9b02 ldr r3, [sp, #8] + 801defc: 2b00 cmp r3, #0 + 801defe: f1aa 0a08 sub.w sl, sl, #8 + 801df02: dc6b bgt.n 801dfdc <__kernel_rem_pio2+0x5ec> + 801df04: 46aa mov sl, r5 + 801df06: f1ba 0f01 cmp.w sl, #1 + 801df0a: f1a4 0408 sub.w r4, r4, #8 + 801df0e: f300 8085 bgt.w 801e01c <__kernel_rem_pio2+0x62c> + 801df12: 9c06 ldr r4, [sp, #24] + 801df14: 2000 movs r0, #0 + 801df16: 3408 adds r4, #8 + 801df18: 2100 movs r1, #0 + 801df1a: 2d01 cmp r5, #1 + 801df1c: f300 809d bgt.w 801e05a <__kernel_rem_pio2+0x66a> + 801df20: e9dd 564a ldrd r5, r6, [sp, #296] ; 0x128 + 801df24: e9dd 784c ldrd r7, r8, [sp, #304] ; 0x130 + 801df28: f1bb 0f00 cmp.w fp, #0 + 801df2c: f040 809b bne.w 801e066 <__kernel_rem_pio2+0x676> + 801df30: 9b01 ldr r3, [sp, #4] + 801df32: e9c3 5600 strd r5, r6, [r3] + 801df36: e9c3 7802 strd r7, r8, [r3, #8] + 801df3a: e9c3 0104 strd r0, r1, [r3, #16] + 801df3e: e7ca b.n 801ded6 <__kernel_rem_pio2+0x4e6> + 801df40: 3408 adds r4, #8 + 801df42: ab4a add r3, sp, #296 ; 0x128 + 801df44: 441c add r4, r3 + 801df46: 462e mov r6, r5 + 801df48: 2000 movs r0, #0 + 801df4a: 2100 movs r1, #0 + 801df4c: 2e00 cmp r6, #0 + 801df4e: da36 bge.n 801dfbe <__kernel_rem_pio2+0x5ce> + 801df50: f1bb 0f00 cmp.w fp, #0 + 801df54: d039 beq.n 801dfca <__kernel_rem_pio2+0x5da> + 801df56: 4602 mov r2, r0 + 801df58: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801df5c: 9c01 ldr r4, [sp, #4] + 801df5e: e9c4 2300 strd r2, r3, [r4] + 801df62: 4602 mov r2, r0 + 801df64: 460b mov r3, r1 + 801df66: e9dd 014a ldrd r0, r1, [sp, #296] ; 0x128 + 801df6a: f7e2 f9ad bl 80002c8 <__aeabi_dsub> + 801df6e: ae4c add r6, sp, #304 ; 0x130 + 801df70: 2401 movs r4, #1 + 801df72: 42a5 cmp r5, r4 + 801df74: da2c bge.n 801dfd0 <__kernel_rem_pio2+0x5e0> + 801df76: f1bb 0f00 cmp.w fp, #0 + 801df7a: d002 beq.n 801df82 <__kernel_rem_pio2+0x592> + 801df7c: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801df80: 4619 mov r1, r3 + 801df82: 9b01 ldr r3, [sp, #4] + 801df84: e9c3 0102 strd r0, r1, [r3, #8] + 801df88: e7a5 b.n 801ded6 <__kernel_rem_pio2+0x4e6> + 801df8a: f504 731a add.w r3, r4, #616 ; 0x268 + 801df8e: eb0d 0403 add.w r4, sp, r3 + 801df92: f5a4 749c sub.w r4, r4, #312 ; 0x138 + 801df96: 2000 movs r0, #0 + 801df98: 2100 movs r1, #0 + 801df9a: 2d00 cmp r5, #0 + 801df9c: da09 bge.n 801dfb2 <__kernel_rem_pio2+0x5c2> + 801df9e: f1bb 0f00 cmp.w fp, #0 + 801dfa2: d002 beq.n 801dfaa <__kernel_rem_pio2+0x5ba> + 801dfa4: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801dfa8: 4619 mov r1, r3 + 801dfaa: 9b01 ldr r3, [sp, #4] + 801dfac: e9c3 0100 strd r0, r1, [r3] + 801dfb0: e791 b.n 801ded6 <__kernel_rem_pio2+0x4e6> + 801dfb2: e974 2302 ldrd r2, r3, [r4, #-8]! + 801dfb6: f7e2 f989 bl 80002cc <__adddf3> + 801dfba: 3d01 subs r5, #1 + 801dfbc: e7ed b.n 801df9a <__kernel_rem_pio2+0x5aa> + 801dfbe: e974 2302 ldrd r2, r3, [r4, #-8]! + 801dfc2: f7e2 f983 bl 80002cc <__adddf3> + 801dfc6: 3e01 subs r6, #1 + 801dfc8: e7c0 b.n 801df4c <__kernel_rem_pio2+0x55c> + 801dfca: 4602 mov r2, r0 + 801dfcc: 460b mov r3, r1 + 801dfce: e7c5 b.n 801df5c <__kernel_rem_pio2+0x56c> + 801dfd0: e8f6 2302 ldrd r2, r3, [r6], #8 + 801dfd4: f7e2 f97a bl 80002cc <__adddf3> + 801dfd8: 3401 adds r4, #1 + 801dfda: e7ca b.n 801df72 <__kernel_rem_pio2+0x582> + 801dfdc: e9da 8900 ldrd r8, r9, [sl] + 801dfe0: e9da 6702 ldrd r6, r7, [sl, #8] + 801dfe4: 9b02 ldr r3, [sp, #8] + 801dfe6: 3b01 subs r3, #1 + 801dfe8: 9302 str r3, [sp, #8] + 801dfea: 4632 mov r2, r6 + 801dfec: 463b mov r3, r7 + 801dfee: 4640 mov r0, r8 + 801dff0: 4649 mov r1, r9 + 801dff2: f7e2 f96b bl 80002cc <__adddf3> + 801dff6: e9cd 0108 strd r0, r1, [sp, #32] + 801dffa: 4602 mov r2, r0 + 801dffc: 460b mov r3, r1 + 801dffe: 4640 mov r0, r8 + 801e000: 4649 mov r1, r9 + 801e002: f7e2 f961 bl 80002c8 <__aeabi_dsub> + 801e006: 4632 mov r2, r6 + 801e008: 463b mov r3, r7 + 801e00a: f7e2 f95f bl 80002cc <__adddf3> + 801e00e: ed9d 7b08 vldr d7, [sp, #32] + 801e012: e9ca 0102 strd r0, r1, [sl, #8] + 801e016: ed8a 7b00 vstr d7, [sl] + 801e01a: e76e b.n 801defa <__kernel_rem_pio2+0x50a> + 801e01c: e9d4 8900 ldrd r8, r9, [r4] + 801e020: e9d4 6702 ldrd r6, r7, [r4, #8] + 801e024: 4640 mov r0, r8 + 801e026: 4632 mov r2, r6 + 801e028: 463b mov r3, r7 + 801e02a: 4649 mov r1, r9 + 801e02c: f7e2 f94e bl 80002cc <__adddf3> + 801e030: e9cd 0102 strd r0, r1, [sp, #8] + 801e034: 4602 mov r2, r0 + 801e036: 460b mov r3, r1 + 801e038: 4640 mov r0, r8 + 801e03a: 4649 mov r1, r9 + 801e03c: f7e2 f944 bl 80002c8 <__aeabi_dsub> + 801e040: 4632 mov r2, r6 + 801e042: 463b mov r3, r7 + 801e044: f7e2 f942 bl 80002cc <__adddf3> + 801e048: ed9d 7b02 vldr d7, [sp, #8] + 801e04c: e9c4 0102 strd r0, r1, [r4, #8] + 801e050: ed84 7b00 vstr d7, [r4] + 801e054: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff + 801e058: e755 b.n 801df06 <__kernel_rem_pio2+0x516> + 801e05a: e974 2302 ldrd r2, r3, [r4, #-8]! + 801e05e: f7e2 f935 bl 80002cc <__adddf3> + 801e062: 3d01 subs r5, #1 + 801e064: e759 b.n 801df1a <__kernel_rem_pio2+0x52a> + 801e066: 9b01 ldr r3, [sp, #4] + 801e068: 9a01 ldr r2, [sp, #4] + 801e06a: 601d str r5, [r3, #0] + 801e06c: f106 4400 add.w r4, r6, #2147483648 ; 0x80000000 + 801e070: 605c str r4, [r3, #4] + 801e072: 609f str r7, [r3, #8] + 801e074: f108 4300 add.w r3, r8, #2147483648 ; 0x80000000 + 801e078: 60d3 str r3, [r2, #12] + 801e07a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 801e07e: 6110 str r0, [r2, #16] + 801e080: 6153 str r3, [r2, #20] + 801e082: e728 b.n 801ded6 <__kernel_rem_pio2+0x4e6> + 801e084: 41700000 .word 0x41700000 + 801e088: 3e700000 .word 0x3e700000 + 801e08c: 00000000 .word 0x00000000 + +0801e090 <__kernel_sin>: + 801e090: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801e094: ed2d 8b04 vpush {d8-d9} + 801e098: eeb0 8a41 vmov.f32 s16, s2 + 801e09c: eef0 8a61 vmov.f32 s17, s3 + 801e0a0: ec55 4b10 vmov r4, r5, d0 + 801e0a4: b083 sub sp, #12 + 801e0a6: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 801e0aa: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 + 801e0ae: 9001 str r0, [sp, #4] + 801e0b0: da06 bge.n 801e0c0 <__kernel_sin+0x30> + 801e0b2: ee10 0a10 vmov r0, s0 + 801e0b6: 4629 mov r1, r5 + 801e0b8: f7e2 fd58 bl 8000b6c <__aeabi_d2iz> + 801e0bc: 2800 cmp r0, #0 + 801e0be: d051 beq.n 801e164 <__kernel_sin+0xd4> + 801e0c0: 4622 mov r2, r4 + 801e0c2: 462b mov r3, r5 + 801e0c4: 4620 mov r0, r4 + 801e0c6: 4629 mov r1, r5 + 801e0c8: f7e2 fab6 bl 8000638 <__aeabi_dmul> + 801e0cc: 4682 mov sl, r0 + 801e0ce: 468b mov fp, r1 + 801e0d0: 4602 mov r2, r0 + 801e0d2: 460b mov r3, r1 + 801e0d4: 4620 mov r0, r4 + 801e0d6: 4629 mov r1, r5 + 801e0d8: f7e2 faae bl 8000638 <__aeabi_dmul> + 801e0dc: a341 add r3, pc, #260 ; (adr r3, 801e1e4 <__kernel_sin+0x154>) + 801e0de: e9d3 2300 ldrd r2, r3, [r3] + 801e0e2: 4680 mov r8, r0 + 801e0e4: 4689 mov r9, r1 + 801e0e6: 4650 mov r0, sl + 801e0e8: 4659 mov r1, fp + 801e0ea: f7e2 faa5 bl 8000638 <__aeabi_dmul> + 801e0ee: a33f add r3, pc, #252 ; (adr r3, 801e1ec <__kernel_sin+0x15c>) + 801e0f0: e9d3 2300 ldrd r2, r3, [r3] + 801e0f4: f7e2 f8e8 bl 80002c8 <__aeabi_dsub> + 801e0f8: 4652 mov r2, sl + 801e0fa: 465b mov r3, fp + 801e0fc: f7e2 fa9c bl 8000638 <__aeabi_dmul> + 801e100: a33c add r3, pc, #240 ; (adr r3, 801e1f4 <__kernel_sin+0x164>) + 801e102: e9d3 2300 ldrd r2, r3, [r3] + 801e106: f7e2 f8e1 bl 80002cc <__adddf3> + 801e10a: 4652 mov r2, sl + 801e10c: 465b mov r3, fp + 801e10e: f7e2 fa93 bl 8000638 <__aeabi_dmul> + 801e112: a33a add r3, pc, #232 ; (adr r3, 801e1fc <__kernel_sin+0x16c>) + 801e114: e9d3 2300 ldrd r2, r3, [r3] + 801e118: f7e2 f8d6 bl 80002c8 <__aeabi_dsub> + 801e11c: 4652 mov r2, sl + 801e11e: 465b mov r3, fp + 801e120: f7e2 fa8a bl 8000638 <__aeabi_dmul> + 801e124: a337 add r3, pc, #220 ; (adr r3, 801e204 <__kernel_sin+0x174>) + 801e126: e9d3 2300 ldrd r2, r3, [r3] + 801e12a: f7e2 f8cf bl 80002cc <__adddf3> + 801e12e: 9b01 ldr r3, [sp, #4] + 801e130: 4606 mov r6, r0 + 801e132: 460f mov r7, r1 + 801e134: b9eb cbnz r3, 801e172 <__kernel_sin+0xe2> + 801e136: 4602 mov r2, r0 + 801e138: 460b mov r3, r1 + 801e13a: 4650 mov r0, sl + 801e13c: 4659 mov r1, fp + 801e13e: f7e2 fa7b bl 8000638 <__aeabi_dmul> + 801e142: a325 add r3, pc, #148 ; (adr r3, 801e1d8 <__kernel_sin+0x148>) + 801e144: e9d3 2300 ldrd r2, r3, [r3] + 801e148: f7e2 f8be bl 80002c8 <__aeabi_dsub> + 801e14c: 4642 mov r2, r8 + 801e14e: 464b mov r3, r9 + 801e150: f7e2 fa72 bl 8000638 <__aeabi_dmul> + 801e154: 4602 mov r2, r0 + 801e156: 460b mov r3, r1 + 801e158: 4620 mov r0, r4 + 801e15a: 4629 mov r1, r5 + 801e15c: f7e2 f8b6 bl 80002cc <__adddf3> + 801e160: 4604 mov r4, r0 + 801e162: 460d mov r5, r1 + 801e164: ec45 4b10 vmov d0, r4, r5 + 801e168: b003 add sp, #12 + 801e16a: ecbd 8b04 vpop {d8-d9} + 801e16e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801e172: 4b1b ldr r3, [pc, #108] ; (801e1e0 <__kernel_sin+0x150>) + 801e174: ec51 0b18 vmov r0, r1, d8 + 801e178: 2200 movs r2, #0 + 801e17a: f7e2 fa5d bl 8000638 <__aeabi_dmul> + 801e17e: 4632 mov r2, r6 + 801e180: ec41 0b19 vmov d9, r0, r1 + 801e184: 463b mov r3, r7 + 801e186: 4640 mov r0, r8 + 801e188: 4649 mov r1, r9 + 801e18a: f7e2 fa55 bl 8000638 <__aeabi_dmul> + 801e18e: 4602 mov r2, r0 + 801e190: 460b mov r3, r1 + 801e192: ec51 0b19 vmov r0, r1, d9 + 801e196: f7e2 f897 bl 80002c8 <__aeabi_dsub> + 801e19a: 4652 mov r2, sl + 801e19c: 465b mov r3, fp + 801e19e: f7e2 fa4b bl 8000638 <__aeabi_dmul> + 801e1a2: ec53 2b18 vmov r2, r3, d8 + 801e1a6: f7e2 f88f bl 80002c8 <__aeabi_dsub> + 801e1aa: a30b add r3, pc, #44 ; (adr r3, 801e1d8 <__kernel_sin+0x148>) + 801e1ac: e9d3 2300 ldrd r2, r3, [r3] + 801e1b0: 4606 mov r6, r0 + 801e1b2: 460f mov r7, r1 + 801e1b4: 4640 mov r0, r8 + 801e1b6: 4649 mov r1, r9 + 801e1b8: f7e2 fa3e bl 8000638 <__aeabi_dmul> + 801e1bc: 4602 mov r2, r0 + 801e1be: 460b mov r3, r1 + 801e1c0: 4630 mov r0, r6 + 801e1c2: 4639 mov r1, r7 + 801e1c4: f7e2 f882 bl 80002cc <__adddf3> + 801e1c8: 4602 mov r2, r0 + 801e1ca: 460b mov r3, r1 + 801e1cc: 4620 mov r0, r4 + 801e1ce: 4629 mov r1, r5 + 801e1d0: f7e2 f87a bl 80002c8 <__aeabi_dsub> + 801e1d4: e7c4 b.n 801e160 <__kernel_sin+0xd0> + 801e1d6: bf00 nop + 801e1d8: 55555549 .word 0x55555549 + 801e1dc: 3fc55555 .word 0x3fc55555 + 801e1e0: 3fe00000 .word 0x3fe00000 + 801e1e4: 5acfd57c .word 0x5acfd57c + 801e1e8: 3de5d93a .word 0x3de5d93a + 801e1ec: 8a2b9ceb .word 0x8a2b9ceb + 801e1f0: 3e5ae5e6 .word 0x3e5ae5e6 + 801e1f4: 57b1fe7d .word 0x57b1fe7d + 801e1f8: 3ec71de3 .word 0x3ec71de3 + 801e1fc: 19c161d5 .word 0x19c161d5 + 801e200: 3f2a01a0 .word 0x3f2a01a0 + 801e204: 1110f8a6 .word 0x1110f8a6 + 801e208: 3f811111 .word 0x3f811111 + +0801e20c : + 801e20c: ec51 0b10 vmov r0, r1, d0 + 801e210: ee10 2a10 vmov r2, s0 + 801e214: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 801e218: ec43 2b10 vmov d0, r2, r3 + 801e21c: 4770 bx lr + ... + +0801e220 : + 801e220: ec51 0b10 vmov r0, r1, d0 + 801e224: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801e228: f3c1 570a ubfx r7, r1, #20, #11 + 801e22c: f2a7 36ff subw r6, r7, #1023 ; 0x3ff + 801e230: 2e13 cmp r6, #19 + 801e232: ee10 5a10 vmov r5, s0 + 801e236: ee10 8a10 vmov r8, s0 + 801e23a: 460c mov r4, r1 + 801e23c: dc32 bgt.n 801e2a4 + 801e23e: 2e00 cmp r6, #0 + 801e240: da14 bge.n 801e26c + 801e242: a333 add r3, pc, #204 ; (adr r3, 801e310 ) + 801e244: e9d3 2300 ldrd r2, r3, [r3] + 801e248: f7e2 f840 bl 80002cc <__adddf3> + 801e24c: 2200 movs r2, #0 + 801e24e: 2300 movs r3, #0 + 801e250: f7e2 fc82 bl 8000b58 <__aeabi_dcmpgt> + 801e254: b138 cbz r0, 801e266 + 801e256: 2c00 cmp r4, #0 + 801e258: da57 bge.n 801e30a + 801e25a: f024 4300 bic.w r3, r4, #2147483648 ; 0x80000000 + 801e25e: 431d orrs r5, r3 + 801e260: d001 beq.n 801e266 + 801e262: 4c2d ldr r4, [pc, #180] ; (801e318 ) + 801e264: 2500 movs r5, #0 + 801e266: 4621 mov r1, r4 + 801e268: 4628 mov r0, r5 + 801e26a: e025 b.n 801e2b8 + 801e26c: 4f2b ldr r7, [pc, #172] ; (801e31c ) + 801e26e: 4137 asrs r7, r6 + 801e270: ea01 0307 and.w r3, r1, r7 + 801e274: 4303 orrs r3, r0 + 801e276: d01f beq.n 801e2b8 + 801e278: a325 add r3, pc, #148 ; (adr r3, 801e310 ) + 801e27a: e9d3 2300 ldrd r2, r3, [r3] + 801e27e: f7e2 f825 bl 80002cc <__adddf3> + 801e282: 2200 movs r2, #0 + 801e284: 2300 movs r3, #0 + 801e286: f7e2 fc67 bl 8000b58 <__aeabi_dcmpgt> + 801e28a: 2800 cmp r0, #0 + 801e28c: d0eb beq.n 801e266 + 801e28e: 2c00 cmp r4, #0 + 801e290: bfbe ittt lt + 801e292: f44f 1380 movlt.w r3, #1048576 ; 0x100000 + 801e296: fa43 f606 asrlt.w r6, r3, r6 + 801e29a: 19a4 addlt r4, r4, r6 + 801e29c: ea24 0407 bic.w r4, r4, r7 + 801e2a0: 2500 movs r5, #0 + 801e2a2: e7e0 b.n 801e266 + 801e2a4: 2e33 cmp r6, #51 ; 0x33 + 801e2a6: dd0b ble.n 801e2c0 + 801e2a8: f5b6 6f80 cmp.w r6, #1024 ; 0x400 + 801e2ac: d104 bne.n 801e2b8 + 801e2ae: ee10 2a10 vmov r2, s0 + 801e2b2: 460b mov r3, r1 + 801e2b4: f7e2 f80a bl 80002cc <__adddf3> + 801e2b8: ec41 0b10 vmov d0, r0, r1 + 801e2bc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801e2c0: f2a7 4713 subw r7, r7, #1043 ; 0x413 + 801e2c4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 801e2c8: fa23 f707 lsr.w r7, r3, r7 + 801e2cc: 4207 tst r7, r0 + 801e2ce: d0f3 beq.n 801e2b8 + 801e2d0: a30f add r3, pc, #60 ; (adr r3, 801e310 ) + 801e2d2: e9d3 2300 ldrd r2, r3, [r3] + 801e2d6: f7e1 fff9 bl 80002cc <__adddf3> + 801e2da: 2200 movs r2, #0 + 801e2dc: 2300 movs r3, #0 + 801e2de: f7e2 fc3b bl 8000b58 <__aeabi_dcmpgt> + 801e2e2: 2800 cmp r0, #0 + 801e2e4: d0bf beq.n 801e266 + 801e2e6: 2c00 cmp r4, #0 + 801e2e8: da02 bge.n 801e2f0 + 801e2ea: 2e14 cmp r6, #20 + 801e2ec: d103 bne.n 801e2f6 + 801e2ee: 3401 adds r4, #1 + 801e2f0: ea25 0507 bic.w r5, r5, r7 + 801e2f4: e7b7 b.n 801e266 + 801e2f6: 2301 movs r3, #1 + 801e2f8: f1c6 0634 rsb r6, r6, #52 ; 0x34 + 801e2fc: fa03 f606 lsl.w r6, r3, r6 + 801e300: 4435 add r5, r6 + 801e302: 4545 cmp r5, r8 + 801e304: bf38 it cc + 801e306: 18e4 addcc r4, r4, r3 + 801e308: e7f2 b.n 801e2f0 + 801e30a: 2500 movs r5, #0 + 801e30c: 462c mov r4, r5 + 801e30e: e7aa b.n 801e266 + 801e310: 8800759c .word 0x8800759c + 801e314: 7e37e43c .word 0x7e37e43c + 801e318: bff00000 .word 0xbff00000 + 801e31c: 000fffff .word 0x000fffff + +0801e320 : + 801e320: b570 push {r4, r5, r6, lr} + 801e322: ec55 4b10 vmov r4, r5, d0 + 801e326: f3c5 520a ubfx r2, r5, #20, #11 + 801e32a: 4606 mov r6, r0 + 801e32c: 462b mov r3, r5 + 801e32e: b99a cbnz r2, 801e358 + 801e330: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 801e334: 4323 orrs r3, r4 + 801e336: d036 beq.n 801e3a6 + 801e338: 4b39 ldr r3, [pc, #228] ; (801e420 ) + 801e33a: 4629 mov r1, r5 + 801e33c: ee10 0a10 vmov r0, s0 + 801e340: 2200 movs r2, #0 + 801e342: f7e2 f979 bl 8000638 <__aeabi_dmul> + 801e346: 4b37 ldr r3, [pc, #220] ; (801e424 ) + 801e348: 429e cmp r6, r3 + 801e34a: 4604 mov r4, r0 + 801e34c: 460d mov r5, r1 + 801e34e: da10 bge.n 801e372 + 801e350: a32b add r3, pc, #172 ; (adr r3, 801e400 ) + 801e352: e9d3 2300 ldrd r2, r3, [r3] + 801e356: e03a b.n 801e3ce + 801e358: f240 71ff movw r1, #2047 ; 0x7ff + 801e35c: 428a cmp r2, r1 + 801e35e: d10c bne.n 801e37a + 801e360: ee10 2a10 vmov r2, s0 + 801e364: 4620 mov r0, r4 + 801e366: 4629 mov r1, r5 + 801e368: f7e1 ffb0 bl 80002cc <__adddf3> + 801e36c: 4604 mov r4, r0 + 801e36e: 460d mov r5, r1 + 801e370: e019 b.n 801e3a6 + 801e372: f3c1 520a ubfx r2, r1, #20, #11 + 801e376: 460b mov r3, r1 + 801e378: 3a36 subs r2, #54 ; 0x36 + 801e37a: 4432 add r2, r6 + 801e37c: f240 71fe movw r1, #2046 ; 0x7fe + 801e380: 428a cmp r2, r1 + 801e382: dd08 ble.n 801e396 + 801e384: 2d00 cmp r5, #0 + 801e386: a120 add r1, pc, #128 ; (adr r1, 801e408 ) + 801e388: e9d1 0100 ldrd r0, r1, [r1] + 801e38c: da1c bge.n 801e3c8 + 801e38e: a120 add r1, pc, #128 ; (adr r1, 801e410 ) + 801e390: e9d1 0100 ldrd r0, r1, [r1] + 801e394: e018 b.n 801e3c8 + 801e396: 2a00 cmp r2, #0 + 801e398: dd08 ble.n 801e3ac + 801e39a: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 801e39e: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 801e3a2: ea43 5502 orr.w r5, r3, r2, lsl #20 + 801e3a6: ec45 4b10 vmov d0, r4, r5 + 801e3aa: bd70 pop {r4, r5, r6, pc} + 801e3ac: f112 0f35 cmn.w r2, #53 ; 0x35 + 801e3b0: da19 bge.n 801e3e6 + 801e3b2: f24c 3350 movw r3, #50000 ; 0xc350 + 801e3b6: 429e cmp r6, r3 + 801e3b8: f005 4300 and.w r3, r5, #2147483648 ; 0x80000000 + 801e3bc: dd0a ble.n 801e3d4 + 801e3be: a112 add r1, pc, #72 ; (adr r1, 801e408 ) + 801e3c0: e9d1 0100 ldrd r0, r1, [r1] + 801e3c4: 2b00 cmp r3, #0 + 801e3c6: d1e2 bne.n 801e38e + 801e3c8: a30f add r3, pc, #60 ; (adr r3, 801e408 ) + 801e3ca: e9d3 2300 ldrd r2, r3, [r3] + 801e3ce: f7e2 f933 bl 8000638 <__aeabi_dmul> + 801e3d2: e7cb b.n 801e36c + 801e3d4: a10a add r1, pc, #40 ; (adr r1, 801e400 ) + 801e3d6: e9d1 0100 ldrd r0, r1, [r1] + 801e3da: 2b00 cmp r3, #0 + 801e3dc: d0b8 beq.n 801e350 + 801e3de: a10e add r1, pc, #56 ; (adr r1, 801e418 ) + 801e3e0: e9d1 0100 ldrd r0, r1, [r1] + 801e3e4: e7b4 b.n 801e350 + 801e3e6: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 801e3ea: 3236 adds r2, #54 ; 0x36 + 801e3ec: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 801e3f0: ea43 5102 orr.w r1, r3, r2, lsl #20 + 801e3f4: 4620 mov r0, r4 + 801e3f6: 4b0c ldr r3, [pc, #48] ; (801e428 ) + 801e3f8: 2200 movs r2, #0 + 801e3fa: e7e8 b.n 801e3ce + 801e3fc: f3af 8000 nop.w + 801e400: c2f8f359 .word 0xc2f8f359 + 801e404: 01a56e1f .word 0x01a56e1f + 801e408: 8800759c .word 0x8800759c + 801e40c: 7e37e43c .word 0x7e37e43c + 801e410: 8800759c .word 0x8800759c + 801e414: fe37e43c .word 0xfe37e43c + 801e418: c2f8f359 .word 0xc2f8f359 + 801e41c: 81a56e1f .word 0x81a56e1f + 801e420: 43500000 .word 0x43500000 + 801e424: ffff3cb0 .word 0xffff3cb0 + 801e428: 3c900000 .word 0x3c900000 + +0801e42c <_init>: + 801e42c: b5f8 push {r3, r4, r5, r6, r7, lr} + 801e42e: bf00 nop + 801e430: bcf8 pop {r3, r4, r5, r6, r7} + 801e432: bc08 pop {r3} + 801e434: 469e mov lr, r3 + 801e436: 4770 bx lr + +0801e438 <_fini>: + 801e438: b5f8 push {r3, r4, r5, r6, r7, lr} + 801e43a: bf00 nop + 801e43c: bcf8 pop {r3, r4, r5, r6, r7} + 801e43e: bc08 pop {r3} + 801e440: 469e mov lr, r3 + 801e442: 4770 bx lr diff --git a/project/Debug/NTP.map b/project/Debug/NTP.map new file mode 100644 index 0000000..fde16dd --- /dev/null +++ b/project/Debug/NTP.map @@ -0,0 +1,35066 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-atoi.o) + ./Middlewares/Third_Party/LwIP/src/api/netdb.o (atoi) +/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-ctype_.o) + ./Middlewares/Third_Party/LwIP/src/core/dns.o (_ctype_) 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0x0000000000050000 xrw +FLASH 0x0000000008000000 0x0000000000100000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crti.o +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/NTP.o +LOAD ./Core/Src/RTC.o +LOAD ./Core/Src/Time.o +LOAD ./Core/Src/app_main.o +LOAD ./Core/Src/clock.o +LOAD ./Core/Src/debug.o +LOAD ./Core/Src/ds3231_for_stm32_hal.o +LOAD ./Core/Src/freertos.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/stm32f7xx_hal_msp.o +LOAD ./Core/Src/stm32f7xx_hal_timebase_tim.o +LOAD ./Core/Src/stm32f7xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f7xx.o +LOAD ./Core/Startup/startup_stm32f746nghx.o +LOAD ./Drivers/BSP/Components/lan8742/lan8742.o +LOAD ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o +LOAD ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o +LOAD ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o +LOAD ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o +LOAD ./LWIP/App/lwip.o +LOAD ./LWIP/Target/ethernetif.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/list.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/queue.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/timers.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o +LOAD ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/api_lib.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/api_msg.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/err.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/if_api.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netbuf.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netdb.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netifapi.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/sockets.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/tcpip.o +LOAD ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/def.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/dns.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/init.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ip.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/mem.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/memp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/netif.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/pbuf.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/raw.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/stats.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/sys.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/timeouts.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/udp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/slipif.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/zepif.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o +LOAD ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o +START GROUP +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x0000000020050000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0x1c8 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0x1c8 ./Core/Startup/startup_stm32f746nghx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080001c8 . = ALIGN (0x4) + +.text 0x00000000080001d0 0x1e274 + 0x00000000080001d0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080001d0 0x40 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .text 0x0000000008000210 0x10 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-strlen.o) + 0x0000000008000210 strlen + .text 0x0000000008000220 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0x00000000080005dc __floatdidf + 0x00000000080005dc __aeabi_l2d + .text 0x0000000008000638 0x424 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o) + 0x0000000008000638 __aeabi_dmul + 0x0000000008000638 __muldf3 + 0x000000000800088c __aeabi_ddiv + 0x000000000800088c __divdf3 + .text 0x0000000008000a5c 0x110 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_cmpdf2.o) + 0x0000000008000a5c __gtdf2 + 0x0000000008000a5c __gedf2 + 0x0000000008000a64 __ltdf2 + 0x0000000008000a64 __ledf2 + 0x0000000008000a6c __cmpdf2 + 0x0000000008000a6c __eqdf2 + 0x0000000008000a6c __nedf2 + 0x0000000008000ae8 __aeabi_cdrcmple + 0x0000000008000af8 __aeabi_cdcmple + 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./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x0000000008010e0c pbuf_copy_partial + .text.pbuf_skip_const + 0x0000000008010ef0 0x52 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + .text.pbuf_skip + 0x0000000008010f42 0x26 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x0000000008010f42 pbuf_skip + .text.pbuf_take + 0x0000000008010f68 0x124 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x0000000008010f68 pbuf_take + .text.pbuf_take_at + 0x000000000801108c 0xd4 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x000000000801108c pbuf_take_at + .text.pbuf_clone + 0x0000000008011160 0x64 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x0000000008011160 pbuf_clone + .text.pbuf_try_get_at + 0x00000000080111c4 0x44 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x00000000080111c4 pbuf_try_get_at + .text.pbuf_put_at + 0x0000000008011208 0x44 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x0000000008011208 pbuf_put_at + .text.tcp_init + 0x000000000801124c 0x24 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000000801124c tcp_init + .text.tcp_free + 0x0000000008011270 0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008011270 tcp_free + .text.tcp_free_listen + 0x00000000080112a8 0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_tmr 0x00000000080112e0 0x2c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080112e0 tcp_tmr + .text.tcp_remove_listener + 0x000000000801130c 0x54 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_listen_closed + 0x0000000008011360 0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_close_shutdown + 0x00000000080113d4 0x1c4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_close_shutdown_fin + 0x0000000008011598 0xd4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_close + 0x000000000801166c 0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000000801166c tcp_close + .text.tcp_abandon + 0x00000000080116c4 0x17c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080116c4 tcp_abandon + .text.tcp_abort + 0x0000000008011840 0x18 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008011840 tcp_abort + .text.tcp_update_rcv_ann_wnd + 0x0000000008011858 0xb4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008011858 tcp_update_rcv_ann_wnd + .text.tcp_recved + 0x000000000801190c 0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000000801190c tcp_recved + .text.tcp_slowtmr + 0x00000000080119ac 0x680 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080119ac tcp_slowtmr + .text.tcp_fasttmr + 0x000000000801202c 0xc8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000000801202c tcp_fasttmr + .text.tcp_process_refused_data + 0x00000000080120f4 0xf8 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080120f4 tcp_process_refused_data + .text.tcp_segs_free + 0x00000000080121ec 0x2a ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080121ec tcp_segs_free + .text.tcp_seg_free + 0x0000000008012216 0x30 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008012216 tcp_seg_free + *fill* 0x0000000008012246 0x2 + .text.tcp_seg_copy + 0x0000000008012248 0x58 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008012248 tcp_seg_copy + .text.tcp_recv_null + 0x00000000080122a0 0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080122a0 tcp_recv_null + .text.tcp_kill_prio + 0x000000000801230c 0x9c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_kill_state + 0x00000000080123a8 0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_kill_timewait + 0x000000000801243c 0x60 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_handle_closepend + 0x000000000801249c 0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_alloc + 0x00000000080124e8 0x108 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080124e8 tcp_alloc + .text.tcp_pcb_purge + 0x00000000080125f0 0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080125f0 tcp_pcb_purge + .text.tcp_pcb_remove + 0x0000000008012690 0x128 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008012690 tcp_pcb_remove + .text.tcp_next_iss + 0x00000000080127b8 0x4c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080127b8 tcp_next_iss + .text.tcp_eff_send_mss_netif + 0x0000000008012804 0x74 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008012804 tcp_eff_send_mss_netif + .text.tcp_netif_ip_addr_changed_pcblist + 0x0000000008012878 0x64 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .text.tcp_netif_ip_addr_changed + 0x00000000080128dc 0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x00000000080128dc tcp_netif_ip_addr_changed + .text.tcp_free_ooseq + 0x0000000008012958 0x28 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x0000000008012958 tcp_free_ooseq + .text.tcp_input + 0x0000000008012980 0x818 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + 0x0000000008012980 tcp_input + .text.tcp_input_delayed_close + 0x0000000008013198 0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_listen_input + 0x0000000008013218 0x1fc ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_timewait_input + 0x0000000008013414 0xf4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_process + 0x0000000008013508 0x7e0 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_oos_insert_segment + 0x0000000008013ce8 0x110 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_free_acked_segments + 0x0000000008013df8 0xf8 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_receive + 0x0000000008013ef0 0xf30 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_get_next_optbyte + 0x0000000008014e20 0x6c ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_parseopt + 0x0000000008014e8c 0xec ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .text.tcp_trigger_input_pcb_close + 0x0000000008014f78 0x20 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + 0x0000000008014f78 tcp_trigger_input_pcb_close + .text.tcp_route + 0x0000000008014f98 0x38 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_create_segment + 0x0000000008014fd0 0x13c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_split_unsent_seg + 0x000000000801510c 0x290 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x000000000801510c tcp_split_unsent_seg + .text.tcp_send_fin + 0x000000000801539c 0xa0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x000000000801539c tcp_send_fin + .text.tcp_enqueue_flags + 0x000000000801543c 0x1dc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x000000000801543c tcp_enqueue_flags + .text.tcp_output + 0x0000000008015618 0x3e8 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015618 tcp_output + .text.tcp_output_segment_busy + 0x0000000008015a00 0x40 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_output_segment + 0x0000000008015a40 0x1bc ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_rexmit_rto_prepare + 0x0000000008015bfc 0xe0 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015bfc tcp_rexmit_rto_prepare + .text.tcp_rexmit_rto_commit + 0x0000000008015cdc 0x50 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015cdc tcp_rexmit_rto_commit + .text.tcp_rexmit_rto + 0x0000000008015d2c 0x44 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015d2c tcp_rexmit_rto + .text.tcp_rexmit + 0x0000000008015d70 0xd8 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015d70 tcp_rexmit + .text.tcp_rexmit_fast + 0x0000000008015e48 0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008015e48 tcp_rexmit_fast + .text.tcp_output_alloc_header_common + 0x0000000008015f0c 0xe4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_output_alloc_header + 0x0000000008015ff0 0x7c ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_output_fill_options + 0x000000000801606c 0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_output_control_segment + 0x00000000080160ec 0x94 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + .text.tcp_rst 0x0000000008016180 0xa4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008016180 tcp_rst + .text.tcp_send_empty_ack + 0x0000000008016224 0xc4 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008016224 tcp_send_empty_ack + .text.tcp_keepalive + 0x00000000080162e8 0x80 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x00000000080162e8 tcp_keepalive + .text.tcp_zero_window_probe + 0x0000000008016368 0x154 ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o + 0x0000000008016368 tcp_zero_window_probe + .text.tcpip_tcp_timer + 0x00000000080164bc 0x48 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .text.tcp_timer_needed + 0x0000000008016504 0x40 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + 0x0000000008016504 tcp_timer_needed + .text.sys_timeout_abs + 0x0000000008016544 0xdc ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .text.lwip_cyclic_timer + 0x0000000008016620 0x64 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .text.sys_timeouts_init + 0x0000000008016684 0x44 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + 0x0000000008016684 sys_timeouts_init + .text.sys_timeout + 0x00000000080166c8 0x4c ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + 0x00000000080166c8 sys_timeout + .text.sys_check_timeouts + 0x0000000008016714 0x74 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + 0x0000000008016714 sys_check_timeouts + .text.sys_timeouts_sleeptime + 0x0000000008016788 0x70 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + 0x0000000008016788 sys_timeouts_sleeptime + .text.udp_init + 0x00000000080167f8 0x24 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x00000000080167f8 udp_init + .text.udp_new_port + 0x000000000801681c 0x70 ./Middlewares/Third_Party/LwIP/src/core/udp.o + .text.udp_input_local_match + 0x000000000801688c 0xc8 ./Middlewares/Third_Party/LwIP/src/core/udp.o + .text.udp_input + 0x0000000008016954 0x228 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016954 udp_input + .text.udp_send + 0x0000000008016b7c 0x68 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016b7c udp_send + .text.udp_sendto + 0x0000000008016be4 0xb8 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016be4 udp_sendto + .text.udp_sendto_if + 0x0000000008016c9c 0xe8 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016c9c udp_sendto_if + .text.udp_sendto_if_src + 0x0000000008016d84 0x1cc ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016d84 udp_sendto_if_src + .text.udp_bind + 0x0000000008016f50 0x110 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008016f50 udp_bind + .text.udp_connect + 0x0000000008017060 0xdc ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008017060 udp_connect + .text.udp_disconnect + 0x000000000801713c 0x50 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x000000000801713c udp_disconnect + .text.udp_recv + 0x000000000801718c 0x40 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x000000000801718c udp_recv + .text.udp_remove + 0x00000000080171cc 0x84 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x00000000080171cc udp_remove + .text.udp_new 0x0000000008017250 0x2e ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008017250 udp_new + .text.udp_new_ip_type + 0x000000000801727e 0x1a ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x000000000801727e udp_new_ip_type + .text.udp_netif_ip_addr_changed + 0x0000000008017298 0x60 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x0000000008017298 udp_netif_ip_addr_changed + .text.dhcp_inc_pcb_refcount + 0x00000000080172f8 0xa4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_dec_pcb_refcount + 0x000000000801739c 0x54 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_handle_nak + 0x00000000080173f0 0x34 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_check + 0x0000000008017424 0x68 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_handle_offer + 0x000000000801748c 0x4c ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_select + 0x00000000080174d8 0x1f8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_coarse_tmr + 0x00000000080176d0 0xa8 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x00000000080176d0 dhcp_coarse_tmr + .text.dhcp_fine_tmr + 0x0000000008017778 0x64 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x0000000008017778 dhcp_fine_tmr + .text.dhcp_timeout + 0x00000000080177dc 0x92 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_t1_timeout + 0x000000000801786e 0x5e ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_t2_timeout + 0x00000000080178cc 0x66 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + *fill* 0x0000000008017932 0x2 + .text.dhcp_handle_ack + 0x0000000008017934 0x100 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_start + 0x0000000008017a34 0xfc ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x0000000008017a34 dhcp_start + .text.dhcp_network_changed + 0x0000000008017b30 0x78 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x0000000008017b30 dhcp_network_changed + .text.dhcp_arp_reply + 0x0000000008017ba8 0x58 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x0000000008017ba8 dhcp_arp_reply + .text.dhcp_decline + 0x0000000008017c00 0xec ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_discover + 0x0000000008017cec 0x144 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_bind + 0x0000000008017e30 0x1b4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_renew + 0x0000000008017fe4 0x138 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x0000000008017fe4 dhcp_renew + .text.dhcp_rebind + 0x000000000801811c 0x138 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_reboot + 0x0000000008018254 0x16c ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_release_and_stop + 0x00000000080183c0 0x134 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x00000000080183c0 dhcp_release_and_stop + .text.dhcp_set_state + 0x00000000080184f4 0x34 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_option + 0x0000000008018528 0x68 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_option_byte + 0x0000000008018590 0x4c ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_option_short + 0x00000000080185dc 0x64 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_option_long + 0x0000000008018640 0x88 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_parse_reply + 0x00000000080186c8 0x608 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .text.dhcp_recv + 0x0000000008018cd0 0x19c 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/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o) + .rodata.init_jk + 0x0000000008023d48 0x10 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(lib_a-k_rem_pio2.o) + 0x0000000008023d58 . = ALIGN (0x4) + +.ARM.extab 0x0000000008023d58 0x0 + 0x0000000008023d58 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000008023d58 . = ALIGN (0x4) + +.ARM 0x0000000008023d58 0x8 + 0x0000000008023d58 . = ALIGN (0x4) + 0x0000000008023d58 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0000000008023d58 0x8 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./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x0000000020000098 uwTickFreq + *fill* 0x0000000020000099 0x3 + .data.LAN8742_IOCtx + 0x000000002000009c 0x14 ./LWIP/Target/ethernetif.o + 0x000000002000009c LAN8742_IOCtx + .data.uxCriticalNesting + 0x00000000200000b0 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .data.tcp_port + 0x00000000200000b4 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + *fill* 0x00000000200000b6 0x2 + .data.iss.0 0x00000000200000b8 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .data.udp_port + 0x00000000200000bc 0x2 ./Middlewares/Third_Party/LwIP/src/core/udp.o + *fill* 0x00000000200000be 0x2 + .data.dhcp_discover_request_options + 0x00000000200000c0 0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .data._impure_ptr + 0x00000000200000c4 0x4 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o) + 0x00000000200000c4 _impure_ptr + .data.impure_data + 0x00000000200000c8 0x60 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-impure.o) + *(.RamFunc) + *(.RamFunc*) + 0x0000000020000128 . = ALIGN (0x4) + 0x0000000020000128 _edata = . + +.igot.plt 0x0000000020000128 0x0 load address 0x0000000008023e90 + .igot.plt 0x0000000020000128 0x0 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + +.RxDecripSection + 0x0000000020000128 0xa0 load address 0x0000000008023e90 + .RxDecripSection + 0x0000000020000128 0xa0 ./LWIP/Target/ethernetif.o + 0x0000000020000128 DMARxDscrTab + +.TxDecripSection + 0x00000000200001c8 0xa0 load address 0x0000000008023f30 + .TxDecripSection + 0x00000000200001c8 0xa0 ./LWIP/Target/ethernetif.o + 0x00000000200001c8 DMATxDscrTab + 0x0000000020000268 . = ALIGN (0x4) + +.bss 0x0000000020000268 0xce88 load address 0x0000000008023fd0 + 0x0000000020000268 _sbss = . + 0x0000000020000268 __bss_start__ = _sbss + *(.bss) + .bss 0x0000000020000268 0x1c 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./Middlewares/Third_Party/LwIP/src/core/ip.o + 0x0000000020009670 ip_data + .bss.ram_heap 0x0000000020009688 0x653 ./Middlewares/Third_Party/LwIP/src/core/mem.o + 0x0000000020009688 ram_heap + *fill* 0x0000000020009cdb 0x1 + .bss.ram 0x0000000020009cdc 0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o + .bss.ram_end 0x0000000020009ce0 0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o + .bss.mem_mutex + 0x0000000020009ce4 0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o + .bss.lfree 0x0000000020009ce8 0x4 ./Middlewares/Third_Party/LwIP/src/core/mem.o + .bss.memp_memory_UDP_PCB_base + 0x0000000020009cec 0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x0000000020009cec memp_memory_UDP_PCB_base + *fill* 0x0000000020009d6f 0x1 + .bss.memp_tab_UDP_PCB + 0x0000000020009d70 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_TCP_PCB_base + 0x0000000020009d74 0x30f ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x0000000020009d74 memp_memory_TCP_PCB_base + *fill* 0x000000002000a083 0x1 + .bss.memp_tab_TCP_PCB + 0x000000002000a084 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_TCP_PCB_LISTEN_base + 0x000000002000a088 0xe3 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a088 memp_memory_TCP_PCB_LISTEN_base + *fill* 0x000000002000a16b 0x1 + .bss.memp_tab_TCP_PCB_LISTEN + 0x000000002000a16c 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_TCP_SEG_base + 0x000000002000a170 0x103 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a170 memp_memory_TCP_SEG_base + *fill* 0x000000002000a273 0x1 + .bss.memp_tab_TCP_SEG + 0x000000002000a274 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_REASSDATA_base + 0x000000002000a278 0xa3 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a278 memp_memory_REASSDATA_base + *fill* 0x000000002000a31b 0x1 + .bss.memp_tab_REASSDATA + 0x000000002000a31c 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_FRAG_PBUF_base + 0x000000002000a320 0x16b ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a320 memp_memory_FRAG_PBUF_base + *fill* 0x000000002000a48b 0x1 + .bss.memp_tab_FRAG_PBUF + 0x000000002000a48c 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_NETBUF_base + 0x000000002000a490 0x23 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a490 memp_memory_NETBUF_base + *fill* 0x000000002000a4b3 0x1 + .bss.memp_tab_NETBUF + 0x000000002000a4b4 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_NETCONN_base + 0x000000002000a4b8 0xa3 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a4b8 memp_memory_NETCONN_base + *fill* 0x000000002000a55b 0x1 + .bss.memp_tab_NETCONN + 0x000000002000a55c 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_TCPIP_MSG_API_base + 0x000000002000a560 0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a560 memp_memory_TCPIP_MSG_API_base + *fill* 0x000000002000a5e3 0x1 + .bss.memp_tab_TCPIP_MSG_API + 0x000000002000a5e4 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_TCPIP_MSG_INPKT_base + 0x000000002000a5e8 0x83 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a5e8 memp_memory_TCPIP_MSG_INPKT_base + *fill* 0x000000002000a66b 0x1 + .bss.memp_tab_TCPIP_MSG_INPKT + 0x000000002000a66c 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_SYS_TIMEOUT_base + 0x000000002000a670 0x63 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a670 memp_memory_SYS_TIMEOUT_base + *fill* 0x000000002000a6d3 0x1 + .bss.memp_tab_SYS_TIMEOUT + 0x000000002000a6d4 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_NETDB_base + 0x000000002000a6d8 0x137 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a6d8 memp_memory_NETDB_base + *fill* 0x000000002000a80f 0x1 + .bss.memp_tab_NETDB + 0x000000002000a810 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_PBUF_base + 0x000000002000a814 0x103 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a814 memp_memory_PBUF_base + *fill* 0x000000002000a917 0x1 + .bss.memp_tab_PBUF + 0x000000002000a918 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.memp_memory_PBUF_POOL_base + 0x000000002000a91c 0x2603 ./Middlewares/Third_Party/LwIP/src/core/memp.o + 0x000000002000a91c memp_memory_PBUF_POOL_base + *fill* 0x000000002000cf1f 0x1 + .bss.memp_tab_PBUF_POOL + 0x000000002000cf20 0x4 ./Middlewares/Third_Party/LwIP/src/core/memp.o + .bss.netif_list + 0x000000002000cf24 0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o + 0x000000002000cf24 netif_list + .bss.netif_default + 0x000000002000cf28 0x4 ./Middlewares/Third_Party/LwIP/src/core/netif.o + 0x000000002000cf28 netif_default + .bss.netif_num + 0x000000002000cf2c 0x1 ./Middlewares/Third_Party/LwIP/src/core/netif.o + .bss.pbuf_free_ooseq_pending + 0x000000002000cf2d 0x1 ./Middlewares/Third_Party/LwIP/src/core/pbuf.o + 0x000000002000cf2d pbuf_free_ooseq_pending + *fill* 0x000000002000cf2e 0x2 + .bss.tcp_ticks + 0x000000002000cf30 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf30 tcp_ticks + .bss.tcp_bound_pcbs + 0x000000002000cf34 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf34 tcp_bound_pcbs + .bss.tcp_listen_pcbs + 0x000000002000cf38 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf38 tcp_listen_pcbs + .bss.tcp_active_pcbs + 0x000000002000cf3c 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf3c tcp_active_pcbs + .bss.tcp_tw_pcbs + 0x000000002000cf40 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf40 tcp_tw_pcbs + .bss.tcp_active_pcbs_changed + 0x000000002000cf44 0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + 0x000000002000cf44 tcp_active_pcbs_changed + .bss.tcp_timer + 0x000000002000cf45 0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + .bss.tcp_timer_ctr + 0x000000002000cf46 0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp.o + *fill* 0x000000002000cf47 0x1 + .bss.inseg 0x000000002000cf48 0x10 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcphdr 0x000000002000cf58 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcphdr_optlen + 0x000000002000cf5c 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcphdr_opt1len + 0x000000002000cf5e 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcphdr_opt2 + 0x000000002000cf60 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcp_optidx + 0x000000002000cf64 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + *fill* 0x000000002000cf66 0x2 + .bss.seqno 0x000000002000cf68 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.ackno 0x000000002000cf6c 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.recv_acked + 0x000000002000cf70 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcplen 0x000000002000cf72 0x2 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.flags 0x000000002000cf74 0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.recv_flags + 0x000000002000cf75 0x1 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + *fill* 0x000000002000cf76 0x2 + .bss.recv_data + 0x000000002000cf78 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + .bss.tcp_input_pcb + 0x000000002000cf7c 0x4 ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o + 0x000000002000cf7c tcp_input_pcb + .bss.next_timeout + 0x000000002000cf80 0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .bss.current_timeout_due_time + 0x000000002000cf84 0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .bss.tcpip_tcp_timer_active + 0x000000002000cf88 0x4 ./Middlewares/Third_Party/LwIP/src/core/timeouts.o + .bss.udp_pcbs 0x000000002000cf8c 0x4 ./Middlewares/Third_Party/LwIP/src/core/udp.o + 0x000000002000cf8c udp_pcbs + .bss.dhcp_rx_options_val + 0x000000002000cf90 0x28 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x000000002000cf90 dhcp_rx_options_val + .bss.dhcp_rx_options_given + 0x000000002000cfb8 0xa ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + 0x000000002000cfb8 dhcp_rx_options_given + *fill* 0x000000002000cfc2 0x2 + .bss.dhcp_pcb 0x000000002000cfc4 0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .bss.dhcp_pcb_refcount + 0x000000002000cfc8 0x1 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + *fill* 0x000000002000cfc9 0x3 + .bss.xid.0 0x000000002000cfcc 0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o + .bss.arp_table + 0x000000002000cfd0 0xf0 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o + .bss.etharp_cached_entry + 0x000000002000d0c0 0x1 ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o + *fill* 0x000000002000d0c1 0x1 + .bss.ip_id 0x000000002000d0c2 0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o + .bss.str.0 0x000000002000d0c4 0x10 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o + .bss.reassdatagrams + 0x000000002000d0d4 0x4 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o + .bss.ip_reass_pbufcount + 0x000000002000d0d8 0x2 ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o + *fill* 0x000000002000d0da 0x2 + .bss.lwip_sys_mutex + 0x000000002000d0dc 0x4 ./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o + 0x000000002000d0dc lwip_sys_mutex + .bss.__lock___malloc_recursive_mutex + 0x000000002000d0e0 0x1 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-lock.o) + 0x000000002000d0e0 __lock___malloc_recursive_mutex + .bss.__lock___sfp_recursive_mutex + 0x000000002000d0e1 0x1 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-lock.o) + 0x000000002000d0e1 __lock___sfp_recursive_mutex + .bss.__lock___sinit_recursive_mutex + 0x000000002000d0e2 0x1 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-lock.o) + 0x000000002000d0e2 __lock___sinit_recursive_mutex + *fill* 0x000000002000d0e3 0x1 + .bss.__malloc_free_list + 0x000000002000d0e4 0x4 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x000000002000d0e4 __malloc_free_list + .bss.__malloc_sbrk_start + 0x000000002000d0e8 0x4 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x000000002000d0e8 __malloc_sbrk_start + .bss.errno 0x000000002000d0ec 0x4 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-reent.o) + 0x000000002000d0ec errno + *(COMMON) + 0x000000002000d0f0 . = ALIGN (0x4) + 0x000000002000d0f0 _ebss = . + 0x000000002000d0f0 __bss_end__ = _ebss + +._user_heap_stack + 0x000000002000d0f0 0x600 load address 0x0000000008023fd0 + 0x000000002000d0f0 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x000000002000d0f0 PROVIDE (_end = .) + 0x000000002000d2f0 . = (. + _Min_Heap_Size) + *fill* 0x000000002000d0f0 0x200 + 0x000000002000d6f0 . = (. + _Min_Stack_Size) + *fill* 0x000000002000d2f0 0x400 + 0x000000002000d6f0 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crti.o + .ARM.attributes + 0x000000000000001e 0x34 /opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.200.202301161003/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .ARM.attributes + 0x0000000000000052 0x34 ./Core/Src/NTP.o + .ARM.attributes + 0x0000000000000086 0x34 ./Core/Src/RTC.o + .ARM.attributes + 0x00000000000000ba 0x34 ./Core/Src/Time.o + .ARM.attributes + 0x00000000000000ee 0x34 ./Core/Src/app_main.o + .ARM.attributes + 0x0000000000000122 0x34 ./Core/Src/clock.o + .ARM.attributes + 0x0000000000000156 0x34 ./Core/Src/debug.o + .ARM.attributes + 0x000000000000018a 0x34 ./Core/Src/ds3231_for_stm32_hal.o + .ARM.attributes + 0x00000000000001be 0x34 ./Core/Src/freertos.o + .ARM.attributes + 0x00000000000001f2 0x34 ./Core/Src/main.o + .ARM.attributes + 0x0000000000000226 0x34 ./Core/Src/stm32f7xx_hal_msp.o + .ARM.attributes + 0x000000000000025a 0x34 ./Core/Src/stm32f7xx_hal_timebase_tim.o + .ARM.attributes + 0x000000000000028e 0x34 ./Core/Src/stm32f7xx_it.o + .ARM.attributes + 0x00000000000002c2 0x34 ./Core/Src/syscalls.o + .ARM.attributes + 0x00000000000002f6 0x34 ./Core/Src/sysmem.o + .ARM.attributes + 0x000000000000032a 0x34 ./Core/Src/system_stm32f7xx.o + .ARM.attributes + 0x000000000000035e 0x21 ./Core/Startup/startup_stm32f746nghx.o + .ARM.attributes + 0x000000000000037f 0x34 ./Drivers/BSP/Components/lan8742/lan8742.o + .ARM.attributes + 0x00000000000003b3 0x34 ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o + .ARM.attributes + 0x00000000000003e7 0x34 ./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o + .ARM.attributes + 0x000000000000041b 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .ARM.attributes + 0x000000000000044f 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .ARM.attributes + 0x0000000000000483 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .ARM.attributes + 0x00000000000004b7 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .ARM.attributes + 0x00000000000004eb 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o + .ARM.attributes + 0x000000000000051f 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .ARM.attributes + 0x0000000000000553 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .ARM.attributes + 0x0000000000000587 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .ARM.attributes + 0x00000000000005bb 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .ARM.attributes + 0x00000000000005ef 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000623 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .ARM.attributes + 0x0000000000000657 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .ARM.attributes + 0x000000000000068b 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .ARM.attributes + 0x00000000000006bf 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .ARM.attributes + 0x00000000000006f3 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .ARM.attributes + 0x0000000000000727 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .ARM.attributes + 0x000000000000075b 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .ARM.attributes + 0x000000000000078f 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .ARM.attributes + 0x00000000000007c3 0x34 ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .ARM.attributes + 0x00000000000007f7 0x34 ./LWIP/App/lwip.o + .ARM.attributes + 0x000000000000082b 0x34 ./LWIP/Target/ethernetif.o + .ARM.attributes + 0x000000000000085f 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .ARM.attributes + 0x0000000000000893 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + .ARM.attributes + 0x00000000000008c7 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 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+################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Middlewares/Third_Party/LwIP/system/OS/subdir.mk +-include Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk +-include Middlewares/Third_Party/LwIP/src/netif/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/subdir.mk +-include Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk +-include Middlewares/Third_Party/LwIP/src/api/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +-include LWIP/Target/subdir.mk +-include LWIP/App/subdir.mk +-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +-include Drivers/BSP/STM32746G-Discovery/subdir.mk +-include Drivers/BSP/Components/lan8742/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := NTP +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +NTP.elf \ + +MAP_FILES += \ +NTP.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +NTP.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: NTP.elf secondary-outputs + +# Tool invocations +NTP.elf NTP.map: $(OBJS) $(USER_OBJS) /home/sanderspeetjens/Documents/ThomasMore/Phase2/Semester1/EmbeddedSystems/lab/project/NTP/STM32F746NGHX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "NTP.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/sanderspeetjens/Documents/ThomasMore/Phase2/Semester1/EmbeddedSystems/lab/project/NTP/STM32F746NGHX_FLASH.ld" --specs=nosys.specs -Wl,-Map="NTP.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +NTP.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "NTP.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) NTP.elf NTP.list NTP.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/project/Debug/objects.list b/project/Debug/objects.list new file mode 100644 index 0000000..da2a52f --- /dev/null +++ b/project/Debug/objects.list @@ -0,0 +1,140 @@ +"./Core/Src/NTP.o" +"./Core/Src/RTC.o" +"./Core/Src/Time.o" +"./Core/Src/app_main.o" +"./Core/Src/clock.o" +"./Core/Src/debug.o" +"./Core/Src/ds3231_for_stm32_hal.o" +"./Core/Src/freertos.o" +"./Core/Src/main.o" +"./Core/Src/stm32f7xx_hal_msp.o" +"./Core/Src/stm32f7xx_hal_timebase_tim.o" +"./Core/Src/stm32f7xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f7xx.o" +"./Core/Startup/startup_stm32f746nghx.o" +"./Drivers/BSP/Components/lan8742/lan8742.o" +"./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.o" +"./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.o" +"./Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o" +"./LWIP/App/lwip.o" +"./LWIP/Target/ethernetif.o" +"./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o" +"./Middlewares/Third_Party/FreeRTOS/Source/croutine.o" +"./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" +"./Middlewares/Third_Party/FreeRTOS/Source/list.o" +"./Middlewares/Third_Party/FreeRTOS/Source/queue.o" +"./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o" +"./Middlewares/Third_Party/FreeRTOS/Source/tasks.o" +"./Middlewares/Third_Party/FreeRTOS/Source/timers.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o" +"./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o" +"./Middlewares/Third_Party/LwIP/src/api/api_lib.o" +"./Middlewares/Third_Party/LwIP/src/api/api_msg.o" +"./Middlewares/Third_Party/LwIP/src/api/err.o" +"./Middlewares/Third_Party/LwIP/src/api/if_api.o" +"./Middlewares/Third_Party/LwIP/src/api/netbuf.o" +"./Middlewares/Third_Party/LwIP/src/api/netdb.o" +"./Middlewares/Third_Party/LwIP/src/api/netifapi.o" +"./Middlewares/Third_Party/LwIP/src/api/sockets.o" +"./Middlewares/Third_Party/LwIP/src/api/tcpip.o" +"./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o" +"./Middlewares/Third_Party/LwIP/src/core/def.o" +"./Middlewares/Third_Party/LwIP/src/core/dns.o" +"./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o" +"./Middlewares/Third_Party/LwIP/src/core/init.o" +"./Middlewares/Third_Party/LwIP/src/core/ip.o" +"./Middlewares/Third_Party/LwIP/src/core/mem.o" +"./Middlewares/Third_Party/LwIP/src/core/memp.o" +"./Middlewares/Third_Party/LwIP/src/core/netif.o" +"./Middlewares/Third_Party/LwIP/src/core/pbuf.o" +"./Middlewares/Third_Party/LwIP/src/core/raw.o" +"./Middlewares/Third_Party/LwIP/src/core/stats.o" +"./Middlewares/Third_Party/LwIP/src/core/sys.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp_in.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp_out.o" +"./Middlewares/Third_Party/LwIP/src/core/timeouts.o" +"./Middlewares/Third_Party/LwIP/src/core/udp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o" +"./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o" +"./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o" +"./Middlewares/Third_Party/LwIP/src/netif/ethernet.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o" +"./Middlewares/Third_Party/LwIP/src/netif/slipif.o" +"./Middlewares/Third_Party/LwIP/src/netif/zepif.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o" +"./Middlewares/Third_Party/LwIP/system/OS/sys_arch.o" diff --git a/project/Debug/objects.mk b/project/Debug/objects.mk new file mode 100644 index 0000000..e423e31 --- /dev/null +++ b/project/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/project/Debug/sources.mk b/project/Debug/sources.mk new file mode 100644 index 0000000..4df2760 --- /dev/null +++ b/project/Debug/sources.mk @@ -0,0 +1,44 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (10.3-2021.10) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/BSP/Components/lan8742 \ +Drivers/BSP/STM32746G-Discovery \ +Drivers/STM32F7xx_HAL_Driver/Src \ +LWIP/App \ +LWIP/Target \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \ +Middlewares/Third_Party/FreeRTOS/Source \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \ +Middlewares/Third_Party/LwIP/src/api \ +Middlewares/Third_Party/LwIP/src/apps/mqtt \ +Middlewares/Third_Party/LwIP/src/core \ +Middlewares/Third_Party/LwIP/src/core/ipv4 \ +Middlewares/Third_Party/LwIP/src/core/ipv6 \ +Middlewares/Third_Party/LwIP/src/netif \ +Middlewares/Third_Party/LwIP/src/netif/ppp \ +Middlewares/Third_Party/LwIP/system/OS \ + diff --git a/NTP/Drivers/BSP/Components/lan8742/lan8742.c b/project/Drivers/BSP/Components/lan8742/lan8742.c similarity index 100% rename from NTP/Drivers/BSP/Components/lan8742/lan8742.c rename to project/Drivers/BSP/Components/lan8742/lan8742.c diff --git a/NTP/Drivers/BSP/Components/lan8742/lan8742.h b/project/Drivers/BSP/Components/lan8742/lan8742.h similarity index 100% rename from NTP/Drivers/BSP/Components/lan8742/lan8742.h rename to project/Drivers/BSP/Components/lan8742/lan8742.h diff --git a/NTP/Drivers/BSP/Components/rk043fn48h/Release_Notes.html b/project/Drivers/BSP/Components/rk043fn48h/Release_Notes.html similarity index 100% rename from NTP/Drivers/BSP/Components/rk043fn48h/Release_Notes.html rename to project/Drivers/BSP/Components/rk043fn48h/Release_Notes.html diff --git a/NTP/Drivers/BSP/Components/rk043fn48h/rk043fn48h.h b/project/Drivers/BSP/Components/rk043fn48h/rk043fn48h.h similarity index 100% rename from NTP/Drivers/BSP/Components/rk043fn48h/rk043fn48h.h rename to project/Drivers/BSP/Components/rk043fn48h/rk043fn48h.h diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.c diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery.h diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.h diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c diff --git a/NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h b/project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h similarity index 100% rename from NTP/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h rename to project/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h diff --git a/NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h similarity index 100% rename from NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h rename to project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h diff --git a/NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h b/project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h similarity index 100% rename from NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h rename to project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h diff --git a/NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h similarity index 100% rename from NTP/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h rename to project/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h diff --git a/NTP/Drivers/CMSIS/Device/ST/STM32F7xx/LICENSE.txt b/project/Drivers/CMSIS/Device/ST/STM32F7xx/LICENSE.txt similarity index 100% rename from NTP/Drivers/CMSIS/Device/ST/STM32F7xx/LICENSE.txt rename to project/Drivers/CMSIS/Device/ST/STM32F7xx/LICENSE.txt diff --git a/NTP/Drivers/CMSIS/Include/cmsis_armcc.h b/project/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_armcc.h rename to project/Drivers/CMSIS/Include/cmsis_armcc.h diff --git a/NTP/Drivers/CMSIS/Include/cmsis_armclang.h b/project/Drivers/CMSIS/Include/cmsis_armclang.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_armclang.h rename to project/Drivers/CMSIS/Include/cmsis_armclang.h diff --git a/NTP/Drivers/CMSIS/Include/cmsis_compiler.h b/project/Drivers/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_compiler.h rename to project/Drivers/CMSIS/Include/cmsis_compiler.h diff --git a/NTP/Drivers/CMSIS/Include/cmsis_gcc.h b/project/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_gcc.h rename to project/Drivers/CMSIS/Include/cmsis_gcc.h diff --git a/NTP/Drivers/CMSIS/Include/cmsis_iccarm.h b/project/Drivers/CMSIS/Include/cmsis_iccarm.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_iccarm.h rename to project/Drivers/CMSIS/Include/cmsis_iccarm.h diff --git a/NTP/Drivers/CMSIS/Include/cmsis_version.h b/project/Drivers/CMSIS/Include/cmsis_version.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/cmsis_version.h rename to project/Drivers/CMSIS/Include/cmsis_version.h diff --git a/NTP/Drivers/CMSIS/Include/core_armv8mbl.h b/project/Drivers/CMSIS/Include/core_armv8mbl.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_armv8mbl.h rename to project/Drivers/CMSIS/Include/core_armv8mbl.h diff --git a/NTP/Drivers/CMSIS/Include/core_armv8mml.h b/project/Drivers/CMSIS/Include/core_armv8mml.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_armv8mml.h rename to project/Drivers/CMSIS/Include/core_armv8mml.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm0.h b/project/Drivers/CMSIS/Include/core_cm0.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm0.h rename to project/Drivers/CMSIS/Include/core_cm0.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm0plus.h b/project/Drivers/CMSIS/Include/core_cm0plus.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm0plus.h rename to project/Drivers/CMSIS/Include/core_cm0plus.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm1.h b/project/Drivers/CMSIS/Include/core_cm1.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm1.h rename to project/Drivers/CMSIS/Include/core_cm1.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm23.h b/project/Drivers/CMSIS/Include/core_cm23.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm23.h rename to project/Drivers/CMSIS/Include/core_cm23.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm3.h b/project/Drivers/CMSIS/Include/core_cm3.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm3.h rename to project/Drivers/CMSIS/Include/core_cm3.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm33.h b/project/Drivers/CMSIS/Include/core_cm33.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm33.h rename to project/Drivers/CMSIS/Include/core_cm33.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm4.h b/project/Drivers/CMSIS/Include/core_cm4.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm4.h rename to project/Drivers/CMSIS/Include/core_cm4.h diff --git a/NTP/Drivers/CMSIS/Include/core_cm7.h b/project/Drivers/CMSIS/Include/core_cm7.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_cm7.h rename to project/Drivers/CMSIS/Include/core_cm7.h diff --git a/NTP/Drivers/CMSIS/Include/core_sc000.h b/project/Drivers/CMSIS/Include/core_sc000.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_sc000.h rename to project/Drivers/CMSIS/Include/core_sc000.h diff --git a/NTP/Drivers/CMSIS/Include/core_sc300.h b/project/Drivers/CMSIS/Include/core_sc300.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/core_sc300.h rename to project/Drivers/CMSIS/Include/core_sc300.h diff --git a/NTP/Drivers/CMSIS/Include/mpu_armv7.h b/project/Drivers/CMSIS/Include/mpu_armv7.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/mpu_armv7.h rename to project/Drivers/CMSIS/Include/mpu_armv7.h diff --git a/NTP/Drivers/CMSIS/Include/mpu_armv8.h b/project/Drivers/CMSIS/Include/mpu_armv8.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/mpu_armv8.h rename to project/Drivers/CMSIS/Include/mpu_armv8.h diff --git a/NTP/Drivers/CMSIS/Include/tz_context.h b/project/Drivers/CMSIS/Include/tz_context.h similarity index 100% rename from NTP/Drivers/CMSIS/Include/tz_context.h rename to project/Drivers/CMSIS/Include/tz_context.h diff --git a/NTP/Drivers/CMSIS/LICENSE.txt b/project/Drivers/CMSIS/LICENSE.txt similarity index 100% rename from NTP/Drivers/CMSIS/LICENSE.txt rename to project/Drivers/CMSIS/LICENSE.txt diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h rename to project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt b/project/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt rename to project/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c diff --git a/NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c similarity index 100% rename from NTP/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c rename to project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c diff --git a/NTP/LWIP/App/lwip.c b/project/LWIP/App/lwip.c similarity index 100% rename from NTP/LWIP/App/lwip.c rename to project/LWIP/App/lwip.c diff --git a/NTP/LWIP/App/lwip.h b/project/LWIP/App/lwip.h similarity index 100% rename from NTP/LWIP/App/lwip.h rename to project/LWIP/App/lwip.h diff --git a/NTP/LWIP/Target/ethernetif.c b/project/LWIP/Target/ethernetif.c similarity index 100% rename from NTP/LWIP/Target/ethernetif.c rename to project/LWIP/Target/ethernetif.c diff --git a/NTP/LWIP/Target/ethernetif.h b/project/LWIP/Target/ethernetif.h similarity index 100% rename from NTP/LWIP/Target/ethernetif.h rename to project/LWIP/Target/ethernetif.h diff --git a/NTP/LWIP/Target/lwipopts.h b/project/LWIP/Target/lwipopts.h similarity index 100% rename from NTP/LWIP/Target/lwipopts.h rename to project/LWIP/Target/lwipopts.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/project/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/project/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/project/Middlewares/Third_Party/FreeRTOS/Source/croutine.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/croutine.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/croutine.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/project/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/list.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/list.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/list.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/task.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/task.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/task.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/project/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/list.c b/project/Middlewares/Third_Party/FreeRTOS/Source/list.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/list.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/list.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/project/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/project/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h rename to project/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/project/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/project/Middlewares/Third_Party/FreeRTOS/Source/queue.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/queue.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/queue.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/project/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/project/Middlewares/Third_Party/FreeRTOS/Source/tasks.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/tasks.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/tasks.c diff --git a/NTP/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/project/Middlewares/Third_Party/FreeRTOS/Source/timers.c similarity index 100% rename from NTP/Middlewares/Third_Party/FreeRTOS/Source/timers.c rename to project/Middlewares/Third_Party/FreeRTOS/Source/timers.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/api_lib.c b/project/Middlewares/Third_Party/LwIP/src/api/api_lib.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/api_lib.c rename to project/Middlewares/Third_Party/LwIP/src/api/api_lib.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/api_msg.c b/project/Middlewares/Third_Party/LwIP/src/api/api_msg.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/api_msg.c rename to project/Middlewares/Third_Party/LwIP/src/api/api_msg.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/err.c b/project/Middlewares/Third_Party/LwIP/src/api/err.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/err.c rename to project/Middlewares/Third_Party/LwIP/src/api/err.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/if_api.c b/project/Middlewares/Third_Party/LwIP/src/api/if_api.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/if_api.c rename to project/Middlewares/Third_Party/LwIP/src/api/if_api.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/netbuf.c b/project/Middlewares/Third_Party/LwIP/src/api/netbuf.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/netbuf.c rename to project/Middlewares/Third_Party/LwIP/src/api/netbuf.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/netdb.c b/project/Middlewares/Third_Party/LwIP/src/api/netdb.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/netdb.c rename to project/Middlewares/Third_Party/LwIP/src/api/netdb.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/netifapi.c b/project/Middlewares/Third_Party/LwIP/src/api/netifapi.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/netifapi.c rename to project/Middlewares/Third_Party/LwIP/src/api/netifapi.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/sockets.c b/project/Middlewares/Third_Party/LwIP/src/api/sockets.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/sockets.c rename to project/Middlewares/Third_Party/LwIP/src/api/sockets.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/api/tcpip.c b/project/Middlewares/Third_Party/LwIP/src/api/tcpip.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/api/tcpip.c rename to project/Middlewares/Third_Party/LwIP/src/api/tcpip.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c b/project/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c rename to project/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/altcp.c b/project/Middlewares/Third_Party/LwIP/src/core/altcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/altcp.c rename to project/Middlewares/Third_Party/LwIP/src/core/altcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c b/project/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c rename to project/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c b/project/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c rename to project/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/def.c b/project/Middlewares/Third_Party/LwIP/src/core/def.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/def.c rename to project/Middlewares/Third_Party/LwIP/src/core/def.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/dns.c b/project/Middlewares/Third_Party/LwIP/src/core/dns.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/dns.c rename to project/Middlewares/Third_Party/LwIP/src/core/dns.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c b/project/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c rename to project/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/init.c b/project/Middlewares/Third_Party/LwIP/src/core/init.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/init.c rename to project/Middlewares/Third_Party/LwIP/src/core/init.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ip.c b/project/Middlewares/Third_Party/LwIP/src/core/ip.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ip.c rename to project/Middlewares/Third_Party/LwIP/src/core/ip.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c b/project/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c rename to project/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/mem.c b/project/Middlewares/Third_Party/LwIP/src/core/mem.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/mem.c rename to project/Middlewares/Third_Party/LwIP/src/core/mem.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/memp.c b/project/Middlewares/Third_Party/LwIP/src/core/memp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/memp.c rename to project/Middlewares/Third_Party/LwIP/src/core/memp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/netif.c b/project/Middlewares/Third_Party/LwIP/src/core/netif.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/netif.c rename to project/Middlewares/Third_Party/LwIP/src/core/netif.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/pbuf.c b/project/Middlewares/Third_Party/LwIP/src/core/pbuf.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/pbuf.c rename to project/Middlewares/Third_Party/LwIP/src/core/pbuf.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/raw.c b/project/Middlewares/Third_Party/LwIP/src/core/raw.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/raw.c rename to project/Middlewares/Third_Party/LwIP/src/core/raw.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/stats.c b/project/Middlewares/Third_Party/LwIP/src/core/stats.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/stats.c rename to project/Middlewares/Third_Party/LwIP/src/core/stats.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/sys.c b/project/Middlewares/Third_Party/LwIP/src/core/sys.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/sys.c rename to project/Middlewares/Third_Party/LwIP/src/core/sys.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/tcp.c b/project/Middlewares/Third_Party/LwIP/src/core/tcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/tcp.c rename to project/Middlewares/Third_Party/LwIP/src/core/tcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/tcp_in.c b/project/Middlewares/Third_Party/LwIP/src/core/tcp_in.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/tcp_in.c rename to project/Middlewares/Third_Party/LwIP/src/core/tcp_in.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/tcp_out.c b/project/Middlewares/Third_Party/LwIP/src/core/tcp_out.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/tcp_out.c rename to project/Middlewares/Third_Party/LwIP/src/core/tcp_out.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/timeouts.c b/project/Middlewares/Third_Party/LwIP/src/core/timeouts.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/timeouts.c rename to project/Middlewares/Third_Party/LwIP/src/core/timeouts.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/core/udp.c b/project/Middlewares/Third_Party/LwIP/src/core/udp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/core/udp.c rename to project/Middlewares/Third_Party/LwIP/src/core/udp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h b/project/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h rename to project/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h b/project/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h rename to project/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h b/project/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h rename to project/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h b/project/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h rename to project/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h b/project/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h rename to project/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/api.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/api.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/api.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/api.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/def.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/def.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/def.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/def.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/err.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/err.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/err.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/err.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/init.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/init.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/init.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/init.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h b/project/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h rename to project/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h b/project/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h rename to project/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c b/project/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c rename to project/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c b/project/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c rename to project/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ethernet.c b/project/Middlewares/Third_Party/LwIP/src/netif/ethernet.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ethernet.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ethernet.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c b/project/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c rename to project/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c b/project/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c rename to project/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c b/project/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c rename to project/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c b/project/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c rename to project/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/slipif.c b/project/Middlewares/Third_Party/LwIP/src/netif/slipif.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/slipif.c rename to project/Middlewares/Third_Party/LwIP/src/netif/slipif.c diff --git a/NTP/Middlewares/Third_Party/LwIP/src/netif/zepif.c b/project/Middlewares/Third_Party/LwIP/src/netif/zepif.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/src/netif/zepif.c rename to project/Middlewares/Third_Party/LwIP/src/netif/zepif.c diff --git a/NTP/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c b/project/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c rename to project/Middlewares/Third_Party/LwIP/system/OS/sys_arch.c diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h b/project/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h rename to project/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/cc.h b/project/Middlewares/Third_Party/LwIP/system/arch/cc.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/cc.h rename to project/Middlewares/Third_Party/LwIP/system/arch/cc.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/cpu.h b/project/Middlewares/Third_Party/LwIP/system/arch/cpu.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/cpu.h rename to project/Middlewares/Third_Party/LwIP/system/arch/cpu.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/epstruct.h b/project/Middlewares/Third_Party/LwIP/system/arch/epstruct.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/epstruct.h rename to project/Middlewares/Third_Party/LwIP/system/arch/epstruct.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/init.h b/project/Middlewares/Third_Party/LwIP/system/arch/init.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/init.h rename to project/Middlewares/Third_Party/LwIP/system/arch/init.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/lib.h b/project/Middlewares/Third_Party/LwIP/system/arch/lib.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/lib.h rename to project/Middlewares/Third_Party/LwIP/system/arch/lib.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/perf.h b/project/Middlewares/Third_Party/LwIP/system/arch/perf.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/perf.h rename to project/Middlewares/Third_Party/LwIP/system/arch/perf.h diff --git a/NTP/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h b/project/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h similarity index 100% rename from NTP/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h rename to project/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h diff --git a/NTP/NTP Debug.launch b/project/NTP Debug.launch similarity index 100% rename from NTP/NTP Debug.launch rename to project/NTP Debug.launch diff --git a/NTP/NTP.ioc b/project/NTP.ioc similarity index 100% rename from NTP/NTP.ioc rename to project/NTP.ioc diff --git a/NTP/STM32F746NGHX_FLASH.ld b/project/STM32F746NGHX_FLASH.ld similarity index 100% rename from NTP/STM32F746NGHX_FLASH.ld rename to project/STM32F746NGHX_FLASH.ld diff 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