From 570c61f379b26ef19d04aa73ac20820f7feac375 Mon Sep 17 00:00:00 2001
From: Sani7 <sander.speetjens@gmail.com>
Date: Mon, 6 Nov 2023 13:29:31 +0100
Subject: [PATCH 1/6] Set ioc File

---
 project/.cproject                             |    2 +-
 project/.mxproject                            |   40 +-
 .../Inc/stm32f7xx_hal_qspi.h                  | 1500 ++---
 .../Src/stm32f7xx_hal_qspi.c                  | 5680 ++++++++---------
 project/LWIP/Target/lwipopts.h                |   14 +
 project/project.ioc                           |   12 +-
 6 files changed, 3634 insertions(+), 3614 deletions(-)

diff --git a/project/.cproject b/project/.cproject
index 5a36f3b..b36ef16 100644
--- a/project/.cproject
+++ b/project/.cproject
@@ -124,7 +124,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.118832767" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1749227860" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="STM32F746G-DISCO" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.752119389" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F746G-DISCO || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../LWIP/App | ../LWIP/Target | ../Core/Inc | ../Middlewares/Third_Party/LwIP/src/include | ../Middlewares/Third_Party/LwIP/system | ../Drivers/STM32F7xx_HAL_Driver/Inc | ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy | ../Drivers/BSP/Components/lan8742 | ../Middlewares/Third_Party/LwIP/src/include/netif/ppp | ../Middlewares/Third_Party/LwIP/src/apps/http | ../Drivers/CMSIS/Device/ST/STM32F7xx/Include | ../Middlewares/Third_Party/LwIP/src/include/lwip | ../Middlewares/Third_Party/LwIP/src/include/lwip/apps | ../Middlewares/Third_Party/LwIP/src/include/lwip/priv | ../Middlewares/Third_Party/LwIP/src/include/lwip/prot | ../Middlewares/Third_Party/LwIP/src/include/netif | ../Middlewares/Third_Party/LwIP/src/include/compat/posix | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/net | ../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys | ../Middlewares/Third_Party/LwIP/src/include/compat/stdc | ../Middlewares/Third_Party/LwIP/system/arch | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F746xx ||  || LWIP | Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F746NGHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.692149734" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="200" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.692149734" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="200" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.31610660" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/project}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.525679761" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.936753340" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/project/.mxproject b/project/.mxproject
index 433d0c1..9ff0a3d 100644
--- a/project/.mxproject
+++ b/project/.mxproject
@@ -1,34 +1,34 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma2d.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma2d.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_fmc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sdram.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dsi.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_qspi.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\BSP\Components\lan8742\lan8742.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ccp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap_ms.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-md5.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-new.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eui64.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\fsm.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipv6cp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\lcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\magic.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\mppe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_impl.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppapi.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppcrypt.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppdebug.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppoe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppol2tp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppos.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\upap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\vj.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ecp.h;Middlewares\Third_Party\LwIP\src\apps\http\fsdata.h;Middlewares\Third_Party\LwIP\src\apps\http\httpd_structs.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma2d.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_fmc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_sdram.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dsi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\BSP\Components\lan8742\lan8742.c;Middlewares\Third_Party\LwIP\src\netif\ppp\auth.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ccp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap_ms.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-md5.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-new.c;Middlewares\Third_Party\LwIP\src\netif\ppp\demand.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eui64.c;Middlewares\Third_Party\LwIP\src\netif\ppp\fsm.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipv6cp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\lcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\magic.c;Middlewares\Third_Party\LwIP\src\netif\ppp\mppe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\multilink.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ppp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppapi.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppcrypt.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppoe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppol2tp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppos.c;Middlewares\Third_Party\LwIP\src\netif\ppp\upap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\utils.c;Middlewares\Third_Party\LwIP\src\netif\ppp\vj.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif_fdb.c;Middlewares\Third_Party\LwIP\src\netif\ethernet.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_ble.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_common.c;Middlewares\Third_Party\LwIP\src\netif\slipif.c;Middlewares\Third_Party\LwIP\src\netif\zepif.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ecp.c;Middlewares\Third_Party\LwIP\src\apps\http\httpd.c;Middlewares\Third_Party\LwIP\src\apps\http\fs.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma2d.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma2d.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_fmc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_sdram.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_ltdc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dsi.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_qspi.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\BSP\Components\lan8742\lan8742.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ccp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap_ms.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-md5.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-new.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eui64.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\fsm.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipv6cp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\lcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\magic.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\mppe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_impl.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppapi.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppcrypt.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppdebug.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppoe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppol2tp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppos.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\upap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\vj.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ecp.h;Middlewares\Third_Party\LwIP\src\apps\http\fsdata.h;Middlewares\Third_Party\LwIP\src\apps\http\httpd_structs.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Middlewares\Third_Party\LwIP\src\include\lwip\altcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\altcp_tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\altcp_tls.h;Middlewares\Third_Party\LwIP\src\include\lwip\api.h;Middlewares\Third_Party\LwIP\src\include\lwip\arch.h;Middlewares\Third_Party\LwIP\src\include\lwip\autoip.h;Middlewares\Third_Party\LwIP\src\include\lwip\debug.h;Middlewares\Third_Party\LwIP\src\include\lwip\def.h;Middlewares\Third_Party\LwIP\src\include\lwip\dhcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\dhcp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\dns.h;Middlewares\Third_Party\LwIP\src\include\lwip\err.h;Middlewares\Third_Party\LwIP\src\include\lwip\errno.h;Middlewares\Third_Party\LwIP\src\include\lwip\etharp.h;Middlewares\Third_Party\LwIP\src\include\lwip\ethip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\icmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\icmp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\if_api.h;Middlewares\Third_Party\LwIP\src\include\lwip\igmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\inet.h;Middlewares\Third_Party\LwIP\src\include\lwip\inet_chksum.h;Middlewares\Third_Party\LwIP\src\include\lwip\init.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4_frag.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_frag.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_zone.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\mem.h;Middlewares\Third_Party\LwIP\src\include\lwip\memp.h;Middlewares\Third_Party\LwIP\src\include\lwip\mld6.h;Middlewares\Third_Party\LwIP\src\include\lwip\nd6.h;Middlewares\Third_Party\LwIP\src\include\lwip\netbuf.h;Middlewares\Third_Party\LwIP\src\include\lwip\netdb.h;Middlewares\Third_Party\LwIP\src\include\lwip\netif.h;Middlewares\Third_Party\LwIP\src\include\lwip\netifapi.h;Middlewares\Third_Party\LwIP\src\include\lwip\opt.h;Middlewares\Third_Party\LwIP\src\include\lwip\pbuf.h;Middlewares\Third_Party\LwIP\src\include\lwip\raw.h;Middlewares\Third_Party\LwIP\src\include\lwip\sio.h;Middlewares\Third_Party\LwIP\src\include\lwip\snmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\sockets.h;Middlewares\Third_Party\LwIP\src\include\lwip\stats.h;Middlewares\Third_Party\LwIP\src\include\lwip\sys.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcpbase.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcpip.h;Middlewares\Third_Party\LwIP\src\include\lwip\timeouts.h;Middlewares\Third_Party\LwIP\src\include\lwip\udp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\altcp_proxyconnect.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\altcp_tls_mbedtls_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\fs.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\httpd.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\httpd_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\http_client.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\lwiperf.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\netbiosns.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\netbiosns_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\smtp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\smtp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmpv3.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_core.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_mib2.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_scalar.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_snmpv2_framework.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_snmpv2_usm.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_table.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_threadsync.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\sntp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\sntp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\tftp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\tftp_server.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\altcp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\api_msg.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\memp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\memp_std.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\mem_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\nd6_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\raw_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\sockets_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\tcpip_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\tcp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\autoip.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dhcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dhcp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dns.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\etharp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ethernet.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\iana.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\icmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\icmp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ieee.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\igmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip4.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\mld6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\nd6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\udp.h;Middlewares\Third_Party\LwIP\src\include\netif\bridgeif.h;Middlewares\Third_Party\LwIP\src\include\netif\bridgeif_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\etharp.h;Middlewares\Third_Party\LwIP\src\include\netif\ethernet.h;Middlewares\Third_Party\LwIP\src\include\netif\ieee802154.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_ble.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_common.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\slipif.h;Middlewares\Third_Party\LwIP\src\include\netif\zepif.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\netdb.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa\inet.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\net\if.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\sys\socket.h;Middlewares\Third_Party\LwIP\src\include\compat\stdc\errno.h;Middlewares\Third_Party\LwIP\system\arch\bpstruct.h;Middlewares\Third_Party\LwIP\system\arch\cc.h;Middlewares\Third_Party\LwIP\system\arch\cpu.h;Middlewares\Third_Party\LwIP\system\arch\epstruct.h;Middlewares\Third_Party\LwIP\system\arch\init.h;Middlewares\Third_Party\LwIP\system\arch\lib.h;Middlewares\Third_Party\LwIP\system\arch\perf.h;Middlewares\Third_Party\LwIP\system\arch\sys_arch.h;Middlewares\Third_Party\LwIP\src\api\api_lib.c;Middlewares\Third_Party\LwIP\src\api\api_msg.c;Middlewares\Third_Party\LwIP\src\api\err.c;Middlewares\Third_Party\LwIP\src\api\if_api.c;Middlewares\Third_Party\LwIP\src\api\netbuf.c;Middlewares\Third_Party\LwIP\src\api\netdb.c;Middlewares\Third_Party\LwIP\src\api\netifapi.c;Middlewares\Third_Party\LwIP\src\api\sockets.c;Middlewares\Third_Party\LwIP\src\api\tcpip.c;Middlewares\Third_Party\LwIP\src\core\altcp.c;Middlewares\Third_Party\LwIP\src\core\altcp_alloc.c;Middlewares\Third_Party\LwIP\src\core\altcp_tcp.c;Middlewares\Third_Party\LwIP\src\core\def.c;Middlewares\Third_Party\LwIP\src\core\dns.c;Middlewares\Third_Party\LwIP\src\core\inet_chksum.c;Middlewares\Third_Party\LwIP\src\core\init.c;Middlewares\Third_Party\LwIP\src\core\ip.c;Middlewares\Third_Party\LwIP\src\core\mem.c;Middlewares\Third_Party\LwIP\src\core\memp.c;Middlewares\Third_Party\LwIP\src\core\netif.c;Middlewares\Third_Party\LwIP\src\core\pbuf.c;Middlewares\Third_Party\LwIP\src\core\raw.c;Middlewares\Third_Party\LwIP\src\core\stats.c;Middlewares\Third_Party\LwIP\src\core\sys.c;Middlewares\Third_Party\LwIP\src\core\tcp.c;Middlewares\Third_Party\LwIP\src\core\tcp_in.c;Middlewares\Third_Party\LwIP\src\core\tcp_out.c;Middlewares\Third_Party\LwIP\src\core\timeouts.c;Middlewares\Third_Party\LwIP\src\core\udp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\autoip.c;Middlewares\Third_Party\LwIP\src\core\ipv4\dhcp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\etharp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\icmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\igmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\dhcp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ethip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\icmp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\inet6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\mld6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\nd6.c;Middlewares\Third_Party\LwIP\src\apps\mqtt\mqtt.c;Middlewares\Third_Party\LwIP\src\include\lwip\altcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\altcp_tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\altcp_tls.h;Middlewares\Third_Party\LwIP\src\include\lwip\api.h;Middlewares\Third_Party\LwIP\src\include\lwip\arch.h;Middlewares\Third_Party\LwIP\src\include\lwip\autoip.h;Middlewares\Third_Party\LwIP\src\include\lwip\debug.h;Middlewares\Third_Party\LwIP\src\include\lwip\def.h;Middlewares\Third_Party\LwIP\src\include\lwip\dhcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\dhcp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\dns.h;Middlewares\Third_Party\LwIP\src\include\lwip\err.h;Middlewares\Third_Party\LwIP\src\include\lwip\errno.h;Middlewares\Third_Party\LwIP\src\include\lwip\etharp.h;Middlewares\Third_Party\LwIP\src\include\lwip\ethip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\icmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\icmp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\if_api.h;Middlewares\Third_Party\LwIP\src\include\lwip\igmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\inet.h;Middlewares\Third_Party\LwIP\src\include\lwip\inet_chksum.h;Middlewares\Third_Party\LwIP\src\include\lwip\init.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip4_frag.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_frag.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip6_zone.h;Middlewares\Third_Party\LwIP\src\include\lwip\ip_addr.h;Middlewares\Third_Party\LwIP\src\include\lwip\mem.h;Middlewares\Third_Party\LwIP\src\include\lwip\memp.h;Middlewares\Third_Party\LwIP\src\include\lwip\mld6.h;Middlewares\Third_Party\LwIP\src\include\lwip\nd6.h;Middlewares\Third_Party\LwIP\src\include\lwip\netbuf.h;Middlewares\Third_Party\LwIP\src\include\lwip\netdb.h;Middlewares\Third_Party\LwIP\src\include\lwip\netif.h;Middlewares\Third_Party\LwIP\src\include\lwip\netifapi.h;Middlewares\Third_Party\LwIP\src\include\lwip\opt.h;Middlewares\Third_Party\LwIP\src\include\lwip\pbuf.h;Middlewares\Third_Party\LwIP\src\include\lwip\raw.h;Middlewares\Third_Party\LwIP\src\include\lwip\sio.h;Middlewares\Third_Party\LwIP\src\include\lwip\snmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\sockets.h;Middlewares\Third_Party\LwIP\src\include\lwip\stats.h;Middlewares\Third_Party\LwIP\src\include\lwip\sys.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcpbase.h;Middlewares\Third_Party\LwIP\src\include\lwip\tcpip.h;Middlewares\Third_Party\LwIP\src\include\lwip\timeouts.h;Middlewares\Third_Party\LwIP\src\include\lwip\udp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\altcp_proxyconnect.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\altcp_tls_mbedtls_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\fs.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\httpd.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\httpd_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\http_client.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\lwiperf.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mdns_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\mqtt_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\netbiosns.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\netbiosns_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\smtp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\smtp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmpv3.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_core.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_mib2.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_scalar.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_snmpv2_framework.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_snmpv2_usm.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_table.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\snmp_threadsync.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\sntp.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\sntp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\tftp_opts.h;Middlewares\Third_Party\LwIP\src\include\lwip\apps\tftp_server.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\altcp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\api_msg.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\memp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\memp_std.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\mem_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\nd6_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\raw_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\sockets_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\tcpip_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\priv\tcp_priv.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\autoip.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dhcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dhcp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\dns.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\etharp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ethernet.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\iana.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\icmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\icmp6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ieee.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\igmp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip4.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\ip6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\mld6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\nd6.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\tcp.h;Middlewares\Third_Party\LwIP\src\include\lwip\prot\udp.h;Middlewares\Third_Party\LwIP\src\include\netif\bridgeif.h;Middlewares\Third_Party\LwIP\src\include\netif\bridgeif_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\etharp.h;Middlewares\Third_Party\LwIP\src\include\netif\ethernet.h;Middlewares\Third_Party\LwIP\src\include\netif\ieee802154.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_ble.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_common.h;Middlewares\Third_Party\LwIP\src\include\netif\lowpan6_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\slipif.h;Middlewares\Third_Party\LwIP\src\include\netif\zepif.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\netdb.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa\inet.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\net\if.h;Middlewares\Third_Party\LwIP\src\include\compat\posix\sys\socket.h;Middlewares\Third_Party\LwIP\src\include\compat\stdc\errno.h;Middlewares\Third_Party\LwIP\system\arch\bpstruct.h;Middlewares\Third_Party\LwIP\system\arch\cc.h;Middlewares\Third_Party\LwIP\system\arch\cpu.h;Middlewares\Third_Party\LwIP\system\arch\epstruct.h;Middlewares\Third_Party\LwIP\system\arch\init.h;Middlewares\Third_Party\LwIP\system\arch\lib.h;Middlewares\Third_Party\LwIP\system\arch\perf.h;Middlewares\Third_Party\LwIP\system\arch\sys_arch.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dmamux.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/BSP/Components/lan8742/lan8742.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h;Middlewares/Third_Party/LwIP/src/apps/http/fsdata.h;Middlewares/Third_Party/LwIP/src/apps/http/httpd_structs.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/BSP/Components/lan8742/lan8742.c;Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c;Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c;Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c;Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c;Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c;Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c;Middlewares/Third_Party/LwIP/src/netif/ethernet.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c;Middlewares/Third_Party/LwIP/src/netif/slipif.c;Middlewares/Third_Party/LwIP/src/netif/zepif.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c;Middlewares/Third_Party/LwIP/src/apps/http/httpd.c;Middlewares/Third_Party/LwIP/src/apps/http/fs.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dmamux.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/BSP/Components/lan8742/lan8742.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h;Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h;Middlewares/Third_Party/LwIP/src/apps/http/fsdata.h;Middlewares/Third_Party/LwIP/src/apps/http/httpd_structs.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h;Middlewares/Third_Party/LwIP/src/include/lwip/api.h;Middlewares/Third_Party/LwIP/src/include/lwip/arch.h;Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h;Middlewares/Third_Party/LwIP/src/include/lwip/debug.h;Middlewares/Third_Party/LwIP/src/include/lwip/def.h;Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/dns.h;Middlewares/Third_Party/LwIP/src/include/lwip/err.h;Middlewares/Third_Party/LwIP/src/include/lwip/errno.h;Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h;Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h;Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/inet.h;Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h;Middlewares/Third_Party/LwIP/src/include/lwip/init.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/mem.h;Middlewares/Third_Party/LwIP/src/include/lwip/memp.h;Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h;Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h;Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h;Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h;Middlewares/Third_Party/LwIP/src/include/lwip/netif.h;Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h;Middlewares/Third_Party/LwIP/src/include/lwip/opt.h;Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h;Middlewares/Third_Party/LwIP/src/include/lwip/raw.h;Middlewares/Third_Party/LwIP/src/include/lwip/sio.h;Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h;Middlewares/Third_Party/LwIP/src/include/lwip/stats.h;Middlewares/Third_Party/LwIP/src/include/lwip/sys.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h;Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h;Middlewares/Third_Party/LwIP/src/include/lwip/udp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h;Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h;Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/etharp.h;Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h;Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/slipif.h;Middlewares/Third_Party/LwIP/src/include/netif/zepif.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h;Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h;Middlewares/Third_Party/LwIP/system/arch/bpstruct.h;Middlewares/Third_Party/LwIP/system/arch/cc.h;Middlewares/Third_Party/LwIP/system/arch/cpu.h;Middlewares/Third_Party/LwIP/system/arch/epstruct.h;Middlewares/Third_Party/LwIP/system/arch/init.h;Middlewares/Third_Party/LwIP/system/arch/lib.h;Middlewares/Third_Party/LwIP/system/arch/perf.h;Middlewares/Third_Party/LwIP/system/arch/sys_arch.h;Middlewares/Third_Party/LwIP/src/api/api_lib.c;Middlewares/Third_Party/LwIP/src/api/api_msg.c;Middlewares/Third_Party/LwIP/src/api/err.c;Middlewares/Third_Party/LwIP/src/api/if_api.c;Middlewares/Third_Party/LwIP/src/api/netbuf.c;Middlewares/Third_Party/LwIP/src/api/netdb.c;Middlewares/Third_Party/LwIP/src/api/netifapi.c;Middlewares/Third_Party/LwIP/src/api/sockets.c;Middlewares/Third_Party/LwIP/src/api/tcpip.c;Middlewares/Third_Party/LwIP/src/core/altcp.c;Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c;Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c;Middlewares/Third_Party/LwIP/src/core/def.c;Middlewares/Third_Party/LwIP/src/core/dns.c;Middlewares/Third_Party/LwIP/src/core/inet_chksum.c;Middlewares/Third_Party/LwIP/src/core/init.c;Middlewares/Third_Party/LwIP/src/core/ip.c;Middlewares/Third_Party/LwIP/src/core/mem.c;Middlewares/Third_Party/LwIP/src/core/memp.c;Middlewares/Third_Party/LwIP/src/core/netif.c;Middlewares/Third_Party/LwIP/src/core/pbuf.c;Middlewares/Third_Party/LwIP/src/core/raw.c;Middlewares/Third_Party/LwIP/src/core/stats.c;Middlewares/Third_Party/LwIP/src/core/sys.c;Middlewares/Third_Party/LwIP/src/core/tcp.c;Middlewares/Third_Party/LwIP/src/core/tcp_in.c;Middlewares/Third_Party/LwIP/src/core/tcp_out.c;Middlewares/Third_Party/LwIP/src/core/timeouts.c;Middlewares/Third_Party/LwIP/src/core/udp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c;Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c;Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c;Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h;Middlewares/Third_Party/LwIP/src/include/lwip/api.h;Middlewares/Third_Party/LwIP/src/include/lwip/arch.h;Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h;Middlewares/Third_Party/LwIP/src/include/lwip/debug.h;Middlewares/Third_Party/LwIP/src/include/lwip/def.h;Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/dns.h;Middlewares/Third_Party/LwIP/src/include/lwip/err.h;Middlewares/Third_Party/LwIP/src/include/lwip/errno.h;Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h;Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h;Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/inet.h;Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h;Middlewares/Third_Party/LwIP/src/include/lwip/init.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h;Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h;Middlewares/Third_Party/LwIP/src/include/lwip/mem.h;Middlewares/Third_Party/LwIP/src/include/lwip/memp.h;Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h;Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h;Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h;Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h;Middlewares/Third_Party/LwIP/src/include/lwip/netif.h;Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h;Middlewares/Third_Party/LwIP/src/include/lwip/opt.h;Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h;Middlewares/Third_Party/LwIP/src/include/lwip/raw.h;Middlewares/Third_Party/LwIP/src/include/lwip/sio.h;Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h;Middlewares/Third_Party/LwIP/src/include/lwip/stats.h;Middlewares/Third_Party/LwIP/src/include/lwip/sys.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h;Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h;Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h;Middlewares/Third_Party/LwIP/src/include/lwip/udp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h;Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h;Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h;Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h;Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/etharp.h;Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h;Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h;Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h;Middlewares/Third_Party/LwIP/src/include/netif/slipif.h;Middlewares/Third_Party/LwIP/src/include/netif/zepif.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h;Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h;Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h;Middlewares/Third_Party/LwIP/system/arch/bpstruct.h;Middlewares/Third_Party/LwIP/system/arch/cc.h;Middlewares/Third_Party/LwIP/system/arch/cpu.h;Middlewares/Third_Party/LwIP/system/arch/epstruct.h;Middlewares/Third_Party/LwIP/system/arch/init.h;Middlewares/Third_Party/LwIP/system/arch/lib.h;Middlewares/Third_Party/LwIP/system/arch/perf.h;Middlewares/Third_Party/LwIP/system/arch/sys_arch.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
 
 [PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;LWIP\App\lwip.c;LWIP\Target\ethernetif.c;Core\Src\stm32f7xx_it.c;Core\Src\stm32f7xx_hal_msp.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma2d.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_fmc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_sdram.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dsi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\BSP\Components\lan8742\lan8742.c;Middlewares\Third_Party\LwIP\src\netif\ppp\auth.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ccp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap_ms.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-md5.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-new.c;Middlewares\Third_Party\LwIP\src\netif\ppp\demand.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eui64.c;Middlewares\Third_Party\LwIP\src\netif\ppp\fsm.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipv6cp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\lcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\magic.c;Middlewares\Third_Party\LwIP\src\netif\ppp\mppe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\multilink.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ppp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppapi.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppcrypt.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppoe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppol2tp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppos.c;Middlewares\Third_Party\LwIP\src\netif\ppp\upap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\utils.c;Middlewares\Third_Party\LwIP\src\netif\ppp\vj.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif_fdb.c;Middlewares\Third_Party\LwIP\src\netif\ethernet.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_ble.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_common.c;Middlewares\Third_Party\LwIP\src\netif\slipif.c;Middlewares\Third_Party\LwIP\src\netif\zepif.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ecp.c;Middlewares\Third_Party\LwIP\src\apps\http\httpd.c;Middlewares\Third_Party\LwIP\src\apps\http\fs.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Middlewares\Third_Party\LwIP\src\api\api_lib.c;Middlewares\Third_Party\LwIP\src\api\api_msg.c;Middlewares\Third_Party\LwIP\src\api\err.c;Middlewares\Third_Party\LwIP\src\api\if_api.c;Middlewares\Third_Party\LwIP\src\api\netbuf.c;Middlewares\Third_Party\LwIP\src\api\netdb.c;Middlewares\Third_Party\LwIP\src\api\netifapi.c;Middlewares\Third_Party\LwIP\src\api\sockets.c;Middlewares\Third_Party\LwIP\src\api\tcpip.c;Middlewares\Third_Party\LwIP\src\core\altcp.c;Middlewares\Third_Party\LwIP\src\core\altcp_alloc.c;Middlewares\Third_Party\LwIP\src\core\altcp_tcp.c;Middlewares\Third_Party\LwIP\src\core\def.c;Middlewares\Third_Party\LwIP\src\core\dns.c;Middlewares\Third_Party\LwIP\src\core\inet_chksum.c;Middlewares\Third_Party\LwIP\src\core\init.c;Middlewares\Third_Party\LwIP\src\core\ip.c;Middlewares\Third_Party\LwIP\src\core\mem.c;Middlewares\Third_Party\LwIP\src\core\memp.c;Middlewares\Third_Party\LwIP\src\core\netif.c;Middlewares\Third_Party\LwIP\src\core\pbuf.c;Middlewares\Third_Party\LwIP\src\core\raw.c;Middlewares\Third_Party\LwIP\src\core\stats.c;Middlewares\Third_Party\LwIP\src\core\sys.c;Middlewares\Third_Party\LwIP\src\core\tcp.c;Middlewares\Third_Party\LwIP\src\core\tcp_in.c;Middlewares\Third_Party\LwIP\src\core\tcp_out.c;Middlewares\Third_Party\LwIP\src\core\timeouts.c;Middlewares\Third_Party\LwIP\src\core\udp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\autoip.c;Middlewares\Third_Party\LwIP\src\core\ipv4\dhcp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\etharp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\icmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\igmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\dhcp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ethip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\icmp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\inet6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\mld6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\nd6.c;Middlewares\Third_Party\LwIP\src\apps\mqtt\mqtt.c;Core\Src\system_stm32f7xx.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma2d.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_fmc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_sdram.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_ltdc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dsi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\BSP\Components\lan8742\lan8742.c;Middlewares\Third_Party\LwIP\src\netif\ppp\auth.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ccp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap_ms.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-md5.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-new.c;Middlewares\Third_Party\LwIP\src\netif\ppp\demand.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eui64.c;Middlewares\Third_Party\LwIP\src\netif\ppp\fsm.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipv6cp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\lcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\magic.c;Middlewares\Third_Party\LwIP\src\netif\ppp\mppe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\multilink.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ppp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppapi.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppcrypt.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppoe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppol2tp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppos.c;Middlewares\Third_Party\LwIP\src\netif\ppp\upap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\utils.c;Middlewares\Third_Party\LwIP\src\netif\ppp\vj.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif_fdb.c;Middlewares\Third_Party\LwIP\src\netif\ethernet.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_ble.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_common.c;Middlewares\Third_Party\LwIP\src\netif\slipif.c;Middlewares\Third_Party\LwIP\src\netif\zepif.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ecp.c;Middlewares\Third_Party\LwIP\src\apps\http\httpd.c;Middlewares\Third_Party\LwIP\src\apps\http\fs.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Middlewares\Third_Party\LwIP\src\api\api_lib.c;Middlewares\Third_Party\LwIP\src\api\api_msg.c;Middlewares\Third_Party\LwIP\src\api\err.c;Middlewares\Third_Party\LwIP\src\api\if_api.c;Middlewares\Third_Party\LwIP\src\api\netbuf.c;Middlewares\Third_Party\LwIP\src\api\netdb.c;Middlewares\Third_Party\LwIP\src\api\netifapi.c;Middlewares\Third_Party\LwIP\src\api\sockets.c;Middlewares\Third_Party\LwIP\src\api\tcpip.c;Middlewares\Third_Party\LwIP\src\core\altcp.c;Middlewares\Third_Party\LwIP\src\core\altcp_alloc.c;Middlewares\Third_Party\LwIP\src\core\altcp_tcp.c;Middlewares\Third_Party\LwIP\src\core\def.c;Middlewares\Third_Party\LwIP\src\core\dns.c;Middlewares\Third_Party\LwIP\src\core\inet_chksum.c;Middlewares\Third_Party\LwIP\src\core\init.c;Middlewares\Third_Party\LwIP\src\core\ip.c;Middlewares\Third_Party\LwIP\src\core\mem.c;Middlewares\Third_Party\LwIP\src\core\memp.c;Middlewares\Third_Party\LwIP\src\core\netif.c;Middlewares\Third_Party\LwIP\src\core\pbuf.c;Middlewares\Third_Party\LwIP\src\core\raw.c;Middlewares\Third_Party\LwIP\src\core\stats.c;Middlewares\Third_Party\LwIP\src\core\sys.c;Middlewares\Third_Party\LwIP\src\core\tcp.c;Middlewares\Third_Party\LwIP\src\core\tcp_in.c;Middlewares\Third_Party\LwIP\src\core\tcp_out.c;Middlewares\Third_Party\LwIP\src\core\timeouts.c;Middlewares\Third_Party\LwIP\src\core\udp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\autoip.c;Middlewares\Third_Party\LwIP\src\core\ipv4\dhcp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\etharp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\icmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\igmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\dhcp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ethip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\icmp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\inet6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\mld6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\nd6.c;Middlewares\Third_Party\LwIP\src\apps\mqtt\mqtt.c;Core\Src\system_stm32f7xx.c;;;Middlewares\Third_Party\LwIP\src\netif\ppp\auth.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ccp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap_ms.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-md5.c;Middlewares\Third_Party\LwIP\src\netif\ppp\chap-new.c;Middlewares\Third_Party\LwIP\src\netif\ppp\demand.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\eui64.c;Middlewares\Third_Party\LwIP\src\netif\ppp\fsm.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ipv6cp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\lcp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\magic.c;Middlewares\Third_Party\LwIP\src\netif\ppp\mppe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\multilink.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ppp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppapi.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppcrypt.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppoe.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppol2tp.c;Middlewares\Third_Party\LwIP\src\netif\ppp\pppos.c;Middlewares\Third_Party\LwIP\src\netif\ppp\upap.c;Middlewares\Third_Party\LwIP\src\netif\ppp\utils.c;Middlewares\Third_Party\LwIP\src\netif\ppp\vj.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif.c;Middlewares\Third_Party\LwIP\src\netif\bridgeif_fdb.c;Middlewares\Third_Party\LwIP\src\netif\ethernet.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_ble.c;Middlewares\Third_Party\LwIP\src\netif\lowpan6_common.c;Middlewares\Third_Party\LwIP\src\netif\slipif.c;Middlewares\Third_Party\LwIP\src\netif\zepif.c;Middlewares\Third_Party\LwIP\src\netif\ppp\ecp.c;Middlewares\Third_Party\LwIP\src\apps\http\httpd.c;Middlewares\Third_Party\LwIP\src\apps\http\fs.c;Middlewares\Third_Party\LwIP\src\api\api_lib.c;Middlewares\Third_Party\LwIP\src\api\api_msg.c;Middlewares\Third_Party\LwIP\src\api\err.c;Middlewares\Third_Party\LwIP\src\api\if_api.c;Middlewares\Third_Party\LwIP\src\api\netbuf.c;Middlewares\Third_Party\LwIP\src\api\netdb.c;Middlewares\Third_Party\LwIP\src\api\netifapi.c;Middlewares\Third_Party\LwIP\src\api\sockets.c;Middlewares\Third_Party\LwIP\src\api\tcpip.c;Middlewares\Third_Party\LwIP\src\core\altcp.c;Middlewares\Third_Party\LwIP\src\core\altcp_alloc.c;Middlewares\Third_Party\LwIP\src\core\altcp_tcp.c;Middlewares\Third_Party\LwIP\src\core\def.c;Middlewares\Third_Party\LwIP\src\core\dns.c;Middlewares\Third_Party\LwIP\src\core\inet_chksum.c;Middlewares\Third_Party\LwIP\src\core\init.c;Middlewares\Third_Party\LwIP\src\core\ip.c;Middlewares\Third_Party\LwIP\src\core\mem.c;Middlewares\Third_Party\LwIP\src\core\memp.c;Middlewares\Third_Party\LwIP\src\core\netif.c;Middlewares\Third_Party\LwIP\src\core\pbuf.c;Middlewares\Third_Party\LwIP\src\core\raw.c;Middlewares\Third_Party\LwIP\src\core\stats.c;Middlewares\Third_Party\LwIP\src\core\sys.c;Middlewares\Third_Party\LwIP\src\core\tcp.c;Middlewares\Third_Party\LwIP\src\core\tcp_in.c;Middlewares\Third_Party\LwIP\src\core\tcp_out.c;Middlewares\Third_Party\LwIP\src\core\timeouts.c;Middlewares\Third_Party\LwIP\src\core\udp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\autoip.c;Middlewares\Third_Party\LwIP\src\core\ipv4\dhcp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\etharp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\icmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\igmp.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv4\ip4_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\dhcp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ethip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\icmp6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\inet6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_addr.c;Middlewares\Third_Party\LwIP\src\core\ipv6\ip6_frag.c;Middlewares\Third_Party\LwIP\src\core\ipv6\mld6.c;Middlewares\Third_Party\LwIP\src\core\ipv6\nd6.c;Middlewares\Third_Party\LwIP\src\apps\mqtt\mqtt.c;
-HeaderPath=Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Drivers\STM32F7xx_HAL_Driver\Inc;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;Drivers\BSP\Components\lan8742;Middlewares\Third_Party\LwIP\src\include\netif\ppp;Middlewares\Third_Party\LwIP\src\apps\http;Drivers\CMSIS\Device\ST\STM32F7xx\Include;Middlewares\Third_Party\LwIP\src\include\lwip;Middlewares\Third_Party\LwIP\src\include\lwip\apps;Middlewares\Third_Party\LwIP\src\include\lwip\priv;Middlewares\Third_Party\LwIP\src\include\lwip\prot;Middlewares\Third_Party\LwIP\src\include\netif;Middlewares\Third_Party\LwIP\src\include\compat\posix;Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa;Middlewares\Third_Party\LwIP\src\include\compat\posix\net;Middlewares\Third_Party\LwIP\src\include\compat\posix\sys;Middlewares\Third_Party\LwIP\src\include\compat\stdc;Middlewares\Third_Party\LwIP\system\arch;Drivers\CMSIS\Include;LWIP\App;LWIP\Target;Core\Inc;
+SourceFiles=Core/Src/main.c;LWIP/App/lwip.c;LWIP/Target/ethernetif.c;Core/Src/stm32f7xx_it.c;Core/Src/stm32f7xx_hal_msp.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/BSP/Components/lan8742/lan8742.c;Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c;Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c;Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c;Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c;Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c;Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c;Middlewares/Third_Party/LwIP/src/netif/ethernet.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c;Middlewares/Third_Party/LwIP/src/netif/slipif.c;Middlewares/Third_Party/LwIP/src/netif/zepif.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c;Middlewares/Third_Party/LwIP/src/apps/http/httpd.c;Middlewares/Third_Party/LwIP/src/apps/http/fs.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Middlewares/Third_Party/LwIP/src/api/api_lib.c;Middlewares/Third_Party/LwIP/src/api/api_msg.c;Middlewares/Third_Party/LwIP/src/api/err.c;Middlewares/Third_Party/LwIP/src/api/if_api.c;Middlewares/Third_Party/LwIP/src/api/netbuf.c;Middlewares/Third_Party/LwIP/src/api/netdb.c;Middlewares/Third_Party/LwIP/src/api/netifapi.c;Middlewares/Third_Party/LwIP/src/api/sockets.c;Middlewares/Third_Party/LwIP/src/api/tcpip.c;Middlewares/Third_Party/LwIP/src/core/altcp.c;Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c;Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c;Middlewares/Third_Party/LwIP/src/core/def.c;Middlewares/Third_Party/LwIP/src/core/dns.c;Middlewares/Third_Party/LwIP/src/core/inet_chksum.c;Middlewares/Third_Party/LwIP/src/core/init.c;Middlewares/Third_Party/LwIP/src/core/ip.c;Middlewares/Third_Party/LwIP/src/core/mem.c;Middlewares/Third_Party/LwIP/src/core/memp.c;Middlewares/Third_Party/LwIP/src/core/netif.c;Middlewares/Third_Party/LwIP/src/core/pbuf.c;Middlewares/Third_Party/LwIP/src/core/raw.c;Middlewares/Third_Party/LwIP/src/core/stats.c;Middlewares/Third_Party/LwIP/src/core/sys.c;Middlewares/Third_Party/LwIP/src/core/tcp.c;Middlewares/Third_Party/LwIP/src/core/tcp_in.c;Middlewares/Third_Party/LwIP/src/core/tcp_out.c;Middlewares/Third_Party/LwIP/src/core/timeouts.c;Middlewares/Third_Party/LwIP/src/core/udp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c;Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c;Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c;Core/Src/system_stm32f7xx.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/BSP/Components/lan8742/lan8742.c;Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c;Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c;Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c;Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c;Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c;Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c;Middlewares/Third_Party/LwIP/src/netif/ethernet.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c;Middlewares/Third_Party/LwIP/src/netif/slipif.c;Middlewares/Third_Party/LwIP/src/netif/zepif.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c;Middlewares/Third_Party/LwIP/src/apps/http/httpd.c;Middlewares/Third_Party/LwIP/src/apps/http/fs.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Middlewares/Third_Party/LwIP/src/api/api_lib.c;Middlewares/Third_Party/LwIP/src/api/api_msg.c;Middlewares/Third_Party/LwIP/src/api/err.c;Middlewares/Third_Party/LwIP/src/api/if_api.c;Middlewares/Third_Party/LwIP/src/api/netbuf.c;Middlewares/Third_Party/LwIP/src/api/netdb.c;Middlewares/Third_Party/LwIP/src/api/netifapi.c;Middlewares/Third_Party/LwIP/src/api/sockets.c;Middlewares/Third_Party/LwIP/src/api/tcpip.c;Middlewares/Third_Party/LwIP/src/core/altcp.c;Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c;Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c;Middlewares/Third_Party/LwIP/src/core/def.c;Middlewares/Third_Party/LwIP/src/core/dns.c;Middlewares/Third_Party/LwIP/src/core/inet_chksum.c;Middlewares/Third_Party/LwIP/src/core/init.c;Middlewares/Third_Party/LwIP/src/core/ip.c;Middlewares/Third_Party/LwIP/src/core/mem.c;Middlewares/Third_Party/LwIP/src/core/memp.c;Middlewares/Third_Party/LwIP/src/core/netif.c;Middlewares/Third_Party/LwIP/src/core/pbuf.c;Middlewares/Third_Party/LwIP/src/core/raw.c;Middlewares/Third_Party/LwIP/src/core/stats.c;Middlewares/Third_Party/LwIP/src/core/sys.c;Middlewares/Third_Party/LwIP/src/core/tcp.c;Middlewares/Third_Party/LwIP/src/core/tcp_in.c;Middlewares/Third_Party/LwIP/src/core/tcp_out.c;Middlewares/Third_Party/LwIP/src/core/timeouts.c;Middlewares/Third_Party/LwIP/src/core/udp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c;Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c;Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c;Core/Src/system_stm32f7xx.c;;;Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c;Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c;Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c;Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c;Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c;Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c;Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c;Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c;Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif.c;Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c;Middlewares/Third_Party/LwIP/src/netif/ethernet.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c;Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c;Middlewares/Third_Party/LwIP/src/netif/slipif.c;Middlewares/Third_Party/LwIP/src/netif/zepif.c;Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c;Middlewares/Third_Party/LwIP/src/apps/http/httpd.c;Middlewares/Third_Party/LwIP/src/apps/http/fs.c;Middlewares/Third_Party/LwIP/src/api/api_lib.c;Middlewares/Third_Party/LwIP/src/api/api_msg.c;Middlewares/Third_Party/LwIP/src/api/err.c;Middlewares/Third_Party/LwIP/src/api/if_api.c;Middlewares/Third_Party/LwIP/src/api/netbuf.c;Middlewares/Third_Party/LwIP/src/api/netdb.c;Middlewares/Third_Party/LwIP/src/api/netifapi.c;Middlewares/Third_Party/LwIP/src/api/sockets.c;Middlewares/Third_Party/LwIP/src/api/tcpip.c;Middlewares/Third_Party/LwIP/src/core/altcp.c;Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c;Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c;Middlewares/Third_Party/LwIP/src/core/def.c;Middlewares/Third_Party/LwIP/src/core/dns.c;Middlewares/Third_Party/LwIP/src/core/inet_chksum.c;Middlewares/Third_Party/LwIP/src/core/init.c;Middlewares/Third_Party/LwIP/src/core/ip.c;Middlewares/Third_Party/LwIP/src/core/mem.c;Middlewares/Third_Party/LwIP/src/core/memp.c;Middlewares/Third_Party/LwIP/src/core/netif.c;Middlewares/Third_Party/LwIP/src/core/pbuf.c;Middlewares/Third_Party/LwIP/src/core/raw.c;Middlewares/Third_Party/LwIP/src/core/stats.c;Middlewares/Third_Party/LwIP/src/core/sys.c;Middlewares/Third_Party/LwIP/src/core/tcp.c;Middlewares/Third_Party/LwIP/src/core/tcp_in.c;Middlewares/Third_Party/LwIP/src/core/tcp_out.c;Middlewares/Third_Party/LwIP/src/core/timeouts.c;Middlewares/Third_Party/LwIP/src/core/udp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c;Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c;Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c;Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c;Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c;Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c;
+HeaderPath=Middlewares/Third_Party/LwIP/src/include;Middlewares/Third_Party/LwIP/system;Middlewares/Third_Party/LwIP/src/include;Middlewares/Third_Party/LwIP/system;Drivers/STM32F7xx_HAL_Driver/Inc;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;Drivers/BSP/Components/lan8742;Middlewares/Third_Party/LwIP/src/include/netif/ppp;Middlewares/Third_Party/LwIP/src/apps/http;Drivers/CMSIS/Device/ST/STM32F7xx/Include;Middlewares/Third_Party/LwIP/src/include/lwip;Middlewares/Third_Party/LwIP/src/include/lwip/apps;Middlewares/Third_Party/LwIP/src/include/lwip/priv;Middlewares/Third_Party/LwIP/src/include/lwip/prot;Middlewares/Third_Party/LwIP/src/include/netif;Middlewares/Third_Party/LwIP/src/include/compat/posix;Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa;Middlewares/Third_Party/LwIP/src/include/compat/posix/net;Middlewares/Third_Party/LwIP/src/include/compat/posix/sys;Middlewares/Third_Party/LwIP/src/include/compat/stdc;Middlewares/Third_Party/LwIP/system/arch;Drivers/CMSIS/Include;LWIP/App;LWIP/Target;Core/Inc;
 CDefines=USE_HAL_DRIVER;STM32F746xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
 [PreviousGenFiles]
 AdvancedFolderStructure=true
 HeaderFileListSize=6
-HeaderFiles#0=..\LWIP\App\lwip.h
-HeaderFiles#1=..\LWIP\Target\lwipopts.h
-HeaderFiles#2=..\LWIP\Target\ethernetif.h
-HeaderFiles#3=..\Core\Inc\stm32f7xx_it.h
-HeaderFiles#4=..\Core\Inc\stm32f7xx_hal_conf.h
-HeaderFiles#5=..\Core\Inc\main.h
+HeaderFiles#0=../LWIP/App/lwip.h
+HeaderFiles#1=../LWIP/Target/lwipopts.h
+HeaderFiles#2=../LWIP/Target/ethernetif.h
+HeaderFiles#3=../Core/Inc/stm32f7xx_it.h
+HeaderFiles#4=../Core/Inc/stm32f7xx_hal_conf.h
+HeaderFiles#5=../Core/Inc/main.h
 HeaderFolderListSize=3
-HeaderPath#0=..\LWIP\App
-HeaderPath#1=..\LWIP\Target
-HeaderPath#2=..\Core\Inc
+HeaderPath#0=../LWIP/App
+HeaderPath#1=../LWIP/Target
+HeaderPath#2=../Core/Inc
 HeaderFiles=;
 SourceFileListSize=5
-SourceFiles#0=..\LWIP\App\lwip.c
-SourceFiles#1=..\LWIP\Target\ethernetif.c
-SourceFiles#2=..\Core\Src\stm32f7xx_it.c
-SourceFiles#3=..\Core\Src\stm32f7xx_hal_msp.c
-SourceFiles#4=..\Core\Src\main.c
+SourceFiles#0=../LWIP/App/lwip.c
+SourceFiles#1=../LWIP/Target/ethernetif.c
+SourceFiles#2=../Core/Src/stm32f7xx_it.c
+SourceFiles#3=../Core/Src/stm32f7xx_hal_msp.c
+SourceFiles#4=../Core/Src/main.c
 SourceFolderListSize=3
-SourcePath#0=..\LWIP\App
-SourcePath#1=..\LWIP\Target
-SourcePath#2=..\Core\Src
+SourcePath#0=../LWIP/App
+SourcePath#1=../LWIP/Target
+SourcePath#2=../Core/Src
 SourceFiles=;
 
diff --git a/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h
index 3c90ad3..6c42094 100644
--- a/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h
+++ b/project/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h
@@ -1,750 +1,750 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_qspi.h
-  * @author  MCD Application Team
-  * @brief   Header file of QSPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F7xx_HAL_QSPI_H
-#define STM32F7xx_HAL_QSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-#if defined(QUADSPI)
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup QSPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Types QSPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  QSPI Init structure definition
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
-                                  This parameter can be a number between 0 and 255 */
-  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
-                                  This parameter can be a value between 1 and 32 */
-  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
-                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
-                                  This parameter can be a value of @ref QSPI_SampleShifting */
-  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
-                                  required to address the flash memory. The flash capacity can be up to 4GB
-                                  (addressed using 32 bits) in indirect mode, but the addressable space in
-                                  memory-mapped mode is limited to 256MB
-                                  This parameter can be a number between 0 and 31 */
-  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
-                                  of clock cycles which the chip select must remain high between commands.
-                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
-                                  This parameter can be a value of @ref QSPI_ClockMode */
-  uint32_t FlashID;            /* Specifies the Flash which will be used,
-                                  This parameter can be a value of @ref QSPI_Flash_Select */
-  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
-                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */
-}QSPI_InitTypeDef;
-
-/**
-  * @brief HAL QSPI State structures definition
-  */
-typedef enum
-{
-  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
-  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
-  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
-  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
-  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
-  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
-  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
-  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
-  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
-}HAL_QSPI_StateTypeDef;
-
-/**
-  * @brief  QSPI Handle Structure definition
-  */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-typedef struct __QSPI_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
-  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
-  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
-  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
-  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
-  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
-  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
-  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
-  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
-  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
-  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
-  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
-  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
-  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
-  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
-  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
-  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
-  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
-  void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
-  void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
-  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
-  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
-
-  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
-  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
-#endif
-}QSPI_HandleTypeDef;
-
-/**
-  * @brief  QSPI Command structure definition
-  */
-typedef struct
-{
-  uint32_t Instruction;        /* Specifies the Instruction to be sent
-                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
-  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
-  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
-                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
-  uint32_t AddressSize;        /* Specifies the Address Size
-                                  This parameter can be a value of @ref QSPI_AddressSize */
-  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
-                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
-  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
-                                  This parameter can be a number between 0 and 31 */
-  uint32_t InstructionMode;    /* Specifies the Instruction Mode
-                                  This parameter can be a value of @ref QSPI_InstructionMode */
-  uint32_t AddressMode;        /* Specifies the Address Mode
-                                  This parameter can be a value of @ref QSPI_AddressMode */
-  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
-                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
-  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
-                                  This parameter can be a value of @ref QSPI_DataMode */
-  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
-                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
-                                  until end of memory)*/
-  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
-                                  This parameter can be a value of @ref QSPI_DdrMode */
-  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data
-                                  output by one half of system clock in DDR mode.
-                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
-  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
-                                  This parameter can be a value of @ref QSPI_SIOOMode */
-}QSPI_CommandTypeDef;
-
-/**
-  * @brief  QSPI Auto Polling mode configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */
-  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
-                                  This parameter can be any value between 0 and 0xFFFFFFFF */
-  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
-                                  This parameter can be any value between 0 and 0xFFFF */
-  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
-                                  This parameter can be any value between 1 and 4 */
-  uint32_t MatchMode;          /* Specifies the method used for determining a match.
-                                  This parameter can be a value of @ref QSPI_MatchMode */
-  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
-                                  This parameter can be a value of @ref QSPI_AutomaticStop */
-}QSPI_AutoPollingTypeDef;
-
-/**
-  * @brief  QSPI Memory Mapped mode configuration structure definition
-  */
-typedef struct
-{
-  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
-                                  This parameter can be any value between 0 and 0xFFFF */
-  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
-                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
-}QSPI_MemoryMappedTypeDef;
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL QSPI Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
-  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
-  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
-  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
-  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
-  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
-  HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */
-  HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */
-  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
-  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
-
-  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
-  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
-}HAL_QSPI_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL QSPI Callback pointer definition
-  */
-typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
-#endif
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
-  * @{
-  */
-
-/** @defgroup QSPI_ErrorCode QSPI Error Code
-  * @{
-  */
-#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
-#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
-#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
-#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
-#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
-  * @{
-  */
-#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/
-#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
-  * @{
-  */
-#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/
-#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_ClockMode QSPI Clock Mode
-  * @{
-  */
-#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/
-#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Flash_Select QSPI Flash Select
-  * @{
-  */
-#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/
-#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
-/**
-  * @}
-  */
-
-  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
-  * @{
-  */
-#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
-#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AddressSize QSPI Address Size
-  * @{
-  */
-#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/
-#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
-#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
-#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
-  * @{
-  */
-#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
-* @{
-*/
-#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/
-#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
-#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
-#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AddressMode QSPI Address Mode
-* @{
-*/
-#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/
-#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
-#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
-#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
-* @{
-*/
-#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/
-#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
-#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
-#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_DataMode QSPI Data Mode
-  * @{
-  */
-#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/
-#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
-#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
-#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_DdrMode QSPI DDR Mode
-  * @{
-  */
-#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/
-#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
-  * @{
-  */
-#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/
-#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
-  * @{
-  */
-#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/
-#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_MatchMode QSPI Match Mode
-  * @{
-  */
-#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/
-#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
-  * @{
-  */
-#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/
-#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
-  * @{
-  */
-#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/
-#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Flags QSPI Flags
-  * @{
-  */
-#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
-#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
-#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
-#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
-#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
-#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Interrupts QSPI Interrupts
-  * @{
-  */
-#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
-#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
-#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
-#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
-#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
-  * @brief QSPI Timeout definition
-  * @{
-  */
-#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
-  * @{
-  */
-/** @brief Reset QSPI handle state.
-  * @param  __HANDLE__ QSPI handle.
-  * @retval None
-  */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
-                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
-                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
-                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                               } while(0)
-#else
-#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
-#endif
-
-/** @brief  Enable the QSPI peripheral.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @retval None
-  */
-#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief  Disable the QSPI peripheral.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @retval None
-  */
-#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief  Enable the specified QSPI interrupt.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval None
-  */
-#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-
-/** @brief  Disable the specified QSPI interrupt.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval None
-  */
-#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
-  *            @arg QSPI_IT_SM: QSPI Status match interrupt
-  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
-  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
-  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the selected QSPI flag is set or not.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @param  __FLAG__ specifies the QSPI flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
-  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
-  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
-  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
-  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
-  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
-  * @retval None
-  */
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
-
-/** @brief  Clears the specified QSPI's flag status.
-  * @param  __HANDLE__ specifies the QSPI Handle.
-  * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set
-  *          This parameter can be one of the following values:
-  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
-  *            @arg QSPI_FLAG_SM: QSPI Status match flag
-  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
-  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
-  * @retval None
-  */
-#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup QSPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup QSPI_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
-/**
-  * @}
-  */
-
-/** @addtogroup QSPI_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-/* QSPI IRQ handler method */
-void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
-HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-
-/* QSPI status flag polling mode */
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
-
-/* QSPI memory-mapped mode */
-HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-
-/* Callback functions in non-blocking modes ***********************************/
-void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI status flag polling mode */
-void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI memory-mapped mode */
-void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/* QSPI callback registering/unregistering */
-HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup QSPI_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
-uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
-  * @{
-  */
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
-
-#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 32U))
-
-#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
-                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
-                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
-                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \
-                                            ((FLASH_ID) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
-                                            ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
-                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
-                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
-                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
-                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
-                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
-                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
-                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
-                                            ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
-                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
-                                            ((MODE) == QSPI_DATA_1_LINE)  || \
-                                            ((MODE) == QSPI_DATA_2_LINES) || \
-                                            ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
-                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
-                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
-                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
-
-#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
-                                            ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
-                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
-                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
-
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
-/**
-* @}
-*/
-/* End of private macros -----------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(QUADSPI) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F7xx_HAL_QSPI_H */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_qspi.h
+  * @author  MCD Application Team
+  * @brief   Header file of QSPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_QSPI_H
+#define STM32F7xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+#if defined(QUADSPI)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup QSPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  QSPI Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
+                                  This parameter can be a number between 0 and 255 */
+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+                                  This parameter can be a value between 1 and 32 */
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+                                  This parameter can be a value of @ref QSPI_SampleShifting */
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+                                  required to address the flash memory. The flash capacity can be up to 4GB
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in
+                                  memory-mapped mode is limited to 256MB
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+                                  of clock cycles which the chip select must remain high between commands.
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+                                  This parameter can be a value of @ref QSPI_ClockMode */
+  uint32_t FlashID;            /* Specifies the Flash which will be used,
+                                  This parameter can be a value of @ref QSPI_Flash_Select */
+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */
+}QSPI_InitTypeDef;
+
+/**
+  * @brief HAL QSPI State structures definition
+  */
+typedef enum
+{
+  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
+  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
+  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
+  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
+}HAL_QSPI_StateTypeDef;
+
+/**
+  * @brief  QSPI Handle Structure definition
+  */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+typedef struct __QSPI_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
+  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
+  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
+  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
+  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
+  void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
+  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+
+  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
+#endif
+}QSPI_HandleTypeDef;
+
+/**
+  * @brief  QSPI Command structure definition
+  */
+typedef struct
+{
+  uint32_t Instruction;        /* Specifies the Instruction to be sent
+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AddressSize;        /* Specifies the Address Size
+                                  This parameter can be a value of @ref QSPI_AddressSize */
+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t InstructionMode;    /* Specifies the Instruction Mode
+                                  This parameter can be a value of @ref QSPI_InstructionMode */
+  uint32_t AddressMode;        /* Specifies the Address Mode
+                                  This parameter can be a value of @ref QSPI_AddressMode */
+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
+                                  This parameter can be a value of @ref QSPI_DataMode */
+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
+                                  until end of memory)*/
+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
+                                  This parameter can be a value of @ref QSPI_DdrMode */
+  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data
+                                  output by one half of system clock in DDR mode.
+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
+                                  This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/**
+  * @brief  QSPI Auto Polling mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
+                                  This parameter can be any value between 1 and 4 */
+  uint32_t MatchMode;          /* Specifies the method used for determining a match.
+                                  This parameter can be a value of @ref QSPI_MatchMode */
+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
+                                  This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+
+/**
+  * @brief  QSPI Memory Mapped mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL QSPI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
+  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
+  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
+  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
+  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
+  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
+  HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */
+  HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */
+  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
+  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
+
+  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
+  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
+}HAL_QSPI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL QSPI Callback pointer definition
+  */
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
+#endif
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+  * @{
+  */
+
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+  * @{
+  */
+#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
+#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
+#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
+#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
+#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+  * @{
+  */
+#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
+  * @{
+  */
+#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+  * @{
+  */
+#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+  * @{
+  */
+#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
+/**
+  * @}
+  */
+
+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+  * @{
+  */
+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+  * @{
+  */
+#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+  * @{
+  */
+#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/
+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+  * @{
+  */
+#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/
+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
+  * @{
+  */
+#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
+  * @{
+  */
+#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
+  * @{
+  */
+#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+  * @{
+  */
+#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+  * @{
+  */
+#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
+  * @{
+  */
+#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Flags QSPI Flags
+  * @{
+  */
+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+  * @{
+  */
+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+  * @brief QSPI Timeout definition
+  * @{
+  */
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+  * @{
+  */
+/** @brief Reset QSPI handle state.
+  * @param  __HANDLE__ QSPI handle.
+  * @retval None
+  */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                               } while(0)
+#else
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+#endif
+
+/** @brief  Enable the QSPI peripheral.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Disable the QSPI peripheral.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Enable the specified QSPI interrupt.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief  Disable the specified QSPI interrupt.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected QSPI flag is set or not.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
+
+/** @brief  Clears the specified QSPI's flag status.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM: QSPI Status match flag
+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup QSPI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+  * @}
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/* QSPI callback registering/unregistering */
+HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+  * @{
+  */
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 32U))
+
+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \
+                                            ((FLASH_ID) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
+                                            ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
+                                            ((MODE) == QSPI_DATA_1_LINE)  || \
+                                            ((MODE) == QSPI_DATA_2_LINES) || \
+                                            ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
+                                            ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
+/**
+* @}
+*/
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(QUADSPI) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_HAL_QSPI_H */
diff --git a/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c
index 7d3dade..787aea7 100644
--- a/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c
+++ b/project/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c
@@ -1,2840 +1,2840 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_qspi.c
-  * @author  MCD Application Team
-  * @brief   QSPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the QuadSPI interface (QSPI).
-  *           + Initialization and de-initialization functions
-  *           + Indirect functional mode management
-  *           + Memory-mapped functional mode management
-  *           + Auto-polling functional mode management
-  *           + Interrupts and flags management
-  *           + DMA channel configuration for indirect functional mode
-  *           + Errors management and abort functionality
-  *
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
- ===============================================================================
-                        ##### How to use this driver #####
- ===============================================================================
-  [..]
-    *** Initialization ***
-    ======================
-    [..]
-      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
-        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
-        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
-        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
-        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
-        (++) If interrupt mode is used, enable and configure QuadSPI global
-            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
-        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
-            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
-            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
-            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
-      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
-          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
-
-    *** Indirect functional mode ***
-    ================================
-    [..]
-      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
-          functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and if present the size and the address value.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used and if present the number of bytes.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-      (#) If no data is required for the command, it is sent directly to the memory :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
-      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
-          HAL_QSPI_Transmit_IT() after the command configuration :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
-             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
-         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
-             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
-      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
-          HAL_QSPI_Receive_IT() after the command configuration :
-         (++) In polling mode, the output of the function is done when the transfer is complete.
-         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
-             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
-             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-
-    *** Auto-polling functional mode ***
-    ====================================
-    [..]
-      (#) Configure the command sequence and the auto-polling functional mode using the
-          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and if present the size and the address value.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
-             the polling interval and the automatic stop activation.
-      (#) After the configuration :
-         (++) In polling mode, the output of the function is done when the status match is reached. The
-             automatic stop is activated to avoid an infinite loop.
-         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
-
-    *** Memory-mapped functional mode ***
-    =====================================
-    [..]
-      (#) Configure the command sequence and the memory-mapped functional mode using the
-          HAL_QSPI_MemoryMapped() functions :
-         (++) Instruction phase : the mode used and if present the instruction opcode.
-         (++) Address phase : the mode used and the size.
-         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
-             bytes values.
-         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (++) Data phase : the mode used.
-         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
-             if activated.
-         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (++) The timeout activation and the timeout period.
-      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
-          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
-
-    *** Errors management and abort functionality ***
-    =================================================
-    [..]
-      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
-      (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
-          flushes the fifo :
-         (++) In polling mode, the output of the function is done when the transfer
-              complete bit is set and the busy bit cleared.
-         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
-              the transfer complete bit is set.
-
-    *** Control functions ***
-    =========================
-    [..]
-      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
-      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
-      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
-      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
-      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
-
-    *** Callback registration ***
-    =============================================
-    [..]
-      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-      Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
-      it allows to register following callbacks:
-        (+) ErrorCallback : callback when error occurs.
-        (+) AbortCpltCallback : callback when abort is completed.
-        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
-        (+) CmdCpltCallback : callback when a command without data is completed.
-        (+) RxCpltCallback : callback when a reception transfer is completed.
-        (+) TxCpltCallback : callback when a transmission transfer is completed.
-        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
-        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
-        (+) StatusMatchCallback : callback when a status match occurs.
-        (+) TimeOutCallback : callback when the timeout perioed expires.
-        (+) MspInitCallback    : QSPI MspInit.
-        (+) MspDeInitCallback  : QSPI MspDeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-      Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
-        (+) ErrorCallback : callback when error occurs.
-        (+) AbortCpltCallback : callback when abort is completed.
-        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
-        (+) CmdCpltCallback : callback when a command without data is completed.
-        (+) RxCpltCallback : callback when a reception transfer is completed.
-        (+) TxCpltCallback : callback when a transmission transfer is completed.
-        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
-        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
-        (+) StatusMatchCallback : callback when a status match occurs.
-        (+) TimeOutCallback : callback when the timeout perioed expires.
-        (+) MspInitCallback    : QSPI MspInit.
-        (+) MspDeInitCallback  : QSPI MspDeInit.
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-      By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-      Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
-      and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-      Callbacks can be registered/unregistered in READY state only.
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-      during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
-      or HAL_QSPI_Init function.
-
-      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
-
-    *** Workarounds linked to Silicon Limitation ***
-    ====================================================
-    [..]
-      (#) Workarounds Implemented inside HAL Driver
-         (++) Extra data written in the FIFO at the end of a read transfer
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-#if defined(QUADSPI)
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup QSPI QSPI
-  * @brief QSPI HAL module driver
-  * @{
-  */
-#ifdef HAL_QSPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-
-/* Private define ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Constants QSPI Private Constants
-  * @{
-  */
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
-#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
-#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
-  * @{
-  */
-#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
-                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
-  * @{
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Initialize the QuadSPI.
-      (+) De-initialize the QuadSPI.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initialize the QSPI mode according to the specified parameters
-  *        in the QSPI_InitTypeDef and initialize the associated handle.
-  * @param hqspi QSPI handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
-{
-  HAL_StatusTypeDef status;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the QSPI handle allocation */
-  if(hqspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
-  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
-  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
-  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
-  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
-  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
-  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
-  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
-
-  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
-  {
-    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
-  }
-
-  if(hqspi->State == HAL_QSPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hqspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-    /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
-    hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
-    hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
-    hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
-    hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
-    hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
-    hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
-    hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;
-    hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;
-    hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
-    hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
-
-    if(hqspi->MspInitCallback == NULL)
-    {
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hqspi->MspInitCallback(hqspi);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_QSPI_MspInit(hqspi);
-#endif
-
-    /* Configure the default timeout for the QSPI memory access */
-    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
-  }
-
-  /* Configure QSPI FIFO Threshold */
-  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
-             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
-
-  /* Wait till BUSY flag reset */
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
-  if(status == HAL_OK)
-  {
-    /* Configure QSPI Clock Prescaler and Sample Shift */
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
-               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
-                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
-
-    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
-    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
-               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
-                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
-    /* Enable the QSPI peripheral */
-    __HAL_QSPI_ENABLE(hqspi);
-
-    /* Set QSPI error code to none */
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Initialize the QSPI state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief De-Initialize the QSPI peripheral.
-  * @param hqspi QSPI handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Check the QSPI handle allocation */
-  if(hqspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Disable the QSPI Peripheral Clock */
-  __HAL_QSPI_DISABLE(hqspi);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-  if(hqspi->MspDeInitCallback == NULL)
-  {
-    hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
-  }
-
-  /* DeInit the low level hardware */
-  hqspi->MspDeInitCallback(hqspi);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_QSPI_MspDeInit(hqspi);
-#endif
-
-  /* Set QSPI error code to none */
-  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-  /* Initialize the QSPI state */
-  hqspi->State = HAL_QSPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Initialize the QSPI MSP.
-  * @param hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief DeInitialize the QSPI MSP.
-  * @param hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_MspDeInit can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief QSPI Transmit/Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Handle the interrupts.
-      (+) Handle the command sequence.
-      (+) Transmit data in blocking, interrupt or DMA mode.
-      (+) Receive data in blocking, interrupt or DMA mode.
-      (+) Manage the auto-polling functional mode.
-      (+) Manage the memory-mapped functional mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Handle QSPI interrupt request.
-  * @param hqspi QSPI handle
-  * @retval None
-  */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
-{
-  __IO uint32_t *data_reg;
-  uint32_t flag = READ_REG(hqspi->Instance->SR);
-  uint32_t itsource = READ_REG(hqspi->Instance->CR);
-
-  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
-  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
-  {
-    data_reg = &hqspi->Instance->DR;
-
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
-    {
-      /* Transmission process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
-      {
-        if (hqspi->TxXferCount > 0U)
-        {
-          /* Fill the FIFO until the threshold is reached */
-          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
-          hqspi->pTxBuffPtr++;
-          hqspi->TxXferCount--;
-        }
-        else
-        {
-          /* No more data available for the transfer */
-          /* Disable the QSPI FIFO Threshold Interrupt */
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
-          break;
-        }
-      }
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
-    {
-      /* Receiving Process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
-      {
-        if (hqspi->RxXferCount > 0U)
-        {
-          /* Read the FIFO until the threshold is reached */
-          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
-          hqspi->pRxBuffPtr++;
-          hqspi->RxXferCount--;
-        }
-        else
-        {
-          /* All data have been received for the transfer */
-          /* Disable the QSPI FIFO Threshold Interrupt */
-          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
-          break;
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    /* FIFO Threshold callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-    hqspi->FifoThresholdCallback(hqspi);
-#else
-    HAL_QSPI_FifoThresholdCallback(hqspi);
-#endif
-  }
-
-  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
-  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
-  {
-    /* Clear interrupt */
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
-
-    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
-    /* Transfer complete callback */
-    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
-    {
-      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
-      {
-        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-        /* Disable the DMA channel */
-        __HAL_DMA_DISABLE(hqspi->hdma);
-      }
-
-#if  defined(QSPI1_V1_0)
-      /* Clear Busy bit */
-      HAL_QSPI_Abort_IT(hqspi);
-#endif
-
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-
-      /* TX Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-      hqspi->TxCpltCallback(hqspi);
-#else
-      HAL_QSPI_TxCpltCallback(hqspi);
-#endif
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
-    {
-      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
-      {
-        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-        /* Disable the DMA channel */
-        __HAL_DMA_DISABLE(hqspi->hdma);
-      }
-      else
-      {
-        data_reg = &hqspi->Instance->DR;
-        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
-        {
-          if (hqspi->RxXferCount > 0U)
-          {
-            /* Read the last data received in the FIFO until it is empty */
-            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
-            hqspi->pRxBuffPtr++;
-            hqspi->RxXferCount--;
-          }
-          else
-          {
-            /* All data have been received for the transfer */
-            break;
-          }
-        }
-      }
-
-#if  defined(QSPI1_V1_0)
-      /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-      HAL_QSPI_Abort_IT(hqspi);
-#endif
-
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-
-      /* RX Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-      hqspi->RxCpltCallback(hqspi);
-#else
-      HAL_QSPI_RxCpltCallback(hqspi);
-#endif
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
-    {
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-
-      /* Command Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-      hqspi->CmdCpltCallback(hqspi);
-#else
-      HAL_QSPI_CmdCpltCallback(hqspi);
-#endif
-    }
-    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
-    {
-      /* Reset functional mode configuration to indirect write mode by default */
-      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
-
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-
-      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
-      {
-        /* Abort called by the user */
-
-        /* Abort Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-        hqspi->AbortCpltCallback(hqspi);
-#else
-        HAL_QSPI_AbortCpltCallback(hqspi);
-#endif
-      }
-      else
-      {
-        /* Abort due to an error (eg :  DMA error) */
-
-        /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-        hqspi->ErrorCallback(hqspi);
-#else
-        HAL_QSPI_ErrorCallback(hqspi);
-#endif
-      }
-    }
-    else
-    {
-     /* Nothing to do */
-    }
-  }
-
-  /* QSPI Status Match interrupt occurred ------------------------------------*/
-  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
-  {
-    /* Clear interrupt */
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
-
-    /* Check if the automatic poll mode stop is activated */
-    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
-    {
-      /* Disable the QSPI Transfer Error and Status Match Interrupts */
-      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-    }
-
-    /* Status match callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-    hqspi->StatusMatchCallback(hqspi);
-#else
-    HAL_QSPI_StatusMatchCallback(hqspi);
-#endif
-  }
-
-  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
-  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
-  {
-    /* Clear interrupt */
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
-
-    /* Disable all the QSPI Interrupts */
-    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
-    /* Set error code */
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
-    {
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-      /* Disable the DMA channel */
-      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
-      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
-      {
-        /* Set error code to DMA */
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
-        /* Change state of QSPI */
-        hqspi->State = HAL_QSPI_STATE_READY;
-
-        /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-        hqspi->ErrorCallback(hqspi);
-#else
-        HAL_QSPI_ErrorCallback(hqspi);
-#endif
-      }
-    }
-    else
-    {
-      /* Change state of QSPI */
-      hqspi->State = HAL_QSPI_STATE_READY;
-
-      /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-      hqspi->ErrorCallback(hqspi);
-#else
-      HAL_QSPI_ErrorCallback(hqspi);
-#endif
-    }
-  }
-
-  /* QSPI Timeout interrupt occurred -----------------------------------------*/
-  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
-  {
-    /* Clear interrupt */
-    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
-
-    /* Timeout callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-    hqspi->TimeOutCallback(hqspi);
-#else
-    HAL_QSPI_TimeOutCallback(hqspi);
-#endif
-  }
-
-   else
-  {
-   /* Nothing to do */
-  }
-}
-
-/**
-  * @brief Set the command configuration.
-  * @param hqspi QSPI handle
-  * @param cmd : structure that contains the command configuration information
-  * @param Timeout Timeout duration
-  * @note   This function is used only in Indirect Read or Write Modes
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Update QSPI state */
-    hqspi->State = HAL_QSPI_STATE_BUSY;
-
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
-    if (status == HAL_OK)
-    {
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-      if (cmd->DataMode == QSPI_DATA_NONE)
-      {
-        /* When there is no data phase, the transfer start as soon as the configuration is done
-        so wait until TC flag is set to go back in idle state */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
-        if (status == HAL_OK)
-        {
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-          /* Update QSPI state */
-          hqspi->State = HAL_QSPI_STATE_READY;
-        }
-      }
-      else
-      {
-        /* Update QSPI state */
-        hqspi->State = HAL_QSPI_STATE_READY;
-      }
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief Set the command configuration in interrupt mode.
-  * @param hqspi QSPI handle
-  * @param cmd structure that contains the command configuration information
-  * @note   This function is used only in Indirect Read or Write Modes
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Update QSPI state */
-    hqspi->State = HAL_QSPI_STATE_BUSY;
-
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
-
-    if (status == HAL_OK)
-    {
-      if (cmd->DataMode == QSPI_DATA_NONE)
-      {
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-      }
-
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-      if (cmd->DataMode == QSPI_DATA_NONE)
-      {
-        /* When there is no data phase, the transfer start as soon as the configuration is done
-        so activate TC and TE interrupts */
-        /* Process unlocked */
-        __HAL_UNLOCK(hqspi);
-
-        /* Enable the QSPI Transfer Error Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
-      }
-      else
-      {
-        /* Update QSPI state */
-        hqspi->State = HAL_QSPI_STATE_READY;
-
-        /* Process unlocked */
-        __HAL_UNLOCK(hqspi);
-      }
-    }
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief Transmit an amount of data in blocking mode.
-  * @param hqspi QSPI handle
-  * @param pData pointer to data buffer
-  * @param Timeout Timeout duration
-  * @note   This function is used only in Indirect Write Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tickstart = HAL_GetTick();
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->pTxBuffPtr = pData;
-
-      /* Configure QSPI: CCR register with functional as indirect write */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-      while(hqspi->TxXferCount > 0U)
-      {
-        /* Wait until FT flag is set to send data */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
-
-        if (status != HAL_OK)
-        {
-          break;
-        }
-
-        *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
-        hqspi->pTxBuffPtr++;
-        hqspi->TxXferCount--;
-      }
-
-      if (status == HAL_OK)
-      {
-        /* Wait until TC flag is set to go back in idle state */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
-        if (status == HAL_OK)
-        {
-          /* Clear Transfer Complete bit */
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-#if  defined(QSPI1_V1_0)
-          /* Clear Busy bit */
-          status = HAL_QSPI_Abort(hqspi);
-#endif
-        }
-      }
-
-      /* Update QSPI state */
-      hqspi->State = HAL_QSPI_STATE_READY;
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @param hqspi QSPI handle
-  * @param pData pointer to data buffer
-  * @param Timeout Timeout duration
-  * @note   This function is used only in Indirect Read Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-  __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-      while(hqspi->RxXferCount > 0U)
-      {
-        /* Wait until FT or TC flag is set to read received data */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
-
-        if  (status != HAL_OK)
-        {
-          break;
-        }
-
-        *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
-        hqspi->pRxBuffPtr++;
-        hqspi->RxXferCount--;
-      }
-
-      if (status == HAL_OK)
-      {
-        /* Wait until TC flag is set to go back in idle state */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
-        if  (status == HAL_OK)
-        {
-          /* Clear Transfer Complete bit */
-          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-#if  defined(QSPI1_V1_0)
-          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-          status = HAL_QSPI_Abort(hqspi);
-#endif
-        }
-      }
-
-      /* Update QSPI state */
-      hqspi->State = HAL_QSPI_STATE_READY;
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  return status;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi QSPI handle
-  * @param  pData pointer to data buffer
-  * @note   This function is used only in Indirect Write Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->pTxBuffPtr = pData;
-
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
-      /* Configure QSPI: CCR register with functional as indirect write */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi QSPI handle
-  * @param  pData pointer to data buffer
-  * @note   This function is used only in Indirect Read Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-
-      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode with DMA.
-  * @param  hqspi QSPI handle
-  * @param  pData pointer to data buffer
-  * @note   This function is used only in Indirect Write Mode
-  * @note   If DMA peripheral access is configured as halfword, the number
-  *         of data and the fifo threshold should be aligned on halfword
-  * @note   If DMA peripheral access is configured as word, the number
-  *         of data and the fifo threshold should be aligned on word
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    /* Clear the error code */
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Configure counters of the handle */
-      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
-      {
-        hqspi->TxXferCount = data_size;
-      }
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
-      {
-        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
-        {
-          /* The number of data or the fifo threshold is not aligned on halfword
-          => no transfer possible with DMA peripheral access configured as halfword */
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-          status = HAL_ERROR;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-        else
-        {
-          hqspi->TxXferCount = (data_size >> 1U);
-        }
-      }
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
-      {
-        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
-        {
-          /* The number of data or the fifo threshold is not aligned on word
-          => no transfer possible with DMA peripheral access configured as word */
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-          status = HAL_ERROR;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-        else
-        {
-          hqspi->TxXferCount = (data_size >> 2U);
-        }
-      }
-      else
-      {
-        /* Nothing to do */
-      }
-
-      if (status == HAL_OK)
-      {
-        /* Update state */
-        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
-        /* Configure size and pointer of the handle */
-        hqspi->TxXferSize = hqspi->TxXferCount;
-        hqspi->pTxBuffPtr = pData;
-
-        /* Configure QSPI: CCR register with functional mode as indirect write */
-        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
-        /* Set the QSPI DMA transfer complete callback */
-        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
-
-        /* Set the QSPI DMA Half transfer complete callback */
-        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
-
-        /* Set the DMA error callback */
-        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
-        /* Clear the DMA abort callback */
-        hqspi->hdma->XferAbortCallback = NULL;
-
-        /* Configure the direction of the DMA */
-        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
-        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
-        /* Enable the QSPI transmit DMA Channel */
-        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
-        {
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-
-          /* Enable the QSPI transfer error Interrupt */
-          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
-          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
-          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-        }
-        else
-        {
-          status = HAL_ERROR;
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-          hqspi->State = HAL_QSPI_STATE_READY;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-     }
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hqspi QSPI handle
-  * @param  pData pointer to data buffer.
-  * @note   This function is used only in Indirect Read Mode
-  * @note   If DMA peripheral access is configured as halfword, the number
-  *         of data and the fifo threshold should be aligned on halfword
-  * @note   If DMA peripheral access is configured as word, the number
-  *         of data and the fifo threshold should be aligned on word
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    /* Clear the error code */
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    if(pData != NULL )
-    {
-      /* Configure counters of the handle */
-      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
-      {
-        hqspi->RxXferCount = data_size;
-      }
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
-      {
-        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
-        {
-          /* The number of data or the fifo threshold is not aligned on halfword
-             => no transfer possible with DMA peripheral access configured as halfword */
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-          status = HAL_ERROR;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-        else
-        {
-          hqspi->RxXferCount = (data_size >> 1U);
-        }
-      }
-      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
-      {
-        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
-        {
-          /* The number of data or the fifo threshold is not aligned on word
-             => no transfer possible with DMA peripheral access configured as word */
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-          status = HAL_ERROR;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-        else
-        {
-          hqspi->RxXferCount = (data_size >> 2U);
-        }
-      }
-      else
-      {
-        /* Nothing to do */
-      }
-
-      if (status == HAL_OK)
-      {
-        /* Update state */
-        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
-        /* Configure size and pointer of the handle */
-        hqspi->RxXferSize = hqspi->RxXferCount;
-        hqspi->pRxBuffPtr = pData;
-
-        /* Set the QSPI DMA transfer complete callback */
-        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
-
-        /* Set the QSPI DMA Half transfer complete callback */
-        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
-
-        /* Set the DMA error callback */
-        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
-
-        /* Clear the DMA abort callback */
-        hqspi->hdma->XferAbortCallback = NULL;
-
-        /* Configure the direction of the DMA */
-        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
-        /* Enable the DMA Channel */
-        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
-        {
-          /* Configure QSPI: CCR register with functional as indirect read */
-          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-          /* Start the transfer by re-writing the address in AR register */
-          WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-
-          /* Enable the QSPI transfer error Interrupt */
-          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
-          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
-          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-        }
-        else
-        {
-          status = HAL_ERROR;
-          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-          hqspi->State = HAL_QSPI_STATE_READY;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hqspi);
-        }
-      }
-    }
-    else
-    {
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-      status = HAL_ERROR;
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
-  * @param  hqspi QSPI handle
-  * @param  cmd structure that contains the command configuration information.
-  * @param  cfg structure that contains the polling configuration information.
-  * @param  Timeout Timeout duration
-  * @note   This function is used only in Automatic Polling Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: PSMAR register with the status match value */
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
-      /* Configure QSPI: PSMKR register with the status mask value */
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
-      /* Configure QSPI: PIR register with the interval value */
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
-      /* Configure QSPI: CR register with Match mode and Automatic stop enabled
-      (otherwise there will be an infinite loop in blocking mode) */
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
-               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
-      /* Call the configuration function */
-      cmd->NbData = cfg->StatusBytesSize;
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
-      /* Wait until SM flag is set to go back in idle state */
-      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
-
-      if (status == HAL_OK)
-      {
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
-        /* Update state */
-        hqspi->State = HAL_QSPI_STATE_READY;
-      }
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
-  * @param  hqspi QSPI handle
-  * @param  cmd structure that contains the command configuration information.
-  * @param  cfg structure that contains the polling configuration information.
-  * @note   This function is used only in Automatic Polling Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
-  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
-  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
-
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: PSMAR register with the status match value */
-      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
-      /* Configure QSPI: PSMKR register with the status mask value */
-      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
-      /* Configure QSPI: PIR register with the interval value */
-      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
-      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
-      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
-               (cfg->MatchMode | cfg->AutomaticStop));
-
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
-      /* Call the configuration function */
-      cmd->NbData = cfg->StatusBytesSize;
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-
-      /* Enable the QSPI Transfer Error and status match Interrupt */
-      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
-    }
-    else
-    {
-      /* Process unlocked */
-      __HAL_UNLOCK(hqspi);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Configure the Memory Mapped mode.
-  * @param  hqspi QSPI handle
-  * @param  cmd structure that contains the command configuration information.
-  * @param  cfg structure that contains the memory mapped configuration information.
-  * @note   This function is used only in Memory mapped Mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
-{
-  HAL_StatusTypeDef status;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
-  }
-
-  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
-  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-  {
-    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
-  }
-
-  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
-  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-  {
-    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
-  }
-
-  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
-  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
-  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
-  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
-  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
-  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-
-    /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
-    if (status == HAL_OK)
-    {
-      /* Configure QSPI: CR register with timeout counter enable */
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
-
-    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
-      {
-        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-
-        /* Configure QSPI: LPTR register with the low-power timeout value */
-        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
-
-        /* Enable the QSPI TimeOut Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
-      }
-
-      /* Call the configuration function */
-      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
-    }
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Transfer Error callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Abort completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Command completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  FIFO Threshold callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Status Match callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timeout callback.
-  * @param  hqspi QSPI handle
-  * @retval None
-  */
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hqspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_QSPI_TimeOutCallback could be implemented in the user file
-   */
-}
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User QSPI Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hqspi QSPI handle
-  * @param CallbackId ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
-  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
-  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
-  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
-  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
-  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
-  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
-  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
-  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
-  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
-  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
-  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
-  * @param pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(pCallback == NULL)
-  {
-    /* Update the error code */
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    switch (CallbackId)
-    {
-    case  HAL_QSPI_ERROR_CB_ID :
-      hqspi->ErrorCallback = pCallback;
-      break;
-    case HAL_QSPI_ABORT_CB_ID :
-      hqspi->AbortCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
-      hqspi->FifoThresholdCallback = pCallback;
-      break;
-    case HAL_QSPI_CMD_CPLT_CB_ID :
-      hqspi->CmdCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_RX_CPLT_CB_ID :
-      hqspi->RxCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_TX_CPLT_CB_ID :
-      hqspi->TxCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
-      hqspi->RxHalfCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
-      hqspi->TxHalfCpltCallback = pCallback;
-      break;
-    case HAL_QSPI_STATUS_MATCH_CB_ID :
-      hqspi->StatusMatchCallback = pCallback;
-      break;
-    case HAL_QSPI_TIMEOUT_CB_ID :
-      hqspi->TimeOutCallback = pCallback;
-      break;
-    case HAL_QSPI_MSP_INIT_CB_ID :
-      hqspi->MspInitCallback = pCallback;
-      break;
-    case HAL_QSPI_MSP_DEINIT_CB_ID :
-      hqspi->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hqspi->State == HAL_QSPI_STATE_RESET)
-  {
-    switch (CallbackId)
-    {
-    case HAL_QSPI_MSP_INIT_CB_ID :
-      hqspi->MspInitCallback = pCallback;
-      break;
-    case HAL_QSPI_MSP_DEINIT_CB_ID :
-      hqspi->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User QSPI Callback
-  *         QSPI Callback is redirected to the weak (surcharged) predefined callback
-  * @param hqspi QSPI handle
-  * @param CallbackId ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
-  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
-  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
-  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
-  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
-  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
-  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
-  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
-  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
-  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
-  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
-  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    switch (CallbackId)
-    {
-    case  HAL_QSPI_ERROR_CB_ID :
-      hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
-      break;
-    case HAL_QSPI_ABORT_CB_ID :
-      hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
-      break;
-    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
-      hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
-      break;
-    case HAL_QSPI_CMD_CPLT_CB_ID :
-      hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
-      break;
-    case HAL_QSPI_RX_CPLT_CB_ID :
-      hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
-      break;
-    case HAL_QSPI_TX_CPLT_CB_ID :
-      hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
-      break;
-    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
-      hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
-      break;
-    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
-      hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
-      break;
-    case HAL_QSPI_STATUS_MATCH_CB_ID :
-      hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
-      break;
-    case HAL_QSPI_TIMEOUT_CB_ID :
-      hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
-      break;
-    case HAL_QSPI_MSP_INIT_CB_ID :
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;
-      break;
-    case HAL_QSPI_MSP_DEINIT_CB_ID :
-      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hqspi->State == HAL_QSPI_STATE_RESET)
-  {
-    switch (CallbackId)
-    {
-    case HAL_QSPI_MSP_INIT_CB_ID :
-      hqspi->MspInitCallback = HAL_QSPI_MspInit;
-      break;
-    case HAL_QSPI_MSP_DEINIT_CB_ID :
-      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hqspi);
-  return status;
-}
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
-  *  @brief   QSPI control and State functions
-  *
-@verbatim
- ===============================================================================
-                  ##### Peripheral Control and State functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to :
-      (+) Check in run-time the state of the driver.
-      (+) Check the error code set during last operation.
-      (+) Abort any operation.
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the QSPI handle state.
-  * @param  hqspi QSPI handle
-  * @retval HAL state
-  */
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
-{
-  /* Return QSPI handle state */
-  return hqspi->State;
-}
-
-/**
-* @brief  Return the QSPI error code.
-* @param  hqspi QSPI handle
-* @retval QSPI Error Code
-*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
-{
-  return hqspi->ErrorCode;
-}
-
-/**
-* @brief  Abort the current transmission.
-* @param  hqspi QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check if the state is in one of the busy states */
-  if (((uint32_t)hqspi->State & 0x2U) != 0U)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
-    {
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-      /* Abort DMA channel */
-      status = HAL_DMA_Abort(hqspi->hdma);
-      if(status != HAL_OK)
-      {
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-      }
-    }
-
-    if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
-    {
-      /* Configure QSPI: CR register with Abort request */
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-      
-      /* Wait until TC flag is set to go back in idle state */
-      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
-      
-      if (status == HAL_OK)
-      {
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-        
-        /* Wait until BUSY flag is reset */
-        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-      }
-
-      if (status == HAL_OK)
-      {
-        /* Reset functional mode configuration to indirect write mode by default */
-        CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
-        
-        /* Update state */
-        hqspi->State = HAL_QSPI_STATE_READY;
-      }
-    }
-    else
-    {
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_READY;
-    }
-  }
-
-  return status;
-}
-
-/**
-* @brief  Abort the current transmission (non-blocking function)
-* @param  hqspi QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check if the state is in one of the busy states */
-  if (((uint32_t)hqspi->State & 0x2U) != 0U)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hqspi);
-
-    /* Update QSPI state */
-    hqspi->State = HAL_QSPI_STATE_ABORT;
-
-    /* Disable all interrupts */
-    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
-
-    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
-    {
-      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-      /* Abort DMA channel */
-      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
-      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
-      {
-        /* Change state of QSPI */
-        hqspi->State = HAL_QSPI_STATE_READY;
-
-        /* Abort Complete callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-        hqspi->AbortCpltCallback(hqspi);
-#else
-        HAL_QSPI_AbortCpltCallback(hqspi);
-#endif
-      }
-    }
-    else
-    {
-      if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
-      {
-        /* Clear interrupt */
-        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-        
-        /* Enable the QSPI Transfer Complete Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-        
-        /* Configure QSPI: CR register with Abort request */
-        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-      }    
-      else
-      {
-        /* Change state of QSPI */
-        hqspi->State = HAL_QSPI_STATE_READY;
-      }
-    }
-  }
-  return status;
-}
-
-/** @brief Set QSPI timeout.
-  * @param  hqspi QSPI handle.
-  * @param  Timeout Timeout for the QSPI memory access.
-  * @retval None
-  */
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
-{
-  hqspi->Timeout = Timeout;
-}
-
-/** @brief Set QSPI Fifo threshold.
-  * @param  hqspi QSPI handle.
-  * @param  Threshold Threshold of the Fifo (value between 1 and 16).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    /* Synchronize init structure with new FIFO threshold value */
-    hqspi->Init.FifoThreshold = Threshold;
-
-    /* Configure QSPI FIFO Threshold */
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
-               ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/** @brief Get QSPI Fifo threshold.
-  * @param  hqspi QSPI handle.
-  * @retval Fifo threshold (value between 1 and 16)
-  */
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
-{
-  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
-}
-
-/** @brief  Set FlashID.
-  * @param  hqspi QSPI handle.
-  * @param  FlashID Index of the flash memory to be accessed.
-  *                   This parameter can be a value of @ref QSPI_Flash_Select.
-  * @note   The FlashID is ignored when dual flash mode is enabled.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameter */
-  assert_param(IS_QSPI_FLASH_ID(FlashID));
-
-  /* Process locked */
-  __HAL_LOCK(hqspi);
-
-  if(hqspi->State == HAL_QSPI_STATE_READY)
-  {
-    /* Synchronize init structure with new FlashID value */
-    hqspi->Init.FlashID = FlashID;
-
-    /* Configure QSPI FlashID */
-    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
-  }
-  else
-  {
-    status = HAL_BUSY;
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Private_Functions QSPI Private Functions
-  * @{
-  */
-
-/**
-  * @brief  DMA QSPI receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-  hqspi->RxXferCount = 0U;
-
-  /* Enable the QSPI transfer complete Interrupt */
-  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
-  * @brief  DMA QSPI transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-  hqspi->TxXferCount = 0U;
-
-  /* Enable the QSPI transfer complete Interrupt */
-  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
-  * @brief  DMA QSPI receive process half complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-  hqspi->RxHalfCpltCallback(hqspi);
-#else
-  HAL_QSPI_RxHalfCpltCallback(hqspi);
-#endif
-}
-
-/**
-  * @brief  DMA QSPI transmit process half complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
-
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-  hqspi->TxHalfCpltCallback(hqspi);
-#else
-  HAL_QSPI_TxHalfCpltCallback(hqspi);
-#endif
-}
-
-/**
-  * @brief  DMA QSPI communication error callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
-
-  /* if DMA error is FIFO error ignore it */
-  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
-  {
-  hqspi->RxXferCount = 0U;
-  hqspi->TxXferCount = 0U;
-  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
-
-  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-  /* Abort the QSPI */
-  (void)HAL_QSPI_Abort_IT(hqspi);
-
-  }
-}
-
-/**
-  * @brief  DMA QSPI abort complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
-{
-  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
-
-  hqspi->RxXferCount = 0U;
-  hqspi->TxXferCount = 0U;
-
-  if(hqspi->State == HAL_QSPI_STATE_ABORT)
-  {
-    /* DMA Abort called by QSPI abort */
-    /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-    /* Enable the QSPI Transfer Complete Interrupt */
-    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
-    /* Configure QSPI: CR register with Abort request */
-    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-  }
-  else
-  {
-    /* DMA Abort called due to a transfer error interrupt */
-    /* Change state of QSPI */
-    hqspi->State = HAL_QSPI_STATE_READY;
-
-    /* Error callback */
-#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
-    hqspi->ErrorCallback(hqspi);
-#else
-    HAL_QSPI_ErrorCallback(hqspi);
-#endif
-  }
-}
-
-/**
-  * @brief  Wait for a flag state until timeout.
-  * @param  hqspi QSPI handle
-  * @param  Flag Flag checked
-  * @param  State Value of the flag expected
-  * @param  Tickstart Tick start value
-  * @param  Timeout Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
-                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is in expected state */
-  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hqspi->State     = HAL_QSPI_STATE_ERROR;
-        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Wait for a flag state until timeout using CPU cycle.
-  * @param  hqspi : QSPI handle
-  * @param  Flag : Flag checked
-  * @param  State : Value of the flag expected
-  * @param  Timeout : Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
-{ 
-  __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U);
-   do
-   {
-     if (count-- == 0U)
-     {
-       hqspi->State     = HAL_QSPI_STATE_ERROR;
-       hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-       return HAL_TIMEOUT;
-     }
-   }
-   while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
-   
-   return HAL_OK;   
-}
-
-/**
-  * @brief  Configure the communication registers.
-  * @param  hqspi QSPI handle
-  * @param  cmd structure that contains the command configuration information
-  * @param  FunctionalMode functional mode to configured
-  *           This parameter can be one of the following values:
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
-  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
-  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
-  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
-  * @retval None
-  */
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
-{
-  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
-
-  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
-  {
-    /* Configure QSPI: DLR register with the number of data to read or write */
-    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
-  }
-
-  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
-  {
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-    {
-      /* Configure QSPI: ABR register with alternate bytes value */
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with instruction, address and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
-                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
-                                         cmd->Instruction | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with instruction and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
-                                         cmd->AddressMode | cmd->InstructionMode |
-                                         cmd->Instruction | FunctionalMode));
-      }
-    }
-    else
-    {
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with instruction and address ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only instruction ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateByteMode | cmd->AddressMode |
-                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-      }
-    }
-  }
-  else
-  {
-    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
-    {
-      /* Configure QSPI: ABR register with alternate bytes value */
-      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with address and alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
-                                         cmd->AddressSize | cmd->AddressMode |
-                                         cmd->InstructionMode | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only alternate bytes ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-      }
-    }
-    else
-    {
-      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
-      {
-        /*---- Command with only address ----*/
-        /* Configure QSPI: CCR register with all communications parameters */
-        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                         cmd->AlternateByteMode | cmd->AddressSize |
-                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-
-        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
-        {
-          /* Configure QSPI: AR register with address value */
-          WRITE_REG(hqspi->Instance->AR, cmd->Address);
-        }
-      }
-      else
-      {
-        /*---- Command with only data phase ----*/
-        if (cmd->DataMode != QSPI_DATA_NONE)
-        {
-          /* Configure QSPI: CCR register with all communications parameters */
-          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                           cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
-                                           cmd->AlternateByteMode | cmd->AddressMode |
-                                           cmd->InstructionMode | FunctionalMode));
-        }
-      }
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_QSPI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(QUADSPI) */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_qspi.c
+  * @author  MCD Application Team
+  * @brief   QSPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the QuadSPI interface (QSPI).
+  *           + Initialization and de-initialization functions
+  *           + Indirect functional mode management
+  *           + Memory-mapped functional mode management
+  *           + Auto-polling functional mode management
+  *           + Interrupts and flags management
+  *           + DMA channel configuration for indirect functional mode
+  *           + Errors management and abort functionality
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    *** Initialization ***
+    ======================
+    [..]
+      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure QuadSPI global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+    *** Indirect functional mode ***
+    ================================
+    [..]
+      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+          functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used and if present the number of bytes.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+      (#) If no data is required for the command, it is sent directly to the memory :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+          HAL_QSPI_Transmit_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+          HAL_QSPI_Receive_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+    *** Auto-polling functional mode ***
+    ====================================
+    [..]
+      (#) Configure the command sequence and the auto-polling functional mode using the
+          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+             the polling interval and the automatic stop activation.
+      (#) After the configuration :
+         (++) In polling mode, the output of the function is done when the status match is reached. The
+             automatic stop is activated to avoid an infinite loop.
+         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+    *** Memory-mapped functional mode ***
+    =====================================
+    [..]
+      (#) Configure the command sequence and the memory-mapped functional mode using the
+          HAL_QSPI_MemoryMapped() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and the size.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The timeout activation and the timeout period.
+      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+    *** Errors management and abort functionality ***
+    =================================================
+    [..]
+      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
+      (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
+          flushes the fifo :
+         (++) In polling mode, the output of the function is done when the transfer
+              complete bit is set and the busy bit cleared.
+         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
+              the transfer complete bit is set.
+
+    *** Control functions ***
+    =========================
+    [..]
+      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
+      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
+      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) ErrorCallback : callback when error occurs.
+        (+) AbortCpltCallback : callback when abort is completed.
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+        (+) CmdCpltCallback : callback when a command without data is completed.
+        (+) RxCpltCallback : callback when a reception transfer is completed.
+        (+) TxCpltCallback : callback when a transmission transfer is completed.
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+        (+) StatusMatchCallback : callback when a status match occurs.
+        (+) TimeOutCallback : callback when the timeout perioed expires.
+        (+) MspInitCallback    : QSPI MspInit.
+        (+) MspDeInitCallback  : QSPI MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) ErrorCallback : callback when error occurs.
+        (+) AbortCpltCallback : callback when abort is completed.
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+        (+) CmdCpltCallback : callback when a command without data is completed.
+        (+) RxCpltCallback : callback when a reception transfer is completed.
+        (+) TxCpltCallback : callback when a transmission transfer is completed.
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+        (+) StatusMatchCallback : callback when a status match occurs.
+        (+) TimeOutCallback : callback when the timeout perioed expires.
+        (+) MspInitCallback    : QSPI MspInit.
+        (+) MspDeInitCallback  : QSPI MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
+      and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
+      or HAL_QSPI_Init function.
+
+      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
+    *** Workarounds linked to Silicon Limitation ***
+    ====================================================
+    [..]
+      (#) Workarounds Implemented inside HAL Driver
+         (++) Extra data written in the FIFO at the end of a read transfer
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+#if defined(QUADSPI)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup QSPI QSPI
+  * @brief QSPI HAL module driver
+  * @{
+  */
+#ifdef HAL_QSPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
+  * @{
+  */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+  * @{
+  */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+  * @{
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Initialize the QuadSPI.
+      (+) De-initialize the QuadSPI.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the QSPI mode according to the specified parameters
+  *        in the QSPI_InitTypeDef and initialize the associated handle.
+  * @param hqspi QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+  {
+    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+  }
+
+  if(hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hqspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
+    hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
+    hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
+    hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+    hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
+    hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
+    hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
+    hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;
+    hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;
+    hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
+    hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
+
+    if(hqspi->MspInitCallback == NULL)
+    {
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hqspi->MspInitCallback(hqspi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_QSPI_MspInit(hqspi);
+#endif
+
+    /* Configure the default timeout for the QSPI memory access */
+    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
+  }
+
+  /* Configure QSPI FIFO Threshold */
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+
+  /* Wait till BUSY flag reset */
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+  if(status == HAL_OK)
+  {
+    /* Configure QSPI Clock Prescaler and Sample Shift */
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
+               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
+                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+
+    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
+                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+    /* Enable the QSPI peripheral */
+    __HAL_QSPI_ENABLE(hqspi);
+
+    /* Set QSPI error code to none */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Initialize the QSPI state */
+    hqspi->State = HAL_QSPI_STATE_READY;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief De-Initialize the QSPI peripheral.
+  * @param hqspi QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the QSPI Peripheral Clock */
+  __HAL_QSPI_DISABLE(hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  if(hqspi->MspDeInitCallback == NULL)
+  {
+    hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hqspi->MspDeInitCallback(hqspi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_QSPI_MspDeInit(hqspi);
+#endif
+
+  /* Set QSPI error code to none */
+  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+  /* Initialize the QSPI state */
+  hqspi->State = HAL_QSPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the QSPI MSP.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the QSPI MSP.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief QSPI Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Handle the interrupts.
+      (+) Handle the command sequence.
+      (+) Transmit data in blocking, interrupt or DMA mode.
+      (+) Receive data in blocking, interrupt or DMA mode.
+      (+) Manage the auto-polling functional mode.
+      (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle QSPI interrupt request.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+  __IO uint32_t *data_reg;
+  uint32_t flag = READ_REG(hqspi->Instance->SR);
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);
+
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
+  {
+    data_reg = &hqspi->Instance->DR;
+
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      /* Transmission process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+      {
+        if (hqspi->TxXferCount > 0U)
+        {
+          /* Fill the FIFO until the threshold is reached */
+          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+          hqspi->pTxBuffPtr++;
+          hqspi->TxXferCount--;
+        }
+        else
+        {
+          /* No more data available for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      /* Receiving Process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+      {
+        if (hqspi->RxXferCount > 0U)
+        {
+          /* Read the FIFO until the threshold is reached */
+          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+          hqspi->pRxBuffPtr++;
+          hqspi->RxXferCount--;
+        }
+        else
+        {
+          /* All data have been received for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* FIFO Threshold callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->FifoThresholdCallback(hqspi);
+#else
+    HAL_QSPI_FifoThresholdCallback(hqspi);
+#endif
+  }
+
+  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
+
+    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+    /* Transfer complete callback */
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+
+#if  defined(QSPI1_V1_0)
+      /* Clear Busy bit */
+      HAL_QSPI_Abort_IT(hqspi);
+#endif
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* TX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->TxCpltCallback(hqspi);
+#else
+      HAL_QSPI_TxCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+      else
+      {
+        data_reg = &hqspi->Instance->DR;
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+        {
+          if (hqspi->RxXferCount > 0U)
+          {
+            /* Read the last data received in the FIFO until it is empty */
+            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+            hqspi->pRxBuffPtr++;
+            hqspi->RxXferCount--;
+          }
+          else
+          {
+            /* All data have been received for the transfer */
+            break;
+          }
+        }
+      }
+
+#if  defined(QSPI1_V1_0)
+      /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+      HAL_QSPI_Abort_IT(hqspi);
+#endif
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* RX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->RxCpltCallback(hqspi);
+#else
+      HAL_QSPI_RxCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* Command Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->CmdCpltCallback(hqspi);
+#else
+      HAL_QSPI_CmdCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+    {
+      /* Reset functional mode configuration to indirect write mode by default */
+      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+      {
+        /* Abort called by the user */
+
+        /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->AbortCpltCallback(hqspi);
+#else
+        HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+      }
+      else
+      {
+        /* Abort due to an error (eg :  DMA error) */
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+     /* Nothing to do */
+    }
+  }
+
+  /* QSPI Status Match interrupt occurred ------------------------------------*/
+  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
+
+    /* Check if the automatic poll mode stop is activated */
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
+    {
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+
+    /* Status match callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->StatusMatchCallback(hqspi);
+#else
+    HAL_QSPI_StatusMatchCallback(hqspi);
+#endif
+  }
+
+  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
+
+    /* Disable all the QSPI Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+    /* Set error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Disable the DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->ErrorCallback(hqspi);
+#else
+      HAL_QSPI_ErrorCallback(hqspi);
+#endif
+    }
+  }
+
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/
+  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
+
+    /* Timeout callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->TimeOutCallback(hqspi);
+#else
+    HAL_QSPI_TimeOutCallback(hqspi);
+#endif
+  }
+
+   else
+  {
+   /* Nothing to do */
+  }
+}
+
+/**
+  * @brief Set the command configuration.
+  * @param hqspi QSPI handle
+  * @param cmd : structure that contains the command configuration information
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done
+        so wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+          /* Update QSPI state */
+          hqspi->State = HAL_QSPI_STATE_READY;
+        }
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Set the command configuration in interrupt mode.
+  * @param hqspi QSPI handle
+  * @param cmd structure that contains the command configuration information
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
+
+    if (status == HAL_OK)
+    {
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+      }
+
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done
+        so activate TC and TE interrupts */
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+
+        /* Enable the QSPI Transfer Error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+      }
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Transmit an amount of data in blocking mode.
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pTxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      while(hqspi->TxXferCount > 0U)
+      {
+        /* Wait until FT flag is set to send data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
+        {
+          break;
+        }
+
+        *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+        hqspi->pTxBuffPtr++;
+        hqspi->TxXferCount--;
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+#if  defined(QSPI1_V1_0)
+          /* Clear Busy bit */
+          status = HAL_QSPI_Abort(hqspi);
+#endif
+        }
+      }
+
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+      while(hqspi->RxXferCount > 0U)
+      {
+        /* Wait until FT or TC flag is set to read received data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
+
+        if  (status != HAL_OK)
+        {
+          break;
+        }
+
+        *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+        hqspi->pRxBuffPtr++;
+        hqspi->RxXferCount--;
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if  (status == HAL_OK)
+        {
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+#if  defined(QSPI1_V1_0)
+          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+          status = HAL_QSPI_Abort(hqspi);
+#endif
+        }
+      }
+
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pTxBuffPtr = pData;
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with DMA.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->TxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 1U);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+          => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 2U);
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+        /* Configure size and pointer of the handle */
+        hqspi->TxXferSize = hqspi->TxXferCount;
+        hqspi->pTxBuffPtr = pData;
+
+        /* Configure QSPI: CCR register with functional mode as indirect write */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hqspi->hdma->XferAbortCallback = NULL;
+
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+        /* Enable the QSPI transmit DMA Channel */
+        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
+        {
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+
+          /* Enable the QSPI transfer error Interrupt */
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+          hqspi->State = HAL_QSPI_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+     }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer.
+  * @note   This function is used only in Indirect Read Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->RxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+             => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 1U);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+             => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 2U);
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+        /* Configure size and pointer of the handle */
+        hqspi->RxXferSize = hqspi->RxXferCount;
+        hqspi->pRxBuffPtr = pData;
+
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hqspi->hdma->XferAbortCallback = NULL;
+
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+        /* Enable the DMA Channel */
+        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
+        {
+          /* Configure QSPI: CCR register with functional as indirect read */
+          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+          /* Start the transfer by re-writing the address in AR register */
+          WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+
+          /* Enable the QSPI transfer error Interrupt */
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+          hqspi->State = HAL_QSPI_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+      }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
+  * @param  Timeout Timeout duration
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+      (otherwise there will be an infinite loop in blocking mode) */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Wait until SM flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
+
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+               (cfg->MatchMode | cfg->AutomaticStop));
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI Transfer Error and status match Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the Memory Mapped mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the memory mapped configuration information.
+  * @note   This function is used only in Memory mapped Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: CR register with timeout counter enable */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+
+    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+      {
+        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+        /* Configure QSPI: LPTR register with the low-power timeout value */
+        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+        /* Enable the QSPI TimeOut Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+      }
+
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Transfer Error callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Abort completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Command completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FIFO Threshold callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Status Match callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_TimeOutCallback could be implemented in the user file
+   */
+}
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User QSPI Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case  HAL_QSPI_ERROR_CB_ID :
+      hqspi->ErrorCallback = pCallback;
+      break;
+    case HAL_QSPI_ABORT_CB_ID :
+      hqspi->AbortCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+      hqspi->FifoThresholdCallback = pCallback;
+      break;
+    case HAL_QSPI_CMD_CPLT_CB_ID :
+      hqspi->CmdCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_RX_CPLT_CB_ID :
+      hqspi->RxCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_TX_CPLT_CB_ID :
+      hqspi->TxCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+      hqspi->RxHalfCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+      hqspi->TxHalfCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_STATUS_MATCH_CB_ID :
+      hqspi->StatusMatchCallback = pCallback;
+      break;
+    case HAL_QSPI_TIMEOUT_CB_ID :
+      hqspi->TimeOutCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User QSPI Callback
+  *         QSPI Callback is redirected to the weak (surcharged) predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case  HAL_QSPI_ERROR_CB_ID :
+      hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+      break;
+    case HAL_QSPI_ABORT_CB_ID :
+      hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+      break;
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+      hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+      break;
+    case HAL_QSPI_CMD_CPLT_CB_ID :
+      hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+      break;
+    case HAL_QSPI_RX_CPLT_CB_ID :
+      hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+      break;
+    case HAL_QSPI_TX_CPLT_CB_ID :
+      hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+      break;
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+      hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+      break;
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+      hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+      break;
+    case HAL_QSPI_STATUS_MATCH_CB_ID :
+      hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+      break;
+    case HAL_QSPI_TIMEOUT_CB_ID :
+      hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+      break;
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+  return status;
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+  *  @brief   QSPI control and State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral Control and State functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Check in run-time the state of the driver.
+      (+) Check the error code set during last operation.
+      (+) Abort any operation.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the QSPI handle state.
+  * @param  hqspi QSPI handle
+  * @retval HAL state
+  */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+  /* Return QSPI handle state */
+  return hqspi->State;
+}
+
+/**
+* @brief  Return the QSPI error code.
+* @param  hqspi QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+  return hqspi->ErrorCode;
+}
+
+/**
+* @brief  Abort the current transmission.
+* @param  hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check if the state is in one of the busy states */
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Abort DMA channel */
+      status = HAL_DMA_Abort(hqspi->hdma);
+      if(status != HAL_OK)
+      {
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+      }
+    }
+
+    if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+    {
+      /* Configure QSPI: CR register with Abort request */
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      
+      /* Wait until TC flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+      
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Wait until BUSY flag is reset */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Reset functional mode configuration to indirect write mode by default */
+        CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+    else
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+* @brief  Abort the current transmission (non-blocking function)
+* @param  hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check if the state is in one of the busy states */
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_ABORT;
+
+    /* Disable all interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Abort DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+      {
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->AbortCpltCallback(hqspi);
+#else
+        HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+      if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Enable the QSPI Transfer Complete Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+        
+        /* Configure QSPI: CR register with Abort request */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      }    
+      else
+      {
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  return status;
+}
+
+/** @brief Set QSPI timeout.
+  * @param  hqspi QSPI handle.
+  * @param  Timeout Timeout for the QSPI memory access.
+  * @retval None
+  */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+  hqspi->Timeout = Timeout;
+}
+
+/** @brief Set QSPI Fifo threshold.
+  * @param  hqspi QSPI handle.
+  * @param  Threshold Threshold of the Fifo (value between 1 and 16).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FIFO threshold value */
+    hqspi->Init.FifoThreshold = Threshold;
+
+    /* Configure QSPI FIFO Threshold */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+               ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/** @brief Get QSPI Fifo threshold.
+  * @param  hqspi QSPI handle.
+  * @retval Fifo threshold (value between 1 and 16)
+  */
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+{
+  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/** @brief  Set FlashID.
+  * @param  hqspi QSPI handle.
+  * @param  FlashID Index of the flash memory to be accessed.
+  *                   This parameter can be a value of @ref QSPI_Flash_Select.
+  * @note   The FlashID is ignored when dual flash mode is enabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameter */
+  assert_param(IS_QSPI_FLASH_ID(FlashID));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FlashID value */
+    hqspi->Init.FlashID = FlashID;
+
+    /* Configure QSPI FlashID */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA QSPI receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+  hqspi->RxXferCount = 0U;
+
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+  hqspi->TxXferCount = 0U;
+
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI receive process half complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  hqspi->RxHalfCpltCallback(hqspi);
+#else
+  HAL_QSPI_RxHalfCpltCallback(hqspi);
+#endif
+}
+
+/**
+  * @brief  DMA QSPI transmit process half complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  hqspi->TxHalfCpltCallback(hqspi);
+#else
+  HAL_QSPI_TxHalfCpltCallback(hqspi);
+#endif
+}
+
+/**
+  * @brief  DMA QSPI communication error callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+  hqspi->RxXferCount = 0U;
+  hqspi->TxXferCount = 0U;
+  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
+
+  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+  /* Abort the QSPI */
+  (void)HAL_QSPI_Abort_IT(hqspi);
+
+  }
+}
+
+/**
+  * @brief  DMA QSPI abort complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
+  hqspi->RxXferCount = 0U;
+  hqspi->TxXferCount = 0U;
+
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)
+  {
+    /* DMA Abort called by QSPI abort */
+    /* Clear interrupt */
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+    /* Enable the QSPI Transfer Complete Interrupt */
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+  }
+  else
+  {
+    /* DMA Abort called due to a transfer error interrupt */
+    /* Change state of QSPI */
+    hqspi->State = HAL_QSPI_STATE_READY;
+
+    /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->ErrorCallback(hqspi);
+#else
+    HAL_QSPI_ErrorCallback(hqspi);
+#endif
+  }
+}
+
+/**
+  * @brief  Wait for a flag state until timeout.
+  * @param  hqspi QSPI handle
+  * @param  Flag Flag checked
+  * @param  State Value of the flag expected
+  * @param  Tickstart Tick start value
+  * @param  Timeout Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is in expected state */
+  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a flag state until timeout using CPU cycle.
+  * @param  hqspi : QSPI handle
+  * @param  Flag : Flag checked
+  * @param  State : Value of the flag expected
+  * @param  Timeout : Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+{ 
+  __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U);
+   do
+   {
+     if (count-- == 0U)
+     {
+       hqspi->State     = HAL_QSPI_STATE_ERROR;
+       hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+       return HAL_TIMEOUT;
+     }
+   }
+   while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
+   
+   return HAL_OK;   
+}
+
+/**
+  * @brief  Configure the communication registers.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information
+  * @param  FunctionalMode functional mode to configured
+  *           This parameter can be one of the following values:
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+  * @retval None
+  */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+  {
+    /* Configure QSPI: DLR register with the number of data to read or write */
+    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
+  }
+
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction, address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+                                         cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with instruction and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressMode | cmd->InstructionMode |
+                                         cmd->Instruction | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction and address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only instruction ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressMode |
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+      }
+    }
+  }
+  else
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressSize | cmd->AddressMode |
+                                         cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with only address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressSize |
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only data phase ----*/
+        if (cmd->DataMode != QSPI_DATA_NONE)
+        {
+          /* Configure QSPI: CCR register with all communications parameters */
+          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                           cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                           cmd->AlternateByteMode | cmd->AddressMode |
+                                           cmd->InstructionMode | FunctionalMode));
+        }
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(QUADSPI) */
diff --git a/project/LWIP/Target/lwipopts.h b/project/LWIP/Target/lwipopts.h
index dcfbe10..00f792d 100644
--- a/project/LWIP/Target/lwipopts.h
+++ b/project/LWIP/Target/lwipopts.h
@@ -47,12 +47,20 @@
 
 /* LwIP Stack Parameters (modified compared to initialization value in opt.h) -*/
 /* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
+/*----- Default Value for LWIP_IGMP: 0 ---*/
+#define LWIP_IGMP 1
+/*----- Default Value for LWIP_DNS: 0 ---*/
+#define LWIP_DNS 1
 /*----- Value in opt.h for NO_SYS: 0 -----*/
 #define NO_SYS 1
 /*----- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -----*/
 #define SYS_LIGHTWEIGHT_PROT 0
+/*----- Default Value for MEMP_MEM_MALLOC: 0 ---*/
+#define MEMP_MEM_MALLOC 1
 /*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/
 #define MEM_ALIGNMENT 4
+/*----- Value in opt.h for MEMP_NUM_SYS_TIMEOUT: (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) -*/
+#define MEMP_NUM_SYS_TIMEOUT 5
 /*----- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
 #define LWIP_ETHERNET 1
 /*----- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
@@ -75,10 +83,16 @@
 #define RECV_BUFSIZE_DEFAULT 2000000000
 /*----- Default Value for LWIP_HTTPD: 0 ---*/
 #define LWIP_HTTPD 1
+/*----- Default Value for LWIP_HTTPD_CGI: 0 ---*/
+#define LWIP_HTTPD_CGI 1
+/*----- Default Value for LWIP_HTTPD_CGI_SSI: 0 ---*/
+#define LWIP_HTTPD_CGI_SSI 1
 /*----- Default Value for LWIP_HTTPD_SSI: 0 ---*/
 #define LWIP_HTTPD_SSI 1
 /*----- Default Value for LWIP_HTTPD_SSI_RAW: 0 ---*/
 #define LWIP_HTTPD_SSI_RAW 1
+/*----- Default Value for LWIP_HTTPD_SUPPORT_POST: 0 ---*/
+#define LWIP_HTTPD_SUPPORT_POST 1
 /*----- Default Value for LWIP_HTTPD_CUSTOM_FILES: 0 ---*/
 #define LWIP_HTTPD_CUSTOM_FILES 1
 /*----- Value in opt.h for HTTPD_USE_CUSTOM_FSDATA: 0 -----*/
diff --git a/project/project.ioc b/project/project.ioc
index ccb9d73..55aeadd 100644
--- a/project/project.ioc
+++ b/project/project.ioc
@@ -33,14 +33,19 @@ LTDC.WindowX1_L1=480
 LTDC.WindowY1_L0=272
 LTDC.WindowY1_L1=272
 LWIP.BSP.number=1
-LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,LWIP_HTTPD,LWIP_HTTPD_CUSTOM_FILES,LWIP_HTTPD_CGI_SSI,LWIP_HTTPD_SSI,LWIP_HTTPD_SSI_RAW
+LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,LWIP_HTTPD,LWIP_HTTPD_CUSTOM_FILES,LWIP_HTTPD_CGI_SSI,LWIP_HTTPD_SSI,LWIP_HTTPD_SSI_RAW,LWIP_DNS,MEMP_MEM_MALLOC,LWIP_IGMP,LWIP_HTTPD_CGI,LWIP_HTTPD_SUPPORT_POST
 LWIP.IP_ADDRESS=192.168.069.010
 LWIP.LWIP_DHCP=0
+LWIP.LWIP_DNS=1
 LWIP.LWIP_HTTPD=1
-LWIP.LWIP_HTTPD_CGI_SSI=0
+LWIP.LWIP_HTTPD_CGI=1
+LWIP.LWIP_HTTPD_CGI_SSI=1
 LWIP.LWIP_HTTPD_CUSTOM_FILES=1
 LWIP.LWIP_HTTPD_SSI=1
 LWIP.LWIP_HTTPD_SSI_RAW=1
+LWIP.LWIP_HTTPD_SUPPORT_POST=1
+LWIP.LWIP_IGMP=1
+LWIP.MEMP_MEM_MALLOC=1
 LWIP.NETMASK_ADDRESS=255.255.255.000
 LWIP.Version=v2.1.2_Cube
 LWIP0.BSP.STBoard=false
@@ -390,7 +395,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=STM32CubeIDE
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_LTDC_Init-LTDC-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_DMA2D_Init-DMA2D-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_LWIP_Init-LWIP-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_LTDC_Init-LTDC-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_DMA2D_Init-DMA2D-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_LWIP_Init-LWIP-false-HAL-false,8-MX_QUADSPI_Init-QUADSPI-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_6_CYCLE
 QUADSPI.ClockPrescaler=1
 QUADSPI.FifoThreshold=4
@@ -542,3 +547,4 @@ VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 board=STM32F746G-DISCO
 boardIOC=true
+isbadioc=false

From 71571c4e166c6040ea8c4b8e995ca30c79defa7e Mon Sep 17 00:00:00 2001
From: Sani7 <sander.speetjens@gmail.com>
Date: Mon, 6 Nov 2023 13:49:48 +0100
Subject: [PATCH 2/6] Add line endings to logger

---
 project/Core/Inc/log.h | 12 ++++++------
 project/Core/Src/log.c |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/project/Core/Inc/log.h b/project/Core/Inc/log.h
index df8e87f..c89597b 100644
--- a/project/Core/Inc/log.h
+++ b/project/Core/Inc/log.h
@@ -1,7 +1,7 @@
 /**
  * @file log.h
  * @brief Logger header
- * @author Lorenz C.
+ * @authors Lorenz C. Speetjens S.
  *
  * This logging library provides a simple logging interface with different verbosity levels.
  * Each tag can have its own log level.
@@ -88,27 +88,27 @@
 #endif
 
 #if LOGGER_LEVEL <= 1
-#define LOG_DEBUG(tag, fmt, ...) printf(LOG_COLOR_D"[Debug]     (%lu) [%s]: " fmt LOG_RESET_COLOR, logger_get_timestamp(), tag, ##__VA_ARGS__)
+#define LOG_DEBUG(tag, fmt, ...) printf(LOG_COLOR_D"[Debug]     (%lu) [%s]: " fmt LOG_RESET_COLOR "\r\n", logger_get_timestamp(), tag, ##__VA_ARGS__)
 #else
 #define LOG_DEBUG(tag, fmt, ...)
 #endif
 #if LOGGER_LEVEL <= 2
-#define LOG_INFO(tag, fmt, ...)  printf(LOG_COLOR_I"[Info]      (%lu) [%s]: " fmt LOG_RESET_COLOR, logger_get_timestamp(), tag, ##__VA_ARGS__)
+#define LOG_INFO(tag, fmt, ...)  printf(LOG_COLOR_I"[Info]      (%lu) [%s]: " fmt LOG_RESET_COLOR "\r\n", logger_get_timestamp(), tag, ##__VA_ARGS__)
 #else
 #define LOG_INFO(tag, fmt, ...)
 #endif
 #if LOGGER_LEVEL <= 3
-#define LOG_WARN(tag, fmt, ...)  printf(LOG_COLOR_W"[Warning]   (%lu) [%s]: " fmt LOG_RESET_COLOR, logger_get_timestamp(), tag, ##__VA_ARGS__)
+#define LOG_WARN(tag, fmt, ...)  printf(LOG_COLOR_W"[Warning]   (%lu) [%s]: " fmt LOG_RESET_COLOR "\r\n", logger_get_timestamp(), tag, ##__VA_ARGS__)
 #else
 #define LOG_WARN(tag, fmt, ...)
 #endif
 #if LOGGER_LEVEL <= 4
-#define LOG_CRIT(tag, fmt, ...)   printf(LOG_COLOR_C"[Critical] (%lu) [%s]: " fmt LOG_RESET_COLOR, logger_get_timestamp(), tag, ##__VA_ARGS__)
+#define LOG_CRIT(tag, fmt, ...)   printf(LOG_COLOR_C"[Critical] (%lu) [%s]: " fmt LOG_RESET_COLOR "\r\n", logger_get_timestamp(), tag, ##__VA_ARGS__)
 #else
 #define LOG_CRIT(tag, fmt, ...)
 #endif
 #if LOGGER_LEVEL <= 4
-#define LOG_FATAL(tag, fmt, ...)   printf(LOG_COLOR_F"[Fatal]   (%lu) [%s]: " fmt LOG_RESET_COLOR, logger_get_timestamp(), tag, ##__VA_ARGS__)
+#define LOG_FATAL(tag, fmt, ...)   printf(LOG_COLOR_F"[Fatal]   (%lu) [%s]: " fmt LOG_RESET_COLOR "\r\n", logger_get_timestamp(), tag, ##__VA_ARGS__)
 #else
 #define LOG_FATAL(tag, fmt, ...)
 #endif
diff --git a/project/Core/Src/log.c b/project/Core/Src/log.c
index 6370454..ab47e12 100644
--- a/project/Core/Src/log.c
+++ b/project/Core/Src/log.c
@@ -1,7 +1,7 @@
 /**
  * @file log.c
  * @brief Logger implementation
- * @author Lorenz C. && Speetjens S.
+ * @authors Lorenz C. && Speetjens S.
  */
 
 #include <stdarg.h>

From cce5fcfd256cea7550bbb3d5477d032154998fc0 Mon Sep 17 00:00:00 2001
From: Sani7 <sander.speetjens@gmail.com>
Date: Mon, 6 Nov 2023 13:50:02 +0100
Subject: [PATCH 3/6] Add idea files

---
 .gitignore                      |  4 ++
 project/CMakeLists.txt          | 73 +++++++++++++++++++++++++++++++++
 project/CMakeLists_template.txt | 72 ++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 project/CMakeLists.txt
 create mode 100644 project/CMakeLists_template.txt

diff --git a/.gitignore b/.gitignore
index 598f984..38defbf 100644
--- a/.gitignore
+++ b/.gitignore
@@ -32,3 +32,7 @@
 *.app
 
 project/Debug/
+
+project/.idea/
+
+project/cmake-build-debug/
diff --git a/project/CMakeLists.txt b/project/CMakeLists.txt
new file mode 100644
index 0000000..8f9a1a1
--- /dev/null
+++ b/project/CMakeLists.txt
@@ -0,0 +1,73 @@
+#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_VERSION 1)
+cmake_minimum_required(VERSION 3.26)
+
+# specify cross-compilers and tools
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+set(CMAKE_ASM_COMPILER  arm-none-eabi-gcc)
+set(CMAKE_AR arm-none-eabi-ar)
+set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
+set(CMAKE_OBJDUMP arm-none-eabi-objdump)
+set(SIZE arm-none-eabi-size)
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+# project settings
+project(project C CXX ASM)
+set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_C_STANDARD 11)
+
+#Uncomment for hardware floating point
+#add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
+#add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+#add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+
+#Uncomment for software floating point
+#add_compile_options(-mfloat-abi=soft)
+
+add_compile_options(-mcpu=cortex-m7 -mthumb -mthumb-interwork)
+add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
+
+# uncomment to mitigate c++17 absolute addresses warnings
+#set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-register")
+
+# Enable assembler files preprocessing
+add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-x$<SEMICOLON>assembler-with-cpp>)
+
+if ("${CMAKE_BUILD_TYPE}" STREQUAL "Release")
+    message(STATUS "Maximum optimization for speed")
+    add_compile_options(-Ofast)
+elseif ("${CMAKE_BUILD_TYPE}" STREQUAL "RelWithDebInfo")
+    message(STATUS "Maximum optimization for speed, debug info included")
+    add_compile_options(-Ofast -g)
+elseif ("${CMAKE_BUILD_TYPE}" STREQUAL "MinSizeRel")
+    message(STATUS "Maximum optimization for size")
+    add_compile_options(-Os)
+else ()
+    message(STATUS "Minimal optimization, debug info included")
+    add_compile_options(-Og -g)
+endif ()
+
+include_directories(LWIP/App LWIP/Target Core/Inc Middlewares/Third_Party/LwIP/src/include Middlewares/Third_Party/LwIP/system Drivers/STM32F7xx_HAL_Driver/Inc Drivers/STM32F7xx_HAL_Driver/Inc/Legacy Drivers/BSP/Components/lan8742 Middlewares/Third_Party/LwIP/src/include/netif/ppp Middlewares/Third_Party/LwIP/src/apps/http Drivers/CMSIS/Device/ST/STM32F7xx/Include Middlewares/Third_Party/LwIP/src/include/lwip Middlewares/Third_Party/LwIP/src/include/lwip/apps Middlewares/Third_Party/LwIP/src/include/lwip/priv Middlewares/Third_Party/LwIP/src/include/lwip/prot Middlewares/Third_Party/LwIP/src/include/netif Middlewares/Third_Party/LwIP/src/include/compat/posix Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa Middlewares/Third_Party/LwIP/src/include/compat/posix/net Middlewares/Third_Party/LwIP/src/include/compat/posix/sys Middlewares/Third_Party/LwIP/src/include/compat/stdc Middlewares/Third_Party/LwIP/system/arch Drivers/CMSIS/Include)
+
+add_definitions(-DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx)
+
+file(GLOB_RECURSE SOURCES "Core/*.*" "LWIP/*.*" "Middlewares/*.*" "Drivers/*.*")
+
+set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32F746NGHX_FLASH.ld)
+
+add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
+add_link_options(-mcpu=cortex-m7 -mthumb -mthumb-interwork)
+add_link_options(-T ${LINKER_SCRIPT})
+
+add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
+
+set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
+set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
+
+add_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD
+        COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}
+        COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}
+        COMMENT "Building ${HEX_FILE}
+Building ${BIN_FILE}")
diff --git a/project/CMakeLists_template.txt b/project/CMakeLists_template.txt
new file mode 100644
index 0000000..3b7fc44
--- /dev/null
+++ b/project/CMakeLists_template.txt
@@ -0,0 +1,72 @@
+#${templateWarning}
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_VERSION 1)
+${cmakeRequiredVersion}
+# specify cross-compilers and tools
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+set(CMAKE_ASM_COMPILER  arm-none-eabi-gcc)
+set(CMAKE_AR arm-none-eabi-ar)
+set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
+set(CMAKE_OBJDUMP arm-none-eabi-objdump)
+set(SIZE arm-none-eabi-size)
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+# project settings
+project(${projectName} C CXX ASM)
+set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_C_STANDARD 11)
+
+#Uncomment for hardware floating point
+#add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
+#add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+#add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+
+#Uncomment for software floating point
+#add_compile_options(-mfloat-abi=soft)
+
+add_compile_options(-mcpu=${mcpu} -mthumb -mthumb-interwork)
+add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
+
+# uncomment to mitigate c++17 absolute addresses warnings
+#set(CMAKE_CXX_FLAGS "$${CMAKE_CXX_FLAGS} -Wno-register")
+
+# Enable assembler files preprocessing
+add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-x$<SEMICOLON>assembler-with-cpp>)
+
+if ("$${CMAKE_BUILD_TYPE}" STREQUAL "Release")
+    message(STATUS "Maximum optimization for speed")
+    add_compile_options(-Ofast)
+elseif ("$${CMAKE_BUILD_TYPE}" STREQUAL "RelWithDebInfo")
+    message(STATUS "Maximum optimization for speed, debug info included")
+    add_compile_options(-Ofast -g)
+elseif ("$${CMAKE_BUILD_TYPE}" STREQUAL "MinSizeRel")
+    message(STATUS "Maximum optimization for size")
+    add_compile_options(-Os)
+else ()
+    message(STATUS "Minimal optimization, debug info included")
+    add_compile_options(-Og -g)
+endif ()
+
+include_directories(${includes})
+
+add_definitions(${defines})
+
+file(GLOB_RECURSE SOURCES ${sources})
+
+set(LINKER_SCRIPT $${CMAKE_SOURCE_DIR}/${linkerScript})
+
+add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=$${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.map)
+add_link_options(-mcpu=${mcpu} -mthumb -mthumb-interwork)
+add_link_options(-T $${LINKER_SCRIPT})
+
+add_executable($${PROJECT_NAME}.elf $${SOURCES} $${LINKER_SCRIPT})
+
+set(HEX_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.hex)
+set(BIN_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.bin)
+
+add_custom_command(TARGET $${PROJECT_NAME}.elf POST_BUILD
+        COMMAND $${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:$${PROJECT_NAME}.elf> $${HEX_FILE}
+        COMMAND $${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:$${PROJECT_NAME}.elf> $${BIN_FILE}
+        COMMENT "Building $${HEX_FILE}
+Building $${BIN_FILE}")

From b4b54463ef3e5b566d17ee8b71200948c8039bde Mon Sep 17 00:00:00 2001
From: L-diy <ldiy@users.noreply.github.com>
Date: Mon, 6 Nov 2023 15:06:52 +0100
Subject: [PATCH 4/6] Remove the Core/inc folder from the CMake file list

Removed the Core/inc folder from the CMake source file list, otherwise fs_data.c will be compiled and give an error during linking.
---
 project/CMakeLists.txt          | 4 +++-
 project/CMakeLists_template.txt | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/project/CMakeLists.txt b/project/CMakeLists.txt
index 8f9a1a1..06d823d 100644
--- a/project/CMakeLists.txt
+++ b/project/CMakeLists.txt
@@ -53,7 +53,9 @@ include_directories(LWIP/App LWIP/Target Core/Inc Middlewares/Third_Party/LwIP/s
 
 add_definitions(-DDEBUG -DUSE_HAL_DRIVER -DSTM32F746xx)
 
-file(GLOB_RECURSE SOURCES "Core/*.*" "LWIP/*.*" "Middlewares/*.*" "Drivers/*.*")
+#file(GLOB_RECURSE SOURCES "Core/*.*" "LWIP/*.*" "Middlewares/*.*" "Drivers/*.*")
+file(GLOB_RECURSE SOURCES "Core/Src/*.*" "Core/Startup/*.*" "LWIP/*.*" "Middlewares/*.*" "Drivers/*.*")
+
 
 set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32F746NGHX_FLASH.ld)
 
diff --git a/project/CMakeLists_template.txt b/project/CMakeLists_template.txt
index 3b7fc44..f02e32b 100644
--- a/project/CMakeLists_template.txt
+++ b/project/CMakeLists_template.txt
@@ -52,7 +52,9 @@ include_directories(${includes})
 
 add_definitions(${defines})
 
-file(GLOB_RECURSE SOURCES ${sources})
+#file(GLOB_RECURSE SOURCES ${sources})
+file(GLOB_RECURSE SOURCES "Core/Src/*.*" "Core/Startup/*.*" "LWIP/*.*" "Middlewares/*.*" "Drivers/*.*")
+
 
 set(LINKER_SCRIPT $${CMAKE_SOURCE_DIR}/${linkerScript})
 

From 4653d6988c92b7778dd4d71364f9df970592adf0 Mon Sep 17 00:00:00 2001
From: Sani7 <sander.speetjens@gmail.com>
Date: Mon, 6 Nov 2023 15:52:14 +0100
Subject: [PATCH 5/6] MX_LWIP_Process()

---
 project/Core/Src/main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/project/Core/Src/main.c b/project/Core/Src/main.c
index 898334c..691c4fe 100644
--- a/project/Core/Src/main.c
+++ b/project/Core/Src/main.c
@@ -118,6 +118,7 @@ int main(void)
     /* USER CODE END WHILE */
 
     /* USER CODE BEGIN 3 */
+	  MX_LWIP_Process();
   }
   /* USER CODE END 3 */
 }

From c3b771469e93cd66bf290c3be6721b6f5240effe Mon Sep 17 00:00:00 2001
From: Sani7 <sander.speetjens@gmail.com>
Date: Mon, 6 Nov 2023 16:07:52 +0100
Subject: [PATCH 6/6] Fix lwip not initialising properly

---
 project/LWIP/Target/lwipopts.h | 2 ++
 project/project.ioc            | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/project/LWIP/Target/lwipopts.h b/project/LWIP/Target/lwipopts.h
index 00f792d..0571ede 100644
--- a/project/LWIP/Target/lwipopts.h
+++ b/project/LWIP/Target/lwipopts.h
@@ -55,6 +55,8 @@
 #define NO_SYS 1
 /*----- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -----*/
 #define SYS_LIGHTWEIGHT_PROT 0
+/*----- Default Value for MEM_LIBC_MALLOC: 0 ---*/
+#define MEM_LIBC_MALLOC 1
 /*----- Default Value for MEMP_MEM_MALLOC: 0 ---*/
 #define MEMP_MEM_MALLOC 1
 /*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/
diff --git a/project/project.ioc b/project/project.ioc
index 55aeadd..4875fcc 100644
--- a/project/project.ioc
+++ b/project/project.ioc
@@ -33,7 +33,7 @@ LTDC.WindowX1_L1=480
 LTDC.WindowY1_L0=272
 LTDC.WindowY1_L1=272
 LWIP.BSP.number=1
-LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,LWIP_HTTPD,LWIP_HTTPD_CUSTOM_FILES,LWIP_HTTPD_CGI_SSI,LWIP_HTTPD_SSI,LWIP_HTTPD_SSI_RAW,LWIP_DNS,MEMP_MEM_MALLOC,LWIP_IGMP,LWIP_HTTPD_CGI,LWIP_HTTPD_SUPPORT_POST
+LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,LWIP_HTTPD,LWIP_HTTPD_CUSTOM_FILES,LWIP_HTTPD_CGI_SSI,LWIP_HTTPD_SSI,LWIP_HTTPD_SSI_RAW,LWIP_DNS,MEMP_MEM_MALLOC,LWIP_IGMP,LWIP_HTTPD_CGI,LWIP_HTTPD_SUPPORT_POST,MEM_LIBC_MALLOC
 LWIP.IP_ADDRESS=192.168.069.010
 LWIP.LWIP_DHCP=0
 LWIP.LWIP_DNS=1
@@ -46,6 +46,7 @@ LWIP.LWIP_HTTPD_SSI_RAW=1
 LWIP.LWIP_HTTPD_SUPPORT_POST=1
 LWIP.LWIP_IGMP=1
 LWIP.MEMP_MEM_MALLOC=1
+LWIP.MEM_LIBC_MALLOC=1
 LWIP.NETMASK_ADDRESS=255.255.255.000
 LWIP.Version=v2.1.2_Cube
 LWIP0.BSP.STBoard=false